Attachment 44137 Details for Bug 34056 – Poll the FIFO for free entries before writing the register

[patch] Poll the FIFO for free entries before writing the register

0001-drm-i915-Do-not-overflow-the-MMADDR-write-FIFO.patch (text/plain), 4.32 KB, created by Chris Wilson on 2011-03-04 11:34:25 UTC

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Creator: Chris Wilson

Created: 2011-03-04 11:34:25 UTC

Size: 4.32 KB

patch

obsolete

>From 2ef32f57e0b96264f8272d82fc559e837cdd0f80 Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Fri, 4 Mar 2011 19:22:40 +0000
>Subject: [PATCH] drm/i915: Do not overflow the MMADDR write FIFO
>
>Whilst the GT is powered down (rc6), writes to MMADDR are placed in a
>FIFO by the System Agent. This is a limited resource, only 64 entries of
>which 20 are reserved for Display and PCH writes, and so we must take
>care not to queue up too many writes. To avoid this, there is counter of
>which we can poll to ensure there are sufficient free entries in the
>fifo.
>
>"Issuing a write to a full FIFO is not supported; at worst it could
>result in corruption or a system hang."
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34056
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>---
> drivers/gpu/drm/i915/i915_drv.h         |   15 ++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h         |    2 ++
> drivers/gpu/drm/i915/intel_ringbuffer.h |   13 +++++++------
> 3 files changed, 23 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 57e7b3c..8872a13 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1356,7 +1356,7 @@ __i915_write(64, q)
>  */
> void __gen6_force_wake_get(struct drm_i915_private *dev_priv);
> void __gen6_force_wake_put (struct drm_i915_private *dev_priv);
>-static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
>+static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg)
> {
> 	u32 val;
> 
>@@ -1370,6 +1370,19 @@ static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
> 	return val;
> }
> 
>+static inline void i915_gt_write(struct drm_i915_private *dev_priv,
>+				u32 reg, u32 val)
>+{
>+	if (dev_priv->info->gen >= 6) {
>+		u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
>+		while (fifo < 20) {
>+			udelay(10);
>+			fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
>+		}
>+	}
>+	I915_WRITE(reg, val);
>+}
>+
> static inline void
> i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
> {
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 729d423..3e6f486 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -3261,6 +3261,8 @@
> #define  FORCEWAKE				0xA18C
> #define  FORCEWAKE_ACK				0x130090
> 
>+#define  GT_FIFO_FREE_ENTRIES			0x120008
>+
> #define GEN6_RPNSWREQ				0xA008
> #define   GEN6_TURBO_DISABLE			(1<<31)
> #define   GEN6_FREQUENCY(x)			((x)<<25)
>diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
>index 6d6fde8..3430686 100644
>--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
>+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
>@@ -14,22 +14,23 @@ struct  intel_hw_status_page {
> 	struct		drm_i915_gem_object *obj;
> };
> 
>-#define I915_RING_READ(reg) i915_safe_read(dev_priv, reg)
>+#define I915_RING_READ(reg) i915_gt_read(dev_priv, reg)
>+#define I915_RING_WRITE(reg, val) i915_gt_write(dev_priv, reg, val)
> 
> #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
>-#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
>+#define I915_WRITE_TAIL(ring, val) I915_RING_WRITE(RING_TAIL((ring)->mmio_base), val)
> 
> #define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
>-#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
>+#define I915_WRITE_START(ring, val) I915_RING_WRITE(RING_START((ring)->mmio_base), val)
> 
> #define I915_READ_HEAD(ring)  I915_RING_READ(RING_HEAD((ring)->mmio_base))
>-#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
>+#define I915_WRITE_HEAD(ring, val) I915_RING_WRITE(RING_HEAD((ring)->mmio_base), val)
> 
> #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
>-#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
>+#define I915_WRITE_CTL(ring, val) I915_RING_WRITE(RING_CTL((ring)->mmio_base), val)
> 
>-#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
> #define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
>+#define I915_WRITE_IMR(ring, val) I915_RING_WRITE(RING_IMR((ring)->mmio_base), val)
> 
> #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
> #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
>-- 
>1.7.2.3
>

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Attachments on bug 34056: 43142 | 43143 | 43144 | 43861 | 44102 | 44106 | 44137

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