Attachment 44140 Details for Bug 33921 – Poll the FIFO for free entries before writing the register

[patch] Poll the FIFO for free entries before writing the register

0001-drm-i915-Do-not-overflow-the-MMADDR-write-FIFO.patch (text/plain), 8.21 KB, created by Chris Wilson on 2011-03-04 13:36:09 UTC

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Creator: Chris Wilson

Created: 2011-03-04 13:36:09 UTC

Size: 8.21 KB

patch

obsolete

>From 8c68e00af6f356c6466cc8f0778c9f75970edb6e Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Fri, 4 Mar 2011 19:22:40 +0000
>Subject: [PATCH] drm/i915: Do not overflow the MMADDR write FIFO
>
>Whilst the GT is powered down (rc6), writes to MMADDR are placed in a
>FIFO by the System Agent. This is a limited resource, only 64 entries, of
>which 20 are reserved for Display and PCH writes, and so we must take
>care not to queue up too many writes. To avoid this, there is counter
>which we can poll to ensure there are sufficient free entries in the
>fifo.
>
>"Issuing a write to a full FIFO is not supported; at worst it could
>result in corruption or a system hang."
>
>Reported-and-Tested-by: Matt Turner <mattst88@gmail.com>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34056
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>---
> drivers/gpu/drm/i915/i915_debugfs.c     |    4 ++--
> drivers/gpu/drm/i915/i915_drv.c         |   14 ++++++++++++--
> drivers/gpu/drm/i915/i915_drv.h         |   20 +++++++++++++++-----
> drivers/gpu/drm/i915/i915_reg.h         |    2 ++
> drivers/gpu/drm/i915/intel_display.c    |    8 ++++----
> drivers/gpu/drm/i915/intel_ringbuffer.h |   13 +++++++------
> 6 files changed, 42 insertions(+), 19 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>index 3601466..4ff9b6c 100644
>--- a/drivers/gpu/drm/i915/i915_debugfs.c
>+++ b/drivers/gpu/drm/i915/i915_debugfs.c
>@@ -865,7 +865,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
> 		int max_freq;
> 
> 		/* RPSTAT1 is in the GT power well */
>-		__gen6_force_wake_get(dev_priv);
>+		__gen6_gt_force_wake_get(dev_priv);
> 
> 		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> 		seq_printf(m, "RPSTAT1: 0x%08x\n", I915_READ(GEN6_RPSTAT1));
>@@ -888,7 +888,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
> 		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
> 			   max_freq * 100);
> 
>-		__gen6_force_wake_put(dev_priv);
>+		__gen6_gt_force_wake_put(dev_priv);
> 	} else {
> 		seq_printf(m, "no P-state info available\n");
> 	}
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index 2982f41..22ec066 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -257,7 +257,7 @@ void intel_detect_pch (struct drm_device *dev)
> 	}
> }
> 
>-void __gen6_force_wake_get(struct drm_i915_private *dev_priv)
>+void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
> {
> 	int count;
> 
>@@ -273,12 +273,22 @@ void __gen6_force_wake_get(struct drm_i915_private *dev_priv)
> 		udelay(10);
> }
> 
>-void __gen6_force_wake_put(struct drm_i915_private *dev_priv)
>+void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
> {
> 	I915_WRITE_NOTRACE(FORCEWAKE, 0);
> 	POSTING_READ(FORCEWAKE);
> }
> 
>+void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
>+{
>+	int loop = 500;
>+	u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
>+	while (fifo < 20 && loop--) {
>+		udelay(10);
>+		fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
>+	}
>+}
>+
> static int i915_drm_freeze(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 57e7b3c..d023b9b 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1354,22 +1354,32 @@ __i915_write(64, q)
>  * must be set to prevent GT core from power down and stale values being
>  * returned.
>  */
>-void __gen6_force_wake_get(struct drm_i915_private *dev_priv);
>-void __gen6_force_wake_put (struct drm_i915_private *dev_priv);
>-static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
>+void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
>+void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
>+void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
>+
>+static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg)
> {
> 	u32 val;
> 
> 	if (dev_priv->info->gen >= 6) {
>-		__gen6_force_wake_get(dev_priv);
>+		__gen6_gt_force_wake_get(dev_priv);
> 		val = I915_READ(reg);
>-		__gen6_force_wake_put(dev_priv);
>+		__gen6_gt_force_wake_put(dev_priv);
> 	} else
> 		val = I915_READ(reg);
> 
> 	return val;
> }
> 
>+static inline void i915_gt_write(struct drm_i915_private *dev_priv,
>+				u32 reg, u32 val)
>+{
>+	if (dev_priv->info->gen >= 6)
>+		__gen6_gt_wait_for_fifo(dev_priv);
>+	I915_WRITE(reg, val);
>+}
>+
> static inline void
> i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
> {
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 729d423..3e6f486 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -3261,6 +3261,8 @@
> #define  FORCEWAKE				0xA18C
> #define  FORCEWAKE_ACK				0x130090
> 
>+#define  GT_FIFO_FREE_ENTRIES			0x120008
>+
> #define GEN6_RPNSWREQ				0xA008
> #define   GEN6_TURBO_DISABLE			(1<<31)
> #define   GEN6_FREQUENCY(x)			((x)<<25)
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index e79b25b..49fb54f 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -1219,7 +1219,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
> 	u32 blt_ecoskpd;
> 
> 	/* Make sure blitter notifies FBC of writes */
>-	__gen6_force_wake_get(dev_priv);
>+	__gen6_gt_force_wake_get(dev_priv);
> 	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
> 	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
> 		GEN6_BLITTER_LOCK_SHIFT;
>@@ -1230,7 +1230,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
> 			 GEN6_BLITTER_LOCK_SHIFT);
> 	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
> 	POSTING_READ(GEN6_BLITTER_ECOSKPD);
>-	__gen6_force_wake_put(dev_priv);
>+	__gen6_gt_force_wake_put(dev_priv);
> }
> 
> static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
>@@ -6282,7 +6282,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
> 	 * userspace...
> 	 */
> 	I915_WRITE(GEN6_RC_STATE, 0);
>-	__gen6_force_wake_get(dev_priv);
>+	__gen6_gt_force_wake_get(dev_priv);
> 
> 	/* disable the counters and set deterministic thresholds */
> 	I915_WRITE(GEN6_RC_CONTROL, 0);
>@@ -6380,7 +6380,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
> 	/* enable all PM interrupts */
> 	I915_WRITE(GEN6_PMINTRMSK, 0);
> 
>-	__gen6_force_wake_put(dev_priv);
>+	__gen6_gt_force_wake_put(dev_priv);
> }
> 
> void intel_enable_clock_gating(struct drm_device *dev)
>diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
>index 6d6fde8..3430686 100644
>--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
>+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
>@@ -14,22 +14,23 @@ struct  intel_hw_status_page {
> 	struct		drm_i915_gem_object *obj;
> };
> 
>-#define I915_RING_READ(reg) i915_safe_read(dev_priv, reg)
>+#define I915_RING_READ(reg) i915_gt_read(dev_priv, reg)
>+#define I915_RING_WRITE(reg, val) i915_gt_write(dev_priv, reg, val)
> 
> #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
>-#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
>+#define I915_WRITE_TAIL(ring, val) I915_RING_WRITE(RING_TAIL((ring)->mmio_base), val)
> 
> #define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
>-#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
>+#define I915_WRITE_START(ring, val) I915_RING_WRITE(RING_START((ring)->mmio_base), val)
> 
> #define I915_READ_HEAD(ring)  I915_RING_READ(RING_HEAD((ring)->mmio_base))
>-#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
>+#define I915_WRITE_HEAD(ring, val) I915_RING_WRITE(RING_HEAD((ring)->mmio_base), val)
> 
> #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
>-#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
>+#define I915_WRITE_CTL(ring, val) I915_RING_WRITE(RING_CTL((ring)->mmio_base), val)
> 
>-#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
> #define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
>+#define I915_WRITE_IMR(ring, val) I915_RING_WRITE(RING_IMR((ring)->mmio_base), val)
> 
> #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
> #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
>-- 
>1.7.2.3
>

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