Attachment 44154 Details for Bug 35016 – FOR TESTING ONLY: copious debug tracing to i915_tiling_ok()

[patch] FOR TESTING ONLY: copious debug tracing to i915_tiling_ok()

0001-i915_tiling_ok-debugging.patch (text/plain), 2.63 KB, created by Kamal Mostafa on 2011-03-05 12:31:40 UTC

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Creator: Kamal Mostafa

Created: 2011-03-05 12:31:40 UTC

Size: 2.63 KB

patch

obsolete

>From 242ea77db0f97d4cead05d8cbf35efa651ff561d Mon Sep 17 00:00:00 2001
>From: Kamal Mostafa <kamal@canonical.com>
>Date: Sat, 5 Mar 2011 11:33:30 -0800
>Subject: [PATCH] i915_tiling_ok debugging
>
>---
> drivers/gpu/drm/i915/i915_gem_tiling.c |   32 +++++++++++++++++++++-----------
> 1 files changed, 21 insertions(+), 11 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
>index 79a04fd..a3347c2 100644
>--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
>+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
>@@ -180,15 +180,25 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
> 	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
> }
> 
>+#define DBG_return(retval) { \
>+	printk(KERN_INFO "%s(dev,%d,%d,%d)+line %d " \
>+		"return=%d tile_width=%d tile_height=%d\n", \
>+	      	__func__, stride, size, tiling_mode, __LINE__, \
>+		(retval), tile_width, tile_height \
>+		); \
>+    	return retval; \
>+	}
>+
> /* Check pitch constriants for all chips & tiling formats */
> static bool
> i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
>+#line 1
> {
> 	int tile_width, tile_height;
> 
> 	/* Linear is always fine */
> 	if (tiling_mode == I915_TILING_NONE)
>-		return true;
>+		DBG_return( true );
> 
> 	if (IS_GEN2(dev) ||
> 	    (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
>@@ -201,17 +211,17 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> 		/* i965 stores the end address of the gtt mapping in the fence
> 		 * reg, so dont bother to check the size */
> 		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
>-			return false;
>+			DBG_return( false );
> 	} else {
> 		if (stride > 8192)
>-			return false;
>+			DBG_return( false );
> 
> 		if (IS_GEN3(dev)) {
> 			if (size > I830_FENCE_MAX_SIZE_VAL << 20)
>-				return false;
>+				DBG_return( false );
> 		} else {
> 			if (size > I830_FENCE_MAX_SIZE_VAL << 19)
>-				return false;
>+				DBG_return( false );
> 		}
> 	}
> 
>@@ -227,23 +237,23 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> 
> 	/* Size needs to be aligned to a full tile row */
> 	if (size & (tile_height * stride - 1))
>-		return false;
>+		DBG_return( false );
> 
> 	/* 965+ just needs multiples of tile width */
> 	if (INTEL_INFO(dev)->gen >= 4) {
> 		if (stride & (tile_width - 1))
>-			return false;
>-		return true;
>+			DBG_return( false );
>+		DBG_return( true );
> 	}
> 
> 	/* Pre-965 needs power of two tile widths */
> 	if (stride < tile_width)
>-		return false;
>+		DBG_return( false );
> 
> 	if (stride & (stride - 1))
>-		return false;
>+		DBG_return( false );
> 
>-	return true;
>+	DBG_return( true );
> }
> 
> /* Is the current GTT allocation valid for the change in tiling? */
>-- 
>1.7.1
>

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Attachments on bug 35016: 44123 | 44125 | 44126 | 44127 | 44154 | 44155 | 44156

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