Attachment 44257 Details for Bug 35126 – dmesg with drm.debug=0x06

dmesg with drm.debug=0x06

dmesg_dbg.log (text/plain), 30.10 KB, created by Dillon on 2011-03-08 16:59:45 UTC

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Description:

Filename:

MIME Type:

Creator: Dillon

Created: 2011-03-08 16:59:45 UTC

Size: 30.10 KB

patch

obsolete

>ThunderFox ~ # dmesg
>: 0
>[drm:intel_calculate_wm], FIFO watermark level: 29
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 29
>[drm:i9xx_update_wm], self-refresh entries: 80
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 29, C: 2, SR 47
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:SVIDEO-1] 
>disconnected
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:intel_crtc_idle_timer], idle timer fired, downclocking
>[drm:intel_idle_update], enable memory self refresh on 945
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:intel_mark_busy], disable memory self refresh on 945
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:intel_crtc_cursor_set], 
>[drm:intel_crtc_cursor_set], cursor off
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:drm_mode_addfb], [FB:30]
>[drm:drm_mode_addfb], [FB:34]
>[drm:intel_crtc_cursor_set], 
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:drm_mode_addfb], [FB:30]
>grsec: Segmentation fault occurred at (nil) in /usr/bin/Xorg[X:17988] 
>uid/euid:0/0 gid/egid:0/0, parent /usr/bin/kdm[kdm:17886] uid/euid:0/0 
>gid/egid:0/0
>[drm:intel_crtc_cursor_set], 
>[drm:intel_crtc_cursor_set], cursor off
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:3] [FB:29] #connectors=0 (x y) 
>(0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:4] [FB:29] #connectors=1 (x y) 
>(0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[drm:intel_pipe_set_base_atomic], Writing base 007E0000 00000000 0 0 
>5120
>[drm:intel_update_fbc], 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:4] [FB:29] #connectors=1 (x y) 
>(0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:4] [FB:29] #connectors=1 (x y) 
>(0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>grsec: denied resource overstep by requesting 4096 for RLIMIT_CORE 
>against limit 0 for /usr/bin/Xorg[X:17988] uid/euid:0/0 gid/egid:0/0, 
>parent /usr/bin/kdm[kdm:17886] uid/euid:0/0 gid/egid:0/0
>[drm:intel_gpu_idle_timer], idle timer fired, downclocking
>[drm:intel_idle_update], enable memory self refresh on 945
>[drm:intel_crtc_idle_timer], idle timer fired, downclocking
>[drm:intel_idle_update], enable memory self refresh on 945
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:3] [FB:29] #connectors=0 (x y) 
>(0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:4] [FB:29] #connectors=1 (x y) 
>(0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[drm:i915_driver_open], 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:3] [FB:29] #connectors=0 (x y) 
>(0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:4] [FB:29] #connectors=1 (x y) 
>(0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[drm:i915_driver_open], 
>[drm:i915_getparam], Unknown parameter 11
>[drm:i915_getparam], Unknown parameter 12
>[drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3]
>[drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3]
>[drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] 
>probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1280x800" 60 71250 1280 
>1328 1360 1440 800 802 808 823 0x48 0xa
>[drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[drm:drm_mode_getconnector], [CONNECTOR:11:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:11:VGA-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:11:VGA-1] 
>disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:11:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:11:VGA-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:11:VGA-1] 
>disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:SVIDEO-1]
>[drm:drm_crtc_helper_set_mode], [CRTC:3]
>[drm:intel_crtc_mode_set], Mode for pipe A:
>[drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 
>1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[drm:intel_pipe_set_base], No FB bound
>[drm:intel_update_watermarks], plane A (pipe 1) clock: 71250
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[drm:intel_calculate_wm], FIFO entries required for mode: 23
>[drm:intel_calculate_wm], FIFO watermark level: 3
>[drm:intel_calculate_wm], FIFO entries required for mode: 0
>[drm:intel_calculate_wm], FIFO watermark level: 29
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 29
>[drm:i9xx_update_wm], self-refresh entries: 80
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 29, C: 2, SR 47
>[drm:drm_crtc_helper_set_mode], [ENCODER:14:TV-14] set [MODE:0:NTSC 
>480i]
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:intel_wait_for_vblank], vblank wait timed out
>[drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[drm:intel_update_watermarks], plane A (pipe 1) clock: 71250
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[drm:intel_calculate_wm], FIFO entries required for mode: 23
>[drm:intel_calculate_wm], FIFO watermark level: 3
>[drm:intel_calculate_wm], FIFO entries required for mode: 34
>[drm:intel_calculate_wm], FIFO watermark level: -5
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 1
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 1, C: 2, SR 1
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:intel_tv_detect_type], No TV connection detected
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:intel_update_watermarks], plane A (pipe 1) clock: 71250
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[drm:intel_calculate_wm], FIFO entries required for mode: 23
>[drm:intel_calculate_wm], FIFO watermark level: 3
>[drm:intel_calculate_wm], FIFO entries required for mode: 0
>[drm:intel_calculate_wm], FIFO watermark level: 29
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 29
>[drm:i9xx_update_wm], self-refresh entries: 80
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 29, C: 2, SR 47
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:SVIDEO-1] 
>disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:SVIDEO-1]
>[drm:drm_crtc_helper_set_mode], [CRTC:3]
>[drm:intel_crtc_mode_set], Mode for pipe A:
>[drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 
>1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[drm:intel_pipe_set_base], No FB bound
>[drm:intel_update_watermarks], plane A (pipe 1) clock: 71250
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[drm:intel_calculate_wm], FIFO entries required for mode: 23
>[drm:intel_calculate_wm], FIFO watermark level: 3
>[drm:intel_calculate_wm], FIFO entries required for mode: 0
>[drm:intel_calculate_wm], FIFO watermark level: 29
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 29
>[drm:i9xx_update_wm], self-refresh entries: 80
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 29, C: 2, SR 47
>[drm:drm_crtc_helper_set_mode], [ENCODER:14:TV-14] set [MODE:0:NTSC 
>480i]
>[drm:intel_wait_for_vblank], vblank wait timed out
>[drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[drm:intel_update_watermarks], plane A (pipe 1) clock: 71250
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[drm:intel_calculate_wm], FIFO entries required for mode: 23
>[drm:intel_calculate_wm], FIFO watermark level: 3
>[drm:intel_calculate_wm], FIFO entries required for mode: 34
>[drm:intel_calculate_wm], FIFO watermark level: -5
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 1
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 1, C: 2, SR 1
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:intel_tv_detect_type], No TV connection detected
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:intel_update_watermarks], plane A (pipe 1) clock: 71250
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[drm:intel_calculate_wm], FIFO entries required for mode: 23
>[drm:intel_calculate_wm], FIFO watermark level: 3
>[drm:intel_calculate_wm], FIFO entries required for mode: 0
>[drm:intel_calculate_wm], FIFO watermark level: 29
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 29
>[drm:i9xx_update_wm], self-refresh entries: 80
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 29, C: 2, SR 47
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:SVIDEO-1] 
>disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] 
>probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1280x800" 60 71250 1280 
>1328 1360 1440 800 802 808 823 0x48 0xa
>[drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[drm:drm_mode_getconnector], [CONNECTOR:11:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:11:VGA-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:11:VGA-1] 
>disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:11:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:11:VGA-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:11:VGA-1] 
>disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:SVIDEO-1]
>[drm:drm_crtc_helper_set_mode], [CRTC:3]
>[drm:intel_crtc_mode_set], Mode for pipe A:
>[drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 
>1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[drm:intel_pipe_set_base], No FB bound
>[drm:intel_update_watermarks], plane A (pipe 1) clock: 71250
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[drm:intel_calculate_wm], FIFO entries required for mode: 23
>[drm:intel_calculate_wm], FIFO watermark level: 3
>[drm:intel_calculate_wm], FIFO entries required for mode: 0
>[drm:intel_calculate_wm], FIFO watermark level: 29
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 29
>[drm:i9xx_update_wm], self-refresh entries: 80
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 29, C: 2, SR 47
>[drm:drm_crtc_helper_set_mode], [ENCODER:14:TV-14] set [MODE:0:NTSC 
>480i]
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:intel_wait_for_vblank], vblank wait timed out
>[drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[drm:intel_update_watermarks], plane A (pipe 1) clock: 71250
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[drm:intel_calculate_wm], FIFO entries required for mode: 23
>[drm:intel_calculate_wm], FIFO watermark level: 3
>[drm:intel_calculate_wm], FIFO entries required for mode: 34
>[drm:intel_calculate_wm], FIFO watermark level: -5
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 1
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 1, C: 2, SR 1
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:intel_tv_detect_type], No TV connection detected
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:intel_update_watermarks], plane A (pipe 1) clock: 71250
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[drm:intel_calculate_wm], FIFO entries required for mode: 23
>[drm:intel_calculate_wm], FIFO watermark level: 3
>[drm:intel_calculate_wm], FIFO entries required for mode: 0
>[drm:intel_calculate_wm], FIFO watermark level: 29
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 29
>[drm:i9xx_update_wm], self-refresh entries: 80
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 29, C: 2, SR 47
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:SVIDEO-1] 
>disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:13:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:SVIDEO-1]
>[drm:drm_crtc_helper_set_mode], [CRTC:3]
>[drm:intel_crtc_mode_set], Mode for pipe A:
>[drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 
>1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[drm:intel_pipe_set_base], No FB bound
>[drm:intel_update_watermarks], plane A (pipe 1) clock: 71250
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[drm:intel_calculate_wm], FIFO entries required for mode: 23
>[drm:intel_calculate_wm], FIFO watermark level: 3
>[drm:intel_calculate_wm], FIFO entries required for mode: 0
>[drm:intel_calculate_wm], FIFO watermark level: 29
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 29
>[drm:i9xx_update_wm], self-refresh entries: 80
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 29, C: 2, SR 47
>[drm:drm_crtc_helper_set_mode], [ENCODER:14:TV-14] set [MODE:0:NTSC 
>480i]
>[drm:intel_wait_for_vblank], vblank wait timed out
>[drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[drm:intel_update_watermarks], plane A (pipe 1) clock: 71250
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[drm:intel_calculate_wm], FIFO entries required for mode: 23
>[drm:intel_calculate_wm], FIFO watermark level: 3
>[drm:intel_calculate_wm], FIFO entries required for mode: 34
>[drm:intel_calculate_wm], FIFO watermark level: -5
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 1
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 1, C: 2, SR 1
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:intel_tv_detect_type], No TV connection detected
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:intel_update_watermarks], plane A (pipe 1) clock: 71250
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[drm:intel_calculate_wm], FIFO entries required for mode: 23
>[drm:intel_calculate_wm], FIFO watermark level: 3
>[drm:intel_calculate_wm], FIFO entries required for mode: 0
>[drm:intel_calculate_wm], FIFO watermark level: 29
>[drm:i9xx_update_wm], FIFO watermarks - A: 3, B: 29
>[drm:i9xx_update_wm], self-refresh entries: 80
>[drm:i9xx_update_wm], Setting FIFO watermarks - A: 3, B: 29, C: 2, SR 47
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:13:SVIDEO-1] 
>disconnected
>[drm:i915_getparam], Unknown parameter 12
>[drm:i915_getparam], Unknown parameter 12
>[drm:drm_mode_addfb], [FB:30]
>[drm:intel_mark_busy], disable memory self refresh on 945
>[drm:drm_mode_setcrtc], [CRTC:4]
>[drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:4] [FB:30] #connectors=1 (x y) 
>(0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[drm:i915_driver_irq_handler], pipe a underrun
>[drm:intel_pipe_set_base_atomic], Writing base 01000000 00000000 0 0 
>8192
>[drm:intel_update_fbc], 
>[drm:i915_getparam], Unknown parameter 12
>[drm:i915_getparam], Unknown parameter 11
>[drm:i915_getparam], Unknown parameter 12
>[drm:intel_mark_busy], disable memory self refresh on 945
>[drm:intel_gpu_idle_timer], idle timer fired, downclocking
>[drm:intel_idle_update], enable memory self refresh on 945
>[drm:intel_mark_busy], disable memory self refresh on 945
>[drm:intel_crtc_cursor_set], 
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>[drm:i915_gem_phys_pwrite], obj_addr f3838000, 16384
>

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Attachments on bug 35126: 44252 | 44253 | 44254 | 44255 | 44256 | 44257 | 44305 | 46838

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