Attachment 44458 Details for Bug 34601 – The intel_reg_dumper.log

The intel_reg_dumper.log

intel_reg_dumper.log (text/plain), 10.46 KB, created by meng on 2011-03-14 18:53:26 UTC

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Creator: meng

Created: 2011-03-14 18:53:26 UTC

Size: 10.46 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):                  DCC: 0x00100010 (single channel, XOR randomization: enabled, XOR bit: 11)
>(II):            CHDECMISC: 0x00000064 (XOR bank, ch2 enh disabled, ch1 enh disabled, ch0 enh enabled, flex disabled, ep not present)
>(II):               C0DRB0: 0x00100010 (0x0010)
>(II):               C0DRB1: 0x00100010 (0x0010)
>(II):               C0DRB2: 0x00100010 (0x0010)
>(II):               C0DRB3: 0x00860010 (0x0010)
>(II):               C1DRB0: 0x00000000 (0x0000)
>(II):               C1DRB1: 0x00000000 (0x0000)
>(II):               C1DRB2: 0x00000000 (0x0000)
>(II):               C1DRB3: 0x00000000 (0x0000)
>(II):              C0DRA01: 0x00000086 (0x0086)
>(II):              C0DRA23: 0x00000000 (0x0000)
>(II):              C1DRA01: 0x00000000 (0x0000)
>(II):              C1DRA23: 0x00000000 (0x0000)
>(II):           PGETBL_CTL: 0x00000001
>(II):    VCLK_DIVISOR_VGA0: 0x00200074 (n = 5, m1 = 0, m2 = 116)
>(II):    VCLK_DIVISOR_VGA1: 0x00200074 (n = 5, m1 = 0, m2 = 116)
>(II):        VCLK_POST_DIV: 0x00800100 (vga0 p1 = 2, p2 = 2, vga1 p1 = 3, p2 = 2)
>(II):            DPLL_TEST: 0x00010001 ()
>(II):         CACHE_MODE_0: 0x00006820
>(II):              D_STATE: 0x0000000b
>(II):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>(II):                SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>(II):              SDVOUDI: 0x00000000
>(II):               DSPARB: 0x00001d9c
>(II):               DSPFW1: 0xf6030f0f
>(II):               DSPFW2: 0x0000030f
>(II):               DSPFW3: 0x7f3f0197
>(II):                 ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
>(II):                 LVDS: 0xc0300300 (enabled, pipe B, 18 bit, 1 channel)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000001 (power target: on)
>(II):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x025807d0
>(II):        PP_OFF_DELAYS: 0x01f407d0
>(II):           PP_DIVISOR: 0x00209d05
>(II):         PFIT_CONTROL: 0x00000008
>(II):      PFIT_PGM_RATIOS: 0x00000000
>(II):      PORT_HOTPLUG_EN: 0x00000220
>(II):    PORT_HOTPLUG_STAT: 0x00001000
>(II):             DSPACNTR: 0xd9000000 (enabled, pipe B)
>(II):           DSPASTRIDE: 0x00001000 (4096 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x025703ff (1024, 600)
>(II):             DSPABASE: 0x03000000
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x00000000 (disabled, single-wide)
>(II):             PIPEASRC: 0x027f01df (640, 480)
>(II):            PIPEASTAT: 0x00000000 (status:)
>(II):    PIPEA_GMCH_DATA_M: 0x00000000
>(II):    PIPEA_GMCH_DATA_N: 0x00000000
>(II):      PIPEA_DP_LINK_M: 0x00000000
>(II):      PIPEA_DP_LINK_N: 0x00000000
>(II):        CURSOR_A_BASE: 0x00000000
>(II):     CURSOR_A_CONTROL: 0x00000000
>(II):    CURSOR_A_POSITION: 0x00000000
>(II):                 FPA0: 0x00200074 (n = 5, m1 = 0, m2 = 116)
>(II):                 FPA1: 0x00200074 (n = 5, m1 = 0, m2 = 116)
>(II):               DPLL_A: 0x04800000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 9, p2 = 10, SDVO mult 1)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0x19000000 (disabled, pipe B)
>(II):           DSPBSTRIDE: 0x00000c80 (3200 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x018f02cf (720, 400)
>(II):             DSPBBASE: 0x00000000
>(II):             DSPBSURF: 0x00000000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEBSRC: 0x03ff0257 (1024, 600)
>(II):            PIPEBSTAT: 0x00400302 (status: LBLC_EVENT_ENABLE VSYNC_INT_STATUS DLINE_COMPARE_STATUS VBLANK_INT_STATUS)
>(II):    PIPEB_GMCH_DATA_M: 0x00000000
>(II):    PIPEB_GMCH_DATA_N: 0x00000000
>(II):      PIPEB_DP_LINK_M: 0x00000000
>(II):      PIPEB_DP_LINK_N: 0x00000000
>(II):        CURSOR_B_BASE: 0x00b00000
>(II):     CURSOR_B_CONTROL: 0x14000027
>(II):    CURSOR_B_POSITION: 0x01300207
>(II):                 FPB0: 0x0010007c (n = 4, m1 = 0, m2 = 124)
>(II):                 FPB1: 0x0010007c (n = 4, m1 = 0, m2 = 124)
>(II):               DPLL_B: 0x98086000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 5, p2 = 14, SDVO mult 1)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x04af03ff (1024 active, 1200 total)
>(II):             HBLANK_B: 0x04af03ff (1024 start, 1200 end)
>(II):              HSYNC_B: 0x044f042f (1072 start, 1104 end)
>(II):             VTOTAL_B: 0x02700257 (600 active, 625 total)
>(II):             VBLANK_B: 0x02700257 (600 start, 625 end)
>(II):              VSYNC_B: 0x0260025a (603 start, 609 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00200074
>(II):    VCLK_DIVISOR_VGA1: 0x00200074
>(II):        VCLK_POST_DIV: 0x00800100
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x00000000
>(II):               TV_DAC: 0x00000000
>(II):             TV_CSC_Y: 0x00000000
>(II):            TV_CSC_Y2: 0x00000000
>(II):             TV_CSC_U: 0x00000000
>(II):            TV_CSC_U2: 0x00000000
>(II):             TV_CSC_V: 0x00000000
>(II):            TV_CSC_V2: 0x00000000
>(II):         TV_CLR_KNOBS: 0x00000000
>(II):         TV_CLR_LEVEL: 0x00000000
>(II):           TV_H_CTL_1: 0x00000000
>(II):           TV_H_CTL_2: 0x00000000
>(II):           TV_H_CTL_3: 0x00000000
>(II):           TV_V_CTL_1: 0x00000000
>(II):           TV_V_CTL_2: 0x00000000
>(II):           TV_V_CTL_3: 0x00000000
>(II):           TV_V_CTL_4: 0x00000000
>(II):           TV_V_CTL_5: 0x00000000
>(II):           TV_V_CTL_6: 0x00000000
>(II):           TV_V_CTL_7: 0x00000000
>(II):          TV_SC_CTL_1: 0x00000000
>(II):          TV_SC_CTL_2: 0x00000000
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00000000
>(II):          TV_WIN_SIZE: 0x00000000
>(II):      TV_FILTER_CTL_1: 0x00000000
>(II):      TV_FILTER_CTL_2: 0x00000000
>(II):      TV_FILTER_CTL_3: 0x00000000
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0x00000000
>(II):         TV_H_LUMA_59: 0x00000000
>(II):        TV_H_CHROMA_0: 0x00000000
>(II):       TV_H_CHROMA_59: 0x00000000
>(II):         FBC_CFB_BASE: 0xffffffff
>(II):          FBC_LL_BASE: 0xffffffff
>(II):          FBC_CONTROL: 0xffffffff
>(II):          FBC_COMMAND: 0xffffffff
>(II):           FBC_STATUS: 0xffffffff
>(II):         FBC_CONTROL2: 0xffffffff
>(II):        FBC_FENCE_OFF: 0xffffffff
>(II):          FBC_MOD_NUM: 0xffffffff
>(II):              MI_MODE: 0x00000200
>(II):         MI_ARB_STATE: 0x00000840
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000000
>(II):       DPB_AUX_CH_CTL: 0x00000000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000000
>(II):       DPC_AUX_CH_CTL: 0x00000000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x00000000
>(II):       DPD_AUX_CH_CTL: 0x00000000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II):           AUD_CONFIG: 0x00000000
>(II):     AUD_HDMIW_STATUS: 0x00000000
>(II):       AUD_CONV_CHCNT: 0x00000000
>(II):        VIDEO_DIP_CTL: 0x00000000
>(II):        AUD_PINW_CNTR: 0x00000000
>(II):          AUD_CNTL_ST: 0x00000000
>(II):          AUD_PIN_CAP: 0x00000000
>(II):         AUD_PINW_CAP: 0x00000000
>(II):   AUD_PINW_UNSOLRESP: 0x00000000
>(II):     AUD_OUT_DIG_CNVT: 0x00000000
>(II):        AUD_OUT_CWCAP: 0x00000000
>(II):          AUD_GRP_CAP: 0x00000000
>(II):             FENCE  0: 0x01900021 ( enabled, X tiled,    8 pitch, 0x01900000 - 0x01900000 (0kb))
>(II):             FENCE  1: 0x02700011 ( enabled, X tiled,    4 pitch, 0x02700000 - 0x02700000 (0kb))
>(II):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  3: 0x03000231 ( enabled, X tiled,   16 pitch, 0x03000000 - 0x03200000 (2048kb))
>(II):             FENCE  4: 0x04c00231 ( enabled, X tiled,   16 pitch, 0x04c00000 - 0x04e00000 (2048kb))
>(II):             FENCE  5: 0x04400231 ( enabled, X tiled,   16 pitch, 0x04400000 - 0x04600000 (2048kb))
>(II):             FENCE  6: 0x00d00011 ( enabled, X tiled,    4 pitch, 0x00d00000 - 0x00d00000 (0kb))
>(II):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  10: 0x02900031 ( enabled, X tiled,   16 pitch, 0x02900000 - 0x02900000 (0kb))
>(II):            FENCE  11: 0x02b00031 ( enabled, X tiled,   16 pitch, 0x02b00000 - 0x02b00000 (0kb))
>(II):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  14: 0x04800231 ( enabled, X tiled,   16 pitch, 0x04800000 - 0x04a00000 (2048kb))
>(II):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II): pipe A dot 25173 n 5 m1 0 m2 116 p1 9 p2 10
>(II): pipe B dot 45000 n 4 m1 0 m2 124 p1 5 p2 14
>(II): DumpRegsEnd

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Attachments on bug 34601: 43698 | 43784 | 44456 | 44457 | 44458 | 44521

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