Attachment 44521 Details for Bug 34601 – Call intel_flush_display_plane() when enabling the plane.

[patch] Call intel_flush_display_plane() when enabling the plane.

0001-drm-i915-Tweak-delays-for-plane-enabling.patch (text/plain), 3.97 KB, created by Chris Wilson on 2011-03-16 13:21:55 UTC

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Creator: Chris Wilson

Created: 2011-03-16 13:21:55 UTC

Size: 3.97 KB

patch

obsolete

>From addee44335aad4f682067c4fa233385c6200dc14 Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Wed, 16 Mar 2011 20:19:08 +0000
>Subject: [PATCH] drm/i915: Tweak delays for plane enabling
>
>---
> drivers/gpu/drm/i915/intel_display.c |   57 ++++++++++++++++++----------------
> 1 files changed, 30 insertions(+), 27 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 89ad6c4..a63d6a5 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -1516,9 +1516,10 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> 
> 	reg = PIPECONF(pipe);
> 	val = I915_READ(reg);
>-	val |= PIPECONF_ENABLE;
>-	I915_WRITE(reg, val);
>-	POSTING_READ(reg);
>+	if (val & PIPECONF_ENABLE)
>+		return;
>+
>+	I915_WRITE(reg, val | PIPECONF_ENABLE);
> 	intel_wait_for_vblank(dev_priv->dev, pipe);
> }
> 
>@@ -1552,12 +1553,25 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
> 
> 	reg = PIPECONF(pipe);
> 	val = I915_READ(reg);
>-	val &= ~PIPECONF_ENABLE;
>-	I915_WRITE(reg, val);
>+	if ((val & PIPECONF_ENABLE) == 0)
>+		return;
>+
>+	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
> 	POSTING_READ(reg);
> 	intel_wait_for_pipe_off(dev_priv->dev, pipe);
> }
> 
>+/*
>+ * Plane regs are double buffered, going from enabled<->disabled needs a
>+ * trigger in order to latch.  The display address reg provides this.
>+ */
>+static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
>+				      enum plane plane)
>+{
>+	u32 reg = DSPADDR(plane);
>+	I915_WRITE(reg, I915_READ(reg));
>+}
>+
> /**
>  * intel_enable_plane - enable a display plane on a given pipe
>  * @dev_priv: i915 private structure
>@@ -1577,21 +1591,11 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv,
> 
> 	reg = DSPCNTR(plane);
> 	val = I915_READ(reg);
>-	val |= DISPLAY_PLANE_ENABLE;
>-	I915_WRITE(reg, val);
>-	POSTING_READ(reg);
>-	intel_wait_for_vblank(dev_priv->dev, pipe);
>-}
>+	if (val & DISPLAY_PLANE_ENABLE)
>+		return;
> 
>-/*
>- * Plane regs are double buffered, going from enabled->disabled needs a
>- * trigger in order to latch.  The display address reg provides this.
>- */
>-static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
>-				      enum plane plane)
>-{
>-	u32 reg = DSPADDR(plane);
>-	I915_WRITE(reg, I915_READ(reg));
>+	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
>+	intel_flush_display_plane(plane);
> }
> 
> /**
>@@ -1610,11 +1614,14 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv,
> 
> 	reg = DSPCNTR(plane);
> 	val = I915_READ(reg);
>-	val &= ~DISPLAY_PLANE_ENABLE;
>-	I915_WRITE(reg, val);
>-	POSTING_READ(reg);
>+	if ((val & DISPLAY_PLANE_ENABLE) == 0)
>+		return;
>+
>+	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
> 	intel_flush_display_plane(dev_priv, plane);
>-	intel_wait_for_vblank(dev_priv->dev, pipe);
>+
>+	if (dev_priv->info->gen == 2)
>+		intel_wait_for_vblank(dev_priv->dev, pipe);
> }
> 
> static void disable_pch_dp(struct drm_i915_private *dev_priv,
>@@ -1769,7 +1776,6 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
> 			return;
> 
> 		I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
>-		POSTING_READ(DPFC_CONTROL);
> 		intel_wait_for_vblank(dev, intel_crtc->pipe);
> 	}
> 
>@@ -1861,7 +1867,6 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
> 			return;
> 
> 		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
>-		POSTING_READ(ILK_DPFC_CONTROL);
> 		intel_wait_for_vblank(dev, intel_crtc->pipe);
> 	}
> 
>@@ -5781,7 +5786,6 @@ static void intel_increase_pllclock(struct drm_crtc *crtc)
> 
> 		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
> 		I915_WRITE(dpll_reg, dpll);
>-		POSTING_READ(dpll_reg);
> 		intel_wait_for_vblank(dev, pipe);
> 
> 		dpll = I915_READ(dpll_reg);
>@@ -5825,7 +5829,6 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
> 
> 		dpll |= DISPLAY_RATE_SELECT_FPA1;
> 		I915_WRITE(dpll_reg, dpll);
>-		dpll = I915_READ(dpll_reg);
> 		intel_wait_for_vblank(dev, pipe);
> 		dpll = I915_READ(dpll_reg);
> 		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
>-- 
>1.7.2.3
>

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Attachments on bug 34601: 43698 | 43784 | 44456 | 44457 | 44458 | 44521

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