Attachment 46083 Details for Bug 36602 – kernel side patch to handle TILE_SURFACE commands

[patch] kernel side patch to handle TILE_SURFACE commands

WIP_hiz_kernel.patch (text/plain), 2.24 KB, created by Pierre-Eric Pelloux-Prayer on 2011-04-26 01:01:54 UTC

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Creator: Pierre-Eric Pelloux-Prayer

Created: 2011-04-26 01:01:54 UTC

Size: 2.24 KB

patch

obsolete

>--- /tmp/radeon/r600_cs.c	2011-04-14 22:03:56.000000000 +0200
>+++ drivers/gpu/drm/radeon/r600_cs.c	2011-04-21 14:04:42.359776967 +0200
>@@ -69,6 +69,9 @@ struct r600_cs_track {
> 	u32			db_offset;
> 	struct radeon_bo	*db_bo;
> 	u64			db_bo_mc;
>+	u32			hiz_offset;
>+	struct radeon_bo	*hiz_bo;
>+	u64			hiz_bo_mc;
> };
> 
> static inline int r600_bpe_from_format(u32 *bpe, u32 format)
>@@ -223,6 +226,8 @@ static void r600_cs_track_init(struct r6
> 	track->cb_shader_mask = 0xFFFFFFFF;
> 	track->db_bo = NULL;
> 	track->db_bo_mc = 0xFFFFFFFF;
>+	track->hiz_bo = NULL;
>+	track->hiz_bo_mc = 0xFFFFFFFF;
> 	/* assume the biggest format and that htile is enabled */
> 	track->db_depth_info = 7 | (1 << 25);
> 	track->db_depth_view = 0xFFFFC000;
>@@ -384,8 +389,8 @@ static int r600_cs_track_check(struct ra
> 			dev_warn(p->dev, "z/stencil with no depth buffer\n");
> 			return -EINVAL;
> 		}
>-		if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
>-			dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
>+		if (track->hiz_bo == NULL && G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
>+			dev_warn(p->dev, "z/stencil htile enabled with no htile surface\n");
> 			return -EINVAL;
> 		}
> 		switch (G_028010_FORMAT(track->db_depth_info)) {
>@@ -442,6 +447,8 @@ static int r600_cs_track_check(struct ra
> 				dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
> 					 G_028010_ARRAY_MODE(track->db_depth_info),
> 					 track->db_depth_info);
>+                dev_warn(p->dev, "%s allowed tiling mode : %d/%d/%d/%d != %d\n", __func__,
>+                    	ARRAY_LINEAR_GENERAL,ARRAY_LINEAR_ALIGNED,ARRAY_1D_TILED_THIN1,ARRAY_2D_TILED_THIN1, array_check.array_mode);
> 				return -EINVAL;
> 			}
> 			switch (array_mode) {
>@@ -1045,6 +1052,17 @@ static inline int r600_cs_check_reg(stru
> 		track->db_bo_mc = reloc->lobj.gpu_offset;
> 		break;
> 	case DB_HTILE_DATA_BASE:
>+		r = r600_cs_packet_next_reloc(p, &reloc);
>+		if (r) {
>+			dev_warn(p->dev, "bad SET_CONTEXT_REG "
>+					"0x%04X\n", reg);
>+			return -EINVAL;
>+		}
>+		track->hiz_offset = radeon_get_ib_value(p, idx) << 8;
>+		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
>+		track->hiz_bo = reloc->robj;
>+		track->hiz_bo_mc = reloc->lobj.gpu_offset;
>+		break;
> 	case SQ_PGM_START_FS:
> 	case SQ_PGM_START_ES:
> 	case SQ_PGM_START_VS:

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Attachments on bug 36602: 46081 | 46082 | 46083 | 46281 | 47419 | 47420 | 49931 | 49966 | 49972 | 50174 | 50175 | 50192 | 56784 | 56785 | 56845

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