Attachment 47074 Details for Bug 35901 – nv17_crtc_large_pitch.patch

[patch] nv17_crtc_large_pitch.patch

nv17_crtc_large_pitch.patch (text/plain), 2.69 KB, created by Francisco Jerez on 2011-05-23 14:35:12 UTC

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Creator: Francisco Jerez

Created: 2011-05-23 14:35:12 UTC

Size: 2.69 KB

patch

obsolete

>diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c b/drivers/gpu/drm/nouveau/nouveau_hw.c
>index 053edf9..ba896e5 100644
>--- a/drivers/gpu/drm/nouveau/nouveau_hw.c
>+++ b/drivers/gpu/drm/nouveau/nouveau_hw.c
>@@ -900,6 +900,7 @@ nv_save_state_ext(struct drm_device *dev, int head,
> 	}
> 	/* NV11 and NV20 don't have this, they stop at 0x52. */
> 	if (nv_gf4_disp_arch(dev)) {
>+		rd_cio_state(dev, head, regp, NV_CIO_CRE_42);
> 		rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
> 		rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
> 
>@@ -1003,6 +1004,7 @@ nv_load_state_ext(struct drm_device *dev, int head,
> 			nouveau_wait_eq(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
> 		}
> 
>+		wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
> 		wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
> 		wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
> 
>diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
>index 3c78bc8..f1a3ae4 100644
>--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
>+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
>@@ -376,7 +376,10 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
> 	 */
> 
> 	/* framebuffer can be larger than crtc scanout area. */
>-	regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
>+	regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
>+		XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
>+	regp->CRTC[NV_CIO_CRE_42] =
>+		XLATE(fb->pitch / 8, 11, NV_CIO_CRE_42_OFFSET_11);
> 	regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
> 					    MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
> 	regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
>@@ -824,8 +827,11 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
> 	regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitch >> 3;
> 	regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
> 		XLATE(drm_fb->pitch >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
>+	regp->CRTC[NV_CIO_CRE_42] =
>+		XLATE(drm_fb->pitch / 8, 11, NV_CIO_CRE_42_OFFSET_11);
> 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
> 	crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
>+	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
> 
> 	/* Update the framebuffer location. */
> 	regp->fb_start = nv_crtc->fb.offset & ~3;
>diff --git a/drivers/gpu/drm/nouveau/nvreg.h b/drivers/gpu/drm/nouveau/nvreg.h
>index fe0f253..bbfb1a6 100644
>--- a/drivers/gpu/drm/nouveau/nvreg.h
>+++ b/drivers/gpu/drm/nouveau/nvreg.h
>@@ -277,6 +277,8 @@
> #		define NV_CIO_CRE_EBR_VDE_11		2:2
> #		define NV_CIO_CRE_EBR_VRS_11		4:4
> #		define NV_CIO_CRE_EBR_VBS_11		6:6
>+#	define NV_CIO_CRE_42			0x42
>+#		define NV_CIO_CRE_42_OFFSET_11		6:6
> #	define NV_CIO_CRE_43			0x43
> #	define NV_CIO_CRE_44			0x44	/* head control */
> #	define NV_CIO_CRE_CSB			0x45	/* colour saturation boost */

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Attachments on bug 35901: 45649 | 45650 | 45669 | 45670 | 45671 | 45672 | 47074

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