Attachment 48390 Details for Bug 38657 – Part of dmesg with power states

Part of dmesg with power states

drm_pm_dmesg (text/plain), 5.66 KB, created by mkgmafbt on 2011-06-24 15:45:28 UTC

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Creator: mkgmafbt

Created: 2011-06-24 15:45:28 UTC

Size: 5.66 KB

patch

obsolete

>[   19.835343] [drm] Initialized drm 1.1.0 20060810
>[   20.762996] [drm] radeon defaulting to kernel modesetting.
>[   20.763046] [drm] radeon kernel modesetting enabled.
>[   20.763099] [drm:drm_pci_init], 
>[   20.763302] [drm:drm_get_pci_dev], 
>[   20.763560] [drm:drm_get_minor], 
>[   20.763737] [drm:drm_get_minor], new minor assigned 64
>[   20.763818] [drm:drm_get_minor], 
>[   20.763949] [drm:drm_get_minor], new minor assigned 0
>[   20.764045] [drm] initializing kernel modesetting (REDWOOD 0x1002:0x68D8).
>[   20.764116] [drm] register mmio base: 0xFE9E0000
>[   20.764158] [drm] register mmio size: 131072
>[   20.764728] [drm:radeon_get_bios], ATOMBIOS detected
>[   20.764853] [drm:atom_allocate_fb_scratch], atom firmware requested 0007ffec 20kb
>[   20.765244] [drm] Detected VRAM RAM=512M, BAR=256M
>[   20.765470] [drm] RAM width 128bits DDR
>[   20.765701] [drm] radeon: 512M of VRAM memory ready
>[   20.765744] [drm] radeon: 512M of GTT memory ready.
>[   20.765803] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
>[   20.765847] [drm] Driver supports precise vblank timestamp query.
>[   20.766015] [drm:drm_irq_install], irq=43
>[   20.766101] [drm:evergreen_irq_process], r600_irq_process start: rptr 0, wptr 0
>[   20.766207] [drm] radeon: irq initialized.
>[   20.766253] [drm] GART: num cpu pages 131072, num gpu pages 131072
>[   20.767547] [drm:r600_init_microcode], 
>[   20.767681] [drm] Loading REDWOOD Microcode
>[   21.409581] [drm:evergreen_blit_init], evergreen blit allocated bo 00000600 vs 00000400 ps 00000500
>[   21.409819] [drm:evergreen_irq_set], evergreen_irq_set: sw int
>[   21.426120] [drm] ring test succeeded in 1 usecs
>[   21.426305] [drm] radeon: ib pool ready.
>[   21.426425] [drm:evergreen_irq_set], 
>[   21.426439] [drm:evergreen_irq_process], r600_irq_process start: rptr 0, wptr 16
>[   21.426461] [drm:evergreen_irq_process], IH: CP EOP
>[   21.426643] [drm] ib test succeeded in 0 usecs
>[   21.426994] [drm:drm_sysfs_connector_add], adding "HDMI-A-1" to sysfs
>[   21.427101] [drm:drm_sysfs_hotplug_event], generating hotplug event
>[   21.427195] [drm:drm_sysfs_connector_add], adding "DVI-I-1" to sysfs
>[   21.427304] [drm:drm_sysfs_hotplug_event], generating hotplug event
>[   21.427395] [drm:drm_sysfs_connector_add], adding "VGA-1" to sysfs
>[   21.427496] [drm:drm_sysfs_hotplug_event], generating hotplug event
>[   21.427583] [drm] Radeon Display Connectors
>[   21.427625] [drm] Connector 0:
>[   21.427667] [drm]   HDMI-A
>[   21.427708] [drm]   HPD5
>[   21.427750] [drm]   DDC: 0x6470 0x6470 0x6474 0x6474 0x6478 0x6478 0x647c 0x647c
>[   21.427796] [drm]   Encoders:
>[   21.427838] [drm]     DFP1: INTERNAL_UNIPHY2
>[   21.427880] [drm] Connector 1:
>[   21.427921] [drm]   DVI-I
>[   21.427963] [drm]   HPD1
>[   21.428006] [drm]   DDC: 0x6450 0x6450 0x6454 0x6454 0x6458 0x6458 0x645c 0x645c
>[   21.428053] [drm]   Encoders:
>[   21.428095] [drm]     DFP2: INTERNAL_UNIPHY1
>[   21.428137] [drm]     CRT1: INTERNAL_KLDSCP_DAC1
>[   21.428180] [drm] Connector 2:
>[   21.428222] [drm]   VGA
>[   21.428264] [drm]   DDC: 0x6440 0x6440 0x6444 0x6444 0x6448 0x6448 0x644c 0x644c
>[   21.428311] [drm]   Encoders:
>[   21.428354] [drm]     CRT2: INTERNAL_KLDSCP_DAC2
>[   21.508227] [drm:evergreen_irq_set], evergreen_irq_set: hpd 1
>[   21.508311] [drm:evergreen_irq_set], evergreen_irq_set: hpd 5
>[   21.508393] [drm] Internal thermal controller with fan control
>[   21.508439] [drm:radeon_pm_print_states], 5 Power State(s)
>[   21.508518] [drm:radeon_pm_print_states], State 0: Default
>[   21.508597] [drm:radeon_pm_print_states], 	Default
>[   21.508672] [drm:radeon_pm_print_states], 	16 PCIE Lanes
>[   21.508790] [drm:radeon_pm_print_states], 	3 Clock Mode(s)
>[   21.508869] [drm:radeon_pm_print_states], 		0 e: 775000	m: 950000	v: 1100	No display only
>[   21.508953] [drm:radeon_pm_print_states], 		1 e: 775000	m: 950000	v: 1100
>[   21.509034] [drm:radeon_pm_print_states], 		2 e: 775000	m: 950000	v: 1100
>[   21.509114] [drm:radeon_pm_print_states], State 1: Performance
>[   21.509194] [drm:radeon_pm_print_states], 	16 PCIE Lanes
>[   21.509272] [drm:radeon_pm_print_states], 	Single display only
>[   21.509351] [drm:radeon_pm_print_states], 	3 Clock Mode(s)
>[   21.509433] [drm:radeon_pm_print_states], 		0 e: 400000	m: 950000	v: 1100	No display only
>[   21.509517] [drm:radeon_pm_print_states], 		1 e: 400000	m: 950000	v: 1100
>[   21.509597] [drm:radeon_pm_print_states], 		2 e: 775000	m: 950000	v: 1100
>[   21.509677] [drm:radeon_pm_print_states], State 2: Default
>[   21.509756] [drm:radeon_pm_print_states], 	16 PCIE Lanes
>[   21.509835] [drm:radeon_pm_print_states], 	3 Clock Mode(s)
>[   21.509914] [drm:radeon_pm_print_states], 		0 e: 400000	m: 950000	v: 1100	No display only
>[   21.510017] [drm:radeon_pm_print_states], 		1 e: 400000	m: 950000	v: 1100
>[   21.510097] [drm:radeon_pm_print_states], 		2 e: 400000	m: 950000	v: 1100
>[   21.510177] [drm:radeon_pm_print_states], State 3: Performance
>[   21.510256] [drm:radeon_pm_print_states], 	16 PCIE Lanes
>[   21.510335] [drm:radeon_pm_print_states], 	3 Clock Mode(s)
>[   21.510414] [drm:radeon_pm_print_states], 		0 e: 400000	m: 950000	v: 1100	No display only
>[   21.510498] [drm:radeon_pm_print_states], 		1 e: 400000	m: 950000	v: 1100
>[   21.510579] [drm:radeon_pm_print_states], 		2 e: 775000	m: 950000	v: 1100
>[   21.510661] [drm:radeon_pm_print_states], State 4: Default
>[   21.511687] [drm:radeon_pm_print_states], 	16 PCIE Lanes
>[   21.511774] [drm:radeon_pm_print_states], 	3 Clock Mode(s)
>[   21.511857] [drm:radeon_pm_print_states], 		0 e: 157000	m: 300000	v: 900	No display only
>[   21.511941] [drm:radeon_pm_print_states], 		1 e: 157000	m: 300000	v: 900
>[   21.512025] [drm:radeon_pm_print_states], 		2 e: 157000	m: 300000	v: 900
>[   21.512181] [drm] radeon: power management initialized

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