Attachment 48693 Details for Bug 38917 – power states by radeon_pm_print_states

power states by radeon_pm_print_states

radeon_pm_print_states.txt (text/plain), 2.25 KB, created by Antti Lahtinen on 2011-07-02 11:43:03 UTC

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Creator: Antti Lahtinen

Created: 2011-07-02 11:43:03 UTC

Size: 2.25 KB

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obsolete

>9 Power State(s)
>State 0: Default
>        Default
>        16 PCIE Lanes
>        3 Clock Mode(s)
>                0 e: 100000     m: 157000       v: 900  No display only
>                1 e: 100000     m: 157000       v: 900
>                2 e: 100000     m: 157000       v: 900
>State 1: Performance
>        16 PCIE Lanes
>        Single display only
>        3 Clock Mode(s)
>                0 e: 100000     m: 150000       v: 900  No display only
>                1 e: 450000     m: 800000       v: 950
>                2 e: 550000     m: 800000       v: 1000
>State 2: Default
>        16 PCIE Lanes
>        3 Clock Mode(s)
>                0 e: 550000     m: 800000       v: 1000 No display only
>                1 e: 550000     m: 800000       v: 1000
>                2 e: 550000     m: 800000       v: 1000
>State 3: Performance
>        16 PCIE Lanes
>        3 Clock Mode(s)
>                0 e: 400000     m: 800000       v: 950  No display only
>                1 e: 450000     m: 800000       v: 950
>                2 e: 550000     m: 800000       v: 1000
>State 4: Battery
>        16 PCIE Lanes
>        Single display only
>        3 Clock Mode(s)
>                0 e: 100000     m: 150000       v: 900  No display only
>                1 e: 100000     m: 150000       v: 900
>                2 e: 300000     m: 300000       v: 900
>State 5: Battery
>        16 PCIE Lanes
>        3 Clock Mode(s)
>                0 e: 100000     m: 150000       v: 900  No display only
>                1 e: 100000     m: 150000       v: 900
>                2 e: 300000     m: 300000       v: 900
>State 6: Battery
>        16 PCIE Lanes
>        3 Clock Mode(s)
>                0 e: 300000     m: 300000       v: 900  No display only
>                1 e: 300000     m: 300000       v: 900
>                2 e: 300000     m: 300000       v: 900
>State 7: Battery
>        16 PCIE Lanes
>        3 Clock Mode(s)
>                0 e: 375000     m: 400000       v: 900  No display only
>                1 e: 375000     m: 400000       v: 900
>                2 e: 375000     m: 400000       v: 900
>State 8: Default
>        16 PCIE Lanes
>        3 Clock Mode(s)
>                0 e: 105000     m: 150000       v: 900  No display only
>                1 e: 105000     m: 150000       v: 900
>                2 e: 300000     m: 300000       v: 900

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Attachments on bug 38917: 48691 | 48693 | 49237

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