Attachment 48844 Details for Bug 33487 – Perform FBC re-enable from a delayed task

[patch] Perform FBC re-enable from a delayed task

0001-drm-i915-Perform-intel_enable_fbc-from-a-delayed-tas.patch (text/plain), 9.18 KB, created by Chris Wilson on 2011-07-07 02:28:40 UTC

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Creator: Chris Wilson

Created: 2011-07-07 02:28:40 UTC

Size: 9.18 KB

patch

obsolete

>From 616a193ae962edf4c481cb2fc10f72f5a9ea4099 Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Thu, 7 Jul 2011 09:28:16 +0100
>Subject: [PATCH] drm/i915: Perform intel_enable_fbc() from a delayed task
>
>In order to accommodate the requirements of re-enabling FBC after
>page-flipping, but to avoid doing so and incurring the cost of a wait
>for vblank in the middle of a page-flip sequence, we defer the actual
>enablement by 50ms. If any request to disable FBC arrive within that
>interval, the enablement is cancelled and we are saved from blocking on
>the wait.
>
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>---
> drivers/gpu/drm/i915/i915_dma.c      |    4 +-
> drivers/gpu/drm/i915/i915_drv.h      |    8 +--
> drivers/gpu/drm/i915/i915_suspend.c  |    4 +-
> drivers/gpu/drm/i915/intel_display.c |  126 +++++++++++++++++++++++++++-------
> drivers/gpu/drm/i915/intel_drv.h     |    7 ++
> 5 files changed, 115 insertions(+), 34 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
>index 2b79588..108ed3a 100644
>--- a/drivers/gpu/drm/i915/i915_dma.c
>+++ b/drivers/gpu/drm/i915/i915_dma.c
>@@ -1073,6 +1073,9 @@ static void i915_setup_compression(struct drm_device *dev, int size)
> 	unsigned long cfb_base;
> 	unsigned long ll_base = 0;
> 
>+	/* Just in case the BIOS is doing something questionable. */
>+	intel_disable_fbc(dev);
>+
> 	compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
> 	if (compressed_fb)
> 		compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
>@@ -1099,7 +1102,6 @@ static void i915_setup_compression(struct drm_device *dev, int size)
> 
> 	dev_priv->cfb_size = size;
> 
>-	intel_disable_fbc(dev);
> 	dev_priv->compressed_fb = compressed_fb;
> 	if (HAS_PCH_SPLIT(dev))
> 		I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 01affb63..2b6b3da 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -264,6 +264,7 @@ enum intel_pch {
> #define QUIRK_PIPEA_FORCE (1<<0)
> 
> struct intel_fbdev;
>+struct intel_fbc_work;
> 
> typedef struct drm_i915_private {
> 	struct drm_device *dev;
>@@ -333,6 +334,7 @@ typedef struct drm_i915_private {
> 	int cfb_fence;
> 	int cfb_plane;
> 	int cfb_y;
>+	struct intel_fbc_work *fbc_work;
> 
> 	struct intel_opregion opregion;
> 
>@@ -1316,12 +1318,8 @@ extern void intel_modeset_init(struct drm_device *dev);
> extern void intel_modeset_gem_init(struct drm_device *dev);
> extern void intel_modeset_cleanup(struct drm_device *dev);
> extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
>-extern void i8xx_disable_fbc(struct drm_device *dev);
>-extern void g4x_disable_fbc(struct drm_device *dev);
>-extern void ironlake_disable_fbc(struct drm_device *dev);
>-extern void intel_disable_fbc(struct drm_device *dev);
>-extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
> extern bool intel_fbc_enabled(struct drm_device *dev);
>+extern void intel_disable_fbc(struct drm_device *dev);
> extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
> extern void ironlake_enable_rc6(struct drm_device *dev);
> extern void gen6_set_rps(struct drm_device *dev, u8 val);
>diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
>index e8152d2..cb75db4 100644
>--- a/drivers/gpu/drm/i915/i915_suspend.c
>+++ b/drivers/gpu/drm/i915/i915_suspend.c
>@@ -762,15 +762,13 @@ void i915_restore_display(struct drm_device *dev)
> 	/* FIXME: restore TV & SDVO state */
> 
> 	/* only restore FBC info on the platform that supports FBC*/
>+	intel_disable_fbc(dev);
> 	if (I915_HAS_FBC(dev)) {
> 		if (HAS_PCH_SPLIT(dev)) {
>-			ironlake_disable_fbc(dev);
> 			I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
> 		} else if (IS_GM45(dev)) {
>-			g4x_disable_fbc(dev);
> 			I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
> 		} else {
>-			i8xx_disable_fbc(dev);
> 			I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
> 			I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
> 			I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index d259338..ed8ee8e 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -1380,6 +1380,28 @@ static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
> 	disable_pch_hdmi(dev_priv, pipe, HDMID);
> }
> 
>+static void i8xx_disable_fbc(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	u32 fbc_ctl;
>+
>+	/* Disable compression */
>+	fbc_ctl = I915_READ(FBC_CONTROL);
>+	if ((fbc_ctl & FBC_CTL_EN) == 0)
>+		return;
>+
>+	fbc_ctl &= ~FBC_CTL_EN;
>+	I915_WRITE(FBC_CONTROL, fbc_ctl);
>+
>+	/* Wait for compressing bit to clear */
>+	if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
>+		DRM_DEBUG_KMS("FBC idle timed out\n");
>+		return;
>+	}
>+
>+	DRM_DEBUG_KMS("disabled FBC\n");
>+}
>+
> static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
> {
> 	struct drm_device *dev = crtc->dev;
>@@ -1435,28 +1457,6 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
> 		      dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
> }
> 
>-void i8xx_disable_fbc(struct drm_device *dev)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	u32 fbc_ctl;
>-
>-	/* Disable compression */
>-	fbc_ctl = I915_READ(FBC_CONTROL);
>-	if ((fbc_ctl & FBC_CTL_EN) == 0)
>-		return;
>-
>-	fbc_ctl &= ~FBC_CTL_EN;
>-	I915_WRITE(FBC_CONTROL, fbc_ctl);
>-
>-	/* Wait for compressing bit to clear */
>-	if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
>-		DRM_DEBUG_KMS("FBC idle timed out\n");
>-		return;
>-	}
>-
>-	DRM_DEBUG_KMS("disabled FBC\n");
>-}
>-
> static bool i8xx_fbc_enabled(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>@@ -1638,20 +1638,96 @@ bool intel_fbc_enabled(struct drm_device *dev)
> 	return dev_priv->display.fbc_enabled(dev);
> }
> 
>-void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
>+static void intel_fbc_work_fn(struct work_struct *__work)
> {
>-	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
>+	struct intel_fbc_work *work =
>+		container_of(to_delayed_work(__work),
>+			     struct intel_fbc_work, work);
>+	struct drm_device *dev = work->crtc->dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	mutex_lock(&dev->struct_mutex);
>+	if (work == dev_priv->fbc_work) {
>+		/* Double check that we haven't switched fb without cancelling
>+		 * the prior work.
>+		 */
>+		if (work->crtc->fb == work->fb)
>+			dev_priv->display.enable_fbc(work->crtc,
>+						     work->interval);
>+
>+		dev_priv->fbc_work = NULL;
>+	}
>+	mutex_unlock(&dev->struct_mutex);
>+
>+	kfree(work);
>+}
>+
>+static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
>+{
>+	if (dev_priv->fbc_work == NULL)
>+		return;
>+
>+	DRM_DEBUG_KMS("cancelling pending FBC enable\n");
>+
>+	/* Synchronsiation is provided by struct_mutex and checking of
>+	 * dev_priv->fbc_work, so we can perform the cancellation
>+	 * entirely asynchronously.
>+	 */
>+	if (cancel_delayed_work(&dev_priv->fbc_work->work))
>+		/* tasklet was killed before being run, clean up */
>+		kfree(dev_priv->fbc_work);
>+
>+	/* Mark the work as no longer wanted so that if it does
>+	 * wake-up (because the work was already running and waiting
>+	 * for our mutex), it will discover that is no longer
>+	 * necessary to run.
>+	 */
>+	dev_priv->fbc_work = NULL;
>+}
>+
>+static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
>+{
>+	struct intel_fbc_work *work;
>+	struct drm_device *dev = crtc->dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
> 
> 	if (!dev_priv->display.enable_fbc)
> 		return;
> 
>-	dev_priv->display.enable_fbc(crtc, interval);
>+	intel_cancel_fbc_work(dev_priv);
>+
>+	work = kzalloc(sizeof *work, GFP_KERNEL);
>+	if (work == NULL) {
>+		dev_priv->display.enable_fbc(crtc, interval);
>+		return;
>+	}
>+
>+	work->crtc = crtc;
>+	work->fb = crtc->fb;
>+	work->interval = interval;
>+	INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
>+
>+	dev_priv->fbc_work = work;
>+
>+	DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
>+
>+	/* Delay the actual enabling to let pageflipping cease and the
>+	 * display to settle before starting the compression.
>+	 *
>+	 * A more complicated solution would involve tracking vblanks
>+	 * following the termination of the page-flipping sequence
>+	 * and indeed performing the enable as a co-routine and not
>+	 * waiting synchronously upon the vblank.
>+	 */
>+	schedule_delayed_work(&work->work, msecs_to_jiffies(50));
> }
> 
> void intel_disable_fbc(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 
>+	intel_cancel_fbc_work(dev_priv);
>+
> 	if (!dev_priv->display.disable_fbc)
> 		return;
> 
>diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index 9ffa61e..bd72f65 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -233,6 +233,13 @@ struct intel_unpin_work {
> 	bool enable_stall_check;
> };
> 
>+struct intel_fbc_work {
>+	struct delayed_work work;
>+	struct drm_crtc *crtc;
>+	struct drm_framebuffer *fb;
>+	int interval;
>+};
>+
> int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
> extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);
> 
>-- 
>1.7.6
>

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Attachments on bug 33487: 42539 | 44487 | 48741 | 48840 | 48844

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