Attachment 49537 Details for Bug 38750 – A patch which turns off SSC for all outputs (kernel 3.0).

[patch] A patch which turns off SSC for all outputs (kernel 3.0).

patch.diff (text/plain), 4.03 KB, created by Maxime C on 2011-07-25 13:55:05 UTC

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Creator: Maxime C

Created: 2011-07-25 13:55:05 UTC

Size: 4.03 KB

patch

obsolete

>diff -uNr linux-3.0/drivers/gpu/drm/i915/i915_drv.c linux-3.0-patched/drivers/gpu/drm/i915/i915_drv.c
>--- linux-3.0/drivers/gpu/drm/i915/i915_drv.c	2011-07-22 04:17:23.000000000 +0200
>+++ linux-3.0-patched/drivers/gpu/drm/i915/i915_drv.c	2011-07-25 14:58:38.568936763 +0200
>@@ -61,7 +61,7 @@
> unsigned int i915_lvds_downclock = 0;
> module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
> 
>-unsigned int i915_panel_use_ssc = 1;
>+unsigned int i915_panel_use_ssc = 0;
> module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
> 
> int i915_vbt_sdvo_panel_type = -1;
>diff -uNr linux-3.0/drivers/gpu/drm/i915/i915_drv.h linux-3.0-patched/drivers/gpu/drm/i915/i915_drv.h
>--- linux-3.0/drivers/gpu/drm/i915/i915_drv.h	2011-07-22 04:17:23.000000000 +0200
>+++ linux-3.0-patched/drivers/gpu/drm/i915/i915_drv.h	2011-07-25 14:58:38.568936763 +0200
>@@ -353,6 +353,7 @@
> 	unsigned int lvds_vbt:1;
> 	unsigned int int_crt_support:1;
> 	unsigned int lvds_use_ssc:1;
>+	unsigned int display_clock_mode:1;
> 	int lvds_ssc_freq;
> 	struct {
> 		int rate;
>diff -uNr linux-3.0/drivers/gpu/drm/i915/intel_bios.c linux-3.0-patched/drivers/gpu/drm/i915/intel_bios.c
>--- linux-3.0/drivers/gpu/drm/i915/intel_bios.c	2011-07-22 04:17:23.000000000 +0200
>+++ linux-3.0-patched/drivers/gpu/drm/i915/intel_bios.c	2011-07-25 22:49:27.773124618 +0200
>@@ -285,6 +285,7 @@
> 		dev_priv->lvds_use_ssc = general->enable_ssc;
> 		dev_priv->lvds_ssc_freq =
> 			intel_bios_ssc_frequency(dev, general->ssc_freq);
>+		dev_priv->display_clock_mode = general->display_clock_mode;
> 	}
> }
> 
>diff -uNr linux-3.0/drivers/gpu/drm/i915/intel_bios.h linux-3.0-patched/drivers/gpu/drm/i915/intel_bios.h
>--- linux-3.0/drivers/gpu/drm/i915/intel_bios.h	2011-07-22 04:17:23.000000000 +0200
>+++ linux-3.0-patched/drivers/gpu/drm/i915/intel_bios.h	2011-07-25 14:58:38.568936763 +0200
>@@ -120,7 +120,9 @@
> 	u8 ssc_freq:1;
> 	u8 enable_lfp_on_override:1;
> 	u8 disable_ssc_ddt:1;
>-	u8 rsvd8:3; /* finish byte */
>+	u8 rsvd7:1;
>+	u8 display_clock_mode:1;
>+	u8 rsvd8:1; /* finish byte */
> 
>         /* bits 3 */
> 	u8 disable_smooth_vision:1;
>diff -uNr linux-3.0/drivers/gpu/drm/i915/intel_display.c linux-3.0-patched/drivers/gpu/drm/i915/intel_display.c
>--- linux-3.0/drivers/gpu/drm/i915/intel_display.c	2011-07-22 04:17:23.000000000 +0200
>+++ linux-3.0-patched/drivers/gpu/drm/i915/intel_display.c	2011-07-25 22:51:48.973122522 +0200
>@@ -4914,42 +4914,30 @@
> 	 */
> 	temp = I915_READ(PCH_DREF_CONTROL);
> 	/* Always enable nonspread source */
>+	temp &= ~DREF_SSC1_ENABLE;
>+	temp &= ~DREF_SSC4_ENABLE;
>+	temp &= ~DREF_SUPERSPREAD_SOURCE_ENABLE;
> 	temp &= ~DREF_NONSPREAD_SOURCE_MASK;
>-	temp |= DREF_NONSPREAD_SOURCE_ENABLE;
>+	//temp |= DREF_NONSPREAD_SOURCE_ENABLE;
> 	temp &= ~DREF_SSC_SOURCE_MASK;
>-	temp |= DREF_SSC_SOURCE_ENABLE;
>+	//temp |= DREF_SSC_SOURCE_ENABLE;
>+	temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> 	I915_WRITE(PCH_DREF_CONTROL, temp);
> 
> 	POSTING_READ(PCH_DREF_CONTROL);
> 	udelay(200);
> 
>-	if (has_edp_encoder) {
>-		if (intel_panel_use_ssc(dev_priv)) {
>-			temp |= DREF_SSC1_ENABLE;
>-			I915_WRITE(PCH_DREF_CONTROL, temp);
>-
>-			POSTING_READ(PCH_DREF_CONTROL);
>-			udelay(200);
>-		}
>-		temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
>+	if (dev_priv->display_clock_mode)
>+		temp |= DREF_NONSPREAD_CK505_ENABLE;
>+	else
>+		temp |= DREF_NONSPREAD_SOURCE_ENABLE;
>+	if (has_edp_encoder &&
>+		!intel_encoder_is_pch_edp(&has_edp_encoder->base))
>+		temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
>+	I915_WRITE(PCH_DREF_CONTROL, temp);
>+	POSTING_READ(PCH_DREF_CONTROL);
>+	udelay(200);
> 
>-		/* Enable CPU source on CPU attached eDP */
>-		if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
>-			if (intel_panel_use_ssc(dev_priv))
>-				temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
>-			else
>-				temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
>-		} else {
>-			/* Enable SSC on PCH eDP if needed */
>-			if (intel_panel_use_ssc(dev_priv)) {
>-				DRM_ERROR("enabling SSC on PCH\n");
>-				temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
>-			}
>-		}
>-		I915_WRITE(PCH_DREF_CONTROL, temp);
>-		POSTING_READ(PCH_DREF_CONTROL);
>-		udelay(200);
>-	}
> 
> 	fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
> 	if (has_reduced_clock)

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Attachments on bug 38750: 49493 | 49537 | 49582 | 49887 | 49888 | 52870

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