Attachment 50936 Details for Bug 38863 – Patch to fix the GPU hangs by emitting depth stalls.

[patch] Patch to fix the GPU hangs by emitting depth stalls.

0001-i965-gen7-Emit-depth-stalls-and-flushes-before-chang.patch (text/plain), 2.36 KB, created by Kenneth Graunke on 2011-09-06 06:01:12 UTC

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Creator: Kenneth Graunke

Created: 2011-09-06 06:01:12 UTC

Size: 2.36 KB

patch

obsolete

>From a66bb7d72ffbcb863fa62140f4940ff32b8249d2 Mon Sep 17 00:00:00 2001
>From: Kenneth Graunke <kenneth@whitecape.org>
>Date: Thu, 1 Sep 2011 04:18:20 -0700
>Subject: [PATCH] i965/gen7: Emit depth stalls and flushes before changing
> depth state.
>
>Fixes OpenArena on Gen7.  Technically, adding only the first depth stall
>fixes it, but the documentation says to do this.
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38863
>Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
>---
> src/mesa/drivers/dri/i965/gen7_misc_state.c |   33 +++++++++++++++++++++++++++
> 1 files changed, 33 insertions(+), 0 deletions(-)
>
>diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
>index 7544f96..d902b02 100644
>--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
>+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
>@@ -80,6 +80,39 @@ static void emit_depthbuffer(struct brw_context *brw)
>    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
>    struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
> 
>+   /**
>+    * Restriction [DevSNB, DevIVB]:
>+    *
>+    * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
>+    * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
>+    * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
>+    * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
>+    * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
>+    * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
>+    * unless SW can otherwise guarantee that the pipeline from WM onwards is
>+    * already flushed (e.g., via a preceding MI_FLUSH).
>+    */
>+   BEGIN_BATCH(4);
>+   OUT_BATCH(_3DSTATE_PIPE_CONTROL);
>+   OUT_BATCH(PIPE_CONTROL_DEPTH_STALL);
>+   OUT_BATCH(0); /* address */
>+   OUT_BATCH(0); /* write data */
>+   ADVANCE_BATCH()
>+
>+   BEGIN_BATCH(4);
>+   OUT_BATCH(_3DSTATE_PIPE_CONTROL);
>+   OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH);
>+   OUT_BATCH(0); /* address */
>+   OUT_BATCH(0); /* write data */
>+   ADVANCE_BATCH();
>+
>+   BEGIN_BATCH(4);
>+   OUT_BATCH(_3DSTATE_PIPE_CONTROL);
>+   OUT_BATCH(PIPE_CONTROL_DEPTH_STALL);
>+   OUT_BATCH(0); /* address */
>+   OUT_BATCH(0); /* write data */
>+   ADVANCE_BATCH();
>+
>    /* Gen7 doesn't support packed depth/stencil */
>    assert(srb == NULL || srb != drb);
> 
>-- 
>1.7.6.1
>

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Attachments on bug 38863: 48634 | 48635 | 48636 | 50936

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