Attachment 52126 Details for Bug 41592 – Xorg log

Xorg log

Xorg.log.aftercrash (text/plain), 403.55 KB, created by mirandir on 2011-10-08 11:29:16 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: mirandir

Created: 2011-10-08 11:29:16 UTC

Size: 403.55 KB

patch

obsolete

>[    20.745] 
>X.Org X Server 1.10.4
>Release Date: 2011-08-19
>[    20.745] X Protocol Version 11, Revision 0
>[    20.745] Build Operating System: Linux 3.0-ARCH x86_64 
>[    20.745] Current Operating System: Linux ArchLinux 3.0-ARCH #1 SMP PREEMPT Fri Oct 7 11:35:34 CEST 2011 x86_64
>[    20.745] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-linux root=/dev/disk/by-label/racine ro resume=/dev/sda6 splash=silent,theme:arch-elegant,fadein,fadeout console=tty1 quiet radeon.modeset=1 drm.debug=0xf
>[    20.745] Build Date: 17 September 2011  07:42:58AM
>[    20.745]  
>[    20.745] Current version of pixman: 0.22.2
>[    20.745] 	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>[    20.746] Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>[    20.746] (==) Log file: "/var/log/Xorg.0.log", Time: Sat Oct  8 19:37:12 2011
>[    20.805] (==) Using config directory: "/etc/X11/xorg.conf.d"
>[    20.827] (==) No Layout section.  Using the first Screen section.
>[    20.827] (==) No screen section available. Using defaults.
>[    20.828] (**) |-->Screen "Default Screen Section" (0)
>[    20.828] (**) |   |-->Monitor "<default monitor>"
>[    20.828] (==) No monitor specified for screen "Default Screen Section".
>	Using a default monitor configuration.
>[    20.828] (==) Automatically adding devices
>[    20.828] (==) Automatically enabling devices
>[    20.896] (WW) The directory "/usr/share/fonts/OTF/" does not exist.
>[    20.896] 	Entry deleted from font path.
>[    20.904] (WW) `fonts.dir' not found (or not valid) in "/usr/share/fonts/100dpi/".
>[    20.904] 	Entry deleted from font path.
>[    20.904] 	(Run 'mkfontdir' on "/usr/share/fonts/100dpi/").
>[    20.905] (WW) `fonts.dir' not found (or not valid) in "/usr/share/fonts/75dpi/".
>[    20.905] 	Entry deleted from font path.
>[    20.905] 	(Run 'mkfontdir' on "/usr/share/fonts/75dpi/").
>[    20.905] (==) FontPath set to:
>	/usr/share/fonts/misc/,
>	/usr/share/fonts/TTF/,
>	/usr/share/fonts/Type1/
>[    20.905] (==) ModulePath set to "/usr/lib/xorg/modules"
>[    20.905] (II) The server relies on udev to provide the list of input devices.
>	If no devices become available, reconfigure udev or disable AutoAddDevices.
>[    20.905] (II) Loader magic: 0x7d6160
>[    20.905] (II) Module ABI versions:
>[    20.905] 	X.Org ANSI C Emulation: 0.4
>[    20.905] 	X.Org Video Driver: 10.0
>[    20.905] 	X.Org XInput driver : 12.2
>[    20.905] 	X.Org Server Extension : 5.0
>[    20.907] (--) PCI:*(0:1:0:0) 1002:68e0:1028:0447 rev 0, Mem @ 0xc0000000/268435456, 0xfbe20000/131072, I/O @ 0x0000e000/256, BIOS @ 0x????????/131072
>[    20.907] (WW) Open ACPI failed (/var/run/acpid.socket) (No such file or directory)
>[    20.907] (II) LoadModule: "extmod"
>[    21.137] (II) Loading /usr/lib/xorg/modules/extensions/libextmod.so
>[    21.150] (II) Module extmod: vendor="X.Org Foundation"
>[    21.150] 	compiled for 1.10.4, module version = 1.0.0
>[    21.150] 	Module class: X.Org Server Extension
>[    21.150] 	ABI class: X.Org Server Extension, version 5.0
>[    21.150] (II) Loading extension MIT-SCREEN-SAVER
>[    21.150] (II) Loading extension XFree86-VidModeExtension
>[    21.150] (II) Loading extension XFree86-DGA
>[    21.150] (II) Loading extension DPMS
>[    21.150] (II) Loading extension XVideo
>[    21.150] (II) Loading extension XVideo-MotionCompensation
>[    21.150] (II) Loading extension X-Resource
>[    21.150] (II) LoadModule: "dbe"
>[    21.150] (II) Loading /usr/lib/xorg/modules/extensions/libdbe.so
>[    21.151] (II) Module dbe: vendor="X.Org Foundation"
>[    21.151] 	compiled for 1.10.4, module version = 1.0.0
>[    21.151] 	Module class: X.Org Server Extension
>[    21.151] 	ABI class: X.Org Server Extension, version 5.0
>[    21.151] (II) Loading extension DOUBLE-BUFFER
>[    21.151] (II) LoadModule: "glx"
>[    21.151] (II) Loading /usr/lib/xorg/modules/extensions/libglx.so
>[    21.170] (II) Module glx: vendor="X.Org Foundation"
>[    21.170] 	compiled for 1.10.4, module version = 1.0.0
>[    21.170] 	ABI class: X.Org Server Extension, version 5.0
>[    21.170] (==) AIGLX enabled
>[    21.170] (II) Loading extension GLX
>[    21.171] (II) LoadModule: "record"
>[    21.171] (II) Loading /usr/lib/xorg/modules/extensions/librecord.so
>[    21.180] (II) Module record: vendor="X.Org Foundation"
>[    21.180] 	compiled for 1.10.4, module version = 1.13.0
>[    21.180] 	Module class: X.Org Server Extension
>[    21.180] 	ABI class: X.Org Server Extension, version 5.0
>[    21.180] (II) Loading extension RECORD
>[    21.181] (II) LoadModule: "dri"
>[    21.181] (II) Loading /usr/lib/xorg/modules/extensions/libdri.so
>[    21.220] (II) Module dri: vendor="X.Org Foundation"
>[    21.220] 	compiled for 1.10.4, module version = 1.0.0
>[    21.220] 	ABI class: X.Org Server Extension, version 5.0
>[    21.220] (II) Loading extension XFree86-DRI
>[    21.220] (II) LoadModule: "dri2"
>[    21.220] (II) Loading /usr/lib/xorg/modules/extensions/libdri2.so
>[    21.221] (II) Module dri2: vendor="X.Org Foundation"
>[    21.221] 	compiled for 1.10.4, module version = 1.2.0
>[    21.222] 	ABI class: X.Org Server Extension, version 5.0
>[    21.222] (II) Loading extension DRI2
>[    21.222] (==) Matched ati as autoconfigured driver 0
>[    21.222] (==) Matched vesa as autoconfigured driver 1
>[    21.222] (==) Matched fbdev as autoconfigured driver 2
>[    21.222] (==) Assigned the driver to the xf86ConfigLayout
>[    21.222] (II) LoadModule: "ati"
>[    21.222] (II) Loading /usr/lib/xorg/modules/drivers/ati_drv.so
>[    21.228] (II) Module ati: vendor="X.Org Foundation"
>[    21.228] 	compiled for 1.10.1, module version = 6.14.2
>[    21.228] 	Module class: X.Org Video Driver
>[    21.228] 	ABI class: X.Org Video Driver, version 10.0
>[    21.228] (II) LoadModule: "radeon"
>[    21.228] (II) Loading /usr/lib/xorg/modules/drivers/radeon_drv.so
>[    21.289] (II) Module radeon: vendor="X.Org Foundation"
>[    21.289] 	compiled for 1.10.1, module version = 6.14.2
>[    21.289] 	Module class: X.Org Video Driver
>[    21.289] 	ABI class: X.Org Video Driver, version 10.0
>[    21.290] (II) LoadModule: "vesa"
>[    21.302] (WW) Warning, couldn't open module vesa
>[    21.302] (II) UnloadModule: "vesa"
>[    21.302] (II) Unloading vesa
>[    21.302] (EE) Failed to load module "vesa" (module does not exist, 0)
>[    21.302] (II) LoadModule: "fbdev"
>[    21.302] (WW) Warning, couldn't open module fbdev
>[    21.302] (II) UnloadModule: "fbdev"
>[    21.302] (II) Unloading fbdev
>[    21.302] (EE) Failed to load module "fbdev" (module does not exist, 0)
>[    21.302] (II) RADEON: Driver for ATI Radeon chipsets:
>	ATI Radeon Mobility X600 (M24) 3150 (PCIE), ATI FireMV 2400 (PCI),
>	ATI Radeon Mobility X300 (M24) 3152 (PCIE),
>	ATI FireGL M24 GL 3154 (PCIE), ATI FireMV 2400 3155 (PCI),
>	ATI Radeon X600 (RV380) 3E50 (PCIE),
>	ATI FireGL V3200 (RV380) 3E54 (PCIE), ATI Radeon IGP320 (A3) 4136,
>	ATI Radeon IGP330/340/350 (A4) 4137, ATI Radeon 9500 AD (AGP),
>	ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP),
>	ATI FireGL Z1 AG (AGP), ATI Radeon 9800SE AH (AGP),
>	ATI Radeon 9800 AI (AGP), ATI Radeon 9800 AJ (AGP),
>	ATI FireGL X2 AK (AGP), ATI Radeon 9600 AP (AGP),
>	ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP),
>	ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), ATI Radeon 9650,
>	ATI FireGL RV360 AV (AGP), ATI Radeon 7000 IGP (A4+) 4237,
>	ATI Radeon 8500 AIW BB (AGP), ATI Radeon IGP320M (U1) 4336,
>	ATI Radeon IGP330M/340M/350M (U2) 4337,
>	ATI Radeon Mobility 7000 IGP 4437, ATI Radeon 9000/PRO If (AGP/PCI),
>	ATI Radeon 9000 Ig (AGP/PCI), ATI Radeon X800 (R420) JH (AGP),
>	ATI Radeon X800PRO (R420) JI (AGP),
>	ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP),
>	ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP),
>	ATI Radeon Mobility 9800 (M18) JN (AGP),
>	ATI Radeon X800 SE (R420) (AGP), ATI Radeon X800XT (R420) JP (AGP),
>	ATI Radeon X800 VE (R420) JT (AGP), ATI Radeon X850 (R480) (AGP),
>	ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 SE (R480) (AGP),
>	ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP),
>	ATI Radeon Mobility M7 LW (AGP),
>	ATI Mobility FireGL 7800 M7 LX (AGP),
>	ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP),
>	ATI FireGL Mobility 9000 (M9) Ld (AGP),
>	ATI Radeon Mobility 9000 (M9) Lf (AGP),
>	ATI Radeon Mobility 9000 (M9) Lg (AGP), ATI Radeon 9700 Pro ND (AGP),
>	ATI Radeon 9700/9500Pro NE (AGP), ATI Radeon 9600TX NF (AGP),
>	ATI FireGL X1 NG (AGP), ATI Radeon 9800PRO NH (AGP),
>	ATI Radeon 9800 NI (AGP), ATI FireGL X2 NK (AGP),
>	ATI Radeon 9800XT NJ (AGP),
>	ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP),
>	ATI Radeon Mobility 9600 (M10) NQ (AGP),
>	ATI Radeon Mobility 9600 (M11) NR (AGP),
>	ATI Radeon Mobility 9600 (M10) NS (AGP),
>	ATI FireGL Mobility T2 (M10) NT (AGP),
>	ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon QD (AGP),
>	ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP),
>	ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP),
>	ATI Radeon 9100 QM (AGP), ATI Radeon 7500 QW (AGP/PCI),
>	ATI Radeon 7500 QX (AGP/PCI), ATI Radeon VE/7000 QY (AGP/PCI),
>	ATI Radeon VE/7000 QZ (AGP/PCI), ATI ES1000 515E (PCI),
>	ATI Radeon Mobility X300 (M22) 5460 (PCIE),
>	ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE),
>	ATI FireGL M22 GL 5464 (PCIE), ATI Radeon X800 (R423) UH (PCIE),
>	ATI Radeon X800PRO (R423) UI (PCIE),
>	ATI Radeon X800LE (R423) UJ (PCIE),
>	ATI Radeon X800SE (R423) UK (PCIE),
>	ATI Radeon X800 XTP (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE),
>	ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 (R430) (PCIE),
>	ATI FireGL V7100 (R423) (PCIE), ATI FireGL V5100 (R423) UQ (PCIE),
>	ATI FireGL unknown (R423) UR (PCIE),
>	ATI FireGL unknown (R423) UT (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility FireGL V5000 (M26) (PCIE),
>	ATI Mobility Radeon X700 XL (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Mobility Radeon X700 (M26) (PCIE),
>	ATI Radeon X550XTX 5657 (PCIE), ATI Radeon 9100 IGP (A5) 5834,
>	ATI Radeon Mobility 9100 IGP (U3) 5835,
>	ATI Radeon XPRESS 200 5954 (PCIE),
>	ATI Radeon XPRESS 200M 5955 (PCIE), ATI Radeon 9250 5960 (AGP),
>	ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP),
>	ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI),
>	ATI ES1000 5969 (PCI), ATI Radeon XPRESS 200 5974 (PCIE),
>	ATI Radeon XPRESS 200M 5975 (PCIE),
>	ATI Radeon XPRESS 200 5A41 (PCIE),
>	ATI Radeon XPRESS 200M 5A42 (PCIE),
>	ATI Radeon XPRESS 200 5A61 (PCIE),
>	ATI Radeon XPRESS 200M 5A62 (PCIE),
>	ATI Radeon X300 (RV370) 5B60 (PCIE),
>	ATI Radeon X600 (RV370) 5B62 (PCIE),
>	ATI Radeon X550 (RV370) 5B63 (PCIE),
>	ATI FireGL V3100 (RV370) 5B64 (PCIE),
>	ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE),
>	ATI Radeon Mobility 9200 (M9+) 5C61 (AGP),
>	ATI Radeon Mobility 9200 (M9+) 5C63 (AGP),
>	ATI Mobility Radeon X800 XT (M28) (PCIE),
>	ATI Mobility FireGL V5100 (M28) (PCIE),
>	ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850 5D4C (PCIE),
>	ATI Radeon X850 XT PE (R480) (PCIE),
>	ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE),
>	ATI unknown Radeon / FireGL (R480) 5D50 (PCIE),
>	ATI Radeon X850 XT (R480) (PCIE),
>	ATI Radeon X800XT (R423) 5D57 (PCIE),
>	ATI FireGL V5000 (RV410) (PCIE), ATI Radeon X700 XT (RV410) (PCIE),
>	ATI Radeon X700 PRO (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE),
>	ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X1800,
>	ATI Mobility Radeon X1800 XT, ATI Mobility Radeon X1800,
>	ATI Mobility FireGL V7200, ATI FireGL V7200, ATI FireGL V5300,
>	ATI Mobility FireGL V7100, ATI Radeon X1800, ATI Radeon X1800,
>	ATI Radeon X1800, ATI Radeon X1800, ATI Radeon X1800,
>	ATI FireGL V7300, ATI FireGL V7350, ATI Radeon X1600, ATI RV505,
>	ATI Radeon X1300/X1550, ATI Radeon X1550, ATI M54-GL,
>	ATI Mobility Radeon X1400, ATI Radeon X1300/X1550,
>	ATI Radeon X1550 64-bit, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Mobility Radeon X1300,
>	ATI Mobility Radeon X1300, ATI Radeon X1300, ATI Radeon X1300,
>	ATI RV505, ATI RV505, ATI FireGL V3300, ATI FireGL V3350,
>	ATI Radeon X1300, ATI Radeon X1550 64-bit, ATI Radeon X1300/X1550,
>	ATI Radeon X1600, ATI Radeon X1300/X1550, ATI Mobility Radeon X1450,
>	ATI Radeon X1300/X1550, ATI Mobility Radeon X2300,
>	ATI Mobility Radeon X2300, ATI Mobility Radeon X1350,
>	ATI Mobility Radeon X1350, ATI Mobility Radeon X1450,
>	ATI Radeon X1300, ATI Radeon X1550, ATI Mobility Radeon X1350,
>	ATI FireMV 2250, ATI Radeon X1550 64-bit, ATI Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1600, ATI Radeon X1600,
>	ATI Mobility FireGL V5200, ATI Mobility Radeon X1600,
>	ATI Radeon X1650, ATI Radeon X1650, ATI Radeon X1600,
>	ATI Radeon X1300 XT/X1600 Pro, ATI FireGL V3400,
>	ATI Mobility FireGL V5250, ATI Mobility Radeon X1700,
>	ATI Mobility Radeon X1700 XT, ATI FireGL V5200,
>	ATI Mobility Radeon X1700, ATI Radeon X2300HD,
>	ATI Mobility Radeon HD 2300, ATI Mobility Radeon HD 2300,
>	ATI Radeon X1950, ATI Radeon X1900, ATI Radeon X1950,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI Radeon X1900, ATI Radeon X1900, ATI Radeon X1900,
>	ATI AMD Stream Processor, ATI Radeon X1900, ATI Radeon X1950,
>	ATI RV560, ATI RV560, ATI Mobility Radeon X1900, ATI RV560,
>	ATI Radeon X1950 GT, ATI RV570, ATI RV570, ATI FireGL V7400,
>	ATI RV560, ATI Radeon X1650, ATI Radeon X1650, ATI RV560,
>	ATI Radeon 9100 PRO IGP 7834, ATI Radeon Mobility 9200 IGP 7835,
>	ATI Radeon X1200, ATI Radeon X1200, ATI Radeon X1200,
>	ATI Radeon X1200, ATI Radeon X1200, ATI RS740, ATI RS740M, ATI RS740,
>	ATI RS740M, ATI Radeon HD 2900 XT, ATI Radeon HD 2900 XT,
>	ATI Radeon HD 2900 XT, ATI Radeon HD 2900 Pro, ATI Radeon HD 2900 GT,
>	ATI FireGL V8650, ATI FireGL V8600, ATI FireGL V7600,
>	ATI Radeon 4800 Series, ATI Radeon HD 4870 x2,
>	ATI Radeon 4800 Series, ATI Radeon HD 4850 x2,
>	ATI FirePro V8750 (FireGL), ATI FirePro V7760 (FireGL),
>	ATI Mobility RADEON HD 4850, ATI Mobility RADEON HD 4850 X2,
>	ATI Radeon 4800 Series, ATI FirePro RV770, AMD FireStream 9270,
>	AMD FireStream 9250, ATI FirePro V8700 (FireGL),
>	ATI Mobility RADEON HD 4870, ATI Mobility RADEON M98,
>	ATI Mobility RADEON HD 4870, ATI Radeon 4800 Series,
>	ATI Radeon 4800 Series, ATI FirePro M7750, ATI M98, ATI M98, ATI M98,
>	ATI Mobility Radeon HD 4650, ATI Radeon RV730 (AGP),
>	ATI Mobility Radeon HD 4670, ATI FirePro M5750,
>	ATI Mobility Radeon HD 4670, ATI Radeon RV730 (AGP),
>	ATI RV730XT [Radeon HD 4670], ATI RADEON E4600,
>	ATI Radeon HD 4600 Series, ATI RV730 PRO [Radeon HD 4650],
>	ATI FirePro V7750 (FireGL), ATI FirePro V5700 (FireGL),
>	ATI FirePro V3750 (FireGL), ATI Mobility Radeon HD 4830,
>	ATI Mobility Radeon HD 4850, ATI FirePro M7740, ATI RV740,
>	ATI Radeon HD 4770, ATI Radeon HD 4700 Series, ATI Radeon HD 4770,
>	ATI FirePro M5750, ATI RV610, ATI Radeon HD 2400 XT,
>	ATI Radeon HD 2400 Pro, ATI Radeon HD 2400 PRO AGP, ATI FireGL V4000,
>	ATI RV610, ATI Radeon HD 2350, ATI Mobility Radeon HD 2400 XT,
>	ATI Mobility Radeon HD 2400, ATI RADEON E2400, ATI RV610,
>	ATI FireMV 2260, ATI RV670, ATI Radeon HD3870,
>	ATI Mobility Radeon HD 3850, ATI Radeon HD3850,
>	ATI Mobility Radeon HD 3850 X2, ATI RV670,
>	ATI Mobility Radeon HD 3870, ATI Mobility Radeon HD 3870 X2,
>	ATI Radeon HD3870 X2, ATI FireGL V7700, ATI Radeon HD3850,
>	ATI Radeon HD3690, AMD Firestream 9170, ATI Radeon HD 4550,
>	ATI Radeon RV710, ATI Radeon RV710, ATI Radeon RV710,
>	ATI Radeon HD 4350, ATI Mobility Radeon 4300 Series,
>	ATI Mobility Radeon 4500 Series, ATI Mobility Radeon 4500 Series,
>	ATI FirePro RG220, ATI Mobility Radeon 4330, ATI RV630,
>	ATI Mobility Radeon HD 2600, ATI Mobility Radeon HD 2600 XT,
>	ATI Radeon HD 2600 XT AGP, ATI Radeon HD 2600 Pro AGP,
>	ATI Radeon HD 2600 XT, ATI Radeon HD 2600 Pro, ATI Gemini RV630,
>	ATI Gemini Mobility Radeon HD 2600 XT, ATI FireGL V5600,
>	ATI FireGL V3600, ATI Radeon HD 2600 LE,
>	ATI Mobility FireGL Graphics Processor, ATI Radeon HD 3470,
>	ATI Mobility Radeon HD 3430, ATI Mobility Radeon HD 3400 Series,
>	ATI Radeon HD 3450, ATI Radeon HD 3450, ATI Radeon HD 3430,
>	ATI Radeon HD 3450, ATI FirePro V3700, ATI FireMV 2450,
>	ATI FireMV 2260, ATI FireMV 2260, ATI Radeon HD 3600 Series,
>	ATI Radeon HD 3650 AGP, ATI Radeon HD 3600 PRO,
>	ATI Radeon HD 3600 XT, ATI Radeon HD 3600 PRO,
>	ATI Mobility Radeon HD 3650, ATI Mobility Radeon HD 3670,
>	ATI Mobility FireGL V5700, ATI Mobility FireGL V5725,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3200 Graphics, ATI Radeon 3100 Graphics,
>	ATI Radeon HD 3300 Graphics, ATI Radeon HD 3200 Graphics,
>	ATI Radeon 3000 Graphics, ATI Radeon HD 4200, ATI Radeon 4100,
>	ATI Mobility Radeon HD 4200, ATI Mobility Radeon 4100,
>	ATI Radeon HD 4290, ATI Radeon HD 4250, AMD Radeon HD 6310 Graphics,
>	AMD Radeon HD 6310 Graphics, AMD Radeon HD 6250 Graphics,
>	AMD Radeon HD 6250 Graphics, AMD Radeon HD 6300 Series Graphics,
>	AMD Radeon HD 6200 Series Graphics, CYPRESS,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, AMD Firestream 9370,
>	AMD Firestream 9350, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5800 Series,
>	ATI Radeon HD 5800 Series, ATI Radeon HD 5900 Series,
>	ATI Radeon HD 5900 Series, ATI Mobility Radeon HD 5800 Series,
>	ATI Mobility Radeon HD 5800 Series,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI Mobility Radeon HD 5800 Series, ATI Radeon HD 5700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Radeon HD 5700 Series, ATI Radeon HD 6700 Series,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon HD 5570,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI Radeon HD 5670,
>	ATI Radeon HD 5570, ATI Radeon HD 5500 Series, REDWOOD,
>	ATI Mobility Radeon HD 5000 Series,
>	ATI Mobility Radeon HD 5000 Series, ATI Mobility Radeon Graphics,
>	ATI Mobility Radeon Graphics, CEDAR,
>	ATI FirePro (FireGL) Graphics Adapter,
>	ATI FirePro (FireGL) Graphics Adapter, ATI FirePro 2270, CEDAR,
>	ATI Radeon HD 5450, CEDAR, CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN,
>	CAYMAN, CAYMAN, CAYMAN, CAYMAN, CAYMAN, AMD Radeon HD 6900 Series,
>	AMD Radeon HD 6900 Series, CAYMAN, CAYMAN, CAYMAN,
>	AMD Radeon HD 6900M Series, Mobility Radeon HD 6000 Series, BARTS,
>	BARTS, Mobility Radeon HD 6000 Series,
>	Mobility Radeon HD 6000 Series, BARTS, BARTS, BARTS, BARTS,
>	AMD Radeon HD 6800 Series, AMD Radeon HD 6800 Series,
>	AMD Radeon HD 6700 Series, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS,
>	TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, TURKS, CAICOS, CAICOS,
>	CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS, CAICOS,
>	CAICOS
>[    21.307] (++) using VT number 7
>
>[    21.310] (II) Loading /usr/lib/xorg/modules/drivers/radeon_drv.so
>[    21.310] (II) [KMS] Kernel modesetting enabled.
>[    21.310] (II) RADEON(0): RADEONPreInit_KMS
>[    21.311] (II) RADEON(0): Creating default Display subsection in Screen section
>	"Default Screen Section" for depth/fbbpp 24/32
>[    21.311] (==) RADEON(0): Depth 24, (--) framebuffer bpp 32
>[    21.311] (II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps)
>[    21.311] (==) RADEON(0): Default visual is TrueColor
>[    21.311] (==) RADEON(0): RGB weight 888
>[    21.311] (II) RADEON(0): Using 8 bits per RGB (8 bit DAC)
>[    21.311] (--) RADEON(0): Chipset: "ATI Mobility Radeon HD 5000 Series" (ChipID = 0x68e0)
>[    21.311] (II) RADEON(0): PCIE card detected
>[    21.311] drmOpenDevice: node name is /dev/dri/card0
>[    21.312] drmOpenDevice: open result is 8, (OK)
>[    21.312] drmOpenByBusid: Searching for BusID pci:0000:01:00.0
>[    21.312] drmOpenDevice: node name is /dev/dri/card0
>[    21.312] drmOpenDevice: open result is 8, (OK)
>[    21.312] drmOpenByBusid: drmOpenMinor returns 8
>[    21.312] drmOpenByBusid: drmGetBusid reports pci:0000:01:00.0
>[    21.312] (II) Loading sub module "exa"
>[    21.312] (II) LoadModule: "exa"
>[    21.312] (II) Loading /usr/lib/xorg/modules/libexa.so
>[    21.324] (II) Module exa: vendor="X.Org Foundation"
>[    21.324] 	compiled for 1.10.4, module version = 2.5.0
>[    21.324] 	ABI class: X.Org Video Driver, version 10.0
>[    21.324] (II) RADEON(0): KMS Color Tiling: disabled
>[    21.324] (II) RADEON(0): KMS Pageflipping: enabled
>[    21.324] (II) RADEON(0): SwapBuffers wait for vsync: enabled
>[    21.360] (II) RADEON(0): Output LVDS has no monitor section
>[    21.364] (II) RADEON(0): Output HDMI-0 has no monitor section
>[    21.387] (II) RADEON(0): Output VGA-0 has no monitor section
>[    21.407] (II) RADEON(0): EDID for output LVDS
>[    21.407] (II) RADEON(0): Printing probed modes for output LVDS
>[    21.407] (II) RADEON(0): Modeline "1366x768"x60.0   65.10  1366 1382 1390 1398  768 771 775 776 -vsync (46.6 kHz)
>[    21.407] (II) RADEON(0): Modeline "1280x720"x59.9   74.50  1280 1344 1472 1664  720 723 728 748 -hsync +vsync (44.8 kHz)
>[    21.407] (II) RADEON(0): Modeline "1152x768"x59.8   71.75  1152 1216 1328 1504  768 771 781 798 -hsync +vsync (47.7 kHz)
>[    21.407] (II) RADEON(0): Modeline "1024x768"x59.9   63.50  1024 1072 1176 1328  768 771 775 798 -hsync +vsync (47.8 kHz)
>[    21.407] (II) RADEON(0): Modeline "800x600"x59.9   38.25  800 832 912 1024  600 603 607 624 -hsync +vsync (37.4 kHz)
>[    21.407] (II) RADEON(0): Modeline "848x480"x59.7   31.50  848 872 952 1056  480 483 493 500 -hsync +vsync (29.8 kHz)
>[    21.407] (II) RADEON(0): Modeline "720x480"x59.7   26.75  720 744 808 896  480 483 493 500 -hsync +vsync (29.9 kHz)
>[    21.407] (II) RADEON(0): Modeline "640x480"x59.4   23.75  640 664 720 800  480 483 487 500 -hsync +vsync (29.7 kHz)
>[    21.412] (II) RADEON(0): EDID for output HDMI-0
>[    21.433] (II) RADEON(0): EDID for output VGA-0
>[    21.433] (II) RADEON(0): Output LVDS connected
>[    21.434] (II) RADEON(0): Output HDMI-0 disconnected
>[    21.434] (II) RADEON(0): Output VGA-0 disconnected
>[    21.434] (II) RADEON(0): Using exact sizes for initial modes
>[    21.434] (II) RADEON(0): Output LVDS using initial mode 1366x768
>[    21.434] (II) RADEON(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
>[    21.434] (II) RADEON(0): mem size init: gart size :1fdff000 vram size: s:20000000 visible:fba0000
>[    21.434] (II) RADEON(0): EXA: Driver will allow EXA pixmaps in VRAM
>[    21.434] (==) RADEON(0): DPI set to (96, 96)
>[    21.434] (II) Loading sub module "fb"
>[    21.434] (II) LoadModule: "fb"
>[    21.434] (II) Loading /usr/lib/xorg/modules/libfb.so
>[    21.445] (II) Module fb: vendor="X.Org Foundation"
>[    21.445] 	compiled for 1.10.4, module version = 1.0.0
>[    21.445] 	ABI class: X.Org ANSI C Emulation, version 0.4
>[    21.445] (II) Loading sub module "ramdac"
>[    21.445] (II) LoadModule: "ramdac"
>[    21.445] (II) Module "ramdac" already built-in
>[    21.445] (--) Depth 24 pixmap format is 32 bpp
>[    21.445] (II) RADEON(0): [DRI2] Setup complete
>[    21.445] (II) RADEON(0): [DRI2]   DRI driver: r600
>[    21.445] (II) RADEON(0): Front buffer size: 4224K
>[    21.445] (II) RADEON(0): VRAM usage limit set to 228096K
>[    21.448] (II) RADEON(0): Initializing backing store
>[    21.448] (==) RADEON(0): Backing store disabled
>[    21.448] (II) RADEON(0): Direct rendering enabled
>[    21.448] (II) RADEON(0): Initializing Acceleration
>[    21.460] (II) RADEON(0): Setting EXA maxPitchBytes
>[    21.460] (II) EXA(0): Driver allocated offscreen pixmaps
>[    21.460] (II) EXA(0): Driver registered support for the following operations:
>[    21.460] (II)         Solid
>[    21.460] (II)         Copy
>[    21.460] (II)         Composite (RENDER acceleration)
>[    21.460] (II)         UploadToScreen
>[    21.460] (II)         DownloadFromScreen
>[    21.460] (II) RADEON(0): Acceleration enabled
>[    21.460] (II) RADEON(0): Initializing DPMS
>[    21.460] (==) RADEON(0): DPMS enabled
>[    21.460] (II) RADEON(0): Initializing Cursor
>[    21.460] (==) RADEON(0): Silken mouse enabled
>[    21.461] (II) RADEON(0): Initializing Xv
>[    21.468] (II) RADEON(0): Set up textured video
>[    21.468] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>[    21.468] (II) RADEON(0): Initializing kms color map
>[    21.468] (II) RADEON(0): RADEONScreenInit finished
>[    21.468] (--) RandR disabled
>[    21.468] (II) Initializing built-in extension Generic Event Extension
>[    21.468] (II) Initializing built-in extension SHAPE
>[    21.468] (II) Initializing built-in extension MIT-SHM
>[    21.468] (II) Initializing built-in extension XInputExtension
>[    21.469] (II) Initializing built-in extension XTEST
>[    21.469] (II) Initializing built-in extension BIG-REQUESTS
>[    21.469] (II) Initializing built-in extension SYNC
>[    21.469] (II) Initializing built-in extension XKEYBOARD
>[    21.469] (II) Initializing built-in extension XC-MISC
>[    21.469] (II) Initializing built-in extension SECURITY
>[    21.469] (II) Initializing built-in extension XINERAMA
>[    21.469] (II) Initializing built-in extension XFIXES
>[    21.469] (II) Initializing built-in extension RENDER
>[    21.469] (II) Initializing built-in extension RANDR
>[    21.469] (II) Initializing built-in extension COMPOSITE
>[    21.469] (II) Initializing built-in extension DAMAGE
>[    21.921] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer
>[    21.921] (II) AIGLX: enabled GLX_INTEL_swap_event
>[    21.921] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control
>[    21.921] (II) AIGLX: enabled GLX_SGI_make_current_read
>[    21.921] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects
>[    21.921] (II) AIGLX: Loaded and initialized /usr/lib/xorg/modules/dri/r600_dri.so
>[    21.921] (II) GLX: Initialized DRI2 GL provider for screen 0
>[    21.944] (II) RADEON(0): Setting screen physical size to 361 x 203
>[    22.258] (II) XKB: Reusing cached keymap
>[    22.274] (II) config/udev: Adding input device Power Button (/dev/input/event4)
>[    22.274] (**) Power Button: Applying InputClass "evdev keyboard catchall"
>[    22.274] (II) LoadModule: "evdev"
>[    22.274] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>[    22.282] (II) Module evdev: vendor="X.Org Foundation"
>[    22.282] 	compiled for 1.10.0, module version = 2.6.0
>[    22.282] 	Module class: X.Org XInput Driver
>[    22.282] 	ABI class: X.Org XInput driver, version 12.2
>[    22.282] (II) Using input driver 'evdev' for 'Power Button'
>[    22.282] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>[    22.283] 	Option "XkbRules" "evdev"
>[    22.283] 	Option "XkbModel" "evdev"
>[    22.283] 	Option "xkb_layout" "fr"
>[    22.283] 	Option "_source" "server/udev"
>[    22.283] 	Option "name" "Power Button"
>[    22.283] 	Option "path" "/dev/input/event4"
>[    22.283] 	Option "device" "/dev/input/event4"
>[    22.283] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input4/event4"
>[    22.283] 	Option "xkb_variant" "latin9"
>[    22.283] 	Option "xkb_options" "lv3:ralt_switch"
>[    22.283] 	Option "driver" "evdev"
>[    22.283] (**) Power Button: always reports core events
>[    22.283] (**) Power Button: Device: "/dev/input/event4"
>[    22.283] (--) Power Button: Found keys
>[    22.283] (II) Power Button: Configuring as keyboard
>[    22.283] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input4/event4"
>[    22.283] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD)
>[    22.283] (**) Option "xkb_rules" "evdev"
>[    22.283] (**) Option "xkb_model" "evdev"
>[    22.283] (**) Option "xkb_layout" "fr"
>[    22.283] (**) Option "xkb_variant" "latin9"
>[    22.283] (**) Option "xkb_options" "lv3:ralt_switch"
>[    22.349] (II) config/udev: Adding input device Video Bus (/dev/input/event5)
>[    22.349] (**) Video Bus: Applying InputClass "evdev keyboard catchall"
>[    22.349] (II) Using input driver 'evdev' for 'Video Bus'
>[    22.349] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>[    22.349] 	Option "XkbRules" "evdev"
>[    22.349] 	Option "XkbModel" "evdev"
>[    22.349] 	Option "xkb_layout" "fr"
>[    22.349] 	Option "_source" "server/udev"
>[    22.349] 	Option "name" "Video Bus"
>[    22.349] 	Option "path" "/dev/input/event5"
>[    22.349] 	Option "device" "/dev/input/event5"
>[    22.349] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0A08:00/device:01/LNXVIDEO:00/input/input5/event5"
>[    22.349] 	Option "xkb_variant" "latin9"
>[    22.349] 	Option "xkb_options" "lv3:ralt_switch"
>[    22.349] 	Option "driver" "evdev"
>[    22.349] (**) Video Bus: always reports core events
>[    22.349] (**) Video Bus: Device: "/dev/input/event5"
>[    22.349] (--) Video Bus: Found keys
>[    22.350] (II) Video Bus: Configuring as keyboard
>[    22.350] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0A08:00/device:01/LNXVIDEO:00/input/input5/event5"
>[    22.350] (II) XINPUT: Adding extended input device "Video Bus" (type: KEYBOARD)
>[    22.350] (**) Option "xkb_rules" "evdev"
>[    22.350] (**) Option "xkb_model" "evdev"
>[    22.350] (**) Option "xkb_layout" "fr"
>[    22.350] (**) Option "xkb_variant" "latin9"
>[    22.350] (**) Option "xkb_options" "lv3:ralt_switch"
>[    22.350] (II) XKB: Reusing cached keymap
>[    22.361] (II) config/udev: Adding input device Power Button (/dev/input/event1)
>[    22.361] (**) Power Button: Applying InputClass "evdev keyboard catchall"
>[    22.361] (II) Using input driver 'evdev' for 'Power Button'
>[    22.361] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>[    22.361] 	Option "XkbRules" "evdev"
>[    22.361] 	Option "XkbModel" "evdev"
>[    22.361] 	Option "xkb_layout" "fr"
>[    22.361] 	Option "_source" "server/udev"
>[    22.361] 	Option "name" "Power Button"
>[    22.361] 	Option "path" "/dev/input/event1"
>[    22.361] 	Option "device" "/dev/input/event1"
>[    22.361] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input1/event1"
>[    22.361] 	Option "xkb_variant" "latin9"
>[    22.361] 	Option "xkb_options" "lv3:ralt_switch"
>[    22.361] 	Option "driver" "evdev"
>[    22.361] (**) Power Button: always reports core events
>[    22.361] (**) Power Button: Device: "/dev/input/event1"
>[    22.361] (--) Power Button: Found keys
>[    22.361] (II) Power Button: Configuring as keyboard
>[    22.361] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input1/event1"
>[    22.361] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD)
>[    22.361] (**) Option "xkb_rules" "evdev"
>[    22.361] (**) Option "xkb_model" "evdev"
>[    22.362] (**) Option "xkb_layout" "fr"
>[    22.362] (**) Option "xkb_variant" "latin9"
>[    22.362] (**) Option "xkb_options" "lv3:ralt_switch"
>[    22.362] (II) XKB: Reusing cached keymap
>[    22.362] (II) config/udev: Adding input device Lid Switch (/dev/input/event2)
>[    22.363] (II) No input driver/identifier specified (ignoring)
>[    22.363] (II) config/udev: Adding input device Sleep Button (/dev/input/event3)
>[    22.363] (**) Sleep Button: Applying InputClass "evdev keyboard catchall"
>[    22.363] (II) Using input driver 'evdev' for 'Sleep Button'
>[    22.363] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>[    22.363] 	Option "XkbRules" "evdev"
>[    22.363] 	Option "XkbModel" "evdev"
>[    22.363] 	Option "xkb_layout" "fr"
>[    22.363] 	Option "_source" "server/udev"
>[    22.363] 	Option "name" "Sleep Button"
>[    22.363] 	Option "path" "/dev/input/event3"
>[    22.363] 	Option "device" "/dev/input/event3"
>[    22.363] 	Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input3/event3"
>[    22.363] 	Option "xkb_variant" "latin9"
>[    22.363] 	Option "xkb_options" "lv3:ralt_switch"
>[    22.363] 	Option "driver" "evdev"
>[    22.363] (**) Sleep Button: always reports core events
>[    22.363] (**) Sleep Button: Device: "/dev/input/event3"
>[    22.363] (--) Sleep Button: Found keys
>[    22.364] (II) Sleep Button: Configuring as keyboard
>[    22.364] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input3/event3"
>[    22.364] (II) XINPUT: Adding extended input device "Sleep Button" (type: KEYBOARD)
>[    22.364] (**) Option "xkb_rules" "evdev"
>[    22.364] (**) Option "xkb_model" "evdev"
>[    22.364] (**) Option "xkb_layout" "fr"
>[    22.364] (**) Option "xkb_variant" "latin9"
>[    22.364] (**) Option "xkb_options" "lv3:ralt_switch"
>[    22.364] (II) XKB: Reusing cached keymap
>[    22.367] (II) config/udev: Adding input device HD-Audio Generic HDMI/DP (/dev/input/event10)
>[    22.367] (II) No input driver/identifier specified (ignoring)
>[    22.370] (II) config/udev: Adding input device Microsoft Basic Optical Mouse (/dev/input/event12)
>[    22.370] (**) Microsoft Basic Optical Mouse: Applying InputClass "evdev pointer catchall"
>[    22.370] (II) Using input driver 'evdev' for 'Microsoft Basic Optical Mouse'
>[    22.370] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>[    22.370] 	Option "XkbRules" "evdev"
>[    22.370] 	Option "XkbModel" "evdev"
>[    22.370] 	Option "XkbLayout" "us"
>[    22.370] 	Option "_source" "server/udev"
>[    22.370] 	Option "name" "Microsoft Basic Optical Mouse"
>[    22.370] 	Option "path" "/dev/input/event12"
>[    22.370] 	Option "device" "/dev/input/event12"
>[    22.370] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.0/input/input12/event12"
>[    22.370] 	Option "driver" "evdev"
>[    22.370] (**) Microsoft Basic Optical Mouse: always reports core events
>[    22.370] (**) Microsoft Basic Optical Mouse: Device: "/dev/input/event12"
>[    22.370] (--) Microsoft Basic Optical Mouse: Found 3 mouse buttons
>[    22.370] (--) Microsoft Basic Optical Mouse: Found scroll wheel(s)
>[    22.370] (--) Microsoft Basic Optical Mouse: Found relative axes
>[    22.370] (--) Microsoft Basic Optical Mouse: Found x and y relative axes
>[    22.370] (II) Microsoft Basic Optical Mouse: Configuring as mouse
>[    22.370] (II) Microsoft Basic Optical Mouse: Adding scrollwheel support
>[    22.370] (**) Microsoft Basic Optical Mouse: YAxisMapping: buttons 4 and 5
>[    22.370] (**) Microsoft Basic Optical Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>[    22.370] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.0/input/input12/event12"
>[    22.370] (II) XINPUT: Adding extended input device "Microsoft Basic Optical Mouse" (type: MOUSE)
>[    22.370] (II) Microsoft Basic Optical Mouse: initialized for relative axes.
>[    22.370] (**) Microsoft Basic Optical Mouse: (accel) keeping acceleration scheme 1
>[    22.370] (**) Microsoft Basic Optical Mouse: (accel) acceleration profile 0
>[    22.370] (**) Microsoft Basic Optical Mouse: (accel) acceleration factor: 2.000
>[    22.370] (**) Microsoft Basic Optical Mouse: (accel) acceleration threshold: 4
>[    22.370] (II) config/udev: Adding input device Microsoft Basic Optical Mouse (/dev/input/mouse1)
>[    22.370] (II) No input driver/identifier specified (ignoring)
>[    22.371] (II) config/udev: Adding input device Laptop_Integrated_Webcam_1.3M (/dev/input/event15)
>[    22.371] (**) Laptop_Integrated_Webcam_1.3M: Applying InputClass "evdev keyboard catchall"
>[    22.371] (II) Using input driver 'evdev' for 'Laptop_Integrated_Webcam_1.3M'
>[    22.371] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>[    22.371] 	Option "XkbRules" "evdev"
>[    22.371] 	Option "XkbModel" "evdev"
>[    22.371] 	Option "xkb_layout" "fr"
>[    22.371] 	Option "_source" "server/udev"
>[    22.371] 	Option "name" "Laptop_Integrated_Webcam_1.3M"
>[    22.371] 	Option "path" "/dev/input/event15"
>[    22.371] 	Option "device" "/dev/input/event15"
>[    22.371] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.6/1-1.6:1.0/input/input15/event15"
>[    22.371] 	Option "xkb_variant" "latin9"
>[    22.371] 	Option "xkb_options" "lv3:ralt_switch"
>[    22.371] 	Option "driver" "evdev"
>[    22.371] (**) Laptop_Integrated_Webcam_1.3M: always reports core events
>[    22.371] (**) Laptop_Integrated_Webcam_1.3M: Device: "/dev/input/event15"
>[    22.371] (--) Laptop_Integrated_Webcam_1.3M: Found keys
>[    22.371] (II) Laptop_Integrated_Webcam_1.3M: Configuring as keyboard
>[    22.371] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.6/1-1.6:1.0/input/input15/event15"
>[    22.371] (II) XINPUT: Adding extended input device "Laptop_Integrated_Webcam_1.3M" (type: KEYBOARD)
>[    22.371] (**) Option "xkb_rules" "evdev"
>[    22.371] (**) Option "xkb_model" "evdev"
>[    22.371] (**) Option "xkb_layout" "fr"
>[    22.371] (**) Option "xkb_variant" "latin9"
>[    22.371] (**) Option "xkb_options" "lv3:ralt_switch"
>[    22.371] (II) XKB: Reusing cached keymap
>[    22.372] (II) config/udev: Adding input device HDA Digital PCBeep (/dev/input/event7)
>[    22.372] (II) No input driver/identifier specified (ignoring)
>[    22.372] (II) config/udev: Adding input device HDA Intel Mic at Ext Left Jack (/dev/input/event8)
>[    22.372] (II) No input driver/identifier specified (ignoring)
>[    22.372] (II) config/udev: Adding input device HDA Intel HP Out at Ext Left Jack (/dev/input/event9)
>[    22.372] (II) No input driver/identifier specified (ignoring)
>[    22.374] (II) config/udev: Adding input device HID 413c:8161 (/dev/input/event13)
>[    22.374] (**) HID 413c:8161: Applying InputClass "evdev keyboard catchall"
>[    22.374] (II) Using input driver 'evdev' for 'HID 413c:8161'
>[    22.374] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>[    22.374] 	Option "XkbRules" "evdev"
>[    22.374] 	Option "XkbModel" "evdev"
>[    22.374] 	Option "xkb_layout" "fr"
>[    22.374] 	Option "_source" "server/udev"
>[    22.374] 	Option "name" "HID 413c:8161"
>[    22.374] 	Option "path" "/dev/input/event13"
>[    22.374] 	Option "device" "/dev/input/event13"
>[    22.374] 	Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.6/2-1.6.1/2-1.6.1:1.0/input/input13/event13"
>[    22.374] 	Option "xkb_variant" "latin9"
>[    22.374] 	Option "xkb_options" "lv3:ralt_switch"
>[    22.374] 	Option "driver" "evdev"
>[    22.374] (**) HID 413c:8161: always reports core events
>[    22.374] (**) HID 413c:8161: Device: "/dev/input/event13"
>[    22.374] (--) HID 413c:8161: Found keys
>[    22.374] (II) HID 413c:8161: Configuring as keyboard
>[    22.374] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.6/2-1.6.1/2-1.6.1:1.0/input/input13/event13"
>[    22.374] (II) XINPUT: Adding extended input device "HID 413c:8161" (type: KEYBOARD)
>[    22.374] (**) Option "xkb_rules" "evdev"
>[    22.374] (**) Option "xkb_model" "evdev"
>[    22.374] (**) Option "xkb_layout" "fr"
>[    22.374] (**) Option "xkb_variant" "latin9"
>[    22.374] (**) Option "xkb_options" "lv3:ralt_switch"
>[    22.374] (II) XKB: Reusing cached keymap
>[    22.379] (II) config/udev: Adding input device AT Translated Set 2 keyboard (/dev/input/event0)
>[    22.379] (**) AT Translated Set 2 keyboard: Applying InputClass "evdev keyboard catchall"
>[    22.379] (II) Using input driver 'evdev' for 'AT Translated Set 2 keyboard'
>[    22.379] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>[    22.379] 	Option "XkbRules" "evdev"
>[    22.379] 	Option "XkbModel" "evdev"
>[    22.379] 	Option "xkb_layout" "fr"
>[    22.379] 	Option "_source" "server/udev"
>[    22.379] 	Option "name" "AT Translated Set 2 keyboard"
>[    22.379] 	Option "path" "/dev/input/event0"
>[    22.379] 	Option "device" "/dev/input/event0"
>[    22.379] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input0/event0"
>[    22.379] 	Option "xkb_variant" "latin9"
>[    22.379] 	Option "xkb_options" "lv3:ralt_switch"
>[    22.379] 	Option "driver" "evdev"
>[    22.379] (**) AT Translated Set 2 keyboard: always reports core events
>[    22.379] (**) AT Translated Set 2 keyboard: Device: "/dev/input/event0"
>[    22.379] (--) AT Translated Set 2 keyboard: Found keys
>[    22.379] (II) AT Translated Set 2 keyboard: Configuring as keyboard
>[    22.379] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio0/input/input0/event0"
>[    22.379] (II) XINPUT: Adding extended input device "AT Translated Set 2 keyboard" (type: KEYBOARD)
>[    22.379] (**) Option "xkb_rules" "evdev"
>[    22.379] (**) Option "xkb_model" "evdev"
>[    22.379] (**) Option "xkb_layout" "fr"
>[    22.379] (**) Option "xkb_variant" "latin9"
>[    22.379] (**) Option "xkb_options" "lv3:ralt_switch"
>[    22.379] (II) XKB: Reusing cached keymap
>[    22.380] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/event11)
>[    22.380] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "evdev touchpad catchall"
>[    22.380] (**) SynPS/2 Synaptics TouchPad: Applying InputClass "touchpad catchall"
>[    22.380] (II) LoadModule: "synaptics"
>[    22.380] (II) Loading /usr/lib/xorg/modules/input/synaptics_drv.so
>[    22.385] (II) Module synaptics: vendor="X.Org Foundation"
>[    22.385] 	compiled for 1.10.2, module version = 1.4.1
>[    22.386] 	Module class: X.Org XInput Driver
>[    22.386] 	ABI class: X.Org XInput driver, version 12.2
>[    22.386] (II) Using input driver 'synaptics' for 'SynPS/2 Synaptics TouchPad'
>[    22.386] (II) Loading /usr/lib/xorg/modules/input/synaptics_drv.so
>[    22.386] 	Option "_source" "server/udev"
>[    22.386] 	Option "name" "SynPS/2 Synaptics TouchPad"
>[    22.386] 	Option "path" "/dev/input/event11"
>[    22.386] 	Option "device" "/dev/input/event11"
>[    22.386] 	Option "config_info" "udev:/sys/devices/platform/i8042/serio1/input/input11/event11"
>[    22.386] 	Option "driver" "synaptics"
>[    22.386] 	Option "TapButton1" "1"
>[    22.386] 	Option "TapButton2" "2"
>[    22.386] 	Option "TapButton3" "3"
>[    22.386] (**) SynPS/2 Synaptics TouchPad: always reports core events
>[    22.386] (**) Option "Device" "/dev/input/event11"
>[    22.386] (**) Option "Device" "/dev/input/event11"
>[    22.386] port opened successfully
>[    22.480] (--) SynPS/2 Synaptics TouchPad: x-axis range 1472 - 5650
>[    22.480] (--) SynPS/2 Synaptics TouchPad: y-axis range 1408 - 4710
>[    22.480] (--) SynPS/2 Synaptics TouchPad: pressure range 0 - 255
>[    22.480] (--) SynPS/2 Synaptics TouchPad: finger width range 0 - 15
>[    22.480] (--) SynPS/2 Synaptics TouchPad: buttons: left right double triple
>[    22.480] (**) Option "TapButton1" "1"
>[    22.480] (**) Option "TapButton2" "2"
>[    22.480] (**) Option "TapButton3" "3"
>[    22.586] (--) SynPS/2 Synaptics TouchPad: touchpad found
>[    22.586] (**) SynPS/2 Synaptics TouchPad: always reports core events
>[    22.693] (**) Option "config_info" "udev:/sys/devices/platform/i8042/serio1/input/input11/event11"
>[    22.693] (II) XINPUT: Adding extended input device "SynPS/2 Synaptics TouchPad" (type: TOUCHPAD)
>[    22.693] (**) SynPS/2 Synaptics TouchPad: (accel) MinSpeed is now constant deceleration 2.5
>[    22.693] (**) SynPS/2 Synaptics TouchPad: MaxSpeed is now 1.75
>[    22.693] (**) SynPS/2 Synaptics TouchPad: AccelFactor is now 0.038
>[    22.694] (**) SynPS/2 Synaptics TouchPad: (accel) keeping acceleration scheme 1
>[    22.694] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration profile 1
>[    22.694] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration factor: 2.000
>[    22.694] (**) SynPS/2 Synaptics TouchPad: (accel) acceleration threshold: 4
>[    22.694] (**) Option "Device" "/dev/input/event11"
>[    22.694] (**) Option "Device" "/dev/input/event11"
>[    22.694] (--) SynPS/2 Synaptics TouchPad: touchpad found
>[    22.694] (II) config/udev: Adding input device SynPS/2 Synaptics TouchPad (/dev/input/mouse0)
>[    22.694] (II) No input driver/identifier specified (ignoring)
>[    22.697] (II) config/udev: Adding input device Dell WMI hotkeys (/dev/input/event6)
>[    22.697] (**) Dell WMI hotkeys: Applying InputClass "evdev keyboard catchall"
>[    22.697] (II) Using input driver 'evdev' for 'Dell WMI hotkeys'
>[    22.697] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>[    22.697] 	Option "XkbRules" "evdev"
>[    22.697] 	Option "XkbModel" "evdev"
>[    22.697] 	Option "xkb_layout" "fr"
>[    22.697] 	Option "_source" "server/udev"
>[    22.697] 	Option "name" "Dell WMI hotkeys"
>[    22.697] 	Option "path" "/dev/input/event6"
>[    22.697] 	Option "device" "/dev/input/event6"
>[    22.697] 	Option "config_info" "udev:/sys/devices/virtual/input/input6/event6"
>[    22.697] 	Option "xkb_variant" "latin9"
>[    22.697] 	Option "xkb_options" "lv3:ralt_switch"
>[    22.697] 	Option "driver" "evdev"
>[    22.697] (**) Dell WMI hotkeys: always reports core events
>[    22.697] (**) Dell WMI hotkeys: Device: "/dev/input/event6"
>[    22.697] (--) Dell WMI hotkeys: Found keys
>[    22.697] (II) Dell WMI hotkeys: Configuring as keyboard
>[    22.697] (**) Option "config_info" "udev:/sys/devices/virtual/input/input6/event6"
>[    22.697] (II) XINPUT: Adding extended input device "Dell WMI hotkeys" (type: KEYBOARD)
>[    22.697] (**) Option "xkb_rules" "evdev"
>[    22.697] (**) Option "xkb_model" "evdev"
>[    22.698] (**) Option "xkb_layout" "fr"
>[    22.698] (**) Option "xkb_variant" "latin9"
>[    22.698] (**) Option "xkb_options" "lv3:ralt_switch"
>[    22.698] (II) XKB: Reusing cached keymap
>[    22.713] (II) RADEON(0): RADEONSaveScreen(2)
>[    36.889] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03190]
>[    36.908] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03190] width 1366 pitch 5632 (/4 1408)
>[    36.915] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1aeaa30]
>[    36.941] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1aeaa30] width 1366 pitch 5632 (/4 1408)
>[    36.976] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03190]
>[    36.991] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03190] width 1366 pitch 5632 (/4 1408)
>[    37.092] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1aeaa30]
>[    37.108] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1aeaa30] width 1366 pitch 5632 (/4 1408)
>[    37.112] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03190]
>[    37.125] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03190] width 1366 pitch 5632 (/4 1408)
>[    39.826] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03260]
>[    39.841] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03260] width 1366 pitch 5632 (/4 1408)
>[    39.993] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03200]
>[    40.008] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03200] width 1366 pitch 5632 (/4 1408)
>[    40.015] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03260]
>[    40.041] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03260] width 1366 pitch 5632 (/4 1408)
>[    40.045] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03200]
>[    40.058] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03200] width 1366 pitch 5632 (/4 1408)
>[    40.062] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03260]
>[    40.074] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03260] width 1366 pitch 5632 (/4 1408)
>[    40.078] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03200]
>[    40.091] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03200] width 1366 pitch 5632 (/4 1408)
>[    40.095] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03260]
>[    40.108] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03260] width 1366 pitch 5632 (/4 1408)
>[    40.112] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03200]
>[    40.124] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03200] width 1366 pitch 5632 (/4 1408)
>[    40.128] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03260]
>[    40.141] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03260] width 1366 pitch 5632 (/4 1408)
>[    40.145] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03200]
>[    40.158] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03200] width 1366 pitch 5632 (/4 1408)
>[    40.164] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03260]
>[    40.191] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03260] width 1366 pitch 5632 (/4 1408)
>[    40.358] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03200]
>[    40.374] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03200] width 1366 pitch 5632 (/4 1408)
>[    40.385] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03260]
>[    40.408] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03260] width 1366 pitch 5632 (/4 1408)
>[    40.412] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03200]
>[    40.424] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03200] width 1366 pitch 5632 (/4 1408)
>[    40.429] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03260]
>[    40.441] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03260] width 1366 pitch 5632 (/4 1408)
>[    40.445] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03200]
>[    40.458] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03200] width 1366 pitch 5632 (/4 1408)
>[    40.462] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03260]
>[    40.474] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03260] width 1366 pitch 5632 (/4 1408)
>[    40.479] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03200]
>[    40.491] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03200] width 1366 pitch 5632 (/4 1408)
>[    40.496] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03260]
>[    40.508] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03260] width 1366 pitch 5632 (/4 1408)
>[    40.513] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03200]
>[    40.524] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03200] width 1366 pitch 5632 (/4 1408)
>[    50.154] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b23680]
>[    50.173] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b23680] width 1366 pitch 5632 (/4 1408)
>[    50.569] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b23620]
>[    50.589] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b23620] width 1366 pitch 5632 (/4 1408)
>[    50.603] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b23680]
>[    50.623] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b23680] width 1366 pitch 5632 (/4 1408)
>[    50.626] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b23620]
>[    50.640] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b23620] width 1366 pitch 5632 (/4 1408)
>[    50.827] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b23680]
>[    50.839] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b23680] width 1366 pitch 5632 (/4 1408)
>[    54.467] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b432d0]
>[    54.489] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b432d0] width 1366 pitch 5632 (/4 1408)
>[    79.591] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f240]
>[    79.602] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f240] width 1366 pitch 5632 (/4 1408)
>[    79.733] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4ecc0]
>[    79.735] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4ecc0] width 1366 pitch 5632 (/4 1408)
>[    79.763] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f240]
>[    79.769] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f240] width 1366 pitch 5632 (/4 1408)
>[    79.941] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4ecc0]
>[    79.952] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4ecc0] width 1366 pitch 5632 (/4 1408)
>[    80.500] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f240]
>[    80.502] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f240] width 1366 pitch 5632 (/4 1408)
>[    80.622] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4ecc0]
>[    80.652] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4ecc0] width 1366 pitch 5632 (/4 1408)
>[    80.803] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f240]
>[    80.819] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f240] width 1366 pitch 5632 (/4 1408)
>[    83.344] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f110]
>[    83.352] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f110] width 1366 pitch 5632 (/4 1408)
>[    83.609] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4feb0]
>[    83.618] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4feb0] width 1366 pitch 5632 (/4 1408)
>[    84.393] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4ffc0]
>[    84.401] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4ffc0] width 1366 pitch 5632 (/4 1408)
>[    84.521] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f0b0]
>[    84.535] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f0b0] width 1366 pitch 5632 (/4 1408)
>[    86.211] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4ffc0]
>[    86.218] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4ffc0] width 1366 pitch 5632 (/4 1408)
>[    86.759] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f0b0]
>[    86.768] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f0b0] width 1366 pitch 5632 (/4 1408)
>[    86.872] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4ffc0]
>[    86.901] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4ffc0] width 1366 pitch 5632 (/4 1408)
>[    87.927] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f0b0]
>[    87.951] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f0b0] width 1366 pitch 5632 (/4 1408)
>[    98.972] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4ec50]
>[    98.983] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4ec50] width 1366 pitch 5632 (/4 1408)
>[    99.116] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4ec50]
>[    99.116] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4ec50] width 1366 pitch 5632 (/4 1408)
>[    99.554] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f8d0]
>[    99.566] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f8d0] width 1366 pitch 5632 (/4 1408)
>[    99.670] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4ec50]
>[    99.699] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4ec50] width 1366 pitch 5632 (/4 1408)
>[    99.776] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f8d0]
>[    99.799] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f8d0] width 1366 pitch 5632 (/4 1408)
>[   100.395] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4ec50]
>[   100.399] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4ec50] width 1366 pitch 5632 (/4 1408)
>[   100.554] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f8d0]
>[   100.566] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f8d0] width 1366 pitch 5632 (/4 1408)
>[   100.929] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4ec50]
>[   100.932] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4ec50] width 1366 pitch 5632 (/4 1408)
>[   101.054] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f8d0]
>[   101.082] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f8d0] width 1366 pitch 5632 (/4 1408)
>[   101.094] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4ec50]
>[   101.116] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4ec50] width 1366 pitch 5632 (/4 1408)
>[   140.399] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b513a0]
>[   140.410] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b513a0] width 1366 pitch 5632 (/4 1408)
>[   140.472] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b515c0]
>[   140.494] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b515c0] width 1366 pitch 5632 (/4 1408)
>[   140.538] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f620]
>[   140.544] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f620] width 1366 pitch 5632 (/4 1408)
>[   140.678] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b515c0]
>[   140.694] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b515c0] width 1366 pitch 5632 (/4 1408)
>[   141.067] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f620]
>[   141.094] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f620] width 1366 pitch 5632 (/4 1408)
>[   141.283] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b515c0]
>[   141.310] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b515c0] width 1366 pitch 5632 (/4 1408)
>[   141.583] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f620]
>[   141.610] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f620] width 1366 pitch 5632 (/4 1408)
>[   143.696] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b515c0]
>[   143.726] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b515c0] width 1366 pitch 5632 (/4 1408)
>[   143.855] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f620]
>[   143.876] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f620] width 1366 pitch 5632 (/4 1408)
>[   144.892] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b515c0]
>[   144.910] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b515c0] width 1366 pitch 5632 (/4 1408)
>[   145.001] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f620]
>[   145.043] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f620] width 1366 pitch 5632 (/4 1408)
>[   146.221] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b515c0]
>[   146.226] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b515c0] width 1366 pitch 5632 (/4 1408)
>[   146.231] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f620]
>[   146.259] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f620] width 1366 pitch 5632 (/4 1408)
>[   146.265] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b515c0]
>[   146.293] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b515c0] width 1366 pitch 5632 (/4 1408)
>[   146.298] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b4f620]
>[   146.326] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b4f620] width 1366 pitch 5632 (/4 1408)
>[   146.342] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b515c0]
>[   146.376] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b515c0] width 1366 pitch 5632 (/4 1408)
>[   150.157] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b5d170]
>[   150.176] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b5d170] width 1366 pitch 5632 (/4 1408)
>[   151.776] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b8b0]
>[   151.792] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b8b0] width 1366 pitch 5632 (/4 1408)
>[   159.260] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbd720]
>[   159.274] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbd720] width 1366 pitch 5632 (/4 1408)
>[   159.297] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbd900]
>[   159.308] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbd900] width 1366 pitch 5632 (/4 1408)
>[   159.327] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbd720]
>[   159.341] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbd720] width 1366 pitch 5632 (/4 1408)
>[   159.361] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbd900]
>[   159.374] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbd900] width 1366 pitch 5632 (/4 1408)
>[   159.390] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbd720]
>[   159.391] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbd720] width 1366 pitch 5632 (/4 1408)
>[   159.406] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbd900]
>[   159.424] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbd900] width 1366 pitch 5632 (/4 1408)
>[   159.435] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbd720]
>[   159.441] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbd720] width 1366 pitch 5632 (/4 1408)
>[   159.477] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbd900]
>[   159.491] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbd900] width 1366 pitch 5632 (/4 1408)
>[   160.056] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   160.074] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   160.085] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbd900]
>[   160.108] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbd900] width 1366 pitch 5632 (/4 1408)
>[   160.238] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbd900]
>[   160.257] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbd900] width 1366 pitch 5632 (/4 1408)
>[   160.539] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   160.557] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   161.035] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdda0]
>[   161.041] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdda0] width 1366 pitch 5632 (/4 1408)
>[   165.857] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb730]
>[   165.873] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb730] width 1366 pitch 5632 (/4 1408)
>[   165.884] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb860]
>[   165.890] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb860] width 1366 pitch 5632 (/4 1408)
>[   165.894] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb730]
>[   165.907] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb730] width 1366 pitch 5632 (/4 1408)
>[   165.914] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb860]
>[   165.923] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb860] width 1366 pitch 5632 (/4 1408)
>[   165.927] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb730]
>[   165.940] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb730] width 1366 pitch 5632 (/4 1408)
>[   165.944] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb860]
>[   165.957] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb860] width 1366 pitch 5632 (/4 1408)
>[   165.961] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb730]
>[   165.973] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb730] width 1366 pitch 5632 (/4 1408)
>[   165.979] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb860]
>[   165.990] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb860] width 1366 pitch 5632 (/4 1408)
>[   165.994] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb730]
>[   166.007] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb730] width 1366 pitch 5632 (/4 1408)
>[   166.010] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb860]
>[   166.023] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb860] width 1366 pitch 5632 (/4 1408)
>[   166.027] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb730]
>[   166.040] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb730] width 1366 pitch 5632 (/4 1408)
>[   166.043] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb860]
>[   166.057] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb860] width 1366 pitch 5632 (/4 1408)
>[   166.068] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb860]
>[   166.075] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb860] width 1366 pitch 5632 (/4 1408)
>[   168.816] GetModeLine - scrn: 0 clock: 65100
>[   168.816] GetModeLine - hdsp: 1366 hbeg: 1382 hend: 1390 httl: 1398
>[   168.816]               vdsp: 768 vbeg: 771 vend: 775 vttl: 776 flags: 8
>[   169.578] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b03b10]
>[   169.590] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b03b10] width 1366 pitch 5632 (/4 1408)
>[   170.821] GetModeLine - scrn: 0 clock: 65100
>[   170.821] GetModeLine - hdsp: 1366 hbeg: 1382 hend: 1390 httl: 1398
>[   170.821]               vdsp: 768 vbeg: 771 vend: 775 vttl: 776 flags: 8
>[   170.826] GetModeLine - scrn: 0 clock: 65100
>[   170.826] GetModeLine - hdsp: 1366 hbeg: 1382 hend: 1390 httl: 1398
>[   170.826]               vdsp: 768 vbeg: 771 vend: 775 vttl: 776 flags: 8
>[   170.827] GetModeLine - scrn: 0 clock: 65100
>[   170.827] GetModeLine - hdsp: 1366 hbeg: 1382 hend: 1390 httl: 1398
>[   170.827]               vdsp: 768 vbeg: 771 vend: 775 vttl: 776 flags: 8
>[   170.827] GetModeLine - scrn: 0 clock: 65100
>[   170.827] GetModeLine - hdsp: 1366 hbeg: 1382 hend: 1390 httl: 1398
>[   170.827]               vdsp: 768 vbeg: 771 vend: 775 vttl: 776 flags: 8
>[   171.130] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.139] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.145] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.156] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.161] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.173] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.177] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.189] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.193] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.206] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.209] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.222] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.225] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.239] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.241] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.256] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.273] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.273] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.289] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.290] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.306] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.308] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.323] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.324] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.339] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.341] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.356] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.357] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.373] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.374] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.389] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.391] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.406] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.407] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.423] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.424] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.439] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.440] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.456] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.457] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.473] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.474] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.489] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.491] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.506] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.508] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.523] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.524] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.539] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.541] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.556] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.559] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.573] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.574] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.589] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.591] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.606] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.608] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.623] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.625] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.639] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.641] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.656] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.658] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.673] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.674] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.693] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.696] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.706] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.708] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.723] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.724] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.739] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.741] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.756] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.758] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.772] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.774] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.789] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.791] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.806] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.808] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.822] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.824] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.839] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.841] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.856] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.858] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.872] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.874] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.889] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.891] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.906] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.908] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.922] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.924] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.939] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.941] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.956] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.958] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   171.972] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   171.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   171.989] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   171.991] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.006] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.008] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.022] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.024] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.039] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.041] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.056] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.058] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.072] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.074] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.089] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.090] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.106] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.108] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.122] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.124] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.139] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.141] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.156] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.158] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.172] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.189] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.193] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.206] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.207] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.222] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.224] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.239] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.241] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.256] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.258] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.272] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.274] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.289] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.291] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.306] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.308] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.324] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.325] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.339] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.341] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.356] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.358] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.372] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.374] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.389] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.391] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.406] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.408] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.422] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.424] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.439] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.441] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.456] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.458] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.472] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.474] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.489] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.491] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.506] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.508] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.522] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.524] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.539] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.541] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.556] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.558] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.572] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.574] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.589] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.591] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.606] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.608] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.622] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.624] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.639] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.641] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.656] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.658] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.672] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.674] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.689] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.697] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.706] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.707] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.722] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.724] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.739] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.741] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.756] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.758] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.772] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.774] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.789] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.791] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.806] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.808] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.822] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.824] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.839] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.841] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.856] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.858] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.872] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.874] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.889] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.891] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.906] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.908] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.922] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.924] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.939] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.941] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.956] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.958] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   172.972] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   172.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   172.989] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   172.991] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.006] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.008] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.022] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.024] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.039] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.041] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.056] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.058] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.072] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.074] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.090] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.092] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.106] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.108] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.122] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.124] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.139] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.141] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.156] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.158] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.172] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.189] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.191] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.206] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.208] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.222] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.224] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.239] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.241] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.256] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.258] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.272] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.274] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.289] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.291] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.306] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.308] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.322] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.324] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.339] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.341] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.356] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.358] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.372] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.374] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.389] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.391] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.406] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.407] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.422] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.424] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.439] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.441] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.456] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.458] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.472] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.474] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.489] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.491] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.506] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.507] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.522] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.524] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.539] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.541] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.556] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.557] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.572] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.574] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.589] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.593] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.606] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.607] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.622] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.624] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.639] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.641] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.656] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.657] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.672] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.674] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.689] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.691] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.706] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.707] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.722] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.724] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.739] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.741] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.756] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.757] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.772] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.774] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.789] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.791] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.806] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.807] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.822] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.824] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.839] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.841] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.856] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.857] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.872] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.874] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.889] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.891] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.906] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.908] (II) RADEON(0): RADEONSaveScreen(2)
>[   173.922] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.924] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.939] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.941] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.956] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   173.972] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   173.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   173.989] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   173.991] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.006] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.022] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.024] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.039] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.041] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.056] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.057] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.072] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.074] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.090] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.093] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.106] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.107] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.122] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.124] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.139] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.141] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.156] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.157] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.172] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.189] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.191] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.206] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.207] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.222] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.224] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.239] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.241] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.256] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.272] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.274] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.289] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.291] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.305] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.307] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.322] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.324] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.339] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.341] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.355] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.357] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.372] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.374] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.389] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.391] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.405] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.407] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.422] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.424] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.439] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.441] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.455] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.457] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.472] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.474] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.489] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.491] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.505] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.507] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.522] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.524] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.539] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.541] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.555] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.557] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.572] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.574] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.591] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.594] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.605] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.607] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.622] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.624] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.639] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.641] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.655] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.657] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.672] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.674] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.689] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.691] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.705] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.748] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.755] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.757] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.772] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.774] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.789] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.790] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.805] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.807] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.822] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.824] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.839] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.841] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.856] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.857] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.872] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.874] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.889] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.891] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.905] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.922] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.924] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.939] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.941] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.955] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   174.972] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   174.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   174.989] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   174.991] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.005] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.022] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.024] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.039] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.041] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.055] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.057] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.072] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.074] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.090] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.093] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.105] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.107] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.122] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.124] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.139] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.141] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.155] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.157] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.172] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.189] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.191] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.205] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.207] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.222] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.224] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.239] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.241] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.255] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.272] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.274] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.289] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.291] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.305] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.307] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.322] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.330] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.339] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.346] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.355] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.361] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.372] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.376] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.389] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.392] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.405] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.408] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.422] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.424] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.439] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.440] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.455] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.457] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.472] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.473] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.489] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.490] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.505] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.507] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.522] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.523] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.539] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.540] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.555] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.557] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.572] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.574] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.591] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.594] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.605] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.607] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.622] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.624] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.639] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.655] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.657] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.672] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.674] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.689] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.691] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.705] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.707] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.722] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.724] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.739] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.755] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.758] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.772] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.774] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.789] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.791] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.805] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.807] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.822] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.824] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.839] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.841] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.855] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.857] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.872] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.874] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.889] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.890] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.905] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.922] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.924] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.939] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.940] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.955] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   175.972] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   175.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   175.989] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   175.991] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.005] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.022] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.024] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.039] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.041] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.055] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.057] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.072] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.074] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.092] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.094] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.105] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.107] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.122] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.124] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.139] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.141] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.155] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.157] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.172] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.189] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.191] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.205] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.206] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.222] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.224] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.239] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.241] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.255] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.272] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.274] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.289] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.290] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.305] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.307] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.322] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.324] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.339] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.341] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.355] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.357] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.372] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.374] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.389] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.390] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.405] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.407] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.422] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.424] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.439] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.440] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.455] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.457] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.472] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.474] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.488] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.490] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.505] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.507] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.522] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.524] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.538] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.540] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.555] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.557] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.572] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.574] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.588] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.593] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.605] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.607] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.622] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.624] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.638] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.655] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.658] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.672] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.674] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.688] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.690] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.705] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.707] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.722] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.724] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.738] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.755] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.757] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.772] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.774] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.788] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.790] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.805] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.807] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.822] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.824] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.838] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.840] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.855] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.857] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.872] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.874] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.888] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.890] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.905] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.922] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.924] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.938] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.940] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.955] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   176.972] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   176.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   176.988] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   176.990] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.005] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.022] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.024] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.038] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.055] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.057] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.072] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.074] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.088] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.096] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.105] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.107] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.122] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.124] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.138] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.140] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.155] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.157] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.172] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.188] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.190] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.205] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.207] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.222] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.224] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.238] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.241] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.255] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.272] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.274] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.288] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.290] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.305] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.307] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.322] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.324] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.338] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.340] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.355] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.357] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.372] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.374] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.388] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.390] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.405] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.407] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.422] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.424] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.438] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.440] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.455] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.457] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.472] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.474] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.488] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.490] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.505] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.507] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.522] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.524] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.538] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.540] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.555] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.557] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.572] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.574] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.588] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.590] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.605] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.607] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.622] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.624] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.638] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.655] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.657] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.672] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.674] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.688] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.691] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.705] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.707] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.722] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.724] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.738] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.755] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.757] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.772] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.773] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.788] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.790] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.805] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.807] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.822] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.824] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.838] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.840] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.855] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.857] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.872] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.873] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.888] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.890] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.905] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.922] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.923] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.938] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.940] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.955] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   177.972] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   177.973] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   177.988] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   177.990] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.005] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.022] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.023] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.038] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.055] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.057] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.072] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.073] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.088] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.095] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.105] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.106] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.122] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.124] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.138] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.139] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.155] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.157] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.172] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.173] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.188] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.190] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.205] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.207] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.222] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.223] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.238] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.240] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.255] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.272] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.274] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.288] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.290] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.305] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.307] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.322] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.323] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.338] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.340] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.355] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.357] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.372] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.373] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.388] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.390] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.405] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.408] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.422] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.423] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.438] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.440] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.455] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.457] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.472] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.473] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.488] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.490] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.505] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.507] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.522] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.523] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.538] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.540] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.555] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.557] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.572] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.573] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.588] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.590] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.605] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.607] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.622] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.623] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.638] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.655] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.657] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.672] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.673] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.688] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.690] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.705] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.707] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.722] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.723] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.738] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.755] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.757] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.772] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.773] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.788] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.790] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.805] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.807] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.822] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.823] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.838] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.840] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.855] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.857] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.872] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.873] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.888] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.890] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.905] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.921] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.923] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.923] (II) RADEON(0): RADEONSaveScreen(2)
>[   178.938] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.940] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.955] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   178.971] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   178.973] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   178.988] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   178.990] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   179.005] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   179.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   179.021] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   179.023] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   179.038] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   179.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   179.055] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   179.057] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   179.071] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   179.073] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   179.088] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   179.093] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   179.105] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   179.109] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   179.121] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   179.123] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   179.138] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   179.140] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   179.155] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   179.157] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   179.171] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   179.173] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   179.188] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   179.190] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   179.205] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   179.207] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   179.221] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   179.223] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   179.238] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   179.240] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   179.255] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   179.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   179.271] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   179.273] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   179.288] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   179.290] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   179.305] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   180.868] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   180.888] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   180.891] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   180.905] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   180.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   180.921] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   180.924] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   180.938] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   180.940] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   180.955] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   180.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   180.971] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   180.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   180.988] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   180.991] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.005] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.021] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.023] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.038] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.054] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.057] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.071] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.074] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.088] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.090] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.105] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.107] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.121] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.124] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.138] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.140] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.155] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.157] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.171] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.188] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.191] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.205] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.207] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.221] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.225] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.238] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.241] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.255] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.271] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.274] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.288] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.290] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.304] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.307] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.321] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.324] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.338] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.340] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.354] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.357] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.371] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.374] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.388] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.390] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.404] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.407] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.421] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.423] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.438] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.440] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.454] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.457] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.471] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.473] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.488] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.490] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.504] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.507] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.521] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.524] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.538] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.540] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.554] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.558] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.571] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.574] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.588] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.590] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.604] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.607] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.621] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.622] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.638] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.654] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.657] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.671] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.674] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.688] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.690] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.704] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.707] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.721] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.723] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.738] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.754] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.757] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.771] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.773] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.788] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.790] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.804] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.807] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.821] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.823] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.838] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.840] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.854] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.857] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.871] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.873] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.888] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.890] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.904] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.921] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.924] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.938] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.941] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.954] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   181.971] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   181.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   181.988] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   181.990] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.004] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.021] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.024] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.038] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.041] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.054] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.057] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.071] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.074] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.088] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.091] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.104] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.107] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.121] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.122] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.138] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.141] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.154] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.157] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.171] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.188] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.190] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.204] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.207] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.221] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.224] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.238] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.240] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.254] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.271] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.275] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.288] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.290] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.304] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.307] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.321] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.323] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.338] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.341] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.354] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.357] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.371] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.374] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.388] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.390] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.404] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.407] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.421] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.423] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.438] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.440] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.454] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.457] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.471] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.473] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.488] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.491] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.504] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.507] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.521] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.523] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.538] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.540] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.554] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.557] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.571] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.573] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.588] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.590] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.604] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.607] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.621] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.622] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.638] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.654] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.657] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.671] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.674] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.688] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.690] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.704] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.708] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.721] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.724] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.738] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.754] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.757] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.771] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.773] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.788] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.790] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.804] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.807] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.821] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.823] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.838] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.840] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.854] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.858] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.871] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.873] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.888] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.890] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.904] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.921] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.924] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.938] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.940] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.954] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   182.971] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   182.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   182.988] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   182.990] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.004] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.021] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.024] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.038] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.054] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.057] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.071] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.073] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.088] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.090] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.104] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.107] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.121] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.123] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.138] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.140] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.154] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.157] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.171] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.188] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.190] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.205] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.209] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.221] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.223] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.238] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.240] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.254] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.271] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.273] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.288] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.290] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.304] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.307] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.321] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.324] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.338] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.340] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.354] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.357] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.371] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.373] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.388] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.390] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.404] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.407] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.421] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.424] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.438] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.440] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.454] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.457] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.471] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.473] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.488] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.490] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.504] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.507] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.521] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.524] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.538] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.540] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.554] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.557] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.571] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.573] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.588] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.590] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.604] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.607] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.621] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.624] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.638] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.654] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.657] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.671] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.674] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.687] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.690] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.706] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.711] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.737] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.754] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.757] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.771] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.774] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.787] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.790] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.804] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.807] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.821] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.824] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.837] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.841] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.854] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.857] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.871] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.873] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.887] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.890] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.904] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.921] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.924] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.924] (II) RADEON(0): RADEONSaveScreen(2)
>[   183.937] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.941] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.954] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   183.971] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   183.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   183.987] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   183.990] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.004] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.021] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.023] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.037] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.054] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.057] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.071] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.073] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.087] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.091] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.105] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.108] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.121] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.124] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.137] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.140] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.154] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.157] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.171] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.187] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.191] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.206] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.210] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.221] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.223] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.237] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.242] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.254] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.271] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.274] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.287] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.291] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.304] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.307] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.321] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.324] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.337] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.341] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.354] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.357] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.371] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.374] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.387] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.390] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.404] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.407] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.421] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.423] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.437] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.441] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.454] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.457] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.471] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.473] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.487] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.491] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.504] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.507] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.521] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.524] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.537] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.541] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.554] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.558] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.571] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.574] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.587] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.590] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.605] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.609] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.621] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.624] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.637] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.641] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.654] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.657] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.671] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.674] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.687] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.690] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.706] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.755] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.771] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.773] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.787] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.789] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.804] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.807] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.821] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.823] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.837] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.840] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.854] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.857] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.871] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.873] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.887] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.890] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.904] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.921] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.924] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.937] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.940] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.954] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   184.971] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   184.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   184.987] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   184.990] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.004] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.021] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.023] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.037] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.054] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.056] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.071] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.073] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.087] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.090] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.105] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.109] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.121] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.123] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.137] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.140] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.154] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.157] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.171] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.187] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.190] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.207] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.211] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.237] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.241] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.254] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.256] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.271] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.274] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.287] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.290] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.304] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.307] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.321] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.323] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.337] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.340] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.354] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.356] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.371] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.373] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.387] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.390] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.404] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.406] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.421] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.423] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.437] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.440] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.454] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.457] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.471] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.473] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.487] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.490] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.504] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.506] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.521] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.523] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.537] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.540] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.554] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.557] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.571] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.573] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.587] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.590] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.605] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.609] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.621] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.623] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.637] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.654] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.657] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.671] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.673] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.687] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.690] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.708] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.711] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.737] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.754] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.757] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.771] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.773] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.787] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.790] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.804] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.806] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.821] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.825] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.837] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.840] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.854] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.857] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.871] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.873] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.887] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.890] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.904] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.921] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.923] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.937] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.940] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.954] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   185.970] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   185.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   185.987] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   185.990] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.004] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.021] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.024] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.037] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.054] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.056] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.070] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.074] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.087] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.090] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.105] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.109] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.120] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.123] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.137] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.140] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.154] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.156] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.170] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.187] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.190] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.204] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.213] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.220] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.222] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.237] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.240] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.254] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.270] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.274] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.287] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.290] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.304] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.307] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.320] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.323] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.337] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.340] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.354] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.356] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.370] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.373] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.387] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.390] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.404] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.407] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.420] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.424] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.437] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.440] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.454] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.457] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.470] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.474] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.487] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.490] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.504] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.507] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.520] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.523] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.537] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.540] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.554] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.557] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.570] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.573] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.587] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.590] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.606] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.610] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.620] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.624] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.637] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.654] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.656] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.670] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.673] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.687] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.689] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.704] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.709] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.720] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.723] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.737] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.754] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.756] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.770] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.773] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.787] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.789] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.804] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.806] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.820] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.823] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.837] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.840] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.854] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.857] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.870] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.873] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.887] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.890] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.904] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.907] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.920] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.923] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.937] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.940] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.954] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   186.970] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   186.973] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   186.987] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   186.990] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.004] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.006] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.020] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.023] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.037] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.054] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.057] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.070] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.073] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.087] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.090] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.106] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.109] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.120] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.123] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.137] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.140] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.154] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.156] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.170] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.173] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.187] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.189] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.204] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.209] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.220] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.222] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.237] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.239] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.254] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.257] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.270] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.273] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.287] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.289] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.304] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.306] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.320] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.323] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.337] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.340] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.354] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.356] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.370] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.373] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.387] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.389] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.404] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.406] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.420] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.423] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.437] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.439] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.454] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.456] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.470] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.473] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.487] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.490] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.504] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.506] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.520] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.523] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.537] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.540] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.554] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.556] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.570] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.573] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.587] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.589] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.607] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.611] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.637] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.639] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.654] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.656] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.670] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.673] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.687] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.690] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.704] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.706] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.720] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.722] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.737] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.754] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.757] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.770] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.773] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.787] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.790] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.804] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.807] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.820] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.823] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.837] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.840] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.854] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.856] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.870] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.874] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.887] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.890] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.904] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.906] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.920] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.923] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.937] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.940] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.954] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.956] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   187.970] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   187.973] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   187.987] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   187.989] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.004] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.006] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.020] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.023] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.037] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.054] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.056] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.070] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.073] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.087] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.090] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.107] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.108] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.120] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.123] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.137] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.139] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.153] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.156] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.170] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.173] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.187] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.189] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.203] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.206] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.220] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.222] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.237] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.239] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.254] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.256] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.270] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.273] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.287] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.289] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.304] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.306] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.320] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.323] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.337] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.339] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.353] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.356] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.370] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.373] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.387] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.389] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.403] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.406] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.420] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.423] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.437] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.439] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.453] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.456] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.470] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.473] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.487] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.489] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.503] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.506] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.520] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.523] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.537] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.539] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.553] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.556] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.570] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.573] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.587] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.589] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.607] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.610] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.620] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.621] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.637] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.653] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.656] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.670] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.673] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.687] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.690] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.703] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.706] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.720] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.721] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.737] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.739] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.753] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.756] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.770] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.772] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.787] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.789] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.803] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.806] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.820] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.822] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.837] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.839] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.853] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.856] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.870] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.872] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.887] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.889] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.903] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.906] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.920] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.922] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.937] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.939] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.939] (II) RADEON(0): RADEONSaveScreen(2)
>[   188.953] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.956] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   188.970] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   188.973] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   188.987] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   188.990] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   189.003] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   189.006] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   189.020] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   189.023] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   189.037] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   189.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   189.053] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   189.056] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   189.070] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   189.072] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   189.087] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   189.089] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   189.103] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   189.107] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   189.120] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   189.123] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   189.137] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   189.139] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   189.153] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   189.156] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   189.170] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   189.172] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   189.187] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   189.190] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   189.203] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   189.206] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   189.220] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   189.222] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   189.237] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   189.239] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   189.253] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   189.256] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   189.270] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   189.272] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   189.287] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   189.289] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   189.303] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   189.306] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   189.320] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   189.322] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1bd0]
>[   189.337] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1bd0] width 1366 pitch 5632 (/4 1408)
>[   189.339] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1be1ab0]
>[   189.353] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1be1ab0] width 1366 pitch 5632 (/4 1408)
>[   189.517] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   189.537] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   189.538] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   189.570] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   189.573] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   189.603] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   189.608] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   189.637] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   189.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   189.670] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   189.674] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   189.703] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   189.708] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   189.737] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   189.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   189.770] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   189.774] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   189.803] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   189.807] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   189.837] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   189.840] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   189.870] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   189.873] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   189.903] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   189.906] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   189.937] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   189.940] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   189.970] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   189.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.003] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.037] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.070] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.073] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.103] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.111] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.137] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.138] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.170] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.203] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.208] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.237] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.240] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.270] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.274] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.303] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.306] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.337] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.340] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.370] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.373] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.403] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.407] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.437] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.440] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.470] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.473] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.503] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.506] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.537] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.539] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.570] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.573] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.603] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.610] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.637] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.670] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.671] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.703] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.705] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.737] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.770] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.773] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.803] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.806] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.837] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.840] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.870] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.873] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.903] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.906] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   190.936] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   190.940] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   190.970] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   190.974] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.003] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.007] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.036] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.040] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.070] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.073] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.103] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.107] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.136] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.140] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.170] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.174] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.203] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.208] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.236] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.240] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.270] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.273] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.303] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.307] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.336] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.341] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.370] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.373] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.403] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.407] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.436] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.440] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.470] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.473] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.503] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.506] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.536] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.540] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.570] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.573] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.603] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.608] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.636] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.640] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.670] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.673] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.703] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.707] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.736] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.770] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.774] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.803] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   191.806] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b43500]
>[   191.836] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b43500] width 1366 pitch 5632 (/4 1408)
>[   191.840] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   191.870] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.223] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.236] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.238] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.253] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.254] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.270] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.271] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.286] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.287] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.303] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.304] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.320] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.321] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.336] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.338] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.353] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.355] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.370] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.372] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.386] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.387] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.403] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.405] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.420] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.422] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.436] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.438] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.453] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.455] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.470] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.471] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.486] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.488] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.503] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.505] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.520] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.522] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.536] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.538] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.553] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.555] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.570] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.571] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.586] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.588] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.603] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.605] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.620] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.622] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.636] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.638] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.653] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.655] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.670] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.671] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.686] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.688] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.703] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.705] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.720] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.721] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.737] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.738] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.753] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.755] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.770] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.771] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.786] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.788] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.803] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.805] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.820] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.821] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.836] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.838] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.853] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.855] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.870] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.871] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.886] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.888] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.903] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.905] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.920] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.921] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.936] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.938] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.953] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.955] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   192.970] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   192.971] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   192.986] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   192.988] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.003] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.005] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.020] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.021] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.036] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.038] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.053] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.055] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.070] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.071] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.086] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.088] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.103] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.105] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.120] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.121] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.136] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.138] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.153] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.155] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.170] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.171] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.186] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.188] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.203] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.205] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.220] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.221] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.236] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.238] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.253] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.255] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.269] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.271] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.286] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.288] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.303] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.305] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.320] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.321] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.336] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.338] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.353] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.355] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.369] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.371] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.386] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.388] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.403] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.405] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.419] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.421] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.436] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.438] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.453] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.455] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.469] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.471] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.486] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.488] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.503] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.505] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.519] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.521] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.536] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.538] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.553] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.555] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.569] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.571] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.586] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.588] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.603] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.605] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.619] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.621] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.636] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.638] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.653] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.655] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.669] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.671] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.686] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.688] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.703] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.705] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.719] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.721] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.736] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.738] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.753] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.755] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.769] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.771] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.786] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.788] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.803] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.805] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.819] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.821] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.836] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.838] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.853] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.855] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.869] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.871] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.886] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.888] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.903] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.905] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.919] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.921] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.936] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.938] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.953] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.954] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   193.955] (II) RADEON(0): RADEONSaveScreen(2)
>[   193.969] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   193.971] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   193.986] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   193.988] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.003] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.005] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.019] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.021] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.036] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.038] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.053] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.054] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.069] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.071] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.086] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.088] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.103] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.104] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.119] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.121] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.136] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.138] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.153] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.155] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.169] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.171] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.186] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.188] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.203] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.204] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.219] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.221] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.236] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.238] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.253] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.254] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.269] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.271] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.286] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.288] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.303] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.304] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.319] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.321] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.336] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.338] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.353] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.354] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.369] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.371] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.386] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.388] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.403] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.404] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.419] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.421] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.436] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.438] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.453] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.454] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.469] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.471] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.486] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.488] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.503] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.505] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.519] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.521] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.536] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.538] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.553] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.554] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.569] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.571] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.586] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.588] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.603] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.604] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.619] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.621] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.636] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.638] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.653] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.654] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.669] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.672] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.686] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.688] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.703] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.704] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.719] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.759] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.769] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.771] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.786] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.788] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.803] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.804] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.819] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.820] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.836] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.837] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.853] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.854] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.869] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.871] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.886] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.888] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.903] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.904] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.919] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.921] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.936] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.938] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.953] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.954] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   194.969] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   194.971] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   194.986] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   194.988] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.003] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.004] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.019] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.021] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.036] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.038] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.053] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.054] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.069] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.071] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.086] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.088] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.103] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.104] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.119] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.121] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.136] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.138] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.153] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.154] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.169] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.171] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.186] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.188] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.203] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.204] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.219] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.221] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.236] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.238] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.253] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.255] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.269] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.271] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.286] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.288] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.303] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.304] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.319] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.321] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.336] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.338] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.353] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.354] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.369] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.371] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.386] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.388] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.403] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.404] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.419] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.421] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.436] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.438] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.452] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.454] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.469] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.471] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.486] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.488] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.502] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.504] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.519] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.521] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.536] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.538] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.552] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.554] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.569] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.571] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.586] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.588] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.602] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.604] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.619] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.621] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.636] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.638] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.652] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.654] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.669] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.671] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.686] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.688] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.702] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.704] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.719] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.721] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.736] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.738] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.752] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.754] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.769] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.771] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.786] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.788] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.802] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.804] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.819] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.821] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.836] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.838] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.852] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.854] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.869] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.871] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.886] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.888] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.902] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.904] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.919] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.921] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.936] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.938] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.952] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.954] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   195.969] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   195.971] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   195.986] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   195.988] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.002] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.004] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.019] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.021] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.036] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.038] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.052] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.054] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.069] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.071] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.086] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.088] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.102] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.104] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.119] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.121] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.136] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.138] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.152] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.154] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.169] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.171] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.186] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.188] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.202] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.204] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.220] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.222] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.236] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.237] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.252] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.254] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.269] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.271] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.286] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.288] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.302] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.304] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.319] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.321] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.336] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.338] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.352] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.354] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.369] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.371] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.386] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.388] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.402] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.404] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.419] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.421] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.436] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.438] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.452] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.454] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.469] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.471] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.486] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.488] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.502] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.504] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.519] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.521] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.536] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.537] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.552] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.554] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.569] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.571] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.586] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.587] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.602] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.604] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.620] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.622] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.636] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.638] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.652] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.654] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.669] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.671] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.686] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.688] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.702] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.704] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.720] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.722] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.736] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.738] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.752] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.754] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.769] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.771] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.786] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.788] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.802] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.804] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.819] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.821] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.836] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.837] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.852] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.854] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.869] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.871] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.886] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.887] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.902] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.904] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.919] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.921] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.936] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.937] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.952] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.954] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   196.969] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   196.971] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   196.986] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   196.987] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.002] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.004] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.019] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.021] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.036] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.037] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.052] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.054] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.069] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.071] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.086] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.087] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.102] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.104] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.120] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.122] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.136] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.137] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.152] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.154] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.169] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.171] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.186] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.188] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.202] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.204] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.220] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.224] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.236] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.237] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.252] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.254] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.269] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.271] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.286] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.287] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.302] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.304] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.319] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.322] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.336] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.337] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.352] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.354] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.369] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.371] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.386] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.387] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.402] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.404] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.419] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.421] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.436] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.437] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.452] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.454] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.469] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.471] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.486] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.487] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.502] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.504] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.519] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.521] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.536] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.537] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.552] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.554] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.569] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.571] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.586] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.587] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.602] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.604] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.619] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.621] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.636] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.637] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.652] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.654] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.669] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.671] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.686] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.687] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.702] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.704] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.720] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.724] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.736] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.737] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.752] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.754] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.769] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.771] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.786] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.787] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.802] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.804] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.819] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.821] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.835] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.837] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.852] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.854] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.869] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.871] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.885] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.887] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.902] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   197.904] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcb180]
>[   197.919] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcb180] width 1366 pitch 5632 (/4 1408)
>[   197.920] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7d20]
>[   197.935] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7d20] width 1366 pitch 5632 (/4 1408)
>[   198.609] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   198.619] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   199.819] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbe110]
>[   199.835] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbe110] width 1366 pitch 5632 (/4 1408)
>[   200.223] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   200.235] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   200.557] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6bf40]
>[   200.568] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6bf40] width 1366 pitch 5632 (/4 1408)
>[   200.689] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6c0a0]
>[   200.702] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6c0a0] width 1366 pitch 5632 (/4 1408)
>[   200.872] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   200.885] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   200.967] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbe110]
>[   200.968] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbe110] width 1366 pitch 5632 (/4 1408)
>[   200.983] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   200.985] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   200.998] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbe110]
>[   201.002] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbe110] width 1366 pitch 5632 (/4 1408)
>[   201.014] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   201.018] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   201.028] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbe110]
>[   201.035] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbe110] width 1366 pitch 5632 (/4 1408)
>[   201.045] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   201.052] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   201.062] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbe110]
>[   201.068] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbe110] width 1366 pitch 5632 (/4 1408)
>[   201.078] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   201.085] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   201.095] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbe110]
>[   201.102] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbe110] width 1366 pitch 5632 (/4 1408)
>[   201.108] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   201.118] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   201.138] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6bf40]
>[   201.152] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6bf40] width 1366 pitch 5632 (/4 1408)
>[   201.188] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbe110]
>[   201.202] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbe110] width 1366 pitch 5632 (/4 1408)
>[   201.855] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbe110]
>[   201.868] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbe110] width 1366 pitch 5632 (/4 1408)
>[   201.883] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbd380]
>[   201.902] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbd380] width 1366 pitch 5632 (/4 1408)
>[   201.957] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbe110]
>[   201.968] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbe110] width 1366 pitch 5632 (/4 1408)
>[   202.289] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdda0]
>[   202.302] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdda0] width 1366 pitch 5632 (/4 1408)
>[   202.989] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6bf40]
>[   203.001] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6bf40] width 1366 pitch 5632 (/4 1408)
>[   205.412] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   205.418] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   205.429] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6bd80]
>[   205.434] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6bd80] width 1366 pitch 5632 (/4 1408)
>[   205.441] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   205.451] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   205.458] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6bd80]
>[   205.468] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6bd80] width 1366 pitch 5632 (/4 1408)
>[   205.473] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbb360]
>[   205.484] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbb360] width 1366 pitch 5632 (/4 1408)
>[   205.491] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6bd80]
>[   205.501] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6bd80] width 1366 pitch 5632 (/4 1408)
>[   205.561] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbe110]
>[   205.610] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbe110] width 1366 pitch 5632 (/4 1408)
>[   205.624] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbee60]
>[   205.673] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbee60] width 1366 pitch 5632 (/4 1408)
>[   206.774] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5420]
>[   206.784] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5420] width 1366 pitch 5632 (/4 1408)
>[   206.788] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   206.801] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   206.804] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5420]
>[   206.818] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5420] width 1366 pitch 5632 (/4 1408)
>[   206.821] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   206.834] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   206.837] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5420]
>[   206.851] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5420] width 1366 pitch 5632 (/4 1408)
>[   206.854] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   206.868] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   206.871] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5420]
>[   206.884] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5420] width 1366 pitch 5632 (/4 1408)
>[   206.887] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   206.901] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   206.904] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5420]
>[   206.918] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5420] width 1366 pitch 5632 (/4 1408)
>[   206.921] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   206.934] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   206.938] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5420]
>[   206.951] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5420] width 1366 pitch 5632 (/4 1408)
>[   206.954] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   206.968] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   206.971] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5420]
>[   206.984] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5420] width 1366 pitch 5632 (/4 1408)
>[   206.987] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.001] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.004] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5420]
>[   207.018] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5420] width 1366 pitch 5632 (/4 1408)
>[   207.021] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.034] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.037] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5420]
>[   207.051] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5420] width 1366 pitch 5632 (/4 1408)
>[   207.054] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.068] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.071] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5420]
>[   207.084] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5420] width 1366 pitch 5632 (/4 1408)
>[   207.088] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.101] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.104] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5420]
>[   207.118] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5420] width 1366 pitch 5632 (/4 1408)
>[   207.121] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.135] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.139] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5e10]
>[   207.151] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5e10] width 1366 pitch 5632 (/4 1408)
>[   207.153] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.168] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.171] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5e10]
>[   207.184] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5e10] width 1366 pitch 5632 (/4 1408)
>[   207.187] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.201] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.204] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5e10]
>[   207.218] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5e10] width 1366 pitch 5632 (/4 1408)
>[   207.221] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.235] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.238] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   207.251] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   207.254] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.267] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.270] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   207.284] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   207.287] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.301] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.302] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   207.318] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   207.321] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.334] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.337] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   207.351] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   207.354] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.367] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.370] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   207.384] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   207.387] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.401] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.404] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   207.417] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   207.421] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.434] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.437] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   207.451] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   207.454] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.467] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.470] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   207.484] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   207.487] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.501] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.504] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   207.517] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   207.521] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.534] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.537] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   207.551] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   207.554] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.567] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.571] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   207.584] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   207.587] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.601] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.604] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   207.617] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   207.621] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.637] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.638] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b25130]
>[   207.651] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b25130] width 1366 pitch 5632 (/4 1408)
>[   207.653] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.667] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.670] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b25130]
>[   207.684] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b25130] width 1366 pitch 5632 (/4 1408)
>[   207.687] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.701] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.704] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b25130]
>[   207.717] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b25130] width 1366 pitch 5632 (/4 1408)
>[   207.721] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   207.735] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   207.739] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5a80]
>[   207.751] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5a80] width 1366 pitch 5632 (/4 1408)
>[   207.753] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7950]
>[   207.767] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7950] width 1366 pitch 5632 (/4 1408)
>[   207.770] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5a80]
>[   207.784] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5a80] width 1366 pitch 5632 (/4 1408)
>[   207.787] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7950]
>[   207.801] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7950] width 1366 pitch 5632 (/4 1408)
>[   207.804] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5a80]
>[   207.817] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5a80] width 1366 pitch 5632 (/4 1408)
>[   207.821] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7950]
>[   207.834] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7950] width 1366 pitch 5632 (/4 1408)
>[   207.837] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5a80]
>[   207.851] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5a80] width 1366 pitch 5632 (/4 1408)
>[   207.854] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7950]
>[   207.867] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7950] width 1366 pitch 5632 (/4 1408)
>[   207.870] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5a80]
>[   207.884] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5a80] width 1366 pitch 5632 (/4 1408)
>[   207.887] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7950]
>[   207.901] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7950] width 1366 pitch 5632 (/4 1408)
>[   207.904] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5a80]
>[   207.917] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5a80] width 1366 pitch 5632 (/4 1408)
>[   207.920] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7950]
>[   207.934] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7950] width 1366 pitch 5632 (/4 1408)
>[   207.937] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5a80]
>[   207.951] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5a80] width 1366 pitch 5632 (/4 1408)
>[   207.954] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7950]
>[   207.967] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7950] width 1366 pitch 5632 (/4 1408)
>[   207.970] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5a80]
>[   207.984] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5a80] width 1366 pitch 5632 (/4 1408)
>[   207.987] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7950]
>[   208.001] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7950] width 1366 pitch 5632 (/4 1408)
>[   208.004] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5a80]
>[   208.017] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5a80] width 1366 pitch 5632 (/4 1408)
>[   208.020] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7950]
>[   208.034] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7950] width 1366 pitch 5632 (/4 1408)
>[   208.037] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5a80]
>[   208.051] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5a80] width 1366 pitch 5632 (/4 1408)
>[   208.054] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7950]
>[   208.067] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7950] width 1366 pitch 5632 (/4 1408)
>[   208.070] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5a80]
>[   208.084] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5a80] width 1366 pitch 5632 (/4 1408)
>[   208.087] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7950]
>[   208.101] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7950] width 1366 pitch 5632 (/4 1408)
>[   208.104] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5a80]
>[   208.117] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5a80] width 1366 pitch 5632 (/4 1408)
>[   208.120] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd7950]
>[   208.137] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd7950] width 1366 pitch 5632 (/4 1408)
>[   208.145] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd52c0]
>[   208.151] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd52c0] width 1366 pitch 5632 (/4 1408)
>[   208.152] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5910]
>[   208.167] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5910] width 1366 pitch 5632 (/4 1408)
>[   208.170] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bde920]
>[   208.184] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bde920] width 1366 pitch 5632 (/4 1408)
>[   208.187] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5910]
>[   208.201] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5910] width 1366 pitch 5632 (/4 1408)
>[   208.204] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bde920]
>[   208.217] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bde920] width 1366 pitch 5632 (/4 1408)
>[   208.220] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5910]
>[   208.234] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5910] width 1366 pitch 5632 (/4 1408)
>[   208.238] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79a0]
>[   208.251] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79a0] width 1366 pitch 5632 (/4 1408)
>[   208.253] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.267] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.270] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79a0]
>[   208.284] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79a0] width 1366 pitch 5632 (/4 1408)
>[   208.286] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.301] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.304] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79a0]
>[   208.317] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79a0] width 1366 pitch 5632 (/4 1408)
>[   208.324] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.334] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.337] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79a0]
>[   208.351] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79a0] width 1366 pitch 5632 (/4 1408)
>[   208.354] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.367] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.370] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79a0]
>[   208.384] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79a0] width 1366 pitch 5632 (/4 1408)
>[   208.387] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.401] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.404] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79a0]
>[   208.417] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79a0] width 1366 pitch 5632 (/4 1408)
>[   208.420] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.434] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.437] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79a0]
>[   208.451] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79a0] width 1366 pitch 5632 (/4 1408)
>[   208.454] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.467] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.470] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79a0]
>[   208.484] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79a0] width 1366 pitch 5632 (/4 1408)
>[   208.487] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.501] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.504] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79a0]
>[   208.517] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79a0] width 1366 pitch 5632 (/4 1408)
>[   208.520] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.534] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.537] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79a0]
>[   208.551] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79a0] width 1366 pitch 5632 (/4 1408)
>[   208.554] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.567] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.570] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79a0]
>[   208.584] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79a0] width 1366 pitch 5632 (/4 1408)
>[   208.587] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.601] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.604] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79a0]
>[   208.617] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79a0] width 1366 pitch 5632 (/4 1408)
>[   208.620] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.639] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.646] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   208.651] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   208.652] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.667] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.670] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   208.684] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   208.687] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.701] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.704] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   208.717] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   208.720] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.737] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.740] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   208.751] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   208.754] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.767] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.770] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   208.784] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   208.787] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.801] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.804] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   208.817] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   208.820] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.834] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.838] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   208.851] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   208.854] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.867] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.870] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   208.884] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   208.887] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.901] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.904] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   208.917] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   208.920] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.934] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.937] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   208.951] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   208.954] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   208.967] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   208.970] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   208.984] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   208.987] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   209.001] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   209.004] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   209.017] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   209.020] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   209.034] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   209.037] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   209.051] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   209.054] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   209.067] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   209.070] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   209.084] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   209.087] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   209.101] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   209.104] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   209.117] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   209.120] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b7a0]
>[   209.134] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b7a0] width 1366 pitch 5632 (/4 1408)
>[   209.144] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   209.151] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   209.152] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5400]
>[   209.167] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5400] width 1366 pitch 5632 (/4 1408)
>[   209.170] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   209.184] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   209.187] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5400]
>[   209.201] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5400] width 1366 pitch 5632 (/4 1408)
>[   209.204] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   209.217] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   209.220] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5400]
>[   209.236] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5400] width 1366 pitch 5632 (/4 1408)
>[   209.239] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf560]
>[   209.251] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf560] width 1366 pitch 5632 (/4 1408)
>[   209.254] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.267] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.271] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf560]
>[   209.284] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf560] width 1366 pitch 5632 (/4 1408)
>[   209.287] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.301] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.304] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf560]
>[   209.317] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf560] width 1366 pitch 5632 (/4 1408)
>[   209.320] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.334] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.337] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf560]
>[   209.351] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf560] width 1366 pitch 5632 (/4 1408)
>[   209.354] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.367] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.370] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf560]
>[   209.384] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf560] width 1366 pitch 5632 (/4 1408)
>[   209.387] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.401] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.404] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf560]
>[   209.417] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf560] width 1366 pitch 5632 (/4 1408)
>[   209.420] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.434] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.437] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf560]
>[   209.451] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf560] width 1366 pitch 5632 (/4 1408)
>[   209.454] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.467] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.471] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf560]
>[   209.484] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf560] width 1366 pitch 5632 (/4 1408)
>[   209.487] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.501] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.503] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf560]
>[   209.517] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf560] width 1366 pitch 5632 (/4 1408)
>[   209.520] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.534] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.537] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf560]
>[   209.551] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf560] width 1366 pitch 5632 (/4 1408)
>[   209.554] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.567] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.570] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf560]
>[   209.584] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf560] width 1366 pitch 5632 (/4 1408)
>[   209.587] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.601] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.604] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf560]
>[   209.617] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf560] width 1366 pitch 5632 (/4 1408)
>[   209.621] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.634] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.642] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.651] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.653] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   209.667] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   209.670] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.684] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.687] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   209.701] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   209.703] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf5c0]
>[   209.717] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf5c0] width 1366 pitch 5632 (/4 1408)
>[   209.720] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   209.734] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   209.788] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b410]
>[   209.801] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b410] width 1366 pitch 5632 (/4 1408)
>[   209.803] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   209.817] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   209.819] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b410]
>[   209.834] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b410] width 1366 pitch 5632 (/4 1408)
>[   209.836] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   209.850] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   209.853] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b410]
>[   209.867] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b410] width 1366 pitch 5632 (/4 1408)
>[   209.870] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   209.884] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   209.887] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b410]
>[   209.900] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b410] width 1366 pitch 5632 (/4 1408)
>[   209.903] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   209.917] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   209.924] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b410]
>[   209.934] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b410] width 1366 pitch 5632 (/4 1408)
>[   209.937] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   209.950] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   209.953] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b410]
>[   209.967] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b410] width 1366 pitch 5632 (/4 1408)
>[   209.970] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   209.984] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   209.987] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b410]
>[   210.000] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b410] width 1366 pitch 5632 (/4 1408)
>[   210.004] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   210.017] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   210.020] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b410]
>[   210.034] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b410] width 1366 pitch 5632 (/4 1408)
>[   210.037] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   210.050] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   210.054] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b410]
>[   210.067] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b410] width 1366 pitch 5632 (/4 1408)
>[   210.070] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   210.084] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   210.087] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b410]
>[   210.100] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b410] width 1366 pitch 5632 (/4 1408)
>[   210.103] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   210.117] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   210.120] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b410]
>[   210.134] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b410] width 1366 pitch 5632 (/4 1408)
>[   210.144] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdea0]
>[   210.151] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdea0] width 1366 pitch 5632 (/4 1408)
>[   210.153] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.167] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.170] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdea0]
>[   210.184] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdea0] width 1366 pitch 5632 (/4 1408)
>[   210.187] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.200] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.204] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdea0]
>[   210.217] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdea0] width 1366 pitch 5632 (/4 1408)
>[   210.220] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.237] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.240] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79f0]
>[   210.250] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79f0] width 1366 pitch 5632 (/4 1408)
>[   210.253] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.267] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.270] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79f0]
>[   210.284] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79f0] width 1366 pitch 5632 (/4 1408)
>[   210.288] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.300] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.303] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79f0]
>[   210.317] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79f0] width 1366 pitch 5632 (/4 1408)
>[   210.320] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.334] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.337] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79f0]
>[   210.350] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79f0] width 1366 pitch 5632 (/4 1408)
>[   210.353] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.367] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.371] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79f0]
>[   210.384] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79f0] width 1366 pitch 5632 (/4 1408)
>[   210.387] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.400] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.403] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79f0]
>[   210.417] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79f0] width 1366 pitch 5632 (/4 1408)
>[   210.420] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.434] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.439] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79f0]
>[   210.450] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79f0] width 1366 pitch 5632 (/4 1408)
>[   210.453] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.467] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.470] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79f0]
>[   210.484] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79f0] width 1366 pitch 5632 (/4 1408)
>[   210.487] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.500] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.503] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79f0]
>[   210.517] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79f0] width 1366 pitch 5632 (/4 1408)
>[   210.520] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.534] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.537] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79f0]
>[   210.550] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79f0] width 1366 pitch 5632 (/4 1408)
>[   210.553] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.567] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.570] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79f0]
>[   210.584] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79f0] width 1366 pitch 5632 (/4 1408)
>[   210.587] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.600] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.604] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd79f0]
>[   210.617] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd79f0] width 1366 pitch 5632 (/4 1408)
>[   210.620] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   210.634] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   210.637] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56d0]
>[   210.650] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56d0] width 1366 pitch 5632 (/4 1408)
>[   210.653] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   210.667] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   210.670] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   210.684] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   210.687] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   210.700] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   210.704] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   210.717] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   210.720] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   210.741] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   210.744] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   210.750] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   210.752] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   210.767] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   210.770] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   210.784] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   210.787] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   210.800] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   210.804] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   210.817] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   210.820] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   210.834] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   210.837] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   210.850] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   210.854] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   210.867] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   210.870] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   210.884] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   210.887] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   210.900] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   210.903] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   210.917] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   210.920] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   210.934] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   210.937] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   210.950] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   210.954] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   210.967] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   210.970] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   210.984] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   210.987] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   211.000] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   211.003] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   211.017] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   211.020] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   211.034] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   211.037] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   211.050] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   211.053] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   211.067] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   211.070] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   211.084] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   211.087] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   211.100] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   211.103] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   211.117] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   211.120] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b80]
>[   211.134] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b80] width 1366 pitch 5632 (/4 1408)
>[   211.138] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcaa20]
>[   211.150] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcaa20] width 1366 pitch 5632 (/4 1408)
>[   211.152] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.167] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.170] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5590]
>[   211.184] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5590] width 1366 pitch 5632 (/4 1408)
>[   211.187] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.200] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.203] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5590]
>[   211.217] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5590] width 1366 pitch 5632 (/4 1408)
>[   211.220] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.235] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.238] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.250] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.252] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.267] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.270] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.284] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.287] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.300] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.303] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.317] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.320] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.334] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.337] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.350] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.353] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.367] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.370] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.384] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.387] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.400] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.403] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.417] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.420] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.434] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.437] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.450] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.453] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.467] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.470] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.484] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.487] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.500] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.503] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.517] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.520] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.534] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.537] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.550] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.553] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.567] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.570] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.584] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.587] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.600] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.603] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.617] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.620] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf510]
>[   211.634] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf510] width 1366 pitch 5632 (/4 1408)
>[   211.637] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.650] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.653] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   211.667] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   211.670] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.684] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.687] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   211.700] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   211.703] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5b20]
>[   211.717] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5b20] width 1366 pitch 5632 (/4 1408)
>[   211.720] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b430]
>[   211.735] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b430] width 1366 pitch 5632 (/4 1408)
>[   211.738] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   211.750] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   211.753] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   211.767] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   211.770] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   211.784] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   211.787] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   211.800] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   211.803] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   211.817] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   211.873] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   211.884] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   211.887] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   211.900] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   211.904] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   211.917] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   211.920] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   211.934] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   211.937] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   211.950] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   211.954] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   211.967] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   211.970] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   211.984] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   211.987] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   212.000] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   212.004] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   212.017] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   212.020] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   212.034] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   212.037] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   212.050] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   212.054] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   212.067] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   212.070] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   212.084] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   212.087] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   212.100] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   212.104] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   212.117] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   212.120] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1b6b3b0]
>[   212.134] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1b6b3b0] width 1366 pitch 5632 (/4 1408)
>[   212.137] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   212.150] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   212.152] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.167] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.170] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   212.183] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   212.186] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.200] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.203] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd53d0]
>[   212.217] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd53d0] width 1366 pitch 5632 (/4 1408)
>[   212.220] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.241] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.244] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.250] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.253] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.267] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.270] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.283] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.286] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.300] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.303] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.317] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.320] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.333] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.336] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.350] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.353] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.367] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.370] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.383] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.386] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.400] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.403] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.417] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.420] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.433] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.436] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.450] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.453] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.467] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.470] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.483] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.486] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.500] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.503] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.517] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.520] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.533] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.536] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.550] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.553] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.567] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.570] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.583] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.586] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.600] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.603] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.617] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.620] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd56b0]
>[   212.633] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd56b0] width 1366 pitch 5632 (/4 1408)
>[   212.637] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.654] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.657] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   212.667] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   212.669] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.683] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.686] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   212.700] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   212.703] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd5cd0]
>[   212.717] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd5cd0] width 1366 pitch 5632 (/4 1408)
>[   212.720] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   212.740] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   212.741] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   212.750] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   212.752] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   212.767] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   212.770] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   212.783] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   212.786] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   212.800] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   212.803] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   212.817] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   212.820] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   212.833] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   212.836] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   212.850] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   212.853] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   212.867] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   212.870] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   212.883] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   212.886] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   212.900] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   212.903] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   212.917] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   212.920] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   212.933] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   212.936] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   212.950] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   212.953] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   212.967] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   212.970] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   212.983] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   212.986] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   213.000] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   213.003] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   213.017] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   213.020] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   213.033] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   213.036] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   213.050] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   213.053] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   213.067] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   213.070] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   213.083] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   213.086] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   213.100] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   213.103] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   213.117] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   213.120] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bd54a0]
>[   213.133] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bd54a0] width 1366 pitch 5632 (/4 1408)
>[   213.136] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   213.153] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   213.156] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcaaf0]
>[   213.167] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcaaf0] width 1366 pitch 5632 (/4 1408)
>[   213.169] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   213.183] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   213.186] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcaaf0]
>[   213.200] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcaaf0] width 1366 pitch 5632 (/4 1408)
>[   213.203] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bbdfe0]
>[   213.217] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bbdfe0] width 1366 pitch 5632 (/4 1408)
>[   213.220] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bcaaf0]
>[   213.236] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bcaaf0] width 1366 pitch 5632 (/4 1408)
>[   213.244] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bdf1b0]
>[   213.293] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bdf1b0] width 1366 pitch 5632 (/4 1408)
>[   213.308] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x1bc9200]
>[   213.317] (II) RADEON(0): radeon_dri2_flip_event_handler:981 fevent[0x1bc9200] width 1366 pitch 5632 (/4 1408)
>[   224.943] (II) AIGLX: Suspending AIGLX clients for VT switch
>[   224.943] (II) RADEON(0): RADEONLeaveVT_KMS
>[   224.943] (II) RADEON(0): Ok, leaving now...

Actions: View

Attachments on bug 41592: 52125 | 52126 | 52909

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.