Attachment 52428 Details for Bug 1837 – patch for CLGD, X.Org 7.5

[patch] patch for CLGD, X.Org 7.5

patch.clgd (text/plain), 4.39 KB, created by Satoshi KImura on 2011-10-17 08:29:25 UTC

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Filename:

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Creator: Satoshi KImura

Created: 2011-10-17 08:29:25 UTC

Size: 4.39 KB

patch

obsolete

>--- src/alp_driver.c.orig	2009-07-28 14:10:51.000000000 +0900
>+++ src/alp_driver.c	2010-07-04 02:07:38.637501000 +0900
>@@ -119,6 +119,9 @@
> static void	AlpDisplayPowerManagementSet(ScrnInfoPtr pScrn,
> 											int PowerManagementMode, int flags);
> 
>+static void PC98CIRRUS755xEnable(ScrnInfoPtr pScrn);
>+static void PC98CIRRUS755xDisable(ScrnInfoPtr pScrn);
>+
> /*
>  * This is intentionally screen-independent.  It indicates the binding
>  * choice made in the first PreInit.
>@@ -153,6 +156,8 @@
> static int gd5446_MaxClocks[] = { 135100, 135100,  85500,  85500,      0 };
> static int gd5480_MaxClocks[] = { 135100, 200000, 200000, 135100, 135100 };
> static int gd7548_MaxClocks[] = {  80100,  80100,  80100,  80100,  80100 };
>+static int gd7555_MaxClocks[] = {  80100,  80100,  80100,  80100,  80100 };
>+static int gd7556_MaxClocks[] = {  80100,  80100,  80100,  80100,  80100 };
> 
> #ifdef XFree86LOADER
> 
>@@ -385,6 +390,11 @@
> 			break;
> 	}
> 	break;
>+
>+    case PCI_CHIP_GD7555:
>+    case PCI_CHIP_GD7556:
>+	videoram = 2048;   /*  for PC-9821 La13 etc.  */
>+	break;
>     }
> 
>     /* UNMap the Alp memory and MMIO areas */
>@@ -498,7 +508,7 @@
> 			      PCI_DEV_DEV(pCir->PciInfo),
> 			      PCI_DEV_FUNC(pCir->PciInfo));
> 
>-    if (xf86LoadSubModule(pScrn, "int10")) {
>+    if (!xf86IsPc98() && xf86LoadSubModule(pScrn, "int10")) {
> 	xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n");
> 	pInt = xf86InitInt10(pCir->pEnt->index);
> 	xf86FreeInt10(pInt);
>@@ -589,6 +599,16 @@
> 
> 	from = X_DEFAULT;
> 	pCir->HWCursor = FALSE;
>+
>+	switch (pCir->Chipset) {
>+	case PCI_CHIP_GD7555:
>+	case PCI_CHIP_GD7556:
>+	  pCir->HWCursor = TRUE;
>+	  break;
>+	default:
>+	  break;
>+	}
>+
> 	if (xf86GetOptValBool(pCir->Options, OPTION_HW_CURSOR, &pCir->HWCursor))
> 		from = X_CONFIG;
> 
>@@ -876,6 +896,12 @@
> 		case PCI_CHIP_GD7548:
> 		        p = gd7548_MaxClocks;
>                         break;
>+		case PCI_CHIP_GD7555:
>+		        p = gd7555_MaxClocks;
>+                        break;
>+		case PCI_CHIP_GD7556:
>+		        p = gd7556_MaxClocks;
>+                        break;
> 		}
> 		if (!p)
> 			return FALSE;
>@@ -1360,6 +1386,9 @@
> 
> 	vgaHWProtect(pScrn, FALSE);
> 
>+	if (xf86IsPc98())
>+		PC98CIRRUS755xEnable(pScrn);
>+
> 	return TRUE;
> }
> 
>@@ -1782,6 +1811,9 @@
> 
> 	AlpRestore(pScrn);
> 	vgaHWLock(hwp);
>+
>+	if (xf86IsPc98())
>+		PC98CIRRUS755xDisable(pScrn);
> }
> 
> 
>@@ -1819,6 +1851,9 @@
> 
> 	pScrn->vtSema = FALSE;
> 
>+	if (xf86IsPc98())
>+		PC98CIRRUS755xDisable(pScrn);
>+
> 	pScreen->CloseScreen = pCir->CloseScreen;
> 	return (*pScreen->CloseScreen)(scrnIndex, pScreen);
> }
>@@ -2081,3 +2116,52 @@
> 		   box.y2 - pScrn->virtualY);
>     }
> }
>+
>+static void
>+PC98CIRRUS755xEnable(ScrnInfoPtr pScrn)  /*  enter_aile()  */
>+{
>+   unsigned int  index,data;
>+   vgaHWPtr hwp = VGAHWPTR(pScrn);
>+
>+   outb(0xfac, 0x02);
>+
>+   outb(0x68, 0x0e);
>+   outb(0x6a, 0x07);
>+   outb(0x6a, 0x8f);
>+   outb(0x6a, 0x06);
>+
>+   outw(VGA_SEQ_INDEX, 0x1206);         /*  unlock cirrus special  */
>+
>+   index = hwp->IOBase + VGA_CRTC_INDEX_OFFSET;
>+   data  = hwp->IOBase + VGA_CRTC_DATA_OFFSET;
>+   outb(index, 0x3c);
>+   outb(data,  inb(data) & 0xef);
>+   outb(index, 0x1a);
>+   outb(data,  inb(data) & 0xf3);
>+}
>+
>+static void
>+PC98CIRRUS755xDisable(ScrnInfoPtr pScrn)  /*  leave_aile()  */
>+{
>+   unsigned int  index,data;
>+   vgaHWPtr hwp = VGAHWPTR(pScrn);
>+
>+   outw(VGA_SEQ_INDEX, 0x1206);         /*  unlock cirrus special  */
>+
>+   index = hwp->IOBase + VGA_CRTC_INDEX_OFFSET;
>+   data  = hwp->IOBase + VGA_CRTC_DATA_OFFSET;
>+   outb(index, 0x3c);
>+   outb(data,  0x71);
>+   outb(index, 0x1a);
>+   outb(data,  inb(data) | 0x0c);
>+
>+   outb(0xfac,0x00);
>+
>+   outb(0x68, 0x0f);
>+   outb(0x6a, 0x07);
>+   outb(0x6a, 0x8e);
>+   outb(0x6a, 0x21);
>+   outb(0x6a, 0x69);
>+   outb(0x6a, 0x06);
>+}
>+
>--- src/cir_driver.c.orig	2009-07-28 14:10:51.000000000 +0900
>+++ src/cir_driver.c	2010-07-04 02:07:45.074826000 +0900
>@@ -90,6 +90,8 @@
> 	{ PCI_CHIP_GD5464BD,	"CL-GD5464BD" },
> 	{ PCI_CHIP_GD5465,		"CL-GD5465" },
> 	{ PCI_CHIP_GD7548,              "CL-GD7548" },
>+	{ PCI_CHIP_GD7555,              "CL-GD7555" },
>+	{ PCI_CHIP_GD7556,              "CL-GD7556" },
> 	{-1,					NULL }
> };
> 
>@@ -107,6 +109,8 @@
> 	{ PCI_CHIP_GD5464BD,PCI_CHIP_GD5464BD,	RES_SHARED_VGA },
> 	{ PCI_CHIP_GD5465,	PCI_CHIP_GD5465,	RES_SHARED_VGA },
> 	{ PCI_CHIP_GD7548,	PCI_CHIP_GD7548,	RES_SHARED_VGA },
>+	{ PCI_CHIP_GD7555,	PCI_CHIP_GD7555,	RES_SHARED_VGA },
>+	{ PCI_CHIP_GD7556,	PCI_CHIP_GD7556,	RES_SHARED_VGA },
> 	{ -1,				-1,					RES_UNDEFINED}
> };
>

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