Attachment 52700 Details for Bug 40221 – possible fix

[patch] possible fix

0001-drm-radeon-kms-cayman-blit-specify-CP_COHER_CNTL2-wi.patch (text/plain), 1.82 KB, created by Alex Deucher on 2011-10-24 10:01:19 UTC

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Creator: Alex Deucher

Created: 2011-10-24 10:01:19 UTC

Size: 1.82 KB

patch

obsolete

>From 7326633df4b1e5e54aca926552f212080992421d Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexander.deucher@amd.com>
>Date: Mon, 24 Oct 2011 12:57:57 -0400
>Subject: [PATCH] drm/radeon/kms/cayman/blit: specify CP_COHER_CNTL2 with surface_sync
>
>CP_COHER_CNTL2 has to be programmed manually when submitting packets
>to the ring directly rather than programmed via an IB.
>
>May fix:
>https://bugs.freedesktop.org/show_bug.cgi?id=40221
>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>---
> drivers/gpu/drm/radeon/evergreen_blit_kms.c |   11 +++++++++++
> 1 files changed, 11 insertions(+), 0 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
>index 9ebbdc5..57b036e 100644
>--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
>+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
>@@ -94,6 +94,15 @@ cp_set_surface_sync(struct radeon_device *rdev,
> 	else
> 		cp_coher_size = ((size + 255) >> 8);
> 
>+	if (rdev->family >= CHIP_CAYMAN) {
>+		/* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync
>+		 * to the RB directly. For IBs, the CP programs this as part of the
>+		 * surface_sync packet.
>+		 */
>+		radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
>+		radeon_ring_write(rdev, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);
>+		radeon_ring_write(rdev, 0); /* CP_COHER_CNTL2 */
>+	}
> 	radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
> 	radeon_ring_write(rdev, sync_type);
> 	radeon_ring_write(rdev, cp_coher_size);
>@@ -626,6 +635,8 @@ int evergreen_blit_init(struct radeon_device *rdev)
> 	rdev->r600_blit.ring_size_common += 10; /* fence emit for done copy */
> 
> 	rdev->r600_blit.ring_size_per_loop = 74;
>+	if (rdev->family >= CHIP_CAYMAN)
>+		rdev->r600_blit.ring_size_per_loop += 9; /* additional DWs for surface sync */
> 
> 	rdev->r600_blit.max_dim = 16384;
> 
>-- 
>1.7.1.1
>

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Attachments on bug 40221: 50369 | 50370 | 50371 | 50375 | 50378 | 50404 | 50461 | 52630 | 52635 | 52690 | 52697 | 52699 | 52700 | 52762

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