Attachment 52708 Details for Bug 42174 – intel_reg_dumper_19VGA1_15VGA2.not_working: 15" L150P plugged into VGA2 does not work

intel_reg_dumper_19VGA1_15VGA2.not_working: 15" L150P plugged into VGA2 does not work

intel_reg_dumper_19VGA1_15VGA2.not_working (text/plain), 11.20 KB, created by Trey Ramsay on 2011-10-24 14:05:20 UTC

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Creator: Trey Ramsay

Created: 2011-10-24 14:05:20 UTC

Size: 11.20 KB

patch

obsolete

>                    PGETBL_CTL: 0x00000000
>               GEN6_INSTDONE_1: 0xfffffffe
>               GEN6_INSTDONE_2: 0xffffffff
>                  CPU_VGACNTRL: 0x80000000 (disabled)
>    DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
>                     RR_HW_CTL: 0x00000000 (low 0, high 0)
>                FDI_PLL_BIOS_0: 0xffffffff
>                FDI_PLL_BIOS_1: 0xffffffff
>                FDI_PLL_BIOS_2: 0xffffffff
>       DISPLAY_PORT_PLL_BIOS_0: 0xffffffff
>       DISPLAY_PORT_PLL_BIOS_1: 0xffffffff
>       DISPLAY_PORT_PLL_BIOS_2: 0xffffffff
>              FDI_PLL_FREQ_CTL: 0xffffffff
>                     PIPEACONF: 0xc0000000 (enabled, active, 8bpc)
>                      HTOTAL_A: 0x069704ff (1280 active, 1688 total)
>                      HBLANK_A: 0x069704ff (1280 start, 1688 end)
>                       HSYNC_A: 0x059f052f (1328 start, 1440 end)
>                      VTOTAL_A: 0x042903ff (1024 active, 1066 total)
>                      VBLANK_A: 0x042903ff (1024 start, 1066 end)
>                       VSYNC_A: 0x04030400 (1025 start, 1028 end)
>                  VSYNCSHIFT_A: 0x00000000
>                      PIPEASRC: 0x04ff03ff (1280, 1024)
>                 PIPEA_DATA_M1: 0x7e278d00 (TU 64, val 0x278d00 2592000)
>                 PIPEA_DATA_N1: 0x0041eb00 (val 0x41eb00 4320000)
>                 PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_M1: 0x0001a5e0 (val 0x1a5e0 108000)
>                 PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>                 PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPACNTR: 0xd8004000 (enabled)
>                      DSPABASE: 0x00000000
>                    DSPASTRIDE: 0x00001400 (80)
>                      DSPASURF: 0x00063000
>                   DSPATILEOFF: 0x00000000 (0, 0)
>                     PIPEBCONF: 0xc0000000 (enabled, active, 8bpc)
>                      HTOTAL_B: 0x053f03ff (1024 active, 1344 total)
>                      HBLANK_B: 0x053f03ff (1024 start, 1344 end)
>                       HSYNC_B: 0x049f0417 (1048 start, 1184 end)
>                      VTOTAL_B: 0x032502ff (768 active, 806 total)
>                      VBLANK_B: 0x032502ff (768 start, 806 end)
>                       VSYNC_B: 0x03080302 (771 start, 777 end)
>                  VSYNCSHIFT_B: 0x00000000
>                      DSPBCNTR: 0xd8004000 (enabled)
>                      DSPBBASE: 0x00000000
>                    DSPBSTRIDE: 0x00001400 (80)
>                      DSPBSURF: 0x00063000
>                   DSPBTILEOFF: 0x00000000 (0, 0)
>                      PIPEBSRC: 0x03ff02ff (1024, 768)
>                 PIPEB_DATA_M1: 0x7e2f9b80 (TU 64, val 0x2f9b80 3120000)
>                 PIPEB_DATA_N1: 0x0083d600 (val 0x83d600 8640000)
>                 PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_M1: 0x0001fbd0 (val 0x1fbd0 130000)
>                 PIPEB_LINK_N1: 0x00083d60 (val 0x83d60 540000)
>                 PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
>                     PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFA_CTL_2: 0x00007e00 (vscale 0.984375)
>                     PFA_CTL_3: 0x00003f00 (vscale initial phase 0.492188)
>                     PFA_CTL_4: 0x00007d80 (hscale 0.980469)
>                   PFA_WIN_POS: 0x00000000 (0, 0)
>                  PFA_WIN_SIZE: 0x00000000 (0, 0)
>                     PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFB_CTL_2: 0x00007e80 (vscale 0.988281)
>                     PFB_CTL_3: 0x00003f40 (vscale initial phase 0.494141)
>                     PFB_CTL_4: 0x00007e00 (hscale 0.984375)
>                   PFB_WIN_POS: 0x00000000 (0, 0)
>                  PFB_WIN_SIZE: 0x00000000 (0, 0)
>              PCH_DREF_CONTROL: 0x00001400 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable)
>               PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>              PCH_DPLL_TMR_CFG: 0x0271186a
>                PCH_SSC4_PARMS: 0x01204860
>            PCH_SSC4_AUX_PARMS: 0x000029c5
>                  PCH_DPLL_SEL: 0x00000098 (TransA DPLL enable (DPLL A), TransB DPLL enable (DPLL B))
>           PCH_DPLL_ANALOG_CTL: 0x00008000
>                    PCH_DPLL_A: 0x84040004 (enable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 3, FPA1 P1 3, refclk default 120Mhz, sdvo/hdmi mul 1)
>                    PCH_DPLL_B: 0xc4020202 (enable, sdvo high speed yes, mode (null), p2 (null), FPA0 P1 2, FPA1 P1 2, refclk default 120Mhz, sdvo/hdmi mul 2)
>                      PCH_FPA0: 0x00010c09 (n = 1, m1 = 12, m2 = 9)
>                      PCH_FPA1: 0x00010c09 (n = 1, m1 = 12, m2 = 9)
>                      PCH_FPB0: 0x00020e05 (n = 2, m1 = 14, m2 = 5)
>                      PCH_FPB1: 0x00020e05 (n = 2, m1 = 14, m2 = 5)
>                TRANS_HTOTAL_A: 0x069704ff (1280 active, 1688 total)
>                TRANS_HBLANK_A: 0x069704ff (1280 start, 1688 end)
>                 TRANS_HSYNC_A: 0x059f052f (1328 start, 1440 end)
>                TRANS_VTOTAL_A: 0x042903ff (1024 active, 1066 total)
>                TRANS_VBLANK_A: 0x042903ff (1024 start, 1066 end)
>                 TRANS_VSYNC_A: 0x04030400 (1025 start, 1028 end)
>                TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_B: 0x053f03ff (1024 active, 1344 total)
>                TRANS_HBLANK_B: 0x053f03ff (1024 start, 1344 end)
>                 TRANS_HSYNC_B: 0x049f0417 (1048 start, 1184 end)
>                TRANS_VTOTAL_B: 0x032502ff (768 active, 806 total)
>                TRANS_VBLANK_B: 0x032502ff (768 start, 806 end)
>                 TRANS_VSYNC_B: 0x03080302 (771 start, 777 end)
>                TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
>                 TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
>                TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_VBLANK_C: 0x00000000 (1 start, 1 end)
>                 TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
>                TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                    TRANSACONF: 0xc0000000 (enable, active)
>                    TRANSBCONF: 0xc0000000 (enable, active)
>                    TRANSCCONF: 0x00000000 (disable, inactive)
>                   FDI_TXA_CTL: 0xb00c4000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis 0dB, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXB_CTL: 0xb00c4000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis 0dB, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_RXA_CTL: 0x80082350 (enable, train pattern not train, port width X2, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXB_CTL: 0x80082350 (enable, train pattern not train, port width X2, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXC_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
>                  FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
>                  FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
>                  FDI_RXC_MISC: 0x00000080 (FDI Delay 128)
>               FDI_RXA_TUSIZE1: 0x7e000000
>               FDI_RXA_TUSIZE2: 0x7e000000
>               FDI_RXB_TUSIZE1: 0x7e000000
>               FDI_RXB_TUSIZE2: 0x7e000000
>               FDI_RXC_TUSIZE1: 0x7e000000
>               FDI_RXC_TUSIZE2: 0x7e000000
>                 FDI_PLL_CTL_1: 0x7e000000
>                 FDI_PLL_CTL_2: 0x7e000000
>                   FDI_RXA_IIR: 0x00000000
>                   FDI_RXA_IMR: 0x000008ff
>                   FDI_RXB_IIR: 0x00000000
>                   FDI_RXB_IMR: 0x000008ff
>                      PCH_ADPA: 0x83f40018 (enabled, transcoder A, +hsync, +vsync)
>                         HDMIB: 0xa0000004 (enabled pipe B 8bpc SDVO DVI audio disabled -vsync -hsync detected)
>                         HDMIC: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
>                         HDMID: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
>                      PCH_LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>                     CPU_eDP_A: 0x00000018
>                      PCH_DP_B: 0x00000004
>                      PCH_DP_C: 0x00000000
>                      PCH_DP_D: 0x00000000
>                TRANS_DP_CTL_A: 0x60000018 (disable port (null) 8bpc +vsync +hsync)
>                TRANS_DP_CTL_B: 0x60000018 (disable port (null) 8bpc +vsync +hsync)
>                TRANS_DP_CTL_C: 0x60000018 (disable port (null) 8bpc +vsync +hsync)
>              BLC_PWM_CPU_CTL2: 0x00000000
>               BLC_PWM_CPU_CTL: 0x00000000
>              BLC_PWM_PCH_CTL1: 0x00000000
>              BLC_PWM_PCH_CTL2: 0x00000000
>                 PCH_PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>                PCH_PP_CONTROL: 0xabcd0000 (blacklight disabled, do not power down on reset, panel off)
>              PCH_PP_ON_DELAYS: 0x00000000
>             PCH_PP_OFF_DELAYS: 0x00000000
>                PCH_PP_DIVISOR: 0x00186904

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Attachments on bug 42174: 52708 | 52712 | 52714 | 52715 | 52760 | 52969 | 52970 | 53752 | 54122 | 54127

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