Attachment 53013 Details for Bug 42484 – intel_reg_dump of a non-working configuration

intel_reg_dump of a non-working configuration

reg_dump-nonworking.txt (text/plain), 11.41 KB, created by Rogan Dawes on 2011-11-01 11:28:00 UTC

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Creator: Rogan Dawes

Created: 2011-11-01 11:28:00 UTC

Size: 11.41 KB

patch

obsolete

>                    PGETBL_CTL: 0x00000000
>               GEN6_INSTDONE_1: 0xfffffffe
>               GEN6_INSTDONE_2: 0xffffffff
>                  CPU_VGACNTRL: 0x80000000 (disabled)
>    DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
>                     RR_HW_CTL: 0x00000000 (low 0, high 0)
>                FDI_PLL_BIOS_0: 0xffffffff
>                FDI_PLL_BIOS_1: 0xffffffff
>                FDI_PLL_BIOS_2: 0xffffffff
>       DISPLAY_PORT_PLL_BIOS_0: 0xffffffff
>       DISPLAY_PORT_PLL_BIOS_1: 0xffffffff
>       DISPLAY_PORT_PLL_BIOS_2: 0xffffffff
>              FDI_PLL_FREQ_CTL: 0xffffffff
>                     PIPEACONF: 0xc0000000 (enabled, active, 8bpc)
>                      HTOTAL_A: 0x072f068f (1680 active, 1840 total)
>                      HBLANK_A: 0x072f068f (1680 start, 1840 end)
>                       HSYNC_A: 0x06df06bf (1728 start, 1760 end)
>                      VTOTAL_A: 0x04370419 (1050 active, 1080 total)
>                      VBLANK_A: 0x04370419 (1050 start, 1080 end)
>                       VSYNC_A: 0x0422041c (1053 start, 1059 end)
>                  VSYNCSHIFT_A: 0x00000000
>                      PIPEASRC: 0x068f0419 (1680, 1050)
>                 PIPEA_DATA_M1: 0x7e2b9440 (TU 64, val 0x2b9440 2856000)
>                 PIPEA_DATA_N1: 0x0041eb00 (val 0x41eb00 4320000)
>                 PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_M1: 0x0001d0d8 (val 0x1d0d8 119000)
>                 PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>                 PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPACNTR: 0xd8004400 (enabled)
>                      DSPABASE: 0x00001e00
>                    DSPASTRIDE: 0x00003a00 (232)
>                      DSPASURF: 0x0e8e1000
>                   DSPATILEOFF: 0x00000780 (1920, 0)
>                     PIPEBCONF: 0xc0000000 (enabled, active, 8bpc)
>                      HTOTAL_B: 0x081f077f (1920 active, 2080 total)
>                      HBLANK_B: 0x081f077f (1920 start, 2080 end)
>                       HSYNC_B: 0x07cf07af (1968 start, 2000 end)
>                      VTOTAL_B: 0x04d204af (1200 active, 1235 total)
>                      VBLANK_B: 0x04d204af (1200 start, 1235 end)
>                       VSYNC_B: 0x04b804b2 (1203 start, 1209 end)
>                  VSYNCSHIFT_B: 0x00000000
>                      DSPBCNTR: 0xd8004400 (enabled)
>                      DSPBBASE: 0x00000000
>                    DSPBSTRIDE: 0x00003a00 (232)
>                      DSPBSURF: 0x0e8e1000
>                   DSPBTILEOFF: 0x00000000 (0, 0)
>                      PIPEBSRC: 0x077f04af (1920, 1200)
>                 PIPEB_DATA_M1: 0x7e386580 (TU 64, val 0x386580 3696000)
>                 PIPEB_DATA_N1: 0x0041eb00 (val 0x41eb00 4320000)
>                 PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_M1: 0x00025990 (val 0x25990 154000)
>                 PIPEB_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>                 PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
>                     PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFA_CTL_2: 0x00007df3 (vscale 0.983978)
>                     PFA_CTL_3: 0x00003ef9 (vscale initial phase 0.491974)
>                     PFA_CTL_4: 0x00007cb8 (hscale 0.974365)
>                   PFA_WIN_POS: 0x00000000 (0, 0)
>                  PFA_WIN_SIZE: 0x00000000 (0, 0)
>                     PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFB_CTL_2: 0x00007da8 (vscale 0.981689)
>                     PFB_CTL_3: 0x00003ed4 (vscale initial phase 0.490845)
>                     PFB_CTL_4: 0x00007c40 (hscale 0.970703)
>                   PFB_WIN_POS: 0x00000000 (0, 0)
>                  PFB_WIN_SIZE: 0x00000000 (0, 0)
>              PCH_DREF_CONTROL: 0x00001400 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable)
>               PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>              PCH_DPLL_TMR_CFG: 0x0271186a
>                PCH_SSC4_PARMS: 0x01204860
>            PCH_SSC4_AUX_PARMS: 0x000029c5
>                  PCH_DPLL_SEL: 0x00000098 (TransA DPLL enable (DPLL A), TransB DPLL enable (DPLL B))
>           PCH_DPLL_ANALOG_CTL: 0x00008000
>                    PCH_DPLL_A: 0xc4020002 (enable, sdvo high speed yes, mode (null), p2 (null), FPA0 P1 2, FPA1 P1 2, refclk default 120Mhz, sdvo/hdmi mul 1)
>                    PCH_DPLL_B: 0xc4020002 (enable, sdvo high speed yes, mode (null), p2 (null), FPA0 P1 2, FPA1 P1 2, refclk default 120Mhz, sdvo/hdmi mul 1)
>                      PCH_FPA0: 0x00020c07 (n = 2, m1 = 12, m2 = 7)
>                      PCH_FPA1: 0x00020c07 (n = 2, m1 = 12, m2 = 7)
>                      PCH_FPB0: 0x00021106 (n = 2, m1 = 17, m2 = 6)
>                      PCH_FPB1: 0x00021106 (n = 2, m1 = 17, m2 = 6)
>                TRANS_HTOTAL_A: 0x072f068f (1680 active, 1840 total)
>                TRANS_HBLANK_A: 0x072f068f (1680 start, 1840 end)
>                 TRANS_HSYNC_A: 0x06df06bf (1728 start, 1760 end)
>                TRANS_VTOTAL_A: 0x04370419 (1050 active, 1080 total)
>                TRANS_VBLANK_A: 0x04370419 (1050 start, 1080 end)
>                 TRANS_VSYNC_A: 0x0422041c (1053 start, 1059 end)
>                TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_B: 0x081f077f (1920 active, 2080 total)
>                TRANS_HBLANK_B: 0x081f077f (1920 start, 2080 end)
>                 TRANS_HSYNC_B: 0x07cf07af (1968 start, 2000 end)
>                TRANS_VTOTAL_B: 0x04d204af (1200 active, 1235 total)
>                TRANS_VBLANK_B: 0x04d204af (1200 start, 1235 end)
>                 TRANS_VSYNC_B: 0x04b804b2 (1203 start, 1209 end)
>                TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
>                 TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
>                TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_VBLANK_C: 0x00000000 (1 start, 1 end)
>                 TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
>                TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                    TRANSACONF: 0xc0000000 (enable, active)
>                    TRANSBCONF: 0xc0000000 (enable, active)
>                    TRANSCCONF: 0x00000000 (disable, inactive)
>                   FDI_TXA_CTL: 0xb00c4000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis 0dB, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXB_CTL: 0xb00c4000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis 0dB, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable)
>                   FDI_RXA_CTL: 0x80082350 (enable, train pattern not train, port width X2, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXB_CTL: 0x80082350 (enable, train pattern not train, port width X2, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXC_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
>                  FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
>                  FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
>                  FDI_RXC_MISC: 0x00000080 (FDI Delay 128)
>               FDI_RXA_TUSIZE1: 0x7e000000
>               FDI_RXA_TUSIZE2: 0x7e000000
>               FDI_RXB_TUSIZE1: 0x7e000000
>               FDI_RXB_TUSIZE2: 0x7e000000
>               FDI_RXC_TUSIZE1: 0x7e000000
>               FDI_RXC_TUSIZE2: 0x7e000000
>                 FDI_PLL_CTL_1: 0x7e000000
>                 FDI_PLL_CTL_2: 0x7e000000
>                   FDI_RXA_IIR: 0x00000000
>                   FDI_RXA_IMR: 0x000008ff
>                   FDI_RXB_IIR: 0x00000000
>                   FDI_RXB_IMR: 0x000008ff
>                      PCH_ADPA: 0x00f40000 (disabled, transcoder A, -hsync, -vsync)
>                         HDMIB: 0x8000088c (enabled pipe A 8bpc TMDS DVI audio disabled -vsync +hsync detected)
>                         HDMIC: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
>                         HDMID: 0xa0000acc (enabled pipe B 8bpc TMDS HDMI audio enabled -vsync +hsync detected)
>                      PCH_LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>                     CPU_eDP_A: 0x00000018
>                      PCH_DP_B: 0x00000004
>                      PCH_DP_C: 0x00000004
>                      PCH_DP_D: 0x00000004
>                TRANS_DP_CTL_A: 0x60000018 (disable port none 8bpc +vsync +hsync)
>                TRANS_DP_CTL_B: 0x60000018 (disable port none 8bpc +vsync +hsync)
>                TRANS_DP_CTL_C: 0x60000018 (disable port none 8bpc +vsync +hsync)
>              BLC_PWM_CPU_CTL2: 0x00000000
>               BLC_PWM_CPU_CTL: 0x00000000
>              BLC_PWM_PCH_CTL1: 0x00000000
>              BLC_PWM_PCH_CTL2: 0x00000000
>                 PCH_PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>                PCH_PP_CONTROL: 0xabcd0000 (blacklight disabled, do not power down on reset, panel off)
>              PCH_PP_ON_DELAYS: 0x00000000
>             PCH_PP_OFF_DELAYS: 0x00000000
>                PCH_PP_DIVISOR: 0x00186904

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Attachments on bug 42484: 53012 | 53013 | 53014 | 53015

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