Attachment 53247 Details for Bug 41838 – flush HDP via the ring

[patch] flush HDP via the ring

0001-drm-radeon-kms-Flush-HDP-cache-via-the-ring-for-ever.patch (text/plain), 5.36 KB, created by Alex Deucher on 2011-11-07 06:51:54 UTC

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Creator: Alex Deucher

Created: 2011-11-07 06:51:54 UTC

Size: 5.36 KB

patch

obsolete

>From c0f06444c41965f346aa7312aace32033c382791 Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexander.deucher@amd.com>
>Date: Mon, 7 Nov 2011 09:41:33 -0500
>Subject: [PATCH] drm/radeon/kms: Flush HDP cache via the ring for evergreen+
>
>On r6xx/r7xx, HDP flushes only seemed to work via MMIO.  On
>evergreen, one user reports a hang in certain cases when flushing
>via MMIO.
>
>Might fix:
>https://bugs.freedesktop.org/show_bug.cgi?id=41838
>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>---
> drivers/gpu/drm/radeon/evergreen_blit_kms.c |    4 ++--
> drivers/gpu/drm/radeon/r600.c               |    6 ++++++
> drivers/gpu/drm/radeon/r600_blit_kms.c      |    4 ++--
> drivers/gpu/drm/radeon/radeon_asic.c        |    8 ++++----
> 4 files changed, 14 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
>index 914e5af..2edfae4 100644
>--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
>+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
>@@ -625,9 +625,9 @@ int evergreen_blit_init(struct radeon_device *rdev)
> 	rdev->r600_blit.primitives.set_default_state = set_default_state;
> 
> 	rdev->r600_blit.ring_size_common = 55; /* shaders + def state */
>-	rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
>+	rdev->r600_blit.ring_size_common += 18; /* fence emit for VB IB */
> 	rdev->r600_blit.ring_size_common += 5; /* done copy */
>-	rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
>+	rdev->r600_blit.ring_size_common += 18; /* fence emit for done copy */
> 
> 	rdev->r600_blit.ring_size_per_loop = 74;
> 	if (rdev->family >= CHIP_CAYMAN)
>diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
>index 4b0eb27..6b6b0ec 100644
>--- a/drivers/gpu/drm/radeon/r600.c
>+++ b/drivers/gpu/drm/radeon/r600.c
>@@ -2331,6 +2331,9 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
> 		radeon_ring_write(rdev, 0xFFFFFFFF);
> 		radeon_ring_write(rdev, 0);
> 		radeon_ring_write(rdev, 10); /* poll interval */
>+		/* FLUSH HDP cache */
>+		radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
>+		radeon_ring_write(rdev, 1);
> 		/* EVENT_WRITE_EOP - flush caches, send int */
> 		radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
> 		radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
>@@ -2353,6 +2356,9 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
> 		radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
> 		radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
> 		radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
>+		/* FLUSH HDP cache */
>+		radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
>+		radeon_ring_write(rdev, 1);
> 		/* Emit fence sequence & fire IRQ */
> 		radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
> 		radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
>diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
>index e09d281..d891b2e 100644
>--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
>+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
>@@ -503,9 +503,9 @@ int r600_blit_init(struct radeon_device *rdev)
> 	rdev->r600_blit.primitives.set_default_state = set_default_state;
> 
> 	rdev->r600_blit.ring_size_common = 40; /* shaders + def state */
>-	rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
>+	rdev->r600_blit.ring_size_common += 18; /* fence emit for VB IB */
> 	rdev->r600_blit.ring_size_common += 5; /* done copy */
>-	rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
>+	rdev->r600_blit.ring_size_common += 18; /* fence emit for done copy */
> 
> 	rdev->r600_blit.ring_size_per_loop = 76;
> 	/* set_render_target emits 2 extra dwords on rv6xx */
>diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
>index a2e1eae..786c578 100644
>--- a/drivers/gpu/drm/radeon/radeon_asic.c
>+++ b/drivers/gpu/drm/radeon/radeon_asic.c
>@@ -782,7 +782,7 @@ static struct radeon_asic evergreen_asic = {
> 	.hpd_fini = &evergreen_hpd_fini,
> 	.hpd_sense = &evergreen_hpd_sense,
> 	.hpd_set_polarity = &evergreen_hpd_set_polarity,
>-	.ioctl_wait_idle = r600_ioctl_wait_idle,
>+	.ioctl_wait_idle = NULL,
> 	.gui_idle = &r600_gui_idle,
> 	.pm_misc = &evergreen_pm_misc,
> 	.pm_prepare = &evergreen_pm_prepare,
>@@ -829,7 +829,7 @@ static struct radeon_asic sumo_asic = {
> 	.hpd_fini = &evergreen_hpd_fini,
> 	.hpd_sense = &evergreen_hpd_sense,
> 	.hpd_set_polarity = &evergreen_hpd_set_polarity,
>-	.ioctl_wait_idle = r600_ioctl_wait_idle,
>+	.ioctl_wait_idle = NULL,
> 	.gui_idle = &r600_gui_idle,
> 	.pm_misc = &evergreen_pm_misc,
> 	.pm_prepare = &evergreen_pm_prepare,
>@@ -876,7 +876,7 @@ static struct radeon_asic btc_asic = {
> 	.hpd_fini = &evergreen_hpd_fini,
> 	.hpd_sense = &evergreen_hpd_sense,
> 	.hpd_set_polarity = &evergreen_hpd_set_polarity,
>-	.ioctl_wait_idle = r600_ioctl_wait_idle,
>+	.ioctl_wait_idle = NULL,
> 	.gui_idle = &r600_gui_idle,
> 	.pm_misc = &evergreen_pm_misc,
> 	.pm_prepare = &evergreen_pm_prepare,
>@@ -923,7 +923,7 @@ static struct radeon_asic cayman_asic = {
> 	.hpd_fini = &evergreen_hpd_fini,
> 	.hpd_sense = &evergreen_hpd_sense,
> 	.hpd_set_polarity = &evergreen_hpd_set_polarity,
>-	.ioctl_wait_idle = r600_ioctl_wait_idle,
>+	.ioctl_wait_idle = NULL,
> 	.gui_idle = &r600_gui_idle,
> 	.pm_misc = &evergreen_pm_misc,
> 	.pm_prepare = &evergreen_pm_prepare,
>-- 
>1.7.3.4
>

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