Attachment 53264 Details for Bug 42625 – fix swizzle detection on gen3/4

[patch] fix swizzle detection on gen3/4

swizzle-fix.patch (text/plain), 2.10 KB, created by Daniel Vetter on 2011-11-07 11:21:18 UTC

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Creator: Daniel Vetter

Created: 2011-11-07 11:21:18 UTC

Size: 2.10 KB

patch

obsolete

>diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
>index 31d334d..3a3ebaf 100644
>--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
>+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
>@@ -107,10 +107,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
> 		 */
> 		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
> 		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
>-	} else if (IS_MOBILE(dev)) {
>+	} else if (!(IS_G33(dev) || IS_G4X(dev))) {
> 		uint32_t dcc;
> 
>-		/* On mobile 9xx chipsets, channel interleave by the CPU is
>+		/* On 9xx chipsets, channel interleave by the CPU is
> 		 * determined by DCC.  For single-channel, neither the CPU
> 		 * nor the GPU do swizzling.  For dual channel interleaved,
> 		 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
>@@ -150,26 +150,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
> 			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> 		}
> 	} else {
>-		/* The 965, G33, and newer, have a very flexible memory
>-		 * configuration.  It will enable dual-channel mode
>-		 * (interleaving) on as much memory as it can, and the GPU
>-		 * will additionally sometimes enable different bit 6
>-		 * swizzling for tiled objects from the CPU.
>-		 *
>-		 * Here's what I found on the G965:
>-		 *    slot fill         memory size  swizzling
>-		 * 0A   0B   1A   1B    1-ch   2-ch
>-		 * 512  0    0    0     512    0     O
>-		 * 512  0    512  0     16     1008  X
>-		 * 512  0    0    512   16     1008  X
>-		 * 0    512  0    512   16     1008  X
>-		 * 1024 1024 1024 0     2048   1024  O
>-		 *
>-		 * We could probably detect this based on either the DRB
>-		 * matching, which was the case for the swizzling required in
>-		 * the table above, or from the 1-ch value being less than
>-		 * the minimum size of a rank.
>-		 */
>+		/* GPUs with VT-d support don't have bit17 swizzling anymore for
>+		 * rather obvious reasons. Swizzling seems to be enabled when
>+		 * both channels have the same configuration, no cpu (bit11)
>+		 * swizzling happens in addition. */
> 		if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
> 			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
> 			swizzle_y = I915_BIT_6_SWIZZLE_NONE;

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Attachments on bug 42625: 53188 | 53189 | 53190 | 53191 | 53203 | 53232 | 53264

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