Attachment 53567 Details for Bug 42943 – the log from intel_reg_dumper

the log from intel_reg_dumper

intel_reg_dumper .log (text/plain), 11.44 KB, created by Guang Yang on 2011-11-15 02:13:59 UTC

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Creator: Guang Yang

Created: 2011-11-15 02:13:59 UTC

Size: 11.44 KB

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obsolete

>                    PGETBL_CTL: 0x00000000
>               GEN6_INSTDONE_1: 0xfffffffe
>               GEN6_INSTDONE_2: 0x00000000
>                  CPU_VGACNTRL: 0x80000000 (disabled)
>    DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
>                     RR_HW_CTL: 0x00000000 (low 0, high 0)
>                FDI_PLL_BIOS_0: 0x00000000
>                FDI_PLL_BIOS_1: 0x00000000
>                FDI_PLL_BIOS_2: 0x00000000
>       DISPLAY_PORT_PLL_BIOS_0: 0x00000000
>       DISPLAY_PORT_PLL_BIOS_1: 0x00000000
>       DISPLAY_PORT_PLL_BIOS_2: 0x00000000
>              FDI_PLL_FREQ_CTL: 0x00000000
>                     PIPEACONF: 0xc0000000 (enabled, active, 8bpc)
>                      HTOTAL_A: 0x089f07ff (2048 active, 2208 total)
>                      HBLANK_A: 0x089f07ff (2048 start, 2208 end)
>                       HSYNC_A: 0x084f082f (2096 start, 2128 end)
>                      VTOTAL_A: 0x052404ff (1280 active, 1317 total)
>                      VBLANK_A: 0x052404ff (1280 start, 1317 end)
>                       VSYNC_A: 0x05080502 (1283 start, 1289 end)
>                  VSYNCSHIFT_A: 0x00000000
>                      PIPEASRC: 0x07ff04ff (2048, 1280)
>                 PIPEA_DATA_M1: 0x7e3fcff0 (TU 64, val 0x3fcff0 4182000)
>                 PIPEA_DATA_N1: 0x0062e080 (val 0x62e080 6480000)
>                 PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_M1: 0x0002a8aa (val 0x2a8aa 174250)
>                 PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>                 PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPACNTR: 0xd8004000 (enabled)
>                      DSPABASE: 0x00000000
>                    DSPASTRIDE: 0x00002800 (160)
>                      DSPASURF: 0x00063000
>                   DSPATILEOFF: 0x00000000 (0, 0)
>                     PIPEBCONF: 0xc0000000 (enabled, active, 8bpc)
>                      HTOTAL_B: 0x0a9f09ff (2560 active, 2720 total)
>                      HBLANK_B: 0x0a9f09ff (2560 start, 2720 end)
>                       HSYNC_B: 0x0a4f0a2f (2608 start, 2640 end)
>                      VTOTAL_B: 0x066d063f (1600 active, 1646 total)
>                      VBLANK_B: 0x066d063f (1600 start, 1646 end)
>                       VSYNC_B: 0x06480642 (1603 start, 1609 end)
>                  VSYNCSHIFT_B: 0x00000000
>                      DSPBCNTR: 0xd8004000 (enabled)
>                      DSPBBASE: 0x00000000
>                    DSPBSTRIDE: 0x00002800 (160)
>                      DSPBSURF: 0x00063000
>                   DSPBTILEOFF: 0x00000000 (0, 0)
>                      PIPEBSRC: 0x09ff063f (2560, 1600)
>                 PIPEB_DATA_M1: 0x7e622500 (TU 64, val 0x622500 6432000)
>                 PIPEB_DATA_N1: 0x0083d600 (val 0x83d600 8640000)
>                 PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_M1: 0x000416e0 (val 0x416e0 268000)
>                 PIPEB_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>                 PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
>                     PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFA_CTL_2: 0x00007d80 (vscale 0.980469)
>                     PFA_CTL_3: 0x00003ec0 (vscale initial phase 0.490234)
>                     PFA_CTL_4: 0x00007c00 (hscale 0.968750)
>                   PFA_WIN_POS: 0x00000000 (0, 0)
>                  PFA_WIN_SIZE: 0x00000000 (0, 0)
>                     PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFB_CTL_2: 0x00007d80 (vscale 0.980469)
>                     PFB_CTL_3: 0x00003ec0 (vscale initial phase 0.490234)
>                     PFB_CTL_4: 0x00007c00 (hscale 0.968750)
>                   PFB_WIN_POS: 0x00000000 (0, 0)
>                  PFB_WIN_SIZE: 0x00000000 (0, 0)
>              PCH_DREF_CONTROL: 0x00001400 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable)
>               PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>              PCH_DPLL_TMR_CFG: 0x0271186a
>                PCH_SSC4_PARMS: 0x01204860
>            PCH_SSC4_AUX_PARMS: 0x000029c5
>                  PCH_DPLL_SEL: 0x00000098 (TransA DPLL enable (DPLL A), TransB DPLL enable (DPLL B))
>           PCH_DPLL_ANALOG_CTL: 0x00008000
>                    PCH_DPLL_A: 0x84020002 (enable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 2, FPA1 P1 2, refclk default 120Mhz, sdvo/hdmi mul 1)
>                    PCH_DPLL_B: 0xc4010001 (enable, sdvo high speed yes, mode (null), p2 (null), FPA0 P1 1, FPA1 P1 1, refclk default 120Mhz, sdvo/hdmi mul 1)
>                      PCH_FPA0: 0x00010e05 (n = 1, m1 = 14, m2 = 5)
>                      PCH_FPA1: 0x00010e05 (n = 1, m1 = 14, m2 = 5)
>                      PCH_FPB0: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
>                      PCH_FPB1: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
>                TRANS_HTOTAL_A: 0x089f07ff (2048 active, 2208 total)
>                TRANS_HBLANK_A: 0x089f07ff (2048 start, 2208 end)
>                 TRANS_HSYNC_A: 0x084f082f (2096 start, 2128 end)
>                TRANS_VTOTAL_A: 0x052404ff (1280 active, 1317 total)
>                TRANS_VBLANK_A: 0x052404ff (1280 start, 1317 end)
>                 TRANS_VSYNC_A: 0x05080502 (1283 start, 1289 end)
>                TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_B: 0x0a9f09ff (2560 active, 2720 total)
>                TRANS_HBLANK_B: 0x0a9f09ff (2560 start, 2720 end)
>                 TRANS_HSYNC_B: 0x0a4f0a2f (2608 start, 2640 end)
>                TRANS_VTOTAL_B: 0x066d063f (1600 active, 1646 total)
>                TRANS_VBLANK_B: 0x066d063f (1600 start, 1646 end)
>                 TRANS_VSYNC_B: 0x06480642 (1603 start, 1609 end)
>                TRANSB_DATA_M1: 0x7e0c44a0 (TU 64, val 0xc44a0 804000)
>                TRANSB_DATA_N1: 0x00107ac0 (val 0x107ac0 1080000)
>                TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M1: 0x000416e0 (val 0x416e0 268000)
>             TRANSB_DP_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>             TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
>                 TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
>                TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_VBLANK_C: 0x00000000 (1 start, 1 end)
>                 TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
>                TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                    TRANSACONF: 0xc0000000 (enable, active)
>                    TRANSBCONF: 0xc0000000 (enable, active)
>                    TRANSCCONF: 0x00000000 (disable, inactive)
>                   FDI_TXA_CTL: 0x80144b00 (enable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X3, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXB_CTL: 0x801c4300 (enable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X4, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXC_CTL: 0x00040000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable)
>                   FDI_RXA_CTL: 0x8c102b50 (enable, train pattern not train, port width X3, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc enable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXB_CTL: 0x8c182350 (enable, train pattern not train, port width X4, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXC_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
>                  FDI_RXA_MISC: 0x00200080 (FDI Delay 128)
>                  FDI_RXB_MISC: 0x00200080 (FDI Delay 128)
>                  FDI_RXC_MISC: 0x00200080 (FDI Delay 128)
>               FDI_RXA_TUSIZE1: 0x7e000000
>               FDI_RXA_TUSIZE2: 0x7e000000
>               FDI_RXB_TUSIZE1: 0x7e000000
>               FDI_RXB_TUSIZE2: 0x7e000000
>               FDI_RXC_TUSIZE1: 0x7e000000
>               FDI_RXC_TUSIZE2: 0x7e000000
>                 FDI_PLL_CTL_1: 0x7e000000
>                 FDI_PLL_CTL_2: 0x7e000000
>                   FDI_RXA_IIR: 0x00000000
>                   FDI_RXA_IMR: 0x000008ff
>                   FDI_RXB_IIR: 0x00000000
>                   FDI_RXB_IMR: 0x000008ff
>                      PCH_ADPA: 0x83f40008 (enabled, transcoder A, +hsync, -vsync)
>                         HDMIB: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
>                         HDMIC: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
>                         HDMID: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
>                      PCH_LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>                     CPU_eDP_A: 0x00000018
>                      PCH_DP_B: 0x00000000
>                      PCH_DP_C: 0x80980304
>                      PCH_DP_D: 0x00000004
>                TRANS_DP_CTL_A: 0x60040018 (disable port none 8bpc +vsync +hsync)
>                TRANS_DP_CTL_B: 0xa0040018 (enable port C 8bpc +vsync +hsync)
>                TRANS_DP_CTL_C: 0x60000018 (disable port none 8bpc +vsync +hsync)
>              BLC_PWM_CPU_CTL2: 0x00000000
>               BLC_PWM_CPU_CTL: 0x00000000
>              BLC_PWM_PCH_CTL1: 0x00000000
>              BLC_PWM_PCH_CTL2: 0x00000000
>                 PCH_PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>                PCH_PP_CONTROL: 0xabcd0000 (blacklight disabled, do not power down on reset, panel off)
>              PCH_PP_ON_DELAYS: 0x00000000
>             PCH_PP_OFF_DELAYS: 0x00000000
>                PCH_PP_DIVISOR: 0x00186904

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Attachments on bug 42943: 53567 | 56179

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