Attachment 53822 Details for Bug 43191 – possible fix

[patch] possible fix

0002-drm-radeon-kms-fix-2D-tiling-CS-support-on-EG-CM.patch (text/plain), 10.17 KB, created by Alex Deucher on 2011-11-23 15:37:51 UTC

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Creator: Alex Deucher

Created: 2011-11-23 15:37:51 UTC

Size: 10.17 KB

patch

obsolete

>From 70403b931f8ef196b115624980f6419e0c48de6e Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexander.deucher@amd.com>
>Date: Wed, 23 Nov 2011 18:37:05 -0500
>Subject: [PATCH 2/2] drm/radeon/kms: fix 2D tiling CS support on EG/CM
>
>May fix:
>https://bugs.freedesktop.org/show_bug.cgi?id=43191
>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>---
> drivers/gpu/drm/radeon/evergreen_cs.c |  146 +++++++++++++++++++++++++++------
> drivers/gpu/drm/radeon/evergreend.h   |   31 +++++++
> 2 files changed, 151 insertions(+), 26 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
>index 7fdfa8e..d4ecc93 100644
>--- a/drivers/gpu/drm/radeon/evergreen_cs.c
>+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
>@@ -38,6 +38,7 @@ struct evergreen_cs_track {
> 	u32			group_size;
> 	u32			nbanks;
> 	u32			npipes;
>+	u32			row_size;
> 	/* value we track */
> 	u32			nsamples;
> 	u32			cb_color_base_last[12];
>@@ -77,6 +78,44 @@ struct evergreen_cs_track {
> 	struct radeon_bo	*db_s_write_bo;
> };
> 
>+static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
>+{
>+	if (tiling_flags & RADEON_TILING_MACRO)
>+		return ARRAY_2D_TILED_THIN1;
>+	else if (tiling_flags & RADEON_TILING_MICRO)
>+		return ARRAY_1D_TILED_THIN1;
>+	else
>+		return ARRAY_LINEAR_GENERAL;
>+}
>+
>+static u32 evergreen_cs_get_num_banks(u32 nbanks)
>+{
>+	switch (nbanks) {
>+	case 2:
>+		return ADDR_SURF_2_BANK;
>+	case 4:
>+		return ADDR_SURF_4_BANK;
>+	case 8:
>+	default:
>+		return ADDR_SURF_8_BANK;
>+	case 16:
>+		return ADDR_SURF_16_BANK;
>+	}
>+}
>+
>+static u32 evergreen_cs_get_tile_split(u32 row_size)
>+{
>+	switch (row_size) {
>+	case 1:
>+	default:
>+		return ADDR_SURF_TILE_SPLIT_1KB;
>+	case 2:
>+		return ADDR_SURF_TILE_SPLIT_2KB;
>+	case 4:
>+		return ADDR_SURF_TILE_SPLIT_4KB;
>+	}
>+}
>+
> static void evergreen_cs_track_init(struct evergreen_cs_track *track)
> {
> 	int i;
>@@ -489,12 +528,11 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
> 		track->db_z_info = radeon_get_ib_value(p, idx);
> 		ib[idx] &= ~Z_ARRAY_MODE(0xf);
> 		track->db_z_info &= ~Z_ARRAY_MODE(0xf);
>+		ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
>+		track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
> 		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
>-			ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
>-			track->db_z_info |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
>-		} else {
>-			ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
>-			track->db_z_info |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
>+			ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
>+			ib[idx] |= DB_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
> 		}
> 		break;
> 	case DB_STENCIL_INFO:
>@@ -615,13 +653,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
> 		}
> 		tmp = (reg - CB_COLOR0_INFO) / 0x3c;
> 		track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
>-		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
>-			ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
>-			track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
>-		} else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
>-			ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
>-			track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
>-		}
>+		ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
>+		track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
> 		break;
> 	case CB_COLOR8_INFO:
> 	case CB_COLOR9_INFO:
>@@ -635,13 +668,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
> 		}
> 		tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
> 		track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
>-		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
>-			ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
>-			track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
>-		} else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
>-			ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
>-			track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
>-		}
>+		ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
>+		track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
> 		break;
> 	case CB_COLOR0_PITCH:
> 	case CB_COLOR1_PITCH:
>@@ -695,6 +723,16 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
> 	case CB_COLOR9_ATTRIB:
> 	case CB_COLOR10_ATTRIB:
> 	case CB_COLOR11_ATTRIB:
>+		r = evergreen_cs_packet_next_reloc(p, &reloc);
>+		if (r) {
>+			dev_warn(p->dev, "bad SET_CONTEXT_REG "
>+					"0x%04X\n", reg);
>+			return -EINVAL;
>+		}
>+		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
>+			ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
>+			ib[idx] |= CB_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
>+		}
> 		break;
> 	case CB_COLOR0_DIM:
> 	case CB_COLOR1_DIM:
>@@ -1311,10 +1349,11 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
> 					return -EINVAL;
> 				}
> 				ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
>-				if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
>-					ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
>-				else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
>-					ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
>+				ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
>+				if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
>+					ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
>+					ib[idx+1+(i*8)+7] |= TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
>+				}
> 				texture = reloc->robj;
> 				/* tex mip base */
> 				r = evergreen_cs_packet_next_reloc(p, &reloc);
>@@ -1414,6 +1453,7 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
> {
> 	struct radeon_cs_packet pkt;
> 	struct evergreen_cs_track *track;
>+	u32 tmp;
> 	int r;
> 
> 	if (p->track == NULL) {
>@@ -1422,9 +1462,63 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
> 		if (track == NULL)
> 			return -ENOMEM;
> 		evergreen_cs_track_init(track);
>-		track->npipes = p->rdev->config.evergreen.tiling_npipes;
>-		track->nbanks = p->rdev->config.evergreen.tiling_nbanks;
>-		track->group_size = p->rdev->config.evergreen.tiling_group_size;
>+		if (p->rdev->family >= CHIP_CAYMAN)
>+			tmp = p->rdev->config.cayman.tile_config;
>+		else
>+			tmp = p->rdev->config.evergreen.tile_config;
>+
>+		switch (tmp & 0xf) {
>+		case 0:
>+			track->npipes = 1;
>+			break;
>+		case 1:
>+		default:
>+			track->npipes = 2;
>+			break;
>+		case 2:
>+			track->npipes = 4;
>+			break;
>+		case 3:
>+			track->npipes = 8;
>+			break;
>+		}
>+
>+		switch ((tmp & 0xf0) >> 4) {
>+		case 0:
>+			track->nbanks = 4;
>+			break;
>+		case 1:
>+		default:
>+			track->nbanks = 8;
>+			break;
>+		case 2:
>+			track->nbanks = 16;
>+			break;
>+		}
>+
>+		switch ((tmp & 0xf00) >> 8) {
>+		case 0:
>+			track->group_size = 256;
>+			break;
>+		case 1:
>+		default:
>+			track->group_size = 512;
>+			break;
>+		}
>+
>+		switch ((tmp & 0xf000) >> 12) {
>+		case 0:
>+			track->row_size = 1;
>+			break;
>+		case 1:
>+		default:
>+			track->row_size = 2;
>+			break;
>+		case 2:
>+			track->row_size = 4;
>+			break;
>+		}
>+
> 		p->track = track;
> 	}
> 	do {
>diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
>index b937c49..e00039e 100644
>--- a/drivers/gpu/drm/radeon/evergreend.h
>+++ b/drivers/gpu/drm/radeon/evergreend.h
>@@ -899,6 +899,10 @@
> #define DB_HTILE_DATA_BASE				0x28014
> #define DB_Z_INFO					0x28040
> #       define Z_ARRAY_MODE(x)                          ((x) << 4)
>+#       define DB_TILE_SPLIT(x)                         (((x) & 0x7) << 8)
>+#       define DB_NUM_BANKS(x)                          (((x) & 0x3) << 12)
>+#       define DB_BANK_WIDTH(x)                         (((x) & 0x3) << 16)
>+#       define DB_BANK_HEIGHT(x)                        (((x) & 0x3) << 20)
> #define DB_STENCIL_INFO					0x28044
> #define DB_Z_READ_BASE					0x28048
> #define DB_STENCIL_READ_BASE				0x2804c
>@@ -951,6 +955,29 @@
> #	define CB_SF_EXPORT_FULL			0
> #	define CB_SF_EXPORT_NORM			1
> #define	CB_COLOR0_ATTRIB				0x28c74
>+#       define CB_TILE_SPLIT(x)                         (((x) & 0x7) << 5)
>+#       define ADDR_SURF_TILE_SPLIT_64B                 0
>+#       define ADDR_SURF_TILE_SPLIT_128B                1
>+#       define ADDR_SURF_TILE_SPLIT_256B                2
>+#       define ADDR_SURF_TILE_SPLIT_512B                3
>+#       define ADDR_SURF_TILE_SPLIT_1KB                 4
>+#       define ADDR_SURF_TILE_SPLIT_2KB                 5
>+#       define ADDR_SURF_TILE_SPLIT_4KB                 6
>+#       define CB_NUM_BANKS(x)                          (((x) & 0x3) << 10)
>+#       define ADDR_SURF_2_BANK                         0
>+#       define ADDR_SURF_4_BANK                         1
>+#       define ADDR_SURF_8_BANK                         2
>+#       define ADDR_SURF_16_BANK                        3
>+#       define CB_BANK_WIDTH(x)                         (((x) & 0x3) << 13)
>+#       define ADDR_SURF_BANK_WIDTH_1                   0
>+#       define ADDR_SURF_BANK_WIDTH_2                   1
>+#       define ADDR_SURF_BANK_WIDTH_4                   2
>+#       define ADDR_SURF_BANK_WIDTH_8                   3
>+#       define CB_BANK_HEIGHT(x)                        (((x) & 0x3) << 16)
>+#       define ADDR_SURF_BANK_HEIGHT_1                  0
>+#       define ADDR_SURF_BANK_HEIGHT_2                  1
>+#       define ADDR_SURF_BANK_HEIGHT_4                  2
>+#       define ADDR_SURF_BANK_HEIGHT_8                  3
> #define	CB_COLOR0_DIM					0x28c78
> /* only CB0-7 blocks have these regs */
> #define	CB_COLOR0_CMASK					0x28c7c
>@@ -1137,7 +1164,11 @@
> #	define SQ_SEL_1					5
> #define SQ_TEX_RESOURCE_WORD5_0                         0x30014
> #define SQ_TEX_RESOURCE_WORD6_0                         0x30018
>+#       define TEX_TILE_SPLIT(x)                        (((x) & 0x7) << 29)
> #define SQ_TEX_RESOURCE_WORD7_0                         0x3001c
>+#       define TEX_BANK_WIDTH(x)                        (((x) & 0x3) << 8)
>+#       define TEX_BANK_HEIGHT(x)                       (((x) & 0x3) << 10)
>+#       define TEX_NUM_BANKS(x)                         (((x) & 0x3) << 16)
> 
> #define SQ_VTX_CONSTANT_WORD0_0				0x30000
> #define SQ_VTX_CONSTANT_WORD1_0				0x30004
>-- 
>1.7.3.4
>

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Attachments on bug 43191: 53797 | 53817 | 53820 | 53821 | 53822 | 53906 | 53912 | 54028 | 54396 | 54397 | 54398

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