Attachment 54366 Details for Bug 39282 – possible fix

[patch] possible fix

0001-drm-radeon-kms-fix-gpu-init-for-barts-LE.patch (text/plain), 2.86 KB, created by Alex Deucher on 2011-12-12 09:33:14 UTC

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Creator: Alex Deucher

Created: 2011-12-12 09:33:14 UTC

Size: 2.86 KB

patch

obsolete

>From 830fdd478ab9a0819ed3a31b6cbb6a240cce846c Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexander.deucher@amd.com>
>Date: Mon, 12 Dec 2011 12:31:33 -0500
>Subject: [PATCH] drm/radeon/kms: fix gpu init for barts LE
>
>May fix:
>https://bugs.freedesktop.org/show_bug.cgi?id=39282
>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>Cc: stable@kernel.org
>---
> drivers/gpu/drm/radeon/evergreen.c |   12 +++++++++---
> 1 files changed, 9 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
>index 93c0348..60ad53a 100644
>--- a/drivers/gpu/drm/radeon/evergreen.c
>+++ b/drivers/gpu/drm/radeon/evergreen.c
>@@ -1837,6 +1837,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
> 		rdev->config.evergreen.max_tile_pipes = 8;
> 		rdev->config.evergreen.max_simds = 7;
> 		rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
>+		rdev->config.evergreen.max_simds = 7;
>+		rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
> 		rdev->config.evergreen.max_gprs = 256;
> 		rdev->config.evergreen.max_threads = 248;
> 		rdev->config.evergreen.max_gs_threads = 32;
>@@ -1910,7 +1912,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
> 	evergreen_fix_pci_max_read_req_size(rdev);
> 
> 	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
>-
> 	cc_gc_shader_pipe_config |=
> 		INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
> 				  & EVERGREEN_MAX_PIPES_MASK);
>@@ -1918,11 +1919,11 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
> 		INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
> 			       & EVERGREEN_MAX_SIMDS_MASK);
> 
>-	cc_rb_backend_disable =
>+	cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
>+	cc_rb_backend_disable |=
> 		BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
> 				& EVERGREEN_MAX_BACKENDS_MASK);
> 
>-
> 	mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
> 	if ((rdev->family == CHIP_PALM) ||
> 	    (rdev->family == CHIP_SUMO) ||
>@@ -2038,6 +2039,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
> 									EVERGREEN_MAX_BACKENDS_MASK));
> 			break;
> 		}
>+	} else if (rdev->ddev->pdev->device == 0x673e) {
>+		/* BARTS LE */
>+		gb_backend_map = 0x77553311;
> 	} else {
> 		switch (rdev->family) {
> 		case CHIP_CYPRESS:
>@@ -2056,6 +2060,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
> 								       ((EVERGREEN_MAX_BACKENDS_MASK <<
> 									 rdev->config.evergreen.max_backends) &
> 									EVERGREEN_MAX_BACKENDS_MASK));
>+			break;
> 		}
> 	}
> 
>@@ -2120,6 +2125,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
> 		WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
> 		WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
> 		WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
>+		WREG32(GC_USER_SHADER_PIPE_CONFIG, sp);
>         }
> 
> 	grbm_gfx_index |= SE_BROADCAST_WRITES;
>-- 
>1.7.3.4
>

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Attachments on bug 39282: 49177 | 49462 | 49463 | 53473 | 53756 | 53757 | 53814 | 54366 | 54374 | 58893 | 62030 | 62067 | 62543 | 62544 | 62545

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