Attachment 55733 Details for Bug 44876 – lid closed and reopened

lid closed and reopened

intel_reg_dump-lib.closed.reopened.txt (text/plain), 11.27 KB, created by daniel on 2012-01-18 04:48:47 UTC

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Creator: daniel

Created: 2012-01-18 04:48:47 UTC

Size: 11.27 KB

patch

obsolete

>                    PGETBL_CTL: 0x00000000
>               GEN6_INSTDONE_1: 0xfffffffe
>               GEN6_INSTDONE_2: 0xffffffff
>                  CPU_VGACNTRL: 0x80000000 (disabled)
>    DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
>                     RR_HW_CTL: 0x00000000 (low 0, high 0)
>                FDI_PLL_BIOS_0: 0xffffffff
>                FDI_PLL_BIOS_1: 0xffffffff
>                FDI_PLL_BIOS_2: 0xffffffff
>       DISPLAY_PORT_PLL_BIOS_0: 0xffffffff
>       DISPLAY_PORT_PLL_BIOS_1: 0xffffffff
>       DISPLAY_PORT_PLL_BIOS_2: 0xffffffff
>              FDI_PLL_FREQ_CTL: 0xffffffff
>                     PIPEACONF: 0xc0000054 (enabled, active, 6bpc)
>                      HTOTAL_A: 0x07fb063f (1600 active, 2044 total)
>                      HBLANK_A: 0x07fb063f (1600 start, 2044 end)
>                       HSYNC_A: 0x068f066f (1648 start, 1680 end)
>                      VTOTAL_A: 0x03a10383 (900 active, 930 total)
>                      VBLANK_A: 0x03a10383 (900 start, 930 end)
>                       VSYNC_A: 0x038a0385 (902 start, 907 end)
>                  VSYNCSHIFT_A: 0x00000000
>                      PIPEASRC: 0x063f0383 (1600, 900)
>                 PIPEA_DATA_M1: 0x7e1f53d8 (TU 64, val 0x1f53d8 2053080)
>                 PIPEA_DATA_N1: 0x0020f580 (val 0x20f580 2160000)
>                 PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_M1: 0x0001bd8c (val 0x1bd8c 114060)
>                 PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>                 PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPACNTR: 0xd8004400 (enabled)
>                      DSPABASE: 0x00000000
>                    DSPASTRIDE: 0x00001a00 (104)
>                      DSPASURF: 0x005e2000
>                   DSPATILEOFF: 0x00000000 (0, 0)
>                     PIPEBCONF: 0x00000000 (disabled, inactive, 8bpc)
>                      HTOTAL_B: 0x00000000 (1 active, 1 total)
>                      HBLANK_B: 0x00000000 (1 start, 1 end)
>                       HSYNC_B: 0x00000000 (1 start, 1 end)
>                      VTOTAL_B: 0x00000000 (1 active, 1 total)
>                      VBLANK_B: 0x00000000 (1 start, 1 end)
>                       VSYNC_B: 0x00000000 (1 start, 1 end)
>                  VSYNCSHIFT_B: 0x00000000
>                      DSPBCNTR: 0x00004000 (disabled)
>                      DSPBBASE: 0x00000000
>                    DSPBSTRIDE: 0x00000000 (0)
>                      DSPBSURF: 0x00000000
>                   DSPBTILEOFF: 0x00000000 (0, 0)
>                      PIPEBSRC: 0x00000000 (1, 1)
>                 PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEB_DATA_N1: 0x00000000 (val 0x0 0)
>                 PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_M1: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_N1: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
>                     PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFA_CTL_2: 0x00007e3e (vscale 0.986267)
>                     PFA_CTL_3: 0x00003f1f (vscale initial phase 0.493134)
>                     PFA_CTL_4: 0x00007ce0 (hscale 0.975586)
>                   PFA_WIN_POS: 0x00000000 (0, 0)
>                  PFA_WIN_SIZE: 0x00000000 (0, 0)
>                     PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFB_CTL_2: 0x00000000 (vscale 0.000000)
>                     PFB_CTL_3: 0x00000000 (vscale initial phase 0.000000)
>                     PFB_CTL_4: 0x00000000 (hscale 0.000000)
>                   PFB_WIN_POS: 0x00000000 (0, 0)
>                  PFB_WIN_SIZE: 0x00000000 (0, 0)
>              PCH_DREF_CONTROL: 0x00005402 (cpu source downspread, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 enable, ssc4 disable)
>               PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>              PCH_DPLL_TMR_CFG: 0x0271186a
>                PCH_SSC4_PARMS: 0x01204860
>            PCH_SSC4_AUX_PARMS: 0x000029c5
>                  PCH_DPLL_SEL: 0x00000008 (TransA DPLL enable (DPLL A), TransB DPLL disable (DPLL (null)))
>           PCH_DPLL_ANALOG_CTL: 0x00008000
>                    PCH_DPLL_A: 0x89086008 (enable, sdvo high speed no, mode LVDS, p2 Div 7, FPA0 P1 4, FPA1 P1 4, refclk SSC, sdvo/hdmi mul 1)
>                    PCH_DPLL_B: 0x04800080 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1)
>                      PCH_FPA0: 0x00010c08 (n = 1, m1 = 12, m2 = 8)
>                      PCH_FPA1: 0x00010c08 (n = 1, m1 = 12, m2 = 8)
>                      PCH_FPB0: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
>                      PCH_FPB1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
>                TRANS_HTOTAL_A: 0x07fb063f (1600 active, 2044 total)
>                TRANS_HBLANK_A: 0x07fb063f (1600 start, 2044 end)
>                 TRANS_HSYNC_A: 0x068f066f (1648 start, 1680 end)
>                TRANS_VTOTAL_A: 0x03a10383 (900 active, 930 total)
>                TRANS_VBLANK_A: 0x03a10383 (900 start, 930 end)
>                 TRANS_VSYNC_A: 0x038a0385 (902 start, 907 end)
>                TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_B: 0x00000000 (1 active, 1 total)
>                TRANS_HBLANK_B: 0x00000000 (1 start, 1 end)
>                 TRANS_HSYNC_B: 0x00000000 (1 start, 1 end)
>                TRANS_VTOTAL_B: 0x00000000 (1 active, 1 total)
>                TRANS_VBLANK_B: 0x00000000 (1 start, 1 end)
>                 TRANS_VSYNC_B: 0x00000000 (1 start, 1 end)
>                TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
>                 TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
>                TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_VBLANK_C: 0x00000000 (1 start, 1 end)
>                 TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
>                TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                    TRANSACONF: 0xc0000000 (enable, active)
>                    TRANSBCONF: 0x00000000 (disable, inactive)
>                    TRANSCCONF: 0x00000000 (disable, inactive)
>                   FDI_TXA_CTL: 0xb0044000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXB_CTL: 0x00040000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable)
>                   FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable)
>                   FDI_RXA_CTL: 0x80022350 (enable, train pattern not train, port width X1, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXB_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
>                   FDI_RXC_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
>                  FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
>                  FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
>                  FDI_RXC_MISC: 0x00000080 (FDI Delay 128)
>               FDI_RXA_TUSIZE1: 0x7e000000
>               FDI_RXA_TUSIZE2: 0x7e000000
>               FDI_RXB_TUSIZE1: 0x7e000000
>               FDI_RXB_TUSIZE2: 0x7e000000
>               FDI_RXC_TUSIZE1: 0x7e000000
>               FDI_RXC_TUSIZE2: 0x7e000000
>                 FDI_PLL_CTL_1: 0x7e000000
>                 FDI_PLL_CTL_2: 0x7e000000
>                   FDI_RXA_IIR: 0x00000000
>                   FDI_RXA_IMR: 0x000008ff
>                   FDI_RXB_IIR: 0x00000000
>                   FDI_RXB_IMR: 0x000008ff
>                      PCH_ADPA: 0x00f40000 (disabled, transcoder A, -hsync, -vsync)
>                         HDMIB: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
>                         HDMIC: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
>                         HDMID: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
>                      PCH_LVDS: 0x8020033e (enabled, pipe A, 18 bit, 2 channels)
>                     CPU_eDP_A: 0x00000018
>                      PCH_DP_B: 0x00000004
>                      PCH_DP_C: 0x00000004
>                      PCH_DP_D: 0x00000004
>                TRANS_DP_CTL_A: 0x60000418 (disable port none 6bpc +vsync +hsync)
>                TRANS_DP_CTL_B: 0x60000018 (disable port none 8bpc +vsync +hsync)
>                TRANS_DP_CTL_C: 0x60000018 (disable port none 8bpc +vsync +hsync)
>              BLC_PWM_CPU_CTL2: 0x80000000
>               BLC_PWM_CPU_CTL: 0x00000430
>              BLC_PWM_PCH_CTL1: 0x80000000
>              BLC_PWM_PCH_CTL2: 0x13121312
>                 PCH_PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>                PCH_PP_CONTROL: 0xabcd0003 (blacklight disabled, power down on reset, panel on)
>              PCH_PP_ON_DELAYS: 0x019008fc
>             PCH_PP_OFF_DELAYS: 0x019008fc
>                PCH_PP_DIVISOR: 0x00186906

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Attachments on bug 44876: 55706 | 55730 | 55731 | 55732 | 55733 | 55755 | 55756 | 55790 | 55791 | 55792 | 55793

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