Attachment 56587 Details for Bug 37526 – dmesg.txt

dmesg.txt

dmesg.txt (text/plain), 123.41 KB, created by Bryce Harrington on 2012-02-03 17:17:05 UTC

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Creator: Bryce Harrington

Created: 2012-02-03 17:17:05 UTC

Size: 123.41 KB

patch

obsolete

>ntel_calculate_wm], FIFO watermark level: -9
>[   30.647923] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   30.647930] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   30.647938] [drm:i9xx_update_wm], memory self refresh disabled
>[   30.648391] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   30.648398] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   30.708033] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   30.708051] [drm:intel_update_fbc], 
>[   30.708060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   30.708067] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   30.708074] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   30.708080] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   30.708088] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   30.708094] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   30.708100] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   30.708108] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   30.708116] [drm:i9xx_update_wm], memory self refresh disabled
>[   30.708127] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   30.728032] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   30.728039] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   30.728045] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   30.728052] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   30.728059] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   30.728065] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   30.728071] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   30.728078] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   30.728085] [drm:i9xx_update_wm], memory self refresh disabled
>[   30.728589] [drm:intel_update_fbc], 
>[   30.788028] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   30.788049] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   30.848166] [drm:drm_mode_addfb], [FB:46]
>[   30.848761] [drm:drm_mode_setcrtc], [CRTC:3]
>[   30.848775] [drm:drm_mode_setcrtc], [CONNECTOR:8:HDMI-A-1]
>[   30.848782] [drm:drm_crtc_helper_set_config], 
>[   30.848787] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:46] #connectors=1 (x y) (0 0)
>[   30.848810] [drm:drm_crtc_helper_set_config], [CONNECTOR:8:HDMI-A-1] to [CRTC:3]
>[   30.848830] [drm:intel_pipe_set_base_atomic], Writing base 01000000 00000000 0 0 8192
>[   30.848840] [drm:intel_update_fbc], 
>[   32.063259] [drm:intel_crtc_cursor_set], 
>[   32.648036] eth0: no IPv6 routers present
>[   32.687744] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   32.687761] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1]
>[   32.743235] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   32.743245] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   32.743255] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   32.787325] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   32.819883] [drm:intel_update_fbc], 
>[   32.819894] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   32.819902] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   32.819909] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   32.819916] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   32.819923] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   32.819929] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   32.819936] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   32.819943] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   32.819951] [drm:i9xx_update_wm], memory self refresh disabled
>[   32.820404] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   32.820411] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   32.852064] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   32.852080] [drm:intel_update_fbc], 
>[   32.852089] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   32.852097] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   32.852104] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   32.852110] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   32.852118] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   32.852124] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   32.852130] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   32.852138] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   32.852146] [drm:i9xx_update_wm], memory self refresh disabled
>[   32.852156] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   32.852167] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   32.852174] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   32.852180] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   32.852186] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   32.852193] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   32.852199] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   32.852205] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   32.852212] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   32.852220] [drm:i9xx_update_wm], memory self refresh disabled
>[   32.852724] [drm:intel_update_fbc], 
>[   32.923478] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   32.923491] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   33.008748] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   33.008768] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected
>[   33.008811] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   33.008820] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1]
>[   33.069539] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   33.069555] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   33.069565] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   33.070378] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   33.103937] [drm:intel_update_fbc], 
>[   33.103950] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   33.103959] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   33.103966] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   33.103972] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   33.103979] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   33.103986] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   33.103992] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   33.104017] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   33.104026] [drm:i9xx_update_wm], memory self refresh disabled
>[   33.104466] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   33.104473] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   33.152028] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   33.152044] [drm:intel_update_fbc], 
>[   33.152052] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   33.152060] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   33.152066] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   33.152073] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   33.152080] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   33.152087] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   33.152093] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   33.152100] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   33.152109] [drm:i9xx_update_wm], memory self refresh disabled
>[   33.152119] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   33.152129] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   33.152136] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   33.152143] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   33.152149] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   33.152156] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   33.152162] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   33.152168] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   33.152175] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   33.152183] [drm:i9xx_update_wm], memory self refresh disabled
>[   33.152688] [drm:intel_update_fbc], 
>[   33.215444] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   33.215454] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   33.236025] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   33.236048] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected
>[   33.236127] [drm:drm_mode_getconnector], [CONNECTOR:8:?]
>[   33.236138] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:HDMI-A-1]
>[   33.236149] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   33.239173] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   33.244985] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   33.245178] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   33.251336] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   33.307640] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   33.313709] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   33.370157] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:HDMI-A-1] probed modes :
>[   33.370167] [drm:drm_mode_debug_printmodeline], Modeline 26:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x48 0x9
>[   33.370181] [drm:drm_mode_debug_printmodeline], Modeline 32:"1600x1000" 60 133161 1600 1704 1872 2144 1000 1001 1004 1035 0x0 0x6
>[   33.370193] [drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   33.370206] [drm:drm_mode_debug_printmodeline], Modeline 29:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   33.370219] [drm:drm_mode_debug_printmodeline], Modeline 31:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[   33.370231] [drm:drm_mode_debug_printmodeline], Modeline 30:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[   33.370244] [drm:drm_mode_debug_printmodeline], Modeline 28:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   33.370257] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   33.370269] [drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   33.370282] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   33.370294] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   33.370307] [drm:drm_mode_debug_printmodeline], Modeline 42:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   33.370319] [drm:drm_mode_debug_printmodeline], Modeline 33:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   33.370331] [drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[   33.370344] [drm:drm_mode_debug_printmodeline], Modeline 34:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   33.370356] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 66 26885 640 664 728 816 480 481 484 499 0x0 0x6
>[   33.370368] [drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   33.370380] [drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   33.370423] [drm:drm_mode_getconnector], [CONNECTOR:8:?]
>[   33.371496] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   33.371508] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1]
>[   33.371519] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   33.371529] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   33.371546] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   33.398917] [drm:intel_update_fbc], 
>[   33.398926] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   33.398935] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   33.398942] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   33.398948] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   33.398955] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   33.398962] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   33.398968] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   33.398975] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   33.398983] [drm:i9xx_update_wm], memory self refresh disabled
>[   33.399421] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   33.399428] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   33.436017] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   33.436029] [drm:intel_update_fbc], 
>[   33.436037] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   33.436044] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   33.436051] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   33.436057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   33.436065] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   33.436071] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   33.436077] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   33.436084] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   33.436092] [drm:i9xx_update_wm], memory self refresh disabled
>[   33.436100] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   33.460959] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   33.460967] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   33.460973] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   33.460980] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   33.460986] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   33.460993] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   33.460999] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   33.461006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   33.461013] [drm:i9xx_update_wm], memory self refresh disabled
>[   33.461516] [drm:intel_update_fbc], 
>[   33.524018] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   33.524036] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   33.524075] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   33.524084] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1]
>[   33.524093] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   33.524102] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   33.524115] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   33.556832] [drm:intel_update_fbc], 
>[   33.556840] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   33.556848] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   33.556855] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   33.556861] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   33.556869] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   33.556875] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   33.556881] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   33.556888] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   33.556896] [drm:i9xx_update_wm], memory self refresh disabled
>[   33.557329] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   33.557336] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   33.596016] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   33.596028] [drm:intel_update_fbc], 
>[   33.596035] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   33.596042] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   33.596049] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   33.596055] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   33.596062] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   33.596069] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   33.596075] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   33.596082] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   33.596090] [drm:i9xx_update_wm], memory self refresh disabled
>[   33.596097] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   33.615992] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   33.616006] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   33.616012] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   33.616019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   33.616026] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   33.616032] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   33.616038] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   33.616045] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   33.616052] [drm:i9xx_update_wm], memory self refresh disabled
>[   33.616555] [drm:intel_update_fbc], 
>[   33.680017] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   33.680032] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   34.073119] [drm:i915_driver_open], 
>[   34.175605] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   34.178682] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   34.193343] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   34.201365] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   34.210546] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   34.272313] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   34.272328] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   34.272349] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   34.307914] [drm:intel_update_fbc], 
>[   34.307926] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.307935] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   34.307942] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   34.307948] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.307956] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   34.307962] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   34.307968] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   34.307976] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   34.307984] [drm:i9xx_update_wm], memory self refresh disabled
>[   34.308433] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   34.308440] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   34.364287] [drm:intel_wait_for_vblank], vblank wait timed out
>[   34.370517] [drm:i915_driver_open], 
>[   34.560135] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   34.560152] [drm:intel_update_fbc], 
>[   34.560164] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.560172] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   34.560179] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   34.560185] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.560193] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   34.560199] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   34.560205] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   34.560213] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   34.560221] [drm:i9xx_update_wm], memory self refresh disabled
>[   34.560232] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   34.580124] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.580132] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   34.580139] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   34.580145] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.580152] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   34.580158] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   34.580164] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   34.580171] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   34.580179] [drm:i9xx_update_wm], memory self refresh disabled
>[   34.580683] [drm:intel_update_fbc], 
>[   34.640160] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   34.695847] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   34.695859] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   34.695868] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   34.701504] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   34.727901] [drm:intel_update_fbc], 
>[   34.727912] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.727921] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   34.727928] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   34.727934] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.727942] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   34.727948] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   34.727954] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   34.727962] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   34.727970] [drm:i9xx_update_wm], memory self refresh disabled
>[   34.728417] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   34.728424] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   34.840069] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   34.840086] [drm:intel_update_fbc], 
>[   34.840095] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.840103] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   34.840110] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   34.840116] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.840124] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   34.840130] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   34.840136] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   34.840144] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   34.840152] [drm:i9xx_update_wm], memory self refresh disabled
>[   34.840163] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   34.840174] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.840180] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   34.840187] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   34.840193] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.840200] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   34.840206] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   34.840212] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   34.840219] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   34.840227] [drm:i9xx_update_wm], memory self refresh disabled
>[   34.840732] [drm:intel_update_fbc], 
>[   34.921717] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   34.921730] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   35.272053] [drm:intel_wait_for_vblank], vblank wait timed out
>[   35.272071] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   36.279478] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   36.279493] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[   36.279503] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   36.444358] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   36.461363] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   36.473369] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   36.484093] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   36.540299] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[   36.540311] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[   39.699975] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   39.699991] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1]
>[   39.755446] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   39.755456] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   39.755466] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   39.756698] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   39.786897] [drm:intel_update_fbc], 
>[   39.786906] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   39.786914] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   39.786921] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   39.786928] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   39.786935] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   39.786942] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   39.786948] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   39.786955] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   39.786964] [drm:i9xx_update_wm], memory self refresh disabled
>[   39.787401] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   39.787408] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   39.816033] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   39.816046] [drm:intel_update_fbc], 
>[   39.816053] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   39.816061] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   39.816067] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   39.816074] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   39.816081] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   39.816087] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   39.816093] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   39.816101] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   39.816109] [drm:i9xx_update_wm], memory self refresh disabled
>[   39.816117] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   39.816126] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   39.816133] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   39.816140] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   39.816146] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   39.816153] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   39.816159] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   39.816165] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   39.816172] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   39.816180] [drm:i9xx_update_wm], memory self refresh disabled
>[   39.816684] [drm:intel_update_fbc], 
>[   39.887423] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   39.887433] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   39.900018] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   39.900037] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected
>[   39.900078] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   39.900086] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1]
>[   39.955514] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   39.955524] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   39.955532] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   39.962936] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   39.987860] [drm:intel_update_fbc], 
>[   39.987869] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   39.987877] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   39.987884] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   39.987891] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   39.987898] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   39.987905] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   39.987911] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   39.987918] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   39.987926] [drm:i9xx_update_wm], memory self refresh disabled
>[   39.988376] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   39.988384] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   40.020016] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   40.020029] [drm:intel_update_fbc], 
>[   40.020036] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   40.020044] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   40.020050] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   40.020057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   40.020064] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   40.020070] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   40.020076] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   40.020083] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   40.020091] [drm:i9xx_update_wm], memory self refresh disabled
>[   40.020099] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   40.020109] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   40.020116] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   40.020122] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   40.020129] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   40.020136] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   40.020142] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   40.020148] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   40.020155] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   40.020162] [drm:i9xx_update_wm], memory self refresh disabled
>[   40.020666] [drm:intel_update_fbc], 
>[   40.091429] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   40.091439] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   40.104026] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   40.104047] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected
>[   40.104123] [drm:drm_mode_getconnector], [CONNECTOR:8:?]
>[   40.104133] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:HDMI-A-1]
>[   40.104144] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   40.107169] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   40.113004] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   40.113199] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   40.119414] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   40.175725] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   40.181801] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   40.238270] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:HDMI-A-1] probed modes :
>[   40.238281] [drm:drm_mode_debug_printmodeline], Modeline 26:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x48 0x9
>[   40.238294] [drm:drm_mode_debug_printmodeline], Modeline 32:"1600x1000" 60 133161 1600 1704 1872 2144 1000 1001 1004 1035 0x0 0x6
>[   40.238307] [drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   40.238320] [drm:drm_mode_debug_printmodeline], Modeline 29:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   40.238333] [drm:drm_mode_debug_printmodeline], Modeline 31:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[   40.238345] [drm:drm_mode_debug_printmodeline], Modeline 30:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[   40.238358] [drm:drm_mode_debug_printmodeline], Modeline 28:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   40.238370] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   40.238383] [drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   40.238395] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   40.238408] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   40.238420] [drm:drm_mode_debug_printmodeline], Modeline 42:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   40.238433] [drm:drm_mode_debug_printmodeline], Modeline 33:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   40.238445] [drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[   40.238457] [drm:drm_mode_debug_printmodeline], Modeline 34:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   40.238469] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 66 26885 640 664 728 816 480 481 484 499 0x0 0x6
>[   40.238481] [drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   40.238494] [drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   40.238543] [drm:drm_mode_getconnector], [CONNECTOR:8:?]
>[   40.239570] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   40.239583] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1]
>[   40.239593] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   40.239603] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   40.239620] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   40.271856] [drm:intel_update_fbc], 
>[   40.271865] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   40.271874] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   40.271881] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   40.271888] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   40.271895] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   40.271902] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   40.271908] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   40.271915] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   40.271923] [drm:i9xx_update_wm], memory self refresh disabled
>[   40.272373] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   40.272379] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   40.312018] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   40.312030] [drm:intel_update_fbc], 
>[   40.312037] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   40.312045] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   40.312052] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   40.312058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   40.312065] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   40.312071] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   40.312077] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   40.312084] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   40.312092] [drm:i9xx_update_wm], memory self refresh disabled
>[   40.312100] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   40.331990] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   40.331998] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   40.332010] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   40.332016] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   40.332023] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   40.332030] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   40.332036] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   40.332043] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   40.332050] [drm:i9xx_update_wm], memory self refresh disabled
>[   40.332553] [drm:intel_update_fbc], 
>[   40.396016] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   40.396032] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   40.396070] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   40.396078] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1]
>[   40.396088] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   40.396096] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   40.396108] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   40.428819] [drm:intel_update_fbc], 
>[   40.428827] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   40.428835] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   40.428842] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   40.428848] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   40.428855] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   40.428861] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   40.428867] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   40.428875] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   40.428883] [drm:i9xx_update_wm], memory self refresh disabled
>[   40.429317] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   40.429323] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   40.468015] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   40.468026] [drm:intel_update_fbc], 
>[   40.468033] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   40.468040] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   40.468047] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   40.468053] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   40.468061] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   40.468067] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   40.468073] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   40.468080] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   40.468088] [drm:i9xx_update_wm], memory self refresh disabled
>[   40.468095] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   40.487983] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   40.487990] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   40.487996] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   40.488008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   40.488015] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   40.488021] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   40.488027] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   40.488034] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   40.488042] [drm:i9xx_update_wm], memory self refresh disabled
>[   40.488545] [drm:intel_update_fbc], 
>[   40.552016] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   40.552032] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   46.615411] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   46.615425] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[   46.615435] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   46.618468] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   46.624191] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   46.624387] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   46.630538] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   46.686706] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[   46.686718] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[   51.226437] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   51.226454] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1]
>[   51.282225] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   51.282238] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   51.282248] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   51.285277] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   51.324815] [drm:intel_update_fbc], 
>[   51.324824] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.324833] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   51.324839] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   51.324846] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.324854] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   51.324860] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   51.324866] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   51.324874] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   51.324882] [drm:i9xx_update_wm], memory self refresh disabled
>[   51.325320] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   51.325327] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   51.356016] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   51.356029] [drm:intel_update_fbc], 
>[   51.356036] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.356044] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   51.356050] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   51.356057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.356064] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   51.356070] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   51.356076] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   51.356084] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   51.356092] [drm:i9xx_update_wm], memory self refresh disabled
>[   51.356100] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   51.356109] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.356116] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   51.356123] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   51.356129] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.356136] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   51.356142] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   51.356148] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   51.356155] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   51.356163] [drm:i9xx_update_wm], memory self refresh disabled
>[   51.356666] [drm:intel_update_fbc], 
>[   51.427412] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   51.427422] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   51.440017] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   51.440036] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected
>[   51.440080] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   51.440088] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1]
>[   51.495495] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   51.495504] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   51.495513] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   51.495615] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   51.522894] [drm:intel_update_fbc], 
>[   51.522903] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.522911] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   51.522917] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   51.522924] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.522931] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   51.522938] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   51.522944] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   51.522951] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   51.522959] [drm:i9xx_update_wm], memory self refresh disabled
>[   51.523393] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   51.523399] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   51.552014] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   51.552027] [drm:intel_update_fbc], 
>[   51.552034] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.552041] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   51.552048] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   51.552054] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.552061] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   51.552068] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   51.552074] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   51.552081] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   51.552089] [drm:i9xx_update_wm], memory self refresh disabled
>[   51.552096] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   51.552105] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.552112] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   51.552118] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   51.552125] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.552132] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   51.552138] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   51.552144] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   51.552151] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   51.552159] [drm:i9xx_update_wm], memory self refresh disabled
>[   51.552662] [drm:intel_update_fbc], 
>[   51.623408] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   51.623417] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   51.636016] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   51.636031] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected
>[   51.636088] [drm:drm_mode_getconnector], [CONNECTOR:8:?]
>[   51.636098] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:HDMI-A-1]
>[   51.636109] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   51.639131] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   51.644942] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   51.645136] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   51.651331] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   51.707623] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   51.713701] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   51.770126] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:HDMI-A-1] probed modes :
>[   51.770136] [drm:drm_mode_debug_printmodeline], Modeline 26:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x48 0x9
>[   51.770150] [drm:drm_mode_debug_printmodeline], Modeline 32:"1600x1000" 60 133161 1600 1704 1872 2144 1000 1001 1004 1035 0x0 0x6
>[   51.770163] [drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   51.770175] [drm:drm_mode_debug_printmodeline], Modeline 29:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   51.770188] [drm:drm_mode_debug_printmodeline], Modeline 31:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[   51.770201] [drm:drm_mode_debug_printmodeline], Modeline 30:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[   51.770214] [drm:drm_mode_debug_printmodeline], Modeline 28:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   51.770226] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   51.770239] [drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   51.770251] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   51.770264] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   51.770276] [drm:drm_mode_debug_printmodeline], Modeline 42:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   51.770289] [drm:drm_mode_debug_printmodeline], Modeline 33:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   51.770301] [drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[   51.770313] [drm:drm_mode_debug_printmodeline], Modeline 34:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   51.770325] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 66 26885 640 664 728 816 480 481 484 499 0x0 0x6
>[   51.770337] [drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   51.770350] [drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   51.770397] [drm:drm_mode_getconnector], [CONNECTOR:8:?]
>[   51.771366] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   51.771378] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1]
>[   51.771389] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   51.771398] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   51.771413] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   51.806901] [drm:intel_update_fbc], 
>[   51.806910] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.806919] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   51.806926] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   51.806932] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.806940] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   51.806946] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   51.806952] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   51.806960] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   51.806968] [drm:i9xx_update_wm], memory self refresh disabled
>[   51.807406] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   51.807413] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   51.844015] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   51.844027] [drm:intel_update_fbc], 
>[   51.844035] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.844043] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   51.844050] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   51.844056] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.844063] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   51.844070] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   51.844076] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   51.844083] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   51.844091] [drm:i9xx_update_wm], memory self refresh disabled
>[   51.844099] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   51.868947] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.868955] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   51.868961] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   51.868968] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.868975] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   51.868981] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   51.868987] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   51.868994] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   51.869001] [drm:i9xx_update_wm], memory self refresh disabled
>[   51.869505] [drm:intel_update_fbc], 
>[   51.932015] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   51.932033] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   51.932072] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   51.932080] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1]
>[   51.932090] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   51.932099] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   51.932112] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   51.964818] [drm:intel_update_fbc], 
>[   51.964826] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.964834] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   51.964841] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   51.964847] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.964854] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   51.964861] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   51.964867] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   51.964874] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   51.964882] [drm:i9xx_update_wm], memory self refresh disabled
>[   51.965316] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   51.965323] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   52.004017] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   52.004029] [drm:intel_update_fbc], 
>[   52.004036] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   52.004044] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   52.004051] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   52.004057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   52.004064] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   52.004071] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   52.004077] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   52.004084] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   52.004092] [drm:i9xx_update_wm], memory self refresh disabled
>[   52.004100] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   52.023987] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   52.023994] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   52.024007] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   52.024014] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   52.024021] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   52.024027] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   52.024033] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   52.024040] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   52.024048] [drm:i9xx_update_wm], memory self refresh disabled
>[   52.024550] [drm:intel_update_fbc], 
>[   52.088018] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   52.088037] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   52.308669] [drm:i915_driver_open], 
>[   52.336412] [drm:i915_driver_open], 
>[   52.373545] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[   52.379103] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.381832] [drm:drm_mode_addfb], [FB:50]
>[   52.381905] [drm:drm_crtc_helper_set_config], 
>[   52.381911] [drm:drm_crtc_helper_set_config], [CRTC:3] [NOFB]
>[   52.381929] [drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[   52.381937] [drm:drm_crtc_helper_set_config], [CONNECTOR:8:HDMI-A-1] to [NOCRTC]
>[   52.386109] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
>[   52.402855] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
>[   52.419568] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
>[   52.435541] [drm:drm_mode_addfb], [FB:46]
>[   52.435587] [drm:drm_mode_setcrtc], [CRTC:3]
>[   52.435599] [drm:drm_mode_setcrtc], [CONNECTOR:8:HDMI-A-1]
>[   52.435607] [drm:drm_crtc_helper_set_config], 
>[   52.435613] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:46] #connectors=1 (x y) (0 0)
>[   52.435633] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[   52.435643] [drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[   52.435651] [drm:drm_crtc_helper_set_config], [CONNECTOR:8:HDMI-A-1] to [CRTC:3]
>[   52.435659] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[   52.435666] [drm:drm_mode_debug_printmodeline], Modeline 51:"" 0 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x0 0x9
>[   52.435685] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[   52.435694] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[   52.441287] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.475857] [drm:intel_update_fbc], 
>[   52.475866] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   52.475874] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   52.475882] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   52.475888] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   52.475895] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 1
>[   52.475902] [drm:i9xx_update_wm], self-refresh entries: 105
>[   52.475909] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 1, C: 2, SR 1
>[   52.475918] [drm:i9xx_update_wm], memory self refresh enabled
>[   52.476372] [drm:i9xx_crtc_mode_set], Mode for pipe A:
>[   52.476378] [drm:drm_mode_debug_printmodeline], Modeline 51:"" 0 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x0 0x9
>[   52.541312] [drm:intel_pipe_set_base_atomic], Writing base 05000000 00000000 0 0 8192
>[   52.541327] [drm:intel_update_fbc], 
>[   52.541335] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   52.541343] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   52.541350] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   52.541357] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   52.541363] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 1
>[   52.541371] [drm:i9xx_update_wm], self-refresh entries: 105
>[   52.541377] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 1, C: 2, SR 1
>[   52.541386] [drm:i9xx_update_wm], memory self refresh enabled
>[   52.541396] [drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7] set [MODE:51:]
>[   52.541406] [drm:intel_sdvo_debug_write], SDVOB: W: 07 01 00 00 00             (SDVO_CMD_SET_IN_OUT_MAP)
>[   52.549437] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.551356] [drm:intel_sdvo_debug_write], SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>[   52.556873] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.559822] [drm:intel_sdvo_debug_write], SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>[   52.565345] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.567147] [drm:intel_sdvo_debug_write], SDVOB: W: 16 7C 2E 90 A0 60 1A 1E 40 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>[   52.580163] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.582272] [drm:intel_sdvo_debug_write], SDVOB: W: 17 30 20 36 00 1A 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>[   52.595301] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.597108] [drm:intel_sdvo_debug_write], SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>[   52.601375] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.603136] [drm:intel_sdvo_debug_write], SDVOB: W: 9F 00                      (SDVO_CMD_SET_ENCODE)
>[   52.607402] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.609163] [drm:intel_sdvo_debug_write], SDVOB: W: 14 7C 2E 90 A0 60 1A 1E 40 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>[   52.622887] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.624652] [drm:intel_sdvo_debug_write], SDVOB: W: 15 30 20 36 00 1A 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>[   52.637871] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.639633] [drm:intel_sdvo_debug_write], SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>[   52.643907] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.645827] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   52.645836] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   52.645843] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   52.645850] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   52.645856] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 1
>[   52.645863] [drm:i9xx_update_wm], self-refresh entries: 105
>[   52.645869] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 1, C: 2, SR 1
>[   52.645878] [drm:i9xx_update_wm], memory self refresh enabled
>[   52.646824] [drm:intel_update_fbc], 
>[   52.684012] [drm:intel_sdvo_debug_write], SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>[   52.687034] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01
>[   52.690701] [drm:intel_sdvo_debug_write], SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[   52.696227] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[   52.698034] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[   52.698043] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:8:HDMI-A-1] set DPMS on
>[   53.575640] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   53.575655] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1]
>[   53.631104] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   53.631114] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   53.631124] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   53.631673] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   53.655867] [drm:intel_update_fbc], 
>[   53.655876] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   53.655884] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   53.655891] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   53.655898] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   53.655905] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   53.655912] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   53.655918] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   53.655926] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   53.655934] [drm:i9xx_update_wm], memory self refresh disabled
>[   53.656387] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   53.656394] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   53.688032] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   53.688050] [drm:intel_update_fbc], 
>[   53.688058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   53.688066] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   53.688073] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   53.688080] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   53.688087] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   53.688094] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   53.688100] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   53.688108] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   53.688116] [drm:i9xx_update_wm], memory self refresh disabled
>[   53.688126] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   53.688137] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   53.688143] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   53.688150] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   53.688156] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   53.688163] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   53.688170] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   53.688175] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   53.688182] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   53.688190] [drm:i9xx_update_wm], memory self refresh disabled
>[   53.688695] [drm:intel_update_fbc], 
>[   53.759719] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   53.759732] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   53.772315] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   53.772337] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected
>[   53.772386] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   53.772395] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1]
>[   53.829987] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   53.830001] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   53.830010] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   53.830114] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   53.855864] [drm:intel_update_fbc], 
>[   53.855874] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   53.855883] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   53.855890] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   53.855896] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   53.855904] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   53.855910] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   53.855916] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   53.855924] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   53.855932] [drm:i9xx_update_wm], memory self refresh disabled
>[   53.856384] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   53.856391] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   53.888025] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   53.888041] [drm:intel_update_fbc], 
>[   53.888049] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   53.888057] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   53.888064] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   53.888071] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   53.888079] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   53.888085] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   53.888091] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   53.888099] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   53.888107] [drm:i9xx_update_wm], memory self refresh disabled
>[   53.888118] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   53.888129] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   53.888136] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   53.888142] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   53.888148] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   53.888155] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   53.888162] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   53.888168] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   53.888174] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   53.888182] [drm:i9xx_update_wm], memory self refresh disabled
>[   53.888687] [drm:intel_update_fbc], 
>[   53.959410] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   53.959420] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   53.972016] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   53.972034] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected
>[   53.972107] [drm:drm_mode_getconnector], [CONNECTOR:8:?]
>[   53.972117] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:HDMI-A-1]
>[   53.972128] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   53.975150] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   53.980929] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   53.981120] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   53.987270] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   54.043561] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   54.049622] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   54.106093] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:HDMI-A-1] probed modes :
>[   54.106104] [drm:drm_mode_debug_printmodeline], Modeline 26:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x48 0x9
>[   54.106118] [drm:drm_mode_debug_printmodeline], Modeline 32:"1600x1000" 60 133161 1600 1704 1872 2144 1000 1001 1004 1035 0x0 0x6
>[   54.106131] [drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   54.106143] [drm:drm_mode_debug_printmodeline], Modeline 29:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   54.106156] [drm:drm_mode_debug_printmodeline], Modeline 31:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[   54.106169] [drm:drm_mode_debug_printmodeline], Modeline 30:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[   54.106182] [drm:drm_mode_debug_printmodeline], Modeline 28:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   54.106194] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   54.106207] [drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   54.106219] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   54.106232] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   54.106244] [drm:drm_mode_debug_printmodeline], Modeline 42:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   54.106257] [drm:drm_mode_debug_printmodeline], Modeline 33:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   54.106269] [drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[   54.106281] [drm:drm_mode_debug_printmodeline], Modeline 34:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   54.106293] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 66 26885 640 664 728 816 480 481 484 499 0x0 0x6
>[   54.106305] [drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   54.106317] [drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   54.106363] [drm:drm_mode_getconnector], [CONNECTOR:8:?]
>[   54.107378] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   54.107390] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1]
>[   54.107401] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   54.107410] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   54.107426] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   54.139857] [drm:intel_update_fbc], 
>[   54.139866] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   54.139874] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   54.139881] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   54.139888] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   54.139895] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   54.139901] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   54.139907] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   54.139915] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   54.139923] [drm:i9xx_update_wm], memory self refresh disabled
>[   54.140371] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   54.140378] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   54.180018] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   54.180030] [drm:intel_update_fbc], 
>[   54.180038] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   54.180045] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   54.180052] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   54.180059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   54.180066] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   54.180072] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   54.180078] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   54.180085] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   54.180093] [drm:i9xx_update_wm], memory self refresh disabled
>[   54.180102] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   54.199990] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   54.199998] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   54.200010] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   54.200016] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   54.200023] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   54.200030] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   54.200035] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   54.200042] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   54.200050] [drm:i9xx_update_wm], memory self refresh disabled
>[   54.200553] [drm:intel_update_fbc], 
>[   54.264015] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   54.264032] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   54.264068] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   54.264077] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1]
>[   54.264086] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   54.264094] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   54.264107] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   54.296819] [drm:intel_update_fbc], 
>[   54.296827] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   54.296835] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   54.296842] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   54.296848] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   54.296856] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   54.296862] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   54.296868] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   54.296875] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   54.296884] [drm:i9xx_update_wm], memory self refresh disabled
>[   54.297317] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   54.297323] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   54.336015] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   54.336027] [drm:intel_update_fbc], 
>[   54.336034] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   54.336041] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   54.336048] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   54.336054] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   54.336061] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   54.336068] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   54.336074] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   54.336081] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   54.336089] [drm:i9xx_update_wm], memory self refresh disabled
>[   54.336097] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   54.355983] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   54.355991] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   54.355997] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   54.356009] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   54.356015] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   54.356022] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   54.356028] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   54.356035] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   54.356043] [drm:i9xx_update_wm], memory self refresh disabled
>[   54.356545] [drm:intel_update_fbc], 
>[   54.420014] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   54.420030] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   54.727964] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   54.727981] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1]
>[   54.783420] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   54.783430] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   54.783440] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   54.834653] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   54.872814] [drm:intel_update_fbc], 
>[   54.872824] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   54.872832] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   54.872839] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   54.872846] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   54.872853] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   54.872860] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   54.872866] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   54.872873] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   54.872882] [drm:i9xx_update_wm], memory self refresh disabled
>[   54.873320] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   54.873327] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   54.904018] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   54.904032] [drm:intel_update_fbc], 
>[   54.904039] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   54.904047] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   54.904053] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   54.904060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   54.904067] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   54.904073] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   54.904080] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   54.904087] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   54.904095] [drm:i9xx_update_wm], memory self refresh disabled
>[   54.904104] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   54.904113] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   54.904120] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   54.904127] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   54.904133] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   54.904140] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   54.904146] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   54.904152] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   54.904159] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   54.904167] [drm:i9xx_update_wm], memory self refresh disabled
>[   54.904670] [drm:intel_update_fbc], 
>[   54.975418] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   54.975428] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   54.988017] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   54.988035] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected
>[   54.988079] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   54.988088] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1]
>[   55.043505] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   55.043515] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   55.043523] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   55.043672] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   55.070895] [drm:intel_update_fbc], 
>[   55.070904] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   55.070913] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   55.070919] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   55.070926] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   55.070933] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   55.070939] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   55.070945] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   55.070952] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   55.070960] [drm:i9xx_update_wm], memory self refresh disabled
>[   55.071395] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   55.071402] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   55.100016] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   55.100027] [drm:intel_update_fbc], 
>[   55.100034] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   55.100042] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   55.100049] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   55.100055] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   55.100062] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   55.100068] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   55.100075] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   55.100082] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   55.100090] [drm:i9xx_update_wm], memory self refresh disabled
>[   55.100098] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   55.100107] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   55.100114] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   55.100121] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   55.100127] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   55.100134] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   55.100140] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   55.100146] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   55.100153] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   55.100161] [drm:i9xx_update_wm], memory self refresh disabled
>[   55.100664] [drm:intel_update_fbc], 
>[   55.171408] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   55.171419] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   55.184018] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   55.184034] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected
>[   55.184099] [drm:drm_mode_getconnector], [CONNECTOR:8:?]
>[   55.184109] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:HDMI-A-1]
>[   55.184121] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   55.187142] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   55.192973] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   55.193170] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   55.199325] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   55.255623] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   55.261700] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   55.318123] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:HDMI-A-1] probed modes :
>[   55.318133] [drm:drm_mode_debug_printmodeline], Modeline 26:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x48 0x9
>[   55.318147] [drm:drm_mode_debug_printmodeline], Modeline 32:"1600x1000" 60 133161 1600 1704 1872 2144 1000 1001 1004 1035 0x0 0x6
>[   55.318159] [drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   55.318172] [drm:drm_mode_debug_printmodeline], Modeline 29:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   55.318185] [drm:drm_mode_debug_printmodeline], Modeline 31:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[   55.318197] [drm:drm_mode_debug_printmodeline], Modeline 30:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[   55.318210] [drm:drm_mode_debug_printmodeline], Modeline 28:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   55.318223] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   55.318235] [drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   55.318248] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   55.318260] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   55.318272] [drm:drm_mode_debug_printmodeline], Modeline 42:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   55.318285] [drm:drm_mode_debug_printmodeline], Modeline 33:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   55.318297] [drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[   55.318309] [drm:drm_mode_debug_printmodeline], Modeline 34:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   55.318321] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 66 26885 640 664 728 816 480 481 484 499 0x0 0x6
>[   55.318334] [drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   55.318346] [drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   55.318389] [drm:drm_mode_getconnector], [CONNECTOR:8:?]
>[   55.319345] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   55.319357] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1]
>[   55.319367] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   55.319377] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   55.319392] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   55.354899] [drm:intel_update_fbc], 
>[   55.354907] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   55.354915] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   55.354922] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   55.354929] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   55.354936] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   55.354943] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   55.354949] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   55.354956] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   55.354964] [drm:i9xx_update_wm], memory self refresh disabled
>[   55.355402] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   55.355409] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   55.392017] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   55.392029] [drm:intel_update_fbc], 
>[   55.392036] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   55.392044] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   55.392051] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   55.392057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   55.392064] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   55.392070] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   55.392076] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   55.392083] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   55.392091] [drm:i9xx_update_wm], memory self refresh disabled
>[   55.392099] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   55.416950] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   55.416958] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   55.416964] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   55.416971] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   55.416977] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   55.416984] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   55.416990] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   55.416997] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   55.417004] [drm:i9xx_update_wm], memory self refresh disabled
>[   55.417507] [drm:intel_update_fbc], 
>[   55.480016] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   55.480033] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   55.480073] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   55.480081] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1]
>[   55.480091] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   55.480100] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   55.480113] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   55.512817] [drm:intel_update_fbc], 
>[   55.512826] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   55.512834] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   55.512841] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   55.512847] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   55.512854] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   55.512861] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   55.512867] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   55.512874] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   55.512882] [drm:i9xx_update_wm], memory self refresh disabled
>[   55.513316] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   55.513323] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   55.552015] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   55.552027] [drm:intel_update_fbc], 
>[   55.552035] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   55.552043] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   55.552049] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   55.552056] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   55.552063] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   55.552069] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   55.552075] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   55.552082] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   55.552090] [drm:i9xx_update_wm], memory self refresh disabled
>[   55.552098] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   55.571984] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   55.571992] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   55.571999] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   55.572011] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   55.572018] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   55.572024] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   55.572030] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   55.572037] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   55.572045] [drm:i9xx_update_wm], memory self refresh disabled
>[   55.572547] [drm:intel_update_fbc], 
>[   55.636015] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   55.636031] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   56.759549] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   56.759565] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[   56.759575] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   56.766374] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   56.774780] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   56.774790] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   56.780919] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   56.837203] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[   56.837216] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[   58.781825] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   58.781847] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1]
>[   58.837946] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   58.837960] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   58.837969] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   58.866698] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   58.904863] [drm:intel_update_fbc], 
>[   58.904875] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   58.904884] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   58.904891] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   58.904897] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   58.904905] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   58.904911] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   58.904917] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   58.904925] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   58.904933] [drm:i9xx_update_wm], memory self refresh disabled
>[   58.905375] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   58.905382] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   58.940068] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   58.940083] [drm:intel_update_fbc], 
>[   58.940092] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   58.940100] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   58.940107] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   58.940113] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   58.940121] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   58.940127] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   58.940133] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   58.940141] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   58.940149] [drm:i9xx_update_wm], memory self refresh disabled
>[   58.940159] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   58.940170] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   58.940177] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   58.940183] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   58.940190] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   58.940197] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   58.940203] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   58.940209] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   58.940216] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   58.940224] [drm:i9xx_update_wm], memory self refresh disabled
>[   58.940728] [drm:intel_update_fbc], 
>[   59.003746] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   59.003760] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   59.027583] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   59.027606] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected
>[   59.027660] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   59.027669] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1]
>[   59.086607] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   59.086624] [drm:intel_get_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   59.086634] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   59.094847] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   59.119907] [drm:intel_update_fbc], 
>[   59.119919] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   59.119928] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   59.119935] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   59.119941] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   59.119949] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   59.119955] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   59.119961] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   59.119969] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   59.119977] [drm:i9xx_update_wm], memory self refresh disabled
>[   59.120436] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   59.120443] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   59.168064] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   59.168080] [drm:intel_update_fbc], 
>[   59.168089] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   59.168097] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   59.168104] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   59.168110] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   59.168117] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   59.168124] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   59.168130] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   59.168138] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   59.168146] [drm:i9xx_update_wm], memory self refresh disabled
>[   59.168156] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480]
>[   59.168167] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   59.168174] [drm:intel_calculate_wm], FIFO entries required for mode: 10
>[   59.168181] [drm:intel_calculate_wm], FIFO watermark level: 16
>[   59.168187] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   59.168194] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   59.168200] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   59.168206] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1
>[   59.168213] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1
>[   59.168221] [drm:i9xx_update_wm], memory self refresh disabled
>[   59.168726] [drm:intel_update_fbc], 
>[   59.231820] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   59.231833] [drm:intel_crt_load_detect], starting load-detect on CRT
>[   59.252069] [drm:intel_release_load_detect_pipe], [CONNECTOR:5:VGA-1], [ENCODER:6:DAC-6]
>[   59.252091] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected
>[   59.252163] [drm:drm_mode_getconnector], [CONNECTOR:8:?]
>[   59.252173] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:HDMI-A-1]
>[   59.252184] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   59.255210] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   59.262526] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   59.262536] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   59.284078] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   59.352068] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   59.378064] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   59.480824] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:HDMI-A-1] probed modes :
>[   59.480837] [drm:drm_mode_debug_printmodeline], Modeline 26:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x48 0x9
>[   59.480850] [drm:drm_mode_debug_printmodeline], Modeline 32:"1600x1000" 60 133161 1600 1704 1872 2144 1000 1001 1004 1035 0x0 0x6
>[   59.480863] [drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   59.480876] [drm:drm_mode_debug_printmodeline], Modeline 29:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   59.480889] [drm:drm_mode_debug_printmodeline], Modeline 31:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[   59.480902] [drm:drm_mode_debug_printmodeline], Modeline 30:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[   59.480914] [drm:drm_mode_debug_printmodeline], Modeline 28:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   59.480927] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   59.480939] [drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   59.480952] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   59.480964] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   59.480977] [drm:drm_mode_debug_printmodeline], Modeline 42:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   59.480989] [drm:drm_mode_debug_printmodeline], Modeline 33:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   59.481001] [drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[   59.481013] [drm:drm_mode_debug_printmodeline], Modeline 34:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   59.481026] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 66 26885 640 664 728 816 480 481 484 499 0x0 0x6
>[   59.481038] [drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   59.481050] [drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   59.481113] [drm:drm_mode_getconnector], [CONNECTOR:8:?]
>[   59.482178] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   59.482191] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1]
>[   59.482202] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   59.482212] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   59.482228] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   59.510934] [drm:intel_update_fbc], 
>[   59.510946] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   59.510955] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   59.510962] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   59.510968] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   59.510976] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   59.510982] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   59.510988] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   59.510996] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   59.511004] [drm:i9xx_update_wm], memory self refresh disabled
>[   59.511444] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   59.511451] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   59.548278] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   59.548296] [drm:intel_update_fbc], 
>[   59.548305] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   59.548313] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   59.548320] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   59.548326] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   59.548334] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   59.548340] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   59.548346] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   59.548354] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   59.548362] [drm:i9xx_update_wm], memory self refresh disabled
>[   59.548376] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   59.573227] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   59.573236] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   59.573243] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   59.573249] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   59.573256] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   59.573262] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   59.573268] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   59.573275] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   59.573283] [drm:i9xx_update_wm], memory self refresh disabled
>[   59.573788] [drm:intel_update_fbc], 
>[   59.636083] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   59.636106] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   59.636155] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   59.636164] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1]
>[   59.636173] [drm:intel_get_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   59.636182] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
>[   59.636199] [drm:drm_crtc_helper_set_mode], [CRTC:4]
>[   59.669502] [drm:intel_update_fbc], 
>[   59.669514] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   59.669523] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   59.669530] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   59.669537] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   59.669544] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   59.669550] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   59.669556] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   59.669564] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   59.669572] [drm:i9xx_update_wm], memory self refresh disabled
>[   59.670013] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   59.670019] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   59.744089] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 6720
>[   59.744107] [drm:intel_update_fbc], 
>[   59.744117] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   59.744126] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   59.744132] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   59.744139] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   59.744147] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   59.744154] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   59.744160] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   59.744167] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   59.744175] [drm:i9xx_update_wm], memory self refresh disabled
>[   59.744187] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TV-11] set [MODE:0:NTSC 480i]
>[   59.764079] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   59.764086] [drm:intel_calculate_wm], FIFO entries required for mode: 34
>[   59.764093] [drm:intel_calculate_wm], FIFO watermark level: -8
>[   59.764099] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   59.764106] [drm:intel_calculate_wm], FIFO entries required for mode: 38
>[   59.764112] [drm:intel_calculate_wm], FIFO watermark level: -9
>[   59.764118] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1
>[   59.764125] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1
>[   59.764133] [drm:i9xx_update_wm], memory self refresh disabled
>[   59.764637] [drm:intel_update_fbc], 
>[   59.828061] [drm:intel_release_load_detect_pipe], [CONNECTOR:10:SVIDEO-1], [ENCODER:11:TV-11]
>[   59.828083] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected
>[   60.103898] [drm:i915_driver_open], 
>[   66.903501] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   66.903517] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[   66.903528] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   66.943028] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   66.951178] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   66.951190] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   66.964073] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   67.020323] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[   67.020336] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[   77.079488] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   77.079504] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[   77.079515] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   77.085293] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   77.094063] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   77.094075] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   77.106071] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   77.162276] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[   77.162289] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[   87.223437] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   87.223452] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[   87.223463] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   87.226673] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   87.237344] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   87.237880] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   87.243920] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   87.300079] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[   87.300091] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[   97.367444] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[   97.367458] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[   97.367469] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   97.375052] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   97.383537] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   97.383547] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   97.392364] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   97.448539] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[   97.448551] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[  107.511427] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[  107.511442] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[  107.511453] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  107.514660] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  107.520370] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  107.520565] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  107.527015] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  107.583193] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[  107.583205] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[  117.655435] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[  117.655450] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[  117.655462] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  117.658765] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  117.664499] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  117.664697] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  117.670848] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  117.727025] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[  117.727038] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[  127.799424] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[  127.799438] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[  127.799449] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  127.802842] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  127.813834] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  127.813844] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  127.821207] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  127.877419] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[  127.877431] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[  137.943472] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[  137.943487] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[  137.943498] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  137.963061] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  137.971626] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  137.976107] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  137.988044] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  138.044235] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[  138.044247] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[  148.119469] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[  148.119484] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[  148.119495] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  148.127063] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  148.135559] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  148.135570] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  148.148058] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  148.204231] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[  148.204243] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[  158.295433] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[  158.295448] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[  158.295459] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  158.298754] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  158.305407] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  158.310309] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  158.317042] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  158.373224] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[  158.373237] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[  166.575937] [drm:intel_crtc_cursor_set], 
>[  166.575947] [drm:intel_crtc_cursor_set], cursor off
>[  168.439433] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[  168.439448] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[  168.439459] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  168.442843] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  168.448543] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  168.448739] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  168.454883] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  168.511040] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[  168.511052] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[  178.583472] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[  178.583486] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[  178.583497] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  178.599195] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  178.611995] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  178.616042] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  178.627374] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  178.683596] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[  178.683609] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[  188.759447] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[  188.759462] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[  188.759473] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  188.762811] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  188.768527] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  188.768722] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  188.774871] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  188.831061] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[  188.831073] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[  198.903471] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[  198.903486] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[  198.903497] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  198.906901] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  198.913394] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  198.918527] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  198.925308] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  198.981515] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[  198.981528] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2
>[  209.047463] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [EDID reports a digital panel]
>[  209.047477] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2
>[  209.047488] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  209.059035] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  209.067520] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  209.067529] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  209.080020] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  209.136319] [drm:output_poll_execute], [CONNECTOR:8:HDMI-A-1] status updated from 1 to 1
>[  209.136333] [drm:output_poll_execute], [CONNECTOR:10:SVIDEO-1] status updated from 2 to 2

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Attachments on bug 37526: 47083 | 47084 | 47085 | 56587

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