Attachment 586 Details for Bug 922 – Radeon render patch

[patch] Radeon render patch

radeon_render_fixes.diff (text/plain), 6.14 KB, created by HUI YU on 2004-08-07 18:56:59 UTC

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Creator: HUI YU

Created: 2004-08-07 18:56:59 UTC

Size: 6.14 KB

patch

obsolete

>Index: radeon.man
>===================================================================
>RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man,v
>retrieving revision 1.6
>diff -u -r1.6 radeon.man
>--- radeon.man	30 Jul 2004 22:20:21 -0000	1.6
>+++ radeon.man	8 Aug 2004 01:14:23 -0000
>@@ -455,7 +455,7 @@
> Enable Render acceleration.  Does not support component alpha (subpixel)
> rendering.  Only supported on Radeon series up to and including 9200 (9500/9700
> and newer unsupported).  The default is 
>-.B on.
>+.B off.
> .TP
> .BI "Option \*qSubPixelOrder\*q \*q" "string" \*q
> Force subpixel order to specified order.
>Index: radeon_accel.c
>===================================================================
>RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c,v
>retrieving revision 1.8
>diff -u -r1.8 radeon_accel.c
>--- radeon_accel.c	30 Jul 2004 22:20:21 -0000	1.8
>+++ radeon_accel.c	8 Aug 2004 01:14:23 -0000
>@@ -314,17 +314,8 @@
>     OUTREG(RADEON_DP_WRITE_MASK,     0xffffffff);
> 
> #ifdef RENDER
>-    /* In the DRI case, it's initialized when the server grabs the lock.  We
>-     * don't hold the lock here, so don't do it in that case.
>-     */
>-#ifdef XF86DRI
>-    if (!info->directRenderingEnabled) {
>-#endif
>-	if (info->RenderAccel)
>-	    RADEONInit3DEngineForRender(pScrn);
>-#ifdef XF86DRI
>-    }
>-#endif
>+    if (info->RenderAccel)
>+        RADEONInit3DEngineForRender(pScrn);
> #endif
> 
>     RADEONWaitForIdleMMIO(pScrn);
>Index: radeon_accelfuncs.c
>===================================================================
>RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c,v
>retrieving revision 1.7
>diff -u -r1.7 radeon_accelfuncs.c
>--- radeon_accelfuncs.c	4 Aug 2004 10:05:37 -0000	1.7
>+++ radeon_accelfuncs.c	8 Aug 2004 01:14:23 -0000
>@@ -1350,7 +1350,7 @@
> 
> #if defined(RENDER)
> #if defined(XF86DRI)
>-    if (info->RenderAccel && info->directRenderingEnabled &&
>+    if (info->RenderAccel &&
> 	info->xaaReq.minorversion >= 2) {
> 	/* XXX: The non-CP vertex dispatch doesn't seem to work. */
> 
>Index: radeon_dri.c
>===================================================================
>RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c,v
>retrieving revision 1.5
>diff -u -r1.5 radeon_dri.c
>--- radeon_dri.c	10 Jul 2004 14:22:35 -0000	1.5
>+++ radeon_dri.c	8 Aug 2004 01:14:24 -0000
>@@ -345,15 +345,7 @@
>     RADEONInfoPtr  info  = RADEONPTR(pScrn);
> 
>     if (info->accel) info->accel->NeedToSync = TRUE;
>-#ifdef RENDER
>-    if (info->RenderAccel) {
>-	RADEONSAREAPrivPtr pSAREAPriv;
>-
>-	RADEONInit3DEngineForRender(pScrn);
>-	pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
>-	pSAREAPriv->ctxOwner = DRIGetContext(pScrn->pScreen);
>-    }
>-#endif
>+
> }
> 
> /* Called when the X server goes to sleep to allow the X server's
>Index: radeon_reg.h
>===================================================================
>RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v
>retrieving revision 1.6
>diff -u -r1.6 radeon_reg.h
>--- radeon_reg.h	30 Jul 2004 22:20:21 -0000	1.6
>+++ radeon_reg.h	8 Aug 2004 01:14:25 -0000
>@@ -2064,7 +2064,7 @@
> #       define RADEON_VF_PRIM_WALK_LIST               (2<<4)
> #       define RADEON_VF_PRIM_WALK_DATA               (3<<4)
> #       define RADEON_VF_COLOR_ORDER_RGBA             (1<<6)
>-#       define RADEON_VF_RADEON_MODE                  (1<<7)
>+#       define RADEON_VF_RADEON_MODE                  (1<<8)
> #       define RADEON_VF_TCL_OUTPUT_CTL_ENA           (1<<9)
> #       define RADEON_VF_PROG_STREAM_ENA              (1<<10)
> #       define RADEON_VF_INDEX_SIZE_SHIFT             11
>Index: radeon_render.c
>===================================================================
>RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_render.c,v
>retrieving revision 1.4
>diff -u -r1.4 radeon_render.c
>--- radeon_render.c	4 Aug 2004 13:17:31 -0000	1.4
>+++ radeon_render.c	8 Aug 2004 01:14:25 -0000
>@@ -230,7 +230,7 @@
> #ifdef XF86DRI
>     RADEONInfoPtr info = RADEONPTR (pScrn);
> 
>-    if (info->directRenderingEnabled)
>+    if (info->CPStarted)
> 	RadeonInit3DEngineCP(pScrn);
>     else
> #endif
>@@ -321,8 +321,13 @@
> 	       (info->ChipFamily == CHIP_FAMILY_RV280) || 
> 	       (info->ChipFamily == CHIP_FAMILY_RS300) || 
> 	       (info->ChipFamily == CHIP_FAMILY_R200)) {
>+
> 	BEGIN_ACCEL(7);
>-	OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
>+        if (info->ChipFamily == CHIP_FAMILY_RS300) {
>+            OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
>+        } else {
>+            OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
>+        }
> 	OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
> 	OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
> 	OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
>@@ -334,7 +339,11 @@
> 	FINISH_ACCEL();
>     } else {
> 	BEGIN_ACCEL(2);
>-	OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
>+        if ((info->ChipFamily == CHIP_FAMILY_RADEON) ||
>+            (info->ChipFamily == CHIP_FAMILY_RV200))
>+            OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0);
>+        else
>+            OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
> 	OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
> 	    RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
> 	    RADEON_VTX_ST0_NONPARAMETRIC |
>@@ -423,8 +432,13 @@
>     /* Upload texture to card.  Should use ImageWrite to avoid syncing. */
>     i = height;
>     dst = (CARD8*)(info->FB + offset);
>-    if (info->accel->NeedToSync)
>+
>+    if (info->accel->NeedToSync) {
> 	info->accel->Sync(pScrn);
>+	if (info->CPStarted)
>+	    RADEONInit3DEngineForRender(pScrn);
>+    }
>+
>     while(i--) {
> 	memcpy(dst, src, width * tex_bytepp);
> 	src += src_pitch;
>@@ -475,7 +489,7 @@
>     blend_cntl = RadeonGetBlendCntl(op, dstFormat);
>     if (blend_cntl == 0)
> 	return FALSE;
>-    
>+
>     if (!FUNC_NAME(R100SetupTexture)(pScrn, maskFormat, alphaPtr, alphaPitch,
> 				     width, height, flags))
> 	return FALSE;
>@@ -727,8 +741,12 @@
>     /* Upload texture to card.  Should use ImageWrite to avoid syncing. */
>     i = height;
>     dst = (CARD8*)(info->FB + offset);
>-    if (info->accel->NeedToSync)
>+    if (info->accel->NeedToSync) {
> 	info->accel->Sync(pScrn);
>+	if (info->CPStarted)
>+	    RADEONInit3DEngineForRender(pScrn);
>+    }
>+
>     while(i--) {
> 	memcpy(dst, src, width * tex_bytepp);
> 	src += src_pitch;

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