Attachment 58893 Details for Bug 39282 – possible fix

[patch] possible fix

0001-drm-radeon-kms-Fixup-backendmap-on-6xx-9xx.patch (text/plain), 19.88 KB, created by Alex Deucher on 2012-03-22 16:41:09 UTC

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Creator: Alex Deucher

Created: 2012-03-22 16:41:09 UTC

Size: 19.88 KB

patch

obsolete

>From f5f716166a57ea3c6178c64854e5e3a0bf59b48c Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexander.deucher@amd.com>
>Date: Thu, 22 Mar 2012 17:01:59 -0400
>Subject: [PATCH] drm/radeon/kms: Fixup backendmap on 6xx-9xx
>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>---
> drivers/gpu/drm/radeon/evergreen.c |  159 ++++++------------------------------
> drivers/gpu/drm/radeon/ni.c        |  105 ++++++++++--------------
> drivers/gpu/drm/radeon/nid.h       |    8 ++
> drivers/gpu/drm/radeon/r600.c      |   33 ++++----
> drivers/gpu/drm/radeon/rv770.c     |   40 ++++-----
> 5 files changed, 113 insertions(+), 232 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
>index cfa372c..ae185b3 100644
>--- a/drivers/gpu/drm/radeon/evergreen.c
>+++ b/drivers/gpu/drm/radeon/evergreen.c
>@@ -1960,20 +1960,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
> 
> 	evergreen_fix_pci_max_read_req_size(rdev);
> 
>-	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
>-
>-	cc_gc_shader_pipe_config |=
>-		INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
>-				  & EVERGREEN_MAX_PIPES_MASK);
>-	cc_gc_shader_pipe_config |=
>-		INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
>-			       & EVERGREEN_MAX_SIMDS_MASK);
>-
>-	cc_rb_backend_disable =
>-		BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
>-				& EVERGREEN_MAX_BACKENDS_MASK);
>-
>-
> 	mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
> 	if ((rdev->family == CHIP_PALM) ||
> 	    (rdev->family == CHIP_SUMO) ||
>@@ -2010,106 +1996,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
> 	else
> 		gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
> 
>-	if (rdev->ddev->pdev->device == 0x689e) {
>-		u32 efuse_straps_4;
>-		u32 efuse_straps_3;
>-		u8 efuse_box_bit_131_124;
>-
>-		WREG32(RCU_IND_INDEX, 0x204);
>-		efuse_straps_4 = RREG32(RCU_IND_DATA);
>-		WREG32(RCU_IND_INDEX, 0x203);
>-		efuse_straps_3 = RREG32(RCU_IND_DATA);
>-		efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
>-
>-		switch(efuse_box_bit_131_124) {
>-		case 0x00:
>-			gb_backend_map = 0x76543210;
>-			break;
>-		case 0x55:
>-			gb_backend_map = 0x77553311;
>-			break;
>-		case 0x56:
>-			gb_backend_map = 0x77553300;
>-			break;
>-		case 0x59:
>-			gb_backend_map = 0x77552211;
>-			break;
>-		case 0x66:
>-			gb_backend_map = 0x77443300;
>-			break;
>-		case 0x99:
>-			gb_backend_map = 0x66552211;
>-			break;
>-		case 0x5a:
>-			gb_backend_map = 0x77552200;
>-			break;
>-		case 0xaa:
>-			gb_backend_map = 0x66442200;
>-			break;
>-		case 0x95:
>-			gb_backend_map = 0x66553311;
>-			break;
>-		default:
>-			DRM_ERROR("bad backend map, using default\n");
>-			gb_backend_map =
>-				evergreen_get_tile_pipe_to_backend_map(rdev,
>-								       rdev->config.evergreen.max_tile_pipes,
>-								       rdev->config.evergreen.max_backends,
>-								       ((EVERGREEN_MAX_BACKENDS_MASK <<
>-								   rdev->config.evergreen.max_backends) &
>-									EVERGREEN_MAX_BACKENDS_MASK));
>-			break;
>-		}
>-	} else if (rdev->ddev->pdev->device == 0x68b9) {
>-		u32 efuse_straps_3;
>-		u8 efuse_box_bit_127_124;
>-
>-		WREG32(RCU_IND_INDEX, 0x203);
>-		efuse_straps_3 = RREG32(RCU_IND_DATA);
>-		efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
>-
>-		switch(efuse_box_bit_127_124) {
>-		case 0x0:
>-			gb_backend_map = 0x00003210;
>-			break;
>-		case 0x5:
>-		case 0x6:
>-		case 0x9:
>-		case 0xa:
>-			gb_backend_map = 0x00003311;
>-			break;
>-		default:
>-			DRM_ERROR("bad backend map, using default\n");
>-			gb_backend_map =
>-				evergreen_get_tile_pipe_to_backend_map(rdev,
>-								       rdev->config.evergreen.max_tile_pipes,
>-								       rdev->config.evergreen.max_backends,
>-								       ((EVERGREEN_MAX_BACKENDS_MASK <<
>-								   rdev->config.evergreen.max_backends) &
>-									EVERGREEN_MAX_BACKENDS_MASK));
>-			break;
>-		}
>-	} else {
>-		switch (rdev->family) {
>-		case CHIP_CYPRESS:
>-		case CHIP_HEMLOCK:
>-		case CHIP_BARTS:
>-			gb_backend_map = 0x66442200;
>-			break;
>-		case CHIP_JUNIPER:
>-			gb_backend_map = 0x00002200;
>-			break;
>-		default:
>-			gb_backend_map =
>-				evergreen_get_tile_pipe_to_backend_map(rdev,
>-								       rdev->config.evergreen.max_tile_pipes,
>-								       rdev->config.evergreen.max_backends,
>-								       ((EVERGREEN_MAX_BACKENDS_MASK <<
>-									 rdev->config.evergreen.max_backends) &
>-									EVERGREEN_MAX_BACKENDS_MASK));
>-		}
>-	}
>-
> 	/* setup tiling info dword.  gb_addr_config is not adequate since it does
> 	 * not have bank info, so create a custom tiling dword.
> 	 * bits 3:0   num_pipes
>@@ -2144,8 +2030,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
> 	rdev->config.evergreen.tile_config |=
> 		((gb_addr_config & 0x30000000) >> 28) << 12;
> 
>-	rdev->config.evergreen.backend_map = gb_backend_map;
>-	WREG32(GB_BACKEND_MAP, gb_backend_map);
> 	WREG32(GB_ADDR_CONFIG, gb_addr_config);
> 	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
> 	WREG32(HDP_ADDR_CONFIG, gb_addr_config);
>@@ -2154,22 +2038,33 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
> 	grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
> 
> 	for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
>-		u32 rb = cc_rb_backend_disable | (0xf0 << 16);
>-		u32 sp = cc_gc_shader_pipe_config;
>-		u32 gfx = grbm_gfx_index | SE_INDEX(i);
>-
>-		if (i == num_shader_engines) {
>-			rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
>-			sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
>-		}
>-
>-		WREG32(GRBM_GFX_INDEX, gfx);
>-		WREG32(RLC_GFX_INDEX, gfx);
>-
>-		WREG32(CC_RB_BACKEND_DISABLE, rb);
>-		WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
>-		WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
>-		WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
>+		WREG32(GRBM_GFX_INDEX, grbm_gfx_index | SE_INDEX(i));
>+		WREG32(RLC_GFX_INDEX, grbm_gfx_index | SE_INDEX(i));
>+
>+		cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
>+		tmp = EVERGREEN_MAX_BACKENDS -
>+			r600_count_pipe_bits((cc_rb_backend_disable >> 16) & EVERGREEN_MAX_BACKENDS_MASK);
>+		if (tmp < rdev->config.evergreen.max_backends)
>+			rdev->config.evergreen.max_backends = tmp;
>+
>+		cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
>+		tmp = EVERGREEN_MAX_PIPES -
>+			r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & EVERGREEN_MAX_PIPES_MASK);
>+		if (tmp < rdev->config.evergreen.max_pipes)
>+			rdev->config.evergreen.max_pipes = tmp;
>+		tmp = EVERGREEN_MAX_SIMDS -
>+			r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & EVERGREEN_MAX_SIMDS_MASK);
>+		if (tmp < rdev->config.evergreen.max_simds)
>+			rdev->config.evergreen.max_simds = tmp;
>+
>+		gb_backend_map =
>+			evergreen_get_tile_pipe_to_backend_map(rdev,
>+							       rdev->config.evergreen.max_tile_pipes,
>+							       rdev->config.evergreen.max_backends,
>+							       (cc_rb_backend_disable >> 16) & EVERGREEN_MAX_BACKENDS_MASK);
>+
>+		rdev->config.evergreen.backend_map = gb_backend_map;
>+		WREG32(GB_BACKEND_MAP, gb_backend_map);
>         }
> 
> 	grbm_gfx_index |= SE_BROADCAST_WRITES;
>diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
>index a48ca53..afbd8f0 100644
>--- a/drivers/gpu/drm/radeon/ni.c
>+++ b/drivers/gpu/drm/radeon/ni.c
>@@ -620,11 +620,9 @@ static void cayman_gpu_init(struct radeon_device *rdev)
> 	u32 cgts_tcc_disable;
> 	u32 sx_debug_1;
> 	u32 smx_dc_ctl0;
>-	u32 gc_user_shader_pipe_config;
>-	u32 gc_user_rb_backend_disable;
>-	u32 cgts_user_tcc_disable;
> 	u32 cgts_sm_ctrl_reg;
> 	u32 hdp_host_path_cntl;
>+	u32 grbm_gfx_index;
> 	u32 tmp;
> 	int i, j;
> 
>@@ -706,35 +704,45 @@ static void cayman_gpu_init(struct radeon_device *rdev)
> 	mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
> 	mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
> 
>-	cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
>-	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
>-	cgts_tcc_disable = 0xffff0000;
>-	for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
>-		cgts_tcc_disable &= ~(1 << (16 + i));
>-	gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
>-	gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
>-	cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
>-
>-	rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
>-	tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
>-	rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
>-	rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
>-	tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
>-	rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
>-	tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
>-	rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
>-	tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
>-	rdev->config.cayman.backend_disable_mask_per_asic =
>-		cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
>-						 rdev->config.cayman.num_shader_engines);
>-	rdev->config.cayman.backend_map =
>-		cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
>-						    rdev->config.cayman.num_backends_per_se *
>-						    rdev->config.cayman.num_shader_engines,
>-						    &rdev->config.cayman.backend_disable_mask_per_asic,
>-						    rdev->config.cayman.num_shader_engines);
>-	tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
>-	rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
>+	grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
>+	for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) {
>+		WREG32(GRBM_GFX_INDEX, grbm_gfx_index | SE_INDEX(i));
>+		WREG32(RLC_GFX_INDEX, grbm_gfx_index | SE_INDEX(i));
>+
>+		cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
>+		tmp = CAYMAN_MAX_BACKENDS -
>+			r600_count_pipe_bits((cc_rb_backend_disable >> 16) & CAYMAN_MAX_BACKENDS_MASK);
>+		if (tmp < rdev->config.cayman.max_backends_per_se)
>+			rdev->config.cayman.max_backends_per_se = tmp;
>+
>+		cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
>+		tmp = CAYMAN_MAX_PIPES -
>+			r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & CAYMAN_MAX_PIPES_MASK);
>+		if (tmp < rdev->config.cayman.max_pipes_per_simd)
>+			rdev->config.cayman.max_pipes_per_simd = tmp;
>+		tmp = CAYMAN_MAX_SIMDS -
>+			r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & CAYMAN_MAX_SIMDS_MASK);
>+		if (tmp < rdev->config.cayman.max_simds_per_se)
>+			rdev->config.cayman.max_simds_per_se = tmp;
>+
>+		rdev->config.cayman.backend_disable_mask_per_asic =
>+			cayman_get_disable_mask_per_asic(rdev, tmp,
>+							 rdev->config.cayman.max_backends_per_se,
>+							 rdev->config.cayman.num_shader_engines);
>+		gb_backend_map =
>+			cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.max_tile_pipes,
>+							    rdev->config.cayman.max_backends_per_se,
>+							    &rdev->config.cayman.backend_disable_mask_per_asic,
>+							    rdev->config.cayman.max_shader_engines);
>+
>+		rdev->config.cayman.backend_map = gb_backend_map;
>+		WREG32(GB_BACKEND_MAP, gb_backend_map);
>+        }
>+
>+	grbm_gfx_index |= SE_BROADCAST_WRITES;
>+	WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
>+	WREG32(RLC_GFX_INDEX, grbm_gfx_index);
>+
> 	tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
> 	rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
> 	if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
>@@ -748,10 +756,6 @@ static void cayman_gpu_init(struct radeon_device *rdev)
> 	rdev->config.cayman.num_gpus = 1;
> 	rdev->config.cayman.multi_gpu_tile_size = 64;
> 
>-	//gb_addr_config = 0x02011003
>-#if 0
>-	gb_addr_config = RREG32(GB_ADDR_CONFIG);
>-#else
> 	gb_addr_config = 0;
> 	switch (rdev->config.cayman.num_tile_pipes) {
> 	case 1:
>@@ -813,7 +817,6 @@ static void cayman_gpu_init(struct radeon_device *rdev)
> 		gb_addr_config |= ROW_SIZE(2);
> 		break;
> 	}
>-#endif
> 
> 	tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
> 	rdev->config.cayman.num_tile_pipes = (1 << tmp);
>@@ -828,17 +831,7 @@ static void cayman_gpu_init(struct radeon_device *rdev)
> 	tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
> 	rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
> 
>-	//gb_backend_map = 0x76541032;
>-#if 0
>-	gb_backend_map = RREG32(GB_BACKEND_MAP);
>-#else
>-	gb_backend_map =
>-		cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
>-						    rdev->config.cayman.num_backends_per_se *
>-						    rdev->config.cayman.num_shader_engines,
>-						    &rdev->config.cayman.backend_disable_mask_per_asic,
>-						    rdev->config.cayman.num_shader_engines);
>-#endif
>+
> 	/* setup tiling info dword.  gb_addr_config is not adequate since it does
> 	 * not have bank info, so create a custom tiling dword.
> 	 * bits 3:0   num_pipes
>@@ -874,25 +867,15 @@ static void cayman_gpu_init(struct radeon_device *rdev)
> 	rdev->config.cayman.tile_config |=
> 		((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
> 
>-	rdev->config.cayman.backend_map = gb_backend_map;
>-	WREG32(GB_BACKEND_MAP, gb_backend_map);
> 	WREG32(GB_ADDR_CONFIG, gb_addr_config);
> 	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
> 	WREG32(HDP_ADDR_CONFIG, gb_addr_config);
> 
>-	/* primary versions */
>-	WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
>-	WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
>-	WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
>-
>+	cgts_tcc_disable = 0xffff0000;
>+	for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
>+		cgts_tcc_disable &= ~(1 << (16 + i));
> 	WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
> 	WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
>-
>-	/* user versions */
>-	WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
>-	WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
>-	WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
>-
> 	WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
> 	WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
> 
>diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
>index 2aa7046..6fb7717 100644
>--- a/drivers/gpu/drm/radeon/nid.h
>+++ b/drivers/gpu/drm/radeon/nid.h
>@@ -148,6 +148,8 @@
> #define	CGTS_SYS_TCC_DISABLE				0x3F90
> #define	CGTS_USER_SYS_TCC_DISABLE			0x3F94
> 
>+#define RLC_GFX_INDEX           			0x3FC4
>+
> #define	CONFIG_MEMSIZE					0x5428
> 
> #define HDP_MEM_COHERENCY_FLUSH_CNTL			0x5480
>@@ -212,6 +214,12 @@
> #define		SOFT_RESET_VGT					(1 << 14)
> #define		SOFT_RESET_IA					(1 << 15)
> 
>+#define GRBM_GFX_INDEX          			0x802C
>+#define		INSTANCE_INDEX(x)			((x) << 0)
>+#define		SE_INDEX(x)     			((x) << 16)
>+#define		INSTANCE_BROADCAST_WRITES      		(1 << 30)
>+#define		SE_BROADCAST_WRITES      		(1 << 31)
>+
> #define	SCRATCH_REG0					0x8500
> #define	SCRATCH_REG1					0x8504
> #define	SCRATCH_REG2					0x8508
>diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
>index 391bd26..b86c9ee 100644
>--- a/drivers/gpu/drm/radeon/r600.c
>+++ b/drivers/gpu/drm/radeon/r600.c
>@@ -1637,20 +1637,24 @@ void r600_gpu_init(struct radeon_device *rdev)
> 	tiling_config |= BANK_SWAPS(1);
> 
> 	cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
>-	cc_rb_backend_disable |=
>-		BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
>-
>-	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
>-	cc_gc_shader_pipe_config |=
>-		INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
>-	cc_gc_shader_pipe_config |=
>-		INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
>+	tmp = R6XX_MAX_BACKENDS -
>+		r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
>+	if (tmp < rdev->config.r600.max_backends)
>+		rdev->config.r600.max_backends = tmp;
>+
>+	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
>+	tmp = R6XX_MAX_PIPES -
>+		r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
>+	if (tmp < rdev->config.r600.max_pipes)
>+		rdev->config.r600.max_pipes = tmp;
>+	tmp = R6XX_MAX_SIMDS -
>+		r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
>+	if (tmp < rdev->config.r600.max_simds)
>+		rdev->config.r600.max_simds = tmp;
> 
> 	backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
>-							(R6XX_MAX_BACKENDS -
>-							 r600_count_pipe_bits((cc_rb_backend_disable &
>-									       R6XX_MAX_BACKENDS_MASK) >> 16)),
>-							(cc_rb_backend_disable >> 16));
>+							rdev->config.r600.max_backends,
>+							(cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
> 	rdev->config.r600.tile_config = tiling_config;
> 	rdev->config.r600.backend_map = backend_map;
> 	tiling_config |= BACKEND_MAP(backend_map);
>@@ -1658,11 +1662,6 @@ void r600_gpu_init(struct radeon_device *rdev)
> 	WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
> 	WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
> 
>-	/* Setup pipes */
>-	WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
>-	WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
>-	WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
>-
> 	tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
> 	WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
> 	WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
>diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
>index c62ae4b..3f834f1 100644
>--- a/drivers/gpu/drm/radeon/rv770.c
>+++ b/drivers/gpu/drm/radeon/rv770.c
>@@ -557,7 +557,7 @@ static void rv770_gpu_init(struct radeon_device *rdev)
> 	u32 cc_rb_backend_disable = 0;
> 	u32 cc_gc_shader_pipe_config = 0;
> 	u32 mc_arb_ramcfg;
>-	u32 db_debug4;
>+	u32 db_debug4, tmp;
> 
> 	/* setup chip specs */
> 	switch (rdev->family) {
>@@ -710,24 +710,25 @@ static void rv770_gpu_init(struct radeon_device *rdev)
> 	gb_tiling_config |= BANK_SWAPS(1);
> 
> 	cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
>-	cc_rb_backend_disable |=
>-		BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
>+	tmp = R7XX_MAX_BACKENDS -
>+		r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R7XX_MAX_BACKENDS_MASK);
>+	if (tmp < rdev->config.rv770.max_backends)
>+		rdev->config.rv770.max_backends = tmp;
> 
> 	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
>-	cc_gc_shader_pipe_config |=
>-		INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
>-	cc_gc_shader_pipe_config |=
>-		INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
>-
>-	if (rdev->family == CHIP_RV740)
>-		backend_map = 0x28;
>-	else
>-		backend_map = r700_get_tile_pipe_to_backend_map(rdev,
>-								rdev->config.rv770.max_tile_pipes,
>-								(R7XX_MAX_BACKENDS -
>-								 r600_count_pipe_bits((cc_rb_backend_disable &
>-										       R7XX_MAX_BACKENDS_MASK) >> 16)),
>-								(cc_rb_backend_disable >> 16));
>+	tmp = R7XX_MAX_PIPES -
>+		r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK);
>+	if (tmp < rdev->config.rv770.max_pipes)
>+		rdev->config.rv770.max_pipes = tmp;
>+	tmp = R7XX_MAX_SIMDS -
>+		r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
>+	if (tmp < rdev->config.rv770.max_simds)
>+		rdev->config.rv770.max_simds = tmp;
>+
>+	backend_map = r700_get_tile_pipe_to_backend_map(rdev,
>+							rdev->config.rv770.max_tile_pipes,
>+							rdev->config.rv770.max_backends,
>+							(cc_rb_backend_disable >> 16) & R7XX_MAX_BACKENDS_MASK);
> 
> 	rdev->config.rv770.tile_config = gb_tiling_config;
> 	rdev->config.rv770.backend_map = backend_map;
>@@ -737,11 +738,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
> 	WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
> 	WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
> 
>-	WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
>-	WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
>-	WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
>-	WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
>-
> 	WREG32(CGTS_SYS_TCC_DISABLE, 0);
> 	WREG32(CGTS_TCC_DISABLE, 0);
> 	WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
>-- 
>1.7.7.5
>

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Attachments on bug 39282: 49177 | 49462 | 49463 | 53473 | 53756 | 53757 | 53814 | 54366 | 54374 | 58893 | 62030 | 62067 | 62543 | 62544 | 62545

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