Attachment 60549 Details for Bug 42194 – dmesg with patch

dmesg with patch

20120425dmesg.log (text/plain), 123.34 KB, created by Guang Yang on 2012-04-24 19:44:48 UTC

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Creator: Guang Yang

Created: 2012-04-24 19:44:48 UTC

Size: 123.34 KB

patch

obsolete

>t timed out
>[  189.686931] [drm:intel_wait_for_vblank], vblank wait timed out
>[  189.687747] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  189.687752] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  189.688409] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  189.688414] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  189.688417] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  189.688419] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  189.688425] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  189.689655] [drm:intel_update_fbc], 
>[  189.690076] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  189.690805] [drm:intel_dp_start_link_train], clock recovery OK
>[  189.692550] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  189.692553] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  189.711902] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  194.730574] [drm:drm_mode_addfb], [FB:68]
>[  194.730597] [drm:drm_mode_setcrtc], [CRTC:3]
>[  194.730602] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  194.730605] [drm:drm_crtc_helper_set_config], 
>[  194.730607] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:68] #connectors=1 (x y) (0 0)
>[  194.730614] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  194.730616] [drm:drm_mode_debug_printmodeline], Modeline 68:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  194.730622] [drm:drm_mode_debug_printmodeline], Modeline 70:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  194.730628] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  194.730631] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  194.730633] [drm:drm_mode_debug_printmodeline], Modeline 70:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  194.730640] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 148500KHz
>[  194.730644] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 2 clock 270000 bpp 24
>[  194.730647] [drm:intel_dp_mode_fixup], DP link bw required 356400 available 432000
>[  194.730650] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  194.730862] [drm:intel_dp_link_down], 
>[  194.766306] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  194.801371] [drm:intel_wait_for_vblank], vblank wait timed out
>[  194.827346] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  194.827353] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  194.827766] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  194.827770] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
>[  194.827774] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
>[  194.827778] [drm:ironlake_check_srwm], watermark 3: display plane 142, fbc lines 4, cursor 10
>[  194.827782] [drm:intel_update_fbc], 
>[  194.828093] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  194.828097] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  194.828100] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  194.828103] [drm:drm_mode_debug_printmodeline], Modeline 70:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  194.828109] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  194.828112] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  194.880285] [drm:intel_wait_for_vblank], vblank wait timed out
>[  194.885800] [drm:ironlake_update_plane], Writing base 055FD000 00000000 0 0 7680
>[  194.937223] [drm:intel_wait_for_vblank], vblank wait timed out
>[  194.937229] [drm:intel_update_fbc], 
>[  194.937232] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  194.937236] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
>[  194.937241] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
>[  194.937245] [drm:ironlake_check_srwm], watermark 3: display plane 142, fbc lines 4, cursor 10
>[  194.937250] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:70:1920x1080]
>[  194.937255] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  194.937259] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  194.937263] [drm:ironlake_write_eld], ELD on pipe A
>[  194.937266] [drm:ironlake_write_eld], Audio directed to unknown port
>[  194.937269] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  194.937283] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  194.937287] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
>[  194.937291] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
>[  194.937295] [drm:ironlake_check_srwm], watermark 3: display plane 142, fbc lines 4, cursor 10
>[  194.989167] [drm:intel_wait_for_vblank], vblank wait timed out
>[  195.041110] [drm:intel_wait_for_vblank], vblank wait timed out
>[  195.041925] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  195.041930] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  195.042587] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  195.042592] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  195.042594] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  195.042597] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  195.042602] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  195.043832] [drm:intel_update_fbc], 
>[  195.044253] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  195.044982] [drm:intel_dp_start_link_train], clock recovery OK
>[  195.046727] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  195.046731] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  195.062750] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  200.084415] [drm:drm_mode_addfb], [FB:70]
>[  200.084435] [drm:drm_mode_setcrtc], [CRTC:3]
>[  200.084439] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  200.084441] [drm:drm_crtc_helper_set_config], 
>[  200.084442] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:70] #connectors=1 (x y) (0 0)
>[  200.084447] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  200.084449] [drm:drm_mode_debug_printmodeline], Modeline 70:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  200.084453] [drm:drm_mode_debug_printmodeline], Modeline 71:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  200.084457] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  200.084459] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  200.084461] [drm:drm_mode_debug_printmodeline], Modeline 71:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  200.084465] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz
>[  200.084468] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  200.084470] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 216000
>[  200.084473] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  200.084695] [drm:intel_dp_link_down], 
>[  200.107173] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  200.155551] [drm:intel_wait_for_vblank], vblank wait timed out
>[  200.175533] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  200.175539] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  200.175952] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  200.175956] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  200.175960] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  200.175964] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  200.175968] [drm:intel_update_fbc], 
>[  200.176268] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  200.176272] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  200.176276] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  200.176278] [drm:drm_mode_debug_printmodeline], Modeline 71:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  200.176284] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  200.176288] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  200.228446] [drm:intel_wait_for_vblank], vblank wait timed out
>[  200.233909] [drm:ironlake_update_plane], Writing base 05DE6000 00000000 0 0 7680
>[  200.285410] [drm:intel_wait_for_vblank], vblank wait timed out
>[  200.285415] [drm:intel_update_fbc], 
>[  200.285418] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  200.285423] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  200.285427] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  200.285431] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  200.285436] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:71:1920x1080]
>[  200.285441] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  200.285445] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  200.285449] [drm:ironlake_write_eld], ELD on pipe A
>[  200.285453] [drm:ironlake_write_eld], Audio directed to unknown port
>[  200.285456] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  200.285470] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  200.285473] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  200.285477] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  200.285481] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  200.337353] [drm:intel_wait_for_vblank], vblank wait timed out
>[  200.389274] [drm:intel_wait_for_vblank], vblank wait timed out
>[  200.390089] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  200.390093] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  200.390750] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  200.390754] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  200.390757] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  200.390759] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  200.390765] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  200.391995] [drm:intel_update_fbc], 
>[  200.392416] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  200.393146] [drm:intel_dp_start_link_train], clock recovery OK
>[  200.394884] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  200.394887] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  200.435871] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  205.430980] [drm:drm_mode_addfb], [FB:71]
>[  205.430999] [drm:drm_mode_setcrtc], [CRTC:3]
>[  205.431002] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  205.431004] [drm:drm_crtc_helper_set_config], 
>[  205.431006] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:71] #connectors=1 (x y) (0 0)
>[  205.431010] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  205.431012] [drm:drm_mode_debug_printmodeline], Modeline 71:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  205.431016] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  205.431020] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  205.431022] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  205.431024] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  205.431028] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz
>[  205.431031] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  205.431033] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 216000
>[  205.431036] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  205.431247] [drm:intel_dp_link_down], 
>[  205.471982] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  205.501740] [drm:intel_wait_for_vblank], vblank wait timed out
>[  205.555684] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  205.555690] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  205.556103] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  205.556107] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  205.556111] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  205.556115] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  205.556119] [drm:intel_update_fbc], 
>[  205.556419] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  205.556423] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  205.556427] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  205.556429] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  205.556435] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  205.556438] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  205.608623] [drm:intel_wait_for_vblank], vblank wait timed out
>[  205.613655] [drm:ironlake_update_plane], Writing base 065CF000 00000000 0 0 7680
>[  205.665561] [drm:intel_wait_for_vblank], vblank wait timed out
>[  205.665566] [drm:intel_update_fbc], 
>[  205.665570] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  205.665574] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  205.665578] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  205.665582] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  205.665587] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:74:1920x1080]
>[  205.665593] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  205.665596] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  205.665600] [drm:ironlake_write_eld], ELD on pipe A
>[  205.665604] [drm:ironlake_write_eld], Audio directed to unknown port
>[  205.665607] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  205.665620] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  205.665624] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  205.665628] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  205.665632] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  205.717505] [drm:intel_wait_for_vblank], vblank wait timed out
>[  205.769449] [drm:intel_wait_for_vblank], vblank wait timed out
>[  205.770265] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  205.770269] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  205.770927] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  205.770931] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  205.770933] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  205.770936] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  205.770941] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  205.772172] [drm:intel_update_fbc], 
>[  205.772593] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  205.773322] [drm:intel_dp_start_link_train], clock recovery OK
>[  205.775068] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  205.775072] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  205.794437] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  210.812964] [drm:drm_mode_addfb], [FB:74]
>[  210.812993] [drm:drm_mode_setcrtc], [CRTC:3]
>[  210.812998] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  210.813000] [drm:drm_crtc_helper_set_config], 
>[  210.813002] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:74] #connectors=1 (x y) (0 0)
>[  210.813009] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  210.813011] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  210.813017] [drm:drm_mode_debug_printmodeline], Modeline 81:"1920x1080" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  210.813023] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  210.813026] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  210.813028] [drm:drm_mode_debug_printmodeline], Modeline 81:"1920x1080" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  210.813035] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz
>[  210.813038] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  210.813041] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 216000
>[  210.813043] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  210.813255] [drm:intel_dp_link_down], 
>[  210.848831] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  210.883889] [drm:intel_wait_for_vblank], vblank wait timed out
>[  210.909865] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  210.909871] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  210.910284] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  210.910288] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  210.910292] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  210.910296] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  210.910300] [drm:intel_update_fbc], 
>[  210.910620] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  210.910624] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  210.910628] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  210.910631] [drm:drm_mode_debug_printmodeline], Modeline 81:"1920x1080" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  210.910637] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  210.910640] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  210.962804] [drm:intel_wait_for_vblank], vblank wait timed out
>[  210.967721] [drm:ironlake_update_plane], Writing base 06DB8000 00000000 0 0 7680
>[  211.018743] [drm:intel_wait_for_vblank], vblank wait timed out
>[  211.018748] [drm:intel_update_fbc], 
>[  211.018752] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  211.018756] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  211.018760] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  211.018764] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  211.018769] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:81:1920x1080]
>[  211.018774] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  211.018778] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  211.018782] [drm:ironlake_write_eld], ELD on pipe A
>[  211.018786] [drm:ironlake_write_eld], Audio directed to unknown port
>[  211.018789] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  211.018802] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  211.018806] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  211.018810] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  211.018814] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  211.070687] [drm:intel_wait_for_vblank], vblank wait timed out
>[  211.122631] [drm:intel_wait_for_vblank], vblank wait timed out
>[  211.123447] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  211.123452] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  211.124109] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  211.124113] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  211.124116] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  211.124118] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  211.124124] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  211.125355] [drm:intel_update_fbc], 
>[  211.125775] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  211.126505] [drm:intel_dp_start_link_train], clock recovery OK
>[  211.128242] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  211.128245] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  211.144286] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  216.165675] [drm:drm_mode_addfb], [FB:81]
>[  216.165694] [drm:drm_mode_setcrtc], [CRTC:3]
>[  216.165697] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  216.165700] [drm:drm_crtc_helper_set_config], 
>[  216.165701] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:81] #connectors=1 (x y) (0 0)
>[  216.165705] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  216.165707] [drm:drm_mode_debug_printmodeline], Modeline 81:"1920x1080" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  216.165711] [drm:drm_mode_debug_printmodeline], Modeline 82:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  216.165715] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  216.165718] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  216.165720] [drm:drm_mode_debug_printmodeline], Modeline 82:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  216.165724] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 162000KHz
>[  216.165726] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 2 clock 270000 bpp 24
>[  216.165729] [drm:intel_dp_mode_fixup], DP link bw required 388800 available 432000
>[  216.165731] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  216.165942] [drm:intel_dp_link_down], 
>[  216.188678] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  216.236072] [drm:intel_wait_for_vblank], vblank wait timed out
>[  216.256055] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  216.256061] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  216.256474] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  216.256478] [drm:ironlake_check_srwm], watermark 1: display plane 13, fbc lines 3, cursor 6
>[  216.256482] [drm:ironlake_check_srwm], watermark 2: display plane 73, fbc lines 3, cursor 6
>[  216.256486] [drm:ironlake_check_srwm], watermark 3: display plane 154, fbc lines 4, cursor 10
>[  216.256490] [drm:intel_update_fbc], 
>[  216.256790] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  216.256794] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  216.256798] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  216.256800] [drm:drm_mode_debug_printmodeline], Modeline 82:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  216.256806] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  216.256810] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  216.308993] [drm:intel_wait_for_vblank], vblank wait timed out
>[  216.313932] [drm:ironlake_update_plane], Writing base 075A1000 00000000 0 0 6400
>[  216.364932] [drm:intel_wait_for_vblank], vblank wait timed out
>[  216.364937] [drm:intel_update_fbc], 
>[  216.364941] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  216.364945] [drm:ironlake_check_srwm], watermark 1: display plane 13, fbc lines 3, cursor 6
>[  216.364949] [drm:ironlake_check_srwm], watermark 2: display plane 73, fbc lines 3, cursor 6
>[  216.364953] [drm:ironlake_check_srwm], watermark 3: display plane 154, fbc lines 4, cursor 10
>[  216.364958] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:82:1600x1200]
>[  216.364964] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  216.364967] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  216.364971] [drm:ironlake_write_eld], ELD on pipe A
>[  216.364975] [drm:ironlake_write_eld], Audio directed to unknown port
>[  216.364978] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  216.364991] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  216.364995] [drm:ironlake_check_srwm], watermark 1: display plane 13, fbc lines 3, cursor 6
>[  216.364999] [drm:ironlake_check_srwm], watermark 2: display plane 73, fbc lines 3, cursor 6
>[  216.365003] [drm:ironlake_check_srwm], watermark 3: display plane 154, fbc lines 4, cursor 10
>[  216.416875] [drm:intel_wait_for_vblank], vblank wait timed out
>[  216.468819] [drm:intel_wait_for_vblank], vblank wait timed out
>[  216.469635] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  216.469639] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  216.470297] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  216.470301] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  216.470304] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  216.470306] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  216.470312] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  216.471535] [drm:intel_update_fbc], 
>[  216.471956] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  216.472686] [drm:intel_dp_start_link_train], clock recovery OK
>[  216.474431] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  216.474435] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  216.490454] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  221.508733] [drm:drm_mode_addfb], [FB:82]
>[  221.508751] [drm:drm_mode_setcrtc], [CRTC:3]
>[  221.508755] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  221.508757] [drm:drm_crtc_helper_set_config], 
>[  221.508758] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:82] #connectors=1 (x y) (0 0)
>[  221.508762] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  221.508764] [drm:drm_mode_debug_printmodeline], Modeline 82:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  221.508768] [drm:drm_mode_debug_printmodeline], Modeline 83:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  221.508772] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  221.508774] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  221.508776] [drm:drm_mode_debug_printmodeline], Modeline 83:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  221.508780] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 135000KHz
>[  221.508783] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 2 clock 270000 bpp 24
>[  221.508785] [drm:intel_dp_mode_fixup], DP link bw required 324000 available 432000
>[  221.508787] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  221.508998] [drm:intel_dp_link_down], 
>[  221.534876] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  221.579264] [drm:intel_wait_for_vblank], vblank wait timed out
>[  221.603242] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  221.603248] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  221.603661] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  221.603665] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
>[  221.603669] [drm:ironlake_check_srwm], watermark 2: display plane 62, fbc lines 3, cursor 6
>[  221.603673] [drm:ironlake_check_srwm], watermark 3: display plane 129, fbc lines 4, cursor 10
>[  221.603677] [drm:intel_update_fbc], 
>[  221.603977] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  221.603981] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  221.603985] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  221.603987] [drm:drm_mode_debug_printmodeline], Modeline 83:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  221.603993] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  221.603996] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  221.656154] [drm:intel_wait_for_vblank], vblank wait timed out
>[  221.659894] [drm:ironlake_update_plane], Writing base 07CF4000 00000000 0 0 5120
>[  221.711121] [drm:intel_wait_for_vblank], vblank wait timed out
>[  221.711126] [drm:intel_update_fbc], 
>[  221.711129] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  221.711133] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
>[  221.711138] [drm:ironlake_check_srwm], watermark 2: display plane 62, fbc lines 3, cursor 6
>[  221.711142] [drm:ironlake_check_srwm], watermark 3: display plane 129, fbc lines 4, cursor 10
>[  221.711147] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:83:1280x1024]
>[  221.711152] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  221.711156] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  221.711160] [drm:ironlake_write_eld], ELD on pipe A
>[  221.711164] [drm:ironlake_write_eld], Audio directed to unknown port
>[  221.711167] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  221.711180] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  221.711184] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
>[  221.711188] [drm:ironlake_check_srwm], watermark 2: display plane 62, fbc lines 3, cursor 6
>[  221.711192] [drm:ironlake_check_srwm], watermark 3: display plane 129, fbc lines 4, cursor 10
>[  221.763065] [drm:intel_wait_for_vblank], vblank wait timed out
>[  221.814982] [drm:intel_wait_for_vblank], vblank wait timed out
>[  221.815798] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  221.815802] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  221.816460] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  221.816464] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  221.816466] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  221.816469] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  221.816474] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  221.817705] [drm:intel_update_fbc], 
>[  221.818125] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  221.818853] [drm:intel_dp_start_link_train], clock recovery OK
>[  221.820592] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  221.820596] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  221.833286] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  226.854043] [drm:drm_mode_addfb], [FB:83]
>[  226.854062] [drm:drm_mode_setcrtc], [CRTC:3]
>[  226.854066] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  226.854068] [drm:drm_crtc_helper_set_config], 
>[  226.854069] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:83] #connectors=1 (x y) (0 0)
>[  226.854073] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  226.854075] [drm:drm_mode_debug_printmodeline], Modeline 83:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  226.854079] [drm:drm_mode_debug_printmodeline], Modeline 84:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  226.854083] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  226.854085] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  226.854087] [drm:drm_mode_debug_printmodeline], Modeline 84:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  226.854091] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 108000KHz
>[  226.854094] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  226.854096] [drm:intel_dp_mode_fixup], DP link bw required 259200 available 259200
>[  226.854098] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  226.854309] [drm:intel_dp_link_down], 
>[  226.879379] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  226.924454] [drm:intel_wait_for_vblank], vblank wait timed out
>[  226.946434] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  226.946440] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  226.946853] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
>[  226.946857] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
>[  226.946861] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
>[  226.946865] [drm:ironlake_check_srwm], watermark 3: display plane 104, fbc lines 4, cursor 10
>[  226.946869] [drm:intel_update_fbc], 
>[  226.947179] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  226.947183] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  226.947187] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  226.947189] [drm:drm_mode_debug_printmodeline], Modeline 84:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  226.947195] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  226.947199] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  226.999346] [drm:intel_wait_for_vblank], vblank wait timed out
>[  227.002660] [drm:ironlake_update_plane], Writing base 081F4000 00000000 0 0 5120
>[  227.054312] [drm:intel_wait_for_vblank], vblank wait timed out
>[  227.054318] [drm:intel_update_fbc], 
>[  227.054321] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
>[  227.054325] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
>[  227.054329] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
>[  227.054334] [drm:ironlake_check_srwm], watermark 3: display plane 104, fbc lines 4, cursor 10
>[  227.054339] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:84:1280x1024]
>[  227.054344] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  227.054348] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  227.054351] [drm:ironlake_write_eld], ELD on pipe A
>[  227.054355] [drm:ironlake_write_eld], Audio directed to unknown port
>[  227.054358] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  227.054372] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
>[  227.054376] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
>[  227.054379] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
>[  227.054383] [drm:ironlake_check_srwm], watermark 3: display plane 104, fbc lines 4, cursor 10
>[  227.106257] [drm:intel_wait_for_vblank], vblank wait timed out
>[  227.158200] [drm:intel_wait_for_vblank], vblank wait timed out
>[  227.159016] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  227.159021] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  227.159678] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  227.159683] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  227.159685] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  227.159688] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  227.159693] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  227.160916] [drm:intel_update_fbc], 
>[  227.161337] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  227.162066] [drm:intel_dp_start_link_train], clock recovery OK
>[  227.163815] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  227.163821] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  227.179850] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  232.196873] [drm:drm_mode_addfb], [FB:84]
>[  232.196892] [drm:drm_mode_setcrtc], [CRTC:3]
>[  232.196895] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  232.196897] [drm:drm_crtc_helper_set_config], 
>[  232.196899] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:84] #connectors=1 (x y) (0 0)
>[  232.196903] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  232.196905] [drm:drm_mode_debug_printmodeline], Modeline 84:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  232.196908] [drm:drm_mode_debug_printmodeline], Modeline 85:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  232.196913] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  232.196915] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  232.196917] [drm:drm_mode_debug_printmodeline], Modeline 85:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  232.196920] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 83500KHz
>[  232.196923] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  232.196926] [drm:intel_dp_mode_fixup], DP link bw required 200400 available 216000
>[  232.196928] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  232.197139] [drm:intel_dp_link_down], 
>[  232.222611] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  232.267647] [drm:intel_wait_for_vblank], vblank wait timed out
>[  232.289626] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  232.289632] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  232.290044] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  232.290048] [drm:ironlake_check_srwm], watermark 1: display plane 8, fbc lines 3, cursor 6
>[  232.290052] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
>[  232.290056] [drm:ironlake_check_srwm], watermark 3: display plane 81, fbc lines 4, cursor 6
>[  232.290060] [drm:intel_update_fbc], 
>[  232.290360] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  232.290364] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  232.290368] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  232.290370] [drm:drm_mode_debug_printmodeline], Modeline 85:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  232.290376] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  232.290380] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  232.342564] [drm:intel_wait_for_vblank], vblank wait timed out
>[  232.345567] [drm:ironlake_update_plane], Writing base 086F4000 00000000 0 0 5120
>[  232.397505] [drm:intel_wait_for_vblank], vblank wait timed out
>[  232.397511] [drm:intel_update_fbc], 
>[  232.397514] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  232.397518] [drm:ironlake_check_srwm], watermark 1: display plane 8, fbc lines 3, cursor 6
>[  232.397523] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
>[  232.397527] [drm:ironlake_check_srwm], watermark 3: display plane 81, fbc lines 4, cursor 6
>[  232.397531] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:85:1280x800]
>[  232.397537] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  232.397541] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  232.397544] [drm:ironlake_write_eld], ELD on pipe A
>[  232.397548] [drm:ironlake_write_eld], Audio directed to unknown port
>[  232.397551] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  232.397565] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  232.397569] [drm:ironlake_check_srwm], watermark 1: display plane 8, fbc lines 3, cursor 6
>[  232.397573] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
>[  232.397577] [drm:ironlake_check_srwm], watermark 3: display plane 81, fbc lines 4, cursor 6
>[  232.449448] [drm:intel_wait_for_vblank], vblank wait timed out
>[  232.501392] [drm:intel_wait_for_vblank], vblank wait timed out
>[  232.502207] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  232.502212] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  232.502870] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  232.502874] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  232.502877] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  232.502879] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  232.502885] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  232.504108] [drm:intel_update_fbc], 
>[  232.504529] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  232.505259] [drm:intel_dp_start_link_train], clock recovery OK
>[  232.507005] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  232.507009] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  232.523079] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  237.539776] [drm:drm_mode_addfb], [FB:85]
>[  237.539795] [drm:drm_mode_setcrtc], [CRTC:3]
>[  237.539798] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  237.539800] [drm:drm_crtc_helper_set_config], 
>[  237.539801] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:85] #connectors=1 (x y) (0 0)
>[  237.539805] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  237.539807] [drm:drm_mode_debug_printmodeline], Modeline 85:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  237.539811] [drm:drm_mode_debug_printmodeline], Modeline 86:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  237.539815] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  237.539817] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  237.539819] [drm:drm_mode_debug_printmodeline], Modeline 86:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  237.539823] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 108000KHz
>[  237.539826] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  237.539828] [drm:intel_dp_mode_fixup], DP link bw required 259200 available 259200
>[  237.539830] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  237.540042] [drm:intel_dp_link_down], 
>[  237.566797] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  237.610837] [drm:intel_wait_for_vblank], vblank wait timed out
>[  237.634815] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  237.634822] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  237.635235] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
>[  237.635239] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
>[  237.635243] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
>[  237.635247] [drm:ironlake_check_srwm], watermark 3: display plane 104, fbc lines 4, cursor 10
>[  237.635251] [drm:intel_update_fbc], 
>[  237.635551] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  237.635555] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  237.635558] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  237.635561] [drm:drm_mode_debug_printmodeline], Modeline 86:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  237.635567] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  237.635570] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  237.687728] [drm:intel_wait_for_vblank], vblank wait timed out
>[  237.690237] [drm:ironlake_update_plane], Writing base 08ADC000 00000000 0 0 4608
>[  237.741698] [drm:intel_wait_for_vblank], vblank wait timed out
>[  237.741703] [drm:intel_update_fbc], 
>[  237.741706] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
>[  237.741711] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
>[  237.741715] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
>[  237.741719] [drm:ironlake_check_srwm], watermark 3: display plane 104, fbc lines 4, cursor 10
>[  237.741724] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:86:1152x864]
>[  237.741729] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  237.741733] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  237.741737] [drm:ironlake_write_eld], ELD on pipe A
>[  237.741741] [drm:ironlake_write_eld], Audio directed to unknown port
>[  237.741744] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  237.741757] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
>[  237.741761] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
>[  237.741765] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
>[  237.741769] [drm:ironlake_check_srwm], watermark 3: display plane 104, fbc lines 4, cursor 10
>[  237.793639] [drm:intel_wait_for_vblank], vblank wait timed out
>[  237.845583] [drm:intel_wait_for_vblank], vblank wait timed out
>[  237.846399] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  237.846404] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  237.847061] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  237.847065] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  237.847067] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  237.847070] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  237.847076] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  237.848299] [drm:intel_update_fbc], 
>[  237.848720] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  237.849449] [drm:intel_dp_start_link_train], clock recovery OK
>[  237.851194] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  237.851198] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  237.863909] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  242.884013] [drm:drm_mode_addfb], [FB:86]
>[  242.884031] [drm:drm_mode_setcrtc], [CRTC:3]
>[  242.884035] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  242.884037] [drm:drm_crtc_helper_set_config], 
>[  242.884038] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:86] #connectors=1 (x y) (0 0)
>[  242.884042] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  242.884044] [drm:drm_mode_debug_printmodeline], Modeline 86:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  242.884048] [drm:drm_mode_debug_printmodeline], Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  242.884052] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  242.884054] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  242.884056] [drm:drm_mode_debug_printmodeline], Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  242.884060] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz
>[  242.884069] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  242.884082] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 216000
>[  242.884084] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  242.884304] [drm:intel_dp_link_down], 
>[  242.911658] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  242.955029] [drm:intel_wait_for_vblank], vblank wait timed out
>[  242.979006] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  242.979013] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  242.979426] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  242.979430] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  242.979434] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  242.979438] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  242.979442] [drm:intel_update_fbc], 
>[  242.979742] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  242.979746] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  242.979749] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  242.979752] [drm:drm_mode_debug_printmodeline], Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  242.979758] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  242.979761] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  243.031919] [drm:intel_wait_for_vblank], vblank wait timed out
>[  243.034237] [drm:ironlake_update_plane], Writing base 08EA8000 00000000 0 0 5120
>[  243.085887] [drm:intel_wait_for_vblank], vblank wait timed out
>[  243.085892] [drm:intel_update_fbc], 
>[  243.085896] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  243.085900] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  243.085904] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  243.085908] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  243.085913] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:87:1280x720]
>[  243.085918] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  243.085922] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  243.085926] [drm:ironlake_write_eld], ELD on pipe A
>[  243.085929] [drm:ironlake_write_eld], Audio directed to unknown port
>[  243.085932] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  243.085945] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  243.085948] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  243.085952] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  243.085956] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  243.137830] [drm:intel_wait_for_vblank], vblank wait timed out
>[  243.189773] [drm:intel_wait_for_vblank], vblank wait timed out
>[  243.190589] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  243.190594] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  243.191251] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  243.191255] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  243.191258] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  243.191260] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  243.191266] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  243.192488] [drm:intel_update_fbc], 
>[  243.192909] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  243.193638] [drm:intel_dp_start_link_train], clock recovery OK
>[  243.195382] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  243.195386] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  243.214733] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  248.227992] [drm:drm_mode_addfb], [FB:87]
>[  248.228011] [drm:drm_mode_setcrtc], [CRTC:3]
>[  248.228015] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  248.228017] [drm:drm_crtc_helper_set_config], 
>[  248.228018] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:87] #connectors=1 (x y) (0 0)
>[  248.228022] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  248.228024] [drm:drm_mode_debug_printmodeline], Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  248.228028] [drm:drm_mode_debug_printmodeline], Modeline 88:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  248.228032] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  248.228034] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  248.228036] [drm:drm_mode_debug_printmodeline], Modeline 88:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  248.228040] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz
>[  248.228042] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  248.228045] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 216000
>[  248.228047] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  248.228262] [drm:intel_dp_link_down], 
>[  248.249168] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  248.299220] [drm:intel_wait_for_vblank], vblank wait timed out
>[  248.329191] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  248.329197] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  248.329610] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  248.329614] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  248.329618] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  248.329622] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  248.329626] [drm:intel_update_fbc], 
>[  248.329936] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  248.329940] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  248.329944] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  248.329947] [drm:drm_mode_debug_printmodeline], Modeline 88:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  248.329953] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  248.329956] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  248.382130] [drm:intel_wait_for_vblank], vblank wait timed out
>[  248.384762] [drm:ironlake_update_plane], Writing base 0922C000 00000000 0 0 5120
>[  248.436045] [drm:intel_wait_for_vblank], vblank wait timed out
>[  248.436050] [drm:intel_update_fbc], 
>[  248.436054] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  248.436058] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  248.436062] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  248.436066] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  248.436071] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:88:1280x720]
>[  248.436076] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  248.436080] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  248.436084] [drm:ironlake_write_eld], ELD on pipe A
>[  248.436088] [drm:ironlake_write_eld], Audio directed to unknown port
>[  248.436091] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  248.436104] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  248.436108] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  248.436112] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
>[  248.436116] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
>[  248.488014] [drm:intel_wait_for_vblank], vblank wait timed out
>[  248.539958] [drm:intel_wait_for_vblank], vblank wait timed out
>[  248.540774] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  248.540779] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  248.541436] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  248.541440] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  248.541443] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  248.541445] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  248.541451] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  248.542681] [drm:intel_update_fbc], 
>[  248.543102] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  248.543830] [drm:intel_dp_start_link_train], clock recovery OK
>[  248.545572] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  248.545576] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  248.561597] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  253.575217] [drm:drm_mode_addfb], [FB:88]
>[  253.575235] [drm:drm_mode_setcrtc], [CRTC:3]
>[  253.575239] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  253.575241] [drm:drm_crtc_helper_set_config], 
>[  253.575242] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:88] #connectors=1 (x y) (0 0)
>[  253.575246] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  253.575248] [drm:drm_mode_debug_printmodeline], Modeline 88:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  253.575252] [drm:drm_mode_debug_printmodeline], Modeline 89:"1440x576" 50 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x1a
>[  253.575256] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  253.575258] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  253.575260] [drm:drm_mode_debug_printmodeline], Modeline 89:"1440x576" 50 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x1a
>[  253.575264] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 27000KHz
>[  253.575266] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
>[  253.575269] [drm:intel_dp_mode_fixup], DP link bw required 64800 available 129600
>[  253.575271] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  253.575482] [drm:intel_dp_link_down], 
>[  253.606022] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  253.646407] [drm:intel_wait_for_vblank], vblank wait timed out
>[  253.674381] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  253.674387] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  253.674800] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 3, cursor: 6
>[  253.674804] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  253.674809] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
>[  253.674813] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
>[  253.674816] [drm:intel_update_fbc], 
>[  253.675116] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  253.675120] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  253.675124] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  253.675127] [drm:drm_mode_debug_printmodeline], Modeline 89:"1440x576" 50 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x1a
>[  253.675133] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  253.675136] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  253.727320] [drm:intel_wait_for_vblank], vblank wait timed out
>[  253.729457] [drm:ironlake_update_plane], Writing base 095B0000 00000000 0 0 5760
>[  253.781235] [drm:intel_wait_for_vblank], vblank wait timed out
>[  253.781240] [drm:intel_update_fbc], 
>[  253.781244] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 3, cursor: 6
>[  253.781248] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  253.781252] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
>[  253.781256] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
>[  253.781261] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:89:1440x576]
>[  253.781266] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  253.781270] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  253.781274] [drm:ironlake_write_eld], ELD on pipe A
>[  253.781278] [drm:ironlake_write_eld], Audio directed to unknown port
>[  253.781281] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  253.781295] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 3, cursor: 6
>[  253.781298] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  253.781302] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
>[  253.781306] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
>[  253.833204] [drm:intel_wait_for_vblank], vblank wait timed out
>[  253.885148] [drm:intel_wait_for_vblank], vblank wait timed out
>[  253.885963] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  253.885968] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  253.886625] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  253.886630] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  253.886632] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  253.886635] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  253.886640] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  253.887871] [drm:intel_update_fbc], 
>[  253.888292] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  253.889021] [drm:intel_dp_start_link_train], clock recovery OK
>[  253.890760] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  253.890763] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  253.910166] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  258.920207] [drm:drm_mode_addfb], [FB:89]
>[  258.920226] [drm:drm_mode_setcrtc], [CRTC:3]
>[  258.920229] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  258.920231] [drm:drm_crtc_helper_set_config], 
>[  258.920232] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:89] #connectors=1 (x y) (0 0)
>[  258.920237] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  258.920239] [drm:drm_mode_debug_printmodeline], Modeline 89:"1440x576" 50 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x1a
>[  258.920242] [drm:drm_mode_debug_printmodeline], Modeline 90:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  258.920246] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  258.920249] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  258.920250] [drm:drm_mode_debug_printmodeline], Modeline 90:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  258.920254] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 78800KHz
>[  258.920257] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  258.920259] [drm:intel_dp_mode_fixup], DP link bw required 189120 available 216000
>[  258.920262] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  258.920473] [drm:intel_dp_link_down], 
>[  258.944591] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  258.990598] [drm:intel_wait_for_vblank], vblank wait timed out
>[  259.024539] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  259.024545] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  259.024958] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  259.024962] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  259.024966] [drm:ironlake_check_srwm], watermark 2: display plane 37, fbc lines 3, cursor 6
>[  259.024970] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 4, cursor 6
>[  259.024974] [drm:intel_update_fbc], 
>[  259.025274] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  259.025278] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  259.025281] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  259.025284] [drm:drm_mode_debug_printmodeline], Modeline 90:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  259.025290] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  259.025293] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  259.077504] [drm:intel_wait_for_vblank], vblank wait timed out
>[  259.079861] [drm:ironlake_update_plane], Writing base 098DA000 00000000 0 0 4096
>[  259.131446] [drm:intel_wait_for_vblank], vblank wait timed out
>[  259.131451] [drm:intel_update_fbc], 
>[  259.131454] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  259.131459] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  259.131463] [drm:ironlake_check_srwm], watermark 2: display plane 37, fbc lines 3, cursor 6
>[  259.131467] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 4, cursor 6
>[  259.131472] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:90:1024x768]
>[  259.131477] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  259.131481] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  259.131485] [drm:ironlake_write_eld], ELD on pipe A
>[  259.131489] [drm:ironlake_write_eld], Audio directed to unknown port
>[  259.131491] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  259.131505] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  259.131509] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  259.131513] [drm:ironlake_check_srwm], watermark 2: display plane 37, fbc lines 3, cursor 6
>[  259.131517] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 4, cursor 6
>[  259.183389] [drm:intel_wait_for_vblank], vblank wait timed out
>[  259.235306] [drm:intel_wait_for_vblank], vblank wait timed out
>[  259.236122] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  259.236127] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  259.236784] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  259.236789] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  259.236791] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  259.236794] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  259.236799] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  259.238030] [drm:intel_update_fbc], 
>[  259.238450] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  259.239179] [drm:intel_dp_start_link_train], clock recovery OK
>[  259.240918] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  259.240922] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  259.253603] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  264.271811] [drm:drm_mode_addfb], [FB:90]
>[  264.271846] [drm:drm_mode_setcrtc], [CRTC:3]
>[  264.271850] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  264.271852] [drm:drm_crtc_helper_set_config], 
>[  264.271856] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:90] #connectors=1 (x y) (0 0)
>[  264.271862] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  264.271865] [drm:drm_mode_debug_printmodeline], Modeline 90:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  264.271872] [drm:drm_mode_debug_printmodeline], Modeline 91:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  264.271879] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  264.271883] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  264.271887] [drm:drm_mode_debug_printmodeline], Modeline 91:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  264.271893] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 65000KHz
>[  264.271898] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  264.271903] [drm:intel_dp_mode_fixup], DP link bw required 156000 available 216000
>[  264.271907] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  264.272120] [drm:intel_dp_link_down], 
>[  264.296232] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  264.342782] [drm:intel_wait_for_vblank], vblank wait timed out
>[  264.362763] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  264.362769] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  264.363182] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  264.363186] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  264.363190] [drm:ironlake_check_srwm], watermark 2: display plane 31, fbc lines 3, cursor 6
>[  264.363194] [drm:ironlake_check_srwm], watermark 3: display plane 63, fbc lines 3, cursor 6
>[  264.363198] [drm:intel_update_fbc], 
>[  264.363498] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  264.363501] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  264.363505] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  264.363508] [drm:drm_mode_debug_printmodeline], Modeline 91:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  264.363514] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  264.363517] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  264.415701] [drm:intel_wait_for_vblank], vblank wait timed out
>[  264.417966] [drm:ironlake_update_plane], Writing base 09BDA000 00000000 0 0 4096
>[  264.469617] [drm:intel_wait_for_vblank], vblank wait timed out
>[  264.469622] [drm:intel_update_fbc], 
>[  264.469625] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  264.469630] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  264.469634] [drm:ironlake_check_srwm], watermark 2: display plane 31, fbc lines 3, cursor 6
>[  264.469638] [drm:ironlake_check_srwm], watermark 3: display plane 63, fbc lines 3, cursor 6
>[  264.469643] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:91:1024x768]
>[  264.469648] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  264.469652] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  264.469656] [drm:ironlake_write_eld], ELD on pipe A
>[  264.469659] [drm:ironlake_write_eld], Audio directed to unknown port
>[  264.469662] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  264.469676] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  264.469680] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  264.469684] [drm:ironlake_check_srwm], watermark 2: display plane 31, fbc lines 3, cursor 6
>[  264.469687] [drm:ironlake_check_srwm], watermark 3: display plane 63, fbc lines 3, cursor 6
>[  264.521586] [drm:intel_wait_for_vblank], vblank wait timed out
>[  264.573530] [drm:intel_wait_for_vblank], vblank wait timed out
>[  264.574346] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  264.574351] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  264.575008] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  264.575013] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  264.575015] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  264.575018] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  264.575023] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  264.576253] [drm:intel_update_fbc], 
>[  264.576674] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  264.577403] [drm:intel_dp_start_link_train], clock recovery OK
>[  264.579142] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  264.579145] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  264.595169] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  269.607882] [drm:drm_mode_addfb], [FB:91]
>[  269.607901] [drm:drm_mode_setcrtc], [CRTC:3]
>[  269.607904] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  269.607906] [drm:drm_crtc_helper_set_config], 
>[  269.607908] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:91] #connectors=1 (x y) (0 0)
>[  269.607912] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  269.607914] [drm:drm_mode_debug_printmodeline], Modeline 91:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  269.607917] [drm:drm_mode_debug_printmodeline], Modeline 92:"1440x480" 60 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x1a
>[  269.607921] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  269.607924] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  269.607925] [drm:drm_mode_debug_printmodeline], Modeline 92:"1440x480" 60 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x1a
>[  269.607929] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 27000KHz
>[  269.607932] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
>[  269.607935] [drm:intel_dp_mode_fixup], DP link bw required 64800 available 129600
>[  269.607937] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  269.608148] [drm:intel_dp_link_down], 
>[  269.639258] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  269.678981] [drm:intel_wait_for_vblank], vblank wait timed out
>[  269.706954] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  269.706960] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  269.707373] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 3, cursor: 6
>[  269.707377] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  269.707381] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
>[  269.707385] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
>[  269.707389] [drm:intel_update_fbc], 
>[  269.707689] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  269.707693] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  269.707697] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  269.707699] [drm:drm_mode_debug_printmodeline], Modeline 92:"1440x480" 60 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x1a
>[  269.707705] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  269.707708] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  269.759893] [drm:intel_wait_for_vblank], vblank wait timed out
>[  269.761686] [drm:ironlake_update_plane], Writing base 09EDA000 00000000 0 0 5760
>[  269.812809] [drm:intel_wait_for_vblank], vblank wait timed out
>[  269.812814] [drm:intel_update_fbc], 
>[  269.812818] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 3, cursor: 6
>[  269.812822] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  269.812826] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
>[  269.812830] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
>[  269.812835] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:92:1440x480]
>[  269.812840] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  269.812844] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  269.812847] [drm:ironlake_write_eld], ELD on pipe A
>[  269.812851] [drm:ironlake_write_eld], Audio directed to unknown port
>[  269.812854] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  269.812868] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 3, cursor: 6
>[  269.812872] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  269.812876] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
>[  269.812880] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
>[  269.864778] [drm:intel_wait_for_vblank], vblank wait timed out
>[  269.916722] [drm:intel_wait_for_vblank], vblank wait timed out
>[  269.917538] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  269.917543] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  269.918200] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  269.918205] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  269.918207] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  269.918210] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  269.918215] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  269.919445] [drm:intel_update_fbc], 
>[  269.919865] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  269.920595] [drm:intel_dp_start_link_train], clock recovery OK
>[  269.922334] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  269.922338] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  269.938428] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  274.951240] [drm:drm_mode_addfb], [FB:92]
>[  274.951259] [drm:drm_mode_setcrtc], [CRTC:3]
>[  274.951262] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  274.951264] [drm:drm_crtc_helper_set_config], 
>[  274.951266] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:92] #connectors=1 (x y) (0 0)
>[  274.951270] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  274.951272] [drm:drm_mode_debug_printmodeline], Modeline 92:"1440x480" 60 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x1a
>[  274.951276] [drm:drm_mode_debug_printmodeline], Modeline 93:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  274.951280] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  274.951282] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  274.951284] [drm:drm_mode_debug_printmodeline], Modeline 93:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  274.951287] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 49500KHz
>[  274.951290] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
>[  274.951293] [drm:intel_dp_mode_fixup], DP link bw required 118800 available 129600
>[  274.951295] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  274.951506] [drm:intel_dp_link_down], 
>[  274.971231] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  275.022173] [drm:intel_wait_for_vblank], vblank wait timed out
>[  275.056140] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  275.056146] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  275.056558] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
>[  275.056562] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[  275.056567] [drm:ironlake_check_srwm], watermark 2: display plane 24, fbc lines 3, cursor 6
>[  275.056570] [drm:ironlake_check_srwm], watermark 3: display plane 49, fbc lines 3, cursor 6
>[  275.056574] [drm:intel_update_fbc], 
>[  275.056884] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  275.056888] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  275.056892] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  275.056895] [drm:drm_mode_debug_printmodeline], Modeline 93:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  275.056900] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  275.056904] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  275.109079] [drm:intel_wait_for_vblank], vblank wait timed out
>[  275.110303] [drm:ironlake_update_plane], Writing base 0A17D000 00000000 0 0 3200
>[  275.162021] [drm:intel_wait_for_vblank], vblank wait timed out
>[  275.162026] [drm:intel_update_fbc], 
>[  275.162029] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
>[  275.162034] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[  275.162038] [drm:ironlake_check_srwm], watermark 2: display plane 24, fbc lines 3, cursor 6
>[  275.162042] [drm:ironlake_check_srwm], watermark 3: display plane 49, fbc lines 3, cursor 6
>[  275.162047] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:93:800x600]
>[  275.162052] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  275.162056] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  275.162059] [drm:ironlake_write_eld], ELD on pipe A
>[  275.162063] [drm:ironlake_write_eld], Audio directed to unknown port
>[  275.162066] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  275.162080] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
>[  275.162084] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[  275.162088] [drm:ironlake_check_srwm], watermark 2: display plane 24, fbc lines 3, cursor 6
>[  275.162092] [drm:ironlake_check_srwm], watermark 3: display plane 49, fbc lines 3, cursor 6
>[  275.213964] [drm:intel_wait_for_vblank], vblank wait timed out
>[  275.265885] [drm:intel_wait_for_vblank], vblank wait timed out
>[  275.266700] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  275.266705] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  275.267363] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  275.267367] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  275.267370] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  275.267372] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  275.267378] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  275.268601] [drm:intel_update_fbc], 
>[  275.269021] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  275.269750] [drm:intel_dp_start_link_train], clock recovery OK
>[  275.271499] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  275.271503] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  275.284210] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  280.302107] [drm:drm_mode_addfb], [FB:93]
>[  280.302126] [drm:drm_mode_setcrtc], [CRTC:3]
>[  280.302129] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  280.302131] [drm:drm_crtc_helper_set_config], 
>[  280.302133] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:93] #connectors=1 (x y) (0 0)
>[  280.302137] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  280.302139] [drm:drm_mode_debug_printmodeline], Modeline 93:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  280.302143] [drm:drm_mode_debug_printmodeline], Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  280.302147] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  280.302149] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  280.302151] [drm:drm_mode_debug_printmodeline], Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  280.302155] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 40000KHz
>[  280.302158] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
>[  280.302160] [drm:intel_dp_mode_fixup], DP link bw required 96000 available 129600
>[  280.302162] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  280.302373] [drm:intel_dp_link_down], 
>[  280.331962] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  280.372331] [drm:intel_wait_for_vblank], vblank wait timed out
>[  280.400331] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  280.400337] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  280.400750] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
>[  280.400754] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
>[  280.400758] [drm:ironlake_check_srwm], watermark 2: display plane 20, fbc lines 3, cursor 6
>[  280.400762] [drm:ironlake_check_srwm], watermark 3: display plane 40, fbc lines 3, cursor 6
>[  280.400766] [drm:intel_update_fbc], 
>[  280.401066] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  280.401070] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  280.401074] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  280.401076] [drm:drm_mode_debug_printmodeline], Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  280.401082] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  280.401085] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  280.453269] [drm:intel_wait_for_vblank], vblank wait timed out
>[  280.454478] [drm:ironlake_update_plane], Writing base 0A352000 00000000 0 0 3200
>[  280.506212] [drm:intel_wait_for_vblank], vblank wait timed out
>[  280.506217] [drm:intel_update_fbc], 
>[  280.506220] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
>[  280.506225] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
>[  280.506229] [drm:ironlake_check_srwm], watermark 2: display plane 20, fbc lines 3, cursor 6
>[  280.506233] [drm:ironlake_check_srwm], watermark 3: display plane 40, fbc lines 3, cursor 6
>[  280.506238] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:94:800x600]
>[  280.506243] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  280.506247] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  280.506251] [drm:ironlake_write_eld], ELD on pipe A
>[  280.506255] [drm:ironlake_write_eld], Audio directed to unknown port
>[  280.506257] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  280.506271] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
>[  280.506275] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
>[  280.506279] [drm:ironlake_check_srwm], watermark 2: display plane 20, fbc lines 3, cursor 6
>[  280.506283] [drm:ironlake_check_srwm], watermark 3: display plane 40, fbc lines 3, cursor 6
>[  280.558155] [drm:intel_wait_for_vblank], vblank wait timed out
>[  280.610099] [drm:intel_wait_for_vblank], vblank wait timed out
>[  280.610915] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  280.610920] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  280.611577] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  280.611582] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  280.611584] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  280.611587] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  280.611592] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  280.612816] [drm:intel_update_fbc], 
>[  280.613235] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  280.613965] [drm:intel_dp_start_link_train], clock recovery OK
>[  280.615709] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  280.615713] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  280.631663] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  285.645740] [drm:drm_mode_addfb], [FB:94]
>[  285.645759] [drm:drm_mode_setcrtc], [CRTC:3]
>[  285.645762] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  285.645764] [drm:drm_crtc_helper_set_config], 
>[  285.645766] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:94] #connectors=1 (x y) (0 0)
>[  285.645770] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  285.645772] [drm:drm_mode_debug_printmodeline], Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  285.645776] [drm:drm_mode_debug_printmodeline], Modeline 95:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  285.645779] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  285.645782] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  285.645783] [drm:drm_mode_debug_printmodeline], Modeline 95:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  285.645787] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 27000KHz
>[  285.645790] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
>[  285.645793] [drm:intel_dp_mode_fixup], DP link bw required 64800 available 129600
>[  285.645795] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  285.646007] [drm:intel_dp_link_down], 
>[  285.666173] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  285.716525] [drm:intel_wait_for_vblank], vblank wait timed out
>[  285.750515] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  285.750521] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  285.750934] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
>[  285.750938] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  285.750942] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
>[  285.750946] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
>[  285.750950] [drm:intel_update_fbc], 
>[  285.751260] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  285.751264] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  285.751268] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  285.751270] [drm:drm_mode_debug_printmodeline], Modeline 95:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  285.751276] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  285.751279] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  285.803454] [drm:intel_wait_for_vblank], vblank wait timed out
>[  285.804523] [drm:ironlake_update_plane], Writing base 0A527000 00000000 0 0 2880
>[  285.856372] [drm:intel_wait_for_vblank], vblank wait timed out
>[  285.856377] [drm:intel_update_fbc], 
>[  285.856381] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
>[  285.856385] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  285.856389] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
>[  285.856393] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
>[  285.856398] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:95:720x576]
>[  285.856403] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  285.856407] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  285.856411] [drm:ironlake_write_eld], ELD on pipe A
>[  285.856415] [drm:ironlake_write_eld], Audio directed to unknown port
>[  285.856418] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  285.856432] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
>[  285.856435] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  285.856439] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
>[  285.856443] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
>[  285.908339] [drm:intel_wait_for_vblank], vblank wait timed out
>[  285.960284] [drm:intel_wait_for_vblank], vblank wait timed out
>[  285.961100] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  285.961105] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  285.961762] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  285.961767] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  285.961769] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  285.961772] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  285.961777] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  285.963008] [drm:intel_update_fbc], 
>[  285.963429] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  285.964158] [drm:intel_dp_start_link_train], clock recovery OK
>[  285.965897] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  285.965900] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  285.985271] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  290.993548] [drm:drm_mode_addfb], [FB:95]
>[  290.993566] [drm:drm_mode_setcrtc], [CRTC:3]
>[  290.993570] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  290.993572] [drm:drm_crtc_helper_set_config], 
>[  290.993573] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:95] #connectors=1 (x y) (0 0)
>[  290.993577] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  290.993579] [drm:drm_mode_debug_printmodeline], Modeline 95:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  290.993583] [drm:drm_mode_debug_printmodeline], Modeline 96:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  290.993587] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  290.993589] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  290.993591] [drm:drm_mode_debug_printmodeline], Modeline 96:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  290.993594] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 27000KHz
>[  290.993597] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
>[  290.993599] [drm:intel_dp_mode_fixup], DP link bw required 64800 available 129600
>[  290.993602] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  290.993812] [drm:intel_dp_link_down], 
>[  291.019704] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  291.064734] [drm:intel_wait_for_vblank], vblank wait timed out
>[  291.100674] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  291.100680] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  291.101093] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
>[  291.101097] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  291.101101] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
>[  291.101105] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
>[  291.101109] [drm:intel_update_fbc], 
>[  291.101409] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  291.101413] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  291.101417] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  291.101419] [drm:drm_mode_debug_printmodeline], Modeline 96:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  291.101425] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  291.101428] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  291.153639] [drm:intel_wait_for_vblank], vblank wait timed out
>[  291.154504] [drm:ironlake_update_plane], Writing base 0A6BC000 00000000 0 0 2880
>[  291.205582] [drm:intel_wait_for_vblank], vblank wait timed out
>[  291.205587] [drm:intel_update_fbc], 
>[  291.205590] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
>[  291.205595] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  291.205599] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
>[  291.205603] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
>[  291.205608] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:96:720x480]
>[  291.205613] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  291.205617] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  291.205621] [drm:ironlake_write_eld], ELD on pipe A
>[  291.205624] [drm:ironlake_write_eld], Audio directed to unknown port
>[  291.205627] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  291.205641] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
>[  291.205645] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  291.205649] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
>[  291.205653] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
>[  291.257525] [drm:intel_wait_for_vblank], vblank wait timed out
>[  291.309446] [drm:intel_wait_for_vblank], vblank wait timed out
>[  291.310262] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  291.310267] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  291.310925] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  291.310929] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  291.310931] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  291.310934] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  291.310940] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  291.312170] [drm:intel_update_fbc], 
>[  291.312591] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  291.313320] [drm:intel_dp_start_link_train], clock recovery OK
>[  291.315060] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  291.315063] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  291.331112] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  296.338878] [drm:drm_mode_addfb], [FB:96]
>[  296.338899] [drm:drm_mode_setcrtc], [CRTC:3]
>[  296.338903] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  296.338906] [drm:drm_crtc_helper_set_config], 
>[  296.338908] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:96] #connectors=1 (x y) (0 0)
>[  296.338914] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  296.338917] [drm:drm_mode_debug_printmodeline], Modeline 96:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  296.338922] [drm:drm_mode_debug_printmodeline], Modeline 97:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  296.338928] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  296.338931] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  296.338933] [drm:drm_mode_debug_printmodeline], Modeline 97:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  296.338939] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 31500KHz
>[  296.338943] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
>[  296.338946] [drm:intel_dp_mode_fixup], DP link bw required 75600 available 129600
>[  296.338948] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  296.339164] [drm:intel_dp_link_down], 
>[  296.363919] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  296.409925] [drm:intel_wait_for_vblank], vblank wait timed out
>[  296.431905] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  296.431911] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  296.432324] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
>[  296.432328] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  296.432332] [drm:ironlake_check_srwm], watermark 2: display plane 16, fbc lines 3, cursor 6
>[  296.432336] [drm:ironlake_check_srwm], watermark 3: display plane 32, fbc lines 3, cursor 6
>[  296.432340] [drm:intel_update_fbc], 
>[  296.432650] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  296.432654] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  296.432658] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  296.432660] [drm:drm_mode_debug_printmodeline], Modeline 97:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  296.432666] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  296.432670] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  296.484820] [drm:intel_wait_for_vblank], vblank wait timed out
>[  296.485591] [drm:ironlake_update_plane], Writing base 0A80E000 00000000 0 0 2560
>[  296.536787] [drm:intel_wait_for_vblank], vblank wait timed out
>[  296.536792] [drm:intel_update_fbc], 
>[  296.536795] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
>[  296.536800] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  296.536804] [drm:ironlake_check_srwm], watermark 2: display plane 16, fbc lines 3, cursor 6
>[  296.536808] [drm:ironlake_check_srwm], watermark 3: display plane 32, fbc lines 3, cursor 6
>[  296.536813] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:97:640x480]
>[  296.536818] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  296.536822] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  296.536825] [drm:ironlake_write_eld], ELD on pipe A
>[  296.536829] [drm:ironlake_write_eld], Audio directed to unknown port
>[  296.536832] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  296.536846] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
>[  296.536850] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  296.536854] [drm:ironlake_check_srwm], watermark 2: display plane 16, fbc lines 3, cursor 6
>[  296.536858] [drm:ironlake_check_srwm], watermark 3: display plane 32, fbc lines 3, cursor 6
>[  296.588730] [drm:intel_wait_for_vblank], vblank wait timed out
>[  296.640674] [drm:intel_wait_for_vblank], vblank wait timed out
>[  296.641490] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  296.641495] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  296.642152] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  296.642157] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  296.642159] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  296.642162] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  296.642167] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  296.643391] [drm:intel_update_fbc], 
>[  296.643811] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  296.644541] [drm:intel_dp_start_link_train], clock recovery OK
>[  296.646286] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  296.646289] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  296.658995] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  301.670967] [drm:drm_mode_addfb], [FB:97]
>[  301.670985] [drm:drm_mode_setcrtc], [CRTC:3]
>[  301.670988] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  301.670991] [drm:drm_crtc_helper_set_config], 
>[  301.670992] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:97] #connectors=1 (x y) (0 0)
>[  301.670996] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  301.670998] [drm:drm_mode_debug_printmodeline], Modeline 97:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  301.671002] [drm:drm_mode_debug_printmodeline], Modeline 98:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  301.671005] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  301.671008] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  301.671009] [drm:drm_mode_debug_printmodeline], Modeline 98:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  301.671013] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 25200KHz
>[  301.671016] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
>[  301.671018] [drm:intel_dp_mode_fixup], DP link bw required 60480 available 129600
>[  301.671020] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  301.671231] [drm:intel_dp_link_down], 
>[  301.693430] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  301.742129] [drm:intel_wait_for_vblank], vblank wait timed out
>[  301.760112] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  301.760119] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  301.760532] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
>[  301.760536] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  301.760540] [drm:ironlake_check_srwm], watermark 2: display plane 13, fbc lines 3, cursor 6
>[  301.760544] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6
>[  301.760547] [drm:intel_update_fbc], 
>[  301.760847] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  301.760851] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  301.760855] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  301.760857] [drm:drm_mode_debug_printmodeline], Modeline 98:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  301.760863] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  301.760866] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  301.813052] [drm:intel_wait_for_vblank], vblank wait timed out
>[  301.813821] [drm:ironlake_update_plane], Writing base 0A93A000 00000000 0 0 2560
>[  301.864971] [drm:intel_wait_for_vblank], vblank wait timed out
>[  301.864976] [drm:intel_update_fbc], 
>[  301.864979] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
>[  301.864983] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  301.864987] [drm:ironlake_check_srwm], watermark 2: display plane 13, fbc lines 3, cursor 6
>[  301.864992] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6
>[  301.864996] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:98:640x480]
>[  301.865002] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  301.865005] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  301.865009] [drm:ironlake_write_eld], ELD on pipe A
>[  301.865013] [drm:ironlake_write_eld], Audio directed to unknown port
>[  301.865016] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  301.865030] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
>[  301.865034] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  301.865038] [drm:ironlake_check_srwm], watermark 2: display plane 13, fbc lines 3, cursor 6
>[  301.865042] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6
>[  301.916939] [drm:intel_wait_for_vblank], vblank wait timed out
>[  301.968856] [drm:intel_wait_for_vblank], vblank wait timed out
>[  301.969672] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  301.969677] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  301.970334] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  301.970339] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  301.970341] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  301.970344] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  301.970349] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  301.971580] [drm:intel_update_fbc], 
>[  301.972001] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  301.972731] [drm:intel_dp_start_link_train], clock recovery OK
>[  301.974469] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  301.974472] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  301.990514] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  306.997901] [drm:drm_mode_addfb], [FB:98]
>[  306.997922] [drm:drm_mode_setcrtc], [CRTC:3]
>[  306.997927] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  306.997930] [drm:drm_crtc_helper_set_config], 
>[  306.997932] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:98] #connectors=1 (x y) (0 0)
>[  306.997938] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  306.997941] [drm:drm_mode_debug_printmodeline], Modeline 98:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  306.997946] [drm:drm_mode_debug_printmodeline], Modeline 99:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  306.997952] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  306.997955] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  306.997957] [drm:drm_mode_debug_printmodeline], Modeline 99:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  306.997963] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 25175KHz
>[  306.997967] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
>[  306.997970] [drm:intel_dp_mode_fixup], DP link bw required 60420 available 129600
>[  306.997972] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  306.998183] [drm:intel_dp_link_down], 
>[  307.018289] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  307.068339] [drm:intel_wait_for_vblank], vblank wait timed out
>[  307.102280] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  307.102286] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  307.102699] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
>[  307.102703] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  307.102707] [drm:ironlake_check_srwm], watermark 2: display plane 13, fbc lines 3, cursor 6
>[  307.102711] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6
>[  307.102715] [drm:intel_update_fbc], 
>[  307.103025] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  307.103029] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  307.103032] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  307.103035] [drm:drm_mode_debug_printmodeline], Modeline 99:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  307.103041] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  307.103044] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  307.155244] [drm:intel_wait_for_vblank], vblank wait timed out
>[  307.156008] [drm:ironlake_update_plane], Writing base 0AA66000 00000000 0 0 2560
>[  307.207189] [drm:intel_wait_for_vblank], vblank wait timed out
>[  307.207194] [drm:intel_update_fbc], 
>[  307.207197] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
>[  307.207202] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  307.207206] [drm:ironlake_check_srwm], watermark 2: display plane 13, fbc lines 3, cursor 6
>[  307.207210] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6
>[  307.207215] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:99:640x480]
>[  307.207220] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  307.207224] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  307.207228] [drm:ironlake_write_eld], ELD on pipe A
>[  307.207231] [drm:ironlake_write_eld], Audio directed to unknown port
>[  307.207234] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  307.207247] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
>[  307.207251] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  307.207255] [drm:ironlake_check_srwm], watermark 2: display plane 13, fbc lines 3, cursor 6
>[  307.207259] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6
>[  307.259133] [drm:intel_wait_for_vblank], vblank wait timed out
>[  307.311076] [drm:intel_wait_for_vblank], vblank wait timed out
>[  307.311892] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  307.311897] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  307.312554] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  307.312559] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  307.312561] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  307.312564] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  307.312569] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  307.313792] [drm:intel_update_fbc], 
>[  307.314213] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  307.314942] [drm:intel_dp_start_link_train], clock recovery OK
>[  307.316689] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  307.316694] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  307.332742] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  312.338519] [drm:drm_mode_addfb], [FB:99]
>[  312.338538] [drm:drm_mode_setcrtc], [CRTC:3]
>[  312.338541] [drm:drm_mode_setcrtc], [CONNECTOR:17:DP-1]
>[  312.338543] [drm:drm_crtc_helper_set_config], 
>[  312.338545] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:99] #connectors=1 (x y) (0 0)
>[  312.338549] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  312.338551] [drm:drm_mode_debug_printmodeline], Modeline 99:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  312.338555] [drm:drm_mode_debug_printmodeline], Modeline 100:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  312.338558] [drm:drm_crtc_helper_set_config], [CONNECTOR:17:DP-1] to [CRTC:3]
>[  312.338561] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  312.338562] [drm:drm_mode_debug_printmodeline], Modeline 100:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  312.338583] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 28320KHz
>[  312.338587] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
>[  312.338590] [drm:intel_dp_mode_fixup], DP link bw required 67968 available 129600
>[  312.338593] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  312.338806] [drm:intel_dp_link_down], 
>[  312.365509] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  312.409534] [drm:intel_wait_for_vblank], vblank wait timed out
>[  312.433511] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  312.433517] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  312.433929] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
>[  312.433933] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  312.433937] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6
>[  312.433941] [drm:ironlake_check_srwm], watermark 3: display plane 29, fbc lines 3, cursor 6
>[  312.433945] [drm:intel_update_fbc], 
>[  312.434255] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  312.434259] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  312.434263] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  312.434265] [drm:drm_mode_debug_printmodeline], Modeline 100:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  312.434271] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  312.434274] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  312.486424] [drm:intel_wait_for_vblank], vblank wait timed out
>[  312.487287] [drm:ironlake_update_plane], Writing base 0AB92000 00000000 0 0 2880
>[  312.538393] [drm:intel_wait_for_vblank], vblank wait timed out
>[  312.538398] [drm:intel_update_fbc], 
>[  312.538402] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
>[  312.538406] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  312.538411] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6
>[  312.538415] [drm:ironlake_check_srwm], watermark 3: display plane 29, fbc lines 3, cursor 6
>[  312.538419] [drm:drm_crtc_helper_set_mode], [ENCODER:18:TMDS-18] set [MODE:100:720x400]
>[  312.538425] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  312.538428] [drm:intel_write_eld], ELD on [CONNECTOR:17:DP-1], [ENCODER:18:TMDS-18]
>[  312.538432] [drm:ironlake_write_eld], ELD on pipe A
>[  312.538436] [drm:ironlake_write_eld], Audio directed to unknown port
>[  312.538439] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  312.538453] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
>[  312.538457] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
>[  312.538460] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6
>[  312.538464] [drm:ironlake_check_srwm], watermark 3: display plane 29, fbc lines 3, cursor 6
>[  312.590337] [drm:intel_wait_for_vblank], vblank wait timed out
>[  312.642281] [drm:intel_wait_for_vblank], vblank wait timed out
>[  312.643096] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  312.643101] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  312.643758] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  312.643763] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  312.643765] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  312.643768] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  312.643773] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  312.645002] [drm:intel_update_fbc], 
>[  312.645423] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  312.646153] [drm:intel_dp_start_link_train], clock recovery OK
>[  312.647890] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  312.647894] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:17:DP-1] set DPMS on
>[  312.661541] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  317.642784] [drm:drm_crtc_helper_set_config], 
>[  317.642789] [drm:drm_crtc_helper_set_config], [CRTC:3] [NOFB]
>[  317.643040] [drm:intel_dp_link_down], 
>[  317.661835] [drm:ironlake_crtc_dpms], crtc 0/0 dpms off
>[  317.661841] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
>[  317.664452] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  317.713768] [drm:intel_wait_for_vblank], vblank wait timed out
>[  317.735748] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  317.735754] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  317.736166] [drm:intel_update_fbc], 
>[  317.736472] [drm:drm_mode_setcrtc], [CRTC:3]
>[  317.736474] [drm:drm_mode_setcrtc], Count connectors is 1 but no mode or fb set
>[  317.736481] [drm:drm_mode_getconnector], [CONNECTOR:19:?]
>[  317.736485] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:DP-2]
>[  317.739039] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
>[  317.743261] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
>[  317.747257] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
>[  317.748702] [drm:intel_dp_detect], DPCD: 0000000000000000
>[  317.748709] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:DP-2] disconnected
>[  317.748719] [drm:drm_mode_getconnector], [CONNECTOR:19:?]
>[  317.748723] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:DP-2]
>[  317.751278] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
>[  317.755275] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
>[  317.759243] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
>[  317.760689] [drm:intel_dp_detect], DPCD: 0000000000000000
>[  317.760696] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:DP-2] disconnected
>[  317.781787] [drm:drm_crtc_helper_set_config], 
>[  317.781789] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  317.781794] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[  317.781796] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[  317.781798] [drm:drm_mode_debug_printmodeline], Modeline 100:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  317.781801] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  317.781805] [drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[  317.781807] [drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[  317.781809] [drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  317.781811] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[  317.781813] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  317.781818] [drm:drm_crtc_helper_set_mode], [CRTC:3]
>[  317.782060] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  317.782062] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  317.782064] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  317.782067] [drm:intel_get_pch_pll], CRTC:3 allocated PCH PLL c6014
>[  317.782069] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  317.782071] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  317.833636] [drm:intel_wait_for_vblank], vblank wait timed out
>[  317.833643] [drm:ironlake_update_plane], Writing base 00064000 00000000 0 0 7680
>[  317.833648] [drm:intel_update_fbc], 
>[  317.833651] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  317.833655] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
>[  317.833659] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
>[  317.833664] [drm:ironlake_check_srwm], watermark 3: display plane 142, fbc lines 4, cursor 10
>[  317.833668] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:33:1920x1080]
>[  317.833674] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  317.833678] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
>[  317.833682] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
>[  317.833685] [drm:ironlake_check_srwm], watermark 3: display plane 142, fbc lines 4, cursor 10
>[  317.885584] [drm:intel_wait_for_vblank], vblank wait timed out
>[  317.937524] [drm:intel_wait_for_vblank], vblank wait timed out
>[  317.938340] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  317.938345] [drm:ivb_manual_fdi_link_train], FDI train 1 done.
>[  317.939002] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  317.939007] [drm:ivb_manual_fdi_link_train], FDI train 2 done.
>[  317.939009] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  317.939012] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  317.939017] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
>[  317.940246] [drm:intel_update_fbc], 
>[  317.940753] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[  317.940757] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:9:VGA-1] set DPMS on
>[  317.940982] [drm:drm_crtc_helper_set_config], 
>[  317.940985] [drm:drm_crtc_helper_set_config], [CRTC:5] [NOFB]
>[  317.941208] [drm:drm_crtc_helper_set_config], 
>[  317.941210] [drm:drm_crtc_helper_set_config], [CRTC:7] [NOFB]
>[  317.941435] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  317.941439] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
>[  317.941443] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
>[  317.941447] [drm:ironlake_check_srwm], watermark 3: display plane 142, fbc lines 4, cursor 10
>[  317.941452] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  317.941456] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
>[  317.941460] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
>[  317.941463] [drm:ironlake_check_srwm], watermark 3: display plane 142, fbc lines 4, cursor 10
>[  317.941468] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  317.941472] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
>[  317.941479] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
>[  317.941483] [drm:ironlake_check_srwm], watermark 3: display plane 142, fbc lines 4, cursor 10
>[  317.956944] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  327.758223] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0x83f40018, result 1
>[  327.758228] [drm:intel_crt_detect], CRT detected via hotplug
>[  327.758232] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 1 to 1
>[  327.759822] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  327.759828] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
>[  327.759833] [drm:output_poll_execute], [CONNECTOR:12:HDMI-A-1] status updated from 2 to 2
>[  327.761829] [drm:gmbus_xfer], GMBUS [i915 gmbus dpd] NAK for addr: 0050 r(1)
>[  327.761836] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpd
>[  327.761840] [drm:output_poll_execute], [CONNECTOR:16:HDMI-A-2] status updated from 2 to 2
>[  327.762156] [drm:intel_dp_detect], DPCD: 110a840101000100
>[  327.763198] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  327.790520] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  327.817837] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  327.817841] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  327.817844] [drm:output_poll_execute], [CONNECTOR:17:DP-1] status updated from 1 to 1
>[  327.820401] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
>[  327.824297] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
>[  327.828291] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
>[  327.829743] [drm:intel_dp_detect], DPCD: 0000000000000000
>[  327.829750] [drm:output_poll_execute], [CONNECTOR:19:DP-2] status updated from 2 to 2

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Attachments on bug 42194: 52730 | 60342 | 60549 | 68754

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