Attachment 60664 Details for Bug 44006 – Always reset interrupts along with setting freqeuncy

[patch] Always reset interrupts along with setting freqeuncy

0001-rps.patch (text/plain), 5.51 KB, created by Chris Wilson on 2012-04-27 05:55:53 UTC

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Creator: Chris Wilson

Created: 2012-04-27 05:55:53 UTC

Size: 5.51 KB

patch

obsolete

>From 627c56542a75a8fc28c957d006fec7a14ca08967 Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Fri, 27 Apr 2012 13:39:55 +0100
>Subject: [PATCH 1/2] rps
>
>---
> drivers/gpu/drm/i915/i915_irq.c |   35 +++++---------------------
> drivers/gpu/drm/i915/intel_pm.c |   53 ++++++++++++++++++++++++++++-----------
> 2 files changed, 44 insertions(+), 44 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index c2511fe..eae30e8 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -353,8 +353,8 @@ static void gen6_pm_rps_work(struct work_struct *work)
> {
> 	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
> 						    rps_work);
>-	u8 new_delay = dev_priv->cur_delay;
> 	u32 pm_iir, pm_imr;
>+	u8 new_delay;
> 
> 	spin_lock_irq(&dev_priv->rps_lock);
> 	pm_iir = dev_priv->pm_iir;
>@@ -367,37 +367,14 @@ static void gen6_pm_rps_work(struct work_struct *work)
> 		return;
> 
> 	mutex_lock(&dev_priv->dev->struct_mutex);
>-	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
>-		if (dev_priv->cur_delay != dev_priv->max_delay)
>-			new_delay = dev_priv->cur_delay + 1;
>-		if (new_delay > dev_priv->max_delay)
>-			new_delay = dev_priv->max_delay;
>-	} else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
>-		gen6_gt_force_wake_get(dev_priv);
>-		if (dev_priv->cur_delay != dev_priv->min_delay)
>-			new_delay = dev_priv->cur_delay - 1;
>-		if (new_delay < dev_priv->min_delay) {
>-			new_delay = dev_priv->min_delay;
>-			I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
>-				   I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
>-				   ((new_delay << 16) & 0x3f0000));
>-		} else {
>-			/* Make sure we continue to get down interrupts
>-			 * until we hit the minimum frequency */
>-			I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
>-				   I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
>-		}
>-		gen6_gt_force_wake_put(dev_priv);
>-	}
>+
>+	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
>+		new_delay = dev_priv->cur_delay + 1;
>+	else
>+		new_delay = dev_priv->cur_delay - 1;
> 
> 	gen6_set_rps(dev_priv->dev, new_delay);
>-	dev_priv->cur_delay = new_delay;
> 
>-	/*
>-	 * rps_lock not held here because clearing is non-destructive. There is
>-	 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
>-	 * by holding struct_mutex for the duration of the write.
>-	 */
> 	mutex_unlock(&dev_priv->dev->struct_mutex);
> }
> 
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index 3b05ba3..ec2a650 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -2127,10 +2127,33 @@ void ironlake_disable_drps(struct drm_device *dev)
> void gen6_set_rps(struct drm_device *dev, u8 val)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>-	u32 swreq;
>+	u32 limits;
> 
>-	swreq = (val & 0x3ff) << 25;
>-	I915_WRITE(GEN6_RPNSWREQ, swreq);
>+	limits = 0;
>+	if (val >= dev_priv->max_delay)
>+		val = dev_priv->max_delay;
>+	else
>+		limits |= dev_priv->max_delay << 24;
>+
>+	if (val <= dev_priv->min_delay)
>+		val = dev_priv->min_delay;
>+	else
>+		limits |= dev_priv->min_delay << 16;
>+
>+	if (val == dev_priv->cur_delay)
>+		return;
>+
>+	I915_WRITE(GEN6_RPNSWREQ,
>+		   GEN6_FREQUENCY(val) |
>+		   GEN6_OFFSET(0) |
>+		   GEN6_AGGRESSIVE_TURBO);
>+
>+	/* Make sure we continue to get interrupts
>+	 * until we hit the minimum or maximum frequencies.
>+	 */
>+	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
>+
>+	dev_priv->cur_delay = val;
> }
> 
> void gen6_disable_rps(struct drm_device *dev)
>@@ -2187,7 +2210,6 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
> 	u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
> 	u32 pcu_mbox, rc6_mask = 0;
> 	u32 gtfifodbg;
>-	int cur_freq, min_freq, max_freq;
> 	int rc6_mode;
> 	int i;
> 
>@@ -2208,6 +2230,14 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
> 
> 	gen6_gt_force_wake_get(dev_priv);
> 
>+	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
>+	gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
>+
>+	/* In units of 100MHz */
>+	dev_priv->max_delay = rp_state_cap & 0xff;
>+	dev_priv->min_delay = (rp_state_cap & 0xff0000) >> 16;
>+	dev_priv->cur_delay = 0;
>+
> 	/* disable the counters and set deterministic thresholds */
> 	I915_WRITE(GEN6_RC_CONTROL, 0);
> 
>@@ -2255,8 +2285,8 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
> 
> 	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
> 	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
>-		   18 << 24 |
>-		   6 << 16);
>+		   dev_priv->max_delay << 24 |
>+		   dev_priv->min_delay << 16);
> 	I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
> 	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
> 	I915_WRITE(GEN6_RP_UP_EI, 100000);
>@@ -2282,10 +2312,6 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
> 		     500))
> 		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
> 
>-	min_freq = (rp_state_cap & 0xff0000) >> 16;
>-	max_freq = rp_state_cap & 0xff;
>-	cur_freq = (gt_perf_status & 0xff00) >> 8;
>-
> 	/* Check for overclock support */
> 	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
> 		     500))
>@@ -2296,14 +2322,11 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
> 		     500))
> 		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
> 	if (pcu_mbox & (1<<31)) { /* OC supported */
>-		max_freq = pcu_mbox & 0xff;
>+		dev_priv->max_delay = pcu_mbox & 0xff;
> 		DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
> 	}
> 
>-	/* In units of 100MHz */
>-	dev_priv->max_delay = max_freq;
>-	dev_priv->min_delay = min_freq;
>-	dev_priv->cur_delay = cur_freq;
>+	gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
> 
> 	/* requires MSI enabled */
> 	I915_WRITE(GEN6_PMIER,
>-- 
>1.7.10
>

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