Attachment 61924 Details for Bug 45729 – reject doubleclocled cea modes on dp

[patch] reject doubleclocled cea modes on dp

0001-drm-i915-reject-doubleclocked-cea-modes-on-dp.patch (text/plain), 1.70 KB, created by Daniel Vetter on 2012-05-21 09:59:12 UTC

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Creator: Daniel Vetter

Created: 2012-05-21 09:59:12 UTC

Size: 1.70 KB

patch

obsolete

>From d28a8803ab0325393fd5c2507f5e3dd5064df2b7 Mon Sep 17 00:00:00 2001
>From: Daniel Vetter <daniel.vetter@ffwll.ch>
>Date: Mon, 21 May 2012 18:54:41 +0200
>Subject: [PATCH] drm/i915: reject doubleclocked cea modes on dp
>
>These are ultra-low-res modes used to upscale SDTV content and we
>don't know how to support these on dp on intel hw:
>- It's unclear whether we can send avi infoframes over dp ports.
>- And the pixel repeat setting that work for hdmi/sdvo explicitly
>  don't work for dp.
>
>So don't bother and just reject these modes. These modes have been
>introduced in
>
>commit 54ac76f851a1789b047b74a8e14980f2dd1ac749
>Author: Christian Schmidt <schmidt@digadd.de>
>Date:   Mon Dec 19 14:53:16 2011 +0000
>
>    drm/edid: support CEA video modes.
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45729
>Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>---
> drivers/gpu/drm/i915/intel_dp.c |    6 ++++++
> 1 file changed, 6 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index a1a5ce7..736a3c8 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -266,6 +266,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
> 	if (mode->clock < 10000)
> 		return MODE_CLOCK_LOW;
> 
>+	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
>+		return MODE_H_ILLEGAL;
>+
> 	return MODE_OK;
> }
> 
>@@ -702,6 +705,9 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
> 		mode->clock = intel_dp->panel_fixed_mode->clock;
> 	}
> 
>+	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
>+		return false;
>+
> 	DRM_DEBUG_KMS("DP link computation with max lane count %i "
> 		      "max bw %02x pixel clock %iKHz\n",
> 		      max_lane_count, bws[max_clock], mode->clock);
>-- 
>1.7.10
>

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