Attachment 62311 Details for Bug 50522 – running ZZ_hangman dmesg info

running ZZ_hangman dmesg info

ZZ_hangman.log (text/plain), 16.08 KB, created by Guang Yang on 2012-05-30 21:33:42 UTC

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Creator: Guang Yang

Created: 2012-05-30 21:33:42 UTC

Size: 16.08 KB

patch

obsolete

>[  169.715330] [drm:i915_ring_stop_write], Stopping rings 0x0000000f
>[  170.065746] [drm:i915_driver_open], 
>[  176.074075] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  176.074138] [drm] capturing error event; look for more information in /debug/dri/0/i915_error_state
>[  176.078555] [drm:i915_error_work_func], resetting chip
>[  176.131291] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  176.131584] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  176.131586] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  176.139271] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  176.154929] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  176.154933] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  176.155180] [drm:drm_crtc_helper_set_config], 
>[  176.155185] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:23] #connectors=1 (x y) (0 0)
>[  176.155196] [drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  176.155199] [drm:drm_crtc_helper_set_config], 
>[  176.155201] [drm:drm_crtc_helper_set_config], [CRTC:5] [NOFB]
>[  176.155218] [drm:drm_crtc_helper_set_config], 
>[  176.155220] [drm:drm_crtc_helper_set_config], [CRTC:7] [NOFB]
>[  176.155237] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
>[  176.155241] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
>[  176.155244] [drm:ironlake_check_srwm], watermark 2: display plane 87, fbc lines 3, cursor 6
>[  176.155247] [drm:ironlake_check_srwm], watermark 3: display plane 184, fbc lines 4, cursor 10
>[  176.155250] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
>[  176.155253] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
>[  176.155256] [drm:ironlake_check_srwm], watermark 2: display plane 87, fbc lines 3, cursor 6
>[  176.155259] [drm:ironlake_check_srwm], watermark 3: display plane 184, fbc lines 4, cursor 10
>[  176.155262] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
>[  176.155265] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
>[  176.155268] [drm:ironlake_check_srwm], watermark 2: display plane 87, fbc lines 3, cursor 6
>[  176.155270] [drm:ironlake_check_srwm], watermark 3: display plane 184, fbc lines 4, cursor 10
>[  176.155286] [drm:i915_driver_open], 
>[  182.163320] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  182.163597] [drm:i915_error_work_func], resetting chip
>[  182.215607] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  182.215900] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  182.215902] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  182.220676] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  182.239269] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  182.239273] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  188.248636] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  188.248922] [drm:i915_error_work_func], resetting chip
>[  188.299925] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  188.300216] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  188.300218] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  188.302078] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  188.323587] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  188.323591] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  194.333954] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  194.334232] [drm:i915_error_work_func], resetting chip
>[  194.386240] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  194.386531] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  194.386533] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  194.400098] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  194.409901] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  194.409904] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  200.419268] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  200.419552] [drm:i915_error_work_func], resetting chip
>[  200.471556] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  200.471847] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  200.471849] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  200.481501] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  200.495217] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  200.495221] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  206.504587] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  206.504897] [drm:i915_error_work_func], resetting chip
>[  206.556872] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  206.557165] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  206.557166] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  206.562874] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  206.580507] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  206.580511] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  212.589903] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  212.590210] [drm:i915_error_work_func], resetting chip
>[  212.642188] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  212.642479] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  212.642481] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  212.644278] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  212.665849] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  212.665853] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  218.675216] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  218.675499] [drm:i915_error_work_func], resetting chip
>[  218.727481] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  218.727772] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  218.727774] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  218.742333] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  218.751166] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  218.751169] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  224.760533] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  224.760825] [drm:i915_error_work_func], resetting chip
>[  224.812820] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  224.813112] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  224.813114] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  224.823735] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  224.836482] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  224.836485] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  230.845848] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  230.846147] [drm:i915_error_work_func], resetting chip
>[  230.898136] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  230.898428] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  230.898430] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  230.905139] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  230.921798] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  230.921802] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  236.931165] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  236.931481] [drm:i915_error_work_func], resetting chip
>[  236.982454] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  236.982746] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  236.982748] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  236.986530] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  237.006115] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  237.006119] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  243.016481] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  243.016844] [drm:i915_error_work_func], resetting chip
>[  243.067770] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  243.068072] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  243.068074] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  243.084564] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  243.091405] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  243.091409] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  249.105793] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  249.106083] [drm:i915_error_work_func], resetting chip
>[  249.158081] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  249.158372] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  249.158374] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  249.165942] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  249.181741] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  249.181745] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  255.203096] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  255.203458] [drm:i915_error_work_func], resetting chip
>[  255.255383] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  255.255674] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  255.255676] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  255.263988] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  255.279045] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  255.279049] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  261.312385] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  261.312736] [drm:i915_error_work_func], resetting chip
>[  261.364673] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  261.364964] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  261.364966] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  261.378624] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  261.388334] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  261.388338] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  267.441652] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  267.441957] [drm:i915_error_work_func], resetting chip
>[  267.493914] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  267.494205] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  267.494207] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  267.509867] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  267.517601] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  267.517605] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  273.614872] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  273.615177] [drm:i915_error_work_func], resetting chip
>[  273.667048] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  273.667279] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  273.667281] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  273.674360] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  273.690821] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  273.690825] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  279.875995] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  279.876303] [drm:i915_error_work_func], resetting chip
>[  279.928284] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  279.928515] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  279.928517] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  279.938536] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  279.951944] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  279.951948] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  286.296942] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
>[  286.297260] [drm:i915_error_work_func], resetting chip
>[  286.349233] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000
>[  286.349462] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
>[  286.349464] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
>[  286.352261] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  286.372864] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[  286.372867] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[  286.373105] [drm:drm_crtc_helper_set_config], 
>[  286.373111] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:23] #connectors=1 (x y) (0 0)
>[  286.373120] [drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  286.373124] [drm:drm_crtc_helper_set_config], 
>[  286.373127] [drm:drm_crtc_helper_set_config], [CRTC:5] [NOFB]
>[  286.373145] [drm:drm_crtc_helper_set_config], 
>[  286.373148] [drm:drm_crtc_helper_set_config], [CRTC:7] [NOFB]
>[  286.373167] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
>[  286.373172] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
>[  286.373176] [drm:ironlake_check_srwm], watermark 2: display plane 87, fbc lines 3, cursor 6
>[  286.373181] [drm:ironlake_check_srwm], watermark 3: display plane 184, fbc lines 4, cursor 10
>[  286.373186] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
>[  286.373190] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
>[  286.373194] [drm:ironlake_check_srwm], watermark 2: display plane 87, fbc lines 3, cursor 6
>[  286.373198] [drm:ironlake_check_srwm], watermark 3: display plane 184, fbc lines 4, cursor 10
>[  286.373203] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
>[  286.373207] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
>[  286.373211] [drm:ironlake_check_srwm], watermark 2: display plane 87, fbc lines 3, cursor 6
>[  286.373215] [drm:ironlake_check_srwm], watermark 3: display plane 184, fbc lines 4, cursor 10
>[  286.441595] [drm:i915_error_state_write], Resetting error state
>[  616.877874] [drm:ironlake_crtc_dpms], crtc 0/0 dpms on

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Attachments on bug 50522: 62311 | 62321 | 62354 | 62359 | 62484 | 62491 | 64372 | 65160 | 65216

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