Attachment 65373 Details for Bug 53322 – Apply post-sync write for TLB invalidate

[patch] Apply post-sync write for TLB invalidate

0001-drm-i915-Apply-post-sync-write-for-pipe-control-inva.patch (text/plain), 2.53 KB, created by Chris Wilson on 2012-08-10 08:34:16 UTC

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Creator: Chris Wilson

Created: 2012-08-10 08:34:16 UTC

Size: 2.53 KB

patch

obsolete

>From cd57bfe9b474edb68d3ea91bab05955fda8846a4 Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Fri, 10 Aug 2012 09:31:00 +0100
>Subject: [PATCH] drm/i915: Apply post-sync write for pipe control invalidates
>
>When invalidating the TLBs it is documentated as requiring a post-sync
>write. Failure to do so seems to result in a GPU hang.
>
>Reported-by: yex.tian@intel.com
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53322
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>---
> drivers/gpu/drm/i915/intel_ringbuffer.c |   33 ++++++++++++++++++-------------
> 1 file changed, 19 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>index 13318a0..dd1c6bc 100644
>--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>@@ -213,20 +213,25 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
> 	 * number of bits based on the write domains has little performance
> 	 * impact.
> 	 */
>-	flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>-	flags |= PIPE_CONTROL_TLB_INVALIDATE;
>-	flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
>-	flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
>-	flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>-	flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
>-	flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
>-	flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
>-	/*
>-	 * Ensure that any following seqno writes only happen when the render
>-	 * cache is indeed flushed (but only if the caller actually wants that).
>-	 */
>-	if (flush_domains)
>+	if (flush_domains) {
>+		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>+		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>+		/*
>+		 * Ensure that any following seqno writes only happen
>+		 * when the render cache is indeed flushed.
>+		 */
> 		flags |= PIPE_CONTROL_CS_STALL;
>+	}
>+	if (invalidate_domains) {
>+		flags |= PIPE_CONTROL_TLB_INVALIDATE;
>+		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
>+		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
>+		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
>+		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
>+		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
>+
>+		flags |= PIPE_CONTROL_QW_WRITE;
>+	}
> 
> 	ret = intel_ring_begin(ring, 4);
> 	if (ret)
>@@ -234,7 +239,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
> 
> 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
> 	intel_ring_emit(ring, flags);
>-	intel_ring_emit(ring, 0);
>+	intel_ring_emit(ring, (u32)ring->status_page.gfx_addr+2048);
> 	intel_ring_emit(ring, 0);
> 	intel_ring_advance(ring);
> 
>-- 
>1.7.10.4
>

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