Attachment 66403 Details for Bug 54230 – R600_DUMP_SHADERS=1 compiz --replace > Desktop/compiz-shader.txt 2>&1

R600_DUMP_SHADERS=1 compiz --replace > Desktop/compiz-shader.txt 2>&1

compiz-shader.txt (text/plain), 55.91 KB, created by Thomas Rohloff on 2012-08-31 12:37:31 UTC

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Creator: Thomas Rohloff

Created: 2012-08-31 12:37:31 UTC

Size: 55.91 KB

patch

obsolete

>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400400 TEX/VTX INST:0x1 COUNT:2
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 88CD1001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 88CD1002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0010 00000010   ENDIAN:0 OFFSET:16
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400400 TEX/VTX INST:0x1 COUNT:2
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 88CD1001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 D88D1002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:1 MODE:1)
>0010 00000010   ENDIAN:0 OFFSET:16
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400400 TEX/VTX INST:0x1 COUNT:2
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 88CD1001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 988D1002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:0 MODE:1)
>0010 00000010   ENDIAN:0 OFFSET:16
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 8 dw -- 2 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400000 TEX/VTX INST:0x1 COUNT:1
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 93564001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:4 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:13 NUM:1 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  call void @llvm.AMDGPU.store.output(float %0, i32 4)
>  call void @llvm.AMDGPU.store.output(float %1, i32 5)
>  call void @llvm.AMDGPU.store.output(float %2, i32 6)
>  call void @llvm.AMDGPU.store.output(float %3, i32 7)
>  call void @llvm.AMDGPU.store.output(float %4, i32 8)
>  call void @llvm.AMDGPU.store.output(float %5, i32 9)
>  call void @llvm.AMDGPU.store.output(float %6, i32 10)
>  call void @llvm.AMDGPU.store.output(float %7, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 8 dw -- 3 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0003 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0004 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 00000000 CF ADDR:0
>0007 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>  0: MOV OUT[0], IN[0]
>  1: END
>STREAMOUT
>  0: MEM_STREAM0_BUF0 OUT[0].x___
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  call void @llvm.AMDGPU.store.output(float %0, i32 4)
>  call void @llvm.AMDGPU.store.output(float %1, i32 5)
>  call void @llvm.AMDGPU.store.output(float %2, i32 6)
>  call void @llvm.AMDGPU.store.output(float %3, i32 7)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
>Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T1_W %T1_Z %T1_Y %T1_X
>	RETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 10 dw -- 2 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 00008000 EXPORT MEM_STREAM0_BUF0 GPR:1 ELEM_SIZE:0 ARRAY_BASE:0 TYPE:0
>0003 90001FFF EXPORT MEM_STREAM0_BUF0 ARRAY_SIZE:4095 COMP_MASK:1 BARRIER:1 INST:268435456 BURST_COUNT:1 EOP:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0004000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
># Machine code for function main: Post SSA, not tracking liveness
>
>BB#0: derived from LLVM BB %main_body
>	RETURN
>
># End machine code for function main.
>
>bytecode 14 dw -- 2 gprs ---------------------
>     C
>0000 00000003 ALU ADDR:6 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A00C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:4
>0006 000001C0   SRC0(SEL:448 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0007 00207010   INST:0xe0 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0008 000005C0   SRC0(SEL:448 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0009 20207010   INST:0xe0 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0010 000009C0   SRC0(SEL:448 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 40207010   INST:0xe0 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80000DC0   SRC0(SEL:448 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 60207010 * INST:0xe0 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 C0000000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0003 95000FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0004 00000000 CF ADDR:0
>0005 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV_SAT OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.AMDIL.clamp.(float %0, float 0.000000e+00, float 1.000000e+00)
>  %5 = call float @llvm.AMDIL.clamp.(float %1, float 0.000000e+00, float 1.000000e+00)
>  %6 = call float @llvm.AMDIL.clamp.(float %2, float 0.000000e+00, float 1.000000e+00)
>  %7 = call float @llvm.AMDIL.clamp.(float %3, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %4, i32 4)
>  call void @llvm.AMDGPU.store.output(float %5, i32 5)
>  call void @llvm.AMDGPU.store.output(float %6, i32 6)
>  call void @llvm.AMDGPU.store.output(float %7, i32 7)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
>Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T1_W %T1_Z %T1_Y %T1_X
>	%T1_X<def> = MOV %T1_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T1_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MOV %T1_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T1_W<def> = MOV %T1_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 30 dw -- 2 gprs ---------------------
>     C
>0000 00000003 ALU ADDR:6 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A02C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:12
>0006 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0007 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0008 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0009 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0010 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 40346B90   INST:0xd7 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 60346B90 * INST:0xd7 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 00346B10   INST:0xd6 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0017 20346B10   INST:0xd6 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 80200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0025 A0200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 00000801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 C0200C90   INST:0x19 DST(SEL:1 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 80000C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 E0200C90 * INST:0x19 DST(SEL:1 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 C0008000 EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0003 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0004 00000000 CF ADDR:0
>0005 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.AMDGPU.load.const(i32 0)
>  %9 = call float @llvm.AMDGPU.mul(float %0, float %8)
>  %10 = call float @llvm.AMDGPU.load.const(i32 1)
>  %11 = call float @llvm.AMDGPU.mul(float %0, float %10)
>  %12 = call float @llvm.AMDGPU.load.const(i32 2)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 3)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 4)
>  %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9)
>  %18 = call float @llvm.AMDGPU.load.const(i32 5)
>  %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11)
>  %20 = call float @llvm.AMDGPU.load.const(i32 6)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 7)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 8)
>  %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 9)
>  %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 10)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 11)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 12)
>  %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 13)
>  %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 14)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 15)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  %40 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00)
>  %41 = call float @llvm.AMDIL.clamp.(float %5, float 0.000000e+00, float 1.000000e+00)
>  %42 = call float @llvm.AMDIL.clamp.(float %6, float 0.000000e+00, float 1.000000e+00)
>  %43 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %33, i32 4)
>  call void @llvm.AMDGPU.store.output(float %35, i32 5)
>  call void @llvm.AMDGPU.store.output(float %37, i32 6)
>  call void @llvm.AMDGPU.store.output(float %39, i32 7)
>  call void @llvm.AMDGPU.store.output(float %40, i32 8)
>  call void @llvm.AMDGPU.store.output(float %41, i32 9)
>  call void @llvm.AMDGPU.store.output(float %42, i32 10)
>  call void @llvm.AMDGPU.store.output(float %43, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T3_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T3_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 54 dw -- 4 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0540000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:22
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00600090 * INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 006280FE * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 206284FE * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 206284FE   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20628403   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 006284FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228803 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0044 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0052 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>compiz (core) - Error: Couldn't load plugin 'yes'
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0], LOCAL
>  0: TXP TEMP[0].xyz, IN[0].xyyw, SAMP[0], 2D
>  1: MOV TEMP[0].xyz, TEMP[0].xyzx
>  2: MOV TEMP[0].w, CONST[4].wwww
>  3: MOV_SAT OUT[0], TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  call void @llvm.AMDGPU.reserve.reg(i32 4)
>  call void @llvm.AMDGPU.reserve.reg(i32 5)
>  call void @llvm.AMDGPU.reserve.reg(i32 6)
>  call void @llvm.AMDGPU.reserve.reg(i32 7)
>  %0 = call float @llvm.R600.load.input(i32 8)
>  %1 = call float @llvm.R600.load.input(i32 9)
>  %2 = call float @llvm.R600.load.input(i32 10)
>  %3 = call float @llvm.R600.load.input(i32 11)
>  %4 = call float @llvm.AMDGPU.div(float %0, float %3)
>  %5 = call float @llvm.AMDGPU.div(float %1, float %3)
>  %6 = call float @llvm.AMDGPU.div(float %1, float %3)
>  %7 = insertelement <4 x float> undef, float %4, i32 0
>  %8 = insertelement <4 x float> %7, float %5, i32 1
>  %9 = insertelement <4 x float> %8, float %6, i32 2
>  %10 = insertelement <4 x float> %9, float 1.000000e+00, i32 3
>  %11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %10, i32 0, i32 2)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = call float @llvm.AMDGPU.load.const(i32 19)
>  %16 = call float @llvm.AMDIL.clamp.(float %12, float 0.000000e+00, float 1.000000e+00)
>  %17 = call float @llvm.AMDIL.clamp.(float %13, float 0.000000e+00, float 1.000000e+00)
>  %18 = call float @llvm.AMDIL.clamp.(float %14, float 0.000000e+00, float 1.000000e+00)
>  %19 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %16, i32 8)
>  call void @llvm.AMDGPU.store.output(float %17, i32 9)
>  call void @llvm.AMDGPU.store.output(float %18, i32 10)
>  call void @llvm.AMDGPU.store.output(float %19, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.div(float, float) readnone
>
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Y in %vreg1, %T2_X in %vreg2
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Y %T2_X
>	%T2_Z<def> = RECIP_IEEE_eg %T2_W<kill>, pred:%PRED_SEL_OFF
>	%T0_X<def> = MUL %T2_X<kill>, %T2_Z, pred:%PRED_SEL_OFF, %T0_XYZW<imp-def>
>	%T2_X<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	%T0_W<def> = MOV %T2_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T2_X<def> = MUL %T2_Y<kill>, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %T2_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_Y<def> = MOV %T2_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_XYZW<def> = TEX_SAMPLE %T0_XYZW<kill>, 0, 2
>	%T2_X<def> = MOV %T0_X, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T0_Y, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T0_Z, 1, pred:%PRED_SEL_OFF, %T0_XYZW<imp-use,kill>
>	%T2_W<def> = MOV %C4_W, 1, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 52 dw -- 3 gprs ---------------------
>     C
>0000 00000005 ALU ADDR:10 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A0380000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:15
>0010 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0013 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 40546B90   INST:0xd7 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 60546B90 * INST:0xd7 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 00546B10   INST:0xd6 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0021 20546B10   INST:0xd6 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 40404310 * INST:0x86 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 811FC002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 00000090 * INST:0x1 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 800000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 00400C90 * INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 01004402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:2 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0033 00400090   INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0035 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0037 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0039 40000C90 * INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 00000014 TEX/VTX ADDR:40
>0003 80400000 TEX/VTX INST:0x1 COUNT:1
>0040 00000210   INST:0x10 RESOURCE_ID:2 SRC(GPR:0 REL:0)
>0041 F00D1000   DST(GPR:0 REL:0 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) LOD_BIAS:0 COORD_TYPE_X:1 COORD_TYPE_Y:1 COORD_TYPE_Z:1 COORD_TYPE_W:1
>0042 68800000   OFFSET_X:0 OFFSET_Y:0 OFFSET_Z:0 SAMPLER_ID:0 SRC(SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3)
>0043 00000000   
>0004 40000016 ALU ADDR:44 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0005 A00C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:4
>0044 00000000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00000400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00000800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 80000C84   SRC0(SEL:132 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0006 C0010000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.AMDGPU.load.const(i32 0)
>  %9 = call float @llvm.AMDGPU.mul(float %0, float %8)
>  %10 = call float @llvm.AMDGPU.load.const(i32 1)
>  %11 = call float @llvm.AMDGPU.mul(float %0, float %10)
>  %12 = call float @llvm.AMDGPU.load.const(i32 2)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 3)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 4)
>  %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9)
>  %18 = call float @llvm.AMDGPU.load.const(i32 5)
>  %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11)
>  %20 = call float @llvm.AMDGPU.load.const(i32 6)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 7)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 8)
>  %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 9)
>  %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 10)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 11)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 12)
>  %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 13)
>  %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 14)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 15)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  call void @llvm.AMDGPU.store.output(float %33, i32 4)
>  call void @llvm.AMDGPU.store.output(float %35, i32 5)
>  call void @llvm.AMDGPU.store.output(float %37, i32 6)
>  call void @llvm.AMDGPU.store.output(float %39, i32 7)
>  call void @llvm.AMDGPU.store.output(float %4, i32 8)
>  call void @llvm.AMDGPU.store.output(float %5, i32 9)
>  call void @llvm.AMDGPU.store.output(float %6, i32 10)
>  call void @llvm.AMDGPU.store.output(float %7, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T3_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T3_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T3_X<kill>, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 46 dw -- 4 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0440000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:18
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00600090 * INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 006280FE * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 206284FE * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 206284FE   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20628403   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 006284FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228803 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0044 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0045 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400400 TEX/VTX INST:0x1 COUNT:2
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 8C151001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:48 NUM:0 COMP:0 MODE:1)
>0006 00000008   ENDIAN:0 OFFSET:8
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 87961002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:30 NUM:0 COMP:0 MODE:1)
>0010 00000000   ENDIAN:0 OFFSET:0
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: TXP TEMP[0], IN[0].xyyw, SAMP[0], 2D
>  1: MOV_SAT OUT[0], TEMP[0]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  call void @llvm.AMDGPU.reserve.reg(i32 4)
>  call void @llvm.AMDGPU.reserve.reg(i32 5)
>  call void @llvm.AMDGPU.reserve.reg(i32 6)
>  call void @llvm.AMDGPU.reserve.reg(i32 7)
>  %0 = call float @llvm.R600.load.input(i32 8)
>  %1 = call float @llvm.R600.load.input(i32 9)
>  %2 = call float @llvm.R600.load.input(i32 10)
>  %3 = call float @llvm.R600.load.input(i32 11)
>  %4 = call float @llvm.AMDGPU.div(float %0, float %3)
>  %5 = call float @llvm.AMDGPU.div(float %1, float %3)
>  %6 = call float @llvm.AMDGPU.div(float %1, float %3)
>  %7 = insertelement <4 x float> undef, float %4, i32 0
>  %8 = insertelement <4 x float> %7, float %5, i32 1
>  %9 = insertelement <4 x float> %8, float %6, i32 2
>  %10 = insertelement <4 x float> %9, float 1.000000e+00, i32 3
>  %11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %10, i32 0, i32 2)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = call float @llvm.AMDIL.clamp.(float %12, float 0.000000e+00, float 1.000000e+00)
>  %17 = call float @llvm.AMDIL.clamp.(float %13, float 0.000000e+00, float 1.000000e+00)
>  %18 = call float @llvm.AMDIL.clamp.(float %14, float 0.000000e+00, float 1.000000e+00)
>  %19 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %16, i32 8)
>  call void @llvm.AMDGPU.store.output(float %17, i32 9)
>  call void @llvm.AMDGPU.store.output(float %18, i32 10)
>  call void @llvm.AMDGPU.store.output(float %19, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.div(float, float) readnone
>
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Y in %vreg1, %T2_X in %vreg2
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Y %T2_X
>	%T2_Z<def> = RECIP_IEEE_eg %T2_W<kill>, pred:%PRED_SEL_OFF
>	%T0_X<def> = MUL %T2_X<kill>, %T2_Z, pred:%PRED_SEL_OFF, %T0_XYZW<imp-def>
>	%T2_X<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	%T0_W<def> = MOV %T2_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T2_X<def> = MUL %T2_Y<kill>, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %T2_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_Y<def> = MOV %T2_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_XYZW<def> = TEX_SAMPLE %T0_XYZW<kill>, 0, 2
>	%T2_X<def> = MOV %T0_X, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T0_Y, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T0_Z, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T0_W, 1, pred:%PRED_SEL_OFF, %T0_XYZW<imp-use,kill>
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 52 dw -- 3 gprs ---------------------
>     C
>0000 00000005 ALU ADDR:10 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A0380000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:15
>0010 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0013 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 40546B90   INST:0xd7 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 60546B90 * INST:0xd7 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 00546B10   INST:0xd6 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0021 20546B10   INST:0xd6 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 40404310 * INST:0x86 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 811FC002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 00000090 * INST:0x1 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 800000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 00400C90 * INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 01004402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:2 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0033 00400090   INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0035 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0037 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0039 40000C90 * INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 00000014 TEX/VTX ADDR:40
>0003 80400000 TEX/VTX INST:0x1 COUNT:1
>0040 00000210   INST:0x10 RESOURCE_ID:2 SRC(GPR:0 REL:0)
>0041 F00D1000   DST(GPR:0 REL:0 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) LOD_BIAS:0 COORD_TYPE_X:1 COORD_TYPE_Y:1 COORD_TYPE_Z:1 COORD_TYPE_W:1
>0042 68800000   OFFSET_X:0 OFFSET_Y:0 OFFSET_Z:0 SAMPLER_ID:0 SRC(SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3)
>0043 00000000   
>0004 00000016 ALU ADDR:44 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0005 A00C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:4
>0044 00000000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00000400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00000800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 80000C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0006 C0010000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________

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Attachments on bug 54230: 66294 | 66295 | 66296 | 66297 | 66403 | 66404

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