Attachment 66404 Details for Bug 54230 – R600_DUMP_SHADERS=1 java -jar minecraft.jar > Desktop/minecraft-shader.txt 2>&1

R600_DUMP_SHADERS=1 java -jar minecraft.jar > Desktop/minecraft-shader.txt 2>&1

minecraft-shader.txt (text/plain), 552.12 KB, created by Thomas Rohloff on 2012-08-31 12:38:25 UTC

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Creator: Thomas Rohloff

Created: 2012-08-31 12:38:25 UTC

Size: 552.12 KB

patch

obsolete

>asdf
>27 achievements
>195 recipes
>Setting user: V10lator, -6982137594648686781
>LWJGL Version: 2.4.2
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400400 TEX/VTX INST:0x1 COUNT:2
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 88CD1001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 88CD1002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0010 00000010   ENDIAN:0 OFFSET:16
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400400 TEX/VTX INST:0x1 COUNT:2
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 88CD1001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 D88D1002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:1 MODE:1)
>0010 00000010   ENDIAN:0 OFFSET:16
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400400 TEX/VTX INST:0x1 COUNT:2
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 88CD1001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 988D1002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:0 MODE:1)
>0010 00000010   ENDIAN:0 OFFSET:16
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 8 dw -- 2 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400000 TEX/VTX INST:0x1 COUNT:1
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 93564001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:4 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:13 NUM:1 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  call void @llvm.AMDGPU.store.output(float %0, i32 4)
>  call void @llvm.AMDGPU.store.output(float %1, i32 5)
>  call void @llvm.AMDGPU.store.output(float %2, i32 6)
>  call void @llvm.AMDGPU.store.output(float %3, i32 7)
>  call void @llvm.AMDGPU.store.output(float %4, i32 8)
>  call void @llvm.AMDGPU.store.output(float %5, i32 9)
>  call void @llvm.AMDGPU.store.output(float %6, i32 10)
>  call void @llvm.AMDGPU.store.output(float %7, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 8 dw -- 3 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0003 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0004 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 00000000 CF ADDR:0
>0007 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>  0: MOV OUT[0], IN[0]
>  1: END
>STREAMOUT
>  0: MEM_STREAM0_BUF0 OUT[0].x___
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  call void @llvm.AMDGPU.store.output(float %0, i32 4)
>  call void @llvm.AMDGPU.store.output(float %1, i32 5)
>  call void @llvm.AMDGPU.store.output(float %2, i32 6)
>  call void @llvm.AMDGPU.store.output(float %3, i32 7)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
>Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T1_W %T1_Z %T1_Y %T1_X
>	RETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 10 dw -- 2 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 00008000 EXPORT MEM_STREAM0_BUF0 GPR:1 ELEM_SIZE:0 ARRAY_BASE:0 TYPE:0
>0003 90001FFF EXPORT MEM_STREAM0_BUF0 ARRAY_SIZE:4095 COMP_MASK:1 BARRIER:1 INST:268435456 BURST_COUNT:1 EOP:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0004000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
># Machine code for function main: Post SSA, not tracking liveness
>
>BB#0: derived from LLVM BB %main_body
>	RETURN
>
># End machine code for function main.
>
>bytecode 14 dw -- 2 gprs ---------------------
>     C
>0000 00000003 ALU ADDR:6 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A00C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:4
>0006 000001C0   SRC0(SEL:448 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0007 00207010   INST:0xe0 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0008 000005C0   SRC0(SEL:448 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0009 20207010   INST:0xe0 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0010 000009C0   SRC0(SEL:448 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 40207010   INST:0xe0 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80000DC0   SRC0(SEL:448 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 60207010 * INST:0xe0 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 C0000000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0003 95000FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0004 00000000 CF ADDR:0
>0005 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV_SAT OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.AMDIL.clamp.(float %0, float 0.000000e+00, float 1.000000e+00)
>  %5 = call float @llvm.AMDIL.clamp.(float %1, float 0.000000e+00, float 1.000000e+00)
>  %6 = call float @llvm.AMDIL.clamp.(float %2, float 0.000000e+00, float 1.000000e+00)
>  %7 = call float @llvm.AMDIL.clamp.(float %3, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %4, i32 4)
>  call void @llvm.AMDGPU.store.output(float %5, i32 5)
>  call void @llvm.AMDGPU.store.output(float %6, i32 6)
>  call void @llvm.AMDGPU.store.output(float %7, i32 7)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
>Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T1_W %T1_Z %T1_Y %T1_X
>	%T1_X<def> = MOV %T1_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T1_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MOV %T1_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T1_W<def> = MOV %T1_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 30 dw -- 2 gprs ---------------------
>     C
>0000 00000003 ALU ADDR:6 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A02C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:12
>0006 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0007 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0008 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0009 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0010 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 40346B90   INST:0xd7 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 60346B90 * INST:0xd7 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 00346B10   INST:0xd6 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0017 20346B10   INST:0xd6 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 80200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0025 A0200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 00000801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 C0200C90   INST:0x19 DST(SEL:1 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 80000C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 E0200C90 * INST:0x19 DST(SEL:1 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 C0008000 EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0003 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0004 00000000 CF ADDR:0
>0005 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.AMDGPU.load.const(i32 0)
>  %9 = call float @llvm.AMDGPU.mul(float %0, float %8)
>  %10 = call float @llvm.AMDGPU.load.const(i32 1)
>  %11 = call float @llvm.AMDGPU.mul(float %0, float %10)
>  %12 = call float @llvm.AMDGPU.load.const(i32 2)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 3)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 4)
>  %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9)
>  %18 = call float @llvm.AMDGPU.load.const(i32 5)
>  %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11)
>  %20 = call float @llvm.AMDGPU.load.const(i32 6)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 7)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 8)
>  %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 9)
>  %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 10)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 11)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 12)
>  %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 13)
>  %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 14)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 15)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  %40 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00)
>  %41 = call float @llvm.AMDIL.clamp.(float %5, float 0.000000e+00, float 1.000000e+00)
>  %42 = call float @llvm.AMDIL.clamp.(float %6, float 0.000000e+00, float 1.000000e+00)
>  %43 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %33, i32 4)
>  call void @llvm.AMDGPU.store.output(float %35, i32 5)
>  call void @llvm.AMDGPU.store.output(float %37, i32 6)
>  call void @llvm.AMDGPU.store.output(float %39, i32 7)
>  call void @llvm.AMDGPU.store.output(float %40, i32 8)
>  call void @llvm.AMDGPU.store.output(float %41, i32 9)
>  call void @llvm.AMDGPU.store.output(float %42, i32 10)
>  call void @llvm.AMDGPU.store.output(float %43, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T3_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T3_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 54 dw -- 4 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0540000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:22
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00600090 * INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 006280FE * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 206284FE * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 206284FE   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20628403   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 006284FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228803 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0044 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0052 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  call void @llvm.AMDGPU.reserve.reg(i32 4)
>  call void @llvm.AMDGPU.reserve.reg(i32 5)
>  call void @llvm.AMDGPU.reserve.reg(i32 6)
>  call void @llvm.AMDGPU.reserve.reg(i32 7)
>  %0 = call float @llvm.R600.load.input(i32 8)
>  %1 = call float @llvm.R600.load.input(i32 9)
>  %2 = call float @llvm.R600.load.input(i32 10)
>  %3 = call float @llvm.R600.load.input(i32 11)
>  call void @llvm.AMDGPU.store.output(float %0, i32 8)
>  call void @llvm.AMDGPU.store.output(float %1, i32 9)
>  call void @llvm.AMDGPU.store.output(float %2, i32 10)
>  call void @llvm.AMDGPU.store.output(float %3, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 22 dw -- 3 gprs ---------------------
>     C
>0000 00000003 ALU ADDR:6 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A01C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:8
>0006 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0007 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0008 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0009 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0010 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 40546B90   INST:0xd7 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 60546B90 * INST:0xd7 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 00546B10   INST:0xd6 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0017 20546B10   INST:0xd6 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 C0010000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0003 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0004 00000000 CF ADDR:0
>0005 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  call void @llvm.AMDGPU.reserve.reg(i32 4)
>  call void @llvm.AMDGPU.reserve.reg(i32 5)
>  call void @llvm.AMDGPU.reserve.reg(i32 6)
>  call void @llvm.AMDGPU.reserve.reg(i32 7)
>  %0 = call float @llvm.R600.load.input(i32 8)
>  %1 = call float @llvm.R600.load.input(i32 9)
>  %2 = call float @llvm.R600.load.input(i32 10)
>  %3 = call float @llvm.R600.load.input(i32 11)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  %8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 2)
>  %9 = extractelement <4 x float> %8, i32 0
>  %10 = extractelement <4 x float> %8, i32 1
>  %11 = extractelement <4 x float> %8, i32 2
>  %12 = extractelement <4 x float> %8, i32 3
>  call void @llvm.AMDGPU.store.output(float %9, i32 8)
>  call void @llvm.AMDGPU.store.output(float %10, i32 9)
>  call void @llvm.AMDGPU.store.output(float %11, i32 10)
>  call void @llvm.AMDGPU.store.output(float %12, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X
>	%T0_X<def> = MOV %T2_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_W<def> = MOV %T2_W<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_Z<def> = MOV %T2_Z<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_Y<def> = MOV %T2_Y<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_XYZW<def> = TEX_SAMPLE %T0_XYZW<kill>, 0, 2
>	%T2_X<def> = MOV %T0_X, 0, pred:%noreg
>	%T2_Y<def> = MOV %T0_Y, 0, pred:%noreg
>	%T2_Z<def> = MOV %T0_Z, 0, pred:%noreg
>	%T2_W<def> = MOV %T0_W, 0, pred:%noreg
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 48 dw -- 3 gprs ---------------------
>     C
>0000 00000005 ALU ADDR:10 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A02C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:12
>0010 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0013 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 40546B90   INST:0xd7 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 60546B90 * INST:0xd7 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 00546B10   INST:0xd6 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0021 20546B10   INST:0xd6 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 00000C90   INST:0x19 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0031 40000C90   INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 00000012 TEX/VTX ADDR:36
>0003 80400000 TEX/VTX INST:0x1 COUNT:1
>0036 00000210   INST:0x10 RESOURCE_ID:2 SRC(GPR:0 REL:0)
>0037 F00D1000   DST(GPR:0 REL:0 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) LOD_BIAS:0 COORD_TYPE_X:1 COORD_TYPE_Y:1 COORD_TYPE_Z:1 COORD_TYPE_W:1
>0038 68800000   OFFSET_X:0 OFFSET_Y:0 OFFSET_Z:0 SAMPLER_ID:0 SRC(SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3)
>0039 00000000   
>0004 00000014 ALU ADDR:40 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0005 A00C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:4
>0040 00000000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 00400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 00000400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0043 20400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0044 00000800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 40400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 80000C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0047 60400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0006 C0010000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: TXP TEMP[0], IN[1].xyyw, SAMP[0], 2D
>  1: MUL TEMP[0], TEMP[0], IN[0]
>  2: MOV_SAT OUT[0], TEMP[0]
>  3: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  call void @llvm.AMDGPU.reserve.reg(i32 4)
>  call void @llvm.AMDGPU.reserve.reg(i32 5)
>  call void @llvm.AMDGPU.reserve.reg(i32 6)
>  call void @llvm.AMDGPU.reserve.reg(i32 7)
>  %0 = call float @llvm.R600.load.input(i32 8)
>  %1 = call float @llvm.R600.load.input(i32 9)
>  %2 = call float @llvm.R600.load.input(i32 10)
>  %3 = call float @llvm.R600.load.input(i32 11)
>  %4 = call float @llvm.R600.load.input(i32 12)
>  %5 = call float @llvm.R600.load.input(i32 13)
>  %6 = call float @llvm.R600.load.input(i32 14)
>  %7 = call float @llvm.R600.load.input(i32 15)
>  %8 = call float @llvm.AMDGPU.div(float %4, float %7)
>  %9 = call float @llvm.AMDGPU.div(float %5, float %7)
>  %10 = call float @llvm.AMDGPU.div(float %5, float %7)
>  %11 = insertelement <4 x float> undef, float %8, i32 0
>  %12 = insertelement <4 x float> %11, float %9, i32 1
>  %13 = insertelement <4 x float> %12, float %10, i32 2
>  %14 = insertelement <4 x float> %13, float 1.000000e+00, i32 3
>  %15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %14, i32 0, i32 2)
>  %16 = extractelement <4 x float> %15, i32 0
>  %17 = extractelement <4 x float> %15, i32 1
>  %18 = extractelement <4 x float> %15, i32 2
>  %19 = extractelement <4 x float> %15, i32 3
>  %20 = call float @llvm.AMDGPU.mul(float %16, float %0)
>  %21 = call float @llvm.AMDGPU.mul(float %17, float %1)
>  %22 = call float @llvm.AMDGPU.mul(float %18, float %2)
>  %23 = call float @llvm.AMDGPU.mul(float %19, float %3)
>  %24 = call float @llvm.AMDIL.clamp.(float %20, float 0.000000e+00, float 1.000000e+00)
>  %25 = call float @llvm.AMDIL.clamp.(float %21, float 0.000000e+00, float 1.000000e+00)
>  %26 = call float @llvm.AMDIL.clamp.(float %22, float 0.000000e+00, float 1.000000e+00)
>  %27 = call float @llvm.AMDIL.clamp.(float %23, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %24, i32 8)
>  call void @llvm.AMDGPU.store.output(float %25, i32 9)
>  call void @llvm.AMDGPU.store.output(float %26, i32 10)
>  call void @llvm.AMDGPU.store.output(float %27, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.div(float, float) readnone
>
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T3_W in %vreg0, %T3_Y in %vreg1, %T3_X in %vreg2, %T2_W in %vreg3, %T2_Z in %vreg4, %T2_Y in %vreg5, %T2_X in %vreg6
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T3_W %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X
>	%T3_Z<def> = RECIP_IEEE_eg %T3_W<kill>, pred:%PRED_SEL_OFF
>	%T0_X<def> = MUL %T3_X<kill>, %T3_Z, pred:%PRED_SEL_OFF, %T0_XYZW<imp-def>
>	%T3_X<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	%T0_W<def> = MOV %T3_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T3_X<def> = MUL %T3_Y<kill>, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %T3_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_Y<def> = MOV %T3_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_XYZW<def> = TEX_SAMPLE %T0_XYZW<kill>, 0, 2
>	%T2_X<def> = MUL %T0_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MUL %T0_Y, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MUL %T0_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MUL %T0_W, %T2_W<kill>, pred:%PRED_SEL_OFF, %T0_XYZW<imp-use,kill>
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 76 dw -- 4 gprs ---------------------
>     C
>0000 00000005 ALU ADDR:10 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A0580000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:23
>0010 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0013 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 40546B90   INST:0xd7 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 60546B90 * INST:0xd7 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 00546B10   INST:0xd6 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0021 20546B10   INST:0xd6 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 00382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0031 40746B90   INST:0xd7 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 80382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 60746B90 * INST:0xd7 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00746B10   INST:0xd6 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 00382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0037 20746B10   INST:0xd6 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0040 80382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0041 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 80000C03   SRC0(SEL:3 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40604310 * INST:0x86 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0044 811FC003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0045 00000090 * INST:0x1 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 800000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0047 00600C90 * INST:0x19 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 01006403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:3 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 00600090   INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0052 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0053 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0054 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0055 40000C90 * INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 0000001C TEX/VTX ADDR:56
>0003 80400000 TEX/VTX INST:0x1 COUNT:1
>0056 00000210   INST:0x10 RESOURCE_ID:2 SRC(GPR:0 REL:0)
>0057 F00D1000   DST(GPR:0 REL:0 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) LOD_BIAS:0 COORD_TYPE_X:1 COORD_TYPE_Y:1 COORD_TYPE_Z:1 COORD_TYPE_W:1
>0058 68800000   OFFSET_X:0 OFFSET_Y:0 OFFSET_Z:0 SAMPLER_ID:0 SRC(SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3)
>0059 00000000   
>0004 0000001E ALU ADDR:60 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0005 A01C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:8
>0060 00004000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0061 00400090   INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0062 00804400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:2 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0063 20400090   INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0064 81004800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:2 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0065 40400090 * INST:0x1 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0066 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0067 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0068 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0069 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0070 000008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0071 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0072 81804C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:2 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0073 60400090 * INST:0x1 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0074 80000CFE   SRC0(SEL:254 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0075 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0006 C0010000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.R600.load.input(i32 12)
>  %9 = call float @llvm.R600.load.input(i32 13)
>  %10 = call float @llvm.R600.load.input(i32 14)
>  %11 = call float @llvm.R600.load.input(i32 15)
>  %12 = call float @llvm.AMDGPU.load.const(i32 0)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 1)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 2)
>  %17 = call float @llvm.AMDGPU.mul(float %0, float %16)
>  %18 = call float @llvm.AMDGPU.load.const(i32 3)
>  %19 = call float @llvm.AMDGPU.mul(float %0, float %18)
>  %20 = call float @llvm.AMDGPU.load.const(i32 4)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 5)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 6)
>  %25 = call float @llvm.AMDIL.mad.(float %1, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 7)
>  %27 = call float @llvm.AMDIL.mad.(float %1, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 8)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 9)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 10)
>  %33 = call float @llvm.AMDIL.mad.(float %2, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 11)
>  %35 = call float @llvm.AMDIL.mad.(float %2, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 12)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 13)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  %40 = call float @llvm.AMDGPU.load.const(i32 14)
>  %41 = call float @llvm.AMDIL.mad.(float %3, float %40, float %33)
>  %42 = call float @llvm.AMDGPU.load.const(i32 15)
>  %43 = call float @llvm.AMDIL.mad.(float %3, float %42, float %35)
>  %44 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00)
>  %45 = call float @llvm.AMDIL.clamp.(float %5, float 0.000000e+00, float 1.000000e+00)
>  %46 = call float @llvm.AMDIL.clamp.(float %6, float 0.000000e+00, float 1.000000e+00)
>  %47 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %37, i32 4)
>  call void @llvm.AMDGPU.store.output(float %39, i32 5)
>  call void @llvm.AMDGPU.store.output(float %41, i32 6)
>  call void @llvm.AMDGPU.store.output(float %43, i32 7)
>  call void @llvm.AMDGPU.store.output(float %44, i32 8)
>  call void @llvm.AMDGPU.store.output(float %45, i32 9)
>  call void @llvm.AMDGPU.store.output(float %46, i32 10)
>  call void @llvm.AMDGPU.store.output(float %47, i32 11)
>  call void @llvm.AMDGPU.store.output(float %8, i32 12)
>  call void @llvm.AMDGPU.store.output(float %9, i32 13)
>  call void @llvm.AMDGPU.store.output(float %10, i32 14)
>  call void @llvm.AMDGPU.store.output(float %11, i32 15)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T3_W in %vreg0, %T3_Z in %vreg1, %T3_Y in %vreg2, %T3_X in %vreg3, %T2_W in %vreg4, %T2_Z in %vreg5, %T2_Y in %vreg6, %T2_X in %vreg7, %T1_W in %vreg8, %T1_Z in %vreg9, %T1_Y in %vreg10, %T1_X in %vreg11
>Function Live Outs: %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T4_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %T1_Y, %C1_X, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %T1_Z, %C2_X, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %T1_W, %C3_X, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T1_W, %C3_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T4_X<kill>, 0, pred:%noreg
>	%T4_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T4_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T3_W<imp-use,kill>, %T3_Z<imp-use,kill>, %T3_Y<imp-use,kill>, %T3_X<imp-use,kill>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 54 dw -- 5 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0540000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:22
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00800090 * INST:0x1 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 008280FE * INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 008280FE   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20800090 * INST:0x1 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 008280FE   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 208284FE * INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 208284FE   INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40800090 * INST:0x1 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 408288FE * INST:0x14 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20828404   INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 408288FE * INST:0x14 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 008284FE   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228804 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:2 NEG:0)
>0044 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0052 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95010688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:2 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 16 dw -- 4 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400800 TEX/VTX INST:0x1 COUNT:3
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 8C151001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:48 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 868D1002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:26 NUM:0 COMP:0 MODE:1)
>0010 00000014   ENDIAN:0 OFFSET:20
>0011 00000000   
>0012 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0013 87961003   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:3 SEL_X:0 SEL_Y:1 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:30 NUM:0 COMP:0 MODE:1)
>0014 0000000C   ENDIAN:0 OFFSET:12
>0015 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0], LOCAL
>  0: TXP TEMP[0], IN[0].xyyw, SAMP[0], 2D
>  1: MUL TEMP[0], TEMP[0], CONST[4]
>  2: MOV_SAT OUT[0], TEMP[0]
>  3: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  call void @llvm.AMDGPU.reserve.reg(i32 4)
>  call void @llvm.AMDGPU.reserve.reg(i32 5)
>  call void @llvm.AMDGPU.reserve.reg(i32 6)
>  call void @llvm.AMDGPU.reserve.reg(i32 7)
>  %0 = call float @llvm.R600.load.input(i32 8)
>  %1 = call float @llvm.R600.load.input(i32 9)
>  %2 = call float @llvm.R600.load.input(i32 10)
>  %3 = call float @llvm.R600.load.input(i32 11)
>  %4 = call float @llvm.AMDGPU.div(float %0, float %3)
>  %5 = call float @llvm.AMDGPU.div(float %1, float %3)
>  %6 = call float @llvm.AMDGPU.div(float %1, float %3)
>  %7 = insertelement <4 x float> undef, float %4, i32 0
>  %8 = insertelement <4 x float> %7, float %5, i32 1
>  %9 = insertelement <4 x float> %8, float %6, i32 2
>  %10 = insertelement <4 x float> %9, float 1.000000e+00, i32 3
>  %11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %10, i32 0, i32 2)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = call float @llvm.AMDGPU.load.const(i32 16)
>  %17 = call float @llvm.AMDGPU.mul(float %12, float %16)
>  %18 = call float @llvm.AMDGPU.load.const(i32 17)
>  %19 = call float @llvm.AMDGPU.mul(float %13, float %18)
>  %20 = call float @llvm.AMDGPU.load.const(i32 18)
>  %21 = call float @llvm.AMDGPU.mul(float %14, float %20)
>  %22 = call float @llvm.AMDGPU.load.const(i32 19)
>  %23 = call float @llvm.AMDGPU.mul(float %15, float %22)
>  %24 = call float @llvm.AMDIL.clamp.(float %17, float 0.000000e+00, float 1.000000e+00)
>  %25 = call float @llvm.AMDIL.clamp.(float %19, float 0.000000e+00, float 1.000000e+00)
>  %26 = call float @llvm.AMDIL.clamp.(float %21, float 0.000000e+00, float 1.000000e+00)
>  %27 = call float @llvm.AMDIL.clamp.(float %23, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %24, i32 8)
>  call void @llvm.AMDGPU.store.output(float %25, i32 9)
>  call void @llvm.AMDGPU.store.output(float %26, i32 10)
>  call void @llvm.AMDGPU.store.output(float %27, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.div(float, float) readnone
>
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Y in %vreg1, %T2_X in %vreg2
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Y %T2_X
>	%T2_Z<def> = RECIP_IEEE_eg %T2_W<kill>, pred:%PRED_SEL_OFF
>	%T0_X<def> = MUL %T2_X<kill>, %T2_Z, pred:%PRED_SEL_OFF, %T0_XYZW<imp-def>
>	%T2_X<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	%T0_W<def> = MOV %T2_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T2_X<def> = MUL %T2_Y<kill>, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %T2_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_Y<def> = MOV %T2_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_XYZW<def> = TEX_SAMPLE %T0_XYZW<kill>, 0, 2
>	%T2_X<def> = MUL %T0_X, %C4_X, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MUL %T0_Y, %C4_Y, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MUL %T0_Z, %C4_Z, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MUL %T0_W, %C4_W, pred:%PRED_SEL_OFF, %T0_XYZW<imp-use,kill>
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 60 dw -- 3 gprs ---------------------
>     C
>0000 00000005 ALU ADDR:10 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A0380000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:15
>0010 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0013 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 40546B90   INST:0xd7 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 60546B90 * INST:0xd7 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 00546B10   INST:0xd6 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0021 20546B10   INST:0xd6 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 40404310 * INST:0x86 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 811FC002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 00000090 * INST:0x1 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 800000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 00400C90 * INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 01004402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:2 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0033 00400090   INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0035 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0037 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0039 40000C90 * INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 00000014 TEX/VTX ADDR:40
>0003 80400000 TEX/VTX INST:0x1 COUNT:1
>0040 00000210   INST:0x10 RESOURCE_ID:2 SRC(GPR:0 REL:0)
>0041 F00D1000   DST(GPR:0 REL:0 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) LOD_BIAS:0 COORD_TYPE_X:1 COORD_TYPE_Y:1 COORD_TYPE_Z:1 COORD_TYPE_W:1
>0042 68800000   OFFSET_X:0 OFFSET_Y:0 OFFSET_Z:0 SAMPLER_ID:0 SRC(SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3)
>0043 00000000   
>0004 40000016 ALU ADDR:44 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0005 A01C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:8
>0044 00108000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:132 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 00400090   INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00908400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:132 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 20400090   INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 81108800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:132 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0049 40400090 * INST:0x1 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0051 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0052 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0053 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0054 000008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0055 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0056 81908C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:132 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0057 60400090 * INST:0x1 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0058 80000CFE   SRC0(SEL:254 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0059 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0006 C0010000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.AMDGPU.load.const(i32 0)
>  %9 = call float @llvm.AMDGPU.mul(float %0, float %8)
>  %10 = call float @llvm.AMDGPU.load.const(i32 1)
>  %11 = call float @llvm.AMDGPU.mul(float %0, float %10)
>  %12 = call float @llvm.AMDGPU.load.const(i32 2)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 3)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 4)
>  %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9)
>  %18 = call float @llvm.AMDGPU.load.const(i32 5)
>  %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11)
>  %20 = call float @llvm.AMDGPU.load.const(i32 6)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 7)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 8)
>  %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 9)
>  %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 10)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 11)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 12)
>  %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 13)
>  %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 14)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 15)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  call void @llvm.AMDGPU.store.output(float %33, i32 4)
>  call void @llvm.AMDGPU.store.output(float %35, i32 5)
>  call void @llvm.AMDGPU.store.output(float %37, i32 6)
>  call void @llvm.AMDGPU.store.output(float %39, i32 7)
>  call void @llvm.AMDGPU.store.output(float %4, i32 8)
>  call void @llvm.AMDGPU.store.output(float %5, i32 9)
>  call void @llvm.AMDGPU.store.output(float %6, i32 10)
>  call void @llvm.AMDGPU.store.output(float %7, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T3_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T3_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T3_X<kill>, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 46 dw -- 4 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0440000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:18
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00600090 * INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 006280FE * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 206284FE * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 206284FE   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20628403   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 006284FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228803 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0044 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0045 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400400 TEX/VTX INST:0x1 COUNT:2
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 8C151001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:48 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 87961002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:30 NUM:0 COMP:0 MODE:1)
>0010 0000000C   ENDIAN:0 OFFSET:12
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>
>Starting up SoundSystem...
>Initializing LWJGL OpenAL
>    (The LWJGL binding of OpenAL.  For more information, see http://www.lwjgl.org)
>AL lib: pulseaudio.c:331: PulseAudio returned minreq > tlength/2; expect break up
>OpenAL initialized.
>
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400400 TEX/VTX INST:0x1 COUNT:2
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 88CD1001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 88CD1002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0010 00000010   ENDIAN:0 OFFSET:16
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>IMM FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV OUT[0], IMM[0].xxxy
>  1: TEX OUT[0].xyz, IN[0], SAMP[0], 2D
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  call void @llvm.AMDGPU.reserve.reg(i32 4)
>  call void @llvm.AMDGPU.reserve.reg(i32 5)
>  call void @llvm.AMDGPU.reserve.reg(i32 6)
>  call void @llvm.AMDGPU.reserve.reg(i32 7)
>  %0 = call float @llvm.R600.load.input(i32 8)
>  %1 = call float @llvm.R600.load.input(i32 9)
>  %2 = call float @llvm.R600.load.input(i32 10)
>  %3 = call float @llvm.R600.load.input(i32 11)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  %8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 2)
>  %9 = extractelement <4 x float> %8, i32 0
>  %10 = extractelement <4 x float> %8, i32 1
>  %11 = extractelement <4 x float> %8, i32 2
>  call void @llvm.AMDGPU.store.output(float %9, i32 8)
>  call void @llvm.AMDGPU.store.output(float %10, i32 9)
>  call void @llvm.AMDGPU.store.output(float %11, i32 10)
>  call void @llvm.AMDGPU.store.output(float 1.000000e+00, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X
>	%T0_X<def> = MOV %T2_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_W<def> = MOV %T2_W<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_Z<def> = MOV %T2_Z<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_Y<def> = MOV %T2_Y<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_XYZW<def> = TEX_SAMPLE %T0_XYZW<kill>, 0, 2
>	%T2_X<def> = MOV %T0_X, 0, pred:%noreg
>	%T2_Y<def> = MOV %T0_Y, 0, pred:%noreg
>	%T2_Z<def> = MOV %T0_Z, 0, pred:%noreg
>	%T2_W<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 48 dw -- 3 gprs ---------------------
>     C
>0000 00000005 ALU ADDR:10 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A02C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:12
>0010 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0013 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 40546B90   INST:0xd7 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 60546B90 * INST:0xd7 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 00546B10   INST:0xd6 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0021 20546B10   INST:0xd6 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 00000C90   INST:0x19 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0031 40000C90   INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 00000012 TEX/VTX ADDR:36
>0003 80400000 TEX/VTX INST:0x1 COUNT:1
>0036 00000210   INST:0x10 RESOURCE_ID:2 SRC(GPR:0 REL:0)
>0037 F00D1000   DST(GPR:0 REL:0 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) LOD_BIAS:0 COORD_TYPE_X:1 COORD_TYPE_Y:1 COORD_TYPE_Z:1 COORD_TYPE_W:1
>0038 68800000   OFFSET_X:0 OFFSET_Y:0 OFFSET_Z:0 SAMPLER_ID:0 SRC(SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3)
>0039 00000000   
>0004 00000014 ALU ADDR:40 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0005 A00C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:4
>0040 00000000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 00400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 00000400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0043 20400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0044 00000800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 40400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 800000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0047 60400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0006 C0010000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  call void @llvm.AMDGPU.store.output(float %0, i32 4)
>  call void @llvm.AMDGPU.store.output(float %1, i32 5)
>  call void @llvm.AMDGPU.store.output(float %2, i32 6)
>  call void @llvm.AMDGPU.store.output(float %3, i32 7)
>  call void @llvm.AMDGPU.store.output(float %4, i32 8)
>  call void @llvm.AMDGPU.store.output(float %5, i32 9)
>  call void @llvm.AMDGPU.store.output(float %6, i32 10)
>  call void @llvm.AMDGPU.store.output(float %7, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 8 dw -- 3 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0003 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0004 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 00000000 CF ADDR:0
>0007 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.AMDGPU.load.const(i32 0)
>  %9 = call float @llvm.AMDGPU.mul(float %0, float %8)
>  %10 = call float @llvm.AMDGPU.load.const(i32 1)
>  %11 = call float @llvm.AMDGPU.mul(float %0, float %10)
>  %12 = call float @llvm.AMDGPU.load.const(i32 2)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 3)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 4)
>  %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9)
>  %18 = call float @llvm.AMDGPU.load.const(i32 5)
>  %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11)
>  %20 = call float @llvm.AMDGPU.load.const(i32 6)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 7)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 8)
>  %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 9)
>  %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 10)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 11)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 12)
>  %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 13)
>  %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 14)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 15)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  %40 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00)
>  %41 = call float @llvm.AMDIL.clamp.(float %5, float 0.000000e+00, float 1.000000e+00)
>  %42 = call float @llvm.AMDIL.clamp.(float %6, float 0.000000e+00, float 1.000000e+00)
>  %43 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %33, i32 4)
>  call void @llvm.AMDGPU.store.output(float %35, i32 5)
>  call void @llvm.AMDGPU.store.output(float %37, i32 6)
>  call void @llvm.AMDGPU.store.output(float %39, i32 7)
>  call void @llvm.AMDGPU.store.output(float %40, i32 8)
>  call void @llvm.AMDGPU.store.output(float %41, i32 9)
>  call void @llvm.AMDGPU.store.output(float %42, i32 10)
>  call void @llvm.AMDGPU.store.output(float %43, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T3_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T3_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 54 dw -- 4 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0540000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:22
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00600090 * INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 006280FE * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 206284FE * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 206284FE   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20628403   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 006284FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228803 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0044 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0052 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400400 TEX/VTX INST:0x1 COUNT:2
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 8C151001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:48 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 868D1002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:26 NUM:0 COMP:0 MODE:1)
>0010 00000014   ENDIAN:0 OFFSET:20
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV_SAT OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.AMDIL.clamp.(float %0, float 0.000000e+00, float 1.000000e+00)
>  %5 = call float @llvm.AMDIL.clamp.(float %1, float 0.000000e+00, float 1.000000e+00)
>  %6 = call float @llvm.AMDIL.clamp.(float %2, float 0.000000e+00, float 1.000000e+00)
>  %7 = call float @llvm.AMDIL.clamp.(float %3, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %4, i32 4)
>  call void @llvm.AMDGPU.store.output(float %5, i32 5)
>  call void @llvm.AMDGPU.store.output(float %6, i32 6)
>  call void @llvm.AMDGPU.store.output(float %7, i32 7)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
>Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T1_W %T1_Z %T1_Y %T1_X
>	%T1_X<def> = MOV %T1_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T1_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MOV %T1_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T1_W<def> = MOV %T1_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 30 dw -- 2 gprs ---------------------
>     C
>0000 00000003 ALU ADDR:6 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A02C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:12
>0006 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0007 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0008 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0009 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0010 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 40346B90   INST:0xd7 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 60346B90 * INST:0xd7 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 00346B10   INST:0xd6 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0017 20346B10   INST:0xd6 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 80200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0025 A0200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 00000801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 C0200C90   INST:0x19 DST(SEL:1 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 80000C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 E0200C90 * INST:0x19 DST(SEL:1 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 C0008000 EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0003 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0004 00000000 CF ADDR:0
>0005 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400400 TEX/VTX INST:0x1 COUNT:2
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 8C151001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:48 NUM:0 COMP:0 MODE:1)
>0006 00000008   ENDIAN:0 OFFSET:8
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 87961002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:30 NUM:0 COMP:0 MODE:1)
>0010 00000000   ENDIAN:0 OFFSET:0
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 16 dw -- 4 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400800 TEX/VTX INST:0x1 COUNT:3
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 8C151001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:48 NUM:0 COMP:0 MODE:1)
>0006 00000008   ENDIAN:0 OFFSET:8
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 88CD1002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0010 00000014   ENDIAN:0 OFFSET:20
>0011 00000000   
>0012 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0013 87961003   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:3 SEL_X:0 SEL_Y:1 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:30 NUM:0 COMP:0 MODE:1)
>0014 00000000   ENDIAN:0 OFFSET:0
>0015 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.AMDGPU.load.const(i32 0)
>  %9 = call float @llvm.AMDGPU.mul(float %0, float %8)
>  %10 = call float @llvm.AMDGPU.load.const(i32 1)
>  %11 = call float @llvm.AMDGPU.mul(float %0, float %10)
>  %12 = call float @llvm.AMDGPU.load.const(i32 2)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 3)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 4)
>  %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9)
>  %18 = call float @llvm.AMDGPU.load.const(i32 5)
>  %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11)
>  %20 = call float @llvm.AMDGPU.load.const(i32 6)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 7)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 8)
>  %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 9)
>  %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 10)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 11)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 12)
>  %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 13)
>  %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 14)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 15)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  %40 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00)
>  %41 = call float @llvm.AMDIL.clamp.(float %5, float 0.000000e+00, float 1.000000e+00)
>  %42 = call float @llvm.AMDIL.clamp.(float %6, float 0.000000e+00, float 1.000000e+00)
>  %43 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %33, i32 4)
>  call void @llvm.AMDGPU.store.output(float %35, i32 5)
>  call void @llvm.AMDGPU.store.output(float %37, i32 6)
>  call void @llvm.AMDGPU.store.output(float %39, i32 7)
>  call void @llvm.AMDGPU.store.output(float %40, i32 8)
>  call void @llvm.AMDGPU.store.output(float %41, i32 9)
>  call void @llvm.AMDGPU.store.output(float %42, i32 10)
>  call void @llvm.AMDGPU.store.output(float %43, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T3_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T3_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 54 dw -- 4 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0540000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:22
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00600090 * INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 006280FE * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 206284FE * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 206284FE   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20628403   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 006284FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228803 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0044 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0052 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>31.08.2012 14:34:48 axv b
>INFO: Starting integrated minecraft server version 1.3.2
>31.08.2012 14:34:48 axv b
>INFO: Generating keypair
>31.08.2012 14:34:48 net.minecraft.server.MinecraftServer d
>INFO: Preparing start region for level 0
>31.08.2012 14:34:49 et a
>INFO: V10lator[/127.0.0.1:0] logged in with entity id 245 at (-2146.6463584305047, 79.502303465839, -236.70192475283002)
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], FOG, PERSPECTIVE
>DCL OUT[0], COLOR
>DCL CONST[0..6]
>DCL TEMP[0], LOCAL
>DCL TEMP[1], LOCAL
>DCL TEMP[2], LOCAL
>IMM FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].w, CONST[6]
>  1: MAD_SAT TEMP[1].x, IN[0].xxxx, CONST[0].xxxx, CONST[0].yyyy
>  2: ADD TEMP[2].x, IMM[0].xxxx, -TEMP[1].xxxx
>  3: MUL TEMP[2].xyz, CONST[1].xyzz, TEMP[2].xxxx
>  4: MAD TEMP[0].xyz, CONST[6].xyzz, TEMP[1].xxxx, TEMP[2].xyzz
>  5: MOV_SAT OUT[0], TEMP[0]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  call void @llvm.AMDGPU.reserve.reg(i32 4)
>  call void @llvm.AMDGPU.reserve.reg(i32 5)
>  call void @llvm.AMDGPU.reserve.reg(i32 6)
>  call void @llvm.AMDGPU.reserve.reg(i32 7)
>  %0 = call float @llvm.R600.load.input(i32 8)
>  %1 = call float @llvm.R600.load.input(i32 9)
>  %2 = call float @llvm.R600.load.input(i32 10)
>  %3 = call float @llvm.R600.load.input(i32 11)
>  %4 = call float @llvm.AMDGPU.load.const(i32 27)
>  %5 = call float @llvm.AMDGPU.load.const(i32 0)
>  %6 = call float @llvm.AMDGPU.load.const(i32 1)
>  %7 = call float @llvm.AMDIL.mad.(float %0, float %5, float %6)
>  %8 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
>  %9 = fsub float -0.000000e+00, %8
>  %10 = fadd float 1.000000e+00, %9
>  %11 = call float @llvm.AMDGPU.load.const(i32 4)
>  %12 = call float @llvm.AMDGPU.mul(float %11, float %10)
>  %13 = call float @llvm.AMDGPU.load.const(i32 5)
>  %14 = call float @llvm.AMDGPU.mul(float %13, float %10)
>  %15 = call float @llvm.AMDGPU.load.const(i32 6)
>  %16 = call float @llvm.AMDGPU.mul(float %15, float %10)
>  %17 = call float @llvm.AMDGPU.load.const(i32 24)
>  %18 = call float @llvm.AMDIL.mad.(float %17, float %8, float %12)
>  %19 = call float @llvm.AMDGPU.load.const(i32 25)
>  %20 = call float @llvm.AMDIL.mad.(float %19, float %8, float %14)
>  %21 = call float @llvm.AMDGPU.load.const(i32 26)
>  %22 = call float @llvm.AMDIL.mad.(float %21, float %8, float %16)
>  %23 = call float @llvm.AMDIL.clamp.(float %18, float 0.000000e+00, float 1.000000e+00)
>  %24 = call float @llvm.AMDIL.clamp.(float %20, float 0.000000e+00, float 1.000000e+00)
>  %25 = call float @llvm.AMDIL.clamp.(float %22, float 0.000000e+00, float 1.000000e+00)
>  %26 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %23, i32 8)
>  call void @llvm.AMDGPU.store.output(float %24, i32 9)
>  call void @llvm.AMDGPU.store.output(float %25, i32 10)
>  call void @llvm.AMDGPU.store.output(float %26, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_X in %vreg0
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_X
>	%T2_X<def> = MULADD_eg %T2_X<kill>, %C0_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_X, 128, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	%T2_Y<def> = ADD %T2_Y<kill>, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MUL %C1_X, %T2_Y, pred:%PRED_SEL_OFF
>	%T2_W<def> = MUL %C1_Y, %T2_Y, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MULADD_eg %C6_X, %T2_X, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_W<def> = MULADD_eg %C6_Y, %T2_X, %T2_W<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MUL %C1_Z, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %C6_Z, %T2_X<kill>, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T3_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %C6_W, 1, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 52 dw -- 4 gprs ---------------------
>     C
>0000 40000003 ALU ADDR:6 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A0580000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:23
>0006 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0007 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0008 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0009 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0010 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 40546B90   INST:0xd7 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 60546B90 * INST:0xd7 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 00546B10   INST:0xd6 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0017 20546B10   INST:0xd6 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 801000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0023 00428480 * INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:128 REL:0 CHAN:1 NEG:0)
>0024 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 80400C90 * INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 000010FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:1) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 20400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 800000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 40400C90 * INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 811FC4FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 20400010 * INST:0x0 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 009FC081   SRC0(SEL:129 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0033 40400090   INST:0x1 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 809FC481   SRC0(SEL:129 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0035 60400090 * INST:0x1 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 00804881   SRC0(SEL:129 REL:0 CHAN:2 NEG:0) SRC1(SEL:2 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0037 20400090   INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 00004086   SRC0(SEL:134 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 404288FE   INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0040 80004486   SRC0(SEL:134 REL:0 CHAN:1 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0041 60428CFE * INST:0x14 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:3 NEG:0)
>0042 80004886   SRC0(SEL:134 REL:0 CHAN:2 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 006284FE * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0044 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 80000C86   SRC0(SEL:134 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 C0010000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0003 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0004 00000000 CF ADDR:0
>0005 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], FOG
>DCL CONST[0..7]
>DCL TEMP[0..1]
>IMM FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MUL TEMP[0], IN[0].xxxx, CONST[4]
>  5: MAD TEMP[0], IN[0].yyyy, CONST[5], TEMP[0]
>  6: MAD TEMP[0], IN[0].zzzz, CONST[6], TEMP[0]
>  7: MAD TEMP[0], IN[0].wwww, CONST[7], TEMP[0]
>  8: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  9: RSQ TEMP[1].x, TEMP[1]
> 10: RCP TEMP[1].x, TEMP[1]
> 11: MOV TEMP[1].yzw, IMM[0].xxxy
> 12: MOV OUT[1], TEMP[1]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.AMDGPU.load.const(i32 0)
>  %5 = call float @llvm.AMDGPU.mul(float %0, float %4)
>  %6 = call float @llvm.AMDGPU.load.const(i32 1)
>  %7 = call float @llvm.AMDGPU.mul(float %0, float %6)
>  %8 = call float @llvm.AMDGPU.load.const(i32 2)
>  %9 = call float @llvm.AMDGPU.mul(float %0, float %8)
>  %10 = call float @llvm.AMDGPU.load.const(i32 3)
>  %11 = call float @llvm.AMDGPU.mul(float %0, float %10)
>  %12 = call float @llvm.AMDGPU.load.const(i32 4)
>  %13 = call float @llvm.AMDIL.mad.(float %1, float %12, float %5)
>  %14 = call float @llvm.AMDGPU.load.const(i32 5)
>  %15 = call float @llvm.AMDIL.mad.(float %1, float %14, float %7)
>  %16 = call float @llvm.AMDGPU.load.const(i32 6)
>  %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9)
>  %18 = call float @llvm.AMDGPU.load.const(i32 7)
>  %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11)
>  %20 = call float @llvm.AMDGPU.load.const(i32 8)
>  %21 = call float @llvm.AMDIL.mad.(float %2, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 9)
>  %23 = call float @llvm.AMDIL.mad.(float %2, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 10)
>  %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 11)
>  %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 12)
>  %29 = call float @llvm.AMDIL.mad.(float %3, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 13)
>  %31 = call float @llvm.AMDIL.mad.(float %3, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 14)
>  %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 15)
>  %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 16)
>  %37 = call float @llvm.AMDGPU.mul(float %0, float %36)
>  %38 = call float @llvm.AMDGPU.load.const(i32 17)
>  %39 = call float @llvm.AMDGPU.mul(float %0, float %38)
>  %40 = call float @llvm.AMDGPU.load.const(i32 18)
>  %41 = call float @llvm.AMDGPU.mul(float %0, float %40)
>  %42 = call float @llvm.AMDGPU.load.const(i32 19)
>  %43 = call float @llvm.AMDGPU.mul(float %0, float %42)
>  %44 = call float @llvm.AMDGPU.load.const(i32 20)
>  %45 = call float @llvm.AMDIL.mad.(float %1, float %44, float %37)
>  %46 = call float @llvm.AMDGPU.load.const(i32 21)
>  %47 = call float @llvm.AMDIL.mad.(float %1, float %46, float %39)
>  %48 = call float @llvm.AMDGPU.load.const(i32 22)
>  %49 = call float @llvm.AMDIL.mad.(float %1, float %48, float %41)
>  %50 = call float @llvm.AMDGPU.load.const(i32 23)
>  %51 = call float @llvm.AMDIL.mad.(float %1, float %50, float %43)
>  %52 = call float @llvm.AMDGPU.load.const(i32 24)
>  %53 = call float @llvm.AMDIL.mad.(float %2, float %52, float %45)
>  %54 = call float @llvm.AMDGPU.load.const(i32 25)
>  %55 = call float @llvm.AMDIL.mad.(float %2, float %54, float %47)
>  %56 = call float @llvm.AMDGPU.load.const(i32 26)
>  %57 = call float @llvm.AMDIL.mad.(float %2, float %56, float %49)
>  %58 = call float @llvm.AMDGPU.load.const(i32 27)
>  %59 = call float @llvm.AMDIL.mad.(float %2, float %58, float %51)
>  %60 = call float @llvm.AMDGPU.load.const(i32 28)
>  %61 = call float @llvm.AMDIL.mad.(float %3, float %60, float %53)
>  %62 = call float @llvm.AMDGPU.load.const(i32 29)
>  %63 = call float @llvm.AMDIL.mad.(float %3, float %62, float %55)
>  %64 = call float @llvm.AMDGPU.load.const(i32 30)
>  %65 = call float @llvm.AMDIL.mad.(float %3, float %64, float %57)
>  %66 = call float @llvm.AMDGPU.load.const(i32 31)
>  %67 = call float @llvm.AMDIL.mad.(float %3, float %66, float %59)
>  %68 = insertelement <4 x float> undef, float %61, i32 0
>  %69 = insertelement <4 x float> %68, float %63, i32 1
>  %70 = insertelement <4 x float> %69, float %65, i32 2
>  %71 = insertelement <4 x float> %70, float 0.000000e+00, i32 3
>  %72 = insertelement <4 x float> undef, float %61, i32 0
>  %73 = insertelement <4 x float> %72, float %63, i32 1
>  %74 = insertelement <4 x float> %73, float %65, i32 2
>  %75 = insertelement <4 x float> %74, float 0.000000e+00, i32 3
>  %76 = call float @llvm.AMDGPU.dp4(<4 x float> %71, <4 x float> %75)
>  %77 = call float @llvm.AMDIL.fabs.(float %76)
>  %78 = call float @llvm.AMDGPU.rsq(float %77)
>  %79 = call float @llvm.AMDGPU.rcp(float %78)
>  call void @llvm.AMDGPU.store.output(float %29, i32 4)
>  call void @llvm.AMDGPU.store.output(float %31, i32 5)
>  call void @llvm.AMDGPU.store.output(float %33, i32 6)
>  call void @llvm.AMDGPU.store.output(float %35, i32 7)
>  call void @llvm.AMDGPU.store.output(float %79, i32 8)
>  call void @llvm.AMDGPU.store.output(float 0.000000e+00, i32 9)
>  call void @llvm.AMDGPU.store.output(float 0.000000e+00, i32 10)
>  call void @llvm.AMDGPU.store.output(float 1.000000e+00, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) readnone
>
>declare float @llvm.AMDIL.fabs.(float) readnone
>
>declare float @llvm.AMDGPU.rsq(float) readnone
>
>declare float @llvm.AMDGPU.rcp(float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T1_W %T1_Z %T1_Y %T1_X
>	%T2_X<def> = MUL %T1_X, %C4_X, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_Y, %C5_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_Z, %C6_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T0_X<def> = MULADD_eg %T1_W, %C7_X, %T2_X<kill>, pred:%PRED_SEL_OFF, %T0_XYZW<imp-def>
>	%T2_X<def> = MUL %T1_X, %C4_Z, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_Y, %C5_Z, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_Z, %C6_Z, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MUL %T1_X, %C4_Y, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MULADD_eg %T1_Y, %C5_Y, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MULADD_eg %T1_W, %C7_Z, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_Y, %C1_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C6_Y, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 0.000000e+00
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T0_W<def> = MOV %T2_Z, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T2_W<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %T2_Y<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T2_Y<def> = MULADD_eg %T1_W, %C7_Y, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_Z, %C2_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_W, %C3_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_W<def> = MULADD_eg %T1_Y, %C1_Z, %T2_W<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_Y, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T0_Y<def> = MOV %T2_Y<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T2_W<def> = MULADD_eg %T1_Z, %C2_Z, %T2_W<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_X<kill>, pred:%PRED_SEL_OFF
>	BUNDLE %T3_X<imp-def>, %T3_Y<imp-def>, %T3_Z<imp-def>, %T3_W<imp-def>, %T0_X<imp-use>, %T0_Y<imp-use>, %T0_Z<imp-use>, %T0_W<imp-use>
>	  * %T3_X<def> = DOT4_eg %T0_X, %T0_X, 32; flags: 
>	  * %T3_Y<def> = DOT4_eg %T0_Y, %T0_Y, 40; flags: 
>	  * %T3_Z<def> = DOT4_eg %T0_Z, %T0_Z, 40; flags: 
>	  * %T3_W<def> = DOT4_eg %T0_W, %T0_W, 8; flags: 
>	%T1_X<def> = MOV %T2_X<kill>, 0, pred:%noreg
>	%T2_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T2_W<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T3_X<kill>, 256, pred:%PRED_SEL_OFF
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = RECIPSQRT_CLAMPED_eg %T2_Y<kill>, pred:%PRED_SEL_OFF
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T2_X<imp-use>, %PRED_SEL_OFF<imp-use>
>	  * %T2_X<def> = RECIP_IEEE_cm %T2_X, pred:%PRED_SEL_OFF, 0; flags: 
>	  * %T2_Y<def> = RECIP_IEEE_cm %T2_X<internal>, pred:%PRED_SEL_OFF, 0; flags: 
>	  * %T2_Z<def> = RECIP_IEEE_cm %T2_X<internal>, pred:%PRED_SEL_OFF, 0; flags: 
>	  * %T2_W<def> = RECIP_IEEE_cm %T2_X<internal>, pred:%PRED_SEL_OFF, 0; flags: 
>	%T2_W<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	%T2_Y<def> = MOV %T2_Z, 0, pred:%noreg
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 100 dw -- 4 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0B00000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:45
>0010 80108001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:132 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00400090 * INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 8010A401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:133 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 004280FE * INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 8010C801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:134 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0015 004280FE * INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 8010EC01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:135 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 000280FE * INST:0x14 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0018 81108001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:132 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0019 00400090 * INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 8110A401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:133 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 004280FE * INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0022 0110C801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:134 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 004280FE   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0024 80908001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:132 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 20400090 * INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 0110EC01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:135 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 204280FE   INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0028 8090A401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:133 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 404284FE * INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0030 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 00400090 * INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 004280FE * INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0034 0090C801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:134 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00628802   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:2 NEG:0)
>0036 00900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0037 20600090   INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 800000F8   SRC0(SEL:248 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0039 40400C90 * INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0040 800008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0041 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 0090EC01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:135 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0043 20428003   INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:0 NEG:0)
>0044 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 40000C90   INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0047 60400090 * INST:0x1 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0049 00628403 * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0050 80104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 00428002 * INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:0 NEG:0)
>0052 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0053 004280FE   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0054 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0055 60428C02 * INST:0x14 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:3 NEG:0)
>0056 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0057 00628003   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:0 NEG:0)
>0058 80000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0059 20000C90 * INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0060 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0061 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0062 01902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0063 204280FE   INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0064 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0065 60428C02 * INST:0x14 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:3 NEG:0)
>0066 80906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0067 20228003 * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:0 NEG:0)
>0068 00000000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0069 00605F10   INST:0xbe DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0070 00800400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0071 20605F00   INST:0xbe DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0072 01000800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0073 40605F00   INST:0xbe DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0074 81800C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0075 60605F00 * INST:0xbe DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0076 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0077 00200C90 * INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0078 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0079 00428402   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:1 NEG:0)
>0080 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0081 20400C91   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:1 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0082 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0083 40228C02 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:3 NEG:0)
>0084 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0085 00404390   INST:0x87 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0086 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0087 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0088 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0089 00404310 * INST:0x86 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0090 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0091 20404310   INST:0x86 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0092 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0093 40404310   INST:0x86 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0094 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0095 60404310 * INST:0x86 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0096 000008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0097 20400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0098 800000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0099 60400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000B20 EXPORT SWIZ_X:0 SWIZ_Y:4 SWIZ_Z:4 SWIZ_W:5 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 8 dw -- 2 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400000 TEX/VTX INST:0x1 COUNT:1
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 8C151001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:48 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.AMDGPU.load.const(i32 0)
>  %9 = call float @llvm.AMDGPU.mul(float %0, float %8)
>  %10 = call float @llvm.AMDGPU.load.const(i32 1)
>  %11 = call float @llvm.AMDGPU.mul(float %0, float %10)
>  %12 = call float @llvm.AMDGPU.load.const(i32 2)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 3)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 4)
>  %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9)
>  %18 = call float @llvm.AMDGPU.load.const(i32 5)
>  %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11)
>  %20 = call float @llvm.AMDGPU.load.const(i32 6)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 7)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 8)
>  %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 9)
>  %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 10)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 11)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 12)
>  %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 13)
>  %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 14)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 15)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  %40 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00)
>  %41 = call float @llvm.AMDIL.clamp.(float %5, float 0.000000e+00, float 1.000000e+00)
>  %42 = call float @llvm.AMDIL.clamp.(float %6, float 0.000000e+00, float 1.000000e+00)
>  %43 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %33, i32 4)
>  call void @llvm.AMDGPU.store.output(float %35, i32 5)
>  call void @llvm.AMDGPU.store.output(float %37, i32 6)
>  call void @llvm.AMDGPU.store.output(float %39, i32 7)
>  call void @llvm.AMDGPU.store.output(float %40, i32 8)
>  call void @llvm.AMDGPU.store.output(float %41, i32 9)
>  call void @llvm.AMDGPU.store.output(float %42, i32 10)
>  call void @llvm.AMDGPU.store.output(float %43, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T3_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T3_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 54 dw -- 4 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0540000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:22
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00600090 * INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 006280FE * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 206284FE * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 206284FE   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20628403   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 006284FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228803 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0044 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0052 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.AMDGPU.load.const(i32 0)
>  %9 = call float @llvm.AMDGPU.mul(float %0, float %8)
>  %10 = call float @llvm.AMDGPU.load.const(i32 1)
>  %11 = call float @llvm.AMDGPU.mul(float %0, float %10)
>  %12 = call float @llvm.AMDGPU.load.const(i32 2)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 3)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 4)
>  %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9)
>  %18 = call float @llvm.AMDGPU.load.const(i32 5)
>  %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11)
>  %20 = call float @llvm.AMDGPU.load.const(i32 6)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 7)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 8)
>  %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 9)
>  %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 10)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 11)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 12)
>  %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 13)
>  %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 14)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 15)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  call void @llvm.AMDGPU.store.output(float %33, i32 4)
>  call void @llvm.AMDGPU.store.output(float %35, i32 5)
>  call void @llvm.AMDGPU.store.output(float %37, i32 6)
>  call void @llvm.AMDGPU.store.output(float %39, i32 7)
>  call void @llvm.AMDGPU.store.output(float %4, i32 8)
>  call void @llvm.AMDGPU.store.output(float %5, i32 9)
>  call void @llvm.AMDGPU.store.output(float %6, i32 10)
>  call void @llvm.AMDGPU.store.output(float %7, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T3_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T3_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T3_X<kill>, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 46 dw -- 4 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0440000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:18
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00600090 * INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 006280FE * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 206284FE * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 206284FE   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20628403   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 006284FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228803 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0044 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0045 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL OUT[0], COLOR
>DCL CONST[0..3]
>  0: MOV_SAT OUT[0], CONST[3]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.AMDGPU.load.const(i32 12)
>  %1 = call float @llvm.AMDGPU.load.const(i32 13)
>  %2 = call float @llvm.AMDGPU.load.const(i32 14)
>  %3 = call float @llvm.AMDGPU.load.const(i32 15)
>  %4 = call float @llvm.AMDIL.clamp.(float %0, float 0.000000e+00, float 1.000000e+00)
>  %5 = call float @llvm.AMDIL.clamp.(float %1, float 0.000000e+00, float 1.000000e+00)
>  %6 = call float @llvm.AMDIL.clamp.(float %2, float 0.000000e+00, float 1.000000e+00)
>  %7 = call float @llvm.AMDIL.clamp.(float %3, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %4, i32 4)
>  call void @llvm.AMDGPU.store.output(float %5, i32 5)
>  call void @llvm.AMDGPU.store.output(float %6, i32 6)
>  call void @llvm.AMDGPU.store.output(float %7, i32 7)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>	%T1_X<def> = MOV %C3_X, 1, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %C3_Y, 1, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MOV %C3_Z, 1, pred:%PRED_SEL_OFF
>	%T1_W<def> = MOV %C3_W, 1, pred:%PRED_SEL_OFF
>	RETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 14 dw -- 2 gprs ---------------------
>     C
>0000 40000003 ALU ADDR:6 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A00C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:4
>0006 00000083   SRC0(SEL:131 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0007 80200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0008 00000483   SRC0(SEL:131 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0009 A0200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0010 00000883   SRC0(SEL:131 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 C0200C90   INST:0x19 DST(SEL:1 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80000C83   SRC0(SEL:131 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 E0200C90 * INST:0x19 DST(SEL:1 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 C0008000 EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0003 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0004 00000000 CF ADDR:0
>0005 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.AMDGPU.load.const(i32 0)
>  %5 = call float @llvm.AMDGPU.mul(float %0, float %4)
>  %6 = call float @llvm.AMDGPU.load.const(i32 1)
>  %7 = call float @llvm.AMDGPU.mul(float %0, float %6)
>  %8 = call float @llvm.AMDGPU.load.const(i32 2)
>  %9 = call float @llvm.AMDGPU.mul(float %0, float %8)
>  %10 = call float @llvm.AMDGPU.load.const(i32 3)
>  %11 = call float @llvm.AMDGPU.mul(float %0, float %10)
>  %12 = call float @llvm.AMDGPU.load.const(i32 4)
>  %13 = call float @llvm.AMDIL.mad.(float %1, float %12, float %5)
>  %14 = call float @llvm.AMDGPU.load.const(i32 5)
>  %15 = call float @llvm.AMDIL.mad.(float %1, float %14, float %7)
>  %16 = call float @llvm.AMDGPU.load.const(i32 6)
>  %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9)
>  %18 = call float @llvm.AMDGPU.load.const(i32 7)
>  %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11)
>  %20 = call float @llvm.AMDGPU.load.const(i32 8)
>  %21 = call float @llvm.AMDIL.mad.(float %2, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 9)
>  %23 = call float @llvm.AMDIL.mad.(float %2, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 10)
>  %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 11)
>  %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 12)
>  %29 = call float @llvm.AMDIL.mad.(float %3, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 13)
>  %31 = call float @llvm.AMDIL.mad.(float %3, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 14)
>  %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 15)
>  %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27)
>  call void @llvm.AMDGPU.store.output(float %29, i32 4)
>  call void @llvm.AMDGPU.store.output(float %31, i32 5)
>  call void @llvm.AMDGPU.store.output(float %33, i32 6)
>  call void @llvm.AMDGPU.store.output(float %35, i32 7)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
>Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T1_W %T1_Z %T1_Y %T1_X
>	%T2_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_Y, %C1_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_Z, %C2_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_W, %C3_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MULADD_eg %T1_W, %C3_Y, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T2_X<kill>, 0, pred:%noreg
>	%T2_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T2_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T2_X<kill>, pred:%PRED_SEL_OFF
>	RETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 46 dw -- 3 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0440000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:18
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00400090 * INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 004280FE * INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 004280FE   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20400090 * INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 004280FE   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 204284FE * INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 204284FE   INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40400090 * INST:0x1 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 404288FE * INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20428402   INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 404288FE * INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 004284FE   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228802 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:2 NEG:0)
>0044 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0045 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0004000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..3]
>DCL TEMP[0], LOCAL
>DCL TEMP[1], LOCAL
>DCL TEMP[2], LOCAL
>DCL TEMP[3], LOCAL
>IMM FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: TXP TEMP[0], IN[2].xyyw, SAMP[0], 2D
>  1: MUL TEMP[0], TEMP[0], IN[0]
>  2: MOV TEMP[1].w, TEMP[0].wwww
>  3: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  4: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].xxxx
>  5: MUL TEMP[3].xyz, CONST[2].xyzz, TEMP[3].xxxx
>  6: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
>  7: MOV_SAT OUT[0], TEMP[1]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  call void @llvm.AMDGPU.reserve.reg(i32 4)
>  call void @llvm.AMDGPU.reserve.reg(i32 5)
>  call void @llvm.AMDGPU.reserve.reg(i32 6)
>  call void @llvm.AMDGPU.reserve.reg(i32 7)
>  %0 = call float @llvm.R600.load.input(i32 8)
>  %1 = call float @llvm.R600.load.input(i32 9)
>  %2 = call float @llvm.R600.load.input(i32 10)
>  %3 = call float @llvm.R600.load.input(i32 11)
>  %4 = call float @llvm.R600.load.input(i32 12)
>  %5 = call float @llvm.R600.load.input(i32 13)
>  %6 = call float @llvm.R600.load.input(i32 14)
>  %7 = call float @llvm.R600.load.input(i32 15)
>  %8 = call float @llvm.R600.load.input(i32 16)
>  %9 = call float @llvm.R600.load.input(i32 17)
>  %10 = call float @llvm.R600.load.input(i32 18)
>  %11 = call float @llvm.R600.load.input(i32 19)
>  %12 = call float @llvm.AMDGPU.div(float %8, float %11)
>  %13 = call float @llvm.AMDGPU.div(float %9, float %11)
>  %14 = call float @llvm.AMDGPU.div(float %9, float %11)
>  %15 = insertelement <4 x float> undef, float %12, i32 0
>  %16 = insertelement <4 x float> %15, float %13, i32 1
>  %17 = insertelement <4 x float> %16, float %14, i32 2
>  %18 = insertelement <4 x float> %17, float 1.000000e+00, i32 3
>  %19 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %18, i32 0, i32 2)
>  %20 = extractelement <4 x float> %19, i32 0
>  %21 = extractelement <4 x float> %19, i32 1
>  %22 = extractelement <4 x float> %19, i32 2
>  %23 = extractelement <4 x float> %19, i32 3
>  %24 = call float @llvm.AMDGPU.mul(float %20, float %0)
>  %25 = call float @llvm.AMDGPU.mul(float %21, float %1)
>  %26 = call float @llvm.AMDGPU.mul(float %22, float %2)
>  %27 = call float @llvm.AMDGPU.mul(float %23, float %3)
>  %28 = call float @llvm.AMDGPU.load.const(i32 4)
>  %29 = call float @llvm.AMDGPU.load.const(i32 5)
>  %30 = call float @llvm.AMDIL.mad.(float %4, float %28, float %29)
>  %31 = call float @llvm.AMDIL.clamp.(float %30, float 0.000000e+00, float 1.000000e+00)
>  %32 = fsub float -0.000000e+00, %31
>  %33 = fadd float 1.000000e+00, %32
>  %34 = call float @llvm.AMDGPU.load.const(i32 8)
>  %35 = call float @llvm.AMDGPU.mul(float %34, float %33)
>  %36 = call float @llvm.AMDGPU.load.const(i32 9)
>  %37 = call float @llvm.AMDGPU.mul(float %36, float %33)
>  %38 = call float @llvm.AMDGPU.load.const(i32 10)
>  %39 = call float @llvm.AMDGPU.mul(float %38, float %33)
>  %40 = call float @llvm.AMDIL.mad.(float %24, float %31, float %35)
>  %41 = call float @llvm.AMDIL.mad.(float %25, float %31, float %37)
>  %42 = call float @llvm.AMDIL.mad.(float %26, float %31, float %39)
>  %43 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %44 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %45 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %46 = call float @llvm.AMDIL.clamp.(float %27, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %43, i32 8)
>  call void @llvm.AMDGPU.store.output(float %44, i32 9)
>  call void @llvm.AMDGPU.store.output(float %45, i32 10)
>  call void @llvm.AMDGPU.store.output(float %46, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.div(float, float) readnone
>
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T4_W in %vreg0, %T4_Y in %vreg1, %T4_X in %vreg2, %T3_X in %vreg3, %T2_W in %vreg4, %T2_Z in %vreg5, %T2_Y in %vreg6, %T2_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T4_W %T4_Y %T4_X %T3_X %T2_W %T2_Z %T2_Y %T2_X
>	%T3_Z<def> = RECIP_IEEE_eg %T4_W<kill>, pred:%PRED_SEL_OFF
>	%T0_X<def> = MUL %T4_X<kill>, %T3_Z, pred:%PRED_SEL_OFF, %T0_XYZW<imp-def>
>	%T3_Y<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	%T0_W<def> = MOV %T3_Y, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T3_Z<def> = MUL %T4_Y<kill>, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %T3_Z, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T3_X<def> = MULADD_eg %T3_X<kill>, %C1_X, %C1_Y, pred:%PRED_SEL_OFF
>	%T0_Y<def> = MOV %T3_Z<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_XYZW<def> = TEX_SAMPLE %T0_XYZW<kill>, 0, 2
>	%T3_X<def> = MOV %T3_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MOV %T3_X, 128, pred:%PRED_SEL_OFF
>	%T3_Y<def> = ADD %T3_Z<kill>, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MUL %T0_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %C2_X, %T3_Y, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T2_X<kill>, %T3_X, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MUL %T0_Y, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %C2_Y, %T3_Y, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MULADD_eg %T2_Y<kill>, %T3_X, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MUL %T0_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %C2_Z, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MULADD_eg %T2_Z<kill>, %T3_X<kill>, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MUL %T0_W, %T2_W<kill>, pred:%PRED_SEL_OFF, %T0_XYZW<imp-use,kill>
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 114 dw -- 5 gprs ---------------------
>     C
>0000 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A07C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:32
>0010 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0011 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0013 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 40546B90   INST:0xd7 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 60546B90 * INST:0xd7 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 00546B10   INST:0xd6 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0021 20546B10   INST:0xd6 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 00382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0031 40746B90   INST:0xd7 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 80382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 60746B90 * INST:0xd7 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00746B10   INST:0xd6 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 00382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0037 20746B10   INST:0xd6 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0040 80382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0041 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 00384400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0043 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0044 00384000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00384400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 40946B90   INST:0xd7 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 80384000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0049 60946B90 * INST:0xd7 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 00384400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0051 00946B10   INST:0xd6 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0052 00384000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0053 20946B10   INST:0xd6 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0054 00384400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0055 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0056 80384000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0057 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0058 80000C04   SRC0(SEL:4 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0059 40604310 * INST:0x86 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0060 011FC004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0061 00000090   INST:0x1 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0062 800000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0063 20600C90 * INST:0x19 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0064 01006404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:3 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0065 40600090   INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0066 800004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0067 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0068 00102003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0069 00628481   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:129 REL:0 CHAN:1 NEG:0)
>0070 000008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0071 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0072 800008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0073 40000C90 * INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 00000026 TEX/VTX ADDR:76
>0003 80400000 TEX/VTX INST:0x1 COUNT:1
>0076 00000210   INST:0x10 RESOURCE_ID:2 SRC(GPR:0 REL:0)
>0077 F00D1000   DST(GPR:0 REL:0 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) LOD_BIAS:0 COORD_TYPE_X:1 COORD_TYPE_Y:1 COORD_TYPE_Z:1 COORD_TYPE_W:1
>0078 68800000   OFFSET_X:0 OFFSET_Y:0 OFFSET_Z:0 SAMPLER_ID:0 SRC(SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3)
>0079 00000000   
>0004 40000028 ALU ADDR:80 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0005 A0400000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:17
>0080 80000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0081 80600C90 * INST:0x19 DST(SEL:3 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0082 800010FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:1) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0083 40600C90 * INST:0x19 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0084 00004000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0085 00400090   INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0086 808068FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:3 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0087 20600010 * INST:0x0 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0088 809FC082   SRC0(SEL:130 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0089 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0090 00006002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:3 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0091 004288FE   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0092 80804400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:2 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0093 20400090 * INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0094 80806482   SRC0(SEL:130 REL:0 CHAN:1 NEG:0) SRC1(SEL:3 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0095 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0096 00006402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:3 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0097 204288FE   INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0098 81004800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:2 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0099 40400090 * INST:0x1 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0100 80806882   SRC0(SEL:130 REL:0 CHAN:2 NEG:0) SRC1(SEL:3 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0101 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0102 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0103 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0104 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0105 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0106 00006802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:3 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0107 404284FE   INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0108 81804C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:2 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0109 60400090 * INST:0x1 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0110 000008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0111 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0112 80000CFE   SRC0(SEL:254 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0113 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0006 C0010000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0..1]
>IMM FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MUL TEMP[0], IN[0].xxxx, CONST[4]
>  6: MAD TEMP[0], IN[0].yyyy, CONST[5], TEMP[0]
>  7: MAD TEMP[0], IN[0].zzzz, CONST[6], TEMP[0]
>  8: MAD TEMP[0], IN[0].wwww, CONST[7], TEMP[0]
>  9: DP3 TEMP[1].x, TEMP[0], TEMP[0]
> 10: RSQ TEMP[1].x, TEMP[1]
> 11: RCP TEMP[1].x, TEMP[1]
> 12: MOV TEMP[1].yzw, IMM[0].xxxy
> 13: MOV OUT[3], IN[2]
> 14: MOV OUT[2], TEMP[1]
> 15: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.R600.load.input(i32 12)
>  %9 = call float @llvm.R600.load.input(i32 13)
>  %10 = call float @llvm.R600.load.input(i32 14)
>  %11 = call float @llvm.R600.load.input(i32 15)
>  %12 = call float @llvm.AMDGPU.load.const(i32 0)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 1)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 2)
>  %17 = call float @llvm.AMDGPU.mul(float %0, float %16)
>  %18 = call float @llvm.AMDGPU.load.const(i32 3)
>  %19 = call float @llvm.AMDGPU.mul(float %0, float %18)
>  %20 = call float @llvm.AMDGPU.load.const(i32 4)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 5)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 6)
>  %25 = call float @llvm.AMDIL.mad.(float %1, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 7)
>  %27 = call float @llvm.AMDIL.mad.(float %1, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 8)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 9)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 10)
>  %33 = call float @llvm.AMDIL.mad.(float %2, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 11)
>  %35 = call float @llvm.AMDIL.mad.(float %2, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 12)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 13)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  %40 = call float @llvm.AMDGPU.load.const(i32 14)
>  %41 = call float @llvm.AMDIL.mad.(float %3, float %40, float %33)
>  %42 = call float @llvm.AMDGPU.load.const(i32 15)
>  %43 = call float @llvm.AMDIL.mad.(float %3, float %42, float %35)
>  %44 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00)
>  %45 = call float @llvm.AMDIL.clamp.(float %5, float 0.000000e+00, float 1.000000e+00)
>  %46 = call float @llvm.AMDIL.clamp.(float %6, float 0.000000e+00, float 1.000000e+00)
>  %47 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
>  %48 = call float @llvm.AMDGPU.load.const(i32 16)
>  %49 = call float @llvm.AMDGPU.mul(float %0, float %48)
>  %50 = call float @llvm.AMDGPU.load.const(i32 17)
>  %51 = call float @llvm.AMDGPU.mul(float %0, float %50)
>  %52 = call float @llvm.AMDGPU.load.const(i32 18)
>  %53 = call float @llvm.AMDGPU.mul(float %0, float %52)
>  %54 = call float @llvm.AMDGPU.load.const(i32 19)
>  %55 = call float @llvm.AMDGPU.mul(float %0, float %54)
>  %56 = call float @llvm.AMDGPU.load.const(i32 20)
>  %57 = call float @llvm.AMDIL.mad.(float %1, float %56, float %49)
>  %58 = call float @llvm.AMDGPU.load.const(i32 21)
>  %59 = call float @llvm.AMDIL.mad.(float %1, float %58, float %51)
>  %60 = call float @llvm.AMDGPU.load.const(i32 22)
>  %61 = call float @llvm.AMDIL.mad.(float %1, float %60, float %53)
>  %62 = call float @llvm.AMDGPU.load.const(i32 23)
>  %63 = call float @llvm.AMDIL.mad.(float %1, float %62, float %55)
>  %64 = call float @llvm.AMDGPU.load.const(i32 24)
>  %65 = call float @llvm.AMDIL.mad.(float %2, float %64, float %57)
>  %66 = call float @llvm.AMDGPU.load.const(i32 25)
>  %67 = call float @llvm.AMDIL.mad.(float %2, float %66, float %59)
>  %68 = call float @llvm.AMDGPU.load.const(i32 26)
>  %69 = call float @llvm.AMDIL.mad.(float %2, float %68, float %61)
>  %70 = call float @llvm.AMDGPU.load.const(i32 27)
>  %71 = call float @llvm.AMDIL.mad.(float %2, float %70, float %63)
>  %72 = call float @llvm.AMDGPU.load.const(i32 28)
>  %73 = call float @llvm.AMDIL.mad.(float %3, float %72, float %65)
>  %74 = call float @llvm.AMDGPU.load.const(i32 29)
>  %75 = call float @llvm.AMDIL.mad.(float %3, float %74, float %67)
>  %76 = call float @llvm.AMDGPU.load.const(i32 30)
>  %77 = call float @llvm.AMDIL.mad.(float %3, float %76, float %69)
>  %78 = call float @llvm.AMDGPU.load.const(i32 31)
>  %79 = call float @llvm.AMDIL.mad.(float %3, float %78, float %71)
>  %80 = insertelement <4 x float> undef, float %73, i32 0
>  %81 = insertelement <4 x float> %80, float %75, i32 1
>  %82 = insertelement <4 x float> %81, float %77, i32 2
>  %83 = insertelement <4 x float> %82, float 0.000000e+00, i32 3
>  %84 = insertelement <4 x float> undef, float %73, i32 0
>  %85 = insertelement <4 x float> %84, float %75, i32 1
>  %86 = insertelement <4 x float> %85, float %77, i32 2
>  %87 = insertelement <4 x float> %86, float 0.000000e+00, i32 3
>  %88 = call float @llvm.AMDGPU.dp4(<4 x float> %83, <4 x float> %87)
>  %89 = call float @llvm.AMDIL.fabs.(float %88)
>  %90 = call float @llvm.AMDGPU.rsq(float %89)
>  %91 = call float @llvm.AMDGPU.rcp(float %90)
>  call void @llvm.AMDGPU.store.output(float %37, i32 4)
>  call void @llvm.AMDGPU.store.output(float %39, i32 5)
>  call void @llvm.AMDGPU.store.output(float %41, i32 6)
>  call void @llvm.AMDGPU.store.output(float %43, i32 7)
>  call void @llvm.AMDGPU.store.output(float %44, i32 8)
>  call void @llvm.AMDGPU.store.output(float %45, i32 9)
>  call void @llvm.AMDGPU.store.output(float %46, i32 10)
>  call void @llvm.AMDGPU.store.output(float %47, i32 11)
>  call void @llvm.AMDGPU.store.output(float %91, i32 12)
>  call void @llvm.AMDGPU.store.output(float 0.000000e+00, i32 13)
>  call void @llvm.AMDGPU.store.output(float 0.000000e+00, i32 14)
>  call void @llvm.AMDGPU.store.output(float 1.000000e+00, i32 15)
>  call void @llvm.AMDGPU.store.output(float %8, i32 16)
>  call void @llvm.AMDGPU.store.output(float %9, i32 17)
>  call void @llvm.AMDGPU.store.output(float %10, i32 18)
>  call void @llvm.AMDGPU.store.output(float %11, i32 19)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) readnone
>
>declare float @llvm.AMDIL.fabs.(float) readnone
>
>declare float @llvm.AMDGPU.rsq(float) readnone
>
>declare float @llvm.AMDGPU.rcp(float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T3_W in %vreg0, %T3_Z in %vreg1, %T3_Y in %vreg2, %T3_X in %vreg3, %T2_W in %vreg4, %T2_Z in %vreg5, %T2_Y in %vreg6, %T2_X in %vreg7, %T1_W in %vreg8, %T1_Z in %vreg9, %T1_Y in %vreg10, %T1_X in %vreg11
>Function Live Outs: %T4_W %T4_Z %T4_Y %T4_X %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T4_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T4_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T4_Z<def> = MOV %T3_Z<kill>, 0, pred:%noreg
>	%T4_W<def> = MOV %T3_W<kill>, 0, pred:%noreg
>	%T3_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C4_X, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y, %C5_X, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_W<def> = MULADD_eg %T1_Z, %C6_X, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = MUL %T1_X, %C4_Z, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C4_Y, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C2_Y, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T0_X<def> = MULADD_eg %T1_W, %C7_X, %T3_W<kill>, pred:%PRED_SEL_OFF, %T0_XYZW<imp-def>
>	%T5_X<def> = MULADD_eg %T1_Y, %C5_Z, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T3_W<def> = MULADD_eg %T1_Y, %C1_Z, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MULADD_eg %T1_Y, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y<kill>, %C5_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C6_Z, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = MULADD_eg %T1_Z, %C2_Z, %T3_W<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T3_W<def> = MULADD_eg %T1_Z, %C2_W, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_Z, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = MULADD_eg %T1_W, %C7_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_Z<kill>, %C6_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 0.000000e+00
>	%T0_W<def> = MOV %T3_Z, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T3_Y<def> = MULADD_eg %T1_W, %C7_Y, %T1_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T3_W<kill>, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %T5_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T1_Z<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T0_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	BUNDLE %T3_X<imp-def>, %T3_Y<imp-def>, %T3_Z<imp-def>, %T3_W<imp-def>, %T0_X<imp-use>, %T0_Y<imp-use>, %T0_Z<imp-use>, %T0_W<imp-use>
>	  * %T3_X<def> = DOT4_eg %T0_X, %T0_X, 32; flags: 
>	  * %T3_Y<def> = DOT4_eg %T0_Y, %T0_Y, 40; flags: 
>	  * %T3_Z<def> = DOT4_eg %T0_Z, %T0_Z, 40; flags: 
>	  * %T3_W<def> = DOT4_eg %T0_W, %T0_W, 8; flags: 
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T3_X<def> = MOV %T3_X<kill>, 256, pred:%PRED_SEL_OFF
>	%T3_X<def> = RECIPSQRT_CLAMPED_eg %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	BUNDLE %T3_X<imp-def>, %T3_Y<imp-def>, %T3_Z<imp-def>, %T3_W<imp-def>, %T3_X<imp-use>, %PRED_SEL_OFF<imp-use>
>	  * %T3_X<def> = RECIP_IEEE_cm %T3_X, pred:%PRED_SEL_OFF, 0; flags: 
>	  * %T3_Y<def> = RECIP_IEEE_cm %T3_X<internal>, pred:%PRED_SEL_OFF, 0; flags: 
>	  * %T3_Z<def> = RECIP_IEEE_cm %T3_X<internal>, pred:%PRED_SEL_OFF, 0; flags: 
>	  * %T3_W<def> = RECIP_IEEE_cm %T3_X<internal>, pred:%PRED_SEL_OFF, 0; flags: 
>	%T3_W<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	%T3_Y<def> = MOV %T3_Z, 0, pred:%noreg
>	RETURN %T4_W<imp-use,kill>, %T4_Z<imp-use,kill>, %T4_Y<imp-use,kill>, %T4_X<imp-use,kill>, %T3_W<imp-use,kill>, %T3_Z<imp-use,kill>, %T3_Y<imp-use,kill>, %T3_X<imp-use,kill>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 122 dw -- 6 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000007 ALU ADDR:14 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0D40000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:54
>0014 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 00800C90   INST:0x19 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0017 20800C90   INST:0x19 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 40800C90   INST:0x19 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 80000C03   SRC0(SEL:3 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 60800C90 * INST:0x19 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0023 00600090 * INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 00102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0025 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0026 80108001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:132 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0030 8010A401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:133 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 206284FE * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0032 00900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0033 20600090   INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 8010C801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:134 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0035 606284FE * INST:0x14 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0036 01108001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:132 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0037 00A00090   INST:0x1 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0039 406284FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0041 20A00090 * INST:0x1 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 00908001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:132 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0043 20600090   INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0044 80904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0045 40628803 * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0046 8010EC01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:135 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0047 00028C03 * INST:0x14 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:3 NEG:0)
>0048 0110A401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:133 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 00A28005   INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:0 NEG:0)
>0050 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 60628405 * INST:0x14 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0052 80106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 00628003 * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:0 NEG:0)
>0054 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0055 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0056 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0057 20A280FE * INST:0x14 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0058 8090A401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:133 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0059 20628403 * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0060 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0061 20228803   INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0062 8110C801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:134 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0063 40628005 * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:0 NEG:0)
>0064 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0065 00A28C03 * INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:3 NEG:0)
>0066 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0067 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0068 81904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0069 60628405 * INST:0x14 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0070 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0071 00628005 * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:0 NEG:0)
>0072 0110EC01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:135 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0073 00A28803   INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0074 8090C801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:134 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0075 40228403 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0076 800000F8   SRC0(SEL:248 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0077 40600C90 * INST:0x19 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0078 0090EC01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:135 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0079 20628801   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:1 REL:0 CHAN:2 NEG:0)
>0080 800008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0081 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0082 00000005   SRC0(SEL:5 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0083 40000C90   INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0084 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0085 60228C03 * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:3 NEG:0)
>0086 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0087 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0088 80000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0089 40200C90 * INST:0x19 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0090 00000000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0091 00605F10   INST:0xbe DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0092 009FC4FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0093 20605F00   INST:0xbe DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0094 01000800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0095 40605F00   INST:0xbe DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0096 81800C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0097 60605F00 * INST:0xbe DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0098 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0099 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0100 80000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0101 A0400C90 * INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0102 80000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0103 00600C91 * INST:0x19 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:1 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0104 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0105 00604390   INST:0x87 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0106 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0107 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0108 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0109 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0110 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0111 00604310 * INST:0x86 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0112 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0113 20604310   INST:0x86 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0114 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0115 40604310   INST:0x86 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0116 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0117 60604310 * INST:0x86 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0118 000008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0119 20600C90   INST:0x19 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0120 800000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0121 60600C90 * INST:0x19 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 94C00688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x53 BURST_COUNT:1 EOP:0
>0008 C001C001 EXPORT GPR:3 ELEM_SIZE:3 ARRAY_BASE:1 TYPE:2
>0009 94C00B20 EXPORT SWIZ_X:0 SWIZ_Y:4 SWIZ_Z:4 SWIZ_W:5 BARRIER:1 INST:0x53 BURST_COUNT:1 EOP:0
>0010 C0024002 EXPORT GPR:4 ELEM_SIZE:3 ARRAY_BASE:2 TYPE:2
>0011 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0012 00000000 CF ADDR:0
>0013 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.R600.load.input(i32 12)
>  %9 = call float @llvm.R600.load.input(i32 13)
>  %10 = call float @llvm.R600.load.input(i32 14)
>  %11 = call float @llvm.R600.load.input(i32 15)
>  %12 = call float @llvm.AMDGPU.load.const(i32 0)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 1)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 2)
>  %17 = call float @llvm.AMDGPU.mul(float %0, float %16)
>  %18 = call float @llvm.AMDGPU.load.const(i32 3)
>  %19 = call float @llvm.AMDGPU.mul(float %0, float %18)
>  %20 = call float @llvm.AMDGPU.load.const(i32 4)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 5)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 6)
>  %25 = call float @llvm.AMDIL.mad.(float %1, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 7)
>  %27 = call float @llvm.AMDIL.mad.(float %1, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 8)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 9)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 10)
>  %33 = call float @llvm.AMDIL.mad.(float %2, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 11)
>  %35 = call float @llvm.AMDIL.mad.(float %2, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 12)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 13)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  %40 = call float @llvm.AMDGPU.load.const(i32 14)
>  %41 = call float @llvm.AMDIL.mad.(float %3, float %40, float %33)
>  %42 = call float @llvm.AMDGPU.load.const(i32 15)
>  %43 = call float @llvm.AMDIL.mad.(float %3, float %42, float %35)
>  %44 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00)
>  %45 = call float @llvm.AMDIL.clamp.(float %5, float 0.000000e+00, float 1.000000e+00)
>  %46 = call float @llvm.AMDIL.clamp.(float %6, float 0.000000e+00, float 1.000000e+00)
>  %47 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %37, i32 4)
>  call void @llvm.AMDGPU.store.output(float %39, i32 5)
>  call void @llvm.AMDGPU.store.output(float %41, i32 6)
>  call void @llvm.AMDGPU.store.output(float %43, i32 7)
>  call void @llvm.AMDGPU.store.output(float %44, i32 8)
>  call void @llvm.AMDGPU.store.output(float %45, i32 9)
>  call void @llvm.AMDGPU.store.output(float %46, i32 10)
>  call void @llvm.AMDGPU.store.output(float %47, i32 11)
>  call void @llvm.AMDGPU.store.output(float %8, i32 12)
>  call void @llvm.AMDGPU.store.output(float %9, i32 13)
>  call void @llvm.AMDGPU.store.output(float %10, i32 14)
>  call void @llvm.AMDGPU.store.output(float %11, i32 15)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T3_W in %vreg0, %T3_Z in %vreg1, %T3_Y in %vreg2, %T3_X in %vreg3, %T2_W in %vreg4, %T2_Z in %vreg5, %T2_Y in %vreg6, %T2_X in %vreg7, %T1_W in %vreg8, %T1_Z in %vreg9, %T1_Y in %vreg10, %T1_X in %vreg11
>Function Live Outs: %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T4_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %T1_Y, %C1_X, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %T1_Z, %C2_X, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %T1_W, %C3_X, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T1_W, %C3_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T4_X<kill>, 0, pred:%noreg
>	%T4_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T4_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T3_W<imp-use,kill>, %T3_Z<imp-use,kill>, %T3_Y<imp-use,kill>, %T3_X<imp-use,kill>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 54 dw -- 5 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0540000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:22
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00800090 * INST:0x1 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 008280FE * INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 008280FE   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20800090 * INST:0x1 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 008280FE   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 208284FE * INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 208284FE   INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40800090 * INST:0x1 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 408288FE * INST:0x14 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20828404   INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 408288FE * INST:0x14 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 008284FE   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228804 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:2 NEG:0)
>0044 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0052 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95010688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:2 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0], LOCAL
>DCL TEMP[1], LOCAL
>  0: TXP TEMP[0], IN[2].xyyw, SAMP[0], 2D
>  1: TXP TEMP[1], IN[1].xyyw, SAMP[1], 2D
>  2: MUL TEMP[1], TEMP[1], IN[0]
>  3: MUL TEMP[0], TEMP[0], TEMP[1]
>  4: MOV_SAT OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  call void @llvm.AMDGPU.reserve.reg(i32 4)
>  call void @llvm.AMDGPU.reserve.reg(i32 5)
>  call void @llvm.AMDGPU.reserve.reg(i32 6)
>  call void @llvm.AMDGPU.reserve.reg(i32 7)
>  %0 = call float @llvm.R600.load.input(i32 8)
>  %1 = call float @llvm.R600.load.input(i32 9)
>  %2 = call float @llvm.R600.load.input(i32 10)
>  %3 = call float @llvm.R600.load.input(i32 11)
>  %4 = call float @llvm.R600.load.input(i32 12)
>  %5 = call float @llvm.R600.load.input(i32 13)
>  %6 = call float @llvm.R600.load.input(i32 14)
>  %7 = call float @llvm.R600.load.input(i32 15)
>  %8 = call float @llvm.R600.load.input(i32 16)
>  %9 = call float @llvm.R600.load.input(i32 17)
>  %10 = call float @llvm.R600.load.input(i32 18)
>  %11 = call float @llvm.R600.load.input(i32 19)
>  %12 = call float @llvm.AMDGPU.div(float %8, float %11)
>  %13 = call float @llvm.AMDGPU.div(float %9, float %11)
>  %14 = call float @llvm.AMDGPU.div(float %9, float %11)
>  %15 = insertelement <4 x float> undef, float %12, i32 0
>  %16 = insertelement <4 x float> %15, float %13, i32 1
>  %17 = insertelement <4 x float> %16, float %14, i32 2
>  %18 = insertelement <4 x float> %17, float 1.000000e+00, i32 3
>  %19 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %18, i32 0, i32 2)
>  %20 = extractelement <4 x float> %19, i32 0
>  %21 = extractelement <4 x float> %19, i32 1
>  %22 = extractelement <4 x float> %19, i32 2
>  %23 = extractelement <4 x float> %19, i32 3
>  %24 = call float @llvm.AMDGPU.div(float %4, float %7)
>  %25 = call float @llvm.AMDGPU.div(float %5, float %7)
>  %26 = call float @llvm.AMDGPU.div(float %5, float %7)
>  %27 = insertelement <4 x float> undef, float %24, i32 0
>  %28 = insertelement <4 x float> %27, float %25, i32 1
>  %29 = insertelement <4 x float> %28, float %26, i32 2
>  %30 = insertelement <4 x float> %29, float 1.000000e+00, i32 3
>  %31 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %30, i32 1, i32 2)
>  %32 = extractelement <4 x float> %31, i32 0
>  %33 = extractelement <4 x float> %31, i32 1
>  %34 = extractelement <4 x float> %31, i32 2
>  %35 = extractelement <4 x float> %31, i32 3
>  %36 = call float @llvm.AMDGPU.mul(float %32, float %0)
>  %37 = call float @llvm.AMDGPU.mul(float %33, float %1)
>  %38 = call float @llvm.AMDGPU.mul(float %34, float %2)
>  %39 = call float @llvm.AMDGPU.mul(float %35, float %3)
>  %40 = call float @llvm.AMDGPU.mul(float %20, float %36)
>  %41 = call float @llvm.AMDGPU.mul(float %21, float %37)
>  %42 = call float @llvm.AMDGPU.mul(float %22, float %38)
>  %43 = call float @llvm.AMDGPU.mul(float %23, float %39)
>  %44 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %45 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %46 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %47 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %44, i32 8)
>  call void @llvm.AMDGPU.store.output(float %45, i32 9)
>  call void @llvm.AMDGPU.store.output(float %46, i32 10)
>  call void @llvm.AMDGPU.store.output(float %47, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.div(float, float) readnone
>
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T4_W in %vreg0, %T4_Y in %vreg1, %T4_X in %vreg2, %T3_W in %vreg3, %T3_Y in %vreg4, %T3_X in %vreg5, %T2_W in %vreg6, %T2_Z in %vreg7, %T2_Y in %vreg8, %T2_X in %vreg9
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T4_W %T4_Y %T4_X %T3_W %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X
>	%T3_W<def> = RECIP_IEEE_eg %T3_W<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = RECIP_IEEE_eg %T4_W<kill>, pred:%PRED_SEL_OFF
>	%T0_X<def> = MUL %T3_X<kill>, %T3_W, pred:%PRED_SEL_OFF, %T0_XYZW<imp-def>
>	%T1_X<def> = MUL %T4_X<kill>, %T3_Z, pred:%PRED_SEL_OFF, %T1_XYZW<imp-def>
>	%T3_X<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	%T3_Y<def> = MUL %T3_Y<kill>, %T3_W<kill>, pred:%PRED_SEL_OFF
>	%T0_W<def> = MOV %T3_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_Z<def> = MOV %T3_Y, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_XYZW<def> = TEX_SAMPLE %T0_XYZW<kill>, 1, 2
>	%T1_W<def> = MOV %T3_X<kill>, 0, pred:%noreg, %T1_XYZW<imp-def>
>	%T3_X<def> = MUL %T4_Y<kill>, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MOV %T3_X, 0, pred:%noreg, %T1_XYZW<imp-def>
>	%T1_Y<def> = MOV %T3_X<kill>, 0, pred:%noreg, %T1_XYZW<imp-def>
>	%T1_XYZW<def> = TEX_SAMPLE %T1_XYZW<kill>, 0, 2
>	%T2_X<def> = MUL %T0_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MUL %T1_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MUL %T0_Y, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MUL %T0_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MUL %T1_Y, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MUL %T1_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MUL %T0_W, %T2_W<kill>, pred:%PRED_SEL_OFF, %T0_XYZW<imp-use,kill>
>	%T2_W<def> = MUL %T1_W, %T2_W<kill>, pred:%PRED_SEL_OFF, %T1_XYZW<imp-use,kill>
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 120 dw -- 5 gprs ---------------------
>     C
>0000 00000007 ALU ADDR:14 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A0800000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:33
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0017 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 40546B90   INST:0xd7 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 60546B90 * INST:0xd7 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 00546B10   INST:0xd6 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0025 20546B10   INST:0xd6 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0031 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 00382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0033 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 40746B90   INST:0xd7 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 80382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 60746B90 * INST:0xd7 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 00746B10   INST:0xd6 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0040 00382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20746B10   INST:0xd6 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0043 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0044 80382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0045 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00384400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00384000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 00384400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0051 40946B90   INST:0xd7 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0052 80384000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 60946B90 * INST:0xd7 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0054 00384400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0055 00946B10   INST:0xd6 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0056 00384000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0057 20946B10   INST:0xd6 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0058 00384400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0059 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0060 80384000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0061 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0062 80000C03   SRC0(SEL:3 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0063 60604310 * INST:0x86 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0064 019FC003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0065 00000090   INST:0x1 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0066 80000C04   SRC0(SEL:4 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0067 40604310 * INST:0x86 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0068 811FC004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0069 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0070 000000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0071 00600C90   INST:0x19 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0072 81806403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:3 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0073 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0074 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0075 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0076 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0077 40000C90   INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0078 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0079 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 00000028 TEX/VTX ADDR:80
>0003 80400000 TEX/VTX INST:0x1 COUNT:1
>0080 00000310   INST:0x10 RESOURCE_ID:3 SRC(GPR:0 REL:0)
>0081 F00D1000   DST(GPR:0 REL:0 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) LOD_BIAS:0 COORD_TYPE_X:1 COORD_TYPE_Y:1 COORD_TYPE_Z:1 COORD_TYPE_W:1
>0082 68808000   OFFSET_X:0 OFFSET_Y:0 OFFSET_Z:0 SAMPLER_ID:1 SRC(SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3)
>0083 00000000   
>0004 0000002A ALU ADDR:84 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0005 A00C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:4
>0084 01006404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:3 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0085 00600090   INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0086 80000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0087 60200C90 * INST:0x19 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0088 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0089 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0090 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0091 40200C90 * INST:0x19 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0006 0000002E TEX/VTX ADDR:92
>0007 80400000 TEX/VTX INST:0x1 COUNT:1
>0092 00010210   INST:0x10 RESOURCE_ID:2 SRC(GPR:1 REL:0)
>0093 F00D1001   DST(GPR:1 REL:0 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) LOD_BIAS:0 COORD_TYPE_X:1 COORD_TYPE_Y:1 COORD_TYPE_Z:1 COORD_TYPE_W:1
>0094 68800000   OFFSET_X:0 OFFSET_Y:0 OFFSET_Z:0 SAMPLER_ID:0 SRC(SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3)
>0095 00000000   
>0008 00000030 ALU ADDR:96 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0009 A02C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:12
>0096 80004000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0097 00400090 * INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0098 001FC001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0099 00400090   INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0100 00804400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:2 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0101 20400090   INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0102 81004800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:2 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0103 40400090 * INST:0x1 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0104 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0105 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0106 009FC401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0107 20400090   INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0108 011FC801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:254 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0109 40400090   INST:0x1 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0110 81804C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:2 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0111 60400090 * INST:0x1 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0112 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0113 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0114 000008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0115 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0116 819FCC01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:254 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0117 60400090 * INST:0x1 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0118 80000CFE   SRC0(SEL:254 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0119 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0010 C0010000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0011 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0012 00000000 CF ADDR:0
>0013 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..26]
>DCL TEMP[0..3]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: MUL TEMP[0], TEMP[0], CONST[7]
>  8: MOV TEMP[1].w, CONST[8].xxxx
>  9: MOV TEMP[2], CONST[9]
> 10: MOV_SAT OUT[1], TEMP[2]
> 11: DP3 TEMP[1].x, TEMP[0], CONST[10]
> 12: DP3 TEMP[1].y, TEMP[0], CONST[12]
> 13: LIT TEMP[3], TEMP[1]
> 14: ADD TEMP[2], CONST[13], TEMP[2]
> 15: MAD TEMP[2], TEMP[3].yyyy, CONST[14], TEMP[2]
> 16: MAD TEMP[2], TEMP[3].zzzz, CONST[15], TEMP[2]
> 17: DP3 TEMP[1].x, TEMP[0], CONST[16]
> 18: DP3 TEMP[1].y, TEMP[0], CONST[18]
> 19: LIT TEMP[3], TEMP[1]
> 20: ADD TEMP[2], CONST[19], TEMP[2]
> 21: MAD TEMP[2], TEMP[3].yyyy, CONST[20], TEMP[2]
> 22: MAD_SAT OUT[1].xyz, TEMP[3].zzzz, CONST[21], TEMP[2]
> 23: MOV OUT[2], IN[2]
> 24: MUL TEMP[3], CONST[22].xxxx, CONST[23]
> 25: MAD TEMP[3], CONST[22].yyyy, CONST[24], TEMP[3]
> 26: MAD TEMP[3], CONST[22].zzzz, CONST[25], TEMP[3]
> 27: MAD OUT[3], CONST[22].wwww, CONST[26], TEMP[3]
> 28: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.R600.load.input(i32 12)
>  %9 = call float @llvm.R600.load.input(i32 13)
>  %10 = call float @llvm.R600.load.input(i32 14)
>  %11 = call float @llvm.R600.load.input(i32 15)
>  %12 = call float @llvm.AMDGPU.load.const(i32 0)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 1)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 2)
>  %17 = call float @llvm.AMDGPU.mul(float %0, float %16)
>  %18 = call float @llvm.AMDGPU.load.const(i32 3)
>  %19 = call float @llvm.AMDGPU.mul(float %0, float %18)
>  %20 = call float @llvm.AMDGPU.load.const(i32 4)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 5)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 6)
>  %25 = call float @llvm.AMDIL.mad.(float %1, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 7)
>  %27 = call float @llvm.AMDIL.mad.(float %1, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 8)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 9)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 10)
>  %33 = call float @llvm.AMDIL.mad.(float %2, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 11)
>  %35 = call float @llvm.AMDIL.mad.(float %2, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 12)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 13)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  %40 = call float @llvm.AMDGPU.load.const(i32 14)
>  %41 = call float @llvm.AMDIL.mad.(float %3, float %40, float %33)
>  %42 = call float @llvm.AMDGPU.load.const(i32 15)
>  %43 = call float @llvm.AMDIL.mad.(float %3, float %42, float %35)
>  %44 = call float @llvm.AMDGPU.load.const(i32 16)
>  %45 = call float @llvm.AMDGPU.load.const(i32 17)
>  %46 = call float @llvm.AMDGPU.load.const(i32 18)
>  %47 = insertelement <4 x float> undef, float %4, i32 0
>  %48 = insertelement <4 x float> %47, float %5, i32 1
>  %49 = insertelement <4 x float> %48, float %6, i32 2
>  %50 = insertelement <4 x float> %49, float 0.000000e+00, i32 3
>  %51 = insertelement <4 x float> undef, float %44, i32 0
>  %52 = insertelement <4 x float> %51, float %45, i32 1
>  %53 = insertelement <4 x float> %52, float %46, i32 2
>  %54 = insertelement <4 x float> %53, float 0.000000e+00, i32 3
>  %55 = call float @llvm.AMDGPU.dp4(<4 x float> %50, <4 x float> %54)
>  %56 = call float @llvm.AMDGPU.load.const(i32 20)
>  %57 = call float @llvm.AMDGPU.load.const(i32 21)
>  %58 = call float @llvm.AMDGPU.load.const(i32 22)
>  %59 = insertelement <4 x float> undef, float %4, i32 0
>  %60 = insertelement <4 x float> %59, float %5, i32 1
>  %61 = insertelement <4 x float> %60, float %6, i32 2
>  %62 = insertelement <4 x float> %61, float 0.000000e+00, i32 3
>  %63 = insertelement <4 x float> undef, float %56, i32 0
>  %64 = insertelement <4 x float> %63, float %57, i32 1
>  %65 = insertelement <4 x float> %64, float %58, i32 2
>  %66 = insertelement <4 x float> %65, float 0.000000e+00, i32 3
>  %67 = call float @llvm.AMDGPU.dp4(<4 x float> %62, <4 x float> %66)
>  %68 = call float @llvm.AMDGPU.load.const(i32 24)
>  %69 = call float @llvm.AMDGPU.load.const(i32 25)
>  %70 = call float @llvm.AMDGPU.load.const(i32 26)
>  %71 = insertelement <4 x float> undef, float %4, i32 0
>  %72 = insertelement <4 x float> %71, float %5, i32 1
>  %73 = insertelement <4 x float> %72, float %6, i32 2
>  %74 = insertelement <4 x float> %73, float 0.000000e+00, i32 3
>  %75 = insertelement <4 x float> undef, float %68, i32 0
>  %76 = insertelement <4 x float> %75, float %69, i32 1
>  %77 = insertelement <4 x float> %76, float %70, i32 2
>  %78 = insertelement <4 x float> %77, float 0.000000e+00, i32 3
>  %79 = call float @llvm.AMDGPU.dp4(<4 x float> %74, <4 x float> %78)
>  %80 = call float @llvm.AMDGPU.load.const(i32 28)
>  %81 = call float @llvm.AMDGPU.mul(float %55, float %80)
>  %82 = call float @llvm.AMDGPU.load.const(i32 29)
>  %83 = call float @llvm.AMDGPU.mul(float %67, float %82)
>  %84 = call float @llvm.AMDGPU.load.const(i32 30)
>  %85 = call float @llvm.AMDGPU.mul(float %79, float %84)
>  %86 = call float @llvm.AMDGPU.load.const(i32 31)
>  %87 = call float @llvm.AMDGPU.mul(float %35, float %86)
>  %88 = call float @llvm.AMDGPU.load.const(i32 32)
>  %89 = call float @llvm.AMDGPU.load.const(i32 36)
>  %90 = call float @llvm.AMDGPU.load.const(i32 37)
>  %91 = call float @llvm.AMDGPU.load.const(i32 38)
>  %92 = call float @llvm.AMDGPU.load.const(i32 39)
>  %93 = call float @llvm.AMDIL.clamp.(float %89, float 0.000000e+00, float 1.000000e+00)
>  %94 = call float @llvm.AMDIL.clamp.(float %90, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %91, float 0.000000e+00, float 1.000000e+00)
>  %96 = call float @llvm.AMDIL.clamp.(float %92, float 0.000000e+00, float 1.000000e+00)
>  %97 = call float @llvm.AMDGPU.load.const(i32 40)
>  %98 = call float @llvm.AMDGPU.load.const(i32 41)
>  %99 = call float @llvm.AMDGPU.load.const(i32 42)
>  %100 = insertelement <4 x float> undef, float %81, i32 0
>  %101 = insertelement <4 x float> %100, float %83, i32 1
>  %102 = insertelement <4 x float> %101, float %85, i32 2
>  %103 = insertelement <4 x float> %102, float 0.000000e+00, i32 3
>  %104 = insertelement <4 x float> undef, float %97, i32 0
>  %105 = insertelement <4 x float> %104, float %98, i32 1
>  %106 = insertelement <4 x float> %105, float %99, i32 2
>  %107 = insertelement <4 x float> %106, float 0.000000e+00, i32 3
>  %108 = call float @llvm.AMDGPU.dp4(<4 x float> %103, <4 x float> %107)
>  %109 = call float @llvm.AMDGPU.load.const(i32 48)
>  %110 = call float @llvm.AMDGPU.load.const(i32 49)
>  %111 = call float @llvm.AMDGPU.load.const(i32 50)
>  %112 = insertelement <4 x float> undef, float %81, i32 0
>  %113 = insertelement <4 x float> %112, float %83, i32 1
>  %114 = insertelement <4 x float> %113, float %85, i32 2
>  %115 = insertelement <4 x float> %114, float 0.000000e+00, i32 3
>  %116 = insertelement <4 x float> undef, float %109, i32 0
>  %117 = insertelement <4 x float> %116, float %110, i32 1
>  %118 = insertelement <4 x float> %117, float %111, i32 2
>  %119 = insertelement <4 x float> %118, float 0.000000e+00, i32 3
>  %120 = call float @llvm.AMDGPU.dp4(<4 x float> %115, <4 x float> %119)
>  %121 = call float @llvm.AMDIL.max.(float %108, float 0.000000e+00)
>  %122 = call float @llvm.AMDIL.max.(float %120, float 0.000000e+00)
>  %123 = call float @llvm.AMDGPU.pow(float %122, float %88)
>  %124 = call float @llvm.AMDGPU.cndlt(float %108, float 0.000000e+00, float %123)
>  %125 = call float @llvm.AMDGPU.load.const(i32 52)
>  %126 = fadd float %125, %89
>  %127 = call float @llvm.AMDGPU.load.const(i32 53)
>  %128 = fadd float %127, %90
>  %129 = call float @llvm.AMDGPU.load.const(i32 54)
>  %130 = fadd float %129, %91
>  %131 = call float @llvm.AMDGPU.load.const(i32 55)
>  %132 = fadd float %131, %92
>  %133 = call float @llvm.AMDGPU.load.const(i32 56)
>  %134 = call float @llvm.AMDIL.mad.(float %121, float %133, float %126)
>  %135 = call float @llvm.AMDGPU.load.const(i32 57)
>  %136 = call float @llvm.AMDIL.mad.(float %121, float %135, float %128)
>  %137 = call float @llvm.AMDGPU.load.const(i32 58)
>  %138 = call float @llvm.AMDIL.mad.(float %121, float %137, float %130)
>  %139 = call float @llvm.AMDGPU.load.const(i32 59)
>  %140 = call float @llvm.AMDIL.mad.(float %121, float %139, float %132)
>  %141 = call float @llvm.AMDGPU.load.const(i32 60)
>  %142 = call float @llvm.AMDIL.mad.(float %124, float %141, float %134)
>  %143 = call float @llvm.AMDGPU.load.const(i32 61)
>  %144 = call float @llvm.AMDIL.mad.(float %124, float %143, float %136)
>  %145 = call float @llvm.AMDGPU.load.const(i32 62)
>  %146 = call float @llvm.AMDIL.mad.(float %124, float %145, float %138)
>  %147 = call float @llvm.AMDGPU.load.const(i32 63)
>  %148 = call float @llvm.AMDIL.mad.(float %124, float %147, float %140)
>  %149 = call float @llvm.AMDGPU.load.const(i32 64)
>  %150 = call float @llvm.AMDGPU.load.const(i32 65)
>  %151 = call float @llvm.AMDGPU.load.const(i32 66)
>  %152 = insertelement <4 x float> undef, float %81, i32 0
>  %153 = insertelement <4 x float> %152, float %83, i32 1
>  %154 = insertelement <4 x float> %153, float %85, i32 2
>  %155 = insertelement <4 x float> %154, float 0.000000e+00, i32 3
>  %156 = insertelement <4 x float> undef, float %149, i32 0
>  %157 = insertelement <4 x float> %156, float %150, i32 1
>  %158 = insertelement <4 x float> %157, float %151, i32 2
>  %159 = insertelement <4 x float> %158, float 0.000000e+00, i32 3
>  %160 = call float @llvm.AMDGPU.dp4(<4 x float> %155, <4 x float> %159)
>  %161 = call float @llvm.AMDGPU.load.const(i32 72)
>  %162 = call float @llvm.AMDGPU.load.const(i32 73)
>  %163 = call float @llvm.AMDGPU.load.const(i32 74)
>  %164 = insertelement <4 x float> undef, float %81, i32 0
>  %165 = insertelement <4 x float> %164, float %83, i32 1
>  %166 = insertelement <4 x float> %165, float %85, i32 2
>  %167 = insertelement <4 x float> %166, float 0.000000e+00, i32 3
>  %168 = insertelement <4 x float> undef, float %161, i32 0
>  %169 = insertelement <4 x float> %168, float %162, i32 1
>  %170 = insertelement <4 x float> %169, float %163, i32 2
>  %171 = insertelement <4 x float> %170, float 0.000000e+00, i32 3
>  %172 = call float @llvm.AMDGPU.dp4(<4 x float> %167, <4 x float> %171)
>  %173 = call float @llvm.AMDIL.max.(float %160, float 0.000000e+00)
>  %174 = call float @llvm.AMDIL.max.(float %172, float 0.000000e+00)
>  %175 = call float @llvm.AMDGPU.pow(float %174, float %88)
>  %176 = call float @llvm.AMDGPU.cndlt(float %160, float 0.000000e+00, float %175)
>  %177 = call float @llvm.AMDGPU.load.const(i32 76)
>  %178 = fadd float %177, %142
>  %179 = call float @llvm.AMDGPU.load.const(i32 77)
>  %180 = fadd float %179, %144
>  %181 = call float @llvm.AMDGPU.load.const(i32 78)
>  %182 = fadd float %181, %146
>  %183 = call float @llvm.AMDGPU.load.const(i32 79)
>  %184 = fadd float %183, %148
>  %185 = call float @llvm.AMDGPU.load.const(i32 80)
>  %186 = call float @llvm.AMDIL.mad.(float %173, float %185, float %178)
>  %187 = call float @llvm.AMDGPU.load.const(i32 81)
>  %188 = call float @llvm.AMDIL.mad.(float %173, float %187, float %180)
>  %189 = call float @llvm.AMDGPU.load.const(i32 82)
>  %190 = call float @llvm.AMDIL.mad.(float %173, float %189, float %182)
>  %191 = call float @llvm.AMDGPU.load.const(i32 83)
>  %192 = call float @llvm.AMDIL.mad.(float %173, float %191, float %184)
>  %193 = call float @llvm.AMDGPU.load.const(i32 84)
>  %194 = call float @llvm.AMDIL.mad.(float %176, float %193, float %186)
>  %195 = call float @llvm.AMDGPU.load.const(i32 85)
>  %196 = call float @llvm.AMDIL.mad.(float %176, float %195, float %188)
>  %197 = call float @llvm.AMDGPU.load.const(i32 86)
>  %198 = call float @llvm.AMDIL.mad.(float %176, float %197, float %190)
>  %199 = call float @llvm.AMDIL.clamp.(float %194, float 0.000000e+00, float 1.000000e+00)
>  %200 = call float @llvm.AMDIL.clamp.(float %196, float 0.000000e+00, float 1.000000e+00)
>  %201 = call float @llvm.AMDIL.clamp.(float %198, float 0.000000e+00, float 1.000000e+00)
>  %202 = call float @llvm.AMDGPU.load.const(i32 88)
>  %203 = call float @llvm.AMDGPU.load.const(i32 92)
>  %204 = call float @llvm.AMDGPU.mul(float %202, float %203)
>  %205 = call float @llvm.AMDGPU.load.const(i32 88)
>  %206 = call float @llvm.AMDGPU.load.const(i32 93)
>  %207 = call float @llvm.AMDGPU.mul(float %205, float %206)
>  %208 = call float @llvm.AMDGPU.load.const(i32 88)
>  %209 = call float @llvm.AMDGPU.load.const(i32 94)
>  %210 = call float @llvm.AMDGPU.mul(float %208, float %209)
>  %211 = call float @llvm.AMDGPU.load.const(i32 88)
>  %212 = call float @llvm.AMDGPU.load.const(i32 95)
>  %213 = call float @llvm.AMDGPU.mul(float %211, float %212)
>  %214 = call float @llvm.AMDGPU.load.const(i32 89)
>  %215 = call float @llvm.AMDGPU.load.const(i32 96)
>  %216 = call float @llvm.AMDIL.mad.(float %214, float %215, float %204)
>  %217 = call float @llvm.AMDGPU.load.const(i32 89)
>  %218 = call float @llvm.AMDGPU.load.const(i32 97)
>  %219 = call float @llvm.AMDIL.mad.(float %217, float %218, float %207)
>  %220 = call float @llvm.AMDGPU.load.const(i32 89)
>  %221 = call float @llvm.AMDGPU.load.const(i32 98)
>  %222 = call float @llvm.AMDIL.mad.(float %220, float %221, float %210)
>  %223 = call float @llvm.AMDGPU.load.const(i32 89)
>  %224 = call float @llvm.AMDGPU.load.const(i32 99)
>  %225 = call float @llvm.AMDIL.mad.(float %223, float %224, float %213)
>  %226 = call float @llvm.AMDGPU.load.const(i32 90)
>  %227 = call float @llvm.AMDGPU.load.const(i32 100)
>  %228 = call float @llvm.AMDIL.mad.(float %226, float %227, float %216)
>  %229 = call float @llvm.AMDGPU.load.const(i32 90)
>  %230 = call float @llvm.AMDGPU.load.const(i32 101)
>  %231 = call float @llvm.AMDIL.mad.(float %229, float %230, float %219)
>  %232 = call float @llvm.AMDGPU.load.const(i32 90)
>  %233 = call float @llvm.AMDGPU.load.const(i32 102)
>  %234 = call float @llvm.AMDIL.mad.(float %232, float %233, float %222)
>  %235 = call float @llvm.AMDGPU.load.const(i32 90)
>  %236 = call float @llvm.AMDGPU.load.const(i32 103)
>  %237 = call float @llvm.AMDIL.mad.(float %235, float %236, float %225)
>  %238 = call float @llvm.AMDGPU.load.const(i32 91)
>  %239 = call float @llvm.AMDGPU.load.const(i32 104)
>  %240 = call float @llvm.AMDIL.mad.(float %238, float %239, float %228)
>  %241 = call float @llvm.AMDGPU.load.const(i32 91)
>  %242 = call float @llvm.AMDGPU.load.const(i32 105)
>  %243 = call float @llvm.AMDIL.mad.(float %241, float %242, float %231)
>  %244 = call float @llvm.AMDGPU.load.const(i32 91)
>  %245 = call float @llvm.AMDGPU.load.const(i32 106)
>  %246 = call float @llvm.AMDIL.mad.(float %244, float %245, float %234)
>  %247 = call float @llvm.AMDGPU.load.const(i32 91)
>  %248 = call float @llvm.AMDGPU.load.const(i32 107)
>  %249 = call float @llvm.AMDIL.mad.(float %247, float %248, float %237)
>  call void @llvm.AMDGPU.store.output(float %37, i32 4)
>  call void @llvm.AMDGPU.store.output(float %39, i32 5)
>  call void @llvm.AMDGPU.store.output(float %41, i32 6)
>  call void @llvm.AMDGPU.store.output(float %43, i32 7)
>  call void @llvm.AMDGPU.store.output(float %199, i32 8)
>  call void @llvm.AMDGPU.store.output(float %200, i32 9)
>  call void @llvm.AMDGPU.store.output(float %201, i32 10)
>  call void @llvm.AMDGPU.store.output(float %96, i32 11)
>  call void @llvm.AMDGPU.store.output(float %8, i32 12)
>  call void @llvm.AMDGPU.store.output(float %9, i32 13)
>  call void @llvm.AMDGPU.store.output(float %10, i32 14)
>  call void @llvm.AMDGPU.store.output(float %11, i32 15)
>  call void @llvm.AMDGPU.store.output(float %240, i32 16)
>  call void @llvm.AMDGPU.store.output(float %243, i32 17)
>  call void @llvm.AMDGPU.store.output(float %246, i32 18)
>  call void @llvm.AMDGPU.store.output(float %249, i32 19)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare float @llvm.AMDIL.max.(float, float) readnone
>
>declare float @llvm.AMDGPU.pow(float, float) readnone
>
>declare float @llvm.AMDGPU.cndlt(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T3_W in %vreg0, %T3_Z in %vreg1, %T3_Y in %vreg2, %T3_X in %vreg3, %T2_Z in %vreg4, %T2_Y in %vreg5, %T2_X in %vreg6, %T1_W in %vreg7, %T1_Z in %vreg8, %T1_Y in %vreg9, %T1_X in %vreg10
>Function Live Outs: %T4_W %T4_Z %T4_Y %T4_X %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T3_W %T3_Z %T3_Y %T3_X %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T0_X<def> = MOV %T2_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T4_X<def> = MOV %C4_X, 0, pred:%noreg, %T4_XYZW<imp-def>
>	%T7_X<def> = MOV %C6_X, 0, pred:%noreg, %T7_XYZW<imp-def>
>	%T6_X<def> = MOV %C5_X, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T5_X<def> = MOV %C12_X, 0, pred:%noreg, %T5_XYZW<imp-def>
>	%T2_X<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 0.000000e+00
>	%T4_W<def> = MOV %T2_X, 0, pred:%noreg, %T4_XYZW<imp-def>
>	%T0_W<def> = MOV %T2_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T4_Z<def> = MOV %C4_Z, 0, pred:%noreg, %T4_XYZW<imp-def>
>	%T0_Z<def> = MOV %T2_Z<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T4_Y<def> = MOV %C4_Y, 0, pred:%noreg, %T4_XYZW<imp-def>
>	%T7_W<def> = MOV %T2_X, 0, pred:%noreg, %T7_XYZW<imp-def>
>	%T6_W<def> = MOV %T2_X, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T7_Z<def> = MOV %C6_Z, 0, pred:%noreg, %T7_XYZW<imp-def>
>	%T0_Y<def> = MOV %T2_Y<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T0_X<imp-use>, %T4_X<imp-use>, %T0_Y<imp-use>, %T4_Y<imp-use>, %T0_Z<imp-use>, %T4_Z<imp-use>, %T0_W<imp-use>, %T4_W<imp-use>
>	  * %T2_X<def> = DOT4_eg %T0_X, %T4_X, 40; flags: 
>	  * %T2_Y<def> = DOT4_eg %T0_Y, %T4_Y, 32; flags: 
>	  * %T2_Z<def> = DOT4_eg %T0_Z, %T4_Z, 40; flags: 
>	  * %T2_W<def> = DOT4_eg %T0_W, %T4_W, 8; flags: 
>	%T4_X<def> = MUL %T2_Y<kill>, %C7_X, pred:%PRED_SEL_OFF, %T4_XYZW<imp-def>
>	%T6_Z<def> = MOV %C5_Z, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T7_Y<def> = MOV %C6_Y, 0, pred:%noreg, %T7_XYZW<imp-def>
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T0_X<imp-use>, %T7_X<imp-use>, %T0_Y<imp-use>, %T7_Y<imp-use>, %T0_Z<imp-use>, %T7_Z<imp-use>, %T0_W<imp-use>, %T7_W<imp-use>
>	  * %T2_X<def> = DOT4_eg %T0_X, %T7_X, 40; flags: 
>	  * %T2_Y<def> = DOT4_eg %T0_Y, %T7_Y, 32; flags: 
>	  * %T2_Z<def> = DOT4_eg %T0_Z, %T7_Z, 40; flags: 
>	  * %T2_W<def> = DOT4_eg %T0_W, %T7_W, 8; flags: 
>	%T2_Z<def> = MUL %T2_Y<kill>, %C7_Z, pred:%PRED_SEL_OFF
>	%T6_Y<def> = MOV %C5_Y, 0, pred:%noreg, %T6_XYZW<imp-def>
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T0_X<imp-use>, %T6_X<imp-use>, %T0_Y<imp-use>, %T6_Y<imp-use>, %T0_Z<imp-use>, %T6_Z<imp-use>, %T0_W<imp-use>, %T6_W<imp-use>
>	  * %T2_X<def> = DOT4_eg %T0_X, %T6_X, 40; flags: 
>	  * %T2_Y<def> = DOT4_eg %T0_Y, %T6_Y, 32; flags: 
>	  * %T2_Z<def> = DOT4_eg %T0_Z, %T6_Z, 40; flags: 
>	  * %T2_W<def> = DOT4_eg %T0_W, %T6_W, 8; flags: 
>	%T2_Y<def> = MUL %T2_Y<kill>, %C7_Y, pred:%PRED_SEL_OFF
>	%T4_W<def> = MOV %T2_X, 0, pred:%noreg, %T4_XYZW<imp-def>
>	%T5_W<def> = MOV %T2_X, 0, pred:%noreg, %T5_XYZW<imp-def>
>	%T4_Z<def> = MOV %T2_Z<kill>, 0, pred:%noreg, %T4_XYZW<imp-def>
>	%T5_Z<def> = MOV %C12_Z, 0, pred:%noreg, %T5_XYZW<imp-def>
>	%T0_X<def> = MOV %C18_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T5_Y<def> = MOV %C12_Y, 0, pred:%noreg, %T5_XYZW<imp-def>
>	%T6_X<def> = MOV %C10_X, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T0_W<def> = MOV %T2_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T6_W<def> = MOV %T2_X, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T4_Y<def> = MOV %T2_Y<kill>, 0, pred:%noreg, %T4_XYZW<imp-def>
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T4_X<imp-use>, %T5_X<imp-use>, %T4_Y<imp-use>, %T5_Y<imp-use>, %T4_Z<imp-use>, %T5_Z<imp-use>, %T4_W<imp-use>, %T5_W<imp-use>
>	  * %T2_X<def> = DOT4_eg %T4_X, %T5_X, 40; flags: 
>	  * %T2_Y<def> = DOT4_eg %T4_Y, %T5_Y, 32; flags: 
>	  * %T2_Z<def> = DOT4_eg %T4_Z, %T5_Z, 40; flags: 
>	  * %T2_W<def> = DOT4_eg %T4_W, %T5_W, 8; flags: 
>	%T2_Y<def> = MAX %T2_Y<kill>, %T2_X, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %C18_Z, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T6_Z<def> = MOV %C10_Z, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T2_Y<def> = LOG_IEEE_eg %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T6_Y<def> = MOV %C10_Y, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T0_Y<def> = MOV %C18_Y, 0, pred:%noreg, %T0_XYZW<imp-def>
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T4_X<imp-use>, %T0_X<imp-use>, %T4_Y<imp-use>, %T0_Y<imp-use>, %T4_Z<imp-use>, %T0_Z<imp-use>, %T4_W<imp-use>, %T0_W<imp-use>
>	  * %T2_X<def> = DOT4_eg %T4_X, %T0_X, 40; flags: 
>	  * %T2_Y<def> = DOT4_eg %T4_Y, %T0_Y, 40; flags: 
>	  * %T2_Z<def> = DOT4_eg %T4_Z, %T0_Z, 32; flags: 
>	  * %T2_W<def> = DOT4_eg %T4_W, %T0_W, 8; flags: 
>	%T0_X<def> = MOV %C16_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T2_W<def> = MAX %T2_Z<kill>, %T2_X, pred:%PRED_SEL_OFF
>	BUNDLE %T5_X<imp-def>, %T5_Y<imp-def>, %T5_Z<imp-def>, %T5_W<imp-def>, %T4_X<imp-use>, %T6_X<imp-use>, %T4_Y<imp-use>, %T6_Y<imp-use>, %T4_Z<imp-use>, %T6_Z<imp-use>, %T4_W<imp-use>, %T6_W<imp-use>
>	  * %T5_X<def> = DOT4_eg %T4_X, %T6_X, 32; flags: 
>	  * %T5_Y<def> = DOT4_eg %T4_Y, %T6_Y, 40; flags: 
>	  * %T5_Z<def> = DOT4_eg %T4_Z, %T6_Z, 40; flags: 
>	  * %T5_W<def> = DOT4_eg %T4_W, %T6_W, 8; flags: 
>	%T5_Y<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MAX %T5_X, %T2_X, pred:%PRED_SEL_OFF
>	%T0_W<def> = MOV %T2_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T2_Y<def> = MUL %C8_X, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %C16_Z, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T5_W<def> = MULADD_eg %T1_Y, %C1_X, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = EXP_IEEE_eg %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = CNDGE_eg %T5_X<kill>, %T2_Y<kill>, %T2_X, pred:%PRED_SEL_OFF
>	%T5_X<def> = ADD %C13_X, %C9_X, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MULADD_eg %T2_Z, %C14_X, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T2_W<def> = LOG_IEEE_eg %T2_W<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = MUL %C8_X, %T2_W<kill>, pred:%PRED_SEL_OFF
>	%T6_X<def> = ADD %C13_Y, %C9_Y, pred:%PRED_SEL_OFF
>	%T6_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T5_W<def> = MULADD_eg %T1_Z, %C2_X, %T5_W<kill>, pred:%PRED_SEL_OFF
>	%T0_Y<def> = MOV %C16_Y, 0, pred:%noreg, %T0_XYZW<imp-def>
>	BUNDLE %T4_X<imp-def>, %T4_Y<imp-def>, %T4_Z<imp-def>, %T4_W<imp-def>, %T4_X<imp-use>, %T0_X<imp-use>, %T4_Y<imp-use>, %T0_Y<imp-use>, %T4_Z<imp-use>, %T0_Z<imp-use>, %T4_W<imp-use>, %T0_W<imp-use>
>	  * %T4_X<def> = DOT4_eg %T4_X, %T0_X, 32; flags: 
>	  * %T4_Y<def> = DOT4_eg %T4_Y, %T0_Y, 40; flags: 
>	  * %T4_Z<def> = DOT4_eg %T4_Z, %T0_Z, 40; flags: 
>	  * %T4_W<def> = DOT4_eg %T4_W, %T0_W, 8; flags: 
>	%T2_W<def> = MAX %T4_X, %T2_X, pred:%PRED_SEL_OFF
>	%T4_Z<def> = ADD %C13_Z, %C9_Z, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T2_Y, %C15_X, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_W<def> = MULADD_eg %T2_Z, %C14_Y, %T6_X<kill>, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T6_Y<kill>, pred:%PRED_SEL_OFF
>	%T6_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MULADD_eg %T1_W, %C3_X, %T5_W<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = EXP_IEEE_eg %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = CNDGE_eg %T4_X<kill>, %T5_X<kill>, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_Z, %C2_Z, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T6_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MULADD_eg %T2_Z<kill>, %C14_Z, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_W, %C3_Y, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MULADD_eg %T2_Y, %C15_Y, %T4_W<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = ADD %C19_X, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T2_W, %C20_X, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_W, %C3_Z, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MULADD_eg %T2_Y<kill>, %C15_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = ADD %C19_Y, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MULADD_eg %T4_X, %C21_X, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = ADD %C19_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T2_W, %C20_Y, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T1_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MOV %T2_X<kill>, 0, pred:%noreg
>	%T2_X<def> = MULADD_eg %T2_W<kill>, %C20_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_W<def> = MULADD_eg %T4_X, %C21_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MULADD_eg %T4_X<kill>, %C21_Z, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %C9_W, 1, pred:%PRED_SEL_OFF
>	%T4_X<def> = MUL %C22_X, %C23_X, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MUL %C22_X, %C23_Y, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %C22_Y, %C24_X, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %C22_Y, %C24_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_W<def> = MUL %C22_X, %C23_Z, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MUL %C22_X, %C23_W, pred:%PRED_SEL_OFF
>	%T4_W<def> = MULADD_eg %C22_Y, %C24_Z, %T4_W<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %C22_Z, %C25_X, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %C22_Z, %C25_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MULADD_eg %C22_Y, %C24_W, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_W<def> = MULADD_eg %C22_Z, %C25_Z, %T4_W<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %C22_W, %C26_X, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %C22_W, %C26_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = MULADD_eg %C22_Z, %C25_W, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MULADD_eg %C22_W, %C26_Z, %T4_W<kill>, pred:%PRED_SEL_OFF
>	%T4_W<def> = MULADD_eg %C22_W, %C26_W, %T5_X<kill>, pred:%PRED_SEL_OFF
>	RETURN %T4_W<imp-use,kill>, %T4_Z<imp-use,kill>, %T4_Y<imp-use,kill>, %T4_X<imp-use,kill>, %T3_W<imp-use,kill>, %T3_Z<imp-use,kill>, %T3_Y<imp-use,kill>, %T3_X<imp-use,kill>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 280 dw -- 8 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 80000006 ALU ADDR:12 KCACHE_MODE0:2 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A1DC0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:120
>0012 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 00000C90 * INST:0x19 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 80000084   SRC0(SEL:132 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0015 00800C90 * INST:0x19 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 80000086   SRC0(SEL:134 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 00E00C90 * INST:0x19 DST(SEL:7 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 80000085   SRC0(SEL:133 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0019 00C00C90 * INST:0x19 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 8000008C   SRC0(SEL:140 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 00A00C90 * INST:0x19 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 800000F8   SRC0(SEL:248 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0023 00400C90 * INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 60800C90 * INST:0x19 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 00000884   SRC0(SEL:132 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 40800C90   INST:0x19 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 00000484   SRC0(SEL:132 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0031 20800C90   INST:0x19 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0033 40000C90   INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0035 60E00C90 * INST:0x19 DST(SEL:7 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0037 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 00000886   SRC0(SEL:134 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 40E00C90   INST:0x19 DST(SEL:7 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0040 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0041 60C00C90 * INST:0x19 DST(SEL:6 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 00008000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:4 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0043 00405F00   INST:0xbe DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0044 008084FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:4 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 20405F10   INST:0xbe DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 01008800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:4 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 40405F00   INST:0xbe DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 81808C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:4 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0049 60405F00 * INST:0xbe DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 0010E0FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:135 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0051 00800090   INST:0x1 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0052 80000885   SRC0(SEL:133 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 40C00C90 * INST:0x19 DST(SEL:6 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0054 80000486   SRC0(SEL:134 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0055 20E00C90 * INST:0x19 DST(SEL:7 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0056 0000E000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:7 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0057 00405F00   INST:0xbe DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0058 009FC400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0059 20405F10   INST:0xbe DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0060 0100E800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:7 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0061 40405F00   INST:0xbe DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0062 8180EC00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:7 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0063 60405F00 * INST:0xbe DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0064 00000485   SRC0(SEL:133 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0065 20C00C90   INST:0x19 DST(SEL:6 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0066 8110E0FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:135 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0067 40400090 * INST:0x1 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0068 0000C000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:6 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0069 00405F00   INST:0xbe DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0070 009FC400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0071 20405F10   INST:0xbe DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0072 0100C800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:6 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0073 40405F00   INST:0xbe DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0074 8180CC00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:6 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0075 60405F00 * INST:0xbe DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0076 0090E0FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:135 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0077 20400090   INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0078 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0079 60800C90 * INST:0x19 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0080 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0081 40800C90   INST:0x19 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0082 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0083 60A00C90 * INST:0x19 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0084 00000092   SRC0(SEL:146 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0085 00000C90   INST:0x19 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0086 8000088C   SRC0(SEL:140 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0087 40A00C90 * INST:0x19 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0088 0000008A   SRC0(SEL:138 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0089 00C00C90   INST:0x19 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0090 0000048C   SRC0(SEL:140 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0091 20A00C90   INST:0x19 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0092 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0093 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0094 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0095 20800C90   INST:0x19 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0096 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0097 60C00C90 * INST:0x19 DST(SEL:6 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0098 0000A004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:5 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0099 00405F00   INST:0xbe DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0100 0080A4FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:5 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0101 20405F10   INST:0xbe DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0102 0100A804   SRC0(SEL:4 REL:0 CHAN:2 NEG:0) SRC1(SEL:5 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0103 40405F00   INST:0xbe DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0104 8180AC04   SRC0(SEL:4 REL:0 CHAN:3 NEG:0) SRC1(SEL:5 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0105 60405F00 * INST:0xbe DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0106 000040FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0107 20400190   INST:0x3 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0108 80000892   SRC0(SEL:146 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0109 40000C90 * INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0110 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0111 20404190   INST:0x83 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0112 8000088A   SRC0(SEL:138 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0113 40C00C90 * INST:0x19 DST(SEL:6 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0114 8000048A   SRC0(SEL:138 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0115 20C00C90 * INST:0x19 DST(SEL:6 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0116 80000492   SRC0(SEL:146 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0117 20000C90 * INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0118 00000004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0119 00405F00   INST:0xbe DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0120 009FC404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0121 20405F00   INST:0xbe DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0122 01000804   SRC0(SEL:4 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0123 40405F10   INST:0xbe DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0124 81800C04   SRC0(SEL:4 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0125 60405F00 * INST:0xbe DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0126 00000090   SRC0(SEL:144 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0127 00000C90   INST:0x19 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0128 800040FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0129 60400190 * INST:0x3 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0130 0000C004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:6 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0131 00A05F10   INST:0xbe DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0132 0080C404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:6 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0133 20A05F00   INST:0xbe DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0134 0100C804   SRC0(SEL:4 REL:0 CHAN:2 NEG:0) SRC1(SEL:6 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0135 40A05F00   INST:0xbe DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0136 8180CC04   SRC0(SEL:4 REL:0 CHAN:3 NEG:0) SRC1(SEL:6 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0137 60A05F00 * INST:0xbe DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0138 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0139 20A00090 * INST:0x1 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0140 80004005   SRC0(SEL:5 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0141 40400190 * INST:0x3 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0142 00804088   SRC0(SEL:136 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0143 20400090   INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0144 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0145 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0146 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0147 40A00090 * INST:0x1 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0148 00000890   SRC0(SEL:144 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0149 40000C90   INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0150 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0151 60A28405 * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0152 80000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0153 20404090 * INST:0x81 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0154 0011208D   SRC0(SEL:141 REL:0 CHAN:0 NEG:0) SRC1(SEL:137 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0155 00A00010   INST:0x0 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0156 809FC005   SRC0(SEL:5 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0157 20436002 * INST:0x1b DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:0 NEG:0)
>0158 0011C802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:142 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0159 20A280FE   INST:0x14 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0160 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0161 60404190 * INST:0x83 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0162 819FC088   SRC0(SEL:136 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0163 00A00090 * INST:0x1 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0164 8091248D   SRC0(SEL:141 REL:0 CHAN:1 NEG:0) SRC1(SEL:137 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0165 00C00010 * INST:0x0 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0166 00902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0167 20C28805   INST:0x14 DST(SEL:6 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0168 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0169 40A00090 * INST:0x1 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0170 00000490   SRC0(SEL:144 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0171 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0172 80104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0173 60A28C05 * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:3 NEG:0)
>0174 00000004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0175 00805F10   INST:0xbe DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0176 009FC404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0177 20805F00   INST:0xbe DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0178 01000804   SRC0(SEL:4 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0179 40805F00   INST:0xbe DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0180 81800C04   SRC0(SEL:4 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0181 60805F00 * INST:0xbe DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0182 0111288D   SRC0(SEL:141 REL:0 CHAN:2 NEG:0) SRC1(SEL:137 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0183 40800010   INST:0x0 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0184 800040FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0185 60400190 * INST:0x3 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0186 0011E402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:143 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0187 20828405   INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0188 8091C802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:142 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0189 60828006 * INST:0x14 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:0 NEG:0)
>0190 01900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0191 00C00090   INST:0x1 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0192 80904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0193 20A28406 * INST:0x14 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:1 NEG:0)
>0194 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0195 00228C05   INST:0x14 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:3 NEG:0)
>0196 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0197 40A28805 * INST:0x14 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0198 80000005   SRC0(SEL:5 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0199 00A04090 * INST:0x81 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0200 801FC004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0201 00836002 * INST:0x1b DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:0 NEG:0)
>0202 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0203 00428805 * INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0204 01902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0205 00A28006   INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:0 NEG:0)
>0206 8111C802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:142 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0207 40428804 * INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:2 NEG:0)
>0208 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0209 20228405   INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0210 8091E402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:143 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0211 40828C04 * INST:0x14 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:3 NEG:0)
>0212 80808093   SRC0(SEL:147 REL:0 CHAN:0 NEG:0) SRC1(SEL:4 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0213 20800010 * INST:0x0 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0214 01106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0215 004A8002   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:2 SRC2(SEL:2 REL:0 CHAN:0 NEG:0)
>0216 80128C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:148 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0217 208284FE * INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0218 81904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0219 40228005 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:0 NEG:0)
>0220 8111E402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:143 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0221 40428802 * INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:2 NEG:0)
>0222 0012A004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:149 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0223 20428404   INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:1 NEG:0)
>0224 81008493   SRC0(SEL:147 REL:0 CHAN:1 NEG:0) SRC1(SEL:4 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0225 40800010 * INST:0x0 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0226 00928C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:148 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0227 208288FE   INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0228 81004893   SRC0(SEL:147 REL:0 CHAN:2 NEG:0) SRC1(SEL:2 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0229 40400010 * INST:0x0 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0230 01128C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:148 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0231 004A88FE   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:2 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0232 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0233 40200C90   INST:0x19 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0234 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0235 60228801 * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:1 REL:0 CHAN:2 NEG:0)
>0236 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0237 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0238 0112A004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:149 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0239 404280FE   INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0240 8092A004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:149 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0241 60428404 * INST:0x14 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:1 NEG:0)
>0242 00000CFE   SRC0(SEL:254 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0243 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0244 000008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0245 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0246 80000C89   SRC0(SEL:137 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0247 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0248 0012E096   SRC0(SEL:150 REL:0 CHAN:0 NEG:0) SRC1(SEL:151 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0249 00800090   INST:0x1 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0250 8092E096   SRC0(SEL:150 REL:0 CHAN:0 NEG:0) SRC1(SEL:151 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0251 20800090 * INST:0x1 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 4000007E ALU ADDR:252 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0005 A0340004 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:1 KCACHE_ADDR1:0 COUNT:14
>0252 00110486   SRC0(SEL:134 REL:0 CHAN:1 NEG:0) SRC1(SEL:136 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0253 00828004   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:0 NEG:0)
>0254 80910486   SRC0(SEL:134 REL:0 CHAN:1 NEG:0) SRC1(SEL:136 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0255 20828404 * INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:1 NEG:0)
>0256 0190E086   SRC0(SEL:134 REL:0 CHAN:0 NEG:0) SRC1(SEL:135 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0257 40800090   INST:0x1 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0258 8110E086   SRC0(SEL:134 REL:0 CHAN:0 NEG:0) SRC1(SEL:135 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0259 60800090 * INST:0x1 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0260 81110486   SRC0(SEL:134 REL:0 CHAN:1 NEG:0) SRC1(SEL:136 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0261 60828CFE * INST:0x14 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:3 NEG:0)
>0262 00112886   SRC0(SEL:134 REL:0 CHAN:2 NEG:0) SRC1(SEL:137 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0263 00828004   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:0 NEG:0)
>0264 80912886   SRC0(SEL:134 REL:0 CHAN:2 NEG:0) SRC1(SEL:137 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0265 20828404 * INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:1 NEG:0)
>0266 81910486   SRC0(SEL:134 REL:0 CHAN:1 NEG:0) SRC1(SEL:136 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0267 40828804 * INST:0x14 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:2 NEG:0)
>0268 81112886   SRC0(SEL:134 REL:0 CHAN:2 NEG:0) SRC1(SEL:137 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0269 60828C04 * INST:0x14 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:3 NEG:0)
>0270 00114C86   SRC0(SEL:134 REL:0 CHAN:3 NEG:0) SRC1(SEL:138 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0271 00828004   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:0 NEG:0)
>0272 80914C86   SRC0(SEL:134 REL:0 CHAN:3 NEG:0) SRC1(SEL:138 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0273 20828404 * INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:1 NEG:0)
>0274 81912886   SRC0(SEL:134 REL:0 CHAN:2 NEG:0) SRC1(SEL:137 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0275 00A28804 * INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:2 NEG:0)
>0276 01114C86   SRC0(SEL:134 REL:0 CHAN:3 NEG:0) SRC1(SEL:138 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0277 40828C04   INST:0x14 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:3 NEG:0)
>0278 81914C86   SRC0(SEL:134 REL:0 CHAN:3 NEG:0) SRC1(SEL:138 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0279 608280FE * INST:0x14 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0006 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0009 95020688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:3 EOP:0
>0010 00000000 CF ADDR:0
>0011 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 16 dw -- 4 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400800 TEX/VTX INST:0x1 COUNT:3
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 8C151001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:48 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 8C151002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:48 NUM:0 COMP:0 MODE:1)
>0010 0000000C   ENDIAN:0 OFFSET:12
>0011 00000000   
>0012 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0013 87961003   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:3 SEL_X:0 SEL_Y:1 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:30 NUM:0 COMP:0 MODE:1)
>0014 00000018   ENDIAN:0 OFFSET:24
>0015 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.AMDGPU.load.const(i32 0)
>  %9 = call float @llvm.AMDGPU.mul(float %0, float %8)
>  %10 = call float @llvm.AMDGPU.load.const(i32 1)
>  %11 = call float @llvm.AMDGPU.mul(float %0, float %10)
>  %12 = call float @llvm.AMDGPU.load.const(i32 2)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 3)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 4)
>  %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9)
>  %18 = call float @llvm.AMDGPU.load.const(i32 5)
>  %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11)
>  %20 = call float @llvm.AMDGPU.load.const(i32 6)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 7)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 8)
>  %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 9)
>  %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 10)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 11)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 12)
>  %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 13)
>  %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 14)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 15)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  call void @llvm.AMDGPU.store.output(float %33, i32 4)
>  call void @llvm.AMDGPU.store.output(float %35, i32 5)
>  call void @llvm.AMDGPU.store.output(float %37, i32 6)
>  call void @llvm.AMDGPU.store.output(float %39, i32 7)
>  call void @llvm.AMDGPU.store.output(float %4, i32 8)
>  call void @llvm.AMDGPU.store.output(float %5, i32 9)
>  call void @llvm.AMDGPU.store.output(float %6, i32 10)
>  call void @llvm.AMDGPU.store.output(float %7, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T3_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T3_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T3_X<kill>, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 46 dw -- 4 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0440000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:18
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00600090 * INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 006280FE * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 206284FE * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 206284FE   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20628403   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 006284FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228803 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0044 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0045 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400400 TEX/VTX INST:0x1 COUNT:2
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 8C151001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:48 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 87961002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:30 NUM:0 COMP:0 MODE:1)
>0010 00000018   ENDIAN:0 OFFSET:24
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.AMDGPU.load.const(i32 0)
>  %9 = call float @llvm.AMDGPU.mul(float %0, float %8)
>  %10 = call float @llvm.AMDGPU.load.const(i32 1)
>  %11 = call float @llvm.AMDGPU.mul(float %0, float %10)
>  %12 = call float @llvm.AMDGPU.load.const(i32 2)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 3)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 4)
>  %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9)
>  %18 = call float @llvm.AMDGPU.load.const(i32 5)
>  %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11)
>  %20 = call float @llvm.AMDGPU.load.const(i32 6)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 7)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 8)
>  %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 9)
>  %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 10)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 11)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 12)
>  %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 13)
>  %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 14)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 15)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  call void @llvm.AMDGPU.store.output(float %33, i32 4)
>  call void @llvm.AMDGPU.store.output(float %35, i32 5)
>  call void @llvm.AMDGPU.store.output(float %37, i32 6)
>  call void @llvm.AMDGPU.store.output(float %39, i32 7)
>  call void @llvm.AMDGPU.store.output(float %4, i32 8)
>  call void @llvm.AMDGPU.store.output(float %5, i32 9)
>  call void @llvm.AMDGPU.store.output(float %6, i32 10)
>  call void @llvm.AMDGPU.store.output(float %7, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T3_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T3_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T3_X<kill>, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 46 dw -- 4 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0440000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:18
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00600090 * INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 006280FE * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 206284FE * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 206284FE   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20628403   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 406288FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 006284FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228803 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0044 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0045 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.R600.load.input(i32 12)
>  %9 = call float @llvm.R600.load.input(i32 13)
>  %10 = call float @llvm.R600.load.input(i32 14)
>  %11 = call float @llvm.R600.load.input(i32 15)
>  %12 = call float @llvm.AMDGPU.load.const(i32 0)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 1)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 2)
>  %17 = call float @llvm.AMDGPU.mul(float %0, float %16)
>  %18 = call float @llvm.AMDGPU.load.const(i32 3)
>  %19 = call float @llvm.AMDGPU.mul(float %0, float %18)
>  %20 = call float @llvm.AMDGPU.load.const(i32 4)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 5)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 6)
>  %25 = call float @llvm.AMDIL.mad.(float %1, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 7)
>  %27 = call float @llvm.AMDIL.mad.(float %1, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 8)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 9)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 10)
>  %33 = call float @llvm.AMDIL.mad.(float %2, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 11)
>  %35 = call float @llvm.AMDIL.mad.(float %2, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 12)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 13)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  %40 = call float @llvm.AMDGPU.load.const(i32 14)
>  %41 = call float @llvm.AMDIL.mad.(float %3, float %40, float %33)
>  %42 = call float @llvm.AMDGPU.load.const(i32 15)
>  %43 = call float @llvm.AMDIL.mad.(float %3, float %42, float %35)
>  %44 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00)
>  %45 = call float @llvm.AMDIL.clamp.(float %5, float 0.000000e+00, float 1.000000e+00)
>  %46 = call float @llvm.AMDIL.clamp.(float %6, float 0.000000e+00, float 1.000000e+00)
>  %47 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %37, i32 4)
>  call void @llvm.AMDGPU.store.output(float %39, i32 5)
>  call void @llvm.AMDGPU.store.output(float %41, i32 6)
>  call void @llvm.AMDGPU.store.output(float %43, i32 7)
>  call void @llvm.AMDGPU.store.output(float %44, i32 8)
>  call void @llvm.AMDGPU.store.output(float %45, i32 9)
>  call void @llvm.AMDGPU.store.output(float %46, i32 10)
>  call void @llvm.AMDGPU.store.output(float %47, i32 11)
>  call void @llvm.AMDGPU.store.output(float %8, i32 12)
>  call void @llvm.AMDGPU.store.output(float %9, i32 13)
>  call void @llvm.AMDGPU.store.output(float %10, i32 14)
>  call void @llvm.AMDGPU.store.output(float %11, i32 15)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T3_W in %vreg0, %T3_Z in %vreg1, %T3_Y in %vreg2, %T3_X in %vreg3, %T2_W in %vreg4, %T2_Z in %vreg5, %T2_Y in %vreg6, %T2_X in %vreg7, %T1_W in %vreg8, %T1_Z in %vreg9, %T1_Y in %vreg10, %T1_X in %vreg11
>Function Live Outs: %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T4_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %T1_Y, %C1_X, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %T1_Z, %C2_X, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %T1_W, %C3_X, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MULADD_eg %T1_Z, %C2_Z, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T1_W, %C3_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T4_X<kill>, 0, pred:%noreg
>	%T4_X<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_W, %C3_Z, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T4_Y<kill>, 0, pred:%noreg
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T3_W<imp-use,kill>, %T3_Z<imp-use,kill>, %T3_Y<imp-use,kill>, %T3_X<imp-use,kill>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 54 dw -- 5 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000005 ALU ADDR:10 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A0540000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:22
>0010 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00800090 * INST:0x1 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 008280FE * INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0014 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 008280FE   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0016 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 20800090 * INST:0x1 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 008280FE   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0020 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 208284FE * INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0022 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 208284FE   INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0024 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 40800090 * INST:0x1 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 408288FE * INST:0x14 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0028 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20828404   INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:1 NEG:0)
>0030 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 408288FE * INST:0x14 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0032 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 202280FE * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 01904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 008284FE   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00000404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 40228804 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:2 NEG:0)
>0044 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 602280FE * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0052 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95010688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:2 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..21]
>DCL TEMP[0..3]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: MUL TEMP[0], TEMP[0], CONST[7]
>  8: MOV TEMP[1].w, CONST[8].xxxx
>  9: MOV TEMP[2], CONST[9]
> 10: MOV_SAT OUT[1], TEMP[2]
> 11: DP3 TEMP[1].x, TEMP[0], CONST[10]
> 12: DP3 TEMP[1].y, TEMP[0], CONST[12]
> 13: LIT TEMP[3], TEMP[1]
> 14: ADD TEMP[2], CONST[13], TEMP[2]
> 15: MAD TEMP[2], TEMP[3].yyyy, CONST[14], TEMP[2]
> 16: MAD TEMP[2], TEMP[3].zzzz, CONST[15], TEMP[2]
> 17: DP3 TEMP[1].x, TEMP[0], CONST[16]
> 18: DP3 TEMP[1].y, TEMP[0], CONST[18]
> 19: LIT TEMP[3], TEMP[1]
> 20: ADD TEMP[2], CONST[19], TEMP[2]
> 21: MAD TEMP[2], TEMP[3].yyyy, CONST[20], TEMP[2]
> 22: MAD_SAT OUT[1].xyz, TEMP[3].zzzz, CONST[21], TEMP[2]
> 23: MOV OUT[2], IN[2]
> 24: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.R600.load.input(i32 12)
>  %9 = call float @llvm.R600.load.input(i32 13)
>  %10 = call float @llvm.R600.load.input(i32 14)
>  %11 = call float @llvm.R600.load.input(i32 15)
>  %12 = call float @llvm.AMDGPU.load.const(i32 0)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 1)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 2)
>  %17 = call float @llvm.AMDGPU.mul(float %0, float %16)
>  %18 = call float @llvm.AMDGPU.load.const(i32 3)
>  %19 = call float @llvm.AMDGPU.mul(float %0, float %18)
>  %20 = call float @llvm.AMDGPU.load.const(i32 4)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 5)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 6)
>  %25 = call float @llvm.AMDIL.mad.(float %1, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 7)
>  %27 = call float @llvm.AMDIL.mad.(float %1, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 8)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 9)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 10)
>  %33 = call float @llvm.AMDIL.mad.(float %2, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 11)
>  %35 = call float @llvm.AMDIL.mad.(float %2, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 12)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 13)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  %40 = call float @llvm.AMDGPU.load.const(i32 14)
>  %41 = call float @llvm.AMDIL.mad.(float %3, float %40, float %33)
>  %42 = call float @llvm.AMDGPU.load.const(i32 15)
>  %43 = call float @llvm.AMDIL.mad.(float %3, float %42, float %35)
>  %44 = call float @llvm.AMDGPU.load.const(i32 16)
>  %45 = call float @llvm.AMDGPU.load.const(i32 17)
>  %46 = call float @llvm.AMDGPU.load.const(i32 18)
>  %47 = insertelement <4 x float> undef, float %4, i32 0
>  %48 = insertelement <4 x float> %47, float %5, i32 1
>  %49 = insertelement <4 x float> %48, float %6, i32 2
>  %50 = insertelement <4 x float> %49, float 0.000000e+00, i32 3
>  %51 = insertelement <4 x float> undef, float %44, i32 0
>  %52 = insertelement <4 x float> %51, float %45, i32 1
>  %53 = insertelement <4 x float> %52, float %46, i32 2
>  %54 = insertelement <4 x float> %53, float 0.000000e+00, i32 3
>  %55 = call float @llvm.AMDGPU.dp4(<4 x float> %50, <4 x float> %54)
>  %56 = call float @llvm.AMDGPU.load.const(i32 20)
>  %57 = call float @llvm.AMDGPU.load.const(i32 21)
>  %58 = call float @llvm.AMDGPU.load.const(i32 22)
>  %59 = insertelement <4 x float> undef, float %4, i32 0
>  %60 = insertelement <4 x float> %59, float %5, i32 1
>  %61 = insertelement <4 x float> %60, float %6, i32 2
>  %62 = insertelement <4 x float> %61, float 0.000000e+00, i32 3
>  %63 = insertelement <4 x float> undef, float %56, i32 0
>  %64 = insertelement <4 x float> %63, float %57, i32 1
>  %65 = insertelement <4 x float> %64, float %58, i32 2
>  %66 = insertelement <4 x float> %65, float 0.000000e+00, i32 3
>  %67 = call float @llvm.AMDGPU.dp4(<4 x float> %62, <4 x float> %66)
>  %68 = call float @llvm.AMDGPU.load.const(i32 24)
>  %69 = call float @llvm.AMDGPU.load.const(i32 25)
>  %70 = call float @llvm.AMDGPU.load.const(i32 26)
>  %71 = insertelement <4 x float> undef, float %4, i32 0
>  %72 = insertelement <4 x float> %71, float %5, i32 1
>  %73 = insertelement <4 x float> %72, float %6, i32 2
>  %74 = insertelement <4 x float> %73, float 0.000000e+00, i32 3
>  %75 = insertelement <4 x float> undef, float %68, i32 0
>  %76 = insertelement <4 x float> %75, float %69, i32 1
>  %77 = insertelement <4 x float> %76, float %70, i32 2
>  %78 = insertelement <4 x float> %77, float 0.000000e+00, i32 3
>  %79 = call float @llvm.AMDGPU.dp4(<4 x float> %74, <4 x float> %78)
>  %80 = call float @llvm.AMDGPU.load.const(i32 28)
>  %81 = call float @llvm.AMDGPU.mul(float %55, float %80)
>  %82 = call float @llvm.AMDGPU.load.const(i32 29)
>  %83 = call float @llvm.AMDGPU.mul(float %67, float %82)
>  %84 = call float @llvm.AMDGPU.load.const(i32 30)
>  %85 = call float @llvm.AMDGPU.mul(float %79, float %84)
>  %86 = call float @llvm.AMDGPU.load.const(i32 31)
>  %87 = call float @llvm.AMDGPU.mul(float %35, float %86)
>  %88 = call float @llvm.AMDGPU.load.const(i32 32)
>  %89 = call float @llvm.AMDGPU.load.const(i32 36)
>  %90 = call float @llvm.AMDGPU.load.const(i32 37)
>  %91 = call float @llvm.AMDGPU.load.const(i32 38)
>  %92 = call float @llvm.AMDGPU.load.const(i32 39)
>  %93 = call float @llvm.AMDIL.clamp.(float %89, float 0.000000e+00, float 1.000000e+00)
>  %94 = call float @llvm.AMDIL.clamp.(float %90, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %91, float 0.000000e+00, float 1.000000e+00)
>  %96 = call float @llvm.AMDIL.clamp.(float %92, float 0.000000e+00, float 1.000000e+00)
>  %97 = call float @llvm.AMDGPU.load.const(i32 40)
>  %98 = call float @llvm.AMDGPU.load.const(i32 41)
>  %99 = call float @llvm.AMDGPU.load.const(i32 42)
>  %100 = insertelement <4 x float> undef, float %81, i32 0
>  %101 = insertelement <4 x float> %100, float %83, i32 1
>  %102 = insertelement <4 x float> %101, float %85, i32 2
>  %103 = insertelement <4 x float> %102, float 0.000000e+00, i32 3
>  %104 = insertelement <4 x float> undef, float %97, i32 0
>  %105 = insertelement <4 x float> %104, float %98, i32 1
>  %106 = insertelement <4 x float> %105, float %99, i32 2
>  %107 = insertelement <4 x float> %106, float 0.000000e+00, i32 3
>  %108 = call float @llvm.AMDGPU.dp4(<4 x float> %103, <4 x float> %107)
>  %109 = call float @llvm.AMDGPU.load.const(i32 48)
>  %110 = call float @llvm.AMDGPU.load.const(i32 49)
>  %111 = call float @llvm.AMDGPU.load.const(i32 50)
>  %112 = insertelement <4 x float> undef, float %81, i32 0
>  %113 = insertelement <4 x float> %112, float %83, i32 1
>  %114 = insertelement <4 x float> %113, float %85, i32 2
>  %115 = insertelement <4 x float> %114, float 0.000000e+00, i32 3
>  %116 = insertelement <4 x float> undef, float %109, i32 0
>  %117 = insertelement <4 x float> %116, float %110, i32 1
>  %118 = insertelement <4 x float> %117, float %111, i32 2
>  %119 = insertelement <4 x float> %118, float 0.000000e+00, i32 3
>  %120 = call float @llvm.AMDGPU.dp4(<4 x float> %115, <4 x float> %119)
>  %121 = call float @llvm.AMDIL.max.(float %108, float 0.000000e+00)
>  %122 = call float @llvm.AMDIL.max.(float %120, float 0.000000e+00)
>  %123 = call float @llvm.AMDGPU.pow(float %122, float %88)
>  %124 = call float @llvm.AMDGPU.cndlt(float %108, float 0.000000e+00, float %123)
>  %125 = call float @llvm.AMDGPU.load.const(i32 52)
>  %126 = fadd float %125, %89
>  %127 = call float @llvm.AMDGPU.load.const(i32 53)
>  %128 = fadd float %127, %90
>  %129 = call float @llvm.AMDGPU.load.const(i32 54)
>  %130 = fadd float %129, %91
>  %131 = call float @llvm.AMDGPU.load.const(i32 55)
>  %132 = fadd float %131, %92
>  %133 = call float @llvm.AMDGPU.load.const(i32 56)
>  %134 = call float @llvm.AMDIL.mad.(float %121, float %133, float %126)
>  %135 = call float @llvm.AMDGPU.load.const(i32 57)
>  %136 = call float @llvm.AMDIL.mad.(float %121, float %135, float %128)
>  %137 = call float @llvm.AMDGPU.load.const(i32 58)
>  %138 = call float @llvm.AMDIL.mad.(float %121, float %137, float %130)
>  %139 = call float @llvm.AMDGPU.load.const(i32 59)
>  %140 = call float @llvm.AMDIL.mad.(float %121, float %139, float %132)
>  %141 = call float @llvm.AMDGPU.load.const(i32 60)
>  %142 = call float @llvm.AMDIL.mad.(float %124, float %141, float %134)
>  %143 = call float @llvm.AMDGPU.load.const(i32 61)
>  %144 = call float @llvm.AMDIL.mad.(float %124, float %143, float %136)
>  %145 = call float @llvm.AMDGPU.load.const(i32 62)
>  %146 = call float @llvm.AMDIL.mad.(float %124, float %145, float %138)
>  %147 = call float @llvm.AMDGPU.load.const(i32 63)
>  %148 = call float @llvm.AMDIL.mad.(float %124, float %147, float %140)
>  %149 = call float @llvm.AMDGPU.load.const(i32 64)
>  %150 = call float @llvm.AMDGPU.load.const(i32 65)
>  %151 = call float @llvm.AMDGPU.load.const(i32 66)
>  %152 = insertelement <4 x float> undef, float %81, i32 0
>  %153 = insertelement <4 x float> %152, float %83, i32 1
>  %154 = insertelement <4 x float> %153, float %85, i32 2
>  %155 = insertelement <4 x float> %154, float 0.000000e+00, i32 3
>  %156 = insertelement <4 x float> undef, float %149, i32 0
>  %157 = insertelement <4 x float> %156, float %150, i32 1
>  %158 = insertelement <4 x float> %157, float %151, i32 2
>  %159 = insertelement <4 x float> %158, float 0.000000e+00, i32 3
>  %160 = call float @llvm.AMDGPU.dp4(<4 x float> %155, <4 x float> %159)
>  %161 = call float @llvm.AMDGPU.load.const(i32 72)
>  %162 = call float @llvm.AMDGPU.load.const(i32 73)
>  %163 = call float @llvm.AMDGPU.load.const(i32 74)
>  %164 = insertelement <4 x float> undef, float %81, i32 0
>  %165 = insertelement <4 x float> %164, float %83, i32 1
>  %166 = insertelement <4 x float> %165, float %85, i32 2
>  %167 = insertelement <4 x float> %166, float 0.000000e+00, i32 3
>  %168 = insertelement <4 x float> undef, float %161, i32 0
>  %169 = insertelement <4 x float> %168, float %162, i32 1
>  %170 = insertelement <4 x float> %169, float %163, i32 2
>  %171 = insertelement <4 x float> %170, float 0.000000e+00, i32 3
>  %172 = call float @llvm.AMDGPU.dp4(<4 x float> %167, <4 x float> %171)
>  %173 = call float @llvm.AMDIL.max.(float %160, float 0.000000e+00)
>  %174 = call float @llvm.AMDIL.max.(float %172, float 0.000000e+00)
>  %175 = call float @llvm.AMDGPU.pow(float %174, float %88)
>  %176 = call float @llvm.AMDGPU.cndlt(float %160, float 0.000000e+00, float %175)
>  %177 = call float @llvm.AMDGPU.load.const(i32 76)
>  %178 = fadd float %177, %142
>  %179 = call float @llvm.AMDGPU.load.const(i32 77)
>  %180 = fadd float %179, %144
>  %181 = call float @llvm.AMDGPU.load.const(i32 78)
>  %182 = fadd float %181, %146
>  %183 = call float @llvm.AMDGPU.load.const(i32 79)
>  %184 = fadd float %183, %148
>  %185 = call float @llvm.AMDGPU.load.const(i32 80)
>  %186 = call float @llvm.AMDIL.mad.(float %173, float %185, float %178)
>  %187 = call float @llvm.AMDGPU.load.const(i32 81)
>  %188 = call float @llvm.AMDIL.mad.(float %173, float %187, float %180)
>  %189 = call float @llvm.AMDGPU.load.const(i32 82)
>  %190 = call float @llvm.AMDIL.mad.(float %173, float %189, float %182)
>  %191 = call float @llvm.AMDGPU.load.const(i32 83)
>  %192 = call float @llvm.AMDIL.mad.(float %173, float %191, float %184)
>  %193 = call float @llvm.AMDGPU.load.const(i32 84)
>  %194 = call float @llvm.AMDIL.mad.(float %176, float %193, float %186)
>  %195 = call float @llvm.AMDGPU.load.const(i32 85)
>  %196 = call float @llvm.AMDIL.mad.(float %176, float %195, float %188)
>  %197 = call float @llvm.AMDGPU.load.const(i32 86)
>  %198 = call float @llvm.AMDIL.mad.(float %176, float %197, float %190)
>  %199 = call float @llvm.AMDIL.clamp.(float %194, float 0.000000e+00, float 1.000000e+00)
>  %200 = call float @llvm.AMDIL.clamp.(float %196, float 0.000000e+00, float 1.000000e+00)
>  %201 = call float @llvm.AMDIL.clamp.(float %198, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %37, i32 4)
>  call void @llvm.AMDGPU.store.output(float %39, i32 5)
>  call void @llvm.AMDGPU.store.output(float %41, i32 6)
>  call void @llvm.AMDGPU.store.output(float %43, i32 7)
>  call void @llvm.AMDGPU.store.output(float %199, i32 8)
>  call void @llvm.AMDGPU.store.output(float %200, i32 9)
>  call void @llvm.AMDGPU.store.output(float %201, i32 10)
>  call void @llvm.AMDGPU.store.output(float %96, i32 11)
>  call void @llvm.AMDGPU.store.output(float %8, i32 12)
>  call void @llvm.AMDGPU.store.output(float %9, i32 13)
>  call void @llvm.AMDGPU.store.output(float %10, i32 14)
>  call void @llvm.AMDGPU.store.output(float %11, i32 15)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare float @llvm.AMDIL.max.(float, float) readnone
>
>declare float @llvm.AMDGPU.pow(float, float) readnone
>
>declare float @llvm.AMDGPU.cndlt(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T3_W in %vreg0, %T3_Z in %vreg1, %T3_Y in %vreg2, %T3_X in %vreg3, %T2_Z in %vreg4, %T2_Y in %vreg5, %T2_X in %vreg6, %T1_W in %vreg7, %T1_Z in %vreg8, %T1_Y in %vreg9, %T1_X in %vreg10
>Function Live Outs: %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T3_W %T3_Z %T3_Y %T3_X %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T0_X<def> = MOV %T2_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T4_X<def> = MOV %C4_X, 0, pred:%noreg, %T4_XYZW<imp-def>
>	%T7_X<def> = MOV %C6_X, 0, pred:%noreg, %T7_XYZW<imp-def>
>	%T6_X<def> = MOV %C5_X, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T5_X<def> = MOV %C12_X, 0, pred:%noreg, %T5_XYZW<imp-def>
>	%T2_X<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 0.000000e+00
>	%T4_W<def> = MOV %T2_X, 0, pred:%noreg, %T4_XYZW<imp-def>
>	%T0_W<def> = MOV %T2_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T4_Z<def> = MOV %C4_Z, 0, pred:%noreg, %T4_XYZW<imp-def>
>	%T0_Z<def> = MOV %T2_Z<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T4_Y<def> = MOV %C4_Y, 0, pred:%noreg, %T4_XYZW<imp-def>
>	%T7_W<def> = MOV %T2_X, 0, pred:%noreg, %T7_XYZW<imp-def>
>	%T6_W<def> = MOV %T2_X, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T7_Z<def> = MOV %C6_Z, 0, pred:%noreg, %T7_XYZW<imp-def>
>	%T0_Y<def> = MOV %T2_Y<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T0_X<imp-use>, %T4_X<imp-use>, %T0_Y<imp-use>, %T4_Y<imp-use>, %T0_Z<imp-use>, %T4_Z<imp-use>, %T0_W<imp-use>, %T4_W<imp-use>
>	  * %T2_X<def> = DOT4_eg %T0_X, %T4_X, 40; flags: 
>	  * %T2_Y<def> = DOT4_eg %T0_Y, %T4_Y, 32; flags: 
>	  * %T2_Z<def> = DOT4_eg %T0_Z, %T4_Z, 40; flags: 
>	  * %T2_W<def> = DOT4_eg %T0_W, %T4_W, 8; flags: 
>	%T4_X<def> = MUL %T2_Y<kill>, %C7_X, pred:%PRED_SEL_OFF, %T4_XYZW<imp-def>
>	%T6_Z<def> = MOV %C5_Z, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T7_Y<def> = MOV %C6_Y, 0, pred:%noreg, %T7_XYZW<imp-def>
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T0_X<imp-use>, %T7_X<imp-use>, %T0_Y<imp-use>, %T7_Y<imp-use>, %T0_Z<imp-use>, %T7_Z<imp-use>, %T0_W<imp-use>, %T7_W<imp-use>
>	  * %T2_X<def> = DOT4_eg %T0_X, %T7_X, 40; flags: 
>	  * %T2_Y<def> = DOT4_eg %T0_Y, %T7_Y, 32; flags: 
>	  * %T2_Z<def> = DOT4_eg %T0_Z, %T7_Z, 40; flags: 
>	  * %T2_W<def> = DOT4_eg %T0_W, %T7_W, 8; flags: 
>	%T2_Z<def> = MUL %T2_Y<kill>, %C7_Z, pred:%PRED_SEL_OFF
>	%T6_Y<def> = MOV %C5_Y, 0, pred:%noreg, %T6_XYZW<imp-def>
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T0_X<imp-use>, %T6_X<imp-use>, %T0_Y<imp-use>, %T6_Y<imp-use>, %T0_Z<imp-use>, %T6_Z<imp-use>, %T0_W<imp-use>, %T6_W<imp-use>
>	  * %T2_X<def> = DOT4_eg %T0_X, %T6_X, 40; flags: 
>	  * %T2_Y<def> = DOT4_eg %T0_Y, %T6_Y, 32; flags: 
>	  * %T2_Z<def> = DOT4_eg %T0_Z, %T6_Z, 40; flags: 
>	  * %T2_W<def> = DOT4_eg %T0_W, %T6_W, 8; flags: 
>	%T2_Y<def> = MUL %T2_Y<kill>, %C7_Y, pred:%PRED_SEL_OFF
>	%T4_W<def> = MOV %T2_X, 0, pred:%noreg, %T4_XYZW<imp-def>
>	%T5_W<def> = MOV %T2_X, 0, pred:%noreg, %T5_XYZW<imp-def>
>	%T4_Z<def> = MOV %T2_Z<kill>, 0, pred:%noreg, %T4_XYZW<imp-def>
>	%T5_Z<def> = MOV %C12_Z, 0, pred:%noreg, %T5_XYZW<imp-def>
>	%T0_X<def> = MOV %C18_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T5_Y<def> = MOV %C12_Y, 0, pred:%noreg, %T5_XYZW<imp-def>
>	%T6_X<def> = MOV %C10_X, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T0_W<def> = MOV %T2_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T6_W<def> = MOV %T2_X, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T4_Y<def> = MOV %T2_Y<kill>, 0, pred:%noreg, %T4_XYZW<imp-def>
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T4_X<imp-use>, %T5_X<imp-use>, %T4_Y<imp-use>, %T5_Y<imp-use>, %T4_Z<imp-use>, %T5_Z<imp-use>, %T4_W<imp-use>, %T5_W<imp-use>
>	  * %T2_X<def> = DOT4_eg %T4_X, %T5_X, 40; flags: 
>	  * %T2_Y<def> = DOT4_eg %T4_Y, %T5_Y, 32; flags: 
>	  * %T2_Z<def> = DOT4_eg %T4_Z, %T5_Z, 40; flags: 
>	  * %T2_W<def> = DOT4_eg %T4_W, %T5_W, 8; flags: 
>	%T2_Y<def> = MAX %T2_Y<kill>, %T2_X, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %C18_Z, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T6_Z<def> = MOV %C10_Z, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T2_Y<def> = LOG_IEEE_eg %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T6_Y<def> = MOV %C10_Y, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T0_Y<def> = MOV %C18_Y, 0, pred:%noreg, %T0_XYZW<imp-def>
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T4_X<imp-use>, %T0_X<imp-use>, %T4_Y<imp-use>, %T0_Y<imp-use>, %T4_Z<imp-use>, %T0_Z<imp-use>, %T4_W<imp-use>, %T0_W<imp-use>
>	  * %T2_X<def> = DOT4_eg %T4_X, %T0_X, 40; flags: 
>	  * %T2_Y<def> = DOT4_eg %T4_Y, %T0_Y, 40; flags: 
>	  * %T2_Z<def> = DOT4_eg %T4_Z, %T0_Z, 32; flags: 
>	  * %T2_W<def> = DOT4_eg %T4_W, %T0_W, 8; flags: 
>	%T0_X<def> = MOV %C16_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T2_W<def> = MAX %T2_Z<kill>, %T2_X, pred:%PRED_SEL_OFF
>	BUNDLE %T5_X<imp-def>, %T5_Y<imp-def>, %T5_Z<imp-def>, %T5_W<imp-def>, %T4_X<imp-use>, %T6_X<imp-use>, %T4_Y<imp-use>, %T6_Y<imp-use>, %T4_Z<imp-use>, %T6_Z<imp-use>, %T4_W<imp-use>, %T6_W<imp-use>
>	  * %T5_X<def> = DOT4_eg %T4_X, %T6_X, 32; flags: 
>	  * %T5_Y<def> = DOT4_eg %T4_Y, %T6_Y, 40; flags: 
>	  * %T5_Z<def> = DOT4_eg %T4_Z, %T6_Z, 40; flags: 
>	  * %T5_W<def> = DOT4_eg %T4_W, %T6_W, 8; flags: 
>	%T5_Y<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MAX %T5_X, %T2_X, pred:%PRED_SEL_OFF
>	%T0_W<def> = MOV %T2_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T2_Y<def> = MUL %C8_X, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %C16_Z, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T5_W<def> = MULADD_eg %T1_Y, %C1_X, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = EXP_IEEE_eg %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = CNDGE_eg %T5_X<kill>, %T2_Y<kill>, %T2_X, pred:%PRED_SEL_OFF
>	%T5_X<def> = ADD %C13_X, %C9_X, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MULADD_eg %T2_Z, %C14_X, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T2_W<def> = LOG_IEEE_eg %T2_W<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = MUL %C8_X, %T2_W<kill>, pred:%PRED_SEL_OFF
>	%T6_X<def> = ADD %C13_Y, %C9_Y, pred:%PRED_SEL_OFF
>	%T6_Y<def> = MULADD_eg %T1_Y, %C1_Y, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T5_W<def> = MULADD_eg %T1_Z, %C2_X, %T5_W<kill>, pred:%PRED_SEL_OFF
>	%T0_Y<def> = MOV %C16_Y, 0, pred:%noreg, %T0_XYZW<imp-def>
>	BUNDLE %T4_X<imp-def>, %T4_Y<imp-def>, %T4_Z<imp-def>, %T4_W<imp-def>, %T4_X<imp-use>, %T0_X<imp-use>, %T4_Y<imp-use>, %T0_Y<imp-use>, %T4_Z<imp-use>, %T0_Z<imp-use>, %T4_W<imp-use>, %T0_W<imp-use>
>	  * %T4_X<def> = DOT4_eg %T4_X, %T0_X, 32; flags: 
>	  * %T4_Y<def> = DOT4_eg %T4_Y, %T0_Y, 40; flags: 
>	  * %T4_Z<def> = DOT4_eg %T4_Z, %T0_Z, 40; flags: 
>	  * %T4_W<def> = DOT4_eg %T4_W, %T0_W, 8; flags: 
>	%T2_W<def> = MAX %T4_X, %T2_X, pred:%PRED_SEL_OFF
>	%T4_Z<def> = ADD %C13_Z, %C9_Z, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T2_Y, %C15_X, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_W<def> = MULADD_eg %T2_Z, %C14_Y, %T6_X<kill>, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T6_Y<kill>, pred:%PRED_SEL_OFF
>	%T6_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MULADD_eg %T1_Y, %C1_Z, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MULADD_eg %T1_W, %C3_X, %T5_W<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = EXP_IEEE_eg %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = CNDGE_eg %T4_X<kill>, %T5_X<kill>, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_Z, %C2_Z, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T6_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MULADD_eg %T2_Z<kill>, %C14_Z, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_W, %C3_Y, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MULADD_eg %T2_Y, %C15_Y, %T4_W<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = ADD %C19_X, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T2_W, %C20_X, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_W, %C3_Z, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MULADD_eg %T2_Y<kill>, %C15_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = ADD %C19_Y, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MULADD_eg %T4_X, %C21_X, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = ADD %C19_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T2_W, %C20_Y, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T1_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MOV %T2_X<kill>, 0, pred:%noreg
>	%T2_X<def> = MULADD_eg %T2_W<kill>, %C20_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_W<def> = MULADD_eg %T4_X, %C21_Y, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MULADD_eg %T4_X<kill>, %C21_Z, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %C9_W, 1, pred:%PRED_SEL_OFF
>	RETURN %T3_W<imp-use,kill>, %T3_Z<imp-use,kill>, %T3_Y<imp-use,kill>, %T3_X<imp-use,kill>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 246 dw -- 8 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 80000005 ALU ADDR:10 KCACHE_MODE0:2 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A1D40000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:118
>0010 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0011 00000C90 * INST:0x19 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0012 80000084   SRC0(SEL:132 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0013 00800C90 * INST:0x19 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0014 80000086   SRC0(SEL:134 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0015 00E00C90 * INST:0x19 DST(SEL:7 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 80000085   SRC0(SEL:133 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 00C00C90 * INST:0x19 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 8000008C   SRC0(SEL:140 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0019 00A00C90 * INST:0x19 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 800000F8   SRC0(SEL:248 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 00400C90 * INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0023 60800C90 * INST:0x19 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 00000884   SRC0(SEL:132 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0025 40800C90   INST:0x19 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 00000484   SRC0(SEL:132 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0029 20800C90   INST:0x19 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0031 40000C90   INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 60E00C90 * INST:0x19 DST(SEL:7 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 00000886   SRC0(SEL:134 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0037 40E00C90   INST:0x19 DST(SEL:7 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0039 60C00C90 * INST:0x19 DST(SEL:6 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0040 00008000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:4 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 00405F00   INST:0xbe DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 008084FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:4 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0043 20405F10   INST:0xbe DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0044 01008800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:4 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 40405F00   INST:0xbe DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 81808C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:4 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0047 60405F00 * INST:0xbe DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 0010E0FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:135 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 00800090   INST:0x1 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 80000885   SRC0(SEL:133 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 40C00C90 * INST:0x19 DST(SEL:6 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0052 80000486   SRC0(SEL:134 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 20E00C90 * INST:0x19 DST(SEL:7 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0054 0000E000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:7 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0055 00405F00   INST:0xbe DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0056 009FC400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0057 20405F10   INST:0xbe DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0058 0100E800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:7 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0059 40405F00   INST:0xbe DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0060 8180EC00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:7 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0061 60405F00 * INST:0xbe DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0062 00000485   SRC0(SEL:133 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0063 20C00C90   INST:0x19 DST(SEL:6 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0064 8110E0FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:135 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0065 40400090 * INST:0x1 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0066 0000C000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:6 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0067 00405F00   INST:0xbe DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0068 009FC400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0069 20405F10   INST:0xbe DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0070 0100C800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:6 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0071 40405F00   INST:0xbe DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0072 8180CC00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:6 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0073 60405F00 * INST:0xbe DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0074 0090E0FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:135 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0075 20400090   INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0076 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0077 60800C90 * INST:0x19 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0078 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0079 40800C90   INST:0x19 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0080 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0081 60A00C90 * INST:0x19 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0082 00000092   SRC0(SEL:146 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0083 00000C90   INST:0x19 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0084 8000088C   SRC0(SEL:140 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0085 40A00C90 * INST:0x19 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0086 0000008A   SRC0(SEL:138 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0087 00C00C90   INST:0x19 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0088 0000048C   SRC0(SEL:140 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0089 20A00C90   INST:0x19 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0090 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0091 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0092 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0093 20800C90   INST:0x19 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0094 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0095 60C00C90 * INST:0x19 DST(SEL:6 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0096 0000A004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:5 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0097 00405F00   INST:0xbe DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0098 0080A4FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:5 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0099 20405F10   INST:0xbe DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0100 0100A804   SRC0(SEL:4 REL:0 CHAN:2 NEG:0) SRC1(SEL:5 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0101 40405F00   INST:0xbe DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0102 8180AC04   SRC0(SEL:4 REL:0 CHAN:3 NEG:0) SRC1(SEL:5 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0103 60405F00 * INST:0xbe DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0104 000040FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0105 20400190   INST:0x3 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0106 80000892   SRC0(SEL:146 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0107 40000C90 * INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0108 000004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0109 20404190   INST:0x83 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0110 8000088A   SRC0(SEL:138 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0111 40C00C90 * INST:0x19 DST(SEL:6 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0112 8000048A   SRC0(SEL:138 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0113 20C00C90 * INST:0x19 DST(SEL:6 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0114 80000492   SRC0(SEL:146 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0115 20000C90 * INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0116 00000004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0117 00405F00   INST:0xbe DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0118 009FC404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0119 20405F00   INST:0xbe DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0120 01000804   SRC0(SEL:4 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0121 40405F10   INST:0xbe DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0122 81800C04   SRC0(SEL:4 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0123 60405F00 * INST:0xbe DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0124 00000090   SRC0(SEL:144 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0125 00000C90   INST:0x19 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0126 800040FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0127 60400190 * INST:0x3 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0128 0000C004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:6 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0129 00A05F10   INST:0xbe DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0130 0080C404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:6 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0131 20A05F00   INST:0xbe DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0132 0100C804   SRC0(SEL:4 REL:0 CHAN:2 NEG:0) SRC1(SEL:6 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0133 40A05F00   INST:0xbe DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0134 8180CC04   SRC0(SEL:4 REL:0 CHAN:3 NEG:0) SRC1(SEL:6 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0135 60A05F00 * INST:0xbe DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0136 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0137 20A00090 * INST:0x1 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0138 80004005   SRC0(SEL:5 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0139 40400190 * INST:0x3 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0140 00804088   SRC0(SEL:136 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0141 20400090   INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0142 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0143 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0144 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0145 40A00090 * INST:0x1 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0146 00000890   SRC0(SEL:144 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0147 40000C90   INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0148 80102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0149 60A28405 * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0150 80000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0151 20404090 * INST:0x81 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0152 0011208D   SRC0(SEL:141 REL:0 CHAN:0 NEG:0) SRC1(SEL:137 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0153 00A00010   INST:0x0 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0154 809FC005   SRC0(SEL:5 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0155 20436002 * INST:0x1b DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:0 NEG:0)
>0156 0011C802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:142 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0157 20A280FE   INST:0x14 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0158 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0159 60404190 * INST:0x83 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0160 819FC088   SRC0(SEL:136 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0161 00A00090 * INST:0x1 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0162 8091248D   SRC0(SEL:141 REL:0 CHAN:1 NEG:0) SRC1(SEL:137 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0163 00C00010 * INST:0x0 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0164 00902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0165 20C28805   INST:0x14 DST(SEL:6 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0166 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0167 40A00090 * INST:0x1 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0168 00000490   SRC0(SEL:144 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0169 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0170 80104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0171 60A28C05 * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:3 NEG:0)
>0172 00000004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0173 00805F10   INST:0xbe DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0174 009FC404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0175 20805F00   INST:0xbe DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0176 01000804   SRC0(SEL:4 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0177 40805F00   INST:0xbe DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0178 81800C04   SRC0(SEL:4 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0179 60805F00 * INST:0xbe DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0180 0111288D   SRC0(SEL:141 REL:0 CHAN:2 NEG:0) SRC1(SEL:137 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0181 40800010   INST:0x0 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0182 800040FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0183 60400190 * INST:0x3 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0184 0011E402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:143 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0185 20828405   INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0186 8091C802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:142 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0187 60828006 * INST:0x14 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:0 NEG:0)
>0188 01900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0189 00C00090   INST:0x1 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0190 80904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0191 20A28406 * INST:0x14 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:1 NEG:0)
>0192 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0193 00228C05   INST:0x14 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:3 NEG:0)
>0194 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0195 40A28805 * INST:0x14 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0196 80000005   SRC0(SEL:5 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0197 00A04090 * INST:0x81 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0198 801FC004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0199 00836002 * INST:0x1b DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:0 NEG:0)
>0200 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0201 00428805 * INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0202 01902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0203 00A28006   INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:0 NEG:0)
>0204 8111C802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:142 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0205 40428804 * INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:2 NEG:0)
>0206 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0207 20228405   INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0208 8091E402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:143 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0209 40828C04 * INST:0x14 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:3 NEG:0)
>0210 80808093   SRC0(SEL:147 REL:0 CHAN:0 NEG:0) SRC1(SEL:4 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0211 20800010 * INST:0x0 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0212 01106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0213 004A8002   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:2 SRC2(SEL:2 REL:0 CHAN:0 NEG:0)
>0214 80128C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:148 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0215 208284FE * INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0216 81904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0217 40228005 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:0 NEG:0)
>0218 8111E402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:143 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0219 40428802 * INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:2 NEG:0)
>0220 0012A004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:149 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0221 20428404   INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:1 NEG:0)
>0222 81008493   SRC0(SEL:147 REL:0 CHAN:1 NEG:0) SRC1(SEL:4 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0223 40800010 * INST:0x0 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0224 00928C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:148 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0225 208288FE   INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0226 81004893   SRC0(SEL:147 REL:0 CHAN:2 NEG:0) SRC1(SEL:2 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0227 40400010 * INST:0x0 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0228 01128C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:148 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0229 004A88FE   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:2 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0230 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0231 40200C90   INST:0x19 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0232 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0233 60228801 * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:1 REL:0 CHAN:2 NEG:0)
>0234 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0235 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0236 0112A004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:149 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0237 404280FE   INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0238 8092A004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:149 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0239 60428404 * INST:0x14 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:1 NEG:0)
>0240 00000CFE   SRC0(SEL:254 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0241 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0242 000008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0243 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0244 80000C89   SRC0(SEL:137 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0245 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95010688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:2 EOP:0
>0008 00000000 CF ADDR:0
>0009 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 16 dw -- 4 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400800 TEX/VTX INST:0x1 COUNT:3
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 8C151001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:48 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 C6951002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:26 NUM:0 COMP:1 MODE:1)
>0010 00000018   ENDIAN:0 OFFSET:24
>0011 00000000   
>0012 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0013 87961003   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:3 SEL_X:0 SEL_Y:1 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:30 NUM:0 COMP:0 MODE:1)
>0014 0000000C   ENDIAN:0 OFFSET:12
>0015 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..4]
>DCL TEMP[0], LOCAL
>DCL TEMP[1], LOCAL
>DCL TEMP[2], LOCAL
>DCL TEMP[3], LOCAL
>IMM FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: TXP TEMP[0], IN[3].xyyw, SAMP[0], 2D
>  1: TXP TEMP[1], IN[2].xyyw, SAMP[1], 2D
>  2: MUL TEMP[1], TEMP[1], IN[0]
>  3: MUL TEMP[0], TEMP[0], TEMP[1]
>  4: MOV TEMP[1].w, TEMP[0].wwww
>  5: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[2].xxxx, CONST[2].yyyy
>  6: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].xxxx
>  7: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
>  8: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
>  9: MOV_SAT OUT[0], TEMP[1]
> 10: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  call void @llvm.AMDGPU.reserve.reg(i32 4)
>  call void @llvm.AMDGPU.reserve.reg(i32 5)
>  call void @llvm.AMDGPU.reserve.reg(i32 6)
>  call void @llvm.AMDGPU.reserve.reg(i32 7)
>  %0 = call float @llvm.R600.load.input(i32 8)
>  %1 = call float @llvm.R600.load.input(i32 9)
>  %2 = call float @llvm.R600.load.input(i32 10)
>  %3 = call float @llvm.R600.load.input(i32 11)
>  %4 = call float @llvm.R600.load.input(i32 12)
>  %5 = call float @llvm.R600.load.input(i32 13)
>  %6 = call float @llvm.R600.load.input(i32 14)
>  %7 = call float @llvm.R600.load.input(i32 15)
>  %8 = call float @llvm.R600.load.input(i32 16)
>  %9 = call float @llvm.R600.load.input(i32 17)
>  %10 = call float @llvm.R600.load.input(i32 18)
>  %11 = call float @llvm.R600.load.input(i32 19)
>  %12 = call float @llvm.R600.load.input(i32 20)
>  %13 = call float @llvm.R600.load.input(i32 21)
>  %14 = call float @llvm.R600.load.input(i32 22)
>  %15 = call float @llvm.R600.load.input(i32 23)
>  %16 = call float @llvm.AMDGPU.div(float %12, float %15)
>  %17 = call float @llvm.AMDGPU.div(float %13, float %15)
>  %18 = call float @llvm.AMDGPU.div(float %13, float %15)
>  %19 = insertelement <4 x float> undef, float %16, i32 0
>  %20 = insertelement <4 x float> %19, float %17, i32 1
>  %21 = insertelement <4 x float> %20, float %18, i32 2
>  %22 = insertelement <4 x float> %21, float 1.000000e+00, i32 3
>  %23 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %22, i32 0, i32 2)
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = extractelement <4 x float> %23, i32 1
>  %26 = extractelement <4 x float> %23, i32 2
>  %27 = extractelement <4 x float> %23, i32 3
>  %28 = call float @llvm.AMDGPU.div(float %8, float %11)
>  %29 = call float @llvm.AMDGPU.div(float %9, float %11)
>  %30 = call float @llvm.AMDGPU.div(float %9, float %11)
>  %31 = insertelement <4 x float> undef, float %28, i32 0
>  %32 = insertelement <4 x float> %31, float %29, i32 1
>  %33 = insertelement <4 x float> %32, float %30, i32 2
>  %34 = insertelement <4 x float> %33, float 1.000000e+00, i32 3
>  %35 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %34, i32 1, i32 2)
>  %36 = extractelement <4 x float> %35, i32 0
>  %37 = extractelement <4 x float> %35, i32 1
>  %38 = extractelement <4 x float> %35, i32 2
>  %39 = extractelement <4 x float> %35, i32 3
>  %40 = call float @llvm.AMDGPU.mul(float %36, float %0)
>  %41 = call float @llvm.AMDGPU.mul(float %37, float %1)
>  %42 = call float @llvm.AMDGPU.mul(float %38, float %2)
>  %43 = call float @llvm.AMDGPU.mul(float %39, float %3)
>  %44 = call float @llvm.AMDGPU.mul(float %24, float %40)
>  %45 = call float @llvm.AMDGPU.mul(float %25, float %41)
>  %46 = call float @llvm.AMDGPU.mul(float %26, float %42)
>  %47 = call float @llvm.AMDGPU.mul(float %27, float %43)
>  %48 = call float @llvm.AMDGPU.load.const(i32 8)
>  %49 = call float @llvm.AMDGPU.load.const(i32 9)
>  %50 = call float @llvm.AMDIL.mad.(float %4, float %48, float %49)
>  %51 = call float @llvm.AMDIL.clamp.(float %50, float 0.000000e+00, float 1.000000e+00)
>  %52 = fsub float -0.000000e+00, %51
>  %53 = fadd float 1.000000e+00, %52
>  %54 = call float @llvm.AMDGPU.load.const(i32 12)
>  %55 = call float @llvm.AMDGPU.mul(float %54, float %53)
>  %56 = call float @llvm.AMDGPU.load.const(i32 13)
>  %57 = call float @llvm.AMDGPU.mul(float %56, float %53)
>  %58 = call float @llvm.AMDGPU.load.const(i32 14)
>  %59 = call float @llvm.AMDGPU.mul(float %58, float %53)
>  %60 = call float @llvm.AMDIL.mad.(float %44, float %51, float %55)
>  %61 = call float @llvm.AMDIL.mad.(float %45, float %51, float %57)
>  %62 = call float @llvm.AMDIL.mad.(float %46, float %51, float %59)
>  %63 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %64 = call float @llvm.AMDIL.clamp.(float %61, float 0.000000e+00, float 1.000000e+00)
>  %65 = call float @llvm.AMDIL.clamp.(float %62, float 0.000000e+00, float 1.000000e+00)
>  %66 = call float @llvm.AMDIL.clamp.(float %47, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.AMDGPU.store.output(float %63, i32 8)
>  call void @llvm.AMDGPU.store.output(float %64, i32 9)
>  call void @llvm.AMDGPU.store.output(float %65, i32 10)
>  call void @llvm.AMDGPU.store.output(float %66, i32 11)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.div(float, float) readnone
>
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T5_W in %vreg0, %T5_Y in %vreg1, %T5_X in %vreg2, %T4_W in %vreg3, %T4_Y in %vreg4, %T4_X in %vreg5, %T3_X in %vreg6, %T2_W in %vreg7, %T2_Z in %vreg8, %T2_Y in %vreg9, %T2_X in %vreg10
>Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T5_W %T5_Y %T5_X %T4_W %T4_Y %T4_X %T3_X %T2_W %T2_Z %T2_Y %T2_X
>	%T3_W<def> = RECIP_IEEE_eg %T4_W<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = RECIP_IEEE_eg %T5_W<kill>, pred:%PRED_SEL_OFF
>	%T0_X<def> = MUL %T4_X<kill>, %T3_W, pred:%PRED_SEL_OFF, %T0_XYZW<imp-def>
>	%T1_X<def> = MUL %T5_X<kill>, %T3_Z, pred:%PRED_SEL_OFF, %T1_XYZW<imp-def>
>	%T3_Y<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	%T3_W<def> = MUL %T4_Y<kill>, %T3_W<kill>, pred:%PRED_SEL_OFF
>	%T0_W<def> = MOV %T3_Y, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T3_Z<def> = MUL %T5_Y<kill>, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %T3_W, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T1_W<def> = MOV %T3_Y, 0, pred:%noreg, %T1_XYZW<imp-def>
>	%T1_Z<def> = MOV %T3_Z, 0, pred:%noreg, %T1_XYZW<imp-def>
>	%T0_Y<def> = MOV %T3_W<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T0_XYZW<def> = TEX_SAMPLE %T0_XYZW<kill>, 1, 2
>	%T3_X<def> = MULADD_eg %T3_X<kill>, %C2_X, %C2_Y, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T3_Z<kill>, 0, pred:%noreg, %T1_XYZW<imp-def>
>	%T3_Z<def> = MUL %T0_X, %T2_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T3_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T3_X<def> = MOV %T2_X, 128, pred:%PRED_SEL_OFF
>	%T3_X<def> = ADD %T3_X<kill>, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T0_Y, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MUL %C3_X, %T3_X, pred:%PRED_SEL_OFF
>	%T1_XYZW<def> = TEX_SAMPLE %T1_XYZW<kill>, 0, 2
>	%T3_Z<def> = MUL %T1_X, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MULADD_eg %T3_Z<kill>, %T2_X, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MUL %T1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T0_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MUL %C3_Y, %T3_X, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MULADD_eg %T3_Z<kill>, %T2_X, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_Z, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MUL %C3_Z, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T3_Y<kill>, %T2_X<kill>, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MUL %T0_W, %T2_W<kill>, pred:%PRED_SEL_OFF, %T0_XYZW<imp-use,kill>
>	%T2_W<def> = MUL %T1_W, %T2_Y<kill>, pred:%PRED_SEL_OFF, %T1_XYZW<imp-use,kill>
>	%T2_Y<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T3_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 158 dw -- 6 gprs ---------------------
>     C
>0000 00000007 ALU ADDR:14 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0
>0001 A0AC0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:44
>0014 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0017 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 40546B90   INST:0xd7 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 60546B90 * INST:0xd7 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 00546B10   INST:0xd6 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 00380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0025 20546B10   INST:0xd6 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 00380400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 80380000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:448 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0031 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 00382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0033 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0035 40746B90   INST:0xd7 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 80382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0037 60746B90 * INST:0xd7 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0039 00746B10   INST:0xd6 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0040 00382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20746B10   INST:0xd6 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 00382400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0043 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0044 80382000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:449 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0045 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 00384400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0047 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00384000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 00384400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0051 40946B90   INST:0xd7 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0052 80384000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 60946B90 * INST:0xd7 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0054 00384400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0055 00946B10   INST:0xd6 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0056 00384000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0057 20946B10   INST:0xd6 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0058 00384400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0059 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0060 80384000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:450 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0061 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0062 00386400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:451 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0063 00146B80   INST:0xd7 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0064 00386000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:451 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0065 20146B80   INST:0xd7 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0066 00386400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:451 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0067 40B46B90   INST:0xd7 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0068 80386000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:451 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0069 60B46B90 * INST:0xd7 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0070 00386400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:451 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0071 00B46B10   INST:0xd6 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0072 00386000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:451 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0073 20B46B10   INST:0xd6 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0074 00386400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:451 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0075 40146B00   INST:0xd6 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0076 80386000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:451 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0077 60146B00 * INST:0xd6 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:5 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0078 80000C04   SRC0(SEL:4 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0079 60604310 * INST:0x86 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0080 019FC004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0081 00000090   INST:0x1 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0082 80000C05   SRC0(SEL:5 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0083 40604310 * INST:0x86 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0084 011FC005   SRC0(SEL:5 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0085 00200090   INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0086 000000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0087 20600C90   INST:0x19 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0088 81806404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:3 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0089 60600090 * INST:0x1 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0090 01006405   SRC0(SEL:5 REL:0 CHAN:1 NEG:0) SRC1(SEL:3 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0091 40600090   INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0092 800004FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0093 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0094 00000C03   SRC0(SEL:3 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0095 40000C90   INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0096 80000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0097 60200C90 * INST:0x19 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0098 00000C03   SRC0(SEL:3 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0099 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0100 80000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0101 40200C90 * INST:0x19 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0002 00000034 TEX/VTX ADDR:104
>0003 80400000 TEX/VTX INST:0x1 COUNT:1
>0104 00000310   INST:0x10 RESOURCE_ID:3 SRC(GPR:0 REL:0)
>0105 F00D1000   DST(GPR:0 REL:0 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) LOD_BIAS:0 COORD_TYPE_X:1 COORD_TYPE_Y:1 COORD_TYPE_Z:1 COORD_TYPE_W:1
>0106 68808000   OFFSET_X:0 OFFSET_Y:0 OFFSET_Z:0 SAMPLER_ID:1 SRC(SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3)
>0107 00000000   
>0004 40000036 ALU ADDR:108 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0005 A01C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:8
>0108 00104003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0109 00728482   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:4 SRC2(SEL:130 REL:0 CHAN:1 NEG:0)
>0110 00000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0111 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0112 80004000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0113 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0114 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0115 80400C90 * INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0116 800010FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:1) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0117 00600C90 * INST:0x19 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0118 008060FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:3 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0119 00640010   INST:0x0 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:1 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0120 80804400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:2 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0121 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0122 801FC083   SRC0(SEL:131 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0123 20400090 * INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0006 0000003E TEX/VTX ADDR:124
>0007 80400000 TEX/VTX INST:0x1 COUNT:1
>0124 00010210   INST:0x10 RESOURCE_ID:2 SRC(GPR:1 REL:0)
>0125 F00D1001   DST(GPR:1 REL:0 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) LOD_BIAS:0 COORD_TYPE_X:1 COORD_TYPE_Y:1 COORD_TYPE_Z:1 COORD_TYPE_W:1
>0126 68800000   OFFSET_X:0 OFFSET_Y:0 OFFSET_Z:0 SAMPLER_ID:0 SRC(SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3)
>0127 00000000   
>0008 40000040 ALU ADDR:128 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0009 A0380000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:15
>0128 81006001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:3 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0129 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0130 000048FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0131 20428402   INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:1 NEG:0)
>0132 80806401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:3 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0133 40600090 * INST:0x1 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0134 01004800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:2 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0135 20600090   INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0136 80006483   SRC0(SEL:131 REL:0 CHAN:1 NEG:0) SRC1(SEL:3 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0137 40400090 * INST:0x1 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0138 80004803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0139 404288FE * INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0140 00006883   SRC0(SEL:131 REL:0 CHAN:2 NEG:0) SRC1(SEL:3 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0141 00600090   INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0142 80806801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:3 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0143 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0144 800044FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:2 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0145 006280FE * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0146 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0147 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0148 81804C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:2 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0149 20400090 * INST:0x1 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0150 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0151 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0152 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0153 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0154 809FCC01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0155 60400090 * INST:0x1 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0156 80000CFE   SRC0(SEL:254 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0157 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0010 C0010000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0011 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0012 00000000 CF ADDR:0
>0013 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..7]
>DCL CONST[9..12]
>DCL TEMP[0..2]
>IMM FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MUL TEMP[0], IN[0].xxxx, CONST[4]
>  6: MAD TEMP[0], IN[0].yyyy, CONST[5], TEMP[0]
>  7: MAD TEMP[0], IN[0].zzzz, CONST[6], TEMP[0]
>  8: MAD TEMP[0], IN[0].wwww, CONST[7], TEMP[0]
>  9: DP3 TEMP[1].x, TEMP[0], TEMP[0]
> 10: RSQ TEMP[1].x, TEMP[1]
> 11: RCP TEMP[1].x, TEMP[1]
> 12: MOV TEMP[1].yzw, IMM[0].xxxy
> 13: MOV OUT[3], IN[2]
> 14: MUL TEMP[2], IN[3].xxxx, CONST[9]
> 15: MAD TEMP[2], IN[3].yyyy, CONST[10], TEMP[2]
> 16: MAD TEMP[2], IN[3].zzzz, CONST[11], TEMP[2]
> 17: MAD OUT[4], IN[3].wwww, CONST[12], TEMP[2]
> 18: MOV OUT[2], TEMP[1]
> 19: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.R600.load.input(i32 12)
>  %9 = call float @llvm.R600.load.input(i32 13)
>  %10 = call float @llvm.R600.load.input(i32 14)
>  %11 = call float @llvm.R600.load.input(i32 15)
>  %12 = call float @llvm.R600.load.input(i32 16)
>  %13 = call float @llvm.R600.load.input(i32 17)
>  %14 = call float @llvm.R600.load.input(i32 18)
>  %15 = call float @llvm.R600.load.input(i32 19)
>  %16 = call float @llvm.AMDGPU.load.const(i32 0)
>  %17 = call float @llvm.AMDGPU.mul(float %0, float %16)
>  %18 = call float @llvm.AMDGPU.load.const(i32 1)
>  %19 = call float @llvm.AMDGPU.mul(float %0, float %18)
>  %20 = call float @llvm.AMDGPU.load.const(i32 2)
>  %21 = call float @llvm.AMDGPU.mul(float %0, float %20)
>  %22 = call float @llvm.AMDGPU.load.const(i32 3)
>  %23 = call float @llvm.AMDGPU.mul(float %0, float %22)
>  %24 = call float @llvm.AMDGPU.load.const(i32 4)
>  %25 = call float @llvm.AMDIL.mad.(float %1, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 5)
>  %27 = call float @llvm.AMDIL.mad.(float %1, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 6)
>  %29 = call float @llvm.AMDIL.mad.(float %1, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 7)
>  %31 = call float @llvm.AMDIL.mad.(float %1, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 8)
>  %33 = call float @llvm.AMDIL.mad.(float %2, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 9)
>  %35 = call float @llvm.AMDIL.mad.(float %2, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 10)
>  %37 = call float @llvm.AMDIL.mad.(float %2, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 11)
>  %39 = call float @llvm.AMDIL.mad.(float %2, float %38, float %31)
>  %40 = call float @llvm.AMDGPU.load.const(i32 12)
>  %41 = call float @llvm.AMDIL.mad.(float %3, float %40, float %33)
>  %42 = call float @llvm.AMDGPU.load.const(i32 13)
>  %43 = call float @llvm.AMDIL.mad.(float %3, float %42, float %35)
>  %44 = call float @llvm.AMDGPU.load.const(i32 14)
>  %45 = call float @llvm.AMDIL.mad.(float %3, float %44, float %37)
>  %46 = call float @llvm.AMDGPU.load.const(i32 15)
>  %47 = call float @llvm.AMDIL.mad.(float %3, float %46, float %39)
>  %48 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00)
>  %49 = call float @llvm.AMDIL.clamp.(float %5, float 0.000000e+00, float 1.000000e+00)
>  %50 = call float @llvm.AMDIL.clamp.(float %6, float 0.000000e+00, float 1.000000e+00)
>  %51 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
>  %52 = call float @llvm.AMDGPU.load.const(i32 16)
>  %53 = call float @llvm.AMDGPU.mul(float %0, float %52)
>  %54 = call float @llvm.AMDGPU.load.const(i32 17)
>  %55 = call float @llvm.AMDGPU.mul(float %0, float %54)
>  %56 = call float @llvm.AMDGPU.load.const(i32 18)
>  %57 = call float @llvm.AMDGPU.mul(float %0, float %56)
>  %58 = call float @llvm.AMDGPU.load.const(i32 19)
>  %59 = call float @llvm.AMDGPU.mul(float %0, float %58)
>  %60 = call float @llvm.AMDGPU.load.const(i32 20)
>  %61 = call float @llvm.AMDIL.mad.(float %1, float %60, float %53)
>  %62 = call float @llvm.AMDGPU.load.const(i32 21)
>  %63 = call float @llvm.AMDIL.mad.(float %1, float %62, float %55)
>  %64 = call float @llvm.AMDGPU.load.const(i32 22)
>  %65 = call float @llvm.AMDIL.mad.(float %1, float %64, float %57)
>  %66 = call float @llvm.AMDGPU.load.const(i32 23)
>  %67 = call float @llvm.AMDIL.mad.(float %1, float %66, float %59)
>  %68 = call float @llvm.AMDGPU.load.const(i32 24)
>  %69 = call float @llvm.AMDIL.mad.(float %2, float %68, float %61)
>  %70 = call float @llvm.AMDGPU.load.const(i32 25)
>  %71 = call float @llvm.AMDIL.mad.(float %2, float %70, float %63)
>  %72 = call float @llvm.AMDGPU.load.const(i32 26)
>  %73 = call float @llvm.AMDIL.mad.(float %2, float %72, float %65)
>  %74 = call float @llvm.AMDGPU.load.const(i32 27)
>  %75 = call float @llvm.AMDIL.mad.(float %2, float %74, float %67)
>  %76 = call float @llvm.AMDGPU.load.const(i32 28)
>  %77 = call float @llvm.AMDIL.mad.(float %3, float %76, float %69)
>  %78 = call float @llvm.AMDGPU.load.const(i32 29)
>  %79 = call float @llvm.AMDIL.mad.(float %3, float %78, float %71)
>  %80 = call float @llvm.AMDGPU.load.const(i32 30)
>  %81 = call float @llvm.AMDIL.mad.(float %3, float %80, float %73)
>  %82 = call float @llvm.AMDGPU.load.const(i32 31)
>  %83 = call float @llvm.AMDIL.mad.(float %3, float %82, float %75)
>  %84 = insertelement <4 x float> undef, float %77, i32 0
>  %85 = insertelement <4 x float> %84, float %79, i32 1
>  %86 = insertelement <4 x float> %85, float %81, i32 2
>  %87 = insertelement <4 x float> %86, float 0.000000e+00, i32 3
>  %88 = insertelement <4 x float> undef, float %77, i32 0
>  %89 = insertelement <4 x float> %88, float %79, i32 1
>  %90 = insertelement <4 x float> %89, float %81, i32 2
>  %91 = insertelement <4 x float> %90, float 0.000000e+00, i32 3
>  %92 = call float @llvm.AMDGPU.dp4(<4 x float> %87, <4 x float> %91)
>  %93 = call float @llvm.AMDIL.fabs.(float %92)
>  %94 = call float @llvm.AMDGPU.rsq(float %93)
>  %95 = call float @llvm.AMDGPU.rcp(float %94)
>  %96 = call float @llvm.AMDGPU.load.const(i32 36)
>  %97 = call float @llvm.AMDGPU.mul(float %12, float %96)
>  %98 = call float @llvm.AMDGPU.load.const(i32 37)
>  %99 = call float @llvm.AMDGPU.mul(float %12, float %98)
>  %100 = call float @llvm.AMDGPU.load.const(i32 38)
>  %101 = call float @llvm.AMDGPU.mul(float %12, float %100)
>  %102 = call float @llvm.AMDGPU.load.const(i32 39)
>  %103 = call float @llvm.AMDGPU.mul(float %12, float %102)
>  %104 = call float @llvm.AMDGPU.load.const(i32 40)
>  %105 = call float @llvm.AMDIL.mad.(float %13, float %104, float %97)
>  %106 = call float @llvm.AMDGPU.load.const(i32 41)
>  %107 = call float @llvm.AMDIL.mad.(float %13, float %106, float %99)
>  %108 = call float @llvm.AMDGPU.load.const(i32 42)
>  %109 = call float @llvm.AMDIL.mad.(float %13, float %108, float %101)
>  %110 = call float @llvm.AMDGPU.load.const(i32 43)
>  %111 = call float @llvm.AMDIL.mad.(float %13, float %110, float %103)
>  %112 = call float @llvm.AMDGPU.load.const(i32 44)
>  %113 = call float @llvm.AMDIL.mad.(float %14, float %112, float %105)
>  %114 = call float @llvm.AMDGPU.load.const(i32 45)
>  %115 = call float @llvm.AMDIL.mad.(float %14, float %114, float %107)
>  %116 = call float @llvm.AMDGPU.load.const(i32 46)
>  %117 = call float @llvm.AMDIL.mad.(float %14, float %116, float %109)
>  %118 = call float @llvm.AMDGPU.load.const(i32 47)
>  %119 = call float @llvm.AMDIL.mad.(float %14, float %118, float %111)
>  %120 = call float @llvm.AMDGPU.load.const(i32 48)
>  %121 = call float @llvm.AMDIL.mad.(float %15, float %120, float %113)
>  %122 = call float @llvm.AMDGPU.load.const(i32 49)
>  %123 = call float @llvm.AMDIL.mad.(float %15, float %122, float %115)
>  %124 = call float @llvm.AMDGPU.load.const(i32 50)
>  %125 = call float @llvm.AMDIL.mad.(float %15, float %124, float %117)
>  %126 = call float @llvm.AMDGPU.load.const(i32 51)
>  %127 = call float @llvm.AMDIL.mad.(float %15, float %126, float %119)
>  call void @llvm.AMDGPU.store.output(float %41, i32 4)
>  call void @llvm.AMDGPU.store.output(float %43, i32 5)
>  call void @llvm.AMDGPU.store.output(float %45, i32 6)
>  call void @llvm.AMDGPU.store.output(float %47, i32 7)
>  call void @llvm.AMDGPU.store.output(float %48, i32 8)
>  call void @llvm.AMDGPU.store.output(float %49, i32 9)
>  call void @llvm.AMDGPU.store.output(float %50, i32 10)
>  call void @llvm.AMDGPU.store.output(float %51, i32 11)
>  call void @llvm.AMDGPU.store.output(float %95, i32 12)
>  call void @llvm.AMDGPU.store.output(float 0.000000e+00, i32 13)
>  call void @llvm.AMDGPU.store.output(float 0.000000e+00, i32 14)
>  call void @llvm.AMDGPU.store.output(float 1.000000e+00, i32 15)
>  call void @llvm.AMDGPU.store.output(float %8, i32 16)
>  call void @llvm.AMDGPU.store.output(float %9, i32 17)
>  call void @llvm.AMDGPU.store.output(float %10, i32 18)
>  call void @llvm.AMDGPU.store.output(float %11, i32 19)
>  call void @llvm.AMDGPU.store.output(float %121, i32 20)
>  call void @llvm.AMDGPU.store.output(float %123, i32 21)
>  call void @llvm.AMDGPU.store.output(float %125, i32 22)
>  call void @llvm.AMDGPU.store.output(float %127, i32 23)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) readnone
>
>declare float @llvm.AMDIL.fabs.(float) readnone
>
>declare float @llvm.AMDGPU.rsq(float) readnone
>
>declare float @llvm.AMDGPU.rcp(float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T4_W in %vreg0, %T4_Z in %vreg1, %T4_Y in %vreg2, %T4_X in %vreg3, %T3_W in %vreg4, %T3_Z in %vreg5, %T3_Y in %vreg6, %T3_X in %vreg7, %T2_W in %vreg8, %T2_Z in %vreg9, %T2_Y in %vreg10, %T2_X in %vreg11, %T1_W in %vreg12, %T1_Z in %vreg13, %T1_Y in %vreg14, %T1_X in %vreg15
>Function Live Outs: %T5_W %T5_Z %T5_Y %T5_X %T4_W %T4_Z %T4_Y %T4_X %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T4_W %T4_Z %T4_Y %T4_X %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T6_W<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T6_Z<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T6_Y<def> = MOV %T3_Z<kill>, 0, pred:%noreg
>	%T6_X<def> = MOV %T3_W<kill>, 0, pred:%noreg
>	%T5_W<def> = MOV %T4_X<kill>, 0, pred:%noreg
>	%T7_X<def> = MOV %T4_Y<kill>, 0, pred:%noreg
>	%T7_Y<def> = MOV %T4_Z<kill>, 0, pred:%noreg
>	%T7_Z<def> = MOV %T4_W<kill>, 0, pred:%noreg
>	%T3_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Y, %C1_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C4_X, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y, %C5_X, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_Z, %C2_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T3_W<def> = MULADD_eg %T1_Z, %C6_X, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Y, %C1_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = MUL %T1_X, %C4_Z, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MUL %T1_X, %C4_Y, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C2_Y, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T0_X<def> = MULADD_eg %T1_W, %C7_X, %T3_W<kill>, pred:%PRED_SEL_OFF, %T0_XYZW<imp-def>
>	%T4_X<def> = MULADD_eg %T1_Y, %C5_Z, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T3_W<def> = MULADD_eg %T1_Y, %C1_Z, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_X, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MULADD_eg %T1_Y, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T1_Y<kill>, %C5_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_W, %C3_Y, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MULADD_eg %T1_Z, %C6_Z, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %T1_Z, %C2_Z, %T3_W<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T3_W<def> = MULADD_eg %T1_Z, %C2_W, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = MULADD_eg %T1_W, %C3_Z, %T4_X<kill>, pred:%PRED_SEL_OFF
>	%T4_X<def> = MULADD_eg %T1_W, %C7_Z, %T3_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_Z<kill>, %C6_Y, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_Z<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 0.000000e+00
>	%T0_W<def> = MOV %T3_Z, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T3_Y<def> = MULADD_eg %T1_W, %C7_Y, %T1_Z<kill>, pred:%PRED_SEL_OFF
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T3_W<kill>, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %T4_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T1_Z<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T0_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	BUNDLE %T3_X<imp-def>, %T3_Y<imp-def>, %T3_Z<imp-def>, %T3_W<imp-def>, %T0_X<imp-use>, %T0_Y<imp-use>, %T0_Z<imp-use>, %T0_W<imp-use>
>	  * %T3_X<def> = DOT4_eg %T0_X, %T0_X, 32; flags: 
>	  * %T3_Y<def> = DOT4_eg %T0_Y, %T0_Y, 40; flags: 
>	  * %T3_Z<def> = DOT4_eg %T0_Z, %T0_Z, 40; flags: 
>	  * %T3_W<def> = DOT4_eg %T0_W, %T0_W, 8; flags: 
>	%T2_X<def> = MOV %T2_X<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T3_X<def> = MOV %T3_X<kill>, 256, pred:%PRED_SEL_OFF
>	%T3_X<def> = RECIPSQRT_CLAMPED_eg %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T2_W<kill>, 1, pred:%PRED_SEL_OFF
>	BUNDLE %T3_X<imp-def>, %T3_Y<imp-def>, %T3_Z<imp-def>, %T3_W<imp-def>, %T3_X<imp-use>, %PRED_SEL_OFF<imp-use>
>	  * %T3_X<def> = RECIP_IEEE_cm %T3_X, pred:%PRED_SEL_OFF, 0; flags: 
>	  * %T3_Y<def> = RECIP_IEEE_cm %T3_X<internal>, pred:%PRED_SEL_OFF, 0; flags: 
>	  * %T3_Z<def> = RECIP_IEEE_cm %T3_X<internal>, pred:%PRED_SEL_OFF, 0; flags: 
>	  * %T3_W<def> = RECIP_IEEE_cm %T3_X<internal>, pred:%PRED_SEL_OFF, 0; flags: 
>	%T3_W<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	%T3_Y<def> = MOV %T3_Z, 0, pred:%noreg
>	%T4_Y<def> = MUL %T5_W, %C9_X, pred:%PRED_SEL_OFF
>	%T4_X<def> = MOV %T6_W<kill>, 0, pred:%noreg
>	%T4_Z<def> = MULADD_eg %T7_X, %C10_X, %T4_Y<kill>, pred:%PRED_SEL_OFF
>	%T4_Y<def> = MOV %T6_Z<kill>, 0, pred:%noreg
>	%T4_W<def> = MULADD_eg %T7_Y, %C11_X, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MUL %T5_W, %C9_Y, pred:%PRED_SEL_OFF
>	%T5_X<def> = MULADD_eg %T7_X, %C10_Y, %T4_Z<kill>, pred:%PRED_SEL_OFF
>	%T4_Z<def> = MOV %T6_Y<kill>, 0, pred:%noreg
>	%T5_Y<def> = MULADD_eg %T7_Y, %C11_Y, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = MULADD_eg %T7_Z, %C12_X, %T4_W<kill>, pred:%PRED_SEL_OFF
>	%T4_W<def> = MUL %T5_W, %C9_Z, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MULADD_eg %T7_X, %C10_Z, %T4_W<kill>, pred:%PRED_SEL_OFF
>	%T4_W<def> = MOV %T6_X<kill>, 0, pred:%noreg
>	%T5_Y<def> = MULADD_eg %T7_Z, %C12_Y, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MULADD_eg %T7_Y, %C11_Z, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T5_W<def> = MUL %T5_W<kill>, %C9_W, pred:%PRED_SEL_OFF
>	%T5_W<def> = MULADD_eg %T7_X<kill>, %C10_W, %T5_W<kill>, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MULADD_eg %T7_Z, %C12_Z, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T5_W<def> = MULADD_eg %T7_Y<kill>, %C11_W, %T5_W<kill>, pred:%PRED_SEL_OFF
>	%T5_W<def> = MULADD_eg %T7_Z<kill>, %C12_W, %T5_W<kill>, pred:%PRED_SEL_OFF
>	RETURN %T5_W<imp-use,kill>, %T5_Z<imp-use,kill>, %T5_Y<imp-use,kill>, %T5_X<imp-use,kill>, %T4_W<imp-use,kill>, %T4_Z<imp-use,kill>, %T4_Y<imp-use,kill>, %T4_X<imp-use,kill>, %T3_W<imp-use,kill>, %T3_Z<imp-use,kill>, %T3_Y<imp-use,kill>, %T3_X<imp-use,kill>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 170 dw -- 8 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 40000007 ALU ADDR:14 KCACHE_MODE0:1 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A1340000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:78
>0014 00000C03   SRC0(SEL:3 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0015 00C00C90   INST:0x19 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0016 00000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0017 20C00C90   INST:0x19 DST(SEL:6 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 40C00C90   INST:0x19 DST(SEL:6 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 80000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0021 60C00C90 * INST:0x19 DST(SEL:6 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 00000404   SRC0(SEL:4 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 00E00C90   INST:0x19 DST(SEL:7 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 00000804   SRC0(SEL:4 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0025 20E00C90   INST:0x19 DST(SEL:7 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 00000C04   SRC0(SEL:4 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0027 40E00C90   INST:0x19 DST(SEL:7 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 80000004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 60A00C90 * INST:0x19 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 80100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 00600090 * INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 00102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0033 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0034 80108001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:132 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0035 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0037 006280FE   INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0038 8010A401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:133 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0039 206284FE * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0040 00900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0041 20600090   INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 8010C801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:134 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0043 606284FE * INST:0x14 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0044 01108001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:132 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0045 00800090   INST:0x1 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0047 406284FE * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0048 81100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0049 20800090 * INST:0x1 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 00908001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:132 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0051 20600090   INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0052 80904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0053 40628803 * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0054 8010EC01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:135 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0055 00028C03 * INST:0x14 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:3 NEG:0)
>0056 0110A401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:133 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0057 00828004   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:0 NEG:0)
>0058 81102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0059 60628404 * INST:0x14 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:1 NEG:0)
>0060 80106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0061 00628003 * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:0 NEG:0)
>0062 81900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0063 00200090 * INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0064 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0065 208280FE * INST:0x14 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0066 8090A401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:133 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0067 20628403 * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0068 00906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0069 20228803   INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0070 8110C801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:134 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0071 40628004 * INST:0x14 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:0 NEG:0)
>0072 81104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0073 00828C03 * INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:3 NEG:0)
>0074 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0075 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0076 81904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0077 60628404 * INST:0x14 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:1 NEG:0)
>0078 81106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0079 00628004 * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:0 NEG:0)
>0080 0110EC01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:135 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0081 00828803   INST:0x14 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0082 8090C801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:134 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0083 40228403 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0084 800000F8   SRC0(SEL:248 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0085 40600C90 * INST:0x19 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0086 0090EC01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:135 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0087 20628801   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:1 REL:0 CHAN:2 NEG:0)
>0088 800008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0089 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0090 00000004   SRC0(SEL:4 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0091 40000C90   INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0092 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0093 60228C03 * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:3 NEG:0)
>0094 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0095 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0096 80000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0097 40200C90 * INST:0x19 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0098 00000000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0099 00605F10   INST:0xbe DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0100 009FC4FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0101 20605F00   INST:0xbe DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0102 01000800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0103 40605F00   INST:0xbe DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0104 81800C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0105 60605F00 * INST:0xbe DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0106 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0107 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0108 80000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0109 A0400C90 * INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0110 80000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0111 00600C91 * INST:0x19 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:1 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0112 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0113 00604390   INST:0x87 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0114 00000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0115 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0116 80000C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0117 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0118 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0119 00604310 * INST:0x86 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0120 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0121 20604310   INST:0x86 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0122 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0123 40604310   INST:0x86 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0124 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0125 60604310 * INST:0x86 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0126 000008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0127 20600C90   INST:0x19 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0128 800000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0129 60600C90 * INST:0x19 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0130 00000C06   SRC0(SEL:6 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0131 00880C90   INST:0x19 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:2 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0132 80112C05   SRC0(SEL:5 REL:0 CHAN:3 NEG:0) SRC1(SEL:137 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0133 20800090 * INST:0x1 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0134 00000806   SRC0(SEL:6 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0135 20800C90   INST:0x19 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0136 80114007   SRC0(SEL:7 REL:0 CHAN:0 NEG:0) SRC1(SEL:138 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0137 408284FE * INST:0x14 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0138 00912C05   SRC0(SEL:5 REL:0 CHAN:3 NEG:0) SRC1(SEL:137 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0139 40800090   INST:0x1 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0140 80116407   SRC0(SEL:7 REL:0 CHAN:1 NEG:0) SRC1(SEL:139 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0141 608288FE * INST:0x14 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0142 00914007   SRC0(SEL:7 REL:0 CHAN:0 NEG:0) SRC1(SEL:138 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0143 00A288FE   INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0144 80000406   SRC0(SEL:6 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0145 40800C90 * INST:0x19 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0146 00118807   SRC0(SEL:7 REL:0 CHAN:2 NEG:0) SRC1(SEL:140 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0147 00A28C04   INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:4 REL:0 CHAN:3 NEG:0)
>0148 80916407   SRC0(SEL:7 REL:0 CHAN:1 NEG:0) SRC1(SEL:139 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0149 20A280FE * INST:0x14 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0150 81112C05   SRC0(SEL:5 REL:0 CHAN:3 NEG:0) SRC1(SEL:137 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0151 60800090 * INST:0x1 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0152 81114007   SRC0(SEL:7 REL:0 CHAN:0 NEG:0) SRC1(SEL:138 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0153 40A28CFE * INST:0x14 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:3 NEG:0)
>0154 00918807   SRC0(SEL:7 REL:0 CHAN:2 NEG:0) SRC1(SEL:140 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0155 20A28405   INST:0x14 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0156 01116407   SRC0(SEL:7 REL:0 CHAN:1 NEG:0) SRC1(SEL:139 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0157 40A288FE   INST:0x14 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0158 80000006   SRC0(SEL:6 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0159 60800C90 * INST:0x19 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0160 81912C05   SRC0(SEL:5 REL:0 CHAN:3 NEG:0) SRC1(SEL:137 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0161 60A00090 * INST:0x1 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0162 01118807   SRC0(SEL:7 REL:0 CHAN:2 NEG:0) SRC1(SEL:140 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0163 40A28805   INST:0x14 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0164 81914007   SRC0(SEL:7 REL:0 CHAN:0 NEG:0) SRC1(SEL:138 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0165 60A28CFE * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:3 NEG:0)
>0166 81916407   SRC0(SEL:7 REL:0 CHAN:1 NEG:0) SRC1(SEL:139 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0167 60A28CFE * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:3 NEG:0)
>0168 81918807   SRC0(SEL:7 REL:0 CHAN:2 NEG:0) SRC1(SEL:140 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0169 60A28CFE * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:3 NEG:0)
>0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0006 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 94C00688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x53 BURST_COUNT:1 EOP:0
>0008 C001C001 EXPORT GPR:3 ELEM_SIZE:3 ARRAY_BASE:1 TYPE:2
>0009 94C00B20 EXPORT SWIZ_X:0 SWIZ_Y:4 SWIZ_Z:4 SWIZ_W:5 BARRIER:1 INST:0x53 BURST_COUNT:1 EOP:0
>0010 C0024002 EXPORT GPR:4 ELEM_SIZE:3 ARRAY_BASE:2 TYPE:2
>0011 95010688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:2 EOP:0
>0012 00000000 CF ADDR:0
>0013 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 20 dw -- 5 gprs ---------------------
>     C
>0000 00000002 TEX/VTX ADDR:4
>0001 80400C00 TEX/VTX INST:0x1 COUNT:4
>0004 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0005 8C151001   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:48 NUM:0 COMP:0 MODE:1)
>0006 00000000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0009 88CD1002   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0010 0000000C   ENDIAN:0 OFFSET:12
>0011 00000000   
>0012 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0013 87961003   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:3 SEL_X:0 SEL_Y:1 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:30 NUM:0 COMP:0 MODE:1)
>0014 0000001C   ENDIAN:0 OFFSET:28
>0015 00000000   
>0016 00000000   INST:0 FETCH_TYPE:0 BUFFER_ID:0
>0017 87961004   SRC(GPR:0 SEL_X:0) SEL_Y:0) DST(GPR:4 SEL_X:0 SEL_Y:1 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:30 NUM:0 COMP:0 MODE:1)
>0018 00000024   ENDIAN:0 OFFSET:36
>0019 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST:0x14 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..25]
>DCL CONST[27..31]
>DCL TEMP[0..4]
>IMM FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: MUL TEMP[0], TEMP[0], CONST[7]
>  8: MOV TEMP[1].w, CONST[8].xxxx
>  9: MOV TEMP[2], CONST[9]
> 10: MOV_SAT OUT[1], TEMP[2]
> 11: DP3 TEMP[1].x, TEMP[0], CONST[10]
> 12: DP3 TEMP[1].y, TEMP[0], CONST[12]
> 13: LIT TEMP[3], TEMP[1]
> 14: ADD TEMP[2], CONST[13], TEMP[2]
> 15: MAD TEMP[2], TEMP[3].yyyy, CONST[14], TEMP[2]
> 16: MAD TEMP[2], TEMP[3].zzzz, CONST[15], TEMP[2]
> 17: DP3 TEMP[1].x, TEMP[0], CONST[16]
> 18: DP3 TEMP[1].y, TEMP[0], CONST[18]
> 19: LIT TEMP[3], TEMP[1]
> 20: ADD TEMP[2], CONST[19], TEMP[2]
> 21: MAD TEMP[2], TEMP[3].yyyy, CONST[20], TEMP[2]
> 22: MAD_SAT OUT[1].xyz, TEMP[3].zzzz, CONST[21], TEMP[2]
> 23: MUL TEMP[3], IN[0].xxxx, CONST[22]
> 24: MAD TEMP[3], IN[0].yyyy, CONST[23], TEMP[3]
> 25: MAD TEMP[3], IN[0].zzzz, CONST[24], TEMP[3]
> 26: MAD TEMP[3], IN[0].wwww, CONST[25], TEMP[3]
> 27: DP3 TEMP[4].x, TEMP[3], TEMP[3]
> 28: RSQ TEMP[4].x, TEMP[4]
> 29: RCP TEMP[4].x, TEMP[4]
> 30: MOV TEMP[4].yzw, IMM[0].xxxy
> 31: MOV OUT[3], IN[2]
> 32: MUL TEMP[1], CONST[27].xxxx, CONST[28]
> 33: MAD TEMP[1], CONST[27].yyyy, CONST[29], TEMP[1]
> 34: MAD TEMP[1], CONST[27].zzzz, CONST[30], TEMP[1]
> 35: MAD OUT[4], CONST[27].wwww, CONST[31], TEMP[1]
> 36: MOV OUT[2], TEMP[4]
> 37: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  call void @llvm.AMDGPU.reserve.reg(i32 0)
>  call void @llvm.AMDGPU.reserve.reg(i32 1)
>  call void @llvm.AMDGPU.reserve.reg(i32 2)
>  call void @llvm.AMDGPU.reserve.reg(i32 3)
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.R600.load.input(i32 12)
>  %9 = call float @llvm.R600.load.input(i32 13)
>  %10 = call float @llvm.R600.load.input(i32 14)
>  %11 = call float @llvm.R600.load.input(i32 15)
>  %12 = call float @llvm.AMDGPU.load.const(i32 0)
>  %13 = call float @llvm.AMDGPU.mul(float %0, float %12)
>  %14 = call float @llvm.AMDGPU.load.const(i32 1)
>  %15 = call float @llvm.AMDGPU.mul(float %0, float %14)
>  %16 = call float @llvm.AMDGPU.load.const(i32 2)
>  %17 = call float @llvm.AMDGPU.mul(float %0, float %16)
>  %18 = call float @llvm.AMDGPU.load.const(i32 3)
>  %19 = call float @llvm.AMDGPU.mul(float %0, float %18)
>  %20 = call float @llvm.AMDGPU.load.const(i32 4)
>  %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13)
>  %22 = call float @llvm.AMDGPU.load.const(i32 5)
>  %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15)
>  %24 = call float @llvm.AMDGPU.load.const(i32 6)
>  %25 = call float @llvm.AMDIL.mad.(float %1, float %24, float %17)
>  %26 = call float @llvm.AMDGPU.load.const(i32 7)
>  %27 = call float @llvm.AMDIL.mad.(float %1, float %26, float %19)
>  %28 = call float @llvm.AMDGPU.load.const(i32 8)
>  %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21)
>  %30 = call float @llvm.AMDGPU.load.const(i32 9)
>  %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23)
>  %32 = call float @llvm.AMDGPU.load.const(i32 10)
>  %33 = call float @llvm.AMDIL.mad.(float %2, float %32, float %25)
>  %34 = call float @llvm.AMDGPU.load.const(i32 11)
>  %35 = call float @llvm.AMDIL.mad.(float %2, float %34, float %27)
>  %36 = call float @llvm.AMDGPU.load.const(i32 12)
>  %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29)
>  %38 = call float @llvm.AMDGPU.load.const(i32 13)
>  %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31)
>  %40 = call float @llvm.AMDGPU.load.const(i32 14)
>  %41 = call float @llvm.AMDIL.mad.(float %3, float %40, float %33)
>  %42 = call float @llvm.AMDGPU.load.const(i32 15)
>  %43 = call float @llvm.AMDIL.mad.(float %3, float %42, float %35)
>  %44 = call float @llvm.AMDGPU.load.const(i32 16)
>  %45 = call float @llvm.AMDGPU.load.const(i32 17)
>  %46 = call float @llvm.AMDGPU.load.const(i32 18)
>  %47 = insertelement <4 x float> undef, float %4, i32 0
>  %48 = insertelement <4 x float> %47, float %5, i32 1
>  %49 = insertelement <4 x float> %48, float %6, i32 2
>  %50 = insertelement <4 x float> %49, float 0.000000e+00, i32 3
>  %51 = insertelement <4 x float> undef, float %44, i32 0
>  %52 = insertelement <4 x float> %51, float %45, i32 1
>  %53 = insertelement <4 x float> %52, float %46, i32 2
>  %54 = insertelement <4 x float> %53, float 0.000000e+00, i32 3
>  %55 = call float @llvm.AMDGPU.dp4(<4 x float> %50, <4 x float> %54)
>  %56 = call float @llvm.AMDGPU.load.const(i32 20)
>  %57 = call float @llvm.AMDGPU.load.const(i32 21)
>  %58 = call float @llvm.AMDGPU.load.const(i32 22)
>  %59 = insertelement <4 x float> undef, float %4, i32 0
>  %60 = insertelement <4 x float> %59, float %5, i32 1
>  %61 = insertelement <4 x float> %60, float %6, i32 2
>  %62 = insertelement <4 x float> %61, float 0.000000e+00, i32 3
>  %63 = insertelement <4 x float> undef, float %56, i32 0
>  %64 = insertelement <4 x float> %63, float %57, i32 1
>  %65 = insertelement <4 x float> %64, float %58, i32 2
>  %66 = insertelement <4 x float> %65, float 0.000000e+00, i32 3
>  %67 = call float @llvm.AMDGPU.dp4(<4 x float> %62, <4 x float> %66)
>  %68 = call float @llvm.AMDGPU.load.const(i32 24)
>  %69 = call float @llvm.AMDGPU.load.const(i32 25)
>  %70 = call float @llvm.AMDGPU.load.const(i32 26)
>  %71 = insertelement <4 x float> undef, float %4, i32 0
>  %72 = insertelement <4 x float> %71, float %5, i32 1
>  %73 = insertelement <4 x float> %72, float %6, i32 2
>  %74 = insertelement <4 x float> %73, float 0.000000e+00, i32 3
>  %75 = insertelement <4 x float> undef, float %68, i32 0
>  %76 = insertelement <4 x float> %75, float %69, i32 1
>  %77 = insertelement <4 x float> %76, float %70, i32 2
>  %78 = insertelement <4 x float> %77, float 0.000000e+00, i32 3
>  %79 = call float @llvm.AMDGPU.dp4(<4 x float> %74, <4 x float> %78)
>  %80 = call float @llvm.AMDGPU.load.const(i32 28)
>  %81 = call float @llvm.AMDGPU.mul(float %55, float %80)
>  %82 = call float @llvm.AMDGPU.load.const(i32 29)
>  %83 = call float @llvm.AMDGPU.mul(float %67, float %82)
>  %84 = call float @llvm.AMDGPU.load.const(i32 30)
>  %85 = call float @llvm.AMDGPU.mul(float %79, float %84)
>  %86 = call float @llvm.AMDGPU.load.const(i32 31)
>  %87 = call float @llvm.AMDGPU.mul(float %35, float %86)
>  %88 = call float @llvm.AMDGPU.load.const(i32 32)
>  %89 = call float @llvm.AMDGPU.load.const(i32 36)
>  %90 = call float @llvm.AMDGPU.load.const(i32 37)
>  %91 = call float @llvm.AMDGPU.load.const(i32 38)
>  %92 = call float @llvm.AMDGPU.load.const(i32 39)
>  %93 = call float @llvm.AMDIL.clamp.(float %89, float 0.000000e+00, float 1.000000e+00)
>  %94 = call float @llvm.AMDIL.clamp.(float %90, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %91, float 0.000000e+00, float 1.000000e+00)
>  %96 = call float @llvm.AMDIL.clamp.(float %92, float 0.000000e+00, float 1.000000e+00)
>  %97 = call float @llvm.AMDGPU.load.const(i32 40)
>  %98 = call float @llvm.AMDGPU.load.const(i32 41)
>  %99 = call float @llvm.AMDGPU.load.const(i32 42)
>  %100 = insertelement <4 x float> undef, float %81, i32 0
>  %101 = insertelement <4 x float> %100, float %83, i32 1
>  %102 = insertelement <4 x float> %101, float %85, i32 2
>  %103 = insertelement <4 x float> %102, float 0.000000e+00, i32 3
>  %104 = insertelement <4 x float> undef, float %97, i32 0
>  %105 = insertelement <4 x float> %104, float %98, i32 1
>  %106 = insertelement <4 x float> %105, float %99, i32 2
>  %107 = insertelement <4 x float> %106, float 0.000000e+00, i32 3
>  %108 = call float @llvm.AMDGPU.dp4(<4 x float> %103, <4 x float> %107)
>  %109 = call float @llvm.AMDGPU.load.const(i32 48)
>  %110 = call float @llvm.AMDGPU.load.const(i32 49)
>  %111 = call float @llvm.AMDGPU.load.const(i32 50)
>  %112 = insertelement <4 x float> undef, float %81, i32 0
>  %113 = insertelement <4 x float> %112, float %83, i32 1
>  %114 = insertelement <4 x float> %113, float %85, i32 2
>  %115 = insertelement <4 x float> %114, float 0.000000e+00, i32 3
>  %116 = insertelement <4 x float> undef, float %109, i32 0
>  %117 = insertelement <4 x float> %116, float %110, i32 1
>  %118 = insertelement <4 x float> %117, float %111, i32 2
>  %119 = insertelement <4 x float> %118, float 0.000000e+00, i32 3
>  %120 = call float @llvm.AMDGPU.dp4(<4 x float> %115, <4 x float> %119)
>  %121 = call float @llvm.AMDIL.max.(float %108, float 0.000000e+00)
>  %122 = call float @llvm.AMDIL.max.(float %120, float 0.000000e+00)
>  %123 = call float @llvm.AMDGPU.pow(float %122, float %88)
>  %124 = call float @llvm.AMDGPU.cndlt(float %108, float 0.000000e+00, float %123)
>  %125 = call float @llvm.AMDGPU.load.const(i32 52)
>  %126 = fadd float %125, %89
>  %127 = call float @llvm.AMDGPU.load.const(i32 53)
>  %128 = fadd float %127, %90
>  %129 = call float @llvm.AMDGPU.load.const(i32 54)
>  %130 = fadd float %129, %91
>  %131 = call float @llvm.AMDGPU.load.const(i32 55)
>  %132 = fadd float %131, %92
>  %133 = call float @llvm.AMDGPU.load.const(i32 56)
>  %134 = call float @llvm.AMDIL.mad.(float %121, float %133, float %126)
>  %135 = call float @llvm.AMDGPU.load.const(i32 57)
>  %136 = call float @llvm.AMDIL.mad.(float %121, float %135, float %128)
>  %137 = call float @llvm.AMDGPU.load.const(i32 58)
>  %138 = call float @llvm.AMDIL.mad.(float %121, float %137, float %130)
>  %139 = call float @llvm.AMDGPU.load.const(i32 59)
>  %140 = call float @llvm.AMDIL.mad.(float %121, float %139, float %132)
>  %141 = call float @llvm.AMDGPU.load.const(i32 60)
>  %142 = call float @llvm.AMDIL.mad.(float %124, float %141, float %134)
>  %143 = call float @llvm.AMDGPU.load.const(i32 61)
>  %144 = call float @llvm.AMDIL.mad.(float %124, float %143, float %136)
>  %145 = call float @llvm.AMDGPU.load.const(i32 62)
>  %146 = call float @llvm.AMDIL.mad.(float %124, float %145, float %138)
>  %147 = call float @llvm.AMDGPU.load.const(i32 63)
>  %148 = call float @llvm.AMDIL.mad.(float %124, float %147, float %140)
>  %149 = call float @llvm.AMDGPU.load.const(i32 64)
>  %150 = call float @llvm.AMDGPU.load.const(i32 65)
>  %151 = call float @llvm.AMDGPU.load.const(i32 66)
>  %152 = insertelement <4 x float> undef, float %81, i32 0
>  %153 = insertelement <4 x float> %152, float %83, i32 1
>  %154 = insertelement <4 x float> %153, float %85, i32 2
>  %155 = insertelement <4 x float> %154, float 0.000000e+00, i32 3
>  %156 = insertelement <4 x float> undef, float %149, i32 0
>  %157 = insertelement <4 x float> %156, float %150, i32 1
>  %158 = insertelement <4 x float> %157, float %151, i32 2
>  %159 = insertelement <4 x float> %158, float 0.000000e+00, i32 3
>  %160 = call float @llvm.AMDGPU.dp4(<4 x float> %155, <4 x float> %159)
>  %161 = call float @llvm.AMDGPU.load.const(i32 72)
>  %162 = call float @llvm.AMDGPU.load.const(i32 73)
>  %163 = call float @llvm.AMDGPU.load.const(i32 74)
>  %164 = insertelement <4 x float> undef, float %81, i32 0
>  %165 = insertelement <4 x float> %164, float %83, i32 1
>  %166 = insertelement <4 x float> %165, float %85, i32 2
>  %167 = insertelement <4 x float> %166, float 0.000000e+00, i32 3
>  %168 = insertelement <4 x float> undef, float %161, i32 0
>  %169 = insertelement <4 x float> %168, float %162, i32 1
>  %170 = insertelement <4 x float> %169, float %163, i32 2
>  %171 = insertelement <4 x float> %170, float 0.000000e+00, i32 3
>  %172 = call float @llvm.AMDGPU.dp4(<4 x float> %167, <4 x float> %171)
>  %173 = call float @llvm.AMDIL.max.(float %160, float 0.000000e+00)
>  %174 = call float @llvm.AMDIL.max.(float %172, float 0.000000e+00)
>  %175 = call float @llvm.AMDGPU.pow(float %174, float %88)
>  %176 = call float @llvm.AMDGPU.cndlt(float %160, float 0.000000e+00, float %175)
>  %177 = call float @llvm.AMDGPU.load.const(i32 76)
>  %178 = fadd float %177, %142
>  %179 = call float @llvm.AMDGPU.load.const(i32 77)
>  %180 = fadd float %179, %144
>  %181 = call float @llvm.AMDGPU.load.const(i32 78)
>  %182 = fadd float %181, %146
>  %183 = call float @llvm.AMDGPU.load.const(i32 79)
>  %184 = fadd float %183, %148
>  %185 = call float @llvm.AMDGPU.load.const(i32 80)
>  %186 = call float @llvm.AMDIL.mad.(float %173, float %185, float %178)
>  %187 = call float @llvm.AMDGPU.load.const(i32 81)
>  %188 = call float @llvm.AMDIL.mad.(float %173, float %187, float %180)
>  %189 = call float @llvm.AMDGPU.load.const(i32 82)
>  %190 = call float @llvm.AMDIL.mad.(float %173, float %189, float %182)
>  %191 = call float @llvm.AMDGPU.load.const(i32 83)
>  %192 = call float @llvm.AMDIL.mad.(float %173, float %191, float %184)
>  %193 = call float @llvm.AMDGPU.load.const(i32 84)
>  %194 = call float @llvm.AMDIL.mad.(float %176, float %193, float %186)
>  %195 = call float @llvm.AMDGPU.load.const(i32 85)
>  %196 = call float @llvm.AMDIL.mad.(float %176, float %195, float %188)
>  %197 = call float @llvm.AMDGPU.load.const(i32 86)
>  %198 = call float @llvm.AMDIL.mad.(float %176, float %197, float %190)
>  %199 = call float @llvm.AMDIL.clamp.(float %194, float 0.000000e+00, float 1.000000e+00)
>  %200 = call float @llvm.AMDIL.clamp.(float %196, float 0.000000e+00, float 1.000000e+00)
>  %201 = call float @llvm.AMDIL.clamp.(float %198, float 0.000000e+00, float 1.000000e+00)
>  %202 = call float @llvm.AMDGPU.load.const(i32 88)
>  %203 = call float @llvm.AMDGPU.mul(float %0, float %202)
>  %204 = call float @llvm.AMDGPU.load.const(i32 89)
>  %205 = call float @llvm.AMDGPU.mul(float %0, float %204)
>  %206 = call float @llvm.AMDGPU.load.const(i32 90)
>  %207 = call float @llvm.AMDGPU.mul(float %0, float %206)
>  %208 = call float @llvm.AMDGPU.load.const(i32 91)
>  %209 = call float @llvm.AMDGPU.mul(float %0, float %208)
>  %210 = call float @llvm.AMDGPU.load.const(i32 92)
>  %211 = call float @llvm.AMDIL.mad.(float %1, float %210, float %203)
>  %212 = call float @llvm.AMDGPU.load.const(i32 93)
>  %213 = call float @llvm.AMDIL.mad.(float %1, float %212, float %205)
>  %214 = call float @llvm.AMDGPU.load.const(i32 94)
>  %215 = call float @llvm.AMDIL.mad.(float %1, float %214, float %207)
>  %216 = call float @llvm.AMDGPU.load.const(i32 95)
>  %217 = call float @llvm.AMDIL.mad.(float %1, float %216, float %209)
>  %218 = call float @llvm.AMDGPU.load.const(i32 96)
>  %219 = call float @llvm.AMDIL.mad.(float %2, float %218, float %211)
>  %220 = call float @llvm.AMDGPU.load.const(i32 97)
>  %221 = call float @llvm.AMDIL.mad.(float %2, float %220, float %213)
>  %222 = call float @llvm.AMDGPU.load.const(i32 98)
>  %223 = call float @llvm.AMDIL.mad.(float %2, float %222, float %215)
>  %224 = call float @llvm.AMDGPU.load.const(i32 99)
>  %225 = call float @llvm.AMDIL.mad.(float %2, float %224, float %217)
>  %226 = call float @llvm.AMDGPU.load.const(i32 100)
>  %227 = call float @llvm.AMDIL.mad.(float %3, float %226, float %219)
>  %228 = call float @llvm.AMDGPU.load.const(i32 101)
>  %229 = call float @llvm.AMDIL.mad.(float %3, float %228, float %221)
>  %230 = call float @llvm.AMDGPU.load.const(i32 102)
>  %231 = call float @llvm.AMDIL.mad.(float %3, float %230, float %223)
>  %232 = call float @llvm.AMDGPU.load.const(i32 103)
>  %233 = call float @llvm.AMDIL.mad.(float %3, float %232, float %225)
>  %234 = insertelement <4 x float> undef, float %227, i32 0
>  %235 = insertelement <4 x float> %234, float %229, i32 1
>  %236 = insertelement <4 x float> %235, float %231, i32 2
>  %237 = insertelement <4 x float> %236, float 0.000000e+00, i32 3
>  %238 = insertelement <4 x float> undef, float %227, i32 0
>  %239 = insertelement <4 x float> %238, float %229, i32 1
>  %240 = insertelement <4 x float> %239, float %231, i32 2
>  %241 = insertelement <4 x float> %240, float 0.000000e+00, i32 3
>  %242 = call float @llvm.AMDGPU.dp4(<4 x float> %237, <4 x float> %241)
>  %243 = call float @llvm.AMDIL.fabs.(float %242)
>  %244 = call float @llvm.AMDGPU.rsq(float %243)
>  %245 = call float @llvm.AMDGPU.rcp(float %244)
>  %246 = call float @llvm.AMDGPU.load.const(i32 108)
>  %247 = call float @llvm.AMDGPU.load.const(i32 112)
>  %248 = call float @llvm.AMDGPU.mul(float %246, float %247)
>  %249 = call float @llvm.AMDGPU.load.const(i32 108)
>  %250 = call float @llvm.AMDGPU.load.const(i32 113)
>  %251 = call float @llvm.AMDGPU.mul(float %249, float %250)
>  %252 = call float @llvm.AMDGPU.load.const(i32 108)
>  %253 = call float @llvm.AMDGPU.load.const(i32 114)
>  %254 = call float @llvm.AMDGPU.mul(float %252, float %253)
>  %255 = call float @llvm.AMDGPU.load.const(i32 108)
>  %256 = call float @llvm.AMDGPU.load.const(i32 115)
>  %257 = call float @llvm.AMDGPU.mul(float %255, float %256)
>  %258 = call float @llvm.AMDGPU.load.const(i32 109)
>  %259 = call float @llvm.AMDGPU.load.const(i32 116)
>  %260 = call float @llvm.AMDIL.mad.(float %258, float %259, float %248)
>  %261 = call float @llvm.AMDGPU.load.const(i32 109)
>  %262 = call float @llvm.AMDGPU.load.const(i32 117)
>  %263 = call float @llvm.AMDIL.mad.(float %261, float %262, float %251)
>  %264 = call float @llvm.AMDGPU.load.const(i32 109)
>  %265 = call float @llvm.AMDGPU.load.const(i32 118)
>  %266 = call float @llvm.AMDIL.mad.(float %264, float %265, float %254)
>  %267 = call float @llvm.AMDGPU.load.const(i32 109)
>  %268 = call float @llvm.AMDGPU.load.const(i32 119)
>  %269 = call float @llvm.AMDIL.mad.(float %267, float %268, float %257)
>  %270 = call float @llvm.AMDGPU.load.const(i32 110)
>  %271 = call float @llvm.AMDGPU.load.const(i32 120)
>  %272 = call float @llvm.AMDIL.mad.(float %270, float %271, float %260)
>  %273 = call float @llvm.AMDGPU.load.const(i32 110)
>  %274 = call float @llvm.AMDGPU.load.const(i32 121)
>  %275 = call float @llvm.AMDIL.mad.(float %273, float %274, float %263)
>  %276 = call float @llvm.AMDGPU.load.const(i32 110)
>  %277 = call float @llvm.AMDGPU.load.const(i32 122)
>  %278 = call float @llvm.AMDIL.mad.(float %276, float %277, float %266)
>  %279 = call float @llvm.AMDGPU.load.const(i32 110)
>  %280 = call float @llvm.AMDGPU.load.const(i32 123)
>  %281 = call float @llvm.AMDIL.mad.(float %279, float %280, float %269)
>  %282 = call float @llvm.AMDGPU.load.const(i32 111)
>  %283 = call float @llvm.AMDGPU.load.const(i32 124)
>  %284 = call float @llvm.AMDIL.mad.(float %282, float %283, float %272)
>  %285 = call float @llvm.AMDGPU.load.const(i32 111)
>  %286 = call float @llvm.AMDGPU.load.const(i32 125)
>  %287 = call float @llvm.AMDIL.mad.(float %285, float %286, float %275)
>  %288 = call float @llvm.AMDGPU.load.const(i32 111)
>  %289 = call float @llvm.AMDGPU.load.const(i32 126)
>  %290 = call float @llvm.AMDIL.mad.(float %288, float %289, float %278)
>  %291 = call float @llvm.AMDGPU.load.const(i32 111)
>  %292 = call float @llvm.AMDGPU.load.const(i32 127)
>  %293 = call float @llvm.AMDIL.mad.(float %291, float %292, float %281)
>  call void @llvm.AMDGPU.store.output(float %37, i32 4)
>  call void @llvm.AMDGPU.store.output(float %39, i32 5)
>  call void @llvm.AMDGPU.store.output(float %41, i32 6)
>  call void @llvm.AMDGPU.store.output(float %43, i32 7)
>  call void @llvm.AMDGPU.store.output(float %199, i32 8)
>  call void @llvm.AMDGPU.store.output(float %200, i32 9)
>  call void @llvm.AMDGPU.store.output(float %201, i32 10)
>  call void @llvm.AMDGPU.store.output(float %96, i32 11)
>  call void @llvm.AMDGPU.store.output(float %245, i32 12)
>  call void @llvm.AMDGPU.store.output(float 0.000000e+00, i32 13)
>  call void @llvm.AMDGPU.store.output(float 0.000000e+00, i32 14)
>  call void @llvm.AMDGPU.store.output(float 1.000000e+00, i32 15)
>  call void @llvm.AMDGPU.store.output(float %8, i32 16)
>  call void @llvm.AMDGPU.store.output(float %9, i32 17)
>  call void @llvm.AMDGPU.store.output(float %10, i32 18)
>  call void @llvm.AMDGPU.store.output(float %11, i32 19)
>  call void @llvm.AMDGPU.store.output(float %284, i32 20)
>  call void @llvm.AMDGPU.store.output(float %287, i32 21)
>  call void @llvm.AMDGPU.store.output(float %290, i32 22)
>  call void @llvm.AMDGPU.store.output(float %293, i32 23)
>  ret void
>}
>
>declare void @llvm.AMDGPU.reserve.reg(i32)
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare float @llvm.AMDGPU.load.const(i32) readnone
>
>declare float @llvm.AMDGPU.mul(float, float) readnone
>
>declare float @llvm.AMDIL.mad.(float, float, float) readnone
>
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) readnone
>
>declare float @llvm.AMDIL.clamp.(float, float, float) readnone
>
>declare float @llvm.AMDIL.max.(float, float) readnone
>
>declare float @llvm.AMDGPU.pow(float, float) readnone
>
>declare float @llvm.AMDGPU.cndlt(float, float, float) readnone
>
>declare float @llvm.AMDIL.fabs.(float) readnone
>
>declare float @llvm.AMDGPU.rsq(float) readnone
>
>declare float @llvm.AMDGPU.rcp(float) readnone
>
>declare void @llvm.AMDGPU.store.output(float, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T3_W in %vreg0, %T3_Z in %vreg1, %T3_Y in %vreg2, %T3_X in %vreg3, %T2_Z in %vreg4, %T2_Y in %vreg5, %T2_X in %vreg6, %T1_W in %vreg7, %T1_Z in %vreg8, %T1_Y in %vreg9, %T1_X in %vreg10
>Function Live Outs: %T5_W %T5_Z %T5_Y %T5_X %T4_W %T4_Z %T4_Y %T4_X %T3_W %T3_Z %T3_Y %T3_X %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T3_W %T3_Z %T3_Y %T3_X %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>	%T0_X<def> = MOV %T2_X<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T4_X<def> = MOV %T3_X<kill>, 0, pred:%noreg
>	%T4_Y<def> = MOV %T3_Y<kill>, 0, pred:%noreg
>	%T4_Z<def> = MOV %T3_Z<kill>, 0, pred:%noreg
>	%T4_W<def> = MOV %T3_W<kill>, 0, pred:%noreg
>	%T10_X<def> = MOV %C4_X, 0, pred:%noreg, %T10_XYZW<imp-def>
>	%T9_X<def> = MOV %C6_X, 0, pred:%noreg, %T9_XYZW<imp-def>
>	%T8_X<def> = MOV %C5_X, 0, pred:%noreg, %T8_XYZW<imp-def>
>	%T7_X<def> = MOV %C12_X, 0, pred:%noreg, %T7_XYZW<imp-def>
>	%T6_X<def> = MOV %C18_X, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T5_X<def> = MOV %C10_X, 0, pred:%noreg, %T5_XYZW<imp-def>
>	%T3_Z<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 0.000000e+00
>	%T10_W<def> = MOV %T3_Z, 0, pred:%noreg, %T10_XYZW<imp-def>
>	%T0_W<def> = MOV %T3_Z, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T10_Z<def> = MOV %C4_Z, 0, pred:%noreg, %T10_XYZW<imp-def>
>	%T0_Z<def> = MOV %T2_Z<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T9_W<def> = MOV %T3_Z, 0, pred:%noreg, %T9_XYZW<imp-def>
>	%T10_Y<def> = MOV %C4_Y, 0, pred:%noreg, %T10_XYZW<imp-def>
>	%T8_W<def> = MOV %T3_Z, 0, pred:%noreg, %T8_XYZW<imp-def>
>	%T9_Z<def> = MOV %C6_Z, 0, pred:%noreg, %T9_XYZW<imp-def>
>	%T0_Y<def> = MOV %T2_Y<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T0_X<imp-use>, %T10_X<imp-use>, %T0_Y<imp-use>, %T10_Y<imp-use>, %T0_Z<imp-use>, %T10_Z<imp-use>, %T0_W<imp-use>, %T10_W<imp-use>
>	  * %T2_X<def> = DOT4_eg %T0_X, %T10_X, 32; flags: 
>	  * %T2_Y<def> = DOT4_eg %T0_Y, %T10_Y, 40; flags: 
>	  * %T2_Z<def> = DOT4_eg %T0_Z, %T10_Z, 40; flags: 
>	  * %T2_W<def> = DOT4_eg %T0_W, %T10_W, 8; flags: 
>	%T2_X<def> = MUL %T2_X<kill>, %C7_X, pred:%PRED_SEL_OFF, %T2_XYZW<imp-def>
>	%T8_Z<def> = MOV %C5_Z, 0, pred:%noreg, %T8_XYZW<imp-def>
>	%T9_Y<def> = MOV %C6_Y, 0, pred:%noreg, %T9_XYZW<imp-def>
>	BUNDLE %T3_X<imp-def>, %T3_Y<imp-def>, %T3_Z<imp-def>, %T3_W<imp-def>, %T0_X<imp-use>, %T9_X<imp-use>, %T0_Y<imp-use>, %T9_Y<imp-use>, %T0_Z<imp-use>, %T9_Z<imp-use>, %T0_W<imp-use>, %T9_W<imp-use>
>	  * %T3_X<def> = DOT4_eg %T0_X, %T9_X, 32; flags: 
>	  * %T3_Y<def> = DOT4_eg %T0_Y, %T9_Y, 40; flags: 
>	  * %T3_Z<def> = DOT4_eg %T0_Z, %T9_Z, 40; flags: 
>	  * %T3_W<def> = DOT4_eg %T0_W, %T9_W, 8; flags: 
>	%T3_Y<def> = MUL %T3_X<kill>, %C7_Z, pred:%PRED_SEL_OFF
>	%T8_Y<def> = MOV %C5_Y, 0, pred:%noreg, %T8_XYZW<imp-def>
>	BUNDLE %T3_X<imp-def>, %T3_Y<imp-def>, %T3_Z<imp-def>, %T3_W<imp-def>, %T0_X<imp-use>, %T8_X<imp-use>, %T0_Y<imp-use>, %T8_Y<imp-use>, %T0_Z<imp-use>, %T8_Z<imp-use>, %T0_W<imp-use>, %T8_W<imp-use>
>	  * %T3_X<def> = DOT4_eg %T0_X, %T8_X, 32; flags: 
>	  * %T3_Y<def> = DOT4_eg %T0_Y, %T8_Y, 40; flags: 
>	  * %T3_Z<def> = DOT4_eg %T0_Z, %T8_Z, 40; flags: 
>	  * %T3_W<def> = DOT4_eg %T0_W, %T8_W, 8; flags: 
>	%T3_X<def> = MUL %T3_X<kill>, %C7_Y, pred:%PRED_SEL_OFF
>	%T7_W<def> = MOV %T3_Z, 0, pred:%noreg, %T7_XYZW<imp-def>
>	%T2_W<def> = MOV %T3_Z, 0, pred:%noreg, %T2_XYZW<imp-def>
>	%T7_Z<def> = MOV %C12_Z, 0, pred:%noreg, %T7_XYZW<imp-def>
>	%T2_Z<def> = MOV %T3_Y<kill>, 0, pred:%noreg, %T2_XYZW<imp-def>
>	%T7_Y<def> = MOV %C12_Y, 0, pred:%noreg, %T7_XYZW<imp-def>
>	%T5_W<def> = MOV %T3_Z, 0, pred:%noreg, %T5_XYZW<imp-def>
>	%T6_W<def> = MOV %T3_Z, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T2_Y<def> = MOV %T3_X<kill>, 0, pred:%noreg, %T2_XYZW<imp-def>
>	BUNDLE %T3_X<imp-def>, %T3_Y<imp-def>, %T3_Z<imp-def>, %T3_W<imp-def>, %T2_X<imp-use>, %T7_X<imp-use>, %T2_Y<imp-use>, %T7_Y<imp-use>, %T2_Z<imp-use>, %T7_Z<imp-use>, %T2_W<imp-use>, %T7_W<imp-use>
>	  * %T3_X<def> = DOT4_eg %T2_X, %T7_X, 32; flags: 
>	  * %T3_Y<def> = DOT4_eg %T2_Y, %T7_Y, 40; flags: 
>	  * %T3_Z<def> = DOT4_eg %T2_Z, %T7_Z, 40; flags: 
>	  * %T3_W<def> = DOT4_eg %T2_W, %T7_W, 8; flags: 
>	%T3_X<def> = MAX %T3_X<kill>, %T3_Z, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MOV %C10_Z, 0, pred:%noreg, %T5_XYZW<imp-def>
>	%T6_Z<def> = MOV %C18_Z, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T7_X<def> = LOG_IEEE_eg %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T6_Y<def> = MOV %C18_Y, 0, pred:%noreg, %T6_XYZW<imp-def>
>	%T5_Y<def> = MOV %C10_Y, 0, pred:%noreg, %T5_XYZW<imp-def>
>	BUNDLE %T3_X<imp-def>, %T3_Y<imp-def>, %T3_Z<imp-def>, %T3_W<imp-def>, %T2_X<imp-use>, %T6_X<imp-use>, %T2_Y<imp-use>, %T6_Y<imp-use>, %T2_Z<imp-use>, %T6_Z<imp-use>, %T2_W<imp-use>, %T6_W<imp-use>
>	  * %T3_X<def> = DOT4_eg %T2_X, %T6_X, 32; flags: 
>	  * %T3_Y<def> = DOT4_eg %T2_Y, %T6_Y, 40; flags: 
>	  * %T3_Z<def> = DOT4_eg %T2_Z, %T6_Z, 40; flags: 
>	  * %T3_W<def> = DOT4_eg %T2_W, %T6_W, 8; flags: 
>	%T3_W<def> = MAX %T3_X<kill>, %T3_Z, pred:%PRED_SEL_OFF
>	%T0_X<def> = MOV %C16_X, 0, pred:%noreg, %T0_XYZW<imp-def>
>	BUNDLE %T3_X<imp-def>, %T3_Y<imp-def>, %T3_Z<imp-def>, %T3_W<imp-def>, %T2_X<imp-use>, %T5_X<imp-use>, %T2_Y<imp-use>, %T5_Y<imp-use>, %T2_Z<imp-use>, %T5_Z<imp-use>, %T2_W<imp-use>, %T5_W<imp-use>
>	  * %T3_X<def> = DOT4_eg %T2_X, %T5_X, 32; flags: 
>	  * %T3_Y<def> = DOT4_eg %T2_Y, %T5_Y, 40; flags: 
>	  * %T3_Z<def> = DOT4_eg %T2_Z, %T5_Z, 40; flags: 
>	  * %T3_W<def> = DOT4_eg %T2_W, %T5_W, 8; flags: 
>	%T5_Z<def> = MUL %T1_X, %C22_X, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MAX %T3_X, %T3_Z, pred:%PRED_SEL_OFF
>	%T5_X<def> = MUL %T1_X, %C0_X, pred:%PRED_SEL_OFF
>	%T0_W<def> = MOV %T3_Z, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T5_Y<def> = MUL %C8_X, %T7_X<kill>, pred:%PRED_SEL_OFF
>	%T5_W<def> = MULADD_eg %T1_Y, %C23_X, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T6_X<def> = ADD %C13_X, %C9_X, pred:%PRED_SEL_OFF
>	%T0_Z<def> = MOV %C16_Z, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T6_Z<def> = MUL %T1_X, %C0_Y, pred:%PRED_SEL_OFF
>	%T5_Y<def> = EXP_IEEE_eg %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = CNDGE_eg %T3_X<kill>, %T5_Y<kill>, %T3_Z, pred:%PRED_SEL_OFF
>	%T5_X<def> = MULADD_eg %T1_Y, %C1_X, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MUL %T1_X, %C22_Z, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MULADD_eg %T1_Z, %C2_X, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T5_W<def> = MULADD_eg %T1_Z, %C24_X, %T5_W<kill>, pred:%PRED_SEL_OFF
>	%T3_W<def> = LOG_IEEE_eg %T3_W<kill>, pred:%PRED_SEL_OFF
>	%T3_W<def> = MUL %C8_X, %T3_W<kill>, pred:%PRED_SEL_OFF
>	%T6_X<def> = MULADD_eg %T3_Y, %C14_X, %T6_X<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = ADD %C13_Y, %C9_Y, pred:%PRED_SEL_OFF
>	%T0_Y<def> = MOV %C16_Y, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T6_Y<def> = MUL %T1_X, %C0_Z, pred:%PRED_SEL_OFF
>	%T6_W<def> = MULADD_eg %T1_Y, %C1_Y, %T6_Z<kill>, pred:%PRED_SEL_OFF
>	BUNDLE %T2_X<imp-def>, %T2_Y<imp-def>, %T2_Z<imp-def>, %T2_W<imp-def>, %T2_X<imp-use>, %T0_X<imp-use>, %T2_Y<imp-use>, %T0_Y<imp-use>, %T2_Z<imp-use>, %T0_Z<imp-use>, %T2_W<imp-use>, %T0_W<imp-use>
>	  * %T2_X<def> = DOT4_eg %T2_X, %T0_X, 40; flags: 
>	  * %T2_Y<def> = DOT4_eg %T2_Y, %T0_Y, 40; flags: 
>	  * %T2_Z<def> = DOT4_eg %T2_Z, %T0_Z, 40; flags: 
>	  * %T2_W<def> = DOT4_eg %T2_W, %T0_W, 0; flags: 
>	%T6_Z<def> = MUL %T1_X, %C22_Y, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MAX %T2_W, %T3_Z, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MULADD_eg %T1_Z, %C2_Y, %T6_W<kill>, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MULADD_eg %T1_Y, %C23_Z, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_W, %C3_X, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T0_X<def> = MULADD_eg %T1_W, %C25_X, %T5_W<kill>, pred:%PRED_SEL_OFF, %T0_XYZW<imp-def>
>	%T6_X<def> = MULADD_eg %T3_X, %C15_X, %T6_X<kill>, pred:%PRED_SEL_OFF
>	%T5_Z<def> = ADD %C13_Z, %C9_Z, pred:%PRED_SEL_OFF
>	%T1_X<def> = MUL %T1_X<kill>, %C0_W, pred:%PRED_SEL_OFF
>	%T5_W<def> = MULADD_eg %T3_Y, %C14_Y, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T6_Y<def> = MULADD_eg %T1_Y, %C1_Z, %T6_Y<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = MULADD_eg %T1_Y, %C23_Y, %T6_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_W<def> = EXP_IEEE_eg %T3_W<kill>, pred:%PRED_SEL_OFF
>	%T2_W<def> = CNDGE_eg %T2_W<kill>, %T3_W<kill>, %T3_Z, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MULADD_eg %T3_Y<kill>, %C14_Z, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = ADD %C19_X, %T6_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MULADD_eg %T1_W, %C3_Y, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_W<def> = MULADD_eg %T1_Z, %C24_Z, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MULADD_eg %T1_Z, %C2_Z, %T6_Y<kill>, pred:%PRED_SEL_OFF
>	%T5_W<def> = MULADD_eg %T3_X, %C15_Y, %T5_W<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MULADD_eg %T1_Y<kill>, %C1_W, %T1_X<kill>, pred:%PRED_SEL_OFF
>	%T1_X<def> = MOV %T2_X<kill>, 0, pred:%noreg
>	%T5_X<def> = MULADD_eg %T1_Z, %C24_Y, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T0_W<def> = MOV %T3_Z, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T3_X<def> = MULADD_eg %T3_X<kill>, %C15_Z, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_X<def> = MULADD_eg %T1_W, %C3_Z, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T5_Y<def> = ADD %C19_Y, %T5_W<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T2_Z, %C20_X, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_W<def> = MULADD_eg %T1_W, %C25_Z, %T3_W<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MULADD_eg %T1_Z<kill>, %C2_W, %T1_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_Y<def> = MOV %T2_Y<kill>, 0, pred:%noreg
>	%T0_Z<def> = MOV %T3_W<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T2_Y<def> = MULADD_eg %T2_Z, %C20_Y, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T3_W<def> = MULADD_eg %T1_W, %C25_Y, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T3_Y<def> = MULADD_eg %T2_W, %C21_X, %T3_Y<kill>, pred:%PRED_SEL_OFF
>	%T1_W<def> = MULADD_eg %T1_W<kill>, %C3_W, %T1_Z<kill>, pred:%PRED_SEL_OFF
>	%T3_X<def> = ADD %C19_Z, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T1_Z<def> = MOV %T2_X<kill>, 0, pred:%noreg
>	%T2_Z<def> = MULADD_eg %T2_Z<kill>, %C20_Z, %T3_X<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MULADD_eg %T2_W, %C21_Y, %T2_Y<kill>, pred:%PRED_SEL_OFF
>	%T0_Y<def> = MOV %T3_W<kill>, 0, pred:%noreg, %T0_XYZW<imp-def>
>	%T2_X<def> = MOV %T3_Y<kill>, 1, pred:%PRED_SEL_OFF
>	BUNDLE %T3_X<imp-def>, %T3_Y<imp-def>, %T3_Z<imp-def>, %T3_W<imp-def>, %T0_X<imp-use>, %T0_Y<imp-use>, %T0_Z<imp-use>, %T0_W<imp-use>
>	  * %T3_X<def> = DOT4_eg %T0_X, %T0_X, 32; flags: 
>	  * %T3_Y<def> = DOT4_eg %T0_Y, %T0_Y, 40; flags: 
>	  * %T3_Z<def> = DOT4_eg %T0_Z, %T0_Z, 40; flags: 
>	  * %T3_W<def> = DOT4_eg %T0_W, %T0_W, 8; flags: 
>	%T2_Z<def> = MULADD_eg %T2_W<kill>, %C21_Z, %T2_Z<kill>, pred:%PRED_SEL_OFF
>	%T2_Y<def> = MOV %T2_Y<kill>, 1, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %T3_X<kill>, 256, pred:%PRED_SEL_OFF
>	%T2_Z<def> = MOV %T2_Z<kill>, 1, pred:%PRED_SEL_OFF
>	%T3_X<def> = RECIPSQRT_CLAMPED_eg %T2_W<kill>, pred:%PRED_SEL_OFF
>	%T2_W<def> = MOV %C9_W, 1, pred:%PRED_SEL_OFF
>	BUNDLE %T3_X<imp-def>, %T3_Y<imp-def>, %T3_Z<imp-def>, %T3_W<imp-def>, %T3_X<imp-use>, %PRED_SEL_OFF<imp-use>
>	  * %T3_X<def> = RECIP_IEEE_cm %T3_X, pred:%PRED_SEL_OFF, 0; flags: 
>	  * %T3_Y<def> = RECIP_IEEE_cm %T3_X<internal>, pred:%PRED_SEL_OFF, 0; flags: 
>	  * %T3_Z<def> = RECIP_IEEE_cm %T3_X<internal>, pred:%PRED_SEL_OFF, 0; flags: 
>	  * %T3_W<def> = RECIP_IEEE_cm %T3_X<internal>, pred:%PRED_SEL_OFF, 0; flags: 
>	%T3_W<def> = MOV_IMM_F32 %ALU_LITERAL_X, pred:%PRED_SEL_OFF, 1.000000e+00
>	%T3_Y<def> = MOV %T3_Z, 0, pred:%noreg
>	%T5_X<def> = MUL %C27_X, %C28_X, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MUL %C27_X, %C28_Y, pred:%PRED_SEL_OFF
>	%T5_X<def> = MULADD_eg %C27_Y, %C29_X, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MULADD_eg %C27_Y, %C29_Y, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MUL %C27_X, %C28_Z, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MULADD_eg %C27_Y, %C29_Z, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T5_W<def> = MUL %C27_X, %C28_W, pred:%PRED_SEL_OFF
>	%T5_X<def> = MULADD_eg %C27_Z, %C30_X, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MULADD_eg %C27_Z, %C30_Y, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T5_W<def> = MULADD_eg %C27_Y, %C29_W, %T5_W<kill>, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MULADD_eg %C27_Z, %C30_Z, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T5_X<def> = MULADD_eg %C27_W, %C31_X, %T5_X<kill>, pred:%PRED_SEL_OFF
>	%T5_Y<def> = MULADD_eg %C27_W, %C31_Y, %T5_Y<kill>, pred:%PRED_SEL_OFF
>	%T5_W<def> = MULADD_eg %C27_Z, %C30_W, %T5_W<kill>, pred:%PRED_SEL_OFF
>	%T5_Z<def> = MULADD_eg %C27_W, %C31_Z, %T5_Z<kill>, pred:%PRED_SEL_OFF
>	%T5_W<def> = MULADD_eg %C27_W, %C31_W, %T5_W<kill>, pred:%PRED_SEL_OFF
>	RETURN %T5_W<imp-use,kill>, %T5_Z<imp-use,kill>, %T5_Y<imp-use,kill>, %T5_X<imp-use,kill>, %T4_W<imp-use,kill>, %T4_Z<imp-use,kill>, %T4_Y<imp-use,kill>, %T4_X<imp-use,kill>, %T3_W<imp-use,kill>, %T3_Z<imp-use,kill>, %T3_Y<imp-use,kill>, %T3_X<imp-use,kill>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>
>
># End machine code for function main.
>
>bytecode 350 dw -- 11 gprs ---------------------
>     C
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST:0x13 COND:0 POP_COUNT:0
>0002 80000008 ALU ADDR:16 KCACHE_MODE0:2 KCACHE_BANK0:0 KCACHE_BANK1:0
>0003 A1DC0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:120
>0016 80000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0017 00000C90 * INST:0x19 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0018 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0019 00800C90   INST:0x19 DST(SEL:4 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0020 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0021 20800C90   INST:0x19 DST(SEL:4 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0022 00000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0023 40800C90   INST:0x19 DST(SEL:4 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0024 80000C03   SRC0(SEL:3 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0025 60800C90 * INST:0x19 DST(SEL:4 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0026 80000084   SRC0(SEL:132 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0027 01400C90 * INST:0x19 DST(SEL:10 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0028 80000086   SRC0(SEL:134 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0029 01200C90 * INST:0x19 DST(SEL:9 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0030 80000085   SRC0(SEL:133 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0031 01000C90 * INST:0x19 DST(SEL:8 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0032 8000008C   SRC0(SEL:140 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0033 00E00C90 * INST:0x19 DST(SEL:7 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0034 80000092   SRC0(SEL:146 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0035 00C00C90 * INST:0x19 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0036 0000008A   SRC0(SEL:138 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0037 00A00C90   INST:0x19 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0038 800000F8   SRC0(SEL:248 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0039 40600C90 * INST:0x19 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0040 800008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0041 61400C90 * INST:0x19 DST(SEL:10 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0042 00000884   SRC0(SEL:132 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0043 41400C90   INST:0x19 DST(SEL:10 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0044 80000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0045 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0046 80000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0047 40000C90 * INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0048 00000484   SRC0(SEL:132 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0049 21400C90   INST:0x19 DST(SEL:10 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0050 80000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0051 61200C90 * INST:0x19 DST(SEL:9 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0052 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0053 20000C90   INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0054 00000886   SRC0(SEL:134 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0055 41200C90   INST:0x19 DST(SEL:9 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0056 80000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0057 61000C90 * INST:0x19 DST(SEL:8 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0058 00014000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:10 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0059 00405F10   INST:0xbe DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0060 008144FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:10 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0061 20405F00   INST:0xbe DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0062 01014800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:10 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0063 40405F00   INST:0xbe DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0064 81814C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:10 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0065 60405F00 * INST:0xbe DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0066 0010E0FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:135 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0067 00400090   INST:0x1 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0068 80000885   SRC0(SEL:133 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0069 41000C90 * INST:0x19 DST(SEL:8 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0070 80000486   SRC0(SEL:134 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0071 21200C90 * INST:0x19 DST(SEL:9 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0072 00012000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:9 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0073 00605F10   INST:0xbe DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0074 009FC400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0075 20605F00   INST:0xbe DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0076 01012800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:9 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0077 40605F00   INST:0xbe DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0078 81812C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:9 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0079 60605F00 * INST:0xbe DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0080 8110E0FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:135 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0081 20600090 * INST:0x1 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0082 80000485   SRC0(SEL:133 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0083 21000C90 * INST:0x19 DST(SEL:8 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0084 00010000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:8 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0085 00605F10   INST:0xbe DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0086 009FC400   SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0087 20605F00   INST:0xbe DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0088 01010800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:8 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0089 40605F00   INST:0xbe DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0090 81810C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:8 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0091 60605F00 * INST:0xbe DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0092 0090E0FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:135 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0093 00600090   INST:0x1 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0094 80000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0095 60E00C90 * INST:0x19 DST(SEL:7 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0096 0000088C   SRC0(SEL:140 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0097 40E00C90   INST:0x19 DST(SEL:7 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0098 80000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0099 60400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0100 0000048C   SRC0(SEL:140 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0101 20E00C90   INST:0x19 DST(SEL:7 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0102 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0103 40400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0104 80000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0105 60A00C90 * INST:0x19 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0106 00000003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0107 20400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0108 80000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0109 60C00C90 * INST:0x19 DST(SEL:6 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0110 0000E002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:7 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0111 00605F10   INST:0xbe DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0112 0080E4FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:7 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0113 20605F00   INST:0xbe DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0114 0100E802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:7 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0115 40605F00   INST:0xbe DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0116 8180EC02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:7 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0117 60605F00 * INST:0xbe DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0118 010060FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:3 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0119 00600190   INST:0x3 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0120 8000088A   SRC0(SEL:138 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0121 40A00C90 * INST:0x19 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0122 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0123 00E04190   INST:0x83 DST(SEL:7 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0124 00000492   SRC0(SEL:146 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0125 20C00C90   INST:0x19 DST(SEL:6 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0126 80000892   SRC0(SEL:146 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0127 40C00C90 * INST:0x19 DST(SEL:6 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0128 8000048A   SRC0(SEL:138 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0129 20A00C90 * INST:0x19 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0130 0000C002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:6 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0131 00605F10   INST:0xbe DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0132 0080C402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:6 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0133 20605F00   INST:0xbe DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0134 0100C802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:6 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0135 40605F00   INST:0xbe DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0136 8180CC02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:6 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0137 60605F00 * INST:0xbe DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0138 00000090   SRC0(SEL:144 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0139 00000C90   INST:0x19 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0140 810060FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:3 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0141 60600190 * INST:0x3 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0142 0000A002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:5 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0143 00605F10   INST:0xbe DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0144 0080A402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:5 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0145 20605F00   INST:0xbe DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0146 0100A802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:5 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0147 40605F00   INST:0xbe DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0148 8180AC02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:5 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0149 60605F00 * INST:0xbe DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0150 8012C001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:150 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0151 40A00090 * INST:0x1 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0152 00100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0153 00A80090   INST:0x1 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:2 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0154 01006003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:3 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0155 20600190   INST:0x3 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0156 80000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0157 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0158 0000E088   SRC0(SEL:136 REL:0 CHAN:0 NEG:0) SRC1(SEL:7 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0159 20A00090   INST:0x1 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0160 8012E401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:151 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0161 60A28805 * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0162 8011208D   SRC0(SEL:141 REL:0 CHAN:0 NEG:0) SRC1(SEL:137 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0163 00C00010 * INST:0x0 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0164 80000890   SRC0(SEL:144 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0165 40000C90 * INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0166 00000405   SRC0(SEL:5 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0167 20A04090   INST:0x81 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0168 80900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0169 40C00090 * INST:0x1 DST(SEL:6 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0170 809FC003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0171 00636803 * INST:0x1b DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0172 00102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0173 00A28005   INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:0 NEG:0)
>0174 8112C001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:150 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0175 20A00090 * INST:0x1 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0176 00104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0177 40A280FE   INST:0x14 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0178 80130801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:152 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0179 60A28C05 * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:3 NEG:0)
>0180 80000C03   SRC0(SEL:3 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0181 60604190 * INST:0x83 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0182 0011C403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:142 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0183 00C28006   INST:0x14 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:0 NEG:0)
>0184 819FC088   SRC0(SEL:136 REL:0 CHAN:0 NEG:0) SRC1(SEL:254 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0185 60600090 * INST:0x1 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0186 8091248D   SRC0(SEL:141 REL:0 CHAN:1 NEG:0) SRC1(SEL:137 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0187 00A00010 * INST:0x0 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0188 80000490   SRC0(SEL:144 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0189 20000C90 * INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0190 01100001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0191 20C00090   INST:0x1 DST(SEL:6 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0192 80902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0193 60C28806 * INST:0x14 DST(SEL:6 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:2 NEG:0)
>0194 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0195 00405F00   INST:0xbe DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0196 00800402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0197 20405F00   INST:0xbe DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0198 01000802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0199 40405F00   INST:0xbe DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0200 81800C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0201 60405F10 * INST:0xbe DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0202 8092C001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:150 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0203 40C00090 * INST:0x1 DST(SEL:6 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0204 00904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0205 20428C06   INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:3 NEG:0)
>0206 81006C02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:3 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0207 40400190 * INST:0x3 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0208 00106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0209 00428805   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0210 8112E401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:151 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0211 20A28405 * INST:0x14 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0212 80132C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:153 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0213 00028C05 * INST:0x14 DST(SEL:0 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:3 NEG:0)
>0214 8011E003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:143 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0215 00C28006 * INST:0x14 DST(SEL:6 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:0 NEG:0)
>0216 8111288D   SRC0(SEL:141 REL:0 CHAN:2 NEG:0) SRC1(SEL:137 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0217 40A00010 * INST:0x0 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0218 01900001   SRC0(SEL:1 REL:0 CHAN:0 NEG:0) SRC1(SEL:128 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0219 00200090   INST:0x1 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0220 8091C403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:142 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0221 60A28005 * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:0 NEG:0)
>0222 0092E401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:151 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0223 00A28806   INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:2 NEG:0)
>0224 01102401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0225 20C28406   INST:0x14 DST(SEL:6 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:1 NEG:0)
>0226 80000C03   SRC0(SEL:3 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0227 60604090 * INST:0x81 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0228 819FCC02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:254 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0229 60436803 * INST:0x1b DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:2 NEG:0)
>0230 0000C093   SRC0(SEL:147 REL:0 CHAN:0 NEG:0) SRC1(SEL:6 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0231 20600010   INST:0x0 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0232 8111C403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:142 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0233 40A28805 * INST:0x14 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0234 80906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0235 20428402 * INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:1 NEG:0)
>0236 81130801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:152 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0237 60628405 * INST:0x14 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0238 01104801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0239 20A28406   INST:0x14 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:6 REL:0 CHAN:1 NEG:0)
>0240 8091E003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:143 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0241 60A28C05 * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:3 NEG:0)
>0242 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0243 00200C90   INST:0x19 DST(SEL:1 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0244 81902401   SRC0(SEL:1 REL:0 CHAN:1 NEG:0) SRC1(SEL:129 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0245 20228001 * INST:0x14 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:1 REL:0 CHAN:0 NEG:0)
>0246 00930801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:152 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0247 00AA8005   INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:2 SRC2(SEL:5 REL:0 CHAN:0 NEG:0)
>0248 80000803   SRC0(SEL:3 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0249 60000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0250 8111E003   SRC0(SEL:3 REL:0 CHAN:0 NEG:0) SRC1(SEL:143 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0251 00628805 * INST:0x14 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0252 01106C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0253 00428405   INST:0x14 DST(SEL:2 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0254 8180A493   SRC0(SEL:147 REL:0 CHAN:1 NEG:0) SRC1(SEL:5 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0255 20A00010 * INST:0x0 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0004 80000080 ALU ADDR:256 KCACHE_MODE0:2 KCACHE_BANK0:0 KCACHE_BANK1:0
>0005 A0B80000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:47
>0256 00128802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:148 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0257 20628403   INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0258 81132C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:153 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0259 60628C03 * INST:0x14 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:3 NEG:0)
>0260 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0261 20200C90   INST:0x19 DST(SEL:1 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0262 81904801   SRC0(SEL:1 REL:0 CHAN:2 NEG:0) SRC1(SEL:130 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0263 40228401 * INST:0x14 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:1 REL:0 CHAN:1 NEG:0)
>0264 00928802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:148 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0265 20428405   INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0266 80000C03   SRC0(SEL:3 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0267 40000C90 * INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0268 80932C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:153 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0269 60628005 * INST:0x14 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:0 NEG:0)
>0270 8012AC02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:149 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0271 20628403 * INST:0x14 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:3 REL:0 CHAN:1 NEG:0)
>0272 00006893   SRC0(SEL:147 REL:0 CHAN:2 NEG:0) SRC1(SEL:3 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0273 00600010   INST:0x0 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0274 00000002   SRC0(SEL:2 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0275 40200C90   INST:0x19 DST(SEL:1 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0276 81906C01   SRC0(SEL:1 REL:0 CHAN:3 NEG:0) SRC1(SEL:131 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0277 60228801 * INST:0x14 DST(SEL:1 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:1 REL:0 CHAN:2 NEG:0)
>0278 0092AC02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:149 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0279 20428402   INST:0x14 DST(SEL:2 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:1 NEG:0)
>0280 81128802   SRC0(SEL:2 REL:0 CHAN:2 NEG:0) SRC1(SEL:148 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0281 404280FE * INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:0 NEG:0)
>0282 00000403   SRC0(SEL:3 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0283 80400C90   INST:0x19 DST(SEL:2 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0284 80000C03   SRC0(SEL:3 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0285 20000C90 * INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0286 00000000   SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0287 00605F10   INST:0xbe DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0288 009FC4FE   SRC0(SEL:254 REL:0 CHAN:1 NEG:0) SRC1(SEL:254 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0289 20605F00   INST:0xbe DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0290 01000800   SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0291 40605F00   INST:0xbe DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0292 81800C00   SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0293 60605F00 * INST:0xbe DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:0 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0294 00000402   SRC0(SEL:2 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0295 A0400C90   INST:0x19 DST(SEL:2 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0296 0112AC02   SRC0(SEL:2 REL:0 CHAN:3 NEG:0) SRC1(SEL:149 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0297 40428802   INST:0x14 DST(SEL:2 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:2 REL:0 CHAN:2 NEG:0)
>0298 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0299 60400C91 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:1 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0300 00000CFE   SRC0(SEL:254 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0301 00604390   INST:0x87 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0302 000008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0303 C0400C90   INST:0x19 DST(SEL:2 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0304 80000C89   SRC0(SEL:137 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0305 E0400C90 * INST:0x19 DST(SEL:2 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0306 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0307 00604310 * INST:0x86 DST(SEL:3 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0308 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0309 20604310   INST:0x86 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0310 000000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0311 40604310   INST:0x86 DST(SEL:3 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0312 800000FE   SRC0(SEL:254 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0313 60604310 * INST:0x86 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0314 0013809B   SRC0(SEL:155 REL:0 CHAN:0 NEG:0) SRC1(SEL:156 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0315 00A00090   INST:0x1 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0316 000008FE   SRC0(SEL:254 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0317 20600C90   INST:0x19 DST(SEL:3 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0318 800000F9   SRC0(SEL:249 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0319 60600C90 * INST:0x19 DST(SEL:3 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0320 8093809B   SRC0(SEL:155 REL:0 CHAN:0 NEG:0) SRC1(SEL:156 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0321 20A00090 * INST:0x1 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0322 0013A49B   SRC0(SEL:155 REL:0 CHAN:1 NEG:0) SRC1(SEL:157 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0323 00A28005   INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:0 NEG:0)
>0324 8093A49B   SRC0(SEL:155 REL:0 CHAN:1 NEG:0) SRC1(SEL:157 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0325 20A284FE * INST:0x14 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:1 NEG:0)
>0326 8113809B   SRC0(SEL:155 REL:0 CHAN:0 NEG:0) SRC1(SEL:156 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0327 40A00090 * INST:0x1 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0328 8113A49B   SRC0(SEL:155 REL:0 CHAN:1 NEG:0) SRC1(SEL:157 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0329 40A288FE * INST:0x14 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:2 NEG:0)
>0330 8193809B   SRC0(SEL:155 REL:0 CHAN:0 NEG:0) SRC1(SEL:156 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0331 60A00090 * INST:0x1 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0
>0332 0013C89B   SRC0(SEL:155 REL:0 CHAN:2 NEG:0) SRC1(SEL:158 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0333 00A28005   INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:0 NEG:0)
>0334 8093C89B   SRC0(SEL:155 REL:0 CHAN:2 NEG:0) SRC1(SEL:158 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0335 20A28405 * INST:0x14 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0336 8193A49B   SRC0(SEL:155 REL:0 CHAN:1 NEG:0) SRC1(SEL:157 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0337 60A28C05 * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:3 NEG:0)
>0338 8113C89B   SRC0(SEL:155 REL:0 CHAN:2 NEG:0) SRC1(SEL:158 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0339 40A28805 * INST:0x14 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0340 0013EC9B   SRC0(SEL:155 REL:0 CHAN:3 NEG:0) SRC1(SEL:159 REL:0 CHAN:0 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0341 00A28005   INST:0x14 DST(SEL:5 CHAN:0 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:0 NEG:0)
>0342 8093EC9B   SRC0(SEL:155 REL:0 CHAN:3 NEG:0) SRC1(SEL:159 REL:0 CHAN:1 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0343 20A28405 * INST:0x14 DST(SEL:5 CHAN:1 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:1 NEG:0)
>0344 8193C89B   SRC0(SEL:155 REL:0 CHAN:2 NEG:0) SRC1(SEL:158 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0345 60A28C05 * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:3 NEG:0)
>0346 0113EC9B   SRC0(SEL:155 REL:0 CHAN:3 NEG:0) SRC1(SEL:159 REL:0 CHAN:2 NEG:0 IM:0) PRED_SEL:0 LAST:0)
>0347 40A28805   INST:0x14 DST(SEL:5 CHAN:2 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:5 REL:0 CHAN:2 NEG:0)
>0348 8193EC9B   SRC0(SEL:155 REL:0 CHAN:3 NEG:0) SRC1(SEL:159 REL:0 CHAN:3 NEG:0 IM:0) PRED_SEL:0 LAST:1)
>0349 60A28CFE * INST:0x14 DST(SEL:5 CHAN:3 REL:0 CLAMP:0) BANK_SWIZZLE:0 SRC2(SEL:254 REL:0 CHAN:3 NEG:0)
>0006 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0007 95000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:1 EOP:0
>0008 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0009 94C00688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x53 BURST_COUNT:1 EOP:0
>0010 C001C001 EXPORT GPR:3 ELEM_SIZE:3 ARRAY_BASE:1 TYPE:2
>0011 94C00B20 EXPORT SWIZ_X:0 SWIZ_Y:4 SWIZ_Z:4 SWIZ_W:5 BARRIER:1 INST:0x53 BURST_COUNT:1 EOP:0
>0012 C0024002 EXPORT GPR:4 ELEM_SIZE:3 ARRAY_BASE:2 TYPE:2
>0013 95010688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x54 BURST_COUNT:2 EOP:0
>0014 00000000 CF ADDR:0
>0015 88000000 CF INST:0x20 COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>31.08.2012 14:35:08 axv p
>INFO: Saving and pausing game...
>31.08.2012 14:35:08 net.minecraft.server.MinecraftServer a
>INFO: Saving chunks for level 'TÃ¤scht'/Overworld
>31.08.2012 14:35:08 net.minecraft.server.MinecraftServer a
>INFO: Saving chunks for level 'TÃ¤scht'/Nether
>31.08.2012 14:35:08 net.minecraft.server.MinecraftServer a
>INFO: Saving chunks for level 'TÃ¤scht'/The End
>Stopping!
>31.08.2012 14:35:10 net.minecraft.server.MinecraftServer j
>INFO: Stopping server
>31.08.2012 14:35:10 net.minecraft.server.MinecraftServer j
>INFO: Saving players
>31.08.2012 14:35:10 net.minecraft.server.MinecraftServer j
>INFO: Saving worlds
>31.08.2012 14:35:10 net.minecraft.server.MinecraftServer a
>INFO: Saving chunks for level 'TÃ¤scht'/Overworld
>31.08.2012 14:35:10 net.minecraft.server.MinecraftServer a
>INFO: Saving chunks for level 'TÃ¤scht'/Nether
>31.08.2012 14:35:10 net.minecraft.server.MinecraftServer a
>INFO: Saving chunks for level 'TÃ¤scht'/The End
>
>SoundSystem shutting down...
>    Author: Paul Lamb, www.paulscode.com
>

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Attachments on bug 54230: 66294 | 66295 | 66296 | 66297 | 66403 | 66404

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