Attachment 6918 Details for Bug 3621 – patch

[patch] patch

superpatch.diff (text/plain), 143.83 KB, created by Alex Deucher on 2006-09-11 21:02:44 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Alex Deucher

Created: 2006-09-11 21:02:44 UTC

Size: 143.83 KB

patch

obsolete

>diff --git a/src/Makefile.am b/src/Makefile.am
>index 7e6af9c..ad64d55 100644
>--- a/src/Makefile.am
>+++ b/src/Makefile.am
>@@ -81,7 +81,7 @@ radeon_drv_ladir = @moduledir@/drivers
> radeon_drv_la_SOURCES = \
> 	radeon_accel.c radeon_mergedfb.c radeon_cursor.c radeon_dga.c \
> 	radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \
>-	radeon_vip.c radeon_misc.c $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES)
>+	radeon_vip.c radeon_misc.c radeon_display.c $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES)
> 
> theatre_detect_drv_la_LTLIBRARIES = theatre_detect_drv.la
> theatre_detect_drv_la_LDFLAGS = -module -avoid-version
>diff --git a/src/r128_dri.c b/src/r128_dri.c
>diff --git a/src/radeon.h b/src/radeon.h
>index 6402e48..089e3f8 100644
>--- a/src/radeon.h
>+++ b/src/radeon.h
>@@ -79,6 +79,13 @@ #ifdef RENDER
> #include "picturestr.h"
> #endif
> 
>+#ifndef MAX
>+#define MAX(a,b) ((a)>(b)?(a):(b))
>+#endif
>+#ifndef MIN
>+#define MIN(a,b) ((a)>(b)?(b):(a))
>+#endif
>+
> typedef enum {
>     OPTION_NOACCEL,
>     OPTION_SW_CURSOR,
>@@ -144,7 +151,8 @@ #endif
>     OPTION_REVERSE_DDC,
>     OPTION_LVDS_PROBE_PLL,
>     OPTION_ACCELMETHOD,
>-    OPTION_CONSTANTDPI
>+    OPTION_CONSTANTDPI,
>+    OPTION_REVERSE_DISPLAY
> } RADEONOpts;
> 
> /* ------- mergedfb support ------------- */
>@@ -254,6 +262,7 @@ typedef struct {
> 
>     CARD32            dac2_cntl;
>     CARD32            disp_output_cntl;
>+    CARD32            disp_tv_out_cntl;
>     CARD32            disp_hw_debug;
>     CARD32            disp2_merge_cntl;
>     CARD32            grph2_buffer_cntl;
>@@ -267,14 +276,16 @@ typedef struct {
> 				/* Flat panel registers */
>     CARD32            fp_crtc_h_total_disp;
>     CARD32            fp_crtc_v_total_disp;
>+    CARD32            fp_crtc2_h_total_disp;
>+    CARD32            fp_crtc2_v_total_disp;
>     CARD32            fp_gen_cntl;
>     CARD32            fp2_gen_cntl;
>     CARD32            fp_h_sync_strt_wid;
>-    CARD32            fp2_h_sync_strt_wid;
>+    CARD32            fp_h2_sync_strt_wid;
>     CARD32            fp_horz_stretch;
>     CARD32            fp_panel_cntl;
>     CARD32            fp_v_sync_strt_wid;
>-    CARD32            fp2_v_sync_strt_wid;
>+    CARD32            fp_v2_sync_strt_wid;
>     CARD32            fp_vert_stretch;
>     CARD32            lvds_gen_cntl;
>     CARD32            lvds_pll_cntl;
>@@ -291,6 +302,7 @@ typedef struct {
>     unsigned          ppll_ref_div;
>     unsigned          ppll_div_3;
>     CARD32            htotal_cntl;
>+    CARD32            vclk_cntl;
> 
> 				/* Computed values for PLL2 */
>     CARD32            dot_clock_freq_2;
>@@ -302,6 +314,7 @@ typedef struct {
>     CARD32            p2pll_ref_div;
>     CARD32            p2pll_div_0;
>     CARD32            htotal_cntl2;
>+    CARD32            pixclks_cntl;
> 
> 				/* Pallet */
>     Bool              palette_valid;
>@@ -797,6 +810,8 @@ #endif
>     int                MaxSurfaceWidth;
>     int                MaxLines;
> 
>+    CARD32            tv_dac_adj;
>+
> } RADEONInfoRec, *RADEONInfoPtr;
> 
> #define RADEONWaitForFifo(pScrn, entries)				\
>@@ -861,6 +876,20 @@ extern Bool        RADEONGetLVDSInfoFrom
> extern Bool        RADEONGetTMDSInfoFromBIOS (ScrnInfoPtr pScrn);
> extern Bool        RADEONGetHardCodedEDIDFromBIOS (ScrnInfoPtr pScrn);
> 
>+extern xf86MonPtr  RADEONProbeDDC(ScrnInfoPtr pScrn, int indx);
>+extern void        RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
>+extern Bool        RADEONI2cInit(ScrnInfoPtr pScrn);
>+extern void        RADEONSetSyncRangeFromEdid(ScrnInfoPtr pScrn, int flag);
>+extern Bool        RADEONMapControllers(ScrnInfoPtr pScrn);
>+extern void        RADEONEnableDisplay(ScrnInfoPtr pScrn, RADEONController* pCRTC, BOOL bEnable);
>+extern void        RADEONGetPanelInfo(ScrnInfoPtr pScrn);
>+extern void        RADEONGetTVDacAdjInfo(ScrnInfoPtr pScrn);
>+extern void        RADEONUnblank(ScrnInfoPtr pScrn);
>+extern void        RADEONBlank(ScrnInfoPtr pScrn);
>+extern void        RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
>+						   int PowerManagementMode,
>+						   int flags);
>+
> #ifdef XF86DRI
> #ifdef USE_XAA
> extern void        RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a);
>diff --git a/src/radeon_driver.c b/src/radeon_driver.c
>index 770bb02..c42e79a 100644
>--- a/src/radeon_driver.c
>+++ b/src/radeon_driver.c
>@@ -112,31 +112,19 @@ #include <X11/extensions/dpms.h>
> #include "atipciids.h"
> #include "radeon_chipset.h"
> 
>-#ifndef MAX
>-#define MAX(a,b) ((a)>(b)?(a):(b))
>-#endif
>-#ifndef MIN
>-#define MIN(a,b) ((a)>(b)?(b):(a))
>-#endif
>-
> 				/* Forward definitions for driver functions */
> static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen);
> static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode);
> static void RADEONSave(ScrnInfoPtr pScrn);
> static void RADEONRestore(ScrnInfoPtr pScrn);
> static Bool RADEONModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode);
>-static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
>-					    int PowerManagementMode,
>-					    int flags);
>-static void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
> 
> static void RADEONGetMergedFBOptions(ScrnInfoPtr pScrn);
> static int RADEONValidateMergeModes(ScrnInfoPtr pScrn);
> static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode);
> static void RADEONForceSomeClocks(ScrnInfoPtr pScrn);
>-static void RADEONUpdatePanelSize(ScrnInfoPtr pScrn);
> static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
>-static xf86MonPtr RADEONProbeDDC(ScrnInfoPtr pScrn, int indx);
>+xf86MonPtr RADEONProbeDDC(ScrnInfoPtr pScrn, int indx);
> static RADEONMonitorType RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac);
>   
> 
>@@ -213,7 +201,8 @@ #endif
>     { OPTION_REVERSE_DDC,    "ReverseDDC",       OPTV_BOOLEAN, {0}, FALSE },
>     { OPTION_LVDS_PROBE_PLL, "LVDSProbePLL",     OPTV_BOOLEAN, {0}, FALSE },
>     { OPTION_ACCELMETHOD,    "AccelMethod",      OPTV_STRING,  {0}, FALSE },
>-    { OPTION_CONSTANTDPI,    "ConstantDPI",	 OPTV_BOOLEAN,	{0}, FALSE },
>+    { OPTION_CONSTANTDPI,    "ConstantDPI",	 OPTV_BOOLEAN, {0}, FALSE },
>+    { OPTION_REVERSE_DISPLAY,"ReverseDisplay",   OPTV_BOOLEAN, {0}, FALSE },
>     { -1,                    NULL,               OPTV_NONE,    {0}, FALSE }
> };
> 
>@@ -460,28 +449,6 @@ static struct
>     {720, 400, 70},
> };
> 
>-static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] =
>-{
>-    {{0, 0}, {0, 0}, {0, 0}, {0, 0}},				/*CHIP_FAMILY_UNKNOW*/
>-    {{0, 0}, {0, 0}, {0, 0}, {0, 0}},				/*CHIP_FAMILY_LEGACY*/
>-    {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},	/*CHIP_FAMILY_RADEON*/
>-    {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},	/*CHIP_FAMILY_RV100*/
>-    {{0, 0}, {0, 0}, {0, 0}, {0, 0}},				/*CHIP_FAMILY_RS100*/
>-    {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},	/*CHIP_FAMILY_RV200*/
>-    {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},	/*CHIP_FAMILY_RS200*/
>-    {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},	/*CHIP_FAMILY_R200*/
>-    {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},	/*CHIP_FAMILY_RV250*/
>-    {{0, 0}, {0, 0}, {0, 0}, {0, 0}},				/*CHIP_FAMILY_RS300*/
>-    {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /*CHIP_FAMILY_RV280*/
>-    {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},		/*CHIP_FAMILY_R300*/
>-    {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},		/*CHIP_FAMILY_R350*/
>-    {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},	/*CHIP_FAMILY_RV350*/
>-    {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},	/*CHIP_FAMILY_RV380*/
>-    {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},		/*CHIP_FAMILY_R420*/
>-    {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},		/*CHIP_FAMILY_RV410*/ /* FIXME: just values from r420 used... */
>-    {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},	/*CHIP_FAMILY_RS400*/ /* FIXME: just values from rv380 used... */
>-};
>-
> #ifdef XFree86LOADER
> static int getRADEONEntityIndex(void)
> {
>@@ -865,78 +832,6 @@ void RADEONWaitForVerticalSync2(ScrnInfo
>     }
> }
> 
>-/* Blank screen */
>-static void RADEONBlank(ScrnInfoPtr pScrn)
>-{
>-    RADEONInfoPtr  info       = RADEONPTR(pScrn);
>-    unsigned char *RADEONMMIO = info->MMIO;
>-
>-    if (!info->IsSecondary) {
>-	switch(info->DisplayType) {
>-	case MT_LCD:
>-	case MT_CRT:
>-	case MT_DFP:
>-	    OUTREGP(RADEON_CRTC_EXT_CNTL,
>-		    RADEON_CRTC_DISPLAY_DIS,
>-		    ~(RADEON_CRTC_DISPLAY_DIS));
>-	    break;
>-
>-	case MT_NONE:
>-	default:
>-	    break;
>-	}
>-	if (info->MergedFB)
>-	    OUTREGP(RADEON_CRTC2_GEN_CNTL,
>-		    RADEON_CRTC2_DISP_DIS,
>-		    ~(RADEON_CRTC2_DISP_DIS));
>-    } else {
>-	OUTREGP(RADEON_CRTC2_GEN_CNTL,
>-		RADEON_CRTC2_DISP_DIS,
>-		~(RADEON_CRTC2_DISP_DIS));
>-    }
>-}
>-
>-/* Unblank screen */
>-static void RADEONUnblank(ScrnInfoPtr pScrn)
>-{
>-    RADEONInfoPtr  info       = RADEONPTR(pScrn);
>-    unsigned char *RADEONMMIO = info->MMIO;
>-
>-    if (!info->IsSecondary) {
>-	switch (info->DisplayType) {
>-	case MT_LCD:
>-	case MT_CRT:
>-	case MT_DFP:
>-	    OUTREGP(RADEON_CRTC_EXT_CNTL,
>-		    RADEON_CRTC_CRT_ON,
>-		    ~(RADEON_CRTC_DISPLAY_DIS));
>-	    break;
>-
>-	case MT_NONE:
>-	default:
>-	    break;
>-	}
>-	if (info->MergedFB)
>-	    OUTREGP(RADEON_CRTC2_GEN_CNTL,
>-		    0,
>-		    ~(RADEON_CRTC2_DISP_DIS));
>-    } else {
>-	switch (info->DisplayType) {
>-	case MT_LCD:
>-	case MT_DFP:
>-	case MT_CRT:
>-	    OUTREGP(RADEON_CRTC2_GEN_CNTL,
>-		    0,
>-		    ~(RADEON_CRTC2_DISP_DIS));
>-	    break;
>-
>-	case MT_NONE:
>-	default:
>-	    break;
>-	}
>-    }
>-}
>-
> /* Compute log base 2 of val */
> int RADEONMinBits(int val)
> {
>@@ -953,397 +848,6 @@ static int RADEONDiv(int n, int d)
>     return (n + (d / 2)) / d;
> }
> 
>-static RADEONMonitorType RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, RADEONDDCType DDCType, RADEONConnector* port)
>-{
>-    RADEONInfoPtr info = RADEONPTR(pScrn);
>-    unsigned char *RADEONMMIO = info->MMIO;
>-    unsigned long DDCReg;
>-    RADEONMonitorType MonType = MT_NONE;
>-    xf86MonPtr* MonInfo = &port->MonInfo;
>-    int i, j;
>-    RADEONEntPtr pRADEONEnt  = RADEONEntPriv(pScrn);
>-    int vbeProbe = FALSE;
>-
>-    DDCReg = info->DDCReg;
>-    switch(DDCType)
>-    {
>-    case DDC_MONID:
>-	info->DDCReg = RADEON_GPIO_MONID;
>-	break;
>-    case DDC_DVI:
>-	info->DDCReg = RADEON_GPIO_DVI_DDC;
>-	break;
>-    case DDC_VGA:
>-	info->DDCReg = RADEON_GPIO_VGA_DDC;
>-	break;
>-    case DDC_CRT2:
>-	info->DDCReg = RADEON_GPIO_CRT2_DDC;
>-	break;
>-    default:
>-	info->DDCReg = DDCReg;
>-	/* Fall through, can still try ... 
>-	return MT_NONE;
>-	*/
>-    }
>-
>-    /* Read and output monitor info using DDC2 over I2C bus */
>-    if (info->pI2CBus && info->ddc2) {
>-	OUTREG(info->DDCReg, INREG(info->DDCReg) &
>-	       (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1));
>-
>-	/* For some old monitors (like Compaq Presario FP500), we need
>-	 * following process to initialize/stop DDC
>-	 */
>-	OUTREG(info->DDCReg, INREG(info->DDCReg) & ~(RADEON_GPIO_EN_1));
>-	for (j = 0; j < 3; j++) {
>-	    OUTREG(info->DDCReg,
>-		   INREG(info->DDCReg) & ~(RADEON_GPIO_EN_0));
>-	    usleep(13000);
>-
>-	    OUTREG(info->DDCReg,
>-		   INREG(info->DDCReg) & ~(RADEON_GPIO_EN_1));
>-	    for (i = 0; i < 10; i++) {
>-		usleep(15000);
>-		if (INREG(info->DDCReg) & RADEON_GPIO_Y_1)
>-		    break;
>-	    }
>-	    if (i == 10) continue;
>-
>-	    usleep(15000);
>-
>-	    OUTREG(info->DDCReg, INREG(info->DDCReg) | RADEON_GPIO_EN_0);
>-	    usleep(15000);
>-
>-	    OUTREG(info->DDCReg, INREG(info->DDCReg) | RADEON_GPIO_EN_1);
>-	    usleep(15000);
>-	    OUTREG(info->DDCReg,
>-		   INREG(info->DDCReg) & ~(RADEON_GPIO_EN_0));
>-	    usleep(15000);
>-	    *MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, info->pI2CBus);
>-
>-	    OUTREG(info->DDCReg, INREG(info->DDCReg) | RADEON_GPIO_EN_1);
>-	    OUTREG(info->DDCReg, INREG(info->DDCReg) | RADEON_GPIO_EN_0);
>-	    usleep(15000);
>-	    OUTREG(info->DDCReg,
>-		   INREG(info->DDCReg) & ~(RADEON_GPIO_EN_1));
>-	    for (i = 0; i < 5; i++) {
>-		usleep(15000);
>-		if (INREG(info->DDCReg) & RADEON_GPIO_Y_1)
>-		    break;
>-	    }
>-	    usleep(15000);
>-	    OUTREG(info->DDCReg,
>-		   INREG(info->DDCReg) & ~(RADEON_GPIO_EN_0));
>-	    usleep(15000);
>-
>-	    OUTREG(info->DDCReg, INREG(info->DDCReg) | RADEON_GPIO_EN_1);
>-	    OUTREG(info->DDCReg, INREG(info->DDCReg) | RADEON_GPIO_EN_0);
>-	    usleep(15000);
>-	    if(*MonInfo) break;
>-	}
>-    } else {
>-	xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DDC2/I2C is not properly initialized\n");
>-	MonType = MT_NONE;
>-    }
>-
>-    OUTREG(info->DDCReg, INREG(info->DDCReg) &
>-	   ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1));
>-
>-    if ((!*MonInfo) && ((port == &pRADEONEnt->PortInfo[0]) ||
>-	(RADEONCrtIsPhysicallyConnected(pScrn, !(pRADEONEnt->PortInfo[1].DACType)) 
>-	== MT_CRT))) {
>-	vbeProbe = TRUE;
>-	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VBE DDC probing on port %d ::: \n", 
>-	    (port == &pRADEONEnt->PortInfo[0])? 1:2);
>-	*MonInfo = RADEONProbeDDC(pScrn, info->pEnt->index);
>-    }
>-
>-    if (*MonInfo) {
>-	if ((*MonInfo)->rawData[0x14] & 0x80) {
>-	    /* Note some laptops have a DVI output that uses internal TMDS,
>-	     * when its DVI is enabled by hotkey, LVDS panel is not used.
>-	     * In this case, the laptop is configured as DVI+VGA as a normal 
>-	     * desktop card.
>-	     * Also for laptop, when X starts with lid closed (no DVI connection)
>-	     * both LDVS and TMDS are disable, we still need to treat it as a LVDS panel.
>-	     */
>-	    if (vbeProbe && 
>-		(RADEONCrtIsPhysicallyConnected(pScrn, !(port->DACType)) == MT_CRT)) {
>-	    	    MonType = MT_NONE;
>-	    	    *MonInfo = NULL;
>-		    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VBE probed DDC info nullified on port %d :::\n", (port == &pRADEONEnt->PortInfo[0])? 1:2);
>-		    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CRT physically connected but digital device indicated in DDC\n");
>-	    } else {
>-		if (port->TMDSType == TMDS_EXT) MonType = MT_DFP;
>-	    	else {
>-		    if ((INREG(RADEON_FP_GEN_CNTL) & (1<<7)) || !info->IsMobility)
>-		    	MonType = MT_DFP;
>-		    else 
>-		    	MonType = MT_LCD;
>-		}
>-	    }
>-	} else  {
>-	    	if ((RADEONCrtIsPhysicallyConnected(pScrn, 
>-		    !(pRADEONEnt->PortInfo[1].DACType)) == MT_CRT) && vbeProbe && 
>-		    (info->HasCRTC2) && (port == &pRADEONEnt->PortInfo[0])) {
>-	    	    MonType = MT_NONE;
>-	    	    *MonInfo = NULL;
>-		    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DDC info nullified on port 1 :::\n");
>-		    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Analog device indicated in DDC but port 2 CRT physically connected\n");
>-		} else
>-	    	    MonType = MT_CRT;
>-	}
>-    } else MonType = MT_NONE;
>-
>-    info->DDCReg = DDCReg;
>-
>-    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>-	       "DDC Type: %d, Detected Type: %d\n", DDCType, MonType);
>-
>-    return MonType;
>-}
>-
>-static RADEONMonitorType
>-RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac)
>-{
>-    RADEONInfoPtr info       = RADEONPTR(pScrn);
>-    unsigned char *RADEONMMIO = info->MMIO;
>-    int		  bConnected = 0;
>-
>-    /* the monitor either wasn't connected or it is a non-DDC CRT.
>-     * try to probe it
>-     */
>-    if(IsCrtDac) {
>-	unsigned long ulOrigVCLK_ECP_CNTL;
>-	unsigned long ulOrigDAC_CNTL;
>-	unsigned long ulOrigDAC_MACRO_CNTL;
>-	unsigned long ulOrigDAC_EXT_CNTL;
>-	unsigned long ulOrigCRTC_EXT_CNTL;
>-	unsigned long ulData;
>-	unsigned long ulMask;
>-
>-	ulOrigVCLK_ECP_CNTL = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
>-
>-	ulData              = ulOrigVCLK_ECP_CNTL;
>-	ulData             &= ~(RADEON_PIXCLK_ALWAYS_ONb
>-				| RADEON_PIXCLK_DAC_ALWAYS_ONb);
>-	ulMask              = ~(RADEON_PIXCLK_ALWAYS_ONb
>-				|RADEON_PIXCLK_DAC_ALWAYS_ONb);
>-	OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, ulData, ulMask);
>-
>-	ulOrigCRTC_EXT_CNTL = INREG(RADEON_CRTC_EXT_CNTL);
>-	ulData              = ulOrigCRTC_EXT_CNTL;
>-	ulData             |= RADEON_CRTC_CRT_ON;
>-	OUTREG(RADEON_CRTC_EXT_CNTL, ulData);
>-
>-	ulOrigDAC_EXT_CNTL = INREG(RADEON_DAC_EXT_CNTL);
>-	ulData             = ulOrigDAC_EXT_CNTL;
>-	ulData            &= ~RADEON_DAC_FORCE_DATA_MASK;
>-	ulData            |=  (RADEON_DAC_FORCE_BLANK_OFF_EN
>-			       |RADEON_DAC_FORCE_DATA_EN
>-			       |RADEON_DAC_FORCE_DATA_SEL_MASK);
>-	if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
>-	    (info->ChipFamily == CHIP_FAMILY_RV280))
>-	    ulData |= (0x01b6 << RADEON_DAC_FORCE_DATA_SHIFT);
>-	else
>-	    ulData |= (0x01ac << RADEON_DAC_FORCE_DATA_SHIFT);
>-
>-	OUTREG(RADEON_DAC_EXT_CNTL, ulData);
>-
>-	ulOrigDAC_CNTL     = INREG(RADEON_DAC_CNTL);
>-
>-	if (ulOrigDAC_CNTL & RADEON_DAC_PDWN) {
>-	    /* turn on power so testing can go through */
>-	    ulOrigDAC_MACRO_CNTL = INREG(RADEON_DAC_MACRO_CNTL);
>-	    ulOrigDAC_MACRO_CNTL &= ~(RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G |
>-		RADEON_DAC_PDWN_B);
>-	    OUTREG(RADEON_DAC_MACRO_CNTL, ulOrigDAC_MACRO_CNTL);
>-	}
>-
>-	ulData             = ulOrigDAC_CNTL;
>-	ulData            |= RADEON_DAC_CMP_EN;
>-	ulData            &= ~(RADEON_DAC_RANGE_CNTL_MASK
>-			       | RADEON_DAC_PDWN);
>-	ulData            |= 0x2;
>-
>-	OUTREG(RADEON_DAC_CNTL, ulData);
>-
>-	usleep(10000);
>-
>-	ulData     = INREG(RADEON_DAC_CNTL);
>-	bConnected =  (RADEON_DAC_CMP_OUTPUT & ulData)?1:0;
>-
>-	ulData    = ulOrigVCLK_ECP_CNTL;
>-	ulMask    = 0xFFFFFFFFL;
>-	OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, ulData, ulMask);
>-
>-	OUTREG(RADEON_DAC_CNTL,      ulOrigDAC_CNTL     );
>-	OUTREG(RADEON_DAC_EXT_CNTL,  ulOrigDAC_EXT_CNTL );
>-	OUTREG(RADEON_CRTC_EXT_CNTL, ulOrigCRTC_EXT_CNTL);
>-
>-	if (!bConnected) {
>-	    /* Power DAC down if CRT is not connected */
>-            ulOrigDAC_MACRO_CNTL = INREG(RADEON_DAC_MACRO_CNTL);
>-            ulOrigDAC_MACRO_CNTL |= (RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G |
>-	    	RADEON_DAC_PDWN_B);
>-            OUTREG(RADEON_DAC_MACRO_CNTL, ulOrigDAC_MACRO_CNTL);
>-
>-	    ulData     = INREG(RADEON_DAC_CNTL);
>-	    ulData     |= RADEON_DAC_PDWN ;
>-	    OUTREG(RADEON_DAC_CNTL, ulData);
>-    	}
>-    } else { /* TV DAC */
>-
>-        /* This doesn't seem to work reliably (maybe worse on some OEM cards),
>-           for now we always return false. If one wants to connected a
>-           non-DDC monitor on the DVI port when CRT port is also connected,
>-           he will need to explicitly tell the driver in the config file
>-           with Option MonitorLayout.
>-        */
>-        bConnected = FALSE;
>-
>-#if 0
>-	if (info->ChipFamily == CHIP_FAMILY_R200) {
>-	    unsigned long ulOrigGPIO_MONID;
>-	    unsigned long ulOrigFP2_GEN_CNTL;
>-	    unsigned long ulOrigDISP_OUTPUT_CNTL;
>-	    unsigned long ulOrigCRTC2_GEN_CNTL;
>-	    unsigned long ulOrigDISP_LIN_TRANS_GRPH_A;
>-	    unsigned long ulOrigDISP_LIN_TRANS_GRPH_B;
>-	    unsigned long ulOrigDISP_LIN_TRANS_GRPH_C;
>-	    unsigned long ulOrigDISP_LIN_TRANS_GRPH_D;
>-	    unsigned long ulOrigDISP_LIN_TRANS_GRPH_E;
>-	    unsigned long ulOrigDISP_LIN_TRANS_GRPH_F;
>-	    unsigned long ulOrigCRTC2_H_TOTAL_DISP;
>-	    unsigned long ulOrigCRTC2_V_TOTAL_DISP;
>-	    unsigned long ulOrigCRTC2_H_SYNC_STRT_WID;
>-	    unsigned long ulOrigCRTC2_V_SYNC_STRT_WID;
>-	    unsigned long ulData, i;
>-
>-	    ulOrigGPIO_MONID = INREG(RADEON_GPIO_MONID);
>-	    ulOrigFP2_GEN_CNTL = INREG(RADEON_FP2_GEN_CNTL);
>-	    ulOrigDISP_OUTPUT_CNTL = INREG(RADEON_DISP_OUTPUT_CNTL);
>-	    ulOrigCRTC2_GEN_CNTL = INREG(RADEON_CRTC2_GEN_CNTL);
>-	    ulOrigDISP_LIN_TRANS_GRPH_A = INREG(RADEON_DISP_LIN_TRANS_GRPH_A);
>-	    ulOrigDISP_LIN_TRANS_GRPH_B = INREG(RADEON_DISP_LIN_TRANS_GRPH_B);
>-	    ulOrigDISP_LIN_TRANS_GRPH_C = INREG(RADEON_DISP_LIN_TRANS_GRPH_C);
>-	    ulOrigDISP_LIN_TRANS_GRPH_D = INREG(RADEON_DISP_LIN_TRANS_GRPH_D);
>-	    ulOrigDISP_LIN_TRANS_GRPH_E = INREG(RADEON_DISP_LIN_TRANS_GRPH_E);
>-	    ulOrigDISP_LIN_TRANS_GRPH_F = INREG(RADEON_DISP_LIN_TRANS_GRPH_F);
>-
>-	    ulOrigCRTC2_H_TOTAL_DISP = INREG(RADEON_CRTC2_H_TOTAL_DISP);
>-	    ulOrigCRTC2_V_TOTAL_DISP = INREG(RADEON_CRTC2_V_TOTAL_DISP);
>-	    ulOrigCRTC2_H_SYNC_STRT_WID = INREG(RADEON_CRTC2_H_SYNC_STRT_WID);
>-	    ulOrigCRTC2_V_SYNC_STRT_WID = INREG(RADEON_CRTC2_V_SYNC_STRT_WID);
>-
>-	    ulData     = INREG(RADEON_GPIO_MONID);
>-	    ulData    &= ~RADEON_GPIO_A_0;
>-	    OUTREG(RADEON_GPIO_MONID, ulData);
>-
>-	    OUTREG(RADEON_FP2_GEN_CNTL, 0x0a000c0c);
>-
>-	    OUTREG(RADEON_DISP_OUTPUT_CNTL, 0x00000012);
>-
>-	    OUTREG(RADEON_CRTC2_GEN_CNTL, 0x06000000);
>-	    OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
>-	    OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
>-	    OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
>-	    OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
>-	    OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
>-	    OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
>-	    OUTREG(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
>-	    OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
>-	    OUTREG(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
>-	    OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
>-
>-	    for (i = 0; i < 200; i++) {
>-		ulData     = INREG(RADEON_GPIO_MONID);
>-		bConnected = (ulData & RADEON_GPIO_Y_0)?1:0;
>-		if (!bConnected) break;
>-
>-		usleep(1000);
>-	    }
>-
>-	    OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, ulOrigDISP_LIN_TRANS_GRPH_A);
>-	    OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, ulOrigDISP_LIN_TRANS_GRPH_B);
>-	    OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, ulOrigDISP_LIN_TRANS_GRPH_C);
>-	    OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, ulOrigDISP_LIN_TRANS_GRPH_D);
>-	    OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, ulOrigDISP_LIN_TRANS_GRPH_E);
>-	    OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, ulOrigDISP_LIN_TRANS_GRPH_F);
>-	    OUTREG(RADEON_CRTC2_H_TOTAL_DISP, ulOrigCRTC2_H_TOTAL_DISP);
>-	    OUTREG(RADEON_CRTC2_V_TOTAL_DISP, ulOrigCRTC2_V_TOTAL_DISP);
>-	    OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, ulOrigCRTC2_H_SYNC_STRT_WID);
>-	    OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, ulOrigCRTC2_V_SYNC_STRT_WID);
>-	    OUTREG(RADEON_CRTC2_GEN_CNTL, ulOrigCRTC2_GEN_CNTL);
>-	    OUTREG(RADEON_DISP_OUTPUT_CNTL, ulOrigDISP_OUTPUT_CNTL);
>-	    OUTREG(RADEON_FP2_GEN_CNTL, ulOrigFP2_GEN_CNTL);
>-	    OUTREG(RADEON_GPIO_MONID, ulOrigGPIO_MONID);
>-        } else {
>-	    unsigned long ulOrigPIXCLKSDATA;
>-	    unsigned long ulOrigTV_MASTER_CNTL;
>-	    unsigned long ulOrigTV_DAC_CNTL;
>-	    unsigned long ulOrigTV_PRE_DAC_MUX_CNTL;
>-	    unsigned long ulOrigDAC_CNTL2;
>-	    unsigned long ulData;
>-	    unsigned long ulMask;
>-
>-	    ulOrigPIXCLKSDATA = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
>-
>-	    ulData            = ulOrigPIXCLKSDATA;
>-	    ulData           &= ~(RADEON_PIX2CLK_ALWAYS_ONb
>-				  | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
>-	    ulMask            = ~(RADEON_PIX2CLK_ALWAYS_ONb
>-			  | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
>-	    OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, ulData, ulMask);
>-
>-	    ulOrigTV_MASTER_CNTL = INREG(RADEON_TV_MASTER_CNTL);
>-	    ulData               = ulOrigTV_MASTER_CNTL;
>-	    ulData              &= ~RADEON_TVCLK_ALWAYS_ONb;
>-	    OUTREG(RADEON_TV_MASTER_CNTL, ulData);
>-
>-	    ulOrigDAC_CNTL2 = INREG(RADEON_DAC_CNTL2);
>-	    ulData          = ulOrigDAC_CNTL2;
>-	    ulData          &= ~RADEON_DAC2_DAC2_CLK_SEL;
>-	    OUTREG(RADEON_DAC_CNTL2, ulData);
>-
>-	    ulOrigTV_DAC_CNTL = INREG(RADEON_TV_DAC_CNTL);
>-
>-	    ulData  = 0x00880213;
>-	    OUTREG(RADEON_TV_DAC_CNTL, ulData);
>-
>-	    ulOrigTV_PRE_DAC_MUX_CNTL = INREG(RADEON_TV_PRE_DAC_MUX_CNTL);
>-
>-	    ulData  =  (RADEON_Y_RED_EN
>-			| RADEON_C_GRN_EN
>-			| RADEON_CMP_BLU_EN
>-			| RADEON_RED_MX_FORCE_DAC_DATA
>-			| RADEON_GRN_MX_FORCE_DAC_DATA
>-			| RADEON_BLU_MX_FORCE_DAC_DATA);
>-            if (IS_R300_VARIANT)
>-		ulData |= 0x180 << RADEON_TV_FORCE_DAC_DATA_SHIFT;
>-	    else
>-		ulData |= 0x1f5 << RADEON_TV_FORCE_DAC_DATA_SHIFT;
>-	    OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, ulData);
>-
>-	    usleep(10000);
>-
>-	    ulData     = INREG(RADEON_TV_DAC_CNTL);
>-	    bConnected = (ulData & RADEON_TV_DAC_CMPOUT)?1:0;
>-
>-	    ulData    = ulOrigPIXCLKSDATA;
>-	    ulMask    = 0xFFFFFFFFL;
>-	    OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, ulData, ulMask);
>-
>-	    OUTREG(RADEON_TV_MASTER_CNTL, ulOrigTV_MASTER_CNTL);
>-	    OUTREG(RADEON_DAC_CNTL2, ulOrigDAC_CNTL2);
>-	    OUTREG(RADEON_TV_DAC_CNTL, ulOrigTV_DAC_CNTL);
>-	    OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, ulOrigTV_PRE_DAC_MUX_CNTL);
>-	}
>-#endif
>-    }
>-    return(bConnected ? MT_CRT : MT_NONE);
>-}
>-
> static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
> {
>     RADEONInfoPtr info = RADEONPTR(pScrn);
>@@ -1546,155 +1050,6 @@ static Bool RADEONProbePLLParameters(Scr
>     return TRUE;
> }
> 
>-static void RADEONGetPanelInfoFromReg (ScrnInfoPtr pScrn)
>-{
>-    RADEONInfoPtr info     = RADEONPTR(pScrn);
>-    unsigned char *RADEONMMIO = info->MMIO;
>-    CARD32 fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH);
>-    CARD32 fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH);
>-
>-    info->PanelPwrDly = 200;
>-    if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) {
>-	info->PanelYRes = (fp_vert_stretch>>12) + 1;
>-    } else {
>-	info->PanelYRes = (INREG(RADEON_CRTC_V_TOTAL_DISP)>>16) + 1;
>-    }
>-    if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) {
>-	info->PanelXRes = ((fp_horz_stretch>>16) + 1) * 8;
>-    } else {
>-	info->PanelXRes = ((INREG(RADEON_CRTC_H_TOTAL_DISP)>>16) + 1) * 8;
>-    }
>-    
>-    if ((info->PanelXRes < 640) || (info->PanelYRes < 480)) {
>-	info->PanelXRes = 640;
>-	info->PanelYRes = 480;
>-    }
>-
>-    if (xf86ReturnOptValBool(info->Options, OPTION_LVDS_PROBE_PLL, TRUE)) {
>-           CARD32 ppll_div_sel, ppll_val;
>-
>-           ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
>-	   RADEONPllErrataAfterIndex(info);
>-	   ppll_val = INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel);
>-           if ((ppll_val & 0x000707ff) == 0x1bb)
>-		   goto noprobe;
>-	   info->FeedbackDivider = ppll_val & 0x7ff;
>-	   info->PostDivider = (ppll_val >> 16) & 0x7;
>-	   info->RefDivider = info->pll.reference_div;
>-	   info->UseBiosDividers = TRUE;
>-
>-           xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>-                      "Existing panel PLL dividers will be used.\n");
>-    }
>- noprobe:
>-
>-    xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 
>-	       "Panel size %dx%d is derived, this may not be correct.\n"
>-		   "If not, use PanelSize option to overwrite this setting\n",
>-	       info->PanelXRes, info->PanelYRes);
>-}
>-
>-static Bool RADEONGetLVDSInfo (ScrnInfoPtr pScrn)
>-{
>-    RADEONInfoPtr info     = RADEONPTR(pScrn);
>-
>-    if (!RADEONGetLVDSInfoFromBIOS(pScrn))
>-        RADEONGetPanelInfoFromReg(pScrn);
>-
>-    /* The panel size we collected from BIOS may not be the
>-     * maximum size supported by the panel.  If not, we update
>-     * it now.  These will be used if no matching mode can be
>-     * found from EDID data.
>-     */
>-    RADEONUpdatePanelSize(pScrn);
>-
>-    /* No timing information for the native mode,
>-     * use whatever specified in the Modeline.
>-     * If no Modeline specified, we'll just pick
>-     * the VESA mode at 60Hz refresh rate which
>-     * is likely to be the best for a flat panel.
>-     */
>-    if (info->DotClock == 0) {
>-        RADEONEntPtr pRADEONEnt   = RADEONEntPriv(pScrn);
>-        DisplayModePtr  tmp_mode = NULL;
>-        xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
>-                   "No valid timing info from BIOS.\n");
>-        tmp_mode = pScrn->monitor->Modes;
>-        while(tmp_mode) {
>-            if ((tmp_mode->HDisplay == info->PanelXRes) &&
>-                (tmp_mode->VDisplay == info->PanelYRes)) {
>-
>-                float  refresh =
>-                    (float)tmp_mode->Clock * 1000.0 / tmp_mode->HTotal / tmp_mode->VTotal;
>-                if ((abs(60.0 - refresh) < 1.0) ||
>-                    (tmp_mode->type == 0)) {
>-                    info->HBlank     = tmp_mode->HTotal - tmp_mode->HDisplay;
>-                    info->HOverPlus  = tmp_mode->HSyncStart - tmp_mode->HDisplay;
>-                    info->HSyncWidth = tmp_mode->HSyncEnd - tmp_mode->HSyncStart;
>-                    info->VBlank     = tmp_mode->VTotal - tmp_mode->VDisplay;
>-                    info->VOverPlus  = tmp_mode->VSyncStart - tmp_mode->VDisplay;
>-                    info->VSyncWidth = tmp_mode->VSyncEnd - tmp_mode->VSyncStart;
>-                    info->DotClock   = tmp_mode->Clock;
>-                    info->Flags = 0;
>-                    break;
>-                }
>-            }
>-            tmp_mode = tmp_mode->next;
>-        }
>-        if ((info->DotClock == 0) && !pRADEONEnt->PortInfo[0].MonInfo) {
>-            xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
>-                       "Panel size is not correctly detected.\n"
>-                       "Please try to use PanelSize option for correct settings.\n");
>-            return FALSE;
>-        }
>-    }
>-
>-    return TRUE;
>-}
>-
>-static void RADEONGetTMDSInfo(ScrnInfoPtr pScrn)
>-{
>-    RADEONInfoPtr  info = RADEONPTR(pScrn);
>-    int i;
>-
>-    for (i=0; i<4; i++) {
>-        info->tmds_pll[i].value = 0;
>-        info->tmds_pll[i].freq = 0;
>-    }
>-
>-    if (RADEONGetTMDSInfoFromBIOS(pScrn)) return;
>-
>-    for (i=0; i<4; i++) {
>-        info->tmds_pll[i].value = default_tmds_pll[info->ChipFamily][i].value;
>-        info->tmds_pll[i].freq = default_tmds_pll[info->ChipFamily][i].freq;
>-    }
>-}
>-
>-static void RADEONGetPanelInfo (ScrnInfoPtr pScrn)
>-{
>-    RADEONInfoPtr info     = RADEONPTR(pScrn);
>-    char* s;
>-
>-    if((s = xf86GetOptValString(info->Options, OPTION_PANEL_SIZE))) {
>-        info->PanelPwrDly = 200;
>-        if (sscanf (s, "%dx%d", &info->PanelXRes, &info->PanelYRes) != 2) {
>-            xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Invalid PanelSize option: %s\n", s);
>-            RADEONGetPanelInfoFromReg(pScrn);
>-        }
>-    } else {
>-
>-        if(info->DisplayType == MT_LCD) {
>-            RADEONGetLVDSInfo(pScrn);
>-        } else if ((info->DisplayType == MT_DFP) || (info->MergeType == MT_DFP)) {
>-            RADEONGetTMDSInfo(pScrn);
>-            if (!pScrn->monitor->DDC)
>-                RADEONGetHardCodedEDIDFromBIOS(pScrn);
>-            else if (!info->IsSecondary)
>-               RADEONUpdatePanelSize(pScrn);
>-        }
>-    }
>-}
>-
> static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
> {
>     RADEONInfoPtr info = RADEONPTR (pScrn);
>@@ -1786,424 +1141,6 @@ static void RADEONGetClockInfo(ScrnInfoP
>     }
> }
> 
>-static BOOL RADEONQueryConnectedMonitors(ScrnInfoPtr pScrn)
>-{
>-    RADEONInfoPtr info       = RADEONPTR(pScrn);
>-    RADEONEntPtr pRADEONEnt  = RADEONEntPriv(pScrn);
>-    unsigned char *RADEONMMIO = info->MMIO;
>-    const char *s;
>-    Bool ignore_edid = FALSE;
>-    int i = 0, second = 0, max_mt;
>-
>-    const char *MonTypeName[7] =
>-    {
>-	"AUTO",
>-	"NONE",
>-	"CRT",
>-	"LVDS",
>-	"TMDS",
>-	"CTV",
>-	"STV"
>-    };
>-
>-    const RADEONMonitorType MonTypeID[7] =
>-    {
>-	MT_UNKNOWN, /* this is just a dummy value for AUTO DETECTION */
>-	MT_NONE,    /* NONE -> NONE */
>-	MT_CRT,     /* CRT -> CRT */
>-	MT_LCD,     /* Laptop LCDs are driven via LVDS port */
>-	MT_DFP,     /* DFPs are driven via TMDS */
>-	MT_CTV,     /* CTV -> CTV */
>-	MT_STV,     /* STV -> STV */
>-    };
>-
>-    const char *TMDSTypeName[3] =
>-    {
>-	"NONE",
>-	"Internal",
>-    "External"
>-    };
>-
>-    const char *DDCTypeName[5] =
>-    {
>-	"NONE",
>-	"MONID",
>-	"DVI_DDC",
>-	"VGA_DDC",
>-    "CRT2_DDC"
>-    };
>-
>-    const char *DACTypeName[3] =
>-    {
>-	"Unknown",
>-	"Primary",
>-	"TVDAC/ExtDAC",
>-    };
>-
>-    const char *ConnectorTypeName[8] =
>-    {
>-	"None",
>-	"Proprietary",
>-	"VGA",
>-	"DVI-I",
>-	"DVI-D",
>-	"CTV",
>-	"STV",
>-	"Unsupported"
>-    };
>-
>-    const char *ConnectorTypeNameATOM[10] =
>-    {
>-	"None",
>-	"VGA",
>-	"DVI-I",
>-	"DVI-D",
>-	"DVI-A",
>-	"STV",
>-	"CTV",
>-	"LVDS",
>-	"Digital",
>-	"Unsupported"
>-    };
>-
>-    max_mt = 5;
>-
>-    if(info->IsSecondary) {
>-	info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType2;
>-	if(info->DisplayType == MT_NONE) return FALSE;
>-	return TRUE;
>-    }
>-
>-
>-    /* We first get the information about all connectors from BIOS.
>-     * This is how the card is phyiscally wired up.
>-     * The information should be correct even on a OEM card.
>-     * If not, we may have problem -- need to use MonitorLayout option.
>-     */
>-    for (i = 0; i < 2; i++) {
>-	pRADEONEnt->PortInfo[i].MonType = MT_UNKNOWN;
>-	pRADEONEnt->PortInfo[i].MonInfo = NULL;
>-	pRADEONEnt->PortInfo[i].DDCType = DDC_NONE_DETECTED;
>-	pRADEONEnt->PortInfo[i].DACType = DAC_UNKNOWN;
>-	pRADEONEnt->PortInfo[i].TMDSType = TMDS_UNKNOWN;
>-	pRADEONEnt->PortInfo[i].ConnectorType = CONNECTOR_NONE;
>-    }
>-
>-    if (!RADEONGetConnectorInfoFromBIOS(pScrn) ||
>-	((pRADEONEnt->PortInfo[0].DDCType == 0) &&
>-	(pRADEONEnt->PortInfo[1].DDCType == 0))) {
>-	/* Below is the most common setting, but may not be true */
>-	pRADEONEnt->PortInfo[0].MonType = MT_UNKNOWN;
>-	pRADEONEnt->PortInfo[0].MonInfo = NULL;
>-	pRADEONEnt->PortInfo[0].DDCType = DDC_DVI;
>-	pRADEONEnt->PortInfo[0].DACType = DAC_TVDAC;
>-	pRADEONEnt->PortInfo[0].TMDSType = TMDS_INT;
>-	pRADEONEnt->PortInfo[0].ConnectorType = CONNECTOR_DVI_D;
>-
>-	pRADEONEnt->PortInfo[1].MonType = MT_UNKNOWN;
>-	pRADEONEnt->PortInfo[1].MonInfo = NULL;
>-	pRADEONEnt->PortInfo[1].DDCType = DDC_VGA;
>-	pRADEONEnt->PortInfo[1].DACType = DAC_PRIMARY;
>-	pRADEONEnt->PortInfo[1].TMDSType = TMDS_EXT;
>-	pRADEONEnt->PortInfo[1].ConnectorType = CONNECTOR_CRT;
>-
>-       /* Some cards have the DDC lines swapped and we have no way to
>-        * detect it yet (Mac cards)
>-        */
>-       if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) {
>-           pRADEONEnt->PortInfo[0].DDCType = DDC_VGA;
>-           pRADEONEnt->PortInfo[1].DDCType = DDC_DVI;
>-        }
>-    }
>-
>-    /* always make TMDS_INT port first*/
>-    if (pRADEONEnt->PortInfo[1].TMDSType == TMDS_INT) {
>-        RADEONConnector connector;
>-        connector = pRADEONEnt->PortInfo[0];
>-        pRADEONEnt->PortInfo[0] = pRADEONEnt->PortInfo[1];
>-        pRADEONEnt->PortInfo[1] = connector;
>-    } else if ((pRADEONEnt->PortInfo[0].TMDSType != TMDS_INT &&
>-                pRADEONEnt->PortInfo[1].TMDSType != TMDS_INT)) {
>-        /* no TMDS_INT port, make primary DAC port first */
>-	/* On my Inspiron 8600 both internal and external ports are
>-	   marked DAC_PRIMARY in BIOS. So be extra careful - only
>-	   swap when the first port is not DAC_PRIMARY */
>-        if ( (pRADEONEnt->PortInfo[1].DACType == DAC_PRIMARY) &&
>-	     (pRADEONEnt->PortInfo[0].DACType != DAC_PRIMARY)) {
>-            RADEONConnector connector;
>-            connector = pRADEONEnt->PortInfo[0];
>-            pRADEONEnt->PortInfo[0] = pRADEONEnt->PortInfo[1];
>-            pRADEONEnt->PortInfo[1] = connector;
>-        }
>-    }
>-
>-    if (info->HasSingleDAC) {
>-        /* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC*/
>-        if (pRADEONEnt->PortInfo[0].ConnectorType == CONNECTOR_CRT) {
>-            pRADEONEnt->PortInfo[0].DACType = DAC_TVDAC;
>-            pRADEONEnt->PortInfo[1].DACType = DAC_PRIMARY;
>-        } else {
>-            pRADEONEnt->PortInfo[1].DACType = DAC_TVDAC;
>-            pRADEONEnt->PortInfo[0].DACType = DAC_PRIMARY;
>-        }
>-    } else if (!info->HasCRTC2) {
>-        pRADEONEnt->PortInfo[0].DACType = DAC_PRIMARY;
>-    }
>-
>-    /* IgnoreEDID option is different from the NoDDCxx options used by DDC module
>-     * When IgnoreEDID is used, monitor detection will still use DDC
>-     * detection, but all EDID data will not be used in mode validation.
>-     * You can use this option when you have a DDC monitor but want specify your own
>-     * monitor timing parameters by using HSync, VRefresh and Modeline,
>-     */
>-    if (xf86GetOptValBool(info->Options, OPTION_IGNORE_EDID, &ignore_edid)) {
>-        if (ignore_edid)
>-            xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
>-                       "IgnoreEDID is specified, EDID data will be ignored\n");
>-    }
>-
>-    /*
>-     * MonitorLayout option takes a string for two monitors connected in following format:
>-     * Option "MonitorLayout" "primary-port-display, secondary-port-display"
>-     * primary and secondary port displays can have one of following:
>-     *    NONE, CRT, LVDS, TMDS
>-     * With this option, driver will bring up monitors as specified,
>-     * not using auto-detection routines to probe monitors.
>-     *
>-     * This option can be used when the false monitor detection occurs.
>-     *
>-     * This option can also be used to disable one connected display.
>-     * For example, if you have a laptop connected to an external CRT
>-     * and you want to disable the internal LCD panel, you can specify
>-     * Option "MonitorLayout" "NONE, CRT"
>-     *
>-     * This option can also used to disable Clone mode. One there is only
>-     * one monitor is specified, clone mode will be turned off automatically
>-     * even you have two monitors connected.
>-     *
>-     * Another usage of this option is you want to config the server
>-     * to start up with a certain monitor arrangement even one monitor
>-     * is not plugged in when server starts.
>-     */
>-    if ((s = xf86GetOptValString(info->Options, OPTION_MONITOR_LAYOUT))) {
>-        char s1[5], s2[5];
>-        i = 0;
>-        /* When using user specified monitor types, we will not do DDC detection
>-         *
>-         */
>-        do {
>-            switch(*s) {
>-            case ',':
>-                s1[i] = '\0';
>-                i = 0;
>-                second = 1;
>-                break;
>-            case ' ':
>-            case '\t':
>-            case '\n':
>-            case '\r':
>-                break;
>-            default:
>-                if (second)
>-                    s2[i] = *s;
>-                else
>-                    s1[i] = *s;
>-                i++;
>-                break;
>-            }
>-            if (i > 4) i = 4;
>-        } while(*s++);
>-        s2[i] = '\0';
>-
>-	for (i = 0; i < max_mt; i++) {
>-	    if (strcmp(s1, MonTypeName[i]) == 0) {
>-		pRADEONEnt->PortInfo[0].MonType = MonTypeID[i];
>-		break;
>-	    }
>-	}
>-	for (i = 0; i < max_mt; i++) {
>-	    if (strcmp(s2, MonTypeName[i]) == 0) {
>-		pRADEONEnt->PortInfo[1].MonType = MonTypeID[i];
>-		break;
>-	    }
>-	}
>-
>-	if (i ==  max_mt)
>-	    xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
>-		       "Invalid Monitor type specified for 2nd port \n");
>-
>-	xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
>-		   "MonitorLayout Option: \n\tMonitor1--Type %s, Monitor2--Type %s\n\n", s1, s2);
>-
>-	if (pRADEONEnt->PortInfo[1].MonType == MT_CRT) {
>-	    pRADEONEnt->PortInfo[1].DACType = DAC_PRIMARY;
>-	    pRADEONEnt->PortInfo[1].TMDSType = TMDS_UNKNOWN;
>-	    pRADEONEnt->PortInfo[1].DDCType = DDC_VGA;
>-	    pRADEONEnt->PortInfo[1].ConnectorType = CONNECTOR_CRT;
>-	    pRADEONEnt->PortInfo[0].DACType = DAC_TVDAC;
>-	    pRADEONEnt->PortInfo[0].TMDSType = TMDS_UNKNOWN;
>-	    pRADEONEnt->PortInfo[0].DDCType = DDC_NONE_DETECTED;
>-	    pRADEONEnt->PortInfo[0].ConnectorType = pRADEONEnt->PortInfo[0].MonType+1;
>-	    pRADEONEnt->PortInfo[0].MonInfo = NULL;
>-        }
>-
>-        if (!ignore_edid) {
>-            if ((pRADEONEnt->PortInfo[0].MonType > MT_NONE) &&
>-                (pRADEONEnt->PortInfo[0].MonType < MT_STV))
>-		RADEONDisplayDDCConnected(pScrn, pRADEONEnt->PortInfo[0].DDCType,
>-					  &pRADEONEnt->PortInfo[0]);
>-            if ((pRADEONEnt->PortInfo[1].MonType > MT_NONE) &&
>-                (pRADEONEnt->PortInfo[1].MonType < MT_STV))
>-		RADEONDisplayDDCConnected(pScrn, pRADEONEnt->PortInfo[1].DDCType,
>-					  &pRADEONEnt->PortInfo[1]);
>-        }
>-
>-    }
>-
>-    if(((!info->HasCRTC2) || info->IsDellServer)) {
>-	if (pRADEONEnt->PortInfo[0].MonType == MT_UNKNOWN) {
>-	    if((pRADEONEnt->PortInfo[0].MonType = RADEONDisplayDDCConnected(pScrn, DDC_DVI, &pRADEONEnt->PortInfo[0])));
>-	    else if((pRADEONEnt->PortInfo[0].MonType = RADEONDisplayDDCConnected(pScrn, DDC_VGA, &pRADEONEnt->PortInfo[0])));
>-	    else if((pRADEONEnt->PortInfo[0].MonType = RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->PortInfo[0])));
>-	    else
>-		pRADEONEnt->PortInfo[0].MonType = MT_CRT;
>-	}
>-
>-	if (!ignore_edid) {
>-	    if (pRADEONEnt->PortInfo[0].MonInfo) {
>-		xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Monitor1 EDID data ---------------------------\n");
>-		xf86PrintEDID(pRADEONEnt->PortInfo[0].MonInfo );
>-		xf86DrvMsg(pScrn->scrnIndex, X_INFO, "End of Monitor1 EDID data --------------------\n");
>-	    }
>-	}
>-
>-	pRADEONEnt->MonType1 = pRADEONEnt->PortInfo[0].MonType;
>-	pRADEONEnt->MonInfo1 = pRADEONEnt->PortInfo[0].MonInfo;
>-	pRADEONEnt->MonType2 = MT_NONE;
>-	pRADEONEnt->MonInfo2 = NULL;
>-	info->MergeType = MT_NONE;
>-	info->DisplayType = pRADEONEnt->MonType1;
>-
>-	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>-		   "Primary:\n Monitor   -- %s\n Connector -- %s\n DAC Type  -- %s\n TMDS Type -- %s\n DDC Type  -- %s\n",
>-		   MonTypeName[pRADEONEnt->PortInfo[0].MonType+1],
>-		   info->IsAtomBios ?
>-		   ConnectorTypeNameATOM[pRADEONEnt->PortInfo[0].ConnectorType]:
>-		   ConnectorTypeName[pRADEONEnt->PortInfo[0].ConnectorType],
>-		   DACTypeName[pRADEONEnt->PortInfo[0].DACType+1],
>-		   TMDSTypeName[pRADEONEnt->PortInfo[0].TMDSType+1],
>-		   DDCTypeName[pRADEONEnt->PortInfo[0].DDCType]);
>-
>-	return TRUE;
>-    }
>-
>-    if (pRADEONEnt->PortInfo[0].MonType == MT_UNKNOWN || pRADEONEnt->PortInfo[1].MonType == MT_UNKNOWN) {
>-
>-	/* Primary Head (DVI or Laptop Int. panel)*/
>-	/* A ddc capable display connected on DVI port */
>-	if (pRADEONEnt->PortInfo[0].MonType == MT_UNKNOWN) {
>-	    if((pRADEONEnt->PortInfo[0].MonType = RADEONDisplayDDCConnected(pScrn, pRADEONEnt->PortInfo[0].DDCType, &pRADEONEnt->PortInfo[0])));
>-	    else if (info->IsMobility &&
>-		     (INREG(RADEON_BIOS_4_SCRATCH) & 4)) {
>-		/* non-DDC laptop panel connected on primary */
>-		pRADEONEnt->PortInfo[0].MonType = MT_LCD;
>-	    } else {
>-		/* CRT on DVI, TODO: not reliable, make it always return false for now*/
>-		pRADEONEnt->PortInfo[0].MonType = RADEONCrtIsPhysicallyConnected(pScrn, !(pRADEONEnt->PortInfo[0].DACType));
>-	    }
>-	}
>-
>-	/* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/
>-	if (pRADEONEnt->PortInfo[1].MonType == MT_UNKNOWN) {
>-	    if((pRADEONEnt->PortInfo[1].MonType =
>-                RADEONDisplayDDCConnected(pScrn, pRADEONEnt->PortInfo[1].DDCType, &pRADEONEnt->PortInfo[1])));
>-            else if (info->IsMobility &&
>-                     (INREG(RADEON_FP2_GEN_CNTL) & RADEON_FP2_ON)) {
>-                /* non-DDC TMDS panel connected through DVO */
>-                pRADEONEnt->PortInfo[1].MonType = MT_DFP;
>-            } else
>-                pRADEONEnt->PortInfo[1].MonType = RADEONCrtIsPhysicallyConnected(pScrn, !(pRADEONEnt->PortInfo[1].DACType));
>-        }
>-    }
>-
>-    if(ignore_edid) {
>-        pRADEONEnt->PortInfo[0].MonInfo = NULL;
>-        pRADEONEnt->PortInfo[1].MonInfo = NULL;
>-    } else {
>-        if (pRADEONEnt->PortInfo[0].MonInfo) {
>-            xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on port 1 ----------------------\n");
>-            xf86PrintEDID(pRADEONEnt->PortInfo[0].MonInfo );
>-        }
>-
>-        if (pRADEONEnt->PortInfo[1].MonInfo) {
>-            xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on port 2-----------------------\n");
>-            xf86PrintEDID(pRADEONEnt->PortInfo[1].MonInfo );
>-        }
>-    }
>-
>-    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "\n");
>-
>-    pRADEONEnt->MonType1 = pRADEONEnt->PortInfo[0].MonType;
>-    pRADEONEnt->MonInfo1 = pRADEONEnt->PortInfo[0].MonInfo;
>-    pRADEONEnt->MonType2 = pRADEONEnt->PortInfo[1].MonType;
>-    pRADEONEnt->MonInfo2 = pRADEONEnt->PortInfo[1].MonInfo;
>-    if (pRADEONEnt->PortInfo[0].MonType == MT_NONE) {
>-	if (pRADEONEnt->PortInfo[1].MonType == MT_NONE) {
>-	    pRADEONEnt->MonType1 = MT_CRT;
>-	    pRADEONEnt->MonInfo1 = NULL;
>-	} else {
>-	    RADEONConnector tmp;
>-	    pRADEONEnt->MonType1 = pRADEONEnt->PortInfo[1].MonType;
>-	    pRADEONEnt->MonInfo1 = pRADEONEnt->PortInfo[1].MonInfo;
>-	    tmp = pRADEONEnt->PortInfo[0];
>-	    pRADEONEnt->PortInfo[0] = pRADEONEnt->PortInfo[1];
>-	    pRADEONEnt->PortInfo[1] = tmp;
>-	}
>-	pRADEONEnt->MonType2 = MT_NONE;
>-	pRADEONEnt->MonInfo2 = NULL;
>-    }
>-
>-    info->DisplayType = pRADEONEnt->MonType1;
>-    pRADEONEnt->ReversedDAC = FALSE;
>-    info->OverlayOnCRTC2 = FALSE;
>-    info->MergeType = MT_NONE;
>-    if (pRADEONEnt->MonType2 != MT_NONE) {
>-	if(!pRADEONEnt->HasSecondary) {
>-	    info->MergeType = pRADEONEnt->MonType2;
>-	}
>-
>-	if (pRADEONEnt->PortInfo[1].DACType == DAC_TVDAC) {
>-	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Reversed DAC decteced\n");
>-	    pRADEONEnt->ReversedDAC = TRUE;
>-	}
>-    } else {
>-	pRADEONEnt->HasSecondary = FALSE;
>-    }
>-
>-    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>-	       "Primary:\n Monitor   -- %s\n Connector -- %s\n DAC Type  -- %s\n TMDS Type -- %s\n DDC Type  -- %s\n",
>-	       MonTypeName[pRADEONEnt->PortInfo[0].MonType+1],
>-	       info->IsAtomBios ?
>-	       ConnectorTypeNameATOM[pRADEONEnt->PortInfo[0].ConnectorType]:
>-	       ConnectorTypeName[pRADEONEnt->PortInfo[0].ConnectorType],
>-	       DACTypeName[pRADEONEnt->PortInfo[0].DACType+1],
>-	       TMDSTypeName[pRADEONEnt->PortInfo[0].TMDSType+1],
>-	       DDCTypeName[pRADEONEnt->PortInfo[0].DDCType]);
>-
>-    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>-	       "Secondary:\n Monitor   -- %s\n Connector -- %s\n DAC Type  -- %s\n TMDS Type -- %s\n DDC Type  -- %s\n",
>-	       MonTypeName[pRADEONEnt->PortInfo[1].MonType+1],
>-	       info->IsAtomBios ?
>-	       ConnectorTypeNameATOM[pRADEONEnt->PortInfo[1].ConnectorType]:
>-	       ConnectorTypeName[pRADEONEnt->PortInfo[1].ConnectorType],
>-	       DACTypeName[pRADEONEnt->PortInfo[1].DACType+1],
>-	       TMDSTypeName[pRADEONEnt->PortInfo[1].TMDSType+1],
>-	       DDCTypeName[pRADEONEnt->PortInfo[1].DDCType]);
>-
>-    return TRUE;
>-}
>-
>-
> /* This is called by RADEONPreInit to set up the default visual */
> static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn)
> {
>@@ -2802,7 +1739,7 @@ #endif
>     case PCI_CHIP_RS482_5974:
> 	info->ChipFamily = CHIP_FAMILY_RS400;
> 	info->IsIGP = TRUE;
>-	/*info->HasSingleDAC = TRUE;*/ /* ??? */
>+	info->HasSingleDAC = TRUE; /* ??? */
>         break;
> 
>     case PCI_CHIP_RV410_564A:
>@@ -3026,53 +1963,6 @@ #endif
>     return TRUE;
> }
> 
>-static void RADEONI2CGetBits(I2CBusPtr b, int *Clock, int *data)
>-{
>-    ScrnInfoPtr    pScrn      = xf86Screens[b->scrnIndex];
>-    RADEONInfoPtr  info       = RADEONPTR(pScrn);
>-    unsigned long  val;
>-    unsigned char *RADEONMMIO = info->MMIO;
>-
>-    /* Get the result */
>-    val = INREG(info->DDCReg);
>-
>-    *Clock = (val & RADEON_GPIO_Y_1) != 0;
>-    *data  = (val & RADEON_GPIO_Y_0) != 0;
>-}
>-
>-static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data)
>-{
>-    ScrnInfoPtr    pScrn      = xf86Screens[b->scrnIndex];
>-    RADEONInfoPtr  info       = RADEONPTR(pScrn);
>-    unsigned long  val;
>-    unsigned char *RADEONMMIO = info->MMIO;
>-
>-    val = INREG(info->DDCReg) & (CARD32)~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1);
>-    val |= (Clock ? 0:RADEON_GPIO_EN_1);
>-    val |= (data ? 0:RADEON_GPIO_EN_0);
>-    OUTREG(info->DDCReg, val);
>-
>-    /* read back to improve reliability on some cards. */
>-    val = INREG(info->DDCReg);
>-}
>-
>-static Bool RADEONI2cInit(ScrnInfoPtr pScrn)
>-{
>-    RADEONInfoPtr  info = RADEONPTR(pScrn);
>-
>-    info->pI2CBus = xf86CreateI2CBusRec();
>-    if (!info->pI2CBus) return FALSE;
>-
>-    info->pI2CBus->BusName    = "DDC";
>-    info->pI2CBus->scrnIndex  = pScrn->scrnIndex;
>-    info->pI2CBus->I2CPutBits = RADEONI2CPutBits;
>-    info->pI2CBus->I2CGetBits = RADEONI2CGetBits;
>-    info->pI2CBus->AcknTimeout = 5;
>-
>-    if (!xf86I2CBusInit(info->pI2CBus)) return FALSE;
>-    return TRUE;
>-}
>-
> static void RADEONPreInitDDC(ScrnInfoPtr pScrn)
> {
>     RADEONInfoPtr  info = RADEONPTR(pScrn);
>@@ -3098,104 +1988,6 @@ static void RADEONPreInitDDC(ScrnInfoPtr
>     }
> }
> 
>-
>-/* BIOS may not have right panel size, we search through all supported
>- * DDC modes looking for the maximum panel size.
>- */
>-static void RADEONUpdatePanelSize(ScrnInfoPtr pScrn)
>-{
>-    int             j;
>-    RADEONInfoPtr   info = RADEONPTR (pScrn);
>-    xf86MonPtr      ddc  = pScrn->monitor->DDC;
>-    DisplayModePtr  p;
>-
>-    if ((info->UseBiosDividers && info->DotClock != 0) || (ddc == NULL))
>-       return;
>-
>-    /* Go thru detailed timing table first */
>-    for (j = 0; j < 4; j++) {
>-	if (ddc->det_mon[j].type == 0) {
>-	    struct detailed_timings *d_timings =
>-		&ddc->det_mon[j].section.d_timings;
>-           int match = 0;
>-
>-           /* If we didn't get a panel clock or guessed one, try to match the
>-            * mode with the panel size. We do that because we _need_ a panel
>-            * clock, or ValidateFPModes will fail, even when UseBiosDividers
>-            * is set.
>-            */
>-           if (info->DotClock == 0 &&
>-               info->PanelXRes == d_timings->h_active &&
>-               info->PanelYRes == d_timings->v_active)
>-               match = 1;
>-
>-           /* If we don't have a BIOS provided panel data with fixed dividers,
>-            * check for a larger panel size
>-            */
>-	    if (info->PanelXRes < d_timings->h_active &&
>-               info->PanelYRes < d_timings->v_active &&
>-               !info->UseBiosDividers)
>-               match = 1;
>-
>-             if (match) {
>-		info->PanelXRes  = d_timings->h_active;
>-		info->PanelYRes  = d_timings->v_active;
>-		info->DotClock   = d_timings->clock / 1000;
>-		info->HOverPlus  = d_timings->h_sync_off;
>-		info->HSyncWidth = d_timings->h_sync_width;
>-		info->HBlank     = d_timings->h_blanking;
>-		info->VOverPlus  = d_timings->v_sync_off;
>-		info->VSyncWidth = d_timings->v_sync_width;
>-		info->VBlank     = d_timings->v_blanking;
>-                info->Flags      = (d_timings->interlaced ? V_INTERLACE : 0);
>-                if (d_timings->sync == 3) {
>-                   switch (d_timings->misc) {
>-                   case 0: info->Flags |= V_NHSYNC | V_NVSYNC; break;
>-                   case 1: info->Flags |= V_PHSYNC | V_NVSYNC; break;
>-                   case 2: info->Flags |= V_NHSYNC | V_PVSYNC; break;
>-                   case 3: info->Flags |= V_PHSYNC | V_PVSYNC; break;
>-                   }
>-                }
>-                xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC detailed: %dx%d\n",
>-                           info->PanelXRes, info->PanelYRes);
>-	    }
>-	}
>-    }
>-
>-    if (info->UseBiosDividers && info->DotClock != 0)
>-       return;
>-
>-    /* Search thru standard VESA modes from EDID */
>-    for (j = 0; j < 8; j++) {
>-	if ((info->PanelXRes < ddc->timings2[j].hsize) &&
>-	    (info->PanelYRes < ddc->timings2[j].vsize)) {
>-	    for (p = pScrn->monitor->Modes; p && p->next; p = p->next->next) {
>-		if ((ddc->timings2[j].hsize == p->HDisplay) &&
>-		    (ddc->timings2[j].vsize == p->VDisplay)) {
>-		    float  refresh =
>-			(float)p->Clock * 1000.0 / p->HTotal / p->VTotal;
>-
>-		    if (abs((float)ddc->timings2[j].refresh - refresh) < 1.0) {
>-			/* Is this good enough? */
>-			info->PanelXRes  = ddc->timings2[j].hsize;
>-			info->PanelYRes  = ddc->timings2[j].vsize;
>-			info->HBlank     = p->HTotal - p->HDisplay;
>-			info->HOverPlus  = p->HSyncStart - p->HDisplay;
>-			info->HSyncWidth = p->HSyncEnd - p->HSyncStart;
>-			info->VBlank     = p->VTotal - p->VDisplay;
>-			info->VOverPlus  = p->VSyncStart - p->VDisplay;
>-			info->VSyncWidth = p->VSyncEnd - p->VSyncStart;
>-			info->DotClock   = p->Clock;
>-                        info->Flags      = p->Flags;
>-                        xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC VESA/EDID: %dx%d\n",
>-                                   info->PanelXRes, info->PanelYRes);
>-		    }
>-		}
>-	    }
>-	}
>-    }
>-}
>-
> /* This function will sort all modes according to their resolution.
>  * Highest resolution first.
>  */
>@@ -3742,167 +2534,6 @@ static Bool RADEONPreInitGamma(ScrnInfoP
>     return TRUE;
> }
> 
>-static void RADEONSetSyncRangeFromEdid(ScrnInfoPtr pScrn, int flag)
>-{
>-    MonPtr monitor = pScrn->monitor;
>-    xf86MonPtr DDC = (xf86MonPtr)(pScrn->monitor->DDC);
>-    int i, j;
>-    float hmin = 1e6, hmax = 0.0, vmin = 1e6, vmax = 0.0;
>-    float h, v;
>-    struct std_timings *t;
>-    struct detailed_timings *dt;
>-    struct monitor_ranges *mon_range = NULL;
>-    int numTimings = 0;
>-    range hsync[MAX_HSYNC];
>-    range vrefresh[MAX_VREFRESH];
>-
>-    numTimings = 0;
>-
>-    if (flag) { /* Hsync */
>-	for (i = 0; i < DET_TIMINGS; i++) {
>-	    switch (DDC->det_mon[i].type) {
>-	    case DS_RANGES:
>-		mon_range = &DDC->det_mon[i].section.ranges;
>-		hsync[numTimings].lo = mon_range->min_h;
>-		hsync[numTimings].hi = mon_range->max_h;
>-		numTimings++;
>-		break;
>-
>-	    case DS_STD_TIMINGS:
>-		t = DDC->det_mon[i].section.std_t;
>-		for (j = 0; j < 5; j++) {
>-		    if (t[j].hsize > 256) { /* sanity check */
>-			h = t[j].refresh * 1.07 * t[j].vsize / 1000.0;
>-			if (h < hmin)
>-			    hmin = h;
>-			if (h > hmax)
>-			    hmax = h;
>-		    }
>-		}
>-		break;
>-
>-	    case DT:
>-		dt = &DDC->det_mon[i].section.d_timings;
>-		if (dt->clock > 15000000) { /* sanity check */
>-		    h = (float)dt->clock / (dt->h_active + dt->h_blanking);
>-		    h /= 1000.0;
>-		    if (h < hmin)
>-			hmin = h;
>-		    if (h > hmax)
>-			hmax = h;
>-		}
>-		break;
>-	    }
>-
>-	    if (numTimings > MAX_HSYNC)
>-		break;
>-	}
>-
>-	if (numTimings == 0) {
>-	    t = DDC->timings2;
>-	    for (i = 0; i < STD_TIMINGS; i++) {
>-		if (t[i].hsize > 256) { /* sanity check */
>-		    h = t[i].refresh * 1.07 * t[i].vsize / 1000.0;
>-		    if (h < hmin)
>-			hmin = h;
>-		    if (h > hmax)
>-			hmax = h;
>-		}
>-	    }
>-
>-	    if (hmax > 0.0) {
>-		hsync[numTimings].lo = hmin;
>-		hsync[numTimings].hi = hmax;
>-		numTimings++;
>-	    }
>-	}
>-
>-	if (numTimings > 0) {
>-	    monitor->nHsync = numTimings;
>-	    for (i = 0; i < numTimings; i++) {
>-	    	monitor->hsync[i].lo = hsync[i].lo;
>-	    	monitor->hsync[i].hi = hsync[i].hi;
>-	    }
>-	} else {
>-	    pScrn->monitor->hsync[0].lo = 28;
>-            pScrn->monitor->hsync[0].hi = 60;
>-            monitor->nHsync = 1;
>-	}
>-
>-    } else {  /* Vrefresh */
>-	for (i = 0; i < DET_TIMINGS; i++) {
>-	    switch (DDC->det_mon[i].type) {
>-	    case DS_RANGES:
>-		mon_range = &DDC->det_mon[i].section.ranges;
>-		vrefresh[numTimings].lo = mon_range->min_v;
>-		vrefresh[numTimings].hi = mon_range->max_v;
>-		numTimings++;
>-		break;
>-
>-	    case DS_STD_TIMINGS:
>-		t = DDC->det_mon[i].section.std_t;
>-		for (j = 0; j < 5; j++) {
>-		    if (t[j].hsize > 256) { /* sanity check */
>-			if (t[j].refresh < vmin)
>-			    vmin = t[i].refresh;
>-			if (t[j].refresh > vmax)
>-			    vmax = t[i].refresh;
>-		    }
>-		}
>-		break;
>-
>-	    case DT:
>-		dt = &DDC->det_mon[i].section.d_timings;
>-		if (dt->clock > 15000000) { /* sanity check */
>-		    h = (float)dt->clock / (dt->h_active + dt->h_blanking);
>-		    v = h / (dt->v_active + dt->v_blanking);
>-		    if (dt->interlaced) 
>-			v /= 2.0;
>-
>-		    if (v < vmin)
>-			vmin = v;
>-		    if (v > vmax)
>-			vmax = v;
>-		}
>-		break;
>-	    }
>-
>-	    if (numTimings > MAX_HSYNC)
>-		break;
>-	}
>-
>-	if (numTimings == 0) {
>-	    t = DDC->timings2;
>-	    for (i = 0; i < STD_TIMINGS; i++) {
>-		if (t[i].hsize > 256) { /* sanity check */
>-		    if (t[i].refresh < vmin)
>-			vmin = t[i].refresh;
>-		    if (t[i].refresh > vmax)
>-			vmax = t[i].refresh;
>-		}
>-	    }
>-
>-	    if (vmax > 0.0) {
>-		vrefresh[numTimings].lo = vmin;
>-		vrefresh[numTimings].hi = vmax;
>-		numTimings++;
>-	    }
>-	}
>-
>-	if (numTimings > 0) {
>-	    monitor->nVrefresh = numTimings;
>-	    for (i = 0; i < numTimings; i++) {
>-		monitor->vrefresh[i].lo = vrefresh[i].lo;
>-		monitor->vrefresh[i].hi = vrefresh[i].hi;
>-	    }
>-	 } else {
>-	    pScrn->monitor->vrefresh[0].lo = 43;
>-            pScrn->monitor->vrefresh[0].hi = 72;
>-            monitor->nVrefresh = 1;
>-	}
>-    }
>-}
>-
> static int RADEONValidateMergeModes(ScrnInfoPtr pScrn1)
> {
>     RADEONInfoPtr   info             = RADEONPTR(pScrn1);
>@@ -4118,7 +2749,7 @@ static Bool RADEONPreInitModes(ScrnInfoP
> 	xf86ReturnOptValBool(info->Options, OPTION_DDC_MODE, FALSE);
> 
>     /* don't use RMX if we have a dual-tmds panels */
>-   if (pRADEONEnt->MonType2 == MT_DFP)
>+   if (pRADEONEnt->Controller[1].pPort->MonType == MT_DFP)
> 	info->ddc_mode = TRUE;
>    /* don't use RMX if we are Dell Server */  
>    if (info->IsDellServer)
>@@ -4129,17 +2760,12 @@ static Bool RADEONPreInitModes(ScrnInfoP
> 	       "Validating modes on %s head ---------\n",
> 	       info->IsSecondary ? "Secondary" : "Primary");
> 
>-    if (info->IsSecondary)
>-        pScrn->monitor->DDC = pRADEONEnt->MonInfo2;
>-    else
>-        pScrn->monitor->DDC = pRADEONEnt->MonInfo1;
>-
>     if (!pScrn->monitor->DDC && info->ddc_mode) {
> 	info->ddc_mode = FALSE;
> 	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
> 		   "No DDC data available, DDCMode option is dismissed\n");
>     }
>-
>+#if 0
>     if ((info->DisplayType == MT_DFP) ||
> 	(info->DisplayType == MT_LCD)) {
> 	if ((s = xf86GetOptValString(info->Options, OPTION_PANEL_SIZE))) {
>@@ -4193,6 +2819,7 @@ static Bool RADEONPreInitModes(ScrnInfoP
>         } else
>             RADEONGetPanelInfo(pScrn);
>     }
>+#endif
> 
>     if (pScrn->monitor->DDC) {
>         /* If we still don't know sync range yet, let's try EDID.
>@@ -4364,7 +2991,8 @@ static Bool RADEONPreInitModes(ScrnInfoP
> 
>     /* Sort the modes, retain the first */
>     if (pScrn->modes && (start = pScrn->modes->next)) {
>-       for (mp = start; mp->next != pScrn->modes; mp = mp->next) {
>+       /* Copy modelist into a new sorted modelist */
>+       for (mp = start; mp != pScrn->modes; mp = mp->next) {
>            DisplayModePtr 	new = NULL;
> 
>            new = xnfcalloc(1, sizeof (DisplayModeRec));
>@@ -4374,14 +3002,19 @@ static Bool RADEONPreInitModes(ScrnInfoP
>        }
> 
>        if (last && first) {
>+           /* Clean up the old modelist */
>+           start->prev = pScrn->modes->prev;
>+           if (start->prev)
>+               start->prev->next = start;
>+           while (start) 
>+               xf86DeleteMode(&start, start);
>+
>+           /* Switch to the new sorted modelist */
>            pScrn->modes->next = first;
>            pScrn->modes->prev = last;
>            first->prev = pScrn->modes;
>-           /* Make the list circular */
>            last->next = pScrn->modes;
> 
>-           for (mp = start; mp->next != pScrn->modes; mp = mp->next) 
>-	       xf86DeleteMode(&start, mp);
>        }
>     }
> 
>@@ -4946,7 +3579,20 @@ static Bool RADEONPreInitXv(ScrnInfoPtr 
>     return TRUE;
> }
> 
>-static xf86MonPtr
>+static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn, xf86Int10InfoPtr  pInt10)
>+{
>+    RADEONGetBIOSInfo(pScrn, pInt10);
>+
>+    RADEONMapControllers(pScrn);
>+
>+    RADEONGetClockInfo(pScrn);
>+    RADEONGetPanelInfo(pScrn);
>+    RADEONGetTVDacAdjInfo(pScrn);
>+
>+    return TRUE;
>+}
>+
>+xf86MonPtr
> RADEONProbeDDC(ScrnInfoPtr pScrn, int indx)
> {
>     vbeInfoPtr  pVbe;
>@@ -5044,8 +3690,6 @@ #endif
> 	    xf86SetPrimInitDone(info->pEnt->index);
> 
> 	    pRADEONEnt->pPrimaryScrn        = pScrn;
>-	    pRADEONEnt->RestorePrimary      = FALSE;
>-	    pRADEONEnt->IsSecondaryRestored = FALSE;
> 	}
>     }
> 
>@@ -5272,9 +3916,8 @@ #endif
> 
>     RADEONPreInitDDC(pScrn);
> 
>-    RADEONGetBIOSInfo(pScrn, pInt10);
>-    if (!RADEONQueryConnectedMonitors(pScrn))    goto fail;
>-    RADEONGetClockInfo(pScrn);
>+    if (!RADEONPreInitControllers (pScrn, pInt10))
>+       goto fail;
> 
>     /* collect MergedFB options */
>     /* only parse mergedfb options on the primary head. 
>@@ -6634,6 +5277,12 @@ static void RADEONRestoreCrtcRegisters(S
>     OUTREG(RADEON_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
>     OUTREG(RADEON_CRTC_V_TOTAL_DISP,    restore->crtc_v_total_disp);
>     OUTREG(RADEON_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
>+
>+    OUTREG(RADEON_FP_H_SYNC_STRT_WID,   restore->fp_h_sync_strt_wid);
>+    OUTREG(RADEON_FP_V_SYNC_STRT_WID,   restore->fp_v_sync_strt_wid);
>+    OUTREG(RADEON_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp);
>+    OUTREG(RADEON_FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp);
>+
>     OUTREG(RADEON_CRTC_OFFSET,          restore->crtc_offset);
>     OUTREG(RADEON_CRTC_OFFSET_CNTL,     restore->crtc_offset_cntl);
>     OUTREG(RADEON_CRTC_PITCH,           restore->crtc_pitch);
>@@ -6675,10 +5324,15 @@ static void RADEONRestoreCrtc2Registers(
> 
>     OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
> 
>-    OUTREG(RADEON_TV_DAC_CNTL, 0x00280203);
>+    /*OUTREG(RADEON_TV_DAC_CNTL, 0x00280203);*/
>+    if ((info->ChipFamily != CHIP_FAMILY_RADEON) &&
>+	(info->ChipFamily != CHIP_FAMILY_R200)) 
>+	OUTREG (RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
>+
>     if ((info->ChipFamily == CHIP_FAMILY_R200) ||
> 	IS_R300_VARIANT) {
> 	OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl);
>+	OUTREG(RADEON_DISP_TV_OUT_CNTL, restore->disp_tv_out_cntl);
>     } else {
> 	OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
>     }
>@@ -6687,24 +5341,19 @@ static void RADEONRestoreCrtc2Registers(
>     OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid);
>     OUTREG(RADEON_CRTC2_V_TOTAL_DISP,    restore->crtc2_v_total_disp);
>     OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid);
>+
>+    OUTREG(RADEON_FP_H2_SYNC_STRT_WID,   restore->fp_h2_sync_strt_wid);
>+    OUTREG(RADEON_FP_V2_SYNC_STRT_WID,   restore->fp_v2_sync_strt_wid);
>+    OUTREG(RADEON_FP_CRTC2_H_TOTAL_DISP, restore->fp_crtc2_h_total_disp);
>+    OUTREG(RADEON_FP_CRTC2_V_TOTAL_DISP, restore->fp_crtc2_v_total_disp);
>+
>     OUTREG(RADEON_CRTC2_OFFSET,          restore->crtc2_offset);
>     OUTREG(RADEON_CRTC2_OFFSET_CNTL,     restore->crtc2_offset_cntl);
>     OUTREG(RADEON_CRTC2_PITCH,           restore->crtc2_pitch);
>     OUTREG(RADEON_DISP2_MERGE_CNTL,      restore->disp2_merge_cntl);
> 
>-    if ((info->DisplayType == MT_DFP && info->IsSecondary) || 
>-	info->MergeType == MT_DFP) {	
>-	OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp2_h_sync_strt_wid);
>-	OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp2_v_sync_strt_wid);
>-	OUTREG(RADEON_FP2_GEN_CNTL,        restore->fp2_gen_cntl);
>-    }
>-
>     OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
> 
>-#if 0
>-    /* Hack for restoring text mode -- fixed elsewhere */
>-    usleep(100000);
>-#endif
> }
> 
> /* Write flat panel registers */
>@@ -6714,10 +5363,6 @@ static void RADEONRestoreFPRegisters(Scr
>     unsigned char *RADEONMMIO = info->MMIO;
>     unsigned long  tmp;
> 
>-    OUTREG(RADEON_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp);
>-    OUTREG(RADEON_FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp);
>-    OUTREG(RADEON_FP_H_SYNC_STRT_WID,   restore->fp_h_sync_strt_wid);
>-    OUTREG(RADEON_FP_V_SYNC_STRT_WID,   restore->fp_v_sync_strt_wid);
>     OUTREG(RADEON_TMDS_PLL_CNTL,        restore->tmds_pll_cntl);
>     OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl);
>     OUTREG(RADEON_FP_HORZ_STRETCH,      restore->fp_horz_stretch);
>@@ -6737,40 +5382,6 @@ static void RADEONRestoreFPRegisters(Scr
> 	OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch);
>     }
> 
>-    if (info->DisplayType != MT_DFP) {
>-	unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
>-
>-	if (info->IsMobility || info->IsIGP) {
>-	    /* Asic bug, when turning off LVDS_ON, we have to make sure
>-	       RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
>-	    */
>-	    if (!(restore->lvds_gen_cntl & RADEON_LVDS_ON)) {
>-		OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
>-	    }
>-	}
>-
>-	tmp = INREG(RADEON_LVDS_GEN_CNTL);
>-	if ((tmp & (RADEON_LVDS_ON | RADEON_LVDS_BLON)) ==
>-	    (restore->lvds_gen_cntl & (RADEON_LVDS_ON | RADEON_LVDS_BLON))) {
>-	    OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
>-	} else {
>-	    if (restore->lvds_gen_cntl & (RADEON_LVDS_ON | RADEON_LVDS_BLON)) {
>-		usleep(RADEONPTR(pScrn)->PanelPwrDly * 1000);
>-		OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
>-	    } else {
>-		OUTREG(RADEON_LVDS_GEN_CNTL,
>-		       restore->lvds_gen_cntl | RADEON_LVDS_BLON);
>-		usleep(RADEONPTR(pScrn)->PanelPwrDly * 1000);
>-		OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
>-	    }
>-	}
>-
>-	if (info->IsMobility || info->IsIGP) {
>-	    if (!(restore->lvds_gen_cntl & RADEON_LVDS_ON)) {
>-		OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
>-	    }
>-	}
>-    }
> }
> 
> static void RADEONPLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn)
>@@ -6915,6 +5526,7 @@ static void RADEONRestorePLLRegisters(Sc
> 
>     usleep(50000); /* Let the clock to lock */
> 
>+    /*OUTPLLP (pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_cntl, 0);*/
>     OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL,
> 	    RADEON_VCLK_SRC_SEL_PPLLCLK,
> 	    ~(RADEON_VCLK_SRC_SEL_MASK));
>@@ -6974,6 +5586,7 @@ static void RADEONRestorePLL2Registers(S
> 
>     usleep(5000); /* Let the clock to lock */
> 
>+    /*OUTPLLP (pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl, 0);*/
>     OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL,
> 	    RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
> 	    ~(RADEON_PIX2CLK_SRC_SEL_MASK));
>@@ -7194,9 +5807,10 @@ static void RADEONRestoreMode(ScrnInfoPt
> {
>     RADEONInfoPtr      info = RADEONPTR(pScrn);
>     RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
>-    static RADEONSaveRec  restore0;
>+    RADEONController* pCRTC1 = &pRADEONEnt->Controller[0];
>+    RADEONController* pCRTC2 = &pRADEONEnt->Controller[1];
> 
>-    RADEONTRACE(("RADEONRestoreMode()\n"));
>+    RADEONTRACE(("RADEONRestoreMode(%p)\n", restore));
> 
>     /* For Non-dual head card, we don't have private field in the Entity */
>     if (!info->HasCRTC2) {
>@@ -7208,8 +5822,6 @@ static void RADEONRestoreMode(ScrnInfoPt
> 	return;
>     }
> 
>-    RADEONTRACE(("RADEONRestoreMode(%p)\n", restore));
>-
>     /* When changing mode with Dual-head card, care must be taken for
>      * the special order in setting registers. CRTC2 has to be set
>      * before changing CRTC_EXT register.  In the dual-head setup, X
>@@ -7222,43 +5834,44 @@ static void RADEONRestoreMode(ScrnInfoPt
>      * We always restore MemMap first, the saverec should be up to date
>      * in all cases
>      */
>-    if (info->IsSecondary) {
>-	RADEONRestoreMemMapRegisters(pScrn, restore);
>-	RADEONRestoreCommonRegisters(pScrn, restore);
>-	RADEONRestoreCrtc2Registers(pScrn, restore);
>-	RADEONRestorePLL2Registers(pScrn, restore);
>-
>-	if (info->IsSwitching)
>-	    return;
>-
>-	pRADEONEnt->IsSecondaryRestored = TRUE;
>-
>-	if (pRADEONEnt->RestorePrimary) {
>-	    pRADEONEnt->RestorePrimary = FALSE;
>+    if (info->IsSwitching) {
>+	if (info->IsSecondary) {
>+	    RADEONRestoreMemMapRegisters(pScrn, restore);
>+	    RADEONRestoreCommonRegisters(pScrn, restore);
>+	    RADEONRestoreCrtc2Registers(pScrn, restore);
>+	    RADEONRestorePLL2Registers(pScrn, restore);
>+	    RADEONRestoreFPRegisters(pScrn, restore);
>+	    RADEONEnableDisplay(pScrn, pCRTC2, TRUE);
>+	} else {
>+	    RADEONRestoreMemMapRegisters(pScrn, restore);
>+	    RADEONRestoreCommonRegisters(pScrn, restore);
>+	    if (info->MergedFB) {
>+		RADEONRestoreCrtc2Registers(pScrn, restore);
>+		RADEONRestorePLL2Registers(pScrn, restore);
>+	    }
> 
>-	    RADEONRestoreCrtcRegisters(pScrn, &restore0);
>-	    RADEONRestoreFPRegisters(pScrn, &restore0);
>-	    RADEONRestorePLLRegisters(pScrn, &restore0);
>-	    pRADEONEnt->IsSecondaryRestored = FALSE;
>+            RADEONRestoreCrtcRegisters(pScrn, restore);
>+            RADEONRestorePLLRegisters(pScrn, restore);
>+	    RADEONRestoreFPRegisters(pScrn, restore);
>+	    RADEONEnableDisplay(pScrn, pCRTC1, TRUE);
>+	    if (info->MergedFB) {
>+	        RADEONEnableDisplay(pScrn, pCRTC2, TRUE);
>+	    }
> 	}
>     } else {
> 	RADEONRestoreMemMapRegisters(pScrn, restore);
> 	RADEONRestoreCommonRegisters(pScrn, restore);
>-	if (info->MergedFB) {
>+	if ((info->MergedFB) || pRADEONEnt->HasSecondary) {
> 	    RADEONRestoreCrtc2Registers(pScrn, restore);
> 	    RADEONRestorePLL2Registers(pScrn, restore);
> 	}
> 
>-	if (!pRADEONEnt->HasSecondary || pRADEONEnt->IsSecondaryRestored ||
>-	    info->IsSwitching) {
>-	    pRADEONEnt->IsSecondaryRestored = FALSE;
>-
>-	    RADEONRestoreCrtcRegisters(pScrn, restore);
>-	    RADEONRestoreFPRegisters(pScrn, restore);
>-	    RADEONRestorePLLRegisters(pScrn, restore);
>-	} else {
>-	    memcpy(&restore0, restore, sizeof(restore0));
>-	    pRADEONEnt->RestorePrimary = TRUE;
>+	RADEONRestoreCrtcRegisters(pScrn, restore);
>+	RADEONRestorePLLRegisters(pScrn, restore);
>+	RADEONRestoreFPRegisters(pScrn, restore);
>+	RADEONEnableDisplay(pScrn, pCRTC1, TRUE);
>+	if ((info->MergedFB) || pRADEONEnt->HasSecondary) {
>+	    RADEONEnableDisplay(pScrn, pCRTC2, TRUE);
> 	}
>     }
> 
>@@ -7337,6 +5950,12 @@ static void RADEONSaveCrtcRegisters(Scrn
>     save->crtc_h_sync_strt_wid = INREG(RADEON_CRTC_H_SYNC_STRT_WID);
>     save->crtc_v_total_disp    = INREG(RADEON_CRTC_V_TOTAL_DISP);
>     save->crtc_v_sync_strt_wid = INREG(RADEON_CRTC_V_SYNC_STRT_WID);
>+
>+    save->fp_h_sync_strt_wid   = INREG(RADEON_FP_H_SYNC_STRT_WID);
>+    save->fp_v_sync_strt_wid   = INREG(RADEON_FP_V_SYNC_STRT_WID);
>+    save->fp_crtc_h_total_disp = INREG(RADEON_FP_CRTC_H_TOTAL_DISP);
>+    save->fp_crtc_v_total_disp = INREG(RADEON_FP_CRTC_V_TOTAL_DISP);
>+
>     save->crtc_offset          = INREG(RADEON_CRTC_OFFSET);
>     save->crtc_offset_cntl     = INREG(RADEON_CRTC_OFFSET_CNTL);
>     save->crtc_pitch           = INREG(RADEON_CRTC_PITCH);
>@@ -7357,12 +5976,9 @@ static void RADEONSaveFPRegisters(ScrnIn
>     RADEONInfoPtr  info       = RADEONPTR(pScrn);
>     unsigned char *RADEONMMIO = info->MMIO;
> 
>-    save->fp_crtc_h_total_disp = INREG(RADEON_FP_CRTC_H_TOTAL_DISP);
>-    save->fp_crtc_v_total_disp = INREG(RADEON_FP_CRTC_V_TOTAL_DISP);
>     save->fp_gen_cntl          = INREG(RADEON_FP_GEN_CNTL);
>-    save->fp_h_sync_strt_wid   = INREG(RADEON_FP_H_SYNC_STRT_WID);
>+    save->fp2_gen_cntl          = INREG (RADEON_FP2_GEN_CNTL);
>     save->fp_horz_stretch      = INREG(RADEON_FP_HORZ_STRETCH);
>-    save->fp_v_sync_strt_wid   = INREG(RADEON_FP_V_SYNC_STRT_WID);
>     save->fp_vert_stretch      = INREG(RADEON_FP_VERT_STRETCH);
>     save->lvds_gen_cntl        = INREG(RADEON_LVDS_GEN_CNTL);
>     save->lvds_pll_cntl        = INREG(RADEON_LVDS_PLL_CNTL);
>@@ -7385,7 +6001,9 @@ static void RADEONSaveCrtc2Registers(Scr
>     unsigned char *RADEONMMIO = info->MMIO;
> 
>     save->dac2_cntl             = INREG(RADEON_DAC_CNTL2);
>+    save->tv_dac_cntl           = INREG(RADEON_TV_DAC_CNTL);
>     save->disp_output_cntl      = INREG(RADEON_DISP_OUTPUT_CNTL);
>+    save->disp_tv_out_cntl      = INREG(RADEON_DISP_TV_OUT_CNTL);
>     save->disp_hw_debug         = INREG (RADEON_DISP_HW_DEBUG);
> 
>     save->crtc2_gen_cntl        = INREG(RADEON_CRTC2_GEN_CNTL);
>@@ -7397,9 +6015,11 @@ static void RADEONSaveCrtc2Registers(Scr
>     save->crtc2_offset_cntl     = INREG(RADEON_CRTC2_OFFSET_CNTL);
>     save->crtc2_pitch           = INREG(RADEON_CRTC2_PITCH);
> 
>-    save->fp2_h_sync_strt_wid   = INREG (RADEON_FP_H2_SYNC_STRT_WID);
>-    save->fp2_v_sync_strt_wid   = INREG (RADEON_FP_V2_SYNC_STRT_WID);
>-    save->fp2_gen_cntl          = INREG (RADEON_FP2_GEN_CNTL);
>+    save->fp_h2_sync_strt_wid   = INREG (RADEON_FP_H2_SYNC_STRT_WID);
>+    save->fp_v2_sync_strt_wid   = INREG (RADEON_FP_V2_SYNC_STRT_WID);
>+    save->fp_crtc2_h_total_disp = INREG(RADEON_FP_CRTC2_H_TOTAL_DISP);
>+    save->fp_crtc2_v_total_disp = INREG(RADEON_FP_CRTC2_V_TOTAL_DISP);
>+
>     save->disp2_merge_cntl      = INREG(RADEON_DISP2_MERGE_CNTL);
> }
> 
>@@ -7409,6 +6029,7 @@ static void RADEONSavePLLRegisters(ScrnI
>     save->ppll_ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV);
>     save->ppll_div_3   = INPLL(pScrn, RADEON_PPLL_DIV_3);
>     save->htotal_cntl  = INPLL(pScrn, RADEON_HTOTAL_CNTL);
>+    save->vclk_cntl    = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
> 
>     RADEONTRACE(("Read: 0x%08x 0x%08x 0x%08lx\n",
> 		 save->ppll_ref_div,
>@@ -7426,6 +6047,7 @@ static void RADEONSavePLL2Registers(Scrn
>     save->p2pll_ref_div = INPLL(pScrn, RADEON_P2PLL_REF_DIV);
>     save->p2pll_div_0   = INPLL(pScrn, RADEON_P2PLL_DIV_0);
>     save->htotal_cntl2  = INPLL(pScrn, RADEON_HTOTAL2_CNTL);
>+    save->pixclks_cntl  = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
> 
>     RADEONTRACE(("Read: 0x%08lx 0x%08lx 0x%08lx\n",
> 		 save->p2pll_ref_div,
>@@ -7463,21 +6085,21 @@ static void RADEONSaveMode(ScrnInfoPtr p
>     RADEONInfoPtr  info = RADEONPTR(pScrn);
> 
>     RADEONTRACE(("RADEONSaveMode(%p)\n", save));
>-    RADEONSaveMemMapRegisters(pScrn, save);
>-    RADEONSaveCommonRegisters(pScrn, save);
>+
>     if (info->IsSecondary) {
>-	RADEONSaveCrtc2Registers(pScrn, save);
>-	RADEONSavePLL2Registers(pScrn, save);
>+        RADEONEntPtr pRADEONEnt   = RADEONEntPriv(pScrn);
>+        RADEONInfoPtr info0 = RADEONPTR(pRADEONEnt->pPrimaryScrn);
>+        memcpy(&info->SavedReg, &info0->SavedReg, sizeof(RADEONSaveRec));
>     } else {
>-	RADEONSavePLLRegisters(pScrn, save);
>-	RADEONSaveCrtcRegisters(pScrn, save);
>-	RADEONSaveFPRegisters(pScrn, save);
>-
>-	if (info->MergedFB) {
>-	    RADEONSaveCrtc2Registers(pScrn, save);
>-	    RADEONSavePLL2Registers(pScrn, save);
>-	}
>-     /* RADEONSavePalette(pScrn, save); */
>+        RADEONSaveMemMapRegisters(pScrn, save);
>+        RADEONSaveCommonRegisters(pScrn, save);
>+        RADEONSavePLLRegisters (pScrn, save);
>+        RADEONSaveCrtcRegisters (pScrn, save);
>+        RADEONSaveFPRegisters (pScrn, save);
>+        RADEONSaveCrtc2Registers (pScrn, save);
>+        RADEONSavePLL2Registers (pScrn, save);
>+	/*RADEONSavePalette(pScrn, save);*/
>+	/*memcpy(&info->ModeReg, &info->SavedReg, sizeof(RADEONSaveRec));*/
>     }
> 
>     RADEONTRACE(("RADEONSaveMode returns %p\n", save));
>@@ -7639,452 +6261,315 @@ static void RADEONInitCommonRegisters(RA
> 	save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN;
> }
> 
>-
>-/* Calculate display buffer watermark to prevent buffer underflow */
>-static void RADEONInitDispBandwidth(ScrnInfoPtr pScrn)
>+/* XXX: fix me */
>+static void RADEONInitTvDacCntl(ScrnInfoPtr pScrn, RADEONSavePtr save)
> {
>     RADEONInfoPtr  info       = RADEONPTR(pScrn);
>-    RADEONEntPtr pRADEONEnt   = RADEONEntPriv(pScrn);
>-    unsigned char *RADEONMMIO = info->MMIO;
>-    RADEONInfoPtr  info2 = NULL;
>-
>-    DisplayModePtr mode1, mode2;
>-
>-    CARD32 temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0;
>-    float mem_tcas;
>-    int k1, c;
>-    CARD32 MemTrcdExtMemCntl[4]     = {1, 2, 3, 4};
>-    CARD32 MemTrpExtMemCntl[4]      = {1, 2, 3, 4};
>-    CARD32 MemTrasExtMemCntl[8]     = {1, 2, 3, 4, 5, 6, 7, 8};
>-
>-    CARD32 MemTrcdMemTimingCntl[8]     = {1, 2, 3, 4, 5, 6, 7, 8};
>-    CARD32 MemTrpMemTimingCntl[8]      = {1, 2, 3, 4, 5, 6, 7, 8};
>-    CARD32 MemTrasMemTimingCntl[16]    = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19};
>-
>-    float MemTcas[8]  = {0, 1, 2, 3, 0, 1.5, 2.5, 0};
>-    float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7};
>-    float MemTrbs[8]  = {1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5};
>-
>-    float mem_bw, peak_disp_bw;
>-    float min_mem_eff = 0.8;
>-    float sclk_eff, sclk_delay;
>-    float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk;
>-    float disp_latency, disp_latency_overhead, disp_drain_rate, disp_drain_rate2;
>-    float pix_clk, pix_clk2; /* in MHz */
>-    int cur_size = 16;       /* in octawords */
>-    int critical_point, critical_point2;
>-    int stop_req, max_stop_req;
>-    float read_return_rate, time_disp1_drop_priority;
>-
>-    /* 
>-     * Set display0/1 priority up on r3/4xx in the memory controller for 
>-     * high res modes if the user specifies HIGH for displaypriority 
>-     * option.
>-     */
>-    if ((info->DispPriority == 2) && IS_R300_VARIANT) {
>-        CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
>-	if (info->MergedFB || pRADEONEnt->HasSecondary) {
>-	    mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */
>-	} else {
>-	    mc_init_misc_lat_timer |= 0x0100; /* display 0 only */
>-	}
>-	OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
>-    }
>-
>-
>-    /* R420 and RV410 family not supported yet */
>-    if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) return; 
>-
>-    if (pRADEONEnt->pSecondaryScrn) {
>-	if (info->IsSecondary) return;
>-	info2 = RADEONPTR(pRADEONEnt->pSecondaryScrn);
>-    }  else if (info->MergedFB) info2 = info;
>-
>-    /*
>-     * Determine if there is enough bandwidth for current display mode
>-     */
>-    mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1);
>-
>-    mode1 = info->CurrentLayout.mode;
>-    if (info->MergedFB) {
>-	mode1 = ((RADEONMergedDisplayModePtr)info->CurrentLayout.mode->Private)->CRT1;
>-	mode2 = ((RADEONMergedDisplayModePtr)info->CurrentLayout.mode->Private)->CRT2;
>-    } else if ((pRADEONEnt->HasSecondary) && info2) {
>-	mode2 = info2->CurrentLayout.mode;
>+    if (info->ChipFamily == CHIP_FAMILY_R420) {
>+	save->tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
>+			       RADEON_TV_DAC_BGADJ_MASK |
>+			       R420_TV_DAC_DACADJ_MASK |
>+			       R420_TV_DAC_RDACPD |
>+			       R420_TV_DAC_GDACPD |
>+			       R420_TV_DAC_GDACPD |
>+			       R420_TV_DAC_TVENABLE);
>     } else {
>-	mode2 = NULL;
>-    }
>-
>-    pix_clk = mode1->Clock/1000.0;
>-    if (mode2)
>-	pix_clk2 = mode2->Clock/1000.0;
>-    else
>-	pix_clk2 = 0;
>-
>-    peak_disp_bw = (pix_clk * info->CurrentLayout.pixel_bytes);
>-    if (info2) 
>-	peak_disp_bw +=	(pix_clk2 * info2->CurrentLayout.pixel_bytes);
>-
>-    if (peak_disp_bw >= mem_bw * min_mem_eff) {
>-	xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 
>-		   "You may not have enough display bandwidth for current mode\n"
>-		   "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
>-    } 
>-
>-    /*  CRTC1
>-        Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
>-    	GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
>-    */
>-    stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16;
>+	save->tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
>+			       RADEON_TV_DAC_BGADJ_MASK |
>+			       RADEON_TV_DAC_DACADJ_MASK |
>+			       RADEON_TV_DAC_RDACPD |
>+			       RADEON_TV_DAC_GDACPD |
>+			       RADEON_TV_DAC_GDACPD);
>+    }
>+    save->tv_dac_cntl = (RADEON_TV_DAC_NBLANK |
>+			 RADEON_TV_DAC_NHOLD |
>+			 RADEON_TV_DAC_STD_PS2 |
>+			 info->tv_dac_adj);
>+}   
> 
>-    /* setup Max GRPH_STOP_REQ default value */
>-    if (IS_RV100_VARIANT)
>-	max_stop_req = 0x5c;
>-    else
>-	max_stop_req  = 0x7c;
>-    if (stop_req > max_stop_req)
>-	stop_req = max_stop_req;
>-      
>-    /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
>-    temp = INREG(RADEON_MEM_TIMING_CNTL);
>-    if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
>-	mem_trcd      = MemTrcdExtMemCntl[(temp & 0x0c) >> 2];
>-	mem_trp       = MemTrpExtMemCntl[ (temp & 0x03) >> 0];
>-	mem_tras      = MemTrasExtMemCntl[(temp & 0x70) >> 4];
>-    } else { /* RV200 and later */
>-	mem_trcd      = MemTrcdMemTimingCntl[(temp & 0x07) >> 0];
>-	mem_trp       = MemTrpMemTimingCntl[ (temp & 0x700) >> 8];
>-	mem_tras      = MemTrasMemTimingCntl[(temp & 0xf000) >> 12];
>-    }
>+static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
>+				  DisplayModePtr mode, BOOL IsPrimary)
>+{
>+    RADEONEntPtr pRADEONEnt   = RADEONEntPriv(pScrn);
>+    RADEONInfoPtr  info       = RADEONPTR(pScrn);
>+    int    xres = mode->HDisplay;
>+    int    yres = mode->VDisplay;
>+    float  Hratio, Vratio;
>+    RADEONMonitorType MonType;
>+    RADEONTmdsType TmdsType;
>     
>-    /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 
>-    temp = INREG(RADEON_MEM_SDRAM_MODE_REG);
>-    data = (temp & (7<<20)) >> 20;
>-    if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
>-	mem_tcas = MemTcas [data];
>+    if (IsPrimary) {
>+	MonType = pRADEONEnt->Controller[0].pPort->MonType;
>+	TmdsType = pRADEONEnt->Controller[0].pPort->TMDSType;
>     } else {
>-	mem_tcas = MemTcas2 [data];
>+	MonType = pRADEONEnt->Controller[1].pPort->MonType;
>+	TmdsType = pRADEONEnt->Controller[1].pPort->TMDSType;
>     }
> 
>-    if (IS_R300_VARIANT) {
>-
>-	/* on the R300, Tcas is included in Trbs.
>-	*/
>-	temp = INREG(RADEON_MEM_CNTL);
>-	data = (R300_MEM_NUM_CHANNELS_MASK & temp);
>-	if (data == 1) {
>-	    if (R300_MEM_USE_CD_CH_ONLY & temp) {
>-		temp  = INREG(R300_MC_IND_INDEX);
>-		temp &= ~R300_MC_IND_ADDR_MASK;
>-		temp |= R300_MC_READ_CNTL_CD_mcind;
>-		OUTREG(R300_MC_IND_INDEX, temp);
>-		temp  = INREG(R300_MC_IND_DATA);
>-		data = (R300_MEM_RBS_POSITION_C_MASK & temp);
>-	    } else {
>-		temp = INREG(R300_MC_READ_CNTL_AB);
>-		data = (R300_MEM_RBS_POSITION_A_MASK & temp);
>-	    }
>+    if (IsPrimary) {
>+	if (info->PanelXRes == 0 || info->PanelYRes == 0) {
>+	    Hratio = 1.0;
>+	    Vratio = 1.0;
> 	} else {
>-	    temp = INREG(R300_MC_READ_CNTL_AB);
>-	    data = (R300_MEM_RBS_POSITION_A_MASK & temp);
>+	    if (xres > info->PanelXRes) xres = info->PanelXRes;
>+	    if (yres > info->PanelYRes) yres = info->PanelYRes;
>+
>+	    Hratio = (float)xres/(float)info->PanelXRes;
>+	    Vratio = (float)yres/(float)info->PanelYRes;
> 	}
> 
>-	mem_trbs = MemTrbs[data];
>-	mem_tcas += mem_trbs;
>-    }
>+	save->fp_vert_stretch &= RADEON_VERT_STRETCH_RESERVED;
>+	save->fp_horz_stretch &= (RADEON_HORZ_FP_LOOP_STRETCH |
>+				  RADEON_HORZ_AUTO_RATIO_INC);
> 
>-    if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
>-	/* DDR64 SCLK_EFF = SCLK for analysis */
>-	sclk_eff = info->sclk;
>-    } else {
>-#ifdef XF86DRI
>-	if (info->directRenderingEnabled)
>-	    sclk_eff = info->sclk - (info->agpMode * 50.0 / 3.0);
>-	else
>-#endif
>-	    sclk_eff = info->sclk;
>-    }
>-
>-    /* Find the memory controller latency for the display client.
>-    */
>-    if (IS_R300_VARIANT) {
>-	/*not enough for R350 ???*/
>-	/*
>-	if (!mode2) sclk_delay = 150;
>-	else {
>-	    if (info->RamWidth == 256) sclk_delay = 87;
>-	    else sclk_delay = 97;
>-	}
>-	*/
>-	sclk_delay = 250;
>-    } else {
>-	if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
>-	    info->IsIGP) {
>-	    if (info->IsDDR) sclk_delay = 41;
>-	    else sclk_delay = 33;
>+	if (Hratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
>+	    save->fp_horz_stretch |= ((xres/8-1)<<16);
> 	} else {
>-	    if (info->RamWidth == 128) sclk_delay = 57;
>-	    else sclk_delay = 41;
>+	    save->fp_horz_stretch |= ((((unsigned long)(Hratio * RADEON_HORZ_STRETCH_RATIO_MAX +
>+							0.5)) & RADEON_HORZ_STRETCH_RATIO_MASK) |
>+				      RADEON_HORZ_STRETCH_BLEND |
>+				      RADEON_HORZ_STRETCH_ENABLE |
>+				      ((info->PanelXRes/8-1)<<16));
> 	}
>-    }
> 
>-    mc_latency_sclk = sclk_delay / sclk_eff;
>-	
>-    if (info->IsDDR) {
>-	if (info->RamWidth == 32) {
>-	    k1 = 40;
>-	    c  = 3;
>+	if (Vratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
>+	    save->fp_vert_stretch |= ((yres-1)<<12);
> 	} else {
>-	    k1 = 20;
>-	    c  = 1;
>+	    save->fp_vert_stretch |= ((((unsigned long)(Vratio * RADEON_VERT_STRETCH_RATIO_MAX +
>+							0.5)) & RADEON_VERT_STRETCH_RATIO_MASK) |
>+				      RADEON_VERT_STRETCH_ENABLE |
>+				      RADEON_VERT_STRETCH_BLEND |
>+				      ((info->PanelYRes-1)<<12));
> 	}
>-    } else {
>-	k1 = 40;
>-	c  = 3;
>-    }
>-    mc_latency_mclk = ((2.0*mem_trcd + mem_tcas*c + 4.0*mem_tras + 4.0*mem_trp + k1) /
>-		       info->mclk) + (4.0 / sclk_eff);
>-
>-    /*
>-      HW cursor time assuming worst case of full size colour cursor.
>-    */
>-    cur_latency_mclk = (mem_trp + MAX(mem_tras, (mem_trcd + 2*(cur_size - (info->IsDDR+1))))) / info->mclk;
>-    cur_latency_sclk = cur_size / sclk_eff;
>+    } 
> 
>-    /*
>-      Find the total latency for the display data.
>-    */
>-    disp_latency_overhead = 8.0 / info->sclk;
>-    mc_latency_mclk = mc_latency_mclk + disp_latency_overhead + cur_latency_mclk;
>-    mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk;
>-    disp_latency = MAX(mc_latency_mclk, mc_latency_sclk);
>+    save->fp_gen_cntl |= (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
>+			  RADEON_FP_CRTC_DONT_SHADOW_HEND );
> 
>-    /*
>-      Find the drain rate of the display buffer.
>-    */
>-    disp_drain_rate = pix_clk / (16.0/info->CurrentLayout.pixel_bytes);
>-    if (info2)
>-	disp_drain_rate2 = pix_clk2 / (16.0/info2->CurrentLayout.pixel_bytes);
>+    if (pScrn->rgbBits == 8) 
>+        save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format, */
>     else
>-	disp_drain_rate2 = 0;
>+        save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT; /* 18 bit format, */
> 
>-    /*
>-      Find the critical point of the display buffer.
>-    */
>-    critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5); 
>-
>-    /* ???? */
>-    /*
>-    temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT;
>-    if (critical_point < temp) critical_point = temp;
>-    */
>-    if (info->DispPriority == 2) {
>-	critical_point = 0;
>-    }
>-
>-    /*
>-      The critical point should never be above max_stop_req-4.  Setting
>-      GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
>-    */
>-    if (max_stop_req - critical_point < 4) critical_point = 0; 
>-
>-    if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) {
>-	/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
>-	critical_point = 0x10;
>-    }
>-
>-    temp = info->SavedReg.grph_buffer_cntl;
>-    temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
>-    temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
>-    temp &= ~(RADEON_GRPH_START_REQ_MASK);
>-    if ((info->ChipFamily == CHIP_FAMILY_R350) &&
>-	(stop_req > 0x15)) {
>-	stop_req -= 0x10;
>+    info->PanelOff = FALSE;
>+    /*This option is used to force the ONLY DEVICE in XFConfig to
>+      use CRT port, instead of default DVI port */
>+    if (xf86ReturnOptValBool (info->Options, OPTION_PANEL_OFF, FALSE)) {
>+	info->PanelOff = TRUE;
>     }
>-    temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
> 
>-    temp |= RADEON_GRPH_BUFFER_SIZE;
>-    temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
>-	      RADEON_GRPH_CRITICAL_AT_SOF |
>-	      RADEON_GRPH_STOP_CNTL);
>-    /*
>-      Write the result into the register.
>-    */
>-    OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
>-				     (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
>+    if (info->PanelOff && info->MergedFB) {
>+	info->OverlayOnCRTC2 = TRUE;
>+	if (MonType == MT_LCD) {
>+	    /* Turning off LVDS_ON seems to make panel white blooming.
>+	     * For now we just turn off display data ???
>+	     */
>+	    save->lvds_gen_cntl |= (RADEON_LVDS_DISPLAY_DIS);
>+	    save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON | RADEON_LVDS_ON);
> 
>-    RADEONTRACE(("GRPH_BUFFER_CNTL from %x to %x\n",
>-		 (unsigned int)info->SavedReg.grph_buffer_cntl, INREG(RADEON_GRPH_BUFFER_CNTL)));
>+	} else if (MonType == MT_DFP)
>+	    save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
>+    } else {
>+	if (MonType == MT_LCD) {
> 
>-    if (mode2) {
>-	stop_req = mode2->HDisplay * info2->CurrentLayout.pixel_bytes / 16;
>+	    /*save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
>+	    save->fp_gen_cntl   &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);*/
> 
>-	if (stop_req > max_stop_req) stop_req = max_stop_req;
>+	} else if ((MonType == MT_DFP) && (TmdsType == TMDS_INT)) {
>+	    int i;
>+	    CARD32 tmp = save->tmds_pll_cntl & 0xfffff;
>+	    for (i=0; i<4; i++) {
>+		if (info->tmds_pll[i].freq == 0) break;
>+		if ((CARD32)(mode->Clock/10) < info->tmds_pll[i].freq) {
>+		    tmp = info->tmds_pll[i].value ;
>+		    break;
>+		}
>+	    }
>+	    if (IS_R300_VARIANT ||
>+		(info->ChipFamily == CHIP_FAMILY_RV280)) {
>+		if (tmp & 0xfff00000)
>+		    save->tmds_pll_cntl = tmp;
>+		else {
>+		    save->tmds_pll_cntl &= 0xfff00000;
>+		    save->tmds_pll_cntl |= tmp;
>+		}
>+	    } else save->tmds_pll_cntl = tmp;
> 
>-	temp = info->SavedReg.grph2_buffer_cntl;
>-	temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
>-	temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
>-	temp &= ~(RADEON_GRPH_START_REQ_MASK);
>-	if ((info->ChipFamily == CHIP_FAMILY_R350) &&
>-	    (stop_req > 0x15)) {
>-	    stop_req -= 0x10;
>-	}
>-	temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
>-	temp |= RADEON_GRPH_BUFFER_SIZE;
>-	temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
>-		  RADEON_GRPH_CRITICAL_AT_SOF |
>-		  RADEON_GRPH_STOP_CNTL);
>-
>-	if ((info->ChipFamily == CHIP_FAMILY_RS100) || 
>-	    (info->ChipFamily == CHIP_FAMILY_RS200))
>-	    critical_point2 = 0;
>-	else {
>-	    read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128));
>-	    time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate);
>+            save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLRST);
>+            if (IS_R300_VARIANT ||
>+		(info->ChipFamily == CHIP_FAMILY_R200) || !info->HasCRTC2)
>+		save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
>+            else /* weird, RV chips got this bit reversed? */
>+                save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
> 
>-	    critical_point2 = (CARD32)((disp_latency + time_disp1_drop_priority + 
>-					disp_latency) * disp_drain_rate2 + 0.5);
>+ 	    /*save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);*/
>+        }
>+    }
> 
>-	    if (info->DispPriority == 2) {
>-		critical_point2 = 0;
>-	    }
>+    info->BiosHotkeys = FALSE;
>+    /*
>+     * Allow the bios to toggle outputs. see below for more.
>+     */
>+    if (info->IsMobility) {
>+        if (xf86ReturnOptValBool(info->Options, OPTION_BIOS_HOTKEYS, FALSE)) {
>+	    info->BiosHotkeys = TRUE;
>+	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIOS HotKeys Enabled\n");
>+        } else {
>+	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIOS HotKeys Disabled\n");
>+        }
>+    }
> 
>-	    if (max_stop_req - critical_point2 < 4) critical_point2 = 0;
>+    if (info->IsMobility && (!info->BiosHotkeys)) {
> 
>+	/* To work correctly with laptop hotkeys.
>+	 * Since there is no machnism for accessing ACPI evnets
>+	 * and the driver currently doesn't know how to validate
>+	 * a mode dynamically, we have to tell BIOS don't do
>+	 * display switching after X has started.  
>+	 * If LCD is on, lid close/open should still work 
>+	 * with below settings
>+	 */
>+	if (info->DisplayType == MT_LCD) {
>+	    if (pRADEONEnt->Controller[1].pPort->MonType == MT_CRT)
>+		save->bios_5_scratch = 0x0201;
>+	    else if (pRADEONEnt->Controller[1].pPort->MonType == MT_DFP)
>+		save->bios_5_scratch = 0x0801;
>+	} else {
>+	    if (pRADEONEnt->Controller[1].pPort->MonType == MT_CRT)
>+		save->bios_5_scratch = 0x0200;
>+	    else if (pRADEONEnt->Controller[1].pPort->MonType == MT_DFP)
>+		save->bios_5_scratch = 0x0800;
>+	    else
>+		save->bios_5_scratch = 0x0; 
> 	}
>+	save->bios_4_scratch = 0x4;
>+	save->bios_6_scratch |= 0x40000000;
> 
>-	if (critical_point2 == 0 && info->ChipFamily == CHIP_FAMILY_R300) {
>-	    /* some R300 cards have problem with this set to 0 */
>-	    critical_point2 = 0x10;
>-	}
>+    } else if (info->IsMobility && (info->DisplayType == MT_LCD)) {
> 
>-	OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
>-					  (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
>+	/* BIOS will use this setting to reset displays upon lid close/open.
>+	 * Here we let BIOS controls LCD, but the driver will control the external CRT.
>+	 */
>+	if (info->MergedFB || pRADEONEnt->HasSecondary)
>+	    save->bios_5_scratch = 0x01020201;
> 
>-	RADEONTRACE(("GRPH2_BUFFER_CNTL from %x to %x\n",
>-		     (unsigned int)info->SavedReg.grph2_buffer_cntl, INREG(RADEON_GRPH2_BUFFER_CNTL)));
>     }
>-}   
>+}
> 
> /* Define CRTC registers for requested video mode */
>-static Bool RADEONInitCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
>-				  DisplayModePtr mode, RADEONInfoPtr info)
>+Bool RADEONInitCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
>+			     DisplayModePtr mode, RADEONInfoPtr info)
> {
>-    unsigned char *RADEONMMIO = info->MMIO;
>+    int    format;
>+    int    hsync_start;
>+    int    hsync_wid;
>+    int    vsync_wid;
> 
>-    int  format;
>-    int  hsync_start;
>-    int  hsync_wid;
>-    int  vsync_wid;
>+    RADEONEntPtr pRADEONEnt   = RADEONEntPriv(pScrn);
> 
>-    switch (info->CurrentLayout.pixel_code) {
>-    case 4:  format = 1; break;
>-    case 8:  format = 2; break;
>-    case 15: format = 3; break;      /*  555 */
>-    case 16: format = 4; break;      /*  565 */
>-    case 24: format = 5; break;      /*  RGB */
>-    case 32: format = 6; break;      /* xRGB */
>-    default:
>-	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
>-		   "Unsupported pixel depth (%d)\n",
>-		   info->CurrentLayout.bitsPerPixel);
>-	return FALSE;
>-    }
>+    pRADEONEnt->Controller[0].IsUsed = TRUE;
>+    pRADEONEnt->Controller[0].IsActive = TRUE;
>+    pRADEONEnt->Controller[0].pCurMode = mode;
> 
>-    if ((info->DisplayType == MT_DFP) ||
>-	(info->DisplayType == MT_LCD)) {
>-	if (mode->Flags & RADEON_USE_RMX) {
>-#if 0
>-	    mode->CrtcHDisplay   = info->PanelXRes;
>-	    mode->CrtcVDisplay   = info->PanelYRes;
>-#endif
>-	    mode->CrtcHTotal     = mode->CrtcHDisplay + info->HBlank;
>-	    mode->CrtcHSyncStart = mode->CrtcHDisplay + info->HOverPlus;
>-	    mode->CrtcHSyncEnd   = mode->CrtcHSyncStart + info->HSyncWidth;
>-	    mode->CrtcVTotal     = mode->CrtcVDisplay + info->VBlank;
>-	    mode->CrtcVSyncStart = mode->CrtcVDisplay + info->VOverPlus;
>-	    mode->CrtcVSyncEnd   = mode->CrtcVSyncStart + info->VSyncWidth;
>-	    mode->Clock          = info->DotClock;
>-	    mode->Flags          = info->Flags | RADEON_USE_RMX;
>-	}
>+    switch (info->CurrentLayout.pixel_code) {
>+        case 4:  format = 1; break;
>+        case 8:  format = 2; break;
>+        case 15: format = 3; break;      /*  555 */
>+        case 16: format = 4; break;      /*  565 */
>+        case 24: format = 5; break;      /*  RGB */
>+        case 32: format = 6; break;      /* xRGB */
>+        default:
>+        xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
>+               "Unsupported pixel depth (%d)\n", info->CurrentLayout.bitsPerPixel);
>+        return FALSE;
>     }
> 
>     save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
>-			   | RADEON_CRTC_EN
>-			   | (format << 8)
>-			   | ((mode->Flags & V_DBLSCAN)
>-			      ? RADEON_CRTC_DBL_SCAN_EN
>-			      : 0)
>-			   | ((mode->Flags & V_CSYNC)
>-			      ? RADEON_CRTC_CSYNC_EN
>-			      : 0)
>-			   | ((mode->Flags & V_INTERLACE)
>-			      ? RADEON_CRTC_INTERLACE_EN
>-			      : 0));
>-
>-    /* Don't try to be smart and unconditionally enable the analog output
>-     * for now as the dodgy code to handle it for the second head doesn't
>-     * work. This will be correctly fixed when Alex' megapatch gets in that
>-     * reworks the whole output mapping
>+              | RADEON_CRTC_EN
>+              | (format << 8)
>+              | ((mode->Flags & V_DBLSCAN)
>+                 ? RADEON_CRTC_DBL_SCAN_EN
>+                 : 0)
>+              | ((mode->Flags & V_INTERLACE)
>+                 ? RADEON_CRTC_INTERLACE_EN
>+                 : 0));
>+
>+    save->crtc_ext_cntl |= (RADEON_CRTC_CRT_ON |
>+			    RADEON_CRTC_VSYNC_DIS |
>+			    RADEON_CRTC_HSYNC_DIS |
>+			    RADEON_CRTC_DISPLAY_DIS);
>+
>+    save->surface_cntl = 0;
>+    save->disp_merge_cntl = info->SavedReg.disp_merge_cntl;
>+    save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
>+
>+#if X_BYTE_ORDER == X_BIG_ENDIAN
>+    /* We must set both apertures as they can be both used to map the entire
>+     * video memory. -BenH.
>      */
>-#if 0
>-    if ((info->DisplayType == MT_DFP) ||
>-	(info->DisplayType == MT_LCD)) {
>-	save->crtc_ext_cntl = RADEON_VGA_ATI_LINEAR | RADEON_XCRT_CNT_EN;
>-	save->crtc_gen_cntl &= ~(RADEON_CRTC_DBL_SCAN_EN |
>-				 RADEON_CRTC_CSYNC_EN |
>-				 RADEON_CRTC_INTERLACE_EN);
>-    } else
>+    switch (pScrn->bitsPerPixel) {
>+    case 16:
>+	save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
>+	save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
>+	break;
>+
>+    case 32:
>+	save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
>+	save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
>+	break;
>+    }
> #endif
>-    {
>-	save->crtc_ext_cntl = (RADEON_VGA_ATI_LINEAR |
>-			       RADEON_XCRT_CNT_EN |
>-			       RADEON_CRTC_CRT_ON);
>+
>+    save->crtc_more_cntl = 0;
>+    if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
>+	(info->ChipFamily == CHIP_FAMILY_RS200)) {
>+	/* This is to workaround the asic bug for RMX, some versions
>+	   of BIOS dosen't have this register initialized correctly.
>+	*/
>+	save->crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
>     }
> 
>-    save->dac_cntl = (RADEON_DAC_MASK_ALL
>-		      | RADEON_DAC_VGA_ADR_EN
>-		      | (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN));
>+    if (mode->Flags & RADEON_USE_RMX) {
>+	mode->CrtcHTotal     = mode->CrtcHDisplay + info->HBlank;
>+	mode->CrtcHSyncStart = mode->CrtcHDisplay + info->HOverPlus;
>+	mode->CrtcHSyncEnd   = mode->CrtcHSyncStart + info->HSyncWidth;
>+	mode->CrtcVTotal     = mode->CrtcVDisplay + info->VBlank;
>+	mode->CrtcVSyncStart = mode->CrtcVDisplay + info->VOverPlus;
>+	mode->CrtcVSyncEnd   = mode->CrtcVSyncStart + info->VSyncWidth;
>+	mode->Clock          = info->DotClock;
>+	mode->Flags          = info->Flags | RADEON_USE_RMX;
>+    }
> 
>     save->crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0x3ff)
>-			       | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff)
>-				  << 16));
>+       | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) << 16));
> 
>     hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8;
>-    if (!hsync_wid) hsync_wid = 1;
>+    if (!hsync_wid)       hsync_wid = 1;
>+    if (hsync_wid > 0x3f) hsync_wid = 0x3f;
>     hsync_start = mode->CrtcHSyncStart - 8;
> 
>     save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
>-				  | ((hsync_wid & 0x3f) << 16)
>-				  | ((mode->Flags & V_NHSYNC)
>-				     ? RADEON_CRTC_H_SYNC_POL
>-				     : 0));
>+                 | (hsync_wid << 16)
>+                 | ((mode->Flags & V_NHSYNC)
>+                    ? RADEON_CRTC_H_SYNC_POL
>+                    : RADEON_CRTC_H_SYNC_POL));
> 
>-#if 1
>-				/* This works for double scan mode. */
>+                /* This works for double scan mode. */
>     save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
>-			       | ((mode->CrtcVDisplay - 1) << 16));
>-#else
>-				/* This is what cce/nbmode.c example code
>-				 * does -- is this correct?
>-				 */
>-    save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
>-			       | ((mode->CrtcVDisplay
>-				   * ((mode->Flags & V_DBLSCAN) ? 2 : 1) - 1)
>-				  << 16));
>-#endif
>+                  | ((mode->CrtcVDisplay - 1) << 16));
> 
>     vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart;
>-    if (!vsync_wid) vsync_wid = 1;
>+    if (!vsync_wid)       vsync_wid = 1;
>+    if (vsync_wid > 0x1f) vsync_wid = 0x1f;
> 
>     save->crtc_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
>-				  | ((vsync_wid & 0x1f) << 16)
>-				  | ((mode->Flags & V_NVSYNC)
>-				     ? RADEON_CRTC_V_SYNC_POL
>-				     : 0));
>+                 | (vsync_wid << 16)
>+                 | ((mode->Flags & V_NVSYNC)
>+                    ? RADEON_CRTC_V_SYNC_POL
>+                    : RADEON_CRTC_V_SYNC_POL));
> 
>-    save->crtc_offset      = pScrn->fbOffset;
>-    save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
>+    save->crtc_offset      = 0;
>+    /*save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);*/
>     if (info->tilingEnabled) {
>        if (IS_R300_VARIANT)
>           save->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
>@@ -8102,40 +6587,97 @@ #endif
>           save->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
>     }
> 
>-    save->crtc_pitch  = (((pScrn->displayWidth * pScrn->bitsPerPixel) +
>-			  ((pScrn->bitsPerPixel * 8) -1)) /
>-			 (pScrn->bitsPerPixel * 8));
>+    save->crtc_pitch  = ((pScrn->displayWidth * pScrn->bitsPerPixel) +
>+			 ((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8);
>     save->crtc_pitch |= save->crtc_pitch << 16;
>-    
>-    save->crtc_more_cntl = 0;
>-    if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
>-        (info->ChipFamily == CHIP_FAMILY_RS200)) {
>-        /* This is to workaround the asic bug for RMX, some versions
>-           of BIOS dosen't have this register initialized correctly.
>-	*/
>-        save->crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
>-    }
> 
>-    save->surface_cntl = 0;
>-    save->disp_merge_cntl = info->SavedReg.disp_merge_cntl;
>-    save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
>-
>-#if X_BYTE_ORDER == X_BIG_ENDIAN
>-    /* We must set both apertures as they can be both used to map the entire
>-     * video memory. -BenH.
>-     */
>-    switch (pScrn->bitsPerPixel) {
>-    case 16:
>-	save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
>-	save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
>-	break;
>+    /* Set following registers for all cases first, if a DFP/LCD is connected on
>+       internal TMDS/LVDS port, they will be set by RADEONInitFPRegister
>+    */
>+    if (!info->IsSwitching) {
>+	save->fp_gen_cntl = 0;
>+	save->fp_vert_stretch &= RADEON_VERT_STRETCH_RESERVED;
>+	save->fp_horz_stretch &= (RADEON_HORZ_FP_LOOP_STRETCH |
>+				  RADEON_HORZ_AUTO_RATIO_INC);
>+    }
>+
>+    if (pRADEONEnt->Controller[0].pPort->MonType == MT_CRT) {
>+        if (pRADEONEnt->Controller[0].pPort->DACType == DAC_PRIMARY) {
>+            if((info->ChipFamily == CHIP_FAMILY_R200) ||
>+               IS_R300_VARIANT) {
>+                save->disp_output_cntl &= ~RADEON_DISP_DAC_SOURCE_MASK;
>+            } else {
>+                save->dac2_cntl &= ~(RADEON_DAC2_DAC_CLK_SEL);
>+            }
>+	    save->dac_cntl = (RADEON_DAC_MASK_ALL
>+			      | RADEON_DAC_VGA_ADR_EN
>+			      | (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN));
>+        } else {
>+	    /*0x0028023;*/
>+	    RADEONInitTvDacCntl(pScrn, save);
>+	    save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
>+            save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
>+            if(IS_R300_VARIANT) {
>+                save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
>+                save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
>+            } else if (info->ChipFamily == CHIP_FAMILY_R200) {
>+		save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
>+					RADEON_FP2_DVO_RATE_SEL_SDR);
>+                save->fp2_gen_cntl |= (RADEON_FP2_ON |
>+				       RADEON_FP2_BLANK_EN |
>+                                       RADEON_FP2_DVO_EN);
>+	    } else {
>+                save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
>+            }
>+        }
>+    } else if ((pRADEONEnt->Controller[0].pPort->MonType == MT_DFP) || 
>+	       (pRADEONEnt->Controller[0].pPort->MonType == MT_LCD)) {
>+
>+	save->fp_h_sync_strt_wid = save->crtc_h_sync_strt_wid;
>+	save->fp_v_sync_strt_wid = save->crtc_v_sync_strt_wid;
>+        save->fp_crtc_h_total_disp = save->crtc_h_total_disp;
>+        save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
>+
>+	RADEONInitFPRegisters(pScrn, save, mode, TRUE);
>+
>+        if ((pRADEONEnt->Controller[0].pPort->TMDSType == TMDS_INT) ||
>+	    (pRADEONEnt->Controller[0].pPort->MonType == MT_LCD)) {
>+
>+	    if (pRADEONEnt->Controller[0].pPort->MonType == MT_LCD) {
>+	        save->lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
>+    	    } else {
>+	        if ((IS_R300_VARIANT) ||
>+		    (info->ChipFamily == CHIP_FAMILY_R200)) {
>+		    save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
>+		    if (mode->Flags & RADEON_USE_RMX) 
>+		        save->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
>+		    else
>+		        save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
>+	        } else 
>+		    save->fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
>+	    }
>+        } else {
> 
>-    case 32:
>-	save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
>-	save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
>-	break;
>-    }
>-#endif
>+            if((info->ChipFamily == CHIP_FAMILY_R200) ||
>+               IS_R300_VARIANT) {
>+                save->fp2_gen_cntl   &= ~(R200_FP2_SOURCE_SEL_MASK | 
>+                                          RADEON_FP2_DVO_EN |
>+                                          RADEON_FP2_DVO_RATE_SEL_SDR);
>+		if (mode->Flags & RADEON_USE_RMX) 
>+		    save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
>+            } else {
>+                save->fp2_gen_cntl   &= ~(RADEON_FP2_SRC_SEL_CRTC2 | 
>+                                          RADEON_FP2_DVO_RATE_SEL_SDR);
>+            }
>+            save->fp2_gen_cntl   |= ( RADEON_FP2_ON |
>+				      RADEON_FP2_BLANK_EN |
>+                                      RADEON_FP2_DVO_EN);
>+	    if (pScrn->rgbBits == 8) 
>+		save->fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
>+	    else
>+		save->fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
>+        }
>+    } 
> 
>     if (info->IsDellServer) {
> 	save->dac2_cntl = info->SavedReg.dac2_cntl;
>@@ -8154,133 +6696,79 @@ #endif
> 	save->tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
>     }
> 
>-    RADEONTRACE(("Pitch = %ld bytes (virtualX = %d, displayWidth = %d)\n",
>-		 save->crtc_pitch, pScrn->virtualX,
>-		 info->CurrentLayout.displayWidth));
>     return TRUE;
> }
> 
> /* Define CRTC2 registers for requested video mode */
>-static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
>-				     DisplayModePtr mode, RADEONInfoPtr info)
>+Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
>+			      DisplayModePtr mode, RADEONInfoPtr info)
> {
>-    unsigned char *RADEONMMIO = info->MMIO;
>+    int    format;
>+    int    hsync_start;
>+    int    hsync_wid;
>+    int    vsync_wid;
>+
>     RADEONEntPtr pRADEONEnt   = RADEONEntPriv(pScrn);
>+    RADEONInfoPtr info0 = NULL;
>+    if (info->IsSecondary)
>+	info0 = RADEONPTR(pRADEONEnt->pPrimaryScrn);
> 
>-    int  format;
>-    int  hsync_start;
>-    int  hsync_wid;
>-    int  vsync_wid;
>+    pRADEONEnt->Controller[1].IsUsed = TRUE;
>+    pRADEONEnt->Controller[1].IsActive = TRUE;
>+    pRADEONEnt->Controller[1].pCurMode = mode;
> 
>     switch (info->CurrentLayout.pixel_code) {
>-    case 4:  format = 1; break;
>-    case 8:  format = 2; break;
>-    case 15: format = 3; break;      /*  555 */
>-    case 16: format = 4; break;      /*  565 */
>-    case 24: format = 5; break;      /*  RGB */
>-    case 32: format = 6; break;      /* xRGB */
>-    default:
>-	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
>-		   "Unsupported pixel depth (%d)\n",
>-		   info->CurrentLayout.bitsPerPixel);
>-	return FALSE;
>-    }
>-
>-    save->crtc2_gen_cntl = (RADEON_CRTC2_EN
>-			    | RADEON_CRTC2_CRT2_ON
>-			    | (format << 8)
>-			    | ((mode->Flags & V_DBLSCAN)
>-			       ? RADEON_CRTC2_DBL_SCAN_EN
>-			       : 0)
>-			    | ((mode->Flags & V_CSYNC)
>-			       ? RADEON_CRTC2_CSYNC_EN
>-			       : 0)
>-			    | ((mode->Flags & V_INTERLACE)
>-			       ? RADEON_CRTC2_INTERLACE_EN
>-			       : 0));
>-
>-    /* Turn CRT on in case the first head is a DFP */
>-    save->dac2_cntl = info->SavedReg.dac2_cntl;
>-    /* always let TVDAC drive CRT2, we don't support tvout yet */
>-    save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
>-    save->disp_output_cntl = info->SavedReg.disp_output_cntl;
>-    if (info->ChipFamily == CHIP_FAMILY_R200 ||
>-	IS_R300_VARIANT) {
>-	save->disp_output_cntl &= ~(RADEON_DISP_DAC_SOURCE_MASK |
>-				    RADEON_DISP_DAC2_SOURCE_MASK);
>-	if (pRADEONEnt->MonType1 != MT_CRT) {
>-	    save->disp_output_cntl |= (RADEON_DISP_DAC_SOURCE_CRTC2 |
>-				       RADEON_DISP_DAC2_SOURCE_CRTC2);
>-	} else {
>-	    if (pRADEONEnt->ReversedDAC) {
>-		save->disp_output_cntl |= RADEON_DISP_DAC2_SOURCE_CRTC2;
>-	    } else {
>-		save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
>-	    }
>-	}
>-    } else {
>-	save->disp_hw_debug = info->SavedReg.disp_hw_debug;
>-	/* Turn on 2nd CRT */
>-	if (pRADEONEnt->MonType1 != MT_CRT) {
>-	    /* This is for some sample boards with the VGA port
>-	       connected to the TVDAC, but BIOS doesn't reflect this.
>-	       Here we configure both DACs to use CRTC2.
>-	       Not sure if this happens in any retail board.
>-	    */
>-	    save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
>-	    save->dac2_cntl |= RADEON_DAC2_DAC_CLK_SEL;
>-	} else {
>-	    if (pRADEONEnt->ReversedDAC) {
>-		save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
>-		save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
>-	    } else {
>-		save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
>-		save->dac2_cntl |= RADEON_DAC2_DAC_CLK_SEL;
>-	    }
>-	}
>+        case 4:  format = 1;  
>+            break;
>+        case 8:  format = 2; 
>+            break;
>+        case 15: format = 3; 
>+            break;      /*  555 */
>+        case 16: format = 4;  
>+            break;      /*  565 */
>+        case 24: format = 5;  
>+            break;      /*  RGB */
>+        case 32: format = 6;  
>+            break;      /* xRGB */
>+        default:
>+            xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
>+            "Unsupported pixel depth (%d)\n", info->CurrentLayout.bitsPerPixel);
>+            return FALSE;
>     }
> 
>-    save->crtc2_h_total_disp =
>-	((((mode->CrtcHTotal / 8) - 1) & 0x3ff)
>-	 | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) << 16));
>+    save->crtc2_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0x3ff)
>+       | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) << 16));
> 
>     hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8;
>-    if (!hsync_wid) hsync_wid = 1;
>+    if (!hsync_wid)       hsync_wid = 1;
>+    if (hsync_wid > 0x3f) hsync_wid = 0x3f;
>     hsync_start = mode->CrtcHSyncStart - 8;
> 
>     save->crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
>-				   | ((hsync_wid & 0x3f) << 16)
>-				   | ((mode->Flags & V_NHSYNC)
>-				      ? RADEON_CRTC_H_SYNC_POL
>-				      : 0));
>+                 | (hsync_wid << 16)
>+                 | ((mode->Flags & V_NHSYNC)
>+                    ? RADEON_CRTC_H_SYNC_POL
>+                    : RADEON_CRTC_H_SYNC_POL));
> 
>-#if 1
>-				/* This works for double scan mode. */
>+                /* This works for double scan mode. */
>     save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
>-				| ((mode->CrtcVDisplay - 1) << 16));
>-#else
>-				/* This is what cce/nbmode.c example code
>-				 * does -- is this correct?
>-				 */
>-    save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
>-				| ((mode->CrtcVDisplay
>-				    * ((mode->Flags & V_DBLSCAN) ? 2 : 1) - 1)
>-				   << 16));
>-#endif
>+                  | ((mode->CrtcVDisplay - 1) << 16));
> 
>     vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart;
>-    if (!vsync_wid) vsync_wid = 1;
>+    if (!vsync_wid)       vsync_wid = 1;
>+    if (vsync_wid > 0x1f) vsync_wid = 0x1f;
> 
>     save->crtc2_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
>-				   | ((vsync_wid & 0x1f) << 16)
>-				   | ((mode->Flags & V_NVSYNC)
>-				      ? RADEON_CRTC2_V_SYNC_POL
>-				      : 0));
>+                 | (vsync_wid << 16)
>+                 | ((mode->Flags & V_NVSYNC)
>+                    ? RADEON_CRTC2_V_SYNC_POL
>+                    : RADEON_CRTC2_V_SYNC_POL));
> 
>     /* It seems all fancy options apart from pflip can be safely disabled
>      */
>-    save->crtc2_offset      = pScrn->fbOffset;
>-    save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & RADEON_CRTC_OFFSET_FLIP_CNTL;
>+    save->crtc2_offset      = 0;
>+    /*save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & RADEON_CRTC_OFFSET_FLIP_CNTL;*/
>+    save->crtc2_offset_cntl &= RADEON_CRTC_OFFSET_FLIP_CNTL;
>     if (info->tilingEnabled) {
>        if (IS_R300_VARIANT)
>           save->crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
>@@ -8298,46 +6786,104 @@ #endif
>           save->crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN;
>     }
> 
>-    /* this should be right */
>-    if (info->MergedFB) {
>-    save->crtc2_pitch  = (((info->CRT2pScrn->displayWidth * pScrn->bitsPerPixel) +
>-			   ((pScrn->bitsPerPixel * 8) -1)) /
>-			  (pScrn->bitsPerPixel * 8));
>-    save->crtc2_pitch |= save->crtc2_pitch << 16;
>-    } else {
>-    save->crtc2_pitch  = (((pScrn->displayWidth * pScrn->bitsPerPixel) +
>-			   ((pScrn->bitsPerPixel * 8) -1)) /
>-			  (pScrn->bitsPerPixel * 8));
>+    save->crtc2_pitch  = ((pScrn->displayWidth * pScrn->bitsPerPixel) +
>+			  ((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8);
>     save->crtc2_pitch |= save->crtc2_pitch << 16;
>-    }
>-    save->disp2_merge_cntl = info->SavedReg.disp2_merge_cntl;
>-    save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN);
> 
>-    if ((info->DisplayType == MT_DFP && info->IsSecondary) || 
>-	info->MergeType == MT_DFP) {
>-	save->crtc2_gen_cntl      = (RADEON_CRTC2_EN | (format << 8));
>-	save->fp2_h_sync_strt_wid = save->crtc2_h_sync_strt_wid;
>-	save->fp2_v_sync_strt_wid = save->crtc2_v_sync_strt_wid;
>-	save->fp2_gen_cntl        = info->SavedReg.fp2_gen_cntl | RADEON_FP2_ON;
>-	save->fp2_gen_cntl	  &= ~(RADEON_FP2_BLANK_EN);
>-
>-	if ((info->ChipFamily == CHIP_FAMILY_R200) ||
>-	    IS_R300_VARIANT) {
>-	    save->fp2_gen_cntl   &= ~(R200_FP2_SOURCE_SEL_MASK |
>-				      RADEON_FP2_DVO_RATE_SEL_SDR);
>-
>-	    save->fp2_gen_cntl |= (R200_FP2_SOURCE_SEL_CRTC2 | 
>-				   RADEON_FP2_DVO_EN);
>-	} else {
>-	    save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_MASK;
>-	    save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
>-	}
>-
>-	if (pScrn->rgbBits == 8)
>-	    save->fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format */
>-	else
>-	    save->fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format */
>+    save->crtc2_gen_cntl = (RADEON_CRTC2_EN
>+                            | RADEON_CRTC2_CRT2_ON
>+                            | (format << 8)
>+			    | RADEON_CRTC2_VSYNC_DIS
>+			    | RADEON_CRTC2_HSYNC_DIS
>+			    | RADEON_CRTC2_DISP_DIS
>+                            | ((mode->Flags & V_DBLSCAN)
>+                               ? RADEON_CRTC2_DBL_SCAN_EN
>+                               : 0)
>+                            | ((mode->Flags & V_INTERLACE)
>+                               ? RADEON_CRTC2_INTERLACE_EN
>+                               : 0));
> 
>+    save->disp2_merge_cntl = info->SavedReg.disp2_merge_cntl;
>+    save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN);
>+     
>+    if (pRADEONEnt->Controller[1].pPort->MonType == MT_CRT) {
>+        if (pRADEONEnt->Controller[1].pPort->DACType == DAC_PRIMARY) {
>+            if((info->ChipFamily == CHIP_FAMILY_R200) ||
>+               IS_R300_VARIANT) {
>+                save->disp_output_cntl &= ~RADEON_DISP_DAC_SOURCE_MASK;
>+                save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
>+            } else {
>+                save->dac2_cntl |= RADEON_DAC2_DAC_CLK_SEL;
>+            }
>+        } else {
>+	    /*save->tv_dac_cntl = 0x0028023;*/
>+	    RADEONInitTvDacCntl(pScrn, save);
>+            if(IS_R300_VARIANT) {
>+                save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
>+                save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
>+                save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
>+	    } else if (info->ChipFamily == CHIP_FAMILY_R200) {
>+		save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
>+					RADEON_FP2_DVO_RATE_SEL_SDR);
>+                save->fp2_gen_cntl |= (R200_FP2_SOURCE_SEL_CRTC2 |
>+				       RADEON_FP2_BLANK_EN |
>+                                       RADEON_FP2_ON |
>+                                       RADEON_FP2_DVO_EN);
>+		save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
>+		save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid;
>+        	save->fp_crtc2_h_total_disp = save->crtc2_h_total_disp;
>+                save->fp_crtc2_v_total_disp = save->crtc2_v_total_disp;
>+            } else {
>+                save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
>+                save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
>+            }
>+        }
>+    } else if ((pRADEONEnt->Controller[1].pPort->MonType == MT_DFP) || 
>+               (pRADEONEnt->Controller[1].pPort->MonType == MT_LCD)) {
>+
>+	save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
>+	save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid;
>+        save->fp_crtc2_h_total_disp = save->crtc2_h_total_disp;
>+        save->fp_crtc2_v_total_disp = save->crtc2_v_total_disp;
>+
>+        if ((pRADEONEnt->Controller[1].pPort->TMDSType == TMDS_INT) || 
>+	    (pRADEONEnt->Controller[1].pPort->MonType == MT_LCD)) {
>+
>+            RADEONInitFPRegisters(pScrn, save, mode, FALSE);
>+
>+	    if (pRADEONEnt->Controller[1].pPort->MonType == MT_LCD) {
>+	        save->lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
>+    	    } else {
>+	        if ((IS_R300_VARIANT) ||
>+		    (info->ChipFamily == CHIP_FAMILY_R200)) {
>+		    save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
>+		    save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
>+	        } else 
>+		    save->fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
>+	    }
>+        } else {
>+            if((info->ChipFamily == CHIP_FAMILY_R200) ||
>+               IS_R300_VARIANT) {
>+                save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | 
>+                                        RADEON_FP2_DVO_RATE_SEL_SDR);
>+                save->fp2_gen_cntl |= (R200_FP2_SOURCE_SEL_CRTC2 | 
>+                                       RADEON_FP2_PANEL_FORMAT |
>+				       RADEON_FP2_BLANK_EN |
>+                                       RADEON_FP2_ON |
>+                                       RADEON_FP2_DVO_EN);
>+            } else {
>+                save->fp2_gen_cntl &= ~(RADEON_FP2_DVO_RATE_SEL_SDR);
>+                save->fp2_gen_cntl |= (RADEON_FP2_SRC_SEL_CRTC2 | 
>+                                       RADEON_FP2_PANEL_FORMAT |
>+				       RADEON_FP2_BLANK_EN |
>+                                       RADEON_FP2_ON |
>+                                       RADEON_FP2_DVO_EN);
>+            }
>+	    if (pScrn->rgbBits == 8) 
>+		save->fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
>+	    else
>+		save->fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
>+        }
>     }
> 
>     /* We must set SURFACE_CNTL properly on the second screen too */
>@@ -8358,257 +6904,10 @@ #if X_BYTE_ORDER == X_BIG_ENDIAN
>        break;
>     }
> #endif
>-
>-    RADEONTRACE(("Pitch = %ld bytes (virtualX = %d, displayWidth = %d)\n",
>-		 save->crtc2_pitch, pScrn->virtualX,
>-		 info->CurrentLayout.displayWidth));
>-
>+ 
>     return TRUE;
> }
> 
>-/* Define CRTC registers for requested video mode */
>-static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr orig,
>-				  RADEONSavePtr save, DisplayModePtr mode,
>-				  RADEONInfoPtr info)
>-{
>-    int    xres = mode->HDisplay;
>-    int    yres = mode->VDisplay;
>-    float  Hratio, Vratio;
>-
>-    /* If the FP registers have been initialized before for a panel,
>-     * but the primary port is a CRT, we need to reinitialize
>-     * FP registers in order for CRT to work properly
>-     */
>-
>-    if ((info->DisplayType != MT_DFP) && (info->DisplayType != MT_LCD)) {
>-        save->fp_crtc_h_total_disp = orig->fp_crtc_h_total_disp;
>-        save->fp_crtc_v_total_disp = orig->fp_crtc_v_total_disp;
>-        save->fp_gen_cntl          = 0;
>-        save->fp_h_sync_strt_wid   = orig->fp_h_sync_strt_wid;
>-        save->fp_horz_stretch      = 0;
>-        save->fp_v_sync_strt_wid   = orig->fp_v_sync_strt_wid;
>-        save->fp_vert_stretch      = 0;
>-        save->lvds_gen_cntl        = orig->lvds_gen_cntl;
>-        save->lvds_pll_cntl        = orig->lvds_pll_cntl;
>-        save->tmds_pll_cntl        = orig->tmds_pll_cntl;
>-        save->tmds_transmitter_cntl= orig->tmds_transmitter_cntl;
>-
>-        save->lvds_gen_cntl |= ( RADEON_LVDS_DISPLAY_DIS | (1 << 23));
>-        save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON | RADEON_LVDS_ON);
>-        save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
>-
>-        return;
>-    }
>-
>-    if (info->PanelXRes == 0 || info->PanelYRes == 0) {
>-	Hratio = 1.0;
>-	Vratio = 1.0;
>-    } else {
>-	if (xres > info->PanelXRes) xres = info->PanelXRes;
>-	if (yres > info->PanelYRes) yres = info->PanelYRes;
>-
>-	Hratio = (float)xres/(float)info->PanelXRes;
>-	Vratio = (float)yres/(float)info->PanelYRes;
>-    }
>-
>-    if (Hratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
>-	save->fp_horz_stretch = orig->fp_horz_stretch;
>-	save->fp_horz_stretch &= ~(RADEON_HORZ_STRETCH_BLEND |
>-				   RADEON_HORZ_STRETCH_ENABLE);
>-	save->fp_horz_stretch &= ~(RADEON_HORZ_AUTO_RATIO |
>-				   RADEON_HORZ_PANEL_SIZE);
>-	save->fp_horz_stretch |= ((xres/8-1)<<16);
>-
>-    } else {
>-	save->fp_horz_stretch =
>-	    ((((unsigned long)(Hratio * RADEON_HORZ_STRETCH_RATIO_MAX +
>-			       0.5)) & RADEON_HORZ_STRETCH_RATIO_MASK)) |
>-	    (orig->fp_horz_stretch & (RADEON_HORZ_PANEL_SIZE |
>-				      RADEON_HORZ_FP_LOOP_STRETCH |
>-				      RADEON_HORZ_AUTO_RATIO_INC));
>-	save->fp_horz_stretch |= (RADEON_HORZ_STRETCH_BLEND |
>-				  RADEON_HORZ_STRETCH_ENABLE);
>-
>-	save->fp_horz_stretch &= ~(RADEON_HORZ_AUTO_RATIO |
>-				   RADEON_HORZ_PANEL_SIZE);
>-	save->fp_horz_stretch |= ((info->PanelXRes / 8 - 1) << 16);
>-
>-    }
>-
>-    if (Vratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
>-	save->fp_vert_stretch = orig->fp_vert_stretch;
>-	save->fp_vert_stretch &= ~(RADEON_VERT_STRETCH_ENABLE|
>-				   RADEON_VERT_STRETCH_BLEND);
>-	save->fp_vert_stretch &= ~(RADEON_VERT_AUTO_RATIO_EN |
>-				   RADEON_VERT_PANEL_SIZE);
>-	save->fp_vert_stretch |= ((yres-1) << 12);
>-    } else {
>-	save->fp_vert_stretch =
>-	    (((((unsigned long)(Vratio * RADEON_VERT_STRETCH_RATIO_MAX +
>-				0.5)) & RADEON_VERT_STRETCH_RATIO_MASK)) |
>-	     (orig->fp_vert_stretch & (RADEON_VERT_PANEL_SIZE |
>-				       RADEON_VERT_STRETCH_RESERVED)));
>-	save->fp_vert_stretch |= (RADEON_VERT_STRETCH_ENABLE |
>-				  RADEON_VERT_STRETCH_BLEND);
>-
>-	save->fp_vert_stretch &= ~(RADEON_VERT_AUTO_RATIO_EN |
>-				   RADEON_VERT_PANEL_SIZE);
>-	save->fp_vert_stretch |= ((info->PanelYRes-1) << 12);
>-
>-    }
>-
>-    save->fp_gen_cntl = (orig->fp_gen_cntl & (CARD32)
>-			 ~(RADEON_FP_SEL_CRTC2 |
>-			   RADEON_FP_RMX_HVSYNC_CONTROL_EN |
>-			   RADEON_FP_DFP_SYNC_SEL |
>-			   RADEON_FP_CRT_SYNC_SEL |
>-			   RADEON_FP_CRTC_LOCK_8DOT |
>-			   RADEON_FP_USE_SHADOW_EN |
>-			   RADEON_FP_CRTC_USE_SHADOW_VEND |
>-			   RADEON_FP_CRT_SYNC_ALT));
>-    save->fp_gen_cntl |= (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
>-			  RADEON_FP_CRTC_DONT_SHADOW_HEND );
>-
>-    if (pScrn->rgbBits == 8)
>-        save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
>-    else
>-        save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
>-
>-    if (IS_R300_VARIANT ||
>-	(info->ChipFamily == CHIP_FAMILY_R200)) {
>-	save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
>-	if (mode->Flags & RADEON_USE_RMX) 
>-	    save->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
>-	else
>-	    save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
>-    } else 
>-	save->fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
>-
>-    save->lvds_gen_cntl = orig->lvds_gen_cntl;
>-    save->lvds_pll_cntl = orig->lvds_pll_cntl;
>-
>-    info->PanelOff = FALSE;
>-    /* This option is used to force the ONLY DEVICE in XFConfig to use
>-     * CRT port, instead of default DVI port.
>-     */
>-    if (xf86ReturnOptValBool(info->Options, OPTION_PANEL_OFF, FALSE)) {
>-	info->PanelOff = TRUE;
>-    }
>-
>-    save->tmds_pll_cntl = orig->tmds_pll_cntl;
>-    save->tmds_transmitter_cntl= orig->tmds_transmitter_cntl;
>-    if (info->PanelOff && info->MergedFB) {
>-	info->OverlayOnCRTC2 = TRUE;
>-	if (info->DisplayType == MT_LCD) {
>-	    /* Turning off LVDS_ON seems to make panel white blooming.
>-	     * For now we just turn off display data ???
>-	     */
>-	    save->lvds_gen_cntl |= (RADEON_LVDS_DISPLAY_DIS);
>-	    save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON | RADEON_LVDS_ON);
>-
>-	} else if (info->DisplayType == MT_DFP)
>-	    save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
>-    } else {
>-	if (info->DisplayType == MT_LCD) {
>-
>-	    save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
>-	    save->fp_gen_cntl   &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
>-
>-	} else if (info->DisplayType == MT_DFP) {
>-	    int i;
>-	    CARD32 tmp = orig->tmds_pll_cntl & 0xfffff;
>-	    for (i=0; i<4; i++) {
>-		if (info->tmds_pll[i].freq == 0) break;
>-		if (save->dot_clock_freq < info->tmds_pll[i].freq) {
>-		    tmp = info->tmds_pll[i].value ;
>-		    break;
>-		}
>-	    }
>-	    if (IS_R300_VARIANT ||
>-		(info->ChipFamily == CHIP_FAMILY_RV280)) {
>-		if (tmp & 0xfff00000)
>-		    save->tmds_pll_cntl = tmp;
>-		else
>-		    save->tmds_pll_cntl = (orig->tmds_pll_cntl & 0xfff00000) | tmp;
>-	    } else save->tmds_pll_cntl = tmp;
>-
>-	    RADEONTRACE(("TMDS_PLL from %lx to %lx\n", 
>-			 orig->tmds_pll_cntl, 
>-			 save->tmds_pll_cntl));
>-
>-            save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLRST);
>-            if (IS_R300_VARIANT ||
>-		(info->ChipFamily == CHIP_FAMILY_R200) || !info->HasCRTC2)
>-		save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
>-            else /* weird, RV chips got this bit reversed? */
>-                save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
>-
>-	    save->fp_gen_cntl   |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
>-        }
>-    }
>-
>-    info->BiosHotkeys = FALSE;
>-    /*
>-     * Allow the bios to toggle outputs. see below for more.
>-     */
>-    if (xf86ReturnOptValBool(info->Options, OPTION_BIOS_HOTKEYS, FALSE)) {
>-	info->BiosHotkeys = TRUE;
>-	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIOS HotKeys Enabled\n");
>-    } else {
>-	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIOS HotKeys Disabled\n");
>-    }
>-
>-    if (info->IsMobility && (!info->BiosHotkeys)) {
>-	RADEONEntPtr pRADEONEnt   = RADEONEntPriv(pScrn);
>-
>-	/* To work correctly with laptop hotkeys.
>-	 * Since there is no machnism for accessing ACPI evnets
>-	 * and the driver currently doesn't know how to validate
>-	 * a mode dynamically, we have to tell BIOS don't do
>-	 * display switching after X has started.  
>-	 * If LCD is on, lid close/open should still work 
>-	 * with below settings
>-	 */
>-	if (info->DisplayType == MT_LCD) {
>-	    if (pRADEONEnt->MonType2 == MT_CRT)
>-		save->bios_5_scratch = 0x0201;
>-	    else if (pRADEONEnt->MonType2 == MT_DFP)
>-		save->bios_5_scratch = 0x0801;
>-	    else
>-		save->bios_5_scratch = orig->bios_5_scratch;
>-	} else {
>-	    if (pRADEONEnt->MonType2 == MT_CRT)
>-		save->bios_5_scratch = 0x0200;
>-	    else if (pRADEONEnt->MonType2 == MT_DFP)
>-		save->bios_5_scratch = 0x0800;
>-	    else
>-		save->bios_5_scratch = 0x0; 
>-	}
>-	save->bios_4_scratch = 0x4;
>-	save->bios_6_scratch = orig->bios_6_scratch | 0x40000000;
>-
>-    } else if (info->IsMobility && (info->DisplayType == MT_LCD)) {
>-	RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
>-
>-	/* BIOS will use this setting to reset displays upon lid close/open.
>-	 * Here we let BIOS controls LCD, but the driver will control the external CRT.
>-	 */
>-	if (info->MergedFB || pRADEONEnt->HasSecondary)
>-	    save->bios_5_scratch = 0x01020201;
>-	else
>-	    save->bios_5_scratch = orig->bios_5_scratch;
>-
>-    	save->bios_4_scratch = orig->bios_4_scratch;
>-	save->bios_6_scratch = orig->bios_6_scratch;
>-
>-    }
>-
>-    save->fp_crtc_h_total_disp = save->crtc_h_total_disp;
>-    save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
>-    save->fp_h_sync_strt_wid   = save->crtc_h_sync_strt_wid;
>-    save->fp_v_sync_strt_wid   = save->crtc_v_sync_strt_wid;
>-}
>-
> /* Define PLL registers for requested video mode */
> static void RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info,
> 				   RADEONSavePtr save, RADEONPLLPtr pll,
>@@ -8673,6 +6972,10 @@ static void RADEONInitPLLRegisters(ScrnI
>     save->ppll_ref_div   = pll->reference_div;
>     save->ppll_div_3     = (save->feedback_div | (post_div->bitvalue << 16));
>     save->htotal_cntl    = 0;
>+
>+    save->vclk_cntl = (info->SavedReg.vclk_cntl &
>+	    ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
>+
> }
> 
> /* Define PLL2 registers for requested video mode */
>@@ -8680,6 +6983,7 @@ static void RADEONInitPLL2Registers(Scrn
> 				    RADEONPLLPtr pll, double dot_clock,
> 				    int no_odd_postdiv)
> {
>+    RADEONInfoPtr  info      = RADEONPTR(pScrn);
>     unsigned long  freq = dot_clock * 100;
> 
>     struct {
>@@ -8736,6 +7040,11 @@ static void RADEONInitPLL2Registers(Scrn
>     save->p2pll_div_0      = (save->feedback_div_2 |
> 			      (post_div->bitvalue << 16));
>     save->htotal_cntl2     = 0;
>+
>+    save->pixclks_cntl = ((info->SavedReg.pixclks_cntl &
>+			   ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
>+			  RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
>+
> }
> 
> #if 0
>@@ -8753,7 +7062,10 @@ static Bool RADEONInit(ScrnInfoPtr pScrn
> 		       RADEONSavePtr save)
> {
>     RADEONInfoPtr  info      = RADEONPTR(pScrn);
>+    RADEONEntPtr pRADEONEnt  = RADEONEntPriv(pScrn);
>     double         dot_clock = mode->Clock/1000.0;
>+    RADEONInfoPtr  info0     = NULL;
>+    ScrnInfoPtr    pScrn0    = NULL;
> 
> #if RADEON_DEBUG
>     ErrorF("%-12.12s %7.2f  %4d %4d %4d %4d  %4d %4d %4d %4d (%d,%d)",
>@@ -8809,9 +7121,13 @@ #endif
>     RADEONInitMemMapRegisters(pScrn, save, info);
>     RADEONInitCommonRegisters(save, info);
>     if (info->IsSecondary) {
>+	pScrn0 = pRADEONEnt->pPrimaryScrn;
>+	info0 = RADEONPTR(pScrn0);
> 	if (!RADEONInitCrtc2Registers(pScrn, save, mode, info))
> 	    return FALSE;
> 	RADEONInitPLL2Registers(pScrn, save, &info->pll, dot_clock, info->DisplayType != MT_CRT);
>+	/* Make sure primary has the same copy */
>+	memcpy(&info0->ModeReg, save, sizeof(RADEONSaveRec));
>     } else if (info->MergedFB) {
>         if (!RADEONInitCrtcRegisters(pScrn, save, 
> 			((RADEONMergedDisplayModePtr)mode->Private)->CRT1, info))
>@@ -8839,27 +7155,17 @@ #endif
> 	    save->ppll_div_3   = info->SavedReg.ppll_div_3;
> 	    save->htotal_cntl  = info->SavedReg.htotal_cntl;
> 	}
>+	if (pRADEONEnt->HasSecondary) {
>+	    pScrn0 = pRADEONEnt->pSecondaryScrn;
>+	    info0 = RADEONPTR(pScrn0);
>+	    /* carry over to secondary screen */
>+	    memcpy(&info0->ModeReg, save, sizeof(RADEONSaveRec));	
>+	}
> 
> 	/* Not used for now: */
>      /* if (!info->PaletteSavedOnVT) RADEONInitPalette(save); */
>     }
> 
>-    /* make RMX work for mergedfb modes on the LCD */
>-    if (info->MergedFB) {
>-	if ((info->MergeType == MT_LCD) || (info->MergeType == MT_DFP)) {
>-            /* I suppose crtc2 could drive the FP as well... */
>-	    RADEONInitFPRegisters(pScrn, &info->SavedReg, save, 
>-		((RADEONMergedDisplayModePtr)mode->Private)->CRT2, info);
>-	}
>-	else {
>-	    RADEONInitFPRegisters(pScrn, &info->SavedReg, save, 
>-		((RADEONMergedDisplayModePtr)mode->Private)->CRT1, info);
>-	}
>-    }
>-    else {
>-    	RADEONInitFPRegisters(pScrn, &info->SavedReg, save, mode, info);
>-    }
>-
>     RADEONTRACE(("RADEONInit returns %p\n", save));
>     return TRUE;
> }
>@@ -9417,257 +7723,6 @@ #endif
>     RADEONFreeRec(pScrn);
> }
> 
>-/*
>- * Powering done DAC, needed for DPMS problem with ViewSonic P817 (or its variant).
>- *
>- * Note for current DAC mapping when calling this function:
>- * For most of cards:
>- * single CRT:  Driver doesn't change the existing CRTC->DAC mapping, 
>- *              CRTC1 could be driving either DAC or both DACs.
>- * CRT+CRT:     CRTC1->TV DAC, CRTC2->Primary DAC
>- * DFP/LCD+CRT: CRTC2->TV DAC, CRTC2->Primary DAC.
>- * Some boards have two DACs reversed or don't even have a primary DAC,
>- * this is reflected in pRADEONEnt->ReversedDAC. And radeon 7200 doesn't 
>- * have a second DAC.
>- * It's kind of messy, we'll need to redo DAC mapping part some day.
>- */
>-static void RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC)
>-{
>-    RADEONInfoPtr  info       = RADEONPTR(pScrn);
>-    unsigned char *RADEONMMIO = info->MMIO;
>-
>-    if (IsPrimaryDAC) {
>-	CARD32 dac_cntl;
>-	CARD32 dac_macro_cntl = 0;
>-	dac_cntl = INREG(RADEON_DAC_CNTL);
>-	if ((!info->IsMobility) || (info->ChipFamily == CHIP_FAMILY_RV350)) 
>-	    dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL);
>-	if (IsOn) {
>-	    dac_cntl &= ~RADEON_DAC_PDWN;
>-	    dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
>-				RADEON_DAC_PDWN_G |
>-				RADEON_DAC_PDWN_B);
>-	} else {
>-	    dac_cntl |= RADEON_DAC_PDWN;
>-	    dac_macro_cntl |= (RADEON_DAC_PDWN_R |
>-			       RADEON_DAC_PDWN_G |
>-			       RADEON_DAC_PDWN_B);
>-	}
>-	OUTREG(RADEON_DAC_CNTL, dac_cntl);
>-	if ((!info->IsMobility) || (info->ChipFamily == CHIP_FAMILY_RV350)) 
>-	    OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
>-    } else {
>-	if (info->ChipFamily != CHIP_FAMILY_R200) {
>-	    CARD32 tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
>-	    if (IsOn) {
>-		tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
>-				 RADEON_TV_DAC_GDACPD |
>-				 RADEON_TV_DAC_BDACPD |
>-				 RADEON_TV_DAC_BGSLEEP);
>-	    } else {
>-		tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
>-				RADEON_TV_DAC_GDACPD |
>-				RADEON_TV_DAC_BDACPD |
>-				RADEON_TV_DAC_BGSLEEP);
>-	    }
>-	    OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl);
>-	} else {
>-	    CARD32 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL);
>-	    if (IsOn) {
>-		fp2_gen_cntl |= RADEON_FP2_DVO_EN;
>-	    } else {
>-		fp2_gen_cntl &= ~RADEON_FP2_DVO_EN;
>-	    }
>-	    OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
>-	}
>-    }
>-}
>-
>-/* Sets VESA Display Power Management Signaling (DPMS) Mode */
>-static void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
>-					    int PowerManagementMode,
>-					    int flags)
>-{
>-    RADEONInfoPtr  info       = RADEONPTR(pScrn);
>-    RADEONEntPtr pRADEONEnt   = RADEONEntPriv(pScrn);
>-    unsigned char *RADEONMMIO = info->MMIO;
>-
>-    if (!pScrn->vtSema) return;
>-
>-    RADEONTRACE(("RADEONDisplayPowerManagementSet(%d,0x%x)\n", PowerManagementMode, flags));
>-
>-#ifdef XF86DRI
>-    if (info->CPStarted) DRILock(pScrn->pScreen, 0);
>-#endif
>-
>-    if (info->accelOn)
>-        RADEON_SYNC(info, pScrn);
>-
>-    if (info->FBDev) {
>-	fbdevHWDPMSSet(pScrn, PowerManagementMode, flags);
>-    } else {
>-	int             mask1     = (RADEON_CRTC_DISPLAY_DIS |
>-				     RADEON_CRTC_HSYNC_DIS |
>-				     RADEON_CRTC_VSYNC_DIS);
>-	int             mask2     = (RADEON_CRTC2_DISP_DIS |
>-				     RADEON_CRTC2_VSYNC_DIS |
>-				     RADEON_CRTC2_HSYNC_DIS);
>-
>-	switch (PowerManagementMode) {
>-	case DPMSModeOn:
>-	    /* Screen: On; HSync: On, VSync: On */
>-	    if (info->IsSecondary)
>-		OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~mask2);
>-	    else {
>-		if (info->MergedFB)
>-		    OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~mask2);
>-		OUTREGP(RADEON_CRTC_EXT_CNTL, 0, ~mask1);
>-	    }
>-	    break;
>-
>-	case DPMSModeStandby:
>-	    /* Screen: Off; HSync: Off, VSync: On */
>-	    if (info->IsSecondary)
>-		OUTREGP(RADEON_CRTC2_GEN_CNTL,
>-			(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS),
>-			~mask2);
>-	    else {
>-		if (info->MergedFB)
>-		    OUTREGP(RADEON_CRTC2_GEN_CNTL,
>-			    (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS),
>-			    ~mask2);
>-		OUTREGP(RADEON_CRTC_EXT_CNTL,
>-			(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS),
>-			~mask1);
>-	    }
>-	    break;
>-
>-	case DPMSModeSuspend:
>-	    /* Screen: Off; HSync: On, VSync: Off */
>-	    if (info->IsSecondary)
>-		OUTREGP(RADEON_CRTC2_GEN_CNTL,
>-			(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS),
>-			~mask2);
>-	    else {
>-		if (info->MergedFB)
>-		    OUTREGP(RADEON_CRTC2_GEN_CNTL,
>-			    (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS),
>-			    ~mask2);
>-		OUTREGP(RADEON_CRTC_EXT_CNTL,
>-			(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS),
>-			~mask1);
>-	    }
>-	    break;
>-
>-	case DPMSModeOff:
>-	    /* Screen: Off; HSync: Off, VSync: Off */
>-	    if (info->IsSecondary)
>-		OUTREGP(RADEON_CRTC2_GEN_CNTL, mask2, ~mask2);
>-	    else {
>-		if (info->MergedFB)
>-		    OUTREGP(RADEON_CRTC2_GEN_CNTL, mask2, ~mask2);
>-		OUTREGP(RADEON_CRTC_EXT_CNTL, mask1, ~mask1);
>-	    }
>-	    break;
>-	}
>-
>-	if (PowerManagementMode == DPMSModeOn) {
>-	    if (info->IsSecondary) {
>-		if (info->DisplayType == MT_DFP) {
>-		    OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN);
>-		    OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON);
>-		    if (info->ChipFamily >= CHIP_FAMILY_R200) {
>-			OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DVO_EN, ~RADEON_FP2_DVO_EN);
>-		    }
>-		} else if (info->DisplayType == MT_CRT) {
>-		    RADEONDacPowerSet(pScrn, TRUE, !pRADEONEnt->ReversedDAC);
>-		}
>-	    } else {
>-		if ((info->MergedFB) && (info->MergeType == MT_DFP)) {
>-		    OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN);
>-		    OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON);
>-		    if (info->ChipFamily >= CHIP_FAMILY_R200) {
>-			OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DVO_EN, ~RADEON_FP2_DVO_EN);
>-		    }
>-		}
>-		if (info->DisplayType == MT_DFP) {
>-		    OUTREGP (RADEON_FP_GEN_CNTL, (RADEON_FP_FPON | RADEON_FP_TMDS_EN),
>-			     ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN));
>-		} else if (info->DisplayType == MT_LCD) {
>-
>-		    OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON);
>-		    usleep (info->PanelPwrDly * 1000);
>-		    OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON);
>-		} else if (info->DisplayType == MT_CRT) {
>-		    if ((pRADEONEnt->HasSecondary) || info->MergedFB) {
>-			RADEONDacPowerSet(pScrn, TRUE, pRADEONEnt->ReversedDAC);
>-		    } else {
>-			RADEONDacPowerSet(pScrn, TRUE, TRUE);
>-			if (info->HasCRTC2)
>-			    RADEONDacPowerSet(pScrn, TRUE, FALSE);
>-		    }
>-		}
>-	    }
>-	} else if ((PowerManagementMode == DPMSModeOff) ||
>-		   (PowerManagementMode == DPMSModeSuspend) ||
>-		   (PowerManagementMode == DPMSModeStandby)) {
>-	    if (info->IsSecondary) {
>-		if (info->DisplayType == MT_DFP) {
>-		    OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN);
>-		    OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON);
>-		    if (info->ChipFamily >= CHIP_FAMILY_R200) {
>-			OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DVO_EN);
>-		    }
>-		} else if (info->DisplayType == MT_CRT) {
>-		    RADEONDacPowerSet(pScrn, FALSE, !pRADEONEnt->ReversedDAC);
>-		}
>-	    } else {
>-		if ((info->MergedFB) && (info->MergeType == MT_DFP)) {
>-		    OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN);
>-		    OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON);
>-		    if (info->ChipFamily >= CHIP_FAMILY_R200) {
>-			OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DVO_EN);
>-		    }
>-		}
>-		if (info->DisplayType == MT_DFP) {
>-		    OUTREGP (RADEON_FP_GEN_CNTL, 0, ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN));
>-		} else if (info->DisplayType == MT_LCD) {
>-		    unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
>-
>-		    if (info->IsMobility || info->IsIGP) {
>-			/* Asic bug, when turning off LVDS_ON, we have to make sure
>-			   RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
>-			*/
>-			OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
>-		    }
>-
>-		    OUTREGP (RADEON_LVDS_GEN_CNTL, 0,
>-			     ~(RADEON_LVDS_BLON | RADEON_LVDS_ON));
>-
>-		    if (info->IsMobility || info->IsIGP) {
>-			OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
>-		    }
>-		} else if (info->DisplayType == MT_CRT) {
>-		    if ((pRADEONEnt->HasSecondary) || info->MergedFB) {
>-			RADEONDacPowerSet(pScrn, FALSE, pRADEONEnt->ReversedDAC);
>-		    } else {
>-			/* single CRT, turning both DACs off, we don't really know 
>-			 * which DAC is actually connected.
>-			 */
>-			RADEONDacPowerSet(pScrn, FALSE, TRUE);
>-			if (info->HasCRTC2) /* don't apply this to old radeon (singel CRTC) card */
>-			    RADEONDacPowerSet(pScrn, FALSE, FALSE);
>-		    }
>-		}
>-	    }
>-	}
>-    }
>-
>-#ifdef XF86DRI
>-    if (info->CPStarted) DRIUnlock(pScrn->pScreen);
>-#endif
>-}
>-
> static void
> RADEONGetMergedFBOptions(ScrnInfoPtr pScrn)
> {
>@@ -9702,7 +7757,7 @@ RADEONGetMergedFBOptions(ScrnInfoPtr pSc
> 	info->MergedFB = FALSE;
>         xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
>         "Failed to detect secondary monitor, MergedFB/Clone mode disabled\n");
>-    } else if (!pRADEONEnt->MonInfo2) {
>+    } else if (!pRADEONEnt->Controller[1].pPort->MonInfo) {
>         xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
> 	"Failed to detect secondary monitor DDC, default HSync and VRefresh used\n");
> 	default_range = TRUE;
>@@ -9868,7 +7923,7 @@ RADEONGetMergedFBOptions(ScrnInfoPtr pSc
> 	  }
> 
> 	  /* xf86SetDDCproperties(info->CRT2pScrn, pRADEONEnt->MonInfo2); */
>-          info->CRT2pScrn->monitor->DDC = pRADEONEnt->MonInfo2;
>+          info->CRT2pScrn->monitor->DDC = pRADEONEnt->Controller[1].pPort->MonInfo;
>           if (default_range) {
>              RADEONStrToRanges(info->CRT2pScrn->monitor->hsync, default_hsync, MAX_HSYNC);
>              RADEONStrToRanges(info->CRT2pScrn->monitor->vrefresh, default_vrefresh, MAX_VREFRESH);
>diff --git a/src/radeon_probe.h b/src/radeon_probe.h
>index a4f20e7..b86901a 100644
>--- a/src/radeon_probe.h
>+++ b/src/radeon_probe.h
>@@ -115,25 +115,21 @@ typedef struct
> 
> typedef struct
> {
>-    Bool HasSecondary;
>+    Bool IsUsed;
>+    Bool IsActive;
>+    DisplayModePtr pCurMode;
>+    RADEONConnector* pPort;
>+} RADEONController;
> 
>-    /*
>-     * The next two are used to make sure CRTC2 is restored before CRTC_EXT,
>-     * otherwise it could lead to blank screens.
>-     */
>-    Bool IsSecondaryRestored;
>-    Bool RestorePrimary;
>+typedef struct
>+{
>+    Bool HasSecondary;
> 
>     ScrnInfoPtr pSecondaryScrn;
>     ScrnInfoPtr pPrimaryScrn;
> 
>-    int MonType1;
>-    int MonType2;
>-    xf86MonPtr MonInfo1;
>-    xf86MonPtr MonInfo2;
>-    Bool ReversedDAC;	  /* TVDAC used as primary dac */
>-    Bool ReversedTMDS;    /* DDC_DVI is used for external TMDS */
>     RADEONConnector PortInfo[2];
>+    RADEONController Controller[2];
> } RADEONEntRec, *RADEONEntPtr;
> 
> /* radeon_probe.c */
>diff --git a/src/radeon_reg.h b/src/radeon_reg.h
>index b7c6e26..d873a96 100644
>--- a/src/radeon_reg.h
>+++ b/src/radeon_reg.h
>@@ -457,6 +457,7 @@ #       define RADEON_DAC_BLANKING      
> #       define RADEON_DAC_CMP_EN            (1 <<  3)
> #       define RADEON_DAC_CMP_OUTPUT        (1 <<  7)
> #       define RADEON_DAC_8BIT_EN           (1 <<  8)
>+#       define RADEON_DAC_TVO_EN            (1 << 10)
> #       define RADEON_DAC_VGA_ADR_EN        (1 << 13)
> #       define RADEON_DAC_PDWN              (1 << 15)
> #       define RADEON_DAC_MASK_ALL          (0xff << 24)
>@@ -475,11 +476,25 @@ #       define RADEON_DAC_PDWN_R        
> #       define RADEON_DAC_PDWN_G            (1 << 17)
> #       define RADEON_DAC_PDWN_B            (1 << 18)
> #define RADEON_TV_DAC_CNTL                  0x088c
>+#       define RADEON_TV_DAC_NBLANK         (1 << 0)
>+#       define RADEON_TV_DAC_NHOLD          (1 << 1)
>+#       define RADEON_TV_DAC_PEDESTAL       (1 <<  2)
>+#       define RADEON_TV_MONITOR_DETECT_EN  (1 <<  4)
>+#       define RADEON_TV_DAC_CMPOUT         (1 <<  5)
>+#       define RADEON_TV_DAC_STD_NTSC       (1 <<  8)
> #       define RADEON_TV_DAC_STD_MASK       0x0300
>+#       define RADEON_TV_DAC_STD_PS2        0x0200
> #       define RADEON_TV_DAC_BGSLEEP        (1 <<  6)
>+#       define RADEON_TV_DAC_BGADJ_MASK     (0xf <<  16)
>+#       define RADEON_TV_DAC_DACADJ_MASK    (0xf <<  20)
> #       define RADEON_TV_DAC_RDACPD         (1 <<  24)
> #       define RADEON_TV_DAC_GDACPD         (1 <<  25)
> #       define RADEON_TV_DAC_BDACPD         (1 <<  26)
>+#       define R420_TV_DAC_DACADJ_MASK      (0x1f <<  20)
>+#       define R420_TV_DAC_RDACPD           (1 <<  25)
>+#       define R420_TV_DAC_GDACPD           (1 <<  26)
>+#       define R420_TV_DAC_BDACPD           (1 <<  27)
>+#       define R420_TV_DAC_TVENABLE         (1 <<  28)
> #define RADEON_DISP_HW_DEBUG                0x0d14
> #       define RADEON_CRT2_DISP1_SEL        (1 <<  5)
> #define RADEON_DISP_OUTPUT_CNTL             0x0d64
>@@ -487,6 +502,14 @@ #       define RADEON_DISP_DAC_SOURCE_MA
> #       define RADEON_DISP_DAC2_SOURCE_MASK  0x0c
> #       define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
> #       define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
>+#       define RADEON_DISP_TVDAC_SOURCE_MASK  (0x03<<2)
>+#       define RADEON_DISP_TVDAC_SOURCE_CRTC  0x0
>+#       define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01<<2)
>+#       define RADEON_DISP_TV_SOURCE_CRTC   (1 << 16) /* crtc1 or crtc2 */
>+#       define RADEON_DISP_TV_SOURCE_LTU    (0 << 16) /* linear transform unit */
>+#define RADEON_DISP_TV_OUT_CNTL             0x0d6c
>+#       define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)
>+#       define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)
> #define RADEON_DAC_CRC_SIG                  0x02cc
> #define RADEON_DAC_DATA                     0x03c9 /* VGA */
> #define RADEON_DAC_MASK                     0x03c6 /* VGA */
>@@ -1450,6 +1473,9 @@ #define RADEON_VIPH_CH1_ABCNT           
> #define RADEON_VIPH_CH2_ABCNT               0x0c38
> #define RADEON_VIPH_CH3_ABCNT               0x0c3c
> #define RADEON_VIPH_CONTROL                 0x0c40
>+#       define RADEON_VIP_BUSY 0
>+#       define RADEON_VIP_IDLE 1
>+#       define RADEON_VIP_RESET 2
> #define RADEON_VIPH_DV_LAT                  0x0c44
> #define RADEON_VIPH_BM_CHUNK                0x0c48
> #define RADEON_VIPH_DV_INT                  0x0c4c
>@@ -3014,15 +3040,75 @@ #define RADEON_SS_HORZ_GUARD_DISCARD_ADJ
> #define RADEON_SS_SHININESS                      60
> 
> #define RADEON_TV_MASTER_CNTL                    0x0800
>+#       define RADEON_TV_ASYNC_RST               (1 <<  0)
>+#       define RADEON_CRT_ASYNC_RST              (1 <<  1)
>+#       define RADEON_RESTART_PHASE_FIX          (1 <<  3)
>+#       define RADEON_CRT_FIFO_CE_EN             (1 <<  9)
>+#       define RADEON_TV_FIFO_CE_EN              (1 << 10)
> #       define RADEON_TVCLK_ALWAYS_ONb           (1 << 30)
>-#define RADEON_TV_DAC_CNTL                       0x088c
>-#       define RADEON_TV_DAC_CMPOUT              (1 << 5)
> #define RADEON_TV_PRE_DAC_MUX_CNTL               0x0888
> #       define RADEON_Y_RED_EN                   (1 << 0)
> #       define RADEON_C_GRN_EN                   (1 << 1)
> #       define RADEON_CMP_BLU_EN                 (1 << 2)
>+#       define RADEON_DAC_DITHER_EN              (1 << 3)
> #       define RADEON_RED_MX_FORCE_DAC_DATA      (6 << 4)
> #       define RADEON_GRN_MX_FORCE_DAC_DATA      (6 << 8)
> #       define RADEON_BLU_MX_FORCE_DAC_DATA      (6 << 12)
> #       define RADEON_TV_FORCE_DAC_DATA_SHIFT    16
>+#define RADEON_TV_RGB_CNTL                           0x0804
>+#       define RADEON_SWITCH_TO_BLUE		  (1 <<  4)
>+#       define RADEON_RGB_DITHER_EN		  (1 <<  5)
>+#       define RADEON_RGB_SRC_SEL_MASK		  (3 <<  8)
>+#       define RADEON_RGB_SRC_SEL_CRTC1		  (0 <<  8)
>+#       define RADEON_RGB_SRC_SEL_RMX		  (1 <<  8)
>+#       define RADEON_RGB_SRC_SEL_CRTC2		  (2 <<  8)
>+#       define RADEON_RGB_CONVERT_BY_PASS	  (1 << 10)
>+#define RADEON_TV_SYNC_CNTL                          0x0808
>+#define RADEON_TV_HTOTAL                             0x080c
>+#define RADEON_TV_HDISP                              0x0810
>+#define RADEON_TV_HSTART                             0x0818
>+#define RADEON_TV_HCOUNT                             0x081C
>+#define RADEON_TV_VTOTAL                             0x0820
>+#define RADEON_TV_VDISP                              0x0824
>+#define RADEON_TV_VCOUNT                             0x0828
>+#define RADEON_TV_FTOTAL                             0x082c
>+#define RADEON_TV_FCOUNT                             0x0830
>+#define RADEON_TV_FRESTART                           0x0834
>+#define RADEON_TV_HRESTART                           0x0838
>+#define RADEON_TV_VRESTART                           0x083c
>+#define RADEON_TV_HOST_READ_DATA                     0x0840
>+#define RADEON_TV_HOST_WRITE_DATA                    0x0844
>+#define RADEON_TV_HOST_RD_WT_CNTL                    0x0848
>+#define RADEON_TV_VSCALER_CNTL1                      0x084c
>+#       define RADEON_RESTART_FIELD              (1 << 29) /* restart on field 0 */
>+#       define RADEON_Y_DEL_W_SIG_SHIFT          26
>+#define RADEON_TV_TIMING_CNTL                        0x0850
>+#define RADEON_TV_VSCALER_CNTL2                      0x0854
>+#       define RADEON_DITHER_MODE                (1 <<  0)
>+#       define RADEON_Y_OUTPUT_DITHER_EN         (1 <<  1)
>+#       define RADEON_UV_OUTPUT_DITHER_EN        (1 <<  2)
>+#       define RADEON_UV_TO_BUF_DITHER_EN        (1 <<  3)
>+#define RADEON_TV_Y_FALL_CNTL                        0x0858
>+#       define RADEON_Y_FALL_PING_PONG           (1 << 16)
>+#define RADEON_TV_Y_RISE_CNTL                        0x085c
>+#       define RADEON_Y_RISE_PING_PONG           (1 << 16)
>+#define RADEON_TV_Y_SAW_TOOTH_CNTL                   0x0860
>+#define RADEON_TV_UPSAMP_AND_GAIN_CNTL               0x0864
>+#define RADEON_TV_GAIN_LIMIT_SETTINGS                0x0868
>+#define RADEON_TV_LINEAR_GAIN_SETTINGS               0x086c
>+#define RADEON_TV_MODULATOR_CNTL1                    0x0870
>+#       define RADEON_ALT_PHASE_EN               (1 <<  6)
>+#       define RADEON_SYNC_TIP_LEVEL             (1 <<  7)
>+#define RADEON_TV_MODULATOR_CNTL2                    0x0874
>+#define RADEON_TV_CRC_CNTL                           0x0890
>+#define RADEON_TV_UV_ADR                             0x08ac
>+#define RADEON_TV_PLL_FINE_CNTL			     0x0020	/* PLL */
>+#define RADEON_TV_PLL_CNTL                           0x0021	/* PLL */
>+#       define RADEON_TV_SLIP_EN                 (1 << 23)
>+#       define RADEON_TV_DTO_EN                  (1 << 28)
>+#define RADEON_TV_PLL_CNTL1                          0x0022	/* PLL */
>+#       define RADEON_TVPLL_TEST_DIS             (1 << 31)
>+#       define RADEON_TVCLK_SRC_SEL_TVPLL        (1 << 30)
>+#       define RADEON_TVPLL_SLEEP                (1 <<  3)
>+#       define RADEON_TVPLL_REFCLK_SEL           (1 <<  4)
> #endif

Actions: View | Splinter Review

Attachments on bug 3621: 2917 | 2961 | 3488 | 5900 | 6775 | 6776 | 6777 | 6785 | 6918 | 6919 | 7179 | 7180 | 7221 | 7222 | 7410

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.