Attachment 70007 Details for Bug 29259 – dmesg

dmesg

dmesg.txt (text/plain), 123.97 KB, created by Chris Wilson on 2012-11-13 14:51:09 UTC

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Filename:

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Creator: Chris Wilson

Created: 2012-11-13 14:51:09 UTC

Size: 123.97 KB

patch

obsolete

>[   48.308116] [drm:drm_mode_debug_printmodeline], Modeline 45:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[   48.308120] [drm:drm_mode_debug_printmodeline], Modeline 23:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   48.308124] [drm:drm_mode_debug_printmodeline], Modeline 18:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   48.308128] [drm:drm_mode_debug_printmodeline], Modeline 41:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[   48.308132] [drm:drm_mode_debug_printmodeline], Modeline 40:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[   48.308136] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   48.308140] [drm:drm_mode_debug_printmodeline], Modeline 44:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[   48.308144] [drm:drm_mode_debug_printmodeline], Modeline 37:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[   48.308148] [drm:drm_mode_debug_printmodeline], Modeline 35:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[   48.308152] [drm:drm_mode_debug_printmodeline], Modeline 34:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[   48.308156] [drm:drm_mode_debug_printmodeline], Modeline 17:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   48.308160] [drm:drm_mode_debug_printmodeline], Modeline 33:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[   48.308164] [drm:drm_mode_debug_printmodeline], Modeline 32:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[   48.308168] [drm:drm_mode_debug_printmodeline], Modeline 24:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   48.308172] [drm:drm_mode_debug_printmodeline], Modeline 31:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   48.308176] [drm:drm_mode_debug_printmodeline], Modeline 25:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   48.308180] [drm:drm_mode_debug_printmodeline], Modeline 43:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[   48.308184] [drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   48.308187] [drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   48.308191] [drm:drm_mode_debug_printmodeline], Modeline 19:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   48.308195] [drm:drm_mode_debug_printmodeline], Modeline 28:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[   48.308199] [drm:drm_mode_debug_printmodeline], Modeline 30:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[   48.308203] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[   48.308207] [drm:drm_mode_debug_printmodeline], Modeline 20:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   48.308211] [drm:drm_mode_debug_printmodeline], Modeline 21:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   48.308215] [drm:drm_mode_debug_printmodeline], Modeline 22:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   48.308234] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[   48.308292] [drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[   48.308296] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:DVI-D-1]
>[   48.308303] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   48.309830] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   48.312529] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   48.312533] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   48.315645] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   48.344135] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   48.347178] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   48.375622] [drm:intel_sdvo_connector_matches_edid], connector_is_digital? 1, monitor_is_digital? 1
>[   48.375687] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:DVI-D-1] probed modes :
>[   48.375690] [drm:drm_mode_debug_printmodeline], Modeline 48:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   48.375694] [drm:drm_mode_debug_printmodeline], Modeline 74:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   48.375698] [drm:drm_mode_debug_printmodeline], Modeline 78:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[   48.375703] [drm:drm_mode_debug_printmodeline], Modeline 71:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[   48.375707] [drm:drm_mode_debug_printmodeline], Modeline 70:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
>[   48.375711] [drm:drm_mode_debug_printmodeline], Modeline 77:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[   48.375715] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   48.375719] [drm:drm_mode_debug_printmodeline], Modeline 50:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   48.375723] [drm:drm_mode_debug_printmodeline], Modeline 73:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[   48.375727] [drm:drm_mode_debug_printmodeline], Modeline 72:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   48.375731] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   48.375735] [drm:drm_mode_debug_printmodeline], Modeline 76:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[   48.375739] [drm:drm_mode_debug_printmodeline], Modeline 69:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[   48.375743] [drm:drm_mode_debug_printmodeline], Modeline 67:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[   48.375747] [drm:drm_mode_debug_printmodeline], Modeline 66:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[   48.375751] [drm:drm_mode_debug_printmodeline], Modeline 49:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   48.375755] [drm:drm_mode_debug_printmodeline], Modeline 65:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[   48.375759] [drm:drm_mode_debug_printmodeline], Modeline 64:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
>[   48.375763] [drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   48.375767] [drm:drm_mode_debug_printmodeline], Modeline 63:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   48.375771] [drm:drm_mode_debug_printmodeline], Modeline 57:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   48.375775] [drm:drm_mode_debug_printmodeline], Modeline 75:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[   48.375779] [drm:drm_mode_debug_printmodeline], Modeline 61:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   48.375783] [drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   48.375787] [drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   48.375791] [drm:drm_mode_debug_printmodeline], Modeline 60:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[   48.375795] [drm:drm_mode_debug_printmodeline], Modeline 62:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[   48.375799] [drm:drm_mode_debug_printmodeline], Modeline 59:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[   48.375803] [drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   48.375807] [drm:drm_mode_debug_printmodeline], Modeline 53:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   48.375811] [drm:drm_mode_debug_printmodeline], Modeline 54:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   48.375831] [drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[   48.584018] [drm:intel_crt_detect], CRT not detected via hotplug
>[   48.668021] [drm:intel_crt_detect_ddc], CRT detected via DDC:0x50 [EDID]
>[   48.668028] [drm:output_poll_execute], [CONNECTOR:12:VGA-1] status updated from 1 to 1
>[   48.668033] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   48.669569] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   48.672259] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   48.672263] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   48.675319] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   48.703773] [drm:output_poll_execute], [CONNECTOR:15:DVI-D-1] status updated from 1 to 1
>[   48.872851] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[   48.874382] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[   48.877062] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[   48.877066] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   48.880130] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[   48.924019] [drm:intel_crt_detect], CRT not detected via hotplug
>[   49.008031] [drm:intel_crt_detect_ddc], CRT detected via DDC:0x50 [EDID]
>[  860.630481] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  860.632035] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  860.634704] [drm:intel_connector_check_state], [CONNECTOR:15:DVI-D-1]
>[  860.634708] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  860.634711] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  860.634715] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  860.634717] [drm:intel_modeset_check_state], [CRTC:3]
>[  860.634721] [drm:intel_modeset_check_state], [CRTC:4]
>[  860.634729] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[  860.637531] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  860.638608] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[  860.641519] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  860.664033] [drm:intel_update_fbc], fbc set to per-chip default
>[  860.664037] [drm:intel_update_fbc], fbc disabled per module param
>[  860.664041] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  860.664044] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  860.664046] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  860.664052] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  860.665582] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00
>[  860.668345] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  860.668349] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  860.668352] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  860.668355] [drm:intel_modeset_check_state], [CRTC:3]
>[  860.668358] [drm:intel_modeset_check_state], [CRTC:4]
>[  860.668827] [drm:drm_mode_setcrtc], [CRTC:3]
>[  860.668831] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  860.668835] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  860.668838] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  860.668840] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [NOCRTC]
>[  860.668843] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  860.668845] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  860.668848] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  860.668850] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  860.668857] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  860.670385] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00
>[  860.673449] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  860.673453] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  860.673456] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  860.673459] [drm:intel_modeset_check_state], [CRTC:3]
>[  860.673462] [drm:intel_modeset_check_state], [CRTC:4]
>[  921.296515] [drm:drm_mode_setcrtc], [CRTC:3]
>[  921.296525] [drm:drm_mode_setcrtc], [CONNECTOR:12:VGA-1]
>[  921.296528] [drm:drm_mode_setcrtc], [CONNECTOR:15:DVI-D-1]
>[  921.296532] [drm:intel_crtc_set_config], [CRTC:3] [FB:82] #connectors=2 (x y) (0 0)
>[  921.296536] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  921.296539] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  921.296542] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  921.296544] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[  921.296547] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  921.296550] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  921.296552] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  921.296554] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  921.296557] [drm:drm_mode_debug_printmodeline], Modeline 81:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  921.296562] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  921.296567] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  921.297026] [drm:i9xx_crtc_mode_set], Mode for pipe A:
>[  921.297029] [drm:drm_mode_debug_printmodeline], Modeline 81:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  921.320028] [drm:i9xx_update_plane], Writing base 01029000 00000000 0 0 7680
>[  921.320037] [drm:intel_update_fbc], fbc set to per-chip default
>[  921.320039] [drm:intel_update_fbc], fbc disabled per module param
>[  921.320043] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  921.320046] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  921.320049] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  921.320052] [drm:intel_crtc_mode_set], [ENCODER:13:DAC-13] set [MODE:81:]
>[  921.320056] [drm:intel_crtc_mode_set], [ENCODER:14:TMDS-14] set [MODE:81:]
>[  921.320060] [drm:intel_sdvo_debug_write], SDVOB: W: 07 01 00 00 00             (SDVO_CMD_SET_IN_OUT_MAP)
>[  921.324130] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  921.325044] [drm:intel_sdvo_debug_write], SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>[  921.327830] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  921.328739] [drm:intel_sdvo_debug_write], SDVOB: W: 16 02 3A 80 18 71 38 2D 40 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>[  921.335339] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  921.336258] [drm:intel_sdvo_debug_write], SDVOB: W: 17 58 2C 45 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>[  921.342859] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  921.343749] [drm:intel_sdvo_debug_write], SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>[  921.345935] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  921.346832] [drm:intel_sdvo_debug_write], SDVOB: W: 9F 00                      (SDVO_CMD_SET_ENCODE)
>[  921.349029] [drm:intel_sdvo_read_response], SDVOB: R: (Not supported)... failed
>[  921.349928] [drm:intel_sdvo_debug_write], SDVOB: W: 14 02 3A 80 18 71 38 2D 40 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>[  921.356530] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  921.357419] [drm:intel_sdvo_debug_write], SDVOB: W: 15 58 2C 45 00 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>[  921.364046] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  921.364953] [drm:intel_sdvo_debug_write], SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>[  921.367112] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  921.368021] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  921.368026] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  921.368029] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  921.384025] [drm:intel_update_fbc], fbc set to per-chip default
>[  921.384028] [drm:intel_update_fbc], fbc disabled per module param
>[  921.416024] [drm:intel_sdvo_debug_write], SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>[  921.417552] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01
>[  921.419327] [drm:intel_sdvo_debug_write], SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[  921.422138] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  921.423041] [drm:intel_connector_check_state], [CONNECTOR:12:VGA-1]
>[  921.423045] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  921.424594] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  921.427254] [drm:intel_connector_check_state], [CONNECTOR:15:DVI-D-1]
>[  921.427257] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  921.427261] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  921.427264] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  921.427266] [drm:intel_modeset_check_state], [CRTC:3]
>[  921.427269] [drm:intel_modeset_check_state], [CRTC:4]
>[  921.427387] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  921.428937] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  921.431597] [drm:intel_connector_check_state], [CONNECTOR:15:DVI-D-1]
>[  921.431600] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  921.431603] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  921.431606] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  921.431609] [drm:intel_modeset_check_state], [CRTC:3]
>[  921.431612] [drm:intel_modeset_check_state], [CRTC:4]
>[  921.431617] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[  921.434432] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  921.435330] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[  921.438139] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  921.468053] [drm:intel_update_fbc], fbc set to per-chip default
>[  921.468058] [drm:intel_update_fbc], fbc disabled per module param
>[  921.468061] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  921.468064] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  921.468067] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  921.468073] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  921.469619] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00
>[  921.472335] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  921.472339] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  921.472343] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  921.472346] [drm:intel_modeset_check_state], [CRTC:3]
>[  921.472348] [drm:intel_modeset_check_state], [CRTC:4]
>[  921.472464] [drm:drm_mode_setcrtc], [CRTC:3]
>[  921.472468] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  921.472472] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  921.472474] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  921.472477] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [NOCRTC]
>[  921.472479] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  921.472482] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  921.472484] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  921.472487] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  921.472495] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  921.474039] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00
>[  921.476720] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  921.476724] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  921.476727] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  921.476729] [drm:intel_modeset_check_state], [CRTC:3]
>[  921.476732] [drm:intel_modeset_check_state], [CRTC:4]
>[  961.253569] [drm:intel_crtc_cursor_set], cursor off
>[  961.580225] [drm:drm_mode_setcrtc], [CRTC:3]
>[  961.580236] [drm:drm_mode_setcrtc], [CONNECTOR:12:VGA-1]
>[  961.580239] [drm:drm_mode_setcrtc], [CONNECTOR:15:DVI-D-1]
>[  961.580242] [drm:intel_crtc_set_config], [CRTC:3] [FB:82] #connectors=2 (x y) (0 0)
>[  961.580246] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  961.580249] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  961.580252] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  961.580255] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[  961.580258] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  961.580260] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  961.580263] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  961.580265] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  961.580267] [drm:drm_mode_debug_printmodeline], Modeline 81:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  961.580272] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  961.580277] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  961.580738] [drm:i9xx_crtc_mode_set], Mode for pipe A:
>[  961.580740] [drm:drm_mode_debug_printmodeline], Modeline 81:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  961.604026] [drm:i9xx_update_plane], Writing base 01029000 00000000 0 0 7680
>[  961.604035] [drm:intel_update_fbc], fbc set to per-chip default
>[  961.604038] [drm:intel_update_fbc], fbc disabled per module param
>[  961.604042] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  961.604045] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  961.604047] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  961.604052] [drm:intel_crtc_mode_set], [ENCODER:13:DAC-13] set [MODE:81:]
>[  961.604056] [drm:intel_crtc_mode_set], [ENCODER:14:TMDS-14] set [MODE:81:]
>[  961.604060] [drm:intel_sdvo_debug_write], SDVOB: W: 07 01 00 00 00             (SDVO_CMD_SET_IN_OUT_MAP)
>[  961.608127] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.609095] [drm:intel_sdvo_debug_write], SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>[  961.611888] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.612804] [drm:intel_sdvo_debug_write], SDVOB: W: 16 02 3A 80 18 71 38 2D 40 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>[  961.619399] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.624132] [drm:intel_sdvo_debug_write], SDVOB: W: 17 58 2C 45 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>[  961.630755] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.631649] [drm:intel_sdvo_debug_write], SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>[  961.633832] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.635081] [drm:intel_sdvo_debug_write], SDVOB: W: 9F 00                      (SDVO_CMD_SET_ENCODE)
>[  961.637268] [drm:intel_sdvo_read_response], SDVOB: R: (Not supported)... failed
>[  961.638158] [drm:intel_sdvo_debug_write], SDVOB: W: 14 02 3A 80 18 71 38 2D 40 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>[  961.644805] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.645706] [drm:intel_sdvo_debug_write], SDVOB: W: 15 58 2C 45 00 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>[  961.652345] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.653238] [drm:intel_sdvo_debug_write], SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>[  961.655403] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.656325] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  961.656328] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  961.656331] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  961.664052] [drm:intel_update_fbc], fbc set to per-chip default
>[  961.664057] [drm:intel_update_fbc], fbc disabled per module param
>[  961.704030] [drm:intel_sdvo_debug_write], SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>[  961.705574] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01
>[  961.707358] [drm:intel_sdvo_debug_write], SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[  961.710176] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.711089] [drm:intel_connector_check_state], [CONNECTOR:12:VGA-1]
>[  961.711094] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  961.712646] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  961.715329] [drm:intel_connector_check_state], [CONNECTOR:15:DVI-D-1]
>[  961.715333] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  961.715337] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  961.715340] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  961.715343] [drm:intel_modeset_check_state], [CRTC:3]
>[  961.715346] [drm:intel_modeset_check_state], [CRTC:4]
>[  961.717233] [drm:intel_crtc_set_config], [CRTC:3] [FB:80] #connectors=1 (x y) (0 0)
>[  961.717236] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  961.717240] [drm:drm_mode_debug_printmodeline], Modeline 81:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  961.717244] [drm:drm_mode_debug_printmodeline], Modeline 79:"1920x1080" 0 148800 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  961.717246] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  961.717248] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  961.717250] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  961.717251] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  961.717253] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  961.717256] [drm:drm_mode_debug_printmodeline], Modeline 79:"1920x1080" 0 148800 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  961.717258] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  961.717264] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  961.717271] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[  961.720970] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.752048] [drm:intel_update_fbc], fbc set to per-chip default
>[  961.752050] [drm:intel_update_fbc], fbc disabled per module param
>[  961.752054] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  961.752056] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  961.752057] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  961.752530] [drm:i9xx_crtc_mode_set], Mode for pipe A:
>[  961.752535] [drm:drm_mode_debug_printmodeline], Modeline 79:"1920x1080" 0 148800 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  961.776042] [drm:i9xx_update_plane], Writing base 00040000 00000000 0 0 7680
>[  961.776048] [drm:intel_update_fbc], fbc set to per-chip default
>[  961.776049] [drm:intel_update_fbc], fbc disabled per module param
>[  961.776052] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  961.776054] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  961.776055] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  961.776059] [drm:intel_crtc_mode_set], [ENCODER:14:TMDS-14] set [MODE:79:1920x1080]
>[  961.776066] [drm:intel_sdvo_debug_write], SDVOB: W: 07 01 00 00 00             (SDVO_CMD_SET_IN_OUT_MAP)
>[  961.781032] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.781038] [drm:intel_sdvo_debug_write], SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>[  961.784725] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.784732] [drm:intel_sdvo_debug_write], SDVOB: W: 16 20 3A 80 18 71 38 2D 40 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>[  961.795844] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.795851] [drm:intel_sdvo_debug_write], SDVOB: W: 17 58 2C 45 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>[  961.803376] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.803383] [drm:intel_sdvo_debug_write], SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>[  961.806431] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.806436] [drm:intel_sdvo_debug_write], SDVOB: W: 9F 00                      (SDVO_CMD_SET_ENCODE)
>[  961.809524] [drm:intel_sdvo_read_response], SDVOB: R: (Not supported)... failed
>[  961.809531] [drm:intel_sdvo_debug_write], SDVOB: W: 14 20 3A 80 18 71 38 2D 40 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>[  961.817045] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.817051] [drm:intel_sdvo_debug_write], SDVOB: W: 15 58 2C 45 00 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>[  961.824556] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.824570] [drm:intel_sdvo_debug_write], SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>[  961.827609] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.827615] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  961.827617] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  961.827618] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  961.837714] [drm:intel_update_fbc], fbc set to per-chip default
>[  961.837716] [drm:intel_update_fbc], fbc disabled per module param
>[  961.876031] [drm:intel_sdvo_debug_write], SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>[  961.879330] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01
>[  961.879335] [drm:intel_sdvo_debug_write], SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[  961.883017] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  961.883028] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  961.887278] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  961.887282] [drm:intel_connector_check_state], [CONNECTOR:15:DVI-D-1]
>[  961.887285] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  961.887287] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  961.887289] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  961.887291] [drm:intel_modeset_check_state], [CRTC:3]
>[  961.887293] [drm:intel_modeset_check_state], [CRTC:4]
>[  961.887297] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[  961.887300] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  961.887303] [drm:intel_crtc_set_config], [CRTC:3] [FB:80] #connectors=1 (x y) (0 0)
>[  961.887306] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  961.887320] [drm:intel_crtc_set_config], [CRTC:3] [FB:80] #connectors=1 (x y) (0 0)
>[  961.887322] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  961.916812] [drm:intel_crtc_set_config], [CRTC:3] [FB:80] #connectors=1 (x y) (0 0)
>[  961.916822] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  961.916826] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[  961.916829] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.100516] [drm:i915_driver_open], 
>[  969.100547] [drm:intel_crtc_set_config], [CRTC:3] [FB:80] #connectors=1 (x y) (0 0)
>[  969.100555] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.100558] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[  969.100562] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.110859] [drm:intel_crtc_set_config], [CRTC:3] [FB:80] #connectors=1 (x y) (0 0)
>[  969.110864] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.121035] [drm:i915_driver_open], 
>[  969.121056] [drm:intel_crtc_set_config], [CRTC:3] [FB:80] #connectors=1 (x y) (0 0)
>[  969.121063] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.121066] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[  969.121069] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.121081] [drm:i915_driver_open], 
>[  969.121104] [drm:intel_crtc_set_config], [CRTC:3] [FB:80] #connectors=1 (x y) (0 0)
>[  969.121109] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.121111] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[  969.121114] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.121644] [drm:i915_driver_open], 
>[  969.121657] [drm:intel_crtc_set_config], [CRTC:3] [FB:80] #connectors=1 (x y) (0 0)
>[  969.121662] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.121665] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[  969.121668] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.121679] [drm:i915_driver_open], 
>[  969.122337] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3]
>[  969.122342] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3]
>[  969.122384] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[  969.122388] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[  969.122392] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[  969.122396] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[  969.122399] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[  969.122401] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[  969.122626] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[  969.122630] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1]
>[  969.136025] [drm:intel_crt_detect], CRT not detected via hotplug
>[  969.220023] [drm:intel_crt_detect_ddc], CRT detected via DDC:0x50 [EDID]
>[  969.304079] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  969.304111] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1] probed modes :
>[  969.304114] [drm:drm_mode_debug_printmodeline], Modeline 16:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  969.304119] [drm:drm_mode_debug_printmodeline], Modeline 42:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  969.304123] [drm:drm_mode_debug_printmodeline], Modeline 46:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  969.304127] [drm:drm_mode_debug_printmodeline], Modeline 39:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  969.304131] [drm:drm_mode_debug_printmodeline], Modeline 38:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  969.304136] [drm:drm_mode_debug_printmodeline], Modeline 45:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  969.304140] [drm:drm_mode_debug_printmodeline], Modeline 23:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  969.304144] [drm:drm_mode_debug_printmodeline], Modeline 18:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  969.304148] [drm:drm_mode_debug_printmodeline], Modeline 41:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  969.304152] [drm:drm_mode_debug_printmodeline], Modeline 40:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  969.304156] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  969.304160] [drm:drm_mode_debug_printmodeline], Modeline 44:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  969.304164] [drm:drm_mode_debug_printmodeline], Modeline 37:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  969.304168] [drm:drm_mode_debug_printmodeline], Modeline 35:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  969.304172] [drm:drm_mode_debug_printmodeline], Modeline 34:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  969.304177] [drm:drm_mode_debug_printmodeline], Modeline 17:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  969.304181] [drm:drm_mode_debug_printmodeline], Modeline 33:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  969.304185] [drm:drm_mode_debug_printmodeline], Modeline 32:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  969.304189] [drm:drm_mode_debug_printmodeline], Modeline 24:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  969.304193] [drm:drm_mode_debug_printmodeline], Modeline 31:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  969.304197] [drm:drm_mode_debug_printmodeline], Modeline 25:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  969.304201] [drm:drm_mode_debug_printmodeline], Modeline 43:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  969.304205] [drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  969.304209] [drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  969.304213] [drm:drm_mode_debug_printmodeline], Modeline 19:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  969.304217] [drm:drm_mode_debug_printmodeline], Modeline 28:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  969.304221] [drm:drm_mode_debug_printmodeline], Modeline 30:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  969.304225] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  969.304229] [drm:drm_mode_debug_printmodeline], Modeline 20:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  969.304233] [drm:drm_mode_debug_printmodeline], Modeline 21:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  969.304237] [drm:drm_mode_debug_printmodeline], Modeline 22:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  969.304258] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[  969.304327] [drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[  969.304331] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:DVI-D-1]
>[  969.304338] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  969.305870] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  969.308554] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  969.309952] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  969.316912] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  969.345450] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  969.348524] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  969.376954] [drm:intel_sdvo_connector_matches_edid], connector_is_digital? 1, monitor_is_digital? 1
>[  969.384099] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:DVI-D-1] probed modes :
>[  969.384104] [drm:drm_mode_debug_printmodeline], Modeline 48:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  969.384108] [drm:drm_mode_debug_printmodeline], Modeline 74:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  969.384113] [drm:drm_mode_debug_printmodeline], Modeline 78:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  969.384117] [drm:drm_mode_debug_printmodeline], Modeline 71:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  969.384121] [drm:drm_mode_debug_printmodeline], Modeline 70:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
>[  969.384125] [drm:drm_mode_debug_printmodeline], Modeline 77:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  969.384130] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  969.384134] [drm:drm_mode_debug_printmodeline], Modeline 50:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  969.384138] [drm:drm_mode_debug_printmodeline], Modeline 73:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  969.384142] [drm:drm_mode_debug_printmodeline], Modeline 72:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  969.384146] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  969.384150] [drm:drm_mode_debug_printmodeline], Modeline 76:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  969.384154] [drm:drm_mode_debug_printmodeline], Modeline 69:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  969.384158] [drm:drm_mode_debug_printmodeline], Modeline 67:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  969.384162] [drm:drm_mode_debug_printmodeline], Modeline 66:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  969.384166] [drm:drm_mode_debug_printmodeline], Modeline 49:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  969.384171] [drm:drm_mode_debug_printmodeline], Modeline 65:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  969.384175] [drm:drm_mode_debug_printmodeline], Modeline 64:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
>[  969.384179] [drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  969.384183] [drm:drm_mode_debug_printmodeline], Modeline 63:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  969.384187] [drm:drm_mode_debug_printmodeline], Modeline 57:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  969.384191] [drm:drm_mode_debug_printmodeline], Modeline 75:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  969.384195] [drm:drm_mode_debug_printmodeline], Modeline 61:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  969.384199] [drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  969.384203] [drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  969.384207] [drm:drm_mode_debug_printmodeline], Modeline 60:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  969.384211] [drm:drm_mode_debug_printmodeline], Modeline 62:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  969.384215] [drm:drm_mode_debug_printmodeline], Modeline 59:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  969.384219] [drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  969.384223] [drm:drm_mode_debug_printmodeline], Modeline 53:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  969.384227] [drm:drm_mode_debug_printmodeline], Modeline 54:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  969.384247] [drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[  969.384337] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[  969.384341] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[  969.384344] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[  969.384348] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[  969.384350] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[  969.384353] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[  969.384397] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[  969.384400] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1]
>[  969.392020] [drm:intel_crt_detect], CRT not detected via hotplug
>[  969.476042] [drm:intel_crt_detect_ddc], CRT detected via DDC:0x50 [EDID]
>[  969.560080] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  969.560114] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1] probed modes :
>[  969.560117] [drm:drm_mode_debug_printmodeline], Modeline 16:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  969.560122] [drm:drm_mode_debug_printmodeline], Modeline 42:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  969.560126] [drm:drm_mode_debug_printmodeline], Modeline 46:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  969.560130] [drm:drm_mode_debug_printmodeline], Modeline 39:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  969.560134] [drm:drm_mode_debug_printmodeline], Modeline 38:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  969.560138] [drm:drm_mode_debug_printmodeline], Modeline 45:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  969.560143] [drm:drm_mode_debug_printmodeline], Modeline 23:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  969.560147] [drm:drm_mode_debug_printmodeline], Modeline 18:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  969.560151] [drm:drm_mode_debug_printmodeline], Modeline 41:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  969.560154] [drm:drm_mode_debug_printmodeline], Modeline 40:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  969.560159] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  969.560163] [drm:drm_mode_debug_printmodeline], Modeline 44:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  969.560167] [drm:drm_mode_debug_printmodeline], Modeline 37:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  969.560171] [drm:drm_mode_debug_printmodeline], Modeline 35:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  969.560175] [drm:drm_mode_debug_printmodeline], Modeline 34:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  969.560179] [drm:drm_mode_debug_printmodeline], Modeline 17:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  969.560183] [drm:drm_mode_debug_printmodeline], Modeline 33:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  969.560187] [drm:drm_mode_debug_printmodeline], Modeline 32:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  969.560191] [drm:drm_mode_debug_printmodeline], Modeline 24:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  969.560195] [drm:drm_mode_debug_printmodeline], Modeline 31:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  969.560199] [drm:drm_mode_debug_printmodeline], Modeline 25:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  969.560203] [drm:drm_mode_debug_printmodeline], Modeline 43:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  969.560207] [drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  969.560211] [drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  969.560215] [drm:drm_mode_debug_printmodeline], Modeline 19:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  969.560219] [drm:drm_mode_debug_printmodeline], Modeline 28:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  969.560223] [drm:drm_mode_debug_printmodeline], Modeline 30:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  969.560227] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  969.560231] [drm:drm_mode_debug_printmodeline], Modeline 20:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  969.560235] [drm:drm_mode_debug_printmodeline], Modeline 21:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  969.560239] [drm:drm_mode_debug_printmodeline], Modeline 22:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  969.560255] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[  969.561425] [drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[  969.561430] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:DVI-D-1]
>[  969.561437] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  969.562974] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  969.567678] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  969.567683] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  969.571001] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  969.600989] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  969.604171] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  969.632734] [drm:intel_sdvo_connector_matches_edid], connector_is_digital? 1, monitor_is_digital? 1
>[  969.632850] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:DVI-D-1] probed modes :
>[  969.632854] [drm:drm_mode_debug_printmodeline], Modeline 48:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  969.632859] [drm:drm_mode_debug_printmodeline], Modeline 74:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  969.632863] [drm:drm_mode_debug_printmodeline], Modeline 78:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  969.632867] [drm:drm_mode_debug_printmodeline], Modeline 71:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  969.632871] [drm:drm_mode_debug_printmodeline], Modeline 70:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
>[  969.632875] [drm:drm_mode_debug_printmodeline], Modeline 77:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  969.632879] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  969.632883] [drm:drm_mode_debug_printmodeline], Modeline 50:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  969.632887] [drm:drm_mode_debug_printmodeline], Modeline 73:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  969.632892] [drm:drm_mode_debug_printmodeline], Modeline 72:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  969.632896] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  969.632900] [drm:drm_mode_debug_printmodeline], Modeline 76:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  969.632904] [drm:drm_mode_debug_printmodeline], Modeline 69:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  969.632908] [drm:drm_mode_debug_printmodeline], Modeline 67:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  969.632912] [drm:drm_mode_debug_printmodeline], Modeline 66:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  969.632917] [drm:drm_mode_debug_printmodeline], Modeline 49:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  969.632921] [drm:drm_mode_debug_printmodeline], Modeline 65:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  969.632925] [drm:drm_mode_debug_printmodeline], Modeline 64:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
>[  969.632929] [drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  969.632933] [drm:drm_mode_debug_printmodeline], Modeline 63:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  969.632937] [drm:drm_mode_debug_printmodeline], Modeline 57:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  969.632941] [drm:drm_mode_debug_printmodeline], Modeline 75:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  969.632945] [drm:drm_mode_debug_printmodeline], Modeline 61:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  969.632949] [drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  969.632953] [drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  969.632957] [drm:drm_mode_debug_printmodeline], Modeline 60:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  969.632961] [drm:drm_mode_debug_printmodeline], Modeline 62:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  969.632966] [drm:drm_mode_debug_printmodeline], Modeline 59:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  969.632969] [drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  969.632974] [drm:drm_mode_debug_printmodeline], Modeline 53:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  969.632977] [drm:drm_mode_debug_printmodeline], Modeline 54:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  969.632994] [drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[  969.635573] [drm:asle_set_backlight], bclp = 0x80000025
>[  969.635579] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[  969.635582] [drm:intel_panel_actually_set_backlight], set backlight PWM = 1749397
>[  969.635585] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[  969.635590] [drm:intel_opregion_asle_intr], non asle set request??
>[  969.637469] [drm:asle_set_backlight], bclp = 0x80000025
>[  969.637474] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[  969.637477] [drm:intel_panel_actually_set_backlight], set backlight PWM = 1749397
>[  969.637480] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[  969.637485] [drm:intel_opregion_asle_intr], non asle set request??
>[  969.656306] [drm:drm_mode_addfb], [FB:81]
>[  969.666588] [drm:drm_mode_setcrtc], [CRTC:3]
>[  969.666599] [drm:drm_mode_setcrtc], [CONNECTOR:12:VGA-1]
>[  969.666603] [drm:drm_mode_setcrtc], [CONNECTOR:15:DVI-D-1]
>[  969.666606] [drm:intel_crtc_set_config], [CRTC:3] [FB:81] #connectors=2 (x y) (0 0)
>[  969.666611] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  969.666614] [drm:drm_mode_debug_printmodeline], Modeline 79:"1920x1080" 0 148800 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  969.666619] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  969.666623] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  969.666626] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[  969.666629] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.666632] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  969.666635] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  969.666637] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  969.666642] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  969.666647] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  969.666652] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[  969.669493] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  969.704031] [drm:intel_update_fbc], fbc set to per-chip default
>[  969.704037] [drm:intel_update_fbc], fbc disabled per module param
>[  969.704040] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  969.704043] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  969.704046] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  969.704507] [drm:i9xx_crtc_mode_set], Mode for pipe A:
>[  969.704510] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  969.728031] [drm:i9xx_update_plane], Writing base 00829000 00000000 0 0 7680
>[  969.728043] [drm:intel_update_fbc], fbc set to per-chip default
>[  969.728045] [drm:intel_update_fbc], fbc disabled per module param
>[  969.728049] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  969.728052] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  969.728055] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  969.728059] [drm:intel_crtc_mode_set], [ENCODER:13:DAC-13] set [MODE:82:]
>[  969.728063] [drm:intel_crtc_mode_set], [ENCODER:14:TMDS-14] set [MODE:82:]
>[  969.728068] [drm:intel_sdvo_debug_write], SDVOB: W: 07 01 00 00 00             (SDVO_CMD_SET_IN_OUT_MAP)
>[  969.732148] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  969.733608] [drm:intel_sdvo_debug_write], SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>[  969.736415] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  969.737444] [drm:intel_sdvo_debug_write], SDVOB: W: 16 02 3A 80 18 71 38 2D 40 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>[  969.744098] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  969.745168] [drm:intel_sdvo_debug_write], SDVOB: W: 17 58 2C 45 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>[  969.751777] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  969.752815] [drm:intel_sdvo_debug_write], SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>[  969.754977] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  969.755869] [drm:intel_sdvo_debug_write], SDVOB: W: 9F 00                      (SDVO_CMD_SET_ENCODE)
>[  969.758055] [drm:intel_sdvo_read_response], SDVOB: R: (Not supported)... failed
>[  969.759191] [drm:intel_sdvo_debug_write], SDVOB: W: 14 02 3A 80 18 71 38 2D 40 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>[  969.765806] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  969.766832] [drm:intel_sdvo_debug_write], SDVOB: W: 15 58 2C 45 00 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>[  969.773479] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  969.774519] [drm:intel_sdvo_debug_write], SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>[  969.776705] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  969.777721] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  969.777725] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  969.777727] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  969.792039] [drm:intel_update_fbc], fbc set to per-chip default
>[  969.792044] [drm:intel_update_fbc], fbc disabled per module param
>[  969.824028] [drm:intel_sdvo_debug_write], SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>[  969.825570] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01
>[  969.827351] [drm:intel_sdvo_debug_write], SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[  969.830155] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  969.831337] [drm:intel_connector_check_state], [CONNECTOR:12:VGA-1]
>[  969.831341] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  969.832882] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  969.835728] [drm:intel_connector_check_state], [CONNECTOR:15:DVI-D-1]
>[  969.835733] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  969.835736] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  969.835739] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  969.835742] [drm:intel_modeset_check_state], [CRTC:3]
>[  969.835745] [drm:intel_modeset_check_state], [CRTC:4]
>[  969.835797] [drm:drm_mode_setcrtc], [CRTC:4]
>[  969.835801] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[  969.835804] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[  969.835807] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.836977] [drm:asle_set_backlight], bclp = 0x80000025
>[  969.836982] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[  969.836985] [drm:intel_panel_actually_set_backlight], set backlight PWM = 1749397
>[  969.836988] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[  969.836993] [drm:intel_opregion_asle_intr], non asle set request??
>[  969.837586] [drm:drm_mode_setcrtc], [CRTC:4]
>[  969.837589] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[  969.837593] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[  969.837596] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.837604] [drm:drm_mode_setcrtc], [CRTC:4]
>[  969.837607] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[  969.837610] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[  969.837613] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  969.837618] [drm:drm_mode_setcrtc], [CRTC:4]
>[  969.837620] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[  969.837623] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[  969.837626] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[  979.240022] [drm:intel_crt_detect], CRT not detected via hotplug
>[  979.324026] [drm:intel_crt_detect_ddc], CRT detected via DDC:0x50 [EDID]
>[  979.324033] [drm:output_poll_execute], [CONNECTOR:12:VGA-1] status updated from 1 to 1
>[  979.324038] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[  979.325567] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  979.328243] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[  979.328597] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  979.331641] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[  979.363142] [drm:output_poll_execute], [CONNECTOR:15:DVI-D-1] status updated from 1 to 1
>[  995.644238] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  995.645770] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[  995.648461] [drm:intel_connector_check_state], [CONNECTOR:15:DVI-D-1]
>[  995.648465] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  995.648469] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  995.648472] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  995.648474] [drm:intel_modeset_check_state], [CRTC:3]
>[  995.648477] [drm:intel_modeset_check_state], [CRTC:4]
>[  995.649094] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[  995.652028] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  995.652966] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[  995.655787] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[  995.688027] [drm:intel_update_fbc], fbc set to per-chip default
>[  995.688031] [drm:intel_update_fbc], fbc disabled per module param
>[  995.688034] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[  995.688037] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[  995.688040] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[  995.688046] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  995.689575] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00
>[  995.692262] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  995.692265] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  995.692268] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  995.692271] [drm:intel_modeset_check_state], [CRTC:3]
>[  995.692274] [drm:intel_modeset_check_state], [CRTC:4]
>[  995.692301] [drm:drm_mode_setcrtc], [CRTC:3]
>[  995.692304] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  995.692308] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  995.692311] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  995.692314] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [NOCRTC]
>[  995.692316] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  995.692319] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  995.692321] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  995.692324] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  995.692329] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[  995.693868] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00
>[  995.696570] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[  995.696573] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[  995.696578] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[  995.696580] [drm:intel_modeset_check_state], [CRTC:3]
>[  995.696583] [drm:intel_modeset_check_state], [CRTC:4]
>[  995.696617] [drm:drm_mode_setcrtc], [CRTC:3]
>[  995.696619] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[ 1203.268772] [drm:drm_mode_setcrtc], [CRTC:3]
>[ 1203.268782] [drm:drm_mode_setcrtc], [CONNECTOR:12:VGA-1]
>[ 1203.268785] [drm:drm_mode_setcrtc], [CONNECTOR:15:DVI-D-1]
>[ 1203.268788] [drm:intel_crtc_set_config], [CRTC:3] [FB:81] #connectors=2 (x y) (0 0)
>[ 1203.268792] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 1203.268795] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 1203.268798] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 1203.268800] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[ 1203.268803] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[ 1203.268806] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 1203.268808] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 1203.268810] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[ 1203.268813] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1203.268818] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 1203.268822] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[ 1203.269281] [drm:i9xx_crtc_mode_set], Mode for pipe A:
>[ 1203.269284] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1203.296416] [drm:i9xx_update_plane], Writing base 00829000 00000000 0 0 7680
>[ 1203.296422] [drm:intel_update_fbc], fbc set to per-chip default
>[ 1203.296425] [drm:intel_update_fbc], fbc disabled per module param
>[ 1203.296429] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[ 1203.296431] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[ 1203.296434] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[ 1203.296437] [drm:intel_crtc_mode_set], [ENCODER:13:DAC-13] set [MODE:82:]
>[ 1203.296441] [drm:intel_crtc_mode_set], [ENCODER:14:TMDS-14] set [MODE:82:]
>[ 1203.296455] [drm:intel_sdvo_debug_write], SDVOB: W: 07 01 00 00 00             (SDVO_CMD_SET_IN_OUT_MAP)
>[ 1203.300560] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1203.301459] [drm:intel_sdvo_debug_write], SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>[ 1203.304268] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1203.305158] [drm:intel_sdvo_debug_write], SDVOB: W: 16 02 3A 80 18 71 38 2D 40 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>[ 1203.311751] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1203.312662] [drm:intel_sdvo_debug_write], SDVOB: W: 17 58 2C 45 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>[ 1203.319263] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1203.320162] [drm:intel_sdvo_debug_write], SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>[ 1203.322317] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1203.323206] [drm:intel_sdvo_debug_write], SDVOB: W: 9F 00                      (SDVO_CMD_SET_ENCODE)
>[ 1203.325386] [drm:intel_sdvo_read_response], SDVOB: R: (Not supported)... failed
>[ 1203.326283] [drm:intel_sdvo_debug_write], SDVOB: W: 14 02 3A 80 18 71 38 2D 40 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>[ 1203.332899] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1203.333788] [drm:intel_sdvo_debug_write], SDVOB: W: 15 58 2C 45 00 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>[ 1203.340396] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1203.341293] [drm:intel_sdvo_debug_write], SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>[ 1203.343461] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1203.344368] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[ 1203.344370] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[ 1203.344373] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[ 1203.360027] [drm:intel_update_fbc], fbc set to per-chip default
>[ 1203.360030] [drm:intel_update_fbc], fbc disabled per module param
>[ 1203.392022] [drm:intel_sdvo_debug_write], SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>[ 1203.393679] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01
>[ 1203.395583] [drm:intel_sdvo_debug_write], SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[ 1203.398606] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1203.399547] [drm:intel_connector_check_state], [CONNECTOR:12:VGA-1]
>[ 1203.399551] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[ 1203.401094] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[ 1203.403753] [drm:intel_connector_check_state], [CONNECTOR:15:DVI-D-1]
>[ 1203.403757] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[ 1203.403760] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[ 1203.403763] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[ 1203.403766] [drm:intel_modeset_check_state], [CRTC:3]
>[ 1203.403769] [drm:intel_modeset_check_state], [CRTC:4]
>[ 1222.055162] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[ 1222.055170] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[ 1222.055173] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[ 1222.055178] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[ 1222.055181] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[ 1222.055183] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[ 1222.055196] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[ 1222.055199] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1]
>[ 1222.068023] [drm:intel_crt_detect], CRT not detected via hotplug
>[ 1222.152044] [drm:intel_crt_detect_ddc], CRT detected via DDC:0x50 [EDID]
>[ 1222.236139] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[ 1222.236206] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1] probed modes :
>[ 1222.236214] [drm:drm_mode_debug_printmodeline], Modeline 16:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1222.236225] [drm:drm_mode_debug_printmodeline], Modeline 42:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1222.236235] [drm:drm_mode_debug_printmodeline], Modeline 46:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[ 1222.236246] [drm:drm_mode_debug_printmodeline], Modeline 39:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[ 1222.236256] [drm:drm_mode_debug_printmodeline], Modeline 38:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[ 1222.236266] [drm:drm_mode_debug_printmodeline], Modeline 45:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[ 1222.236277] [drm:drm_mode_debug_printmodeline], Modeline 23:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1222.236287] [drm:drm_mode_debug_printmodeline], Modeline 18:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1222.236297] [drm:drm_mode_debug_printmodeline], Modeline 41:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[ 1222.236307] [drm:drm_mode_debug_printmodeline], Modeline 40:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[ 1222.236317] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1222.236327] [drm:drm_mode_debug_printmodeline], Modeline 44:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[ 1222.236337] [drm:drm_mode_debug_printmodeline], Modeline 37:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[ 1222.236347] [drm:drm_mode_debug_printmodeline], Modeline 35:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[ 1222.236358] [drm:drm_mode_debug_printmodeline], Modeline 34:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[ 1222.236368] [drm:drm_mode_debug_printmodeline], Modeline 17:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1222.236378] [drm:drm_mode_debug_printmodeline], Modeline 33:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[ 1222.236388] [drm:drm_mode_debug_printmodeline], Modeline 32:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[ 1222.236398] [drm:drm_mode_debug_printmodeline], Modeline 24:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1222.236408] [drm:drm_mode_debug_printmodeline], Modeline 31:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1222.236418] [drm:drm_mode_debug_printmodeline], Modeline 25:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1222.236428] [drm:drm_mode_debug_printmodeline], Modeline 43:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[ 1222.236438] [drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1222.236448] [drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1222.236458] [drm:drm_mode_debug_printmodeline], Modeline 19:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1222.236468] [drm:drm_mode_debug_printmodeline], Modeline 28:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1222.236478] [drm:drm_mode_debug_printmodeline], Modeline 30:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[ 1222.236487] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1222.236497] [drm:drm_mode_debug_printmodeline], Modeline 20:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1222.236507] [drm:drm_mode_debug_printmodeline], Modeline 21:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1222.236517] [drm:drm_mode_debug_printmodeline], Modeline 22:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1222.236563] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[ 1222.274520] [drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[ 1222.274525] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:DVI-D-1]
>[ 1222.274532] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[ 1222.276074] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[ 1222.278738] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[ 1222.278741] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1222.281796] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1222.310228] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1222.313295] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1222.341727] [drm:intel_sdvo_connector_matches_edid], connector_is_digital? 1, monitor_is_digital? 1
>[ 1222.341797] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:DVI-D-1] probed modes :
>[ 1222.341800] [drm:drm_mode_debug_printmodeline], Modeline 48:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1222.341805] [drm:drm_mode_debug_printmodeline], Modeline 74:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1222.341809] [drm:drm_mode_debug_printmodeline], Modeline 78:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[ 1222.341813] [drm:drm_mode_debug_printmodeline], Modeline 71:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[ 1222.341817] [drm:drm_mode_debug_printmodeline], Modeline 70:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
>[ 1222.341821] [drm:drm_mode_debug_printmodeline], Modeline 77:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[ 1222.341825] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1222.341829] [drm:drm_mode_debug_printmodeline], Modeline 50:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1222.341833] [drm:drm_mode_debug_printmodeline], Modeline 73:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[ 1222.341837] [drm:drm_mode_debug_printmodeline], Modeline 72:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1222.341841] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1222.341845] [drm:drm_mode_debug_printmodeline], Modeline 76:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[ 1222.341849] [drm:drm_mode_debug_printmodeline], Modeline 69:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[ 1222.341854] [drm:drm_mode_debug_printmodeline], Modeline 67:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[ 1222.341858] [drm:drm_mode_debug_printmodeline], Modeline 66:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[ 1222.341862] [drm:drm_mode_debug_printmodeline], Modeline 49:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1222.341866] [drm:drm_mode_debug_printmodeline], Modeline 65:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[ 1222.341870] [drm:drm_mode_debug_printmodeline], Modeline 64:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
>[ 1222.341874] [drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1222.341878] [drm:drm_mode_debug_printmodeline], Modeline 63:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1222.341882] [drm:drm_mode_debug_printmodeline], Modeline 57:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1222.341886] [drm:drm_mode_debug_printmodeline], Modeline 75:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[ 1222.341890] [drm:drm_mode_debug_printmodeline], Modeline 61:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1222.341894] [drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1222.341898] [drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1222.341902] [drm:drm_mode_debug_printmodeline], Modeline 60:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1222.341906] [drm:drm_mode_debug_printmodeline], Modeline 62:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[ 1222.341910] [drm:drm_mode_debug_printmodeline], Modeline 59:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1222.341914] [drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1222.341918] [drm:drm_mode_debug_printmodeline], Modeline 53:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1222.341922] [drm:drm_mode_debug_printmodeline], Modeline 54:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1222.341937] [drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[ 1222.343595] [drm:asle_set_backlight], bclp = 0x80000025
>[ 1222.343600] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[ 1222.343603] [drm:intel_panel_actually_set_backlight], set backlight PWM = 1749397
>[ 1222.343606] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[ 1222.343612] [drm:intel_opregion_asle_intr], non asle set request??
>[ 1222.345007] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[ 1222.346570] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[ 1222.349254] [drm:intel_connector_check_state], [CONNECTOR:15:DVI-D-1]
>[ 1222.349258] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[ 1222.349261] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[ 1222.349264] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[ 1222.349267] [drm:intel_modeset_check_state], [CRTC:3]
>[ 1222.349270] [drm:intel_modeset_check_state], [CRTC:4]
>[ 1222.349277] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[ 1222.352070] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1222.352980] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[ 1222.355785] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1222.388027] [drm:intel_update_fbc], fbc set to per-chip default
>[ 1222.388032] [drm:intel_update_fbc], fbc disabled per module param
>[ 1222.388037] [drm:i965_update_wm], self-refresh entries: 120, wm: 392
>[ 1222.388042] [drm:i965_update_wm], self-refresh watermark: display plane 392 cursor 32
>[ 1222.388047] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 392
>[ 1222.388053] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[ 1222.389611] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00
>[ 1222.392364] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[ 1222.392369] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[ 1222.392374] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[ 1222.392379] [drm:intel_modeset_check_state], [CRTC:3]
>[ 1222.392383] [drm:intel_modeset_check_state], [CRTC:4]
>[ 1222.392414] [drm:drm_mode_setcrtc], [CRTC:3]
>[ 1222.392419] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[ 1222.392424] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [NOCRTC]
>[ 1222.392429] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 1222.392433] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [NOCRTC]
>[ 1222.392437] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 1222.392441] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 1222.392444] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 1222.392449] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[ 1222.392457] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[ 1222.394015] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00
>[ 1222.396768] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[ 1222.396774] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[ 1222.396778] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[ 1222.396783] [drm:intel_modeset_check_state], [CRTC:3]
>[ 1222.396787] [drm:intel_modeset_check_state], [CRTC:4]
>[ 1222.396795] [drm:drm_mode_setcrtc], [CRTC:4]
>[ 1222.396799] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[ 1222.421657] [drm:drm_mode_setcrtc], [CRTC:3]
>[ 1222.421663] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[ 1222.421670] [drm:drm_mode_setcrtc], [CRTC:4]
>[ 1222.421674] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[ 1222.532856] [drm:drm_mode_addfb], [FB:81]
>[ 1222.532867] [drm:drm_mode_setcrtc], [CRTC:4]
>[ 1222.532876] [drm:drm_mode_setcrtc], [CONNECTOR:15:DVI-D-1]
>[ 1222.532881] [drm:intel_crtc_set_config], [CRTC:4] [FB:81] #connectors=1 (x y) (0 0)
>[ 1222.532887] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 1222.532892] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[ 1222.532896] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1222.532902] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 78800 1024 1040 1136 1312 768 769 772 800 0x0 0x5
>[ 1222.532910] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 1222.532915] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:4]
>[ 1222.532920] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 1222.532923] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[ 1222.532927] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 78800 1024 1040 1136 1312 768 769 772 800 0x0 0x5
>[ 1222.532934] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 1222.532941] [drm:intel_modeset_adjusted_mode], [CRTC:4]
>[ 1222.533505] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[ 1222.533509] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 78800 1024 1040 1136 1312 768 769 772 800 0x0 0x5
>[ 1222.548030] [drm:i9xx_update_plane], Writing base 01012000 00000000 0 0 4096
>[ 1222.548035] [drm:intel_update_fbc], fbc set to per-chip default
>[ 1222.548038] [drm:intel_update_fbc], fbc disabled per module param
>[ 1222.548042] [drm:i965_update_wm], self-refresh entries: 64, wm: 448
>[ 1222.548044] [drm:i965_update_wm], self-refresh watermark: display plane 448 cursor 32
>[ 1222.548047] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 448
>[ 1222.548050] [drm:intel_crtc_mode_set], [ENCODER:14:TMDS-14] set [MODE:82:]
>[ 1222.548054] [drm:intel_sdvo_debug_write], SDVOB: W: 07 01 00 00 00             (SDVO_CMD_SET_IN_OUT_MAP)
>[ 1222.552121] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1222.553034] [drm:intel_sdvo_debug_write], SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>[ 1222.555820] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1222.556751] [drm:intel_sdvo_debug_write], SDVOB: W: 16 C8 1E 00 20 41 00 20 30 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>[ 1222.563356] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1222.564261] [drm:intel_sdvo_debug_write], SDVOB: W: 17 10 60 13 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>[ 1222.570852] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1222.571741] [drm:intel_sdvo_debug_write], SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>[ 1222.573917] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1222.574814] [drm:intel_sdvo_debug_write], SDVOB: W: 9F 00                      (SDVO_CMD_SET_ENCODE)
>[ 1222.576979] [drm:intel_sdvo_read_response], SDVOB: R: (Not supported)... failed
>[ 1222.577868] [drm:intel_sdvo_debug_write], SDVOB: W: 14 C8 1E 00 20 41 00 20 30 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>[ 1222.584521] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1222.585418] [drm:intel_sdvo_debug_write], SDVOB: W: 15 10 60 13 00 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>[ 1222.592021] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1222.592910] [drm:intel_sdvo_debug_write], SDVOB: W: 21 02                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>[ 1222.595064] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1222.595955] [drm:i965_update_wm], self-refresh entries: 64, wm: 448
>[ 1222.595958] [drm:i965_update_wm], self-refresh watermark: display plane 448 cursor 32
>[ 1222.595960] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 448
>[ 1222.604019] [drm:intel_update_fbc], fbc set to per-chip default
>[ 1222.604022] [drm:intel_update_fbc], fbc disabled per module param
>[ 1222.628026] [drm:intel_sdvo_debug_write], SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>[ 1222.629679] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01
>[ 1222.631596] [drm:intel_sdvo_debug_write], SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[ 1222.634634] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1222.635576] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[ 1222.637123] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[ 1222.639802] [drm:intel_connector_check_state], [CONNECTOR:15:DVI-D-1]
>[ 1222.639806] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[ 1222.639809] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[ 1222.639812] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[ 1222.639815] [drm:intel_modeset_check_state], [CRTC:3]
>[ 1222.639817] [drm:intel_modeset_check_state], [CRTC:4]
>[ 1222.639845] [drm:drm_mode_setcrtc], [CRTC:3]
>[ 1222.639847] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[ 1222.639851] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:4]
>[ 1222.640780] [drm:asle_set_backlight], bclp = 0x80000025
>[ 1222.640784] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[ 1222.640787] [drm:intel_panel_actually_set_backlight], set backlight PWM = 1749397
>[ 1222.640790] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[ 1222.640796] [drm:intel_opregion_asle_intr], non asle set request??
>[ 1222.641375] [drm:drm_mode_setcrtc], [CRTC:3]
>[ 1222.641379] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[ 1222.641383] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:4]
>[ 1222.641388] [drm:drm_mode_setcrtc], [CRTC:3]
>[ 1222.641390] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[ 1222.641393] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:4]
>[ 1232.168037] [drm:intel_crt_detect], CRT not detected via hotplug
>[ 1232.252038] [drm:intel_crt_detect_ddc], CRT detected via DDC:0x50 [EDID]
>[ 1232.252050] [drm:output_poll_execute], [CONNECTOR:12:VGA-1] status updated from 1 to 1
>[ 1232.252060] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[ 1232.253708] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[ 1232.256593] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[ 1232.256602] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1232.259866] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1232.289404] [drm:output_poll_execute], [CONNECTOR:15:DVI-D-1] status updated from 1 to 1
>[ 1233.186335] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[ 1233.186351] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[ 1233.186359] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[ 1233.186370] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[ 1233.186377] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[ 1233.186384] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[ 1233.186410] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[ 1233.186417] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1]
>[ 1233.200043] [drm:intel_crt_detect], CRT not detected via hotplug
>[ 1233.284044] [drm:intel_crt_detect_ddc], CRT detected via DDC:0x50 [EDID]
>[ 1233.368140] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[ 1233.368205] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1] probed modes :
>[ 1233.368214] [drm:drm_mode_debug_printmodeline], Modeline 16:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1233.368225] [drm:drm_mode_debug_printmodeline], Modeline 42:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1233.368236] [drm:drm_mode_debug_printmodeline], Modeline 46:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[ 1233.368246] [drm:drm_mode_debug_printmodeline], Modeline 39:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[ 1233.368257] [drm:drm_mode_debug_printmodeline], Modeline 38:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[ 1233.368267] [drm:drm_mode_debug_printmodeline], Modeline 45:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[ 1233.368277] [drm:drm_mode_debug_printmodeline], Modeline 23:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1233.368287] [drm:drm_mode_debug_printmodeline], Modeline 18:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1233.368297] [drm:drm_mode_debug_printmodeline], Modeline 41:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[ 1233.368307] [drm:drm_mode_debug_printmodeline], Modeline 40:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[ 1233.368317] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1233.368327] [drm:drm_mode_debug_printmodeline], Modeline 44:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[ 1233.368337] [drm:drm_mode_debug_printmodeline], Modeline 37:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[ 1233.368347] [drm:drm_mode_debug_printmodeline], Modeline 35:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[ 1233.368357] [drm:drm_mode_debug_printmodeline], Modeline 34:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[ 1233.368368] [drm:drm_mode_debug_printmodeline], Modeline 17:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1233.368378] [drm:drm_mode_debug_printmodeline], Modeline 33:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[ 1233.368388] [drm:drm_mode_debug_printmodeline], Modeline 32:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[ 1233.368398] [drm:drm_mode_debug_printmodeline], Modeline 24:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1233.368408] [drm:drm_mode_debug_printmodeline], Modeline 31:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1233.368418] [drm:drm_mode_debug_printmodeline], Modeline 25:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1233.368428] [drm:drm_mode_debug_printmodeline], Modeline 43:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[ 1233.368438] [drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1233.368448] [drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1233.368458] [drm:drm_mode_debug_printmodeline], Modeline 19:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1233.368468] [drm:drm_mode_debug_printmodeline], Modeline 28:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1233.368478] [drm:drm_mode_debug_printmodeline], Modeline 30:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[ 1233.368488] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1233.368497] [drm:drm_mode_debug_printmodeline], Modeline 20:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1233.368508] [drm:drm_mode_debug_printmodeline], Modeline 21:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1233.368517] [drm:drm_mode_debug_printmodeline], Modeline 22:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1233.368563] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[ 1233.368697] [drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[ 1233.368706] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:DVI-D-1]
>[ 1233.368718] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[ 1233.370386] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[ 1233.373342] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[ 1233.373346] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1233.376448] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1233.404925] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1233.407972] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1233.436458] [drm:intel_sdvo_connector_matches_edid], connector_is_digital? 1, monitor_is_digital? 1
>[ 1233.436532] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:DVI-D-1] probed modes :
>[ 1233.436536] [drm:drm_mode_debug_printmodeline], Modeline 48:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1233.436540] [drm:drm_mode_debug_printmodeline], Modeline 74:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1233.436544] [drm:drm_mode_debug_printmodeline], Modeline 78:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[ 1233.436549] [drm:drm_mode_debug_printmodeline], Modeline 71:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[ 1233.436553] [drm:drm_mode_debug_printmodeline], Modeline 70:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
>[ 1233.436557] [drm:drm_mode_debug_printmodeline], Modeline 77:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[ 1233.436561] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1233.436565] [drm:drm_mode_debug_printmodeline], Modeline 50:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1233.436569] [drm:drm_mode_debug_printmodeline], Modeline 73:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[ 1233.436573] [drm:drm_mode_debug_printmodeline], Modeline 72:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1233.436577] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1233.436581] [drm:drm_mode_debug_printmodeline], Modeline 76:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[ 1233.436585] [drm:drm_mode_debug_printmodeline], Modeline 69:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[ 1233.436589] [drm:drm_mode_debug_printmodeline], Modeline 67:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[ 1233.436593] [drm:drm_mode_debug_printmodeline], Modeline 66:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[ 1233.436597] [drm:drm_mode_debug_printmodeline], Modeline 49:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1233.436602] [drm:drm_mode_debug_printmodeline], Modeline 65:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[ 1233.436606] [drm:drm_mode_debug_printmodeline], Modeline 64:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
>[ 1233.436610] [drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1233.436614] [drm:drm_mode_debug_printmodeline], Modeline 63:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1233.436618] [drm:drm_mode_debug_printmodeline], Modeline 57:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1233.436622] [drm:drm_mode_debug_printmodeline], Modeline 75:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[ 1233.436626] [drm:drm_mode_debug_printmodeline], Modeline 61:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1233.436630] [drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1233.436634] [drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1233.436638] [drm:drm_mode_debug_printmodeline], Modeline 60:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1233.436642] [drm:drm_mode_debug_printmodeline], Modeline 62:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[ 1233.436646] [drm:drm_mode_debug_printmodeline], Modeline 59:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1233.436650] [drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1233.436654] [drm:drm_mode_debug_printmodeline], Modeline 53:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1233.436657] [drm:drm_mode_debug_printmodeline], Modeline 54:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1233.436673] [drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[ 1233.438232] [drm:asle_set_backlight], bclp = 0x80000025
>[ 1233.438236] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[ 1233.438239] [drm:intel_panel_actually_set_backlight], set backlight PWM = 1749397
>[ 1233.438242] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[ 1233.438248] [drm:intel_opregion_asle_intr], non asle set request??
>[ 1233.438825] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[ 1233.441739] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1233.442642] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[ 1233.445445] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1233.460026] [drm:intel_update_fbc], fbc set to per-chip default
>[ 1233.460029] [drm:intel_update_fbc], fbc disabled per module param
>[ 1233.460033] [drm:i965_update_wm], self-refresh entries: 64, wm: 448
>[ 1233.460036] [drm:i965_update_wm], self-refresh watermark: display plane 448 cursor 32
>[ 1233.460039] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 448
>[ 1233.460044] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[ 1233.461570] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00
>[ 1233.464273] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[ 1233.464277] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[ 1233.464280] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[ 1233.464282] [drm:intel_modeset_check_state], [CRTC:3]
>[ 1233.464285] [drm:intel_modeset_check_state], [CRTC:4]
>[ 1233.464321] [drm:drm_mode_setcrtc], [CRTC:3]
>[ 1233.464326] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[ 1233.464332] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:4]
>[ 1233.464340] [drm:drm_mode_setcrtc], [CRTC:4]
>[ 1233.464344] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[ 1233.464349] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [NOCRTC]
>[ 1233.464353] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 1233.464357] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 1233.464361] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 1233.464370] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[ 1233.465932] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00
>[ 1233.468696] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[ 1233.468702] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[ 1233.468707] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[ 1233.468712] [drm:intel_modeset_check_state], [CRTC:3]
>[ 1233.468716] [drm:intel_modeset_check_state], [CRTC:4]
>[ 1233.468738] [drm:drm_mode_setcrtc], [CRTC:3]
>[ 1233.468742] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[ 1233.468749] [drm:drm_mode_setcrtc], [CRTC:4]
>[ 1233.468752] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[ 1233.468932] [drm:drm_mode_setcrtc], [CRTC:3]
>[ 1233.468941] [drm:drm_mode_setcrtc], [CONNECTOR:12:VGA-1]
>[ 1233.468946] [drm:intel_crtc_set_config], [CRTC:3] [FB:81] #connectors=1 (x y) (0 0)
>[ 1233.468952] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 1233.468956] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[ 1233.468960] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1233.468967] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 78800 1024 1040 1136 1312 768 769 772 800 0x0 0x5
>[ 1233.468974] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 1233.468979] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[ 1233.468983] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 1233.468987] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[ 1233.468991] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 78800 1024 1040 1136 1312 768 769 772 800 0x0 0x5
>[ 1233.468998] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 1233.469008] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[ 1233.469465] [drm:i9xx_crtc_mode_set], Mode for pipe A:
>[ 1233.469468] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 78800 1024 1040 1136 1312 768 769 772 800 0x0 0x5
>[ 1233.484025] [drm:i9xx_update_plane], Writing base 01012000 00000000 0 0 4096
>[ 1233.484031] [drm:intel_update_fbc], fbc set to per-chip default
>[ 1233.484034] [drm:intel_update_fbc], fbc disabled per module param
>[ 1233.484037] [drm:i965_update_wm], self-refresh entries: 64, wm: 448
>[ 1233.484039] [drm:i965_update_wm], self-refresh watermark: display plane 448 cursor 32
>[ 1233.484042] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 448
>[ 1233.484045] [drm:intel_crtc_mode_set], [ENCODER:13:DAC-13] set [MODE:82:]
>[ 1233.484049] [drm:i965_update_wm], self-refresh entries: 64, wm: 448
>[ 1233.484051] [drm:i965_update_wm], self-refresh watermark: display plane 448 cursor 32
>[ 1233.484054] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 448
>[ 1233.500041] [drm:intel_update_fbc], fbc set to per-chip default
>[ 1233.500049] [drm:intel_update_fbc], fbc disabled per module param
>[ 1233.500070] [drm:intel_connector_check_state], [CONNECTOR:12:VGA-1]
>[ 1233.500079] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[ 1233.501725] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00
>[ 1233.504624] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[ 1233.504632] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[ 1233.504640] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[ 1233.504647] [drm:intel_modeset_check_state], [CRTC:3]
>[ 1233.504653] [drm:intel_modeset_check_state], [CRTC:4]
>[ 1233.504717] [drm:drm_mode_setcrtc], [CRTC:4]
>[ 1233.504724] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[ 1233.504732] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[ 1233.505366] [drm:asle_set_backlight], bclp = 0x80000025
>[ 1233.505370] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[ 1233.505373] [drm:intel_panel_actually_set_backlight], set backlight PWM = 1749397
>[ 1233.505376] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[ 1233.505381] [drm:intel_opregion_asle_intr], non asle set request??
>[ 1233.505940] [drm:drm_mode_setcrtc], [CRTC:4]
>[ 1233.505943] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[ 1233.505947] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[ 1233.505952] [drm:drm_mode_setcrtc], [CRTC:4]
>[ 1233.505955] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[ 1233.505958] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[ 1243.175672] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[ 1243.175681] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[ 1243.175684] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[ 1243.175689] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[ 1243.175692] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[ 1243.175694] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[ 1243.175708] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[ 1243.175711] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1]
>[ 1243.188041] [drm:intel_crt_detect], CRT not detected via hotplug
>[ 1243.272044] [drm:intel_crt_detect_ddc], CRT detected via DDC:0x50 [EDID]
>[ 1243.356136] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[ 1243.356202] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1] probed modes :
>[ 1243.356210] [drm:drm_mode_debug_printmodeline], Modeline 16:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1243.356222] [drm:drm_mode_debug_printmodeline], Modeline 42:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 1243.356232] [drm:drm_mode_debug_printmodeline], Modeline 46:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[ 1243.356242] [drm:drm_mode_debug_printmodeline], Modeline 39:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[ 1243.356253] [drm:drm_mode_debug_printmodeline], Modeline 38:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[ 1243.356263] [drm:drm_mode_debug_printmodeline], Modeline 45:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[ 1243.356273] [drm:drm_mode_debug_printmodeline], Modeline 23:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1243.356283] [drm:drm_mode_debug_printmodeline], Modeline 18:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1243.356293] [drm:drm_mode_debug_printmodeline], Modeline 41:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[ 1243.356303] [drm:drm_mode_debug_printmodeline], Modeline 40:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[ 1243.356313] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1243.356323] [drm:drm_mode_debug_printmodeline], Modeline 44:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[ 1243.356333] [drm:drm_mode_debug_printmodeline], Modeline 37:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[ 1243.356343] [drm:drm_mode_debug_printmodeline], Modeline 35:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[ 1243.356354] [drm:drm_mode_debug_printmodeline], Modeline 34:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[ 1243.356364] [drm:drm_mode_debug_printmodeline], Modeline 17:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1243.356374] [drm:drm_mode_debug_printmodeline], Modeline 33:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[ 1243.356384] [drm:drm_mode_debug_printmodeline], Modeline 32:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[ 1243.356394] [drm:drm_mode_debug_printmodeline], Modeline 24:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1243.356404] [drm:drm_mode_debug_printmodeline], Modeline 31:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1243.356414] [drm:drm_mode_debug_printmodeline], Modeline 25:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1243.356424] [drm:drm_mode_debug_printmodeline], Modeline 43:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[ 1243.356434] [drm:drm_mode_debug_printmodeline], Modeline 29:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1243.356444] [drm:drm_mode_debug_printmodeline], Modeline 26:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1243.356454] [drm:drm_mode_debug_printmodeline], Modeline 19:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1243.356463] [drm:drm_mode_debug_printmodeline], Modeline 28:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1243.356473] [drm:drm_mode_debug_printmodeline], Modeline 30:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[ 1243.356483] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1243.356493] [drm:drm_mode_debug_printmodeline], Modeline 20:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1243.356503] [drm:drm_mode_debug_printmodeline], Modeline 21:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1243.356513] [drm:drm_mode_debug_printmodeline], Modeline 22:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1243.356563] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[ 1243.364041] [drm:intel_crt_detect], CRT not detected via hotplug
>[ 1243.448034] [drm:intel_crt_detect_ddc], CRT detected via DDC:0x50 [EDID]
>[ 1243.448044] [drm:output_poll_execute], [CONNECTOR:12:VGA-1] status updated from 1 to 1
>[ 1243.448055] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[ 1243.449703] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[ 1243.452631] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[ 1243.452640] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1243.455909] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1243.484481] [drm:output_poll_execute], [CONNECTOR:15:DVI-D-1] status updated from 1 to 1
>[ 1243.484573] [drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[ 1243.484577] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:DVI-D-1]
>[ 1243.484584] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[ 1243.486110] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[ 1243.488796] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[ 1243.488808] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1243.491850] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1243.520365] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1243.523412] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1243.552081] [drm:intel_sdvo_connector_matches_edid], connector_is_digital? 1, monitor_is_digital? 1
>[ 1243.552160] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:DVI-D-1] probed modes :
>[ 1243.552164] [drm:drm_mode_debug_printmodeline], Modeline 48:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1243.552169] [drm:drm_mode_debug_printmodeline], Modeline 74:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 1243.552173] [drm:drm_mode_debug_printmodeline], Modeline 78:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[ 1243.552177] [drm:drm_mode_debug_printmodeline], Modeline 71:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[ 1243.552181] [drm:drm_mode_debug_printmodeline], Modeline 70:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
>[ 1243.552185] [drm:drm_mode_debug_printmodeline], Modeline 77:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[ 1243.552190] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1243.552194] [drm:drm_mode_debug_printmodeline], Modeline 50:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1243.552198] [drm:drm_mode_debug_printmodeline], Modeline 73:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[ 1243.552202] [drm:drm_mode_debug_printmodeline], Modeline 72:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 1243.552206] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 1243.552210] [drm:drm_mode_debug_printmodeline], Modeline 76:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[ 1243.552214] [drm:drm_mode_debug_printmodeline], Modeline 69:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[ 1243.552218] [drm:drm_mode_debug_printmodeline], Modeline 67:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[ 1243.552222] [drm:drm_mode_debug_printmodeline], Modeline 66:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[ 1243.552227] [drm:drm_mode_debug_printmodeline], Modeline 49:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1243.552231] [drm:drm_mode_debug_printmodeline], Modeline 65:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[ 1243.552235] [drm:drm_mode_debug_printmodeline], Modeline 64:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
>[ 1243.552239] [drm:drm_mode_debug_printmodeline], Modeline 56:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1243.552243] [drm:drm_mode_debug_printmodeline], Modeline 63:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 1243.552247] [drm:drm_mode_debug_printmodeline], Modeline 57:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1243.552251] [drm:drm_mode_debug_printmodeline], Modeline 75:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[ 1243.552255] [drm:drm_mode_debug_printmodeline], Modeline 61:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 1243.552259] [drm:drm_mode_debug_printmodeline], Modeline 58:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1243.552263] [drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1243.552267] [drm:drm_mode_debug_printmodeline], Modeline 60:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 1243.552271] [drm:drm_mode_debug_printmodeline], Modeline 62:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[ 1243.552274] [drm:drm_mode_debug_printmodeline], Modeline 59:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 1243.552278] [drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1243.552282] [drm:drm_mode_debug_printmodeline], Modeline 53:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1243.552286] [drm:drm_mode_debug_printmodeline], Modeline 54:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1243.552303] [drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[ 1243.558758] [drm:drm_mode_setcrtc], [CRTC:3]
>[ 1243.558764] [drm:drm_mode_setcrtc], [CONNECTOR:12:VGA-1]
>[ 1243.558767] [drm:drm_mode_setcrtc], [CONNECTOR:15:DVI-D-1]
>[ 1243.558770] [drm:intel_crtc_set_config], [CRTC:3] [FB:81] #connectors=2 (x y) (0 0)
>[ 1243.558774] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 1243.558777] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[ 1243.558780] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[ 1243.558783] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 1243.558785] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[ 1243.558787] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 78800 1024 1040 1136 1312 768 769 772 800 0x0 0x5
>[ 1243.558792] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 1243.558796] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[ 1243.604027] [drm:intel_update_fbc], fbc set to per-chip default
>[ 1243.604031] [drm:intel_update_fbc], fbc disabled per module param
>[ 1243.604035] [drm:i965_update_wm], self-refresh entries: 64, wm: 448
>[ 1243.604039] [drm:i965_update_wm], self-refresh watermark: display plane 448 cursor 32
>[ 1243.604042] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 448
>[ 1243.604538] [drm:i9xx_crtc_mode_set], Mode for pipe A:
>[ 1243.604541] [drm:drm_mode_debug_printmodeline], Modeline 82:"" 0 78800 1024 1040 1136 1312 768 769 772 800 0x0 0x5
>[ 1243.620035] [drm:i9xx_update_plane], Writing base 01012000 00000000 0 0 4096
>[ 1243.620045] [drm:intel_update_fbc], fbc set to per-chip default
>[ 1243.620048] [drm:intel_update_fbc], fbc disabled per module param
>[ 1243.620052] [drm:i965_update_wm], self-refresh entries: 64, wm: 448
>[ 1243.620055] [drm:i965_update_wm], self-refresh watermark: display plane 448 cursor 32
>[ 1243.620059] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 448
>[ 1243.620063] [drm:intel_crtc_mode_set], [ENCODER:13:DAC-13] set [MODE:82:]
>[ 1243.620067] [drm:intel_crtc_mode_set], [ENCODER:14:TMDS-14] set [MODE:82:]
>[ 1243.620076] [drm:intel_sdvo_debug_write], SDVOB: W: 07 01 00 00 00             (SDVO_CMD_SET_IN_OUT_MAP)
>[ 1243.624158] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1243.625078] [drm:intel_sdvo_debug_write], SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>[ 1243.627877] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1243.628795] [drm:intel_sdvo_debug_write], SDVOB: W: 16 C8 1E 00 20 41 00 20 30 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>[ 1243.635386] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1243.636294] [drm:intel_sdvo_debug_write], SDVOB: W: 17 10 60 13 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>[ 1243.642915] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1243.643805] [drm:intel_sdvo_debug_write], SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>[ 1243.645981] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1243.646878] [drm:intel_sdvo_debug_write], SDVOB: W: 9F 00                      (SDVO_CMD_SET_ENCODE)
>[ 1243.649049] [drm:intel_sdvo_read_response], SDVOB: R: (Not supported)... failed
>[ 1243.649947] [drm:intel_sdvo_debug_write], SDVOB: W: 14 C8 1E 00 20 41 00 20 30 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>[ 1243.656543] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1243.657457] [drm:intel_sdvo_debug_write], SDVOB: W: 15 10 60 13 00 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>[ 1243.664068] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1243.664957] [drm:intel_sdvo_debug_write], SDVOB: W: 21 02                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>[ 1243.667118] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1243.668020] [drm:i965_update_wm], self-refresh entries: 64, wm: 448
>[ 1243.668028] [drm:i965_update_wm], self-refresh watermark: display plane 448 cursor 32
>[ 1243.668030] [drm:i965_update_wm], Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 448
>[ 1243.676022] [drm:intel_update_fbc], fbc set to per-chip default
>[ 1243.676024] [drm:intel_update_fbc], fbc disabled per module param
>[ 1243.692022] [drm:intel_sdvo_debug_write], SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>[ 1243.693550] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01
>[ 1243.695326] [drm:intel_sdvo_debug_write], SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>[ 1243.698130] [drm:intel_sdvo_read_response], SDVOB: R: (Success)
>[ 1243.699236] [drm:intel_connector_check_state], [CONNECTOR:12:VGA-1]
>[ 1243.699239] [drm:intel_sdvo_debug_write], SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>[ 1243.700782] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[ 1243.703452] [drm:intel_connector_check_state], [CONNECTOR:15:DVI-D-1]
>[ 1243.703456] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[ 1243.703459] [drm:intel_modeset_check_state], [ENCODER:13:DAC-13]
>[ 1243.703462] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14]
>[ 1243.703465] [drm:intel_modeset_check_state], [CRTC:3]
>[ 1243.703467] [drm:intel_modeset_check_state], [CRTC:4]
>[ 1243.703498] [drm:drm_mode_setcrtc], [CRTC:4]
>[ 1243.703501] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[ 1243.703505] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[ 1243.703508] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[ 1243.703984] [drm:asle_set_backlight], bclp = 0x80000025
>[ 1243.703988] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[ 1243.703991] [drm:intel_panel_actually_set_backlight], set backlight PWM = 1749397
>[ 1243.703995] [drm:intel_panel_get_max_backlight], max backlight PWM = 12056655
>[ 1243.704000] [drm:intel_opregion_asle_intr], non asle set request??
>[ 1243.705078] [drm:drm_mode_setcrtc], [CRTC:4]
>[ 1243.705082] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[ 1243.705086] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[ 1243.705089] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[ 1243.705096] [drm:drm_mode_setcrtc], [CRTC:4]
>[ 1243.705099] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[ 1243.705102] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:VGA-1] to [CRTC:3]
>[ 1243.705105] [drm:intel_modeset_stage_output_state], [CONNECTOR:15:DVI-D-1] to [CRTC:3]
>[ 1253.544050] [drm:intel_crt_detect], CRT not detected via hotplug
>[ 1253.628034] [drm:intel_crt_detect_ddc], CRT detected via DDC:0x50 [EDID]
>[ 1253.628045] [drm:output_poll_execute], [CONNECTOR:12:VGA-1] status updated from 1 to 1
>[ 1253.628055] [drm:intel_sdvo_debug_write], SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>[ 1253.629704] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00
>[ 1253.632617] [drm:intel_sdvo_detect], SDVO response 1 0 [1]
>[ 1253.632627] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1253.635891] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>[ 1253.666186] [drm:output_poll_execute], [CONNECTOR:15:DVI-D-1] status updated from 1 to 1

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Attachments on bug 29259: 37820 | 70007 | 70009

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