Attachment 71928 Details for Bug 58615 – dmesg after X start and launching gears

dmesg after X start and launching gears

dmesg-3.7-nv-gears.log (text/plain), 233.61 KB, created by Andrew Randrianasulu on 2012-12-21 13:16:29 UTC

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Creator: Andrew Randrianasulu

Created: 2012-12-21 13:16:29 UTC

Size: 233.61 KB

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>Linux version 3.7.0-small-00147-ga6f3b00 (guest@slax6) (gcc version 4.7.1 (GCC) ) #34 Fri Dec 21 11:51:41 GMT 2012
>KERNEL supported cpus:
>  Intel GenuineIntel
>  AMD AuthenticAMD
>  NSC Geode by NSC
>  Cyrix CyrixInstead
>  Centaur CentaurHauls
>  Transmeta GenuineTMx86
>  Transmeta TransmetaCPU
>  UMC UMC UMC UMC
>e820: BIOS-provided physical RAM map:
>BIOS-e820: [mem 0x0000000000000000-0x000000000009fbff] usable
>BIOS-e820: [mem 0x000000000009fc00-0x000000000009ffff] reserved
>BIOS-e820: [mem 0x00000000000dc000-0x00000000000dffff] reserved
>BIOS-e820: [mem 0x00000000000f0000-0x00000000000fffff] reserved
>BIOS-e820: [mem 0x0000000000100000-0x000000001ffeffff] usable
>BIOS-e820: [mem 0x000000001fff0000-0x000000001fff7fff] ACPI data
>BIOS-e820: [mem 0x000000001fff8000-0x000000001fffffff] ACPI NVS
>BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
>BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
>BIOS-e820: [mem 0x00000000ffff0000-0x00000000ffffffff] reserved
>Notice: NX (Execute Disable) protection missing in CPU!
>DMI 2.3 present.
>DMI:                  /6VTX, BIOS 6.27.10 08/08/2001
>e820: update [mem 0x00000000-0x0000ffff] usable ==> reserved
>e820: remove [mem 0x000a0000-0x000fffff] usable
>e820: last_pfn = 0x1fff0 max_arch_pfn = 0x100000
>MTRR default type: uncachable
>MTRR fixed ranges enabled:
>  00000-9FFFF write-back
>  A0000-BFFFF uncachable
>  C0000-CBFFF write-protect
>  CC000-FFFFF uncachable
>MTRR variable ranges enabled:
>  0 base 000000000 mask FE0000000 write-back
>  1 disabled
>  2 disabled
>  3 disabled
>  4 disabled
>  5 disabled
>  6 base 0E0000000 mask FFF000000 write-combining
>  7 disabled
>PAT not supported by CPU.
>found SMP MP-table at [mem 0x000fb210-0x000fb21f] mapped at [c00fb210]
>initial memory mapped: [mem 0x00000000-0x007fffff]
>Base memory trampoline at [c009b000] 9b000 size 16384
>init_memory_mapping: [mem 0x00000000-0x1ffeffff]
> [mem 0x00000000-0x003fffff] page 4k
> [mem 0x00400000-0x1fbfffff] page 2M
> [mem 0x1fc00000-0x1ffeffff] page 4k
>kernel direct mapping tables up to 0x1ffeffff @ [mem 0x007fa000-0x007fffff]
>early_memtest: # of tests: 17
>  0000010000 - 000009b000 pattern 0000000000000000
>  00003f70f4 - 00007fa000 pattern 0000000000000000
>  00007fb000 - 001fff0000 pattern 0000000000000000
>  0000010000 - 000009b000 pattern ffffffffffffffff
>  00003f70f4 - 00007fa000 pattern ffffffffffffffff
>  00007fb000 - 001fff0000 pattern ffffffffffffffff
>  0000010000 - 000009b000 pattern 5555555555555555
>  00003f70f4 - 00007fa000 pattern 5555555555555555
>  00007fb000 - 001fff0000 pattern 5555555555555555
>  0000010000 - 000009b000 pattern aaaaaaaaaaaaaaaa
>  00003f70f4 - 00007fa000 pattern aaaaaaaaaaaaaaaa
>  00007fb000 - 001fff0000 pattern aaaaaaaaaaaaaaaa
>  0000010000 - 000009b000 pattern 1111111111111111
>  00003f70f4 - 00007fa000 pattern 1111111111111111
>  00007fb000 - 001fff0000 pattern 1111111111111111
>  0000010000 - 000009b000 pattern 2222222222222222
>  00003f70f4 - 00007fa000 pattern 2222222222222222
>  00007fb000 - 001fff0000 pattern 2222222222222222
>  0000010000 - 000009b000 pattern 4444444444444444
>  00003f70f4 - 00007fa000 pattern 4444444444444444
>  00007fb000 - 001fff0000 pattern 4444444444444444
>  0000010000 - 000009b000 pattern 8888888888888888
>  00003f70f4 - 00007fa000 pattern 8888888888888888
>  00007fb000 - 001fff0000 pattern 8888888888888888
>  0000010000 - 000009b000 pattern 3333333333333333
>  00003f70f4 - 00007fa000 pattern 3333333333333333
>  00007fb000 - 001fff0000 pattern 3333333333333333
>  0000010000 - 000009b000 pattern 6666666666666666
>  00003f70f4 - 00007fa000 pattern 6666666666666666
>  00007fb000 - 001fff0000 pattern 6666666666666666
>  0000010000 - 000009b000 pattern 9999999999999999
>  00003f70f4 - 00007fa000 pattern 9999999999999999
>  00007fb000 - 001fff0000 pattern 9999999999999999
>  0000010000 - 000009b000 pattern cccccccccccccccc
>  00003f70f4 - 00007fa000 pattern cccccccccccccccc
>  00007fb000 - 001fff0000 pattern cccccccccccccccc
>  0000010000 - 000009b000 pattern 7777777777777777
>  00003f70f4 - 00007fa000 pattern 7777777777777777
>  00007fb000 - 001fff0000 pattern 7777777777777777
>  0000010000 - 000009b000 pattern bbbbbbbbbbbbbbbb
>  00003f70f4 - 00007fa000 pattern bbbbbbbbbbbbbbbb
>  00007fb000 - 001fff0000 pattern bbbbbbbbbbbbbbbb
>  0000010000 - 000009b000 pattern dddddddddddddddd
>  00003f70f4 - 00007fa000 pattern dddddddddddddddd
>  00007fb000 - 001fff0000 pattern dddddddddddddddd
>  0000010000 - 000009b000 pattern eeeeeeeeeeeeeeee
>  00003f70f4 - 00007fa000 pattern eeeeeeeeeeeeeeee
>  00007fb000 - 001fff0000 pattern eeeeeeeeeeeeeeee
>  0000010000 - 000009b000 pattern 4c494e5558726c7a
>  00003f70f4 - 00007fa000 pattern 4c494e5558726c7a
>  00007fb000 - 001fff0000 pattern 4c494e5558726c7a
>early_memtest: wipe out test pattern from memory
>  0000010000 - 000009b000 pattern 0000000000000000
>  00003f70f4 - 00007fa000 pattern 0000000000000000
>  00007fb000 - 001fff0000 pattern 0000000000000000
>log_buf_len: 4194304
>early log buf free: 26096(79%)
>ACPI: RSDP 000fc550 00014 (v00 AMI   )
>ACPI: RSDT 1fff0000 0002C (v01 AMIINT VIA_P6   00000010 MSFT 00000097)
>ACPI: FACP 1fff0030 00074 (v01 AMIINT VIA_P6   00000011 MSFT 00000097)
>ACPI: DSDT 1fff0110 02EA1 (v01    VIA APOLLO-P 00001000 MSFT 0100000B)
>ACPI: FACS 1fff8000 00040
>ACPI: APIC 1fff00b0 00054 (v01 AMIINT          00000009 MSFT 00000097)
>ACPI: Local APIC address 0xfee00000
>511MB LOWMEM available.
>  mapped low ram: 0 - 1fff0000
>  low ram: 0 - 1fff0000
>Zone ranges:
>  DMA      [mem 0x00010000-0x00ffffff]
>  Normal   [mem 0x01000000-0x1ffeffff]
>Movable zone start for each node
>Early memory node ranges
>  node   0: [mem 0x00010000-0x0009efff]
>  node   0: [mem 0x00100000-0x1ffeffff]
>On node 0 totalpages: 130943
>free_area_init_node: node 0, pgdat c03850dc, node_mem_map df7f0200
>  DMA zone: 32 pages used for memmap
>  DMA zone: 0 pages reserved
>  DMA zone: 3951 pages, LIFO batch:0
>  Normal zone: 992 pages used for memmap
>  Normal zone: 125968 pages, LIFO batch:31
>Using APIC driver default
>ACPI: PM-Timer IO Port: 0x808
>ACPI: Local APIC address 0xfee00000
>ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
>ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
>IOAPIC[0]: apic_id 2, version 17, address 0xfec00000, GSI 0-23
>ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
>ACPI: IRQ0 used by override.
>ACPI: IRQ2 used by override.
>ACPI: IRQ9 used by override.
>Using ACPI (MADT) for SMP configuration information
>nr_irqs_gsi: 40
>PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
>PM: Registered nosave memory: 00000000000a0000 - 00000000000dc000
>PM: Registered nosave memory: 00000000000dc000 - 00000000000e0000
>PM: Registered nosave memory: 00000000000e0000 - 00000000000f0000
>PM: Registered nosave memory: 00000000000f0000 - 0000000000100000
>e820: [mem 0x20000000-0xfebfffff] available for PCI devices
>pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
>pcpu-alloc: [0] 0 
>Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 129919
>Kernel command line: BOOT_IMAGE=lin-3.7-nv root=302 vt.default_utf8=0 memtest resume=/dev/hda3 log-buf-len=4M nouveau.debug=paranoia
>PID hash table entries: 2048 (order: 1, 8192 bytes)
>Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
>Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
>__ex_table already sorted, skipping sort
>Initializing CPU#0
>Memory: 512084k/524224k available (1963k kernel code, 11688k reserved, 627k data, 320k init, 0k highmem)
>virtual kernel memory layout:
>    fixmap  : 0xfffa2000 - 0xfffff000   ( 372 kB)
>    vmalloc : 0xe07f0000 - 0xfffa0000   ( 503 MB)
>    lowmem  : 0xc0000000 - 0xdfff0000   ( 511 MB)
>      .init : 0xc0388000 - 0xc03d8000   ( 320 kB)
>      .data : 0xc02eadeb - 0xc0387bc0   ( 627 kB)
>      .text : 0xc0100000 - 0xc02eadeb   (1963 kB)
>Checking if this processor honours the WP bit even in supervisor mode...Ok.
>SLUB: Genslabs=15, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
>NR_IRQS:2304 nr_irqs:256 16
>CPU 0 irqstacks, hard=df008000 soft=df00a000
>Console: colour VGA+ 80x25
>console [tty0] enabled
>tsc: Fast TSC calibration using PIT
>tsc: Detected 1000.033 MHz processor
>Calibrating delay loop (skipped), value calculated using timer frequency.. 2000.06 BogoMIPS (lpj=4000132)
>pid_max: default: 4096 minimum: 301
>Mount-cache hash table entries: 512
>mce: CPU supports 5 MCE banks
>Last level iTLB entries: 4KB 32, 2MB 0, 4MB 2
>Last level dTLB entries: 4KB 64, 2MB 0, 4MB 8
>tlb_flushall_shift: 6
>CPU: Intel(R) Celeron(TM) CPU                1000MHz (fam: 06, model: 0b, stepping: 01)
>ACPI: Core revision 20120913
>Performance Events: p6 PMU driver.
>... version:                0
>... bit width:              32
>... generic registers:      2
>... value mask:             00000000ffffffff
>... max period:             000000007fffffff
>... fixed-purpose events:   0
>... event mask:             0000000000000003
>Enabling APIC mode:  Flat.  Using 1 I/O APICs
>..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>PM: Registering ACPI NVS region [mem 0x1fff8000-0x1fffffff] (32768 bytes)
>NET: Registered protocol family 16
>ACPI: bus type pci registered
>PCI: PCI BIOS revision 2.10 entry at 0xfdac1, last bus=1
>PCI: Using configuration type 1 for base access
>bio: create slab <bio-0> at 0
>ACPI: Added _OSI(Module Device)
>ACPI: Added _OSI(Processor Device)
>ACPI: Added _OSI(3.0 _SCP Extensions)
>ACPI: Added _OSI(Processor Aggregator Device)
>ACPI: EC: Look up EC in DSDT
>ACPI: Interpreter enabled
>ACPI: (supports S0 S3 S4 S5)
>ACPI: Using IOAPIC for interrupt routing
>ACPI: Power Resource [URP1] (off)
>ACPI: Power Resource [URP2] (off)
>ACPI: Power Resource [FDDP] (off)
>ACPI: Power Resource [LPTP] (off)
>PCI: Ignoring host bridge windows from ACPI; if necessary, use "pci=use_crs" and report a bug
>ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
>pci_root PNP0A03:00: host bridge window [io  0x0000-0x0cf7] (ignored)
>pci_root PNP0A03:00: host bridge window [io  0x0d00-0xffff] (ignored)
>pci_root PNP0A03:00: host bridge window [mem 0x000a0000-0x000bffff] (ignored)
>pci_root PNP0A03:00: host bridge window [mem 0x000c0000-0x000dffff] (ignored)
>pci_root PNP0A03:00: host bridge window [mem 0x20000000-0xffdfffff] (ignored)
>pci_root PNP0A03:00: host bridge window [mem 0xfee01000-0xffdfffff] (ignored)
>PCI: root bus 00: using default resources
>pci_root PNP0A03:00: fail to add MMCONFIG information, can't access extended PCI configuration space under this bridge.
>PCI host bridge to bus 0000:00
>pci_bus 0000:00: root bus resource [bus 00-ff]
>pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
>pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
>pci 0000:00:00.0: [1106:0691] type 00 class 0x060000
>pci 0000:00:00.0: reg 10: [mem 0xe0000000-0xe0ffffff pref]
>pci 0000:00:01.0: [1106:8598] type 01 class 0x060400
>pci 0000:00:01.0: supports D1
>pci 0000:00:07.0: [1106:0686] type 00 class 0x060100
>pci 0000:00:07.1: [1106:0571] type 00 class 0x01018a
>pci 0000:00:07.1: reg 20: [io  0xffa0-0xffaf]
>pci 0000:00:07.2: [1106:3038] type 00 class 0x0c0300
>pci 0000:00:07.2: reg 20: [io  0xbc00-0xbc1f]
>pci 0000:00:07.4: [1106:3057] type 00 class 0x0c0500
>pci 0000:00:07.4: quirk: [io  0x0c00-0x0c7f] claimed by vt82c686 HW-mon
>pci 0000:00:07.4: quirk: [io  0x0400-0x040f] claimed by vt82c686 SMB
>pci 0000:00:07.5: [1106:3058] type 00 class 0x040100
>pci 0000:00:07.5: reg 10: [io  0xc800-0xc8ff]
>pci 0000:00:07.5: reg 14: [io  0xc400-0xc403]
>pci 0000:00:07.5: reg 18: [io  0xc000-0xc003]
>pci 0000:00:0a.0: [10b9:5237] type 00 class 0x0c0310
>pci 0000:00:0a.0: reg 10: [mem 0xdfffc000-0xdfffcfff]
>pci 0000:00:0a.0: PME# supported from D0 D1 D3hot D3cold
>pci 0000:00:0a.1: [10b9:5237] type 00 class 0x0c0310
>pci 0000:00:0a.1: reg 10: [mem 0xdfffd000-0xdfffdfff]
>pci 0000:00:0a.1: PME# supported from D0 D1 D3hot D3cold
>pci 0000:00:0a.2: [10b9:5237] type 00 class 0x0c0310
>pci 0000:00:0a.2: reg 10: [mem 0xdfffe000-0xdfffefff]
>pci 0000:00:0a.2: PME# supported from D0 D1 D3hot D3cold
>pci 0000:00:0a.3: [10b9:5239] type 00 class 0x0c0320
>pci 0000:00:0a.3: reg 10: [mem 0xdffffb00-0xdffffbff]
>pci 0000:00:0a.3: PME# supported from D0 D3hot D3cold
>pci 0000:00:0b.0: [1186:1300] type 00 class 0x020000
>pci 0000:00:0b.0: reg 10: [io  0xb800-0xb8ff]
>pci 0000:00:0b.0: reg 14: [mem 0xdffffa00-0xdffffaff]
>pci 0000:00:0b.0: supports D1 D2
>pci 0000:00:0b.0: PME# supported from D1 D2 D3hot D3cold
>pci 0000:00:0d.0: [1095:3114] type 00 class 0x010400
>pci 0000:00:0d.0: reg 10: [io  0xdc00-0xdc07]
>pci 0000:00:0d.0: reg 14: [io  0xd800-0xd803]
>pci 0000:00:0d.0: reg 18: [io  0xd400-0xd407]
>pci 0000:00:0d.0: reg 1c: [io  0xd000-0xd003]
>pci 0000:00:0d.0: reg 20: [io  0xcc00-0xcc0f]
>pci 0000:00:0d.0: reg 24: [mem 0xdffffc00-0xdfffffff]
>pci 0000:00:0d.0: reg 30: [mem 0xdff00000-0xdff7ffff pref]
>pci 0000:00:0d.0: supports D1 D2
>pci 0000:01:00.0: [10de:00f1] type 00 class 0x030000
>pci 0000:01:00.0: reg 10: [mem 0xde000000-0xdeffffff]
>pci 0000:01:00.0: reg 14: [mem 0xc0000000-0xcfffffff pref]
>pci 0000:01:00.0: reg 18: [mem 0xdd000000-0xddffffff]
>pci 0000:01:00.0: reg 30: [mem 0xdfde0000-0xdfdfffff pref]
>pci 0000:00:01.0: PCI bridge to [bus 01]
>pci 0000:00:01.0:   bridge window [io  0x7000-0x7fff]
>pci 0000:00:01.0:   bridge window [mem 0xdbd00000-0xdfdfffff]
>pci 0000:00:01.0:   bridge window [mem 0xbbb00000-0xdbbfffff pref]
>pci_bus 0000:00: on NUMA node 0
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
> pci0000:00: Unable to request _OSC control (_OSC support mask: 0x08)
>ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 *11 12 14 15)
>ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *10 11 12 14 15)
>ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 11 12 14 15) *9
>ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 *5 6 7 10 11 12 14 15)
>vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=io+mem,locks=none
>vgaarb: loaded
>vgaarb: bridge control possible 0000:01:00.0
>PCI: Using ACPI for IRQ routing
>PCI: pci_cache_line_size set to 32 bytes
>e820: reserve RAM buffer [mem 0x0009fc00-0x0009ffff]
>e820: reserve RAM buffer [mem 0x1fff0000-0x1fffffff]
>Switching to clocksource refined-jiffies
>pnp: PnP ACPI init
>ACPI: bus type pnp registered
>pnp 00:00: [bus 00-ff]
>pnp 00:00: [io  0x0cf8-0x0cff]
>pnp 00:00: [io  0x0000-0x0cf7 window]
>pnp 00:00: [io  0x0d00-0xffff window]
>pnp 00:00: [mem 0x000a0000-0x000bffff window]
>pnp 00:00: [mem 0x000c0000-0x000dffff window]
>pnp 00:00: [mem 0x20000000-0xffdfffff window]
>pnp 00:00: [mem 0xfee01000-0xffdfffff window]
>pnp 00:00: Plug and Play ACPI device, IDs PNP0a03 (active)
>pnp 00:01: [dma 4]
>pnp 00:01: [io  0x0000-0x000f]
>pnp 00:01: [io  0x0081-0x0083]
>pnp 00:01: [io  0x0087]
>pnp 00:01: [io  0x0089-0x008b]
>pnp 00:01: [io  0x008f]
>pnp 00:01: [io  0x00c0-0x00df]
>pnp 00:01: Plug and Play ACPI device, IDs PNP0200 (active)
>pnp 00:02: [io  0x0070-0x0071]
>pnp 00:02: [irq 8]
>pnp 00:02: Plug and Play ACPI device, IDs PNP0b00 (active)
>pnp 00:03: [io  0x0061]
>pnp 00:03: Plug and Play ACPI device, IDs PNP0800 (active)
>pnp 00:04: [io  0x00f0-0x00ff]
>pnp 00:04: [irq 13]
>pnp 00:04: Plug and Play ACPI device, IDs PNP0c04 (active)
>pnp 00:05: [io  0x0060]
>pnp 00:05: [io  0x0064]
>pnp 00:05: [irq 12]
>pnp 00:05: Plug and Play ACPI device, IDs PNP0f13 (active)
>pnp 00:06: [io  0x03f2-0x03f5]
>pnp 00:06: [io  0x03f7]
>pnp 00:06: [irq 6]
>pnp 00:06: [dma 2]
>pnp 00:06: Plug and Play ACPI device, IDs PNP0700 (active)
>pnp 00:07: [io  0x03f8-0x03ff]
>pnp 00:07: [irq 4]
>pnp 00:07: Plug and Play ACPI device, IDs PNP0501 (active)
>pnp 00:08: [io  0x02f8-0x02ff]
>pnp 00:08: [irq 3]
>pnp 00:08: Plug and Play ACPI device, IDs PNP0501 (active)
>pnp 00:09: [mem 0x00000000-0x0009ffff]
>pnp 00:09: [mem 0x000f0000-0x000fffff]
>pnp 00:09: [mem 0x00100000-0x1fffffff]
>pnp 00:09: [mem 0xfec00000-0xfec00fff]
>pnp 00:09: [mem 0xfee00000-0xfee00fff]
>pnp 00:09: [mem 0xfff80000-0xffffffff]
>system 00:09: [mem 0x00000000-0x0009ffff] could not be reserved
>system 00:09: [mem 0x000f0000-0x000fffff] could not be reserved
>system 00:09: [mem 0x00100000-0x1fffffff] could not be reserved
>system 00:09: [mem 0xfec00000-0xfec00fff] could not be reserved
>system 00:09: [mem 0xfee00000-0xfee00fff] has been reserved
>system 00:09: [mem 0xfff80000-0xffffffff] could not be reserved
>system 00:09: Plug and Play ACPI device, IDs PNP0c01 (active)
>pnp: PnP ACPI: found 10 devices
>ACPI: ACPI bus type pnp unregistered
>Switching to clocksource acpi_pm
>pci 0000:00:01.0: PCI bridge to [bus 01]
>pci 0000:00:01.0:   bridge window [io  0x7000-0x7fff]
>pci 0000:00:01.0:   bridge window [mem 0xdbd00000-0xdfdfffff]
>pci 0000:00:01.0:   bridge window [mem 0xbbb00000-0xdbbfffff pref]
>pci 0000:00:01.0: setting latency timer to 64
>pci_bus 0000:00: resource 4 [io  0x0000-0xffff]
>pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
>pci_bus 0000:01: resource 0 [io  0x7000-0x7fff]
>pci_bus 0000:01: resource 1 [mem 0xdbd00000-0xdfdfffff]
>pci_bus 0000:01: resource 2 [mem 0xbbb00000-0xdbbfffff pref]
>NET: Registered protocol family 2
>TCP established hash table entries: 16384 (order: 5, 131072 bytes)
>TCP bind hash table entries: 16384 (order: 4, 65536 bytes)
>TCP: Hash tables configured (established 16384 bind 16384)
>TCP: reno registered
>UDP hash table entries: 256 (order: 0, 4096 bytes)
>UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
>NET: Registered protocol family 1
>pci 0000:00:01.0: disabling DAC on VIA PCI bridge
>pci 0000:00:07.0: Enabling VIA external APIC routing
>ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 11
>pci 0000:00:07.2: VIA VLink IRQ fixup, from 5 to 11
>pci 0000:01:00.0: Boot video device
>PCI: CLS 32 bytes, default 32
>VFS: Disk quotas dquot_6.5.2
>Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
>msgmni has been set to 1000
>Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
>io scheduler noop registered
>io scheduler cfq registered (default)
>input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0
>ACPI: Power Button [PWRB]
>input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input1
>ACPI: Sleep Button [SLPB]
>input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
>ACPI: Power Button [PWRF]
>thermal LNXTHERM:00: registered as thermal_zone0
>ACPI: Thermal Zone [THRM] (30 C)
>Uniform Multi-Platform E-IDE driver
>via82cxxx 0000:00:07.1: VIA vt82c686b (rev 40) IDE UDMA100
>via82cxxx 0000:00:07.1: IDE controller (0x1106:0x0571 rev 0x06)
>via82cxxx 0000:00:07.1: IDE port disabled
>via82cxxx 0000:00:07.1: not 100% native mode: will probe irqs later
>    ide0: BM-DMA at 0xffa0-0xffa7
>Probing IDE interface ide0...
>hda: SAMSUNG SP0802N, ATA DISK drive
>tsc: Refined TSC clocksource calibration: 1000.035 MHz
>Switching to clocksource tsc
>hdb: TOSHIBA ODD-DVD SD-R5272, ATAPI CD/DVD-ROM drive
>hda: host max PIO5 wanted PIO255(auto-tune) selected PIO4
>hda: host side 80-wire cable detection failed, limiting max speed to UDMA33
>hda: UDMA/33 mode selected
>hdb: host max PIO5 wanted PIO255(auto-tune) selected PIO4
>hdb: UDMA/33 mode selected
>ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
>ide_generic: please use "probe_mask=0x3f" module parameter for probing all legacy ISA IDE ports
>ide-gd driver 1.18
>hda: max request size: 512KiB
>hda: 156368016 sectors (80060 MB) w/2048KiB Cache, CHS=16383/255/63
>hda: cache flushes supported
> hda: hda1 hda2 hda3
>i8042: PNP: PS/2 Controller [PNP0f13:PS2M] at 0x60,0x64 irq 12
>i8042: PNP: PS/2 controller doesn't have KBD irq; using default 1
>serio: i8042 KBD port at 0x60,0x64 irq 1
>serio: i8042 AUX port at 0x60,0x64 irq 12
>cpuidle: using governor ladder
>TCP: cubic registered
>Using IPI Shortcut mode
>drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
>BIOS EDD facility v0.16 2004-Jun-25, 1 devices found
>EXT4-fs (hda2): couldn't mount as ext3 due to feature incompatibilities
>EXT4-fs (hda2): couldn't mount as ext2 due to feature incompatibilities
>EXT4-fs (hda2): mounted filesystem with ordered data mode. Opts: (null)
>VFS: Mounted root (ext4 filesystem) readonly on device 3:2.
>Freeing unused kernel memory: 320k freed
>Write protecting the kernel text: 1964k
>Write protecting the kernel read-only data: 452k
>vmalloc: allocation failure: 0 bytes
>modprobe: page allocation failure: order:0, mode:0xd2
>Pid: 61, comm: modprobe Not tainted 3.7.0-small-00147-ga6f3b00 #34
>Call Trace:
> [<c0153724>] ? 0xc0153724
> [<c0144e07>] ? 0xc0144e07
> [<c0169155>] ? 0xc0169155
> [<c0118690>] ? 0xc0118690
> [<c0144e07>] ? 0xc0144e07
> [<c0144e07>] ? 0xc0144e07
> [<c01453dc>] ? 0xc01453dc
> [<c0119574>] ? 0xc0119574
> [<c0145cb8>] ? 0xc0145cb8
> [<c016fe7d>] ? 0xc016fe7d
> [<c02e9608>] ? 0xc02e9608
>Mem-Info:
>DMA per-cpu:
>CPU    0: hi:    0, btch:   1 usd:   0
>Normal per-cpu:
>CPU    0: hi:  186, btch:  31 usd:  51
>active_anon:389 inactive_anon:1 isolated_anon:0
> active_file:666 inactive_file:1579 isolated_file:0
> unevictable:0 dirty:0 writeback:0 unstable:0
> free:124740 slab_reclaimable:177 slab_unreclaimable:311
> mapped:386 shmem:6 pagetables:32 bounce:0
> free_cma:0
>DMA free:13192kB min:84kB low:104kB high:124kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:15804kB mlocked:0kB dirty:0kB writeback:0kB mapped:0kB shmem:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 492 492
>Normal free:485768kB min:2792kB low:3488kB high:4188kB active_anon:1556kB inactive_anon:4kB active_file:2664kB inactive_file:6316kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:503872kB mlocked:0kB dirty:0kB writeback:0kB mapped:1544kB shmem:24kB slab_reclaimable:708kB slab_unreclaimable:1244kB kernel_stack:216kB pagetables:128kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 0 0
>DMA: 2*4kB 2*8kB 1*16kB 5*32kB 5*64kB 3*128kB 2*256kB 1*512kB 1*1024kB 1*2048kB 2*4096kB = 13192kB
>Normal: 2*4kB 0*8kB 2*16kB 3*32kB 2*64kB 1*128kB 2*256kB 1*512kB 3*1024kB 1*2048kB 117*4096kB = 485768kB
>2257 total pagecache pages
>0 pages in swap cache
>Swap cache stats: add 0, delete 0, find 0/0
>Free swap  = 0kB
>Total swap = 0kB
>131040 pages RAM
>2939 pages reserved
>2151 pages shared
>1873 pages non-shared
>Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
>00:07: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
>00:08: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
>Floppy drive(s): fd0 is 1.44M
>FDC 0 is a post-1991 82077
>rtc_cmos 00:02: RTC can wake from S4
>rtc_cmos 00:02: rtc core: registered rtc_cmos as rtc0
>rtc0: alarms up to one year, y3k, 114 bytes nvram
>Linux agpgart interface v0.103
>agpgart: Detected VIA Apollo Pro 133 chipset
>agpgart-via 0000:00:00.0: AGP aperture is 16M @ 0xe0000000
>vmalloc: allocation failure: 0 bytes
>modprobe: page allocation failure: order:0, mode:0xd2
>Pid: 73, comm: modprobe Not tainted 3.7.0-small-00147-ga6f3b00 #34
>Call Trace:
> [<c0153724>] ? 0xc0153724
> [<c0144e07>] ? 0xc0144e07
> [<c0169155>] ? 0xc0169155
> [<c0118690>] ? 0xc0118690
> [<c0144e07>] ? 0xc0144e07
> [<c0144e07>] ? 0xc0144e07
> [<c01453dc>] ? 0xc01453dc
> [<c0119574>] ? 0xc0119574
> [<c0145cb8>] ? 0xc0145cb8
> [<c016fe7d>] ? 0xc016fe7d
> [<c02e9608>] ? 0xc02e9608
>Mem-Info:
>DMA per-cpu:
>CPU    0: hi:    0, btch:   1 usd:   0
>Normal per-cpu:
>CPU    0: hi:  186, btch:  31 usd:  76
>active_anon:386 inactive_anon:1 isolated_anon:0
> active_file:684 inactive_file:1630 isolated_file:0
> unevictable:0 dirty:0 writeback:0 unstable:0
> free:124610 slab_reclaimable:183 slab_unreclaimable:320
> mapped:386 shmem:7 pagetables:31 bounce:0
> free_cma:0
>DMA free:13192kB min:84kB low:104kB high:124kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:15804kB mlocked:0kB dirty:0kB writeback:0kB mapped:0kB shmem:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 492 492
>Normal free:485248kB min:2792kB low:3488kB high:4188kB active_anon:1544kB inactive_anon:4kB active_file:2736kB inactive_file:6520kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:503872kB mlocked:0kB dirty:0kB writeback:0kB mapped:1544kB shmem:28kB slab_reclaimable:732kB slab_unreclaimable:1280kB kernel_stack:216kB pagetables:124kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 0 0
>DMA: 2*4kB 2*8kB 1*16kB 5*32kB 5*64kB 3*128kB 2*256kB 1*512kB 1*1024kB 1*2048kB 2*4096kB = 13192kB
>Normal: 2*4kB 3*8kB 0*16kB 3*32kB 2*64kB 1*128kB 2*256kB 2*512kB 2*1024kB 1*2048kB 117*4096kB = 485248kB
>2322 total pagecache pages
>0 pages in swap cache
>Swap cache stats: add 0, delete 0, find 0/0
>Free swap  = 0kB
>Total swap = 0kB
>131040 pages RAM
>2943 pages reserved
>2154 pages shared
>1970 pages non-shared
>vmalloc: allocation failure: 0 bytes
>modprobe: page allocation failure: order:0, mode:0xd2
>Pid: 73, comm: modprobe Not tainted 3.7.0-small-00147-ga6f3b00 #34
>Call Trace:
> [<c0153724>] ? 0xc0153724
> [<c0144e07>] ? 0xc0144e07
> [<c0169155>] ? 0xc0169155
> [<c0118690>] ? 0xc0118690
> [<c0144e07>] ? 0xc0144e07
> [<c0144e07>] ? 0xc0144e07
> [<c01453dc>] ? 0xc01453dc
> [<c0145cb8>] ? 0xc0145cb8
> [<c016fe7d>] ? 0xc016fe7d
> [<c02e9608>] ? 0xc02e9608
>Mem-Info:
>DMA per-cpu:
>CPU    0: hi:    0, btch:   1 usd:   0
>Normal per-cpu:
>CPU    0: hi:  186, btch:  31 usd:  75
>active_anon:393 inactive_anon:1 isolated_anon:0
> active_file:685 inactive_file:1631 isolated_file:0
> unevictable:0 dirty:0 writeback:0 unstable:0
> free:124610 slab_reclaimable:183 slab_unreclaimable:320
> mapped:386 shmem:7 pagetables:31 bounce:0
> free_cma:0
>DMA free:13192kB min:84kB low:104kB high:124kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:15804kB mlocked:0kB dirty:0kB writeback:0kB mapped:0kB shmem:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 492 492
>Normal free:485248kB min:2792kB low:3488kB high:4188kB active_anon:1572kB inactive_anon:4kB active_file:2740kB inactive_file:6524kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:503872kB mlocked:0kB dirty:0kB writeback:0kB mapped:1544kB shmem:28kB slab_reclaimable:732kB slab_unreclaimable:1280kB kernel_stack:216kB pagetables:124kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 0 0
>DMA: 2*4kB 2*8kB 1*16kB 5*32kB 5*64kB 3*128kB 2*256kB 1*512kB 1*1024kB 1*2048kB 2*4096kB = 13192kB
>Normal: 2*4kB 3*8kB 0*16kB 3*32kB 2*64kB 1*128kB 2*256kB 2*512kB 2*1024kB 1*2048kB 117*4096kB = 485248kB
>2323 total pagecache pages
>0 pages in swap cache
>Swap cache stats: add 0, delete 0, find 0/0
>Free swap  = 0kB
>Total swap = 0kB
>131040 pages RAM
>2943 pages reserved
>2146 pages shared
>1979 pages non-shared
>wmi: Mapper loaded
>vmalloc: allocation failure: 0 bytes
>modprobe: page allocation failure: order:0, mode:0xd2
>Pid: 73, comm: modprobe Not tainted 3.7.0-small-00147-ga6f3b00 #34
>Call Trace:
> [<c0153724>] ? 0xc0153724
> [<c0144e07>] ? 0xc0144e07
> [<c0169155>] ? 0xc0169155
> [<c0118690>] ? 0xc0118690
> [<c0144e07>] ? 0xc0144e07
> [<c0144e07>] ? 0xc0144e07
> [<c01453dc>] ? 0xc01453dc
> [<c0145cb8>] ? 0xc0145cb8
> [<c016fe7d>] ? 0xc016fe7d
> [<c02e9608>] ? 0xc02e9608
>Mem-Info:
>DMA per-cpu:
>CPU    0: hi:    0, btch:   1 usd:   0
>Normal per-cpu:
>CPU    0: hi:  186, btch:  31 usd:  57
>active_anon:394 inactive_anon:1 isolated_anon:0
> active_file:687 inactive_file:1635 isolated_file:0
> unevictable:0 dirty:0 writeback:0 unstable:0
> free:124608 slab_reclaimable:186 slab_unreclaimable:320
> mapped:386 shmem:7 pagetables:31 bounce:0
> free_cma:0
>DMA free:13192kB min:84kB low:104kB high:124kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:15804kB mlocked:0kB dirty:0kB writeback:0kB mapped:0kB shmem:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 492 492
>Normal free:485240kB min:2792kB low:3488kB high:4188kB active_anon:1576kB inactive_anon:4kB active_file:2748kB inactive_file:6540kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:503872kB mlocked:0kB dirty:0kB writeback:0kB mapped:1544kB shmem:28kB slab_reclaimable:744kB slab_unreclaimable:1280kB kernel_stack:216kB pagetables:124kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 0 0
>DMA: 2*4kB 2*8kB 1*16kB 5*32kB 5*64kB 3*128kB 2*256kB 1*512kB 1*1024kB 1*2048kB 2*4096kB = 13192kB
>Normal: 2*4kB 2*8kB 0*16kB 3*32kB 2*64kB 1*128kB 2*256kB 2*512kB 2*1024kB 1*2048kB 117*4096kB = 485240kB
>2331 total pagecache pages
>0 pages in swap cache
>Swap cache stats: add 0, delete 0, find 0/0
>Free swap  = 0kB
>Total swap = 0kB
>131040 pages RAM
>2943 pages reserved
>2153 pages shared
>1992 pages non-shared
>vmalloc: allocation failure: 0 bytes
>modprobe: page allocation failure: order:0, mode:0xd2
>Pid: 73, comm: modprobe Not tainted 3.7.0-small-00147-ga6f3b00 #34
>Call Trace:
> [<c0153724>] ? 0xc0153724
> [<c0144e07>] ? 0xc0144e07
> [<c0169155>] ? 0xc0169155
> [<c0118690>] ? 0xc0118690
> [<c0144e07>] ? 0xc0144e07
> [<c0144e07>] ? 0xc0144e07
> [<c01453dc>] ? 0xc01453dc
> [<c0145cb8>] ? 0xc0145cb8
> [<c016fe7d>] ? 0xc016fe7d
> [<c02e9608>] ? 0xc02e9608
>Mem-Info:
>DMA per-cpu:
>CPU    0: hi:    0, btch:   1 usd:   0
>Normal per-cpu:
>CPU    0: hi:  186, btch:  31 usd:  62
>active_anon:406 inactive_anon:1 isolated_anon:0
> active_file:689 inactive_file:1644 isolated_file:0
> unevictable:0 dirty:0 writeback:0 unstable:0
> free:124577 slab_reclaimable:187 slab_unreclaimable:321
> mapped:386 shmem:7 pagetables:31 bounce:0
> free_cma:0
>DMA free:13192kB min:84kB low:104kB high:124kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:15804kB mlocked:0kB dirty:0kB writeback:0kB mapped:0kB shmem:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 492 492
>Normal free:485116kB min:2792kB low:3488kB high:4188kB active_anon:1624kB inactive_anon:4kB active_file:2756kB inactive_file:6576kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:503872kB mlocked:0kB dirty:0kB writeback:0kB mapped:1544kB shmem:28kB slab_reclaimable:748kB slab_unreclaimable:1284kB kernel_stack:216kB pagetables:124kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 0 0
>DMA: 2*4kB 2*8kB 1*16kB 5*32kB 5*64kB 3*128kB 2*256kB 1*512kB 1*1024kB 1*2048kB 2*4096kB = 13192kB
>Normal: 1*4kB 1*8kB 1*16kB 3*32kB 2*64kB 2*128kB 1*256kB 2*512kB 2*1024kB 1*2048kB 117*4096kB = 485116kB
>2342 total pagecache pages
>0 pages in swap cache
>Swap cache stats: add 0, delete 0, find 0/0
>Free swap  = 0kB
>Total swap = 0kB
>131040 pages RAM
>2943 pages reserved
>2152 pages shared
>2020 pages non-shared
>vmalloc: allocation failure: 0 bytes
>modprobe: page allocation failure: order:0, mode:0xd2
>Pid: 73, comm: modprobe Not tainted 3.7.0-small-00147-ga6f3b00 #34
>Call Trace:
> [<c0153724>] ? 0xc0153724
> [<c0144e07>] ? 0xc0144e07
> [<c0169155>] ? 0xc0169155
> [<c0118690>] ? 0xc0118690
> [<c0144e07>] ? 0xc0144e07
> [<c0144e07>] ? 0xc0144e07
> [<c01453dc>] ? 0xc01453dc
> [<c0145cb8>] ? 0xc0145cb8
> [<c016fe7d>] ? 0xc016fe7d
> [<c02e9608>] ? 0xc02e9608
>Mem-Info:
>DMA per-cpu:
>CPU    0: hi:    0, btch:   1 usd:   0
>Normal per-cpu:
>CPU    0: hi:  186, btch:  31 usd:  49
>active_anon:406 inactive_anon:1 isolated_anon:0
> active_file:691 inactive_file:1650 isolated_file:0
> unevictable:0 dirty:0 writeback:0 unstable:0
> free:124577 slab_reclaimable:187 slab_unreclaimable:322
> mapped:386 shmem:7 pagetables:31 bounce:0
> free_cma:0
>DMA free:13192kB min:84kB low:104kB high:124kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:15804kB mlocked:0kB dirty:0kB writeback:0kB mapped:0kB shmem:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 492 492
>Normal free:485116kB min:2792kB low:3488kB high:4188kB active_anon:1624kB inactive_anon:4kB active_file:2764kB inactive_file:6600kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:503872kB mlocked:0kB dirty:0kB writeback:0kB mapped:1544kB shmem:28kB slab_reclaimable:748kB slab_unreclaimable:1288kB kernel_stack:216kB pagetables:124kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 0 0
>DMA: 2*4kB 2*8kB 1*16kB 5*32kB 5*64kB 3*128kB 2*256kB 1*512kB 1*1024kB 1*2048kB 2*4096kB = 13192kB
>Normal: 1*4kB 1*8kB 1*16kB 3*32kB 2*64kB 2*128kB 1*256kB 2*512kB 2*1024kB 1*2048kB 117*4096kB = 485116kB
>2351 total pagecache pages
>0 pages in swap cache
>Swap cache stats: add 0, delete 0, find 0/0
>Free swap  = 0kB
>Total swap = 0kB
>131040 pages RAM
>2943 pages reserved
>2159 pages shared
>2028 pages non-shared
>[drm] Initialized drm 1.1.0 20060810
>vmalloc: allocation failure: 0 bytes
>modprobe: page allocation failure: order:0, mode:0xd2
>Pid: 73, comm: modprobe Not tainted 3.7.0-small-00147-ga6f3b00 #34
>Call Trace:
> [<c0153724>] ? 0xc0153724
> [<c0144e07>] ? 0xc0144e07
> [<c0169155>] ? 0xc0169155
> [<c0118690>] ? 0xc0118690
> [<c0144e07>] ? 0xc0144e07
> [<c0144e07>] ? 0xc0144e07
> [<c01453dc>] ? 0xc01453dc
> [<c0145cb8>] ? 0xc0145cb8
> [<c016fe7d>] ? 0xc016fe7d
> [<c02e9608>] ? 0xc02e9608
>Mem-Info:
>DMA per-cpu:
>CPU    0: hi:    0, btch:   1 usd:   0
>Normal per-cpu:
>CPU    0: hi:  186, btch:  31 usd: 135
>active_anon:416 inactive_anon:1 isolated_anon:0
> active_file:693 inactive_file:1716 isolated_file:0
> unevictable:0 dirty:0 writeback:0 unstable:0
> free:124358 slab_reclaimable:189 slab_unreclaimable:322
> mapped:386 shmem:7 pagetables:31 bounce:0
> free_cma:0
>DMA free:13192kB min:84kB low:104kB high:124kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:15804kB mlocked:0kB dirty:0kB writeback:0kB mapped:0kB shmem:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 492 492
>Normal free:484240kB min:2792kB low:3488kB high:4188kB active_anon:1664kB inactive_anon:4kB active_file:2772kB inactive_file:6864kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:503872kB mlocked:0kB dirty:0kB writeback:0kB mapped:1544kB shmem:28kB slab_reclaimable:756kB slab_unreclaimable:1288kB kernel_stack:216kB pagetables:124kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 0 0
>DMA: 2*4kB 2*8kB 1*16kB 5*32kB 5*64kB 3*128kB 2*256kB 1*512kB 1*1024kB 1*2048kB 2*4096kB = 13192kB
>Normal: 2*4kB 1*8kB 2*16kB 1*32kB 1*64kB 2*128kB 2*256kB 0*512kB 2*1024kB 1*2048kB 117*4096kB = 484240kB
>2423 total pagecache pages
>0 pages in swap cache
>Swap cache stats: add 0, delete 0, find 0/0
>Free swap  = 0kB
>Total swap = 0kB
>131040 pages RAM
>2943 pages reserved
>2164 pages shared
>2153 pages non-shared
>nouveau T[  DEVICE][0000:01:00.0] inc() == 2
>nouveau T[     DRM] inc() == 3
>nouveau T[     DRM] inc() == 4
>nouveau T[     DRM] inc() == 5
>nouveau T[  DEVICE][0000:01:00.0] inc() == 3
>nouveau  [  DEVICE][0000:01:00.0] BOOT0  : 0x043000a2
>nouveau  [  DEVICE][0000:01:00.0] Chipset: NV43 (NV43)
>nouveau  [  DEVICE][0000:01:00.0] Family : NV40
>nouveau D[  DEVICE][0000:01:00.0] crystal freq: 27000KHz
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1da600] created
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] use(+1) == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] initialising...
>nouveau T[     DRM] use(+1) == 3
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1da600] initialised
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 2
>nouveau T[     DRM] 0xffffffff:0xdddddddd created
>nouveau T[     DRM] 0xffffffff:0xdddddddd init running
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] use(+1) == 2
>nouveau T[     DRM] 0xffffffff:0xdddddddd init children
>nouveau T[     DRM] 0xffffffff:0xdddddddd init completed
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] use(-1) == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 1
>nouveau T[     DRM] dec() == 4
>nouveau T[     DRM] dec() == 3
>nouveau T[     DRM] inc() == 4
>nouveau T[     DRM] 0xffffffff:0xdddddddd fini children
>nouveau T[     DRM] 0xffffffff:0xdddddddd fini running
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] use(-1) == 0
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] stopping...
>nouveau T[  DEVICE][0000:01:00.0] use(-1) == 2
>nouveau T[     DRM] use(-1) == 2
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1da600] stopped
>nouveau T[     DRM] 0xffffffff:0xdddddddd fini completed
>nouveau T[     DRM] 0xffffffff:0xdddddddd destroy running
>nouveau T[     DRM] 0xffffffff:0xdddddddd destroy completed
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 0
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1da600] destroying
>nouveau T[  DEVICE][0000:01:00.0] dec() == 2
>nouveau T[     DRM] dec() == 3
>nouveau T[     DRM] dec() == 2
>nouveau T[     DRM] inc() == 3
>nouveau T[     DRM] inc() == 4
>nouveau T[     DRM] inc() == 5
>nouveau T[  DEVICE][0000:01:00.0] inc() == 3
>nouveau T[  DEVICE][0000:01:00.0] inc() == 4
>nouveau  [   VBIOS][0000:01:00.0] checking PRAMIN for image...
>nouveau  [   VBIOS][0000:01:00.0] ... appears to be valid
>nouveau  [   VBIOS][0000:01:00.0] using image from PRAMIN
>nouveau  [   VBIOS][0000:01:00.0] BIT signature found
>nouveau  [   VBIOS][0000:01:00.0] version 05.43.02.36.00
>nouveau D[   VBIOS][0000:01:00.0] created
>nouveau T[  DEVICE][0000:01:00.0] inc() == 5
>nouveau D[ DEVINIT][0000:01:00.0] created
>nouveau T[  DEVICE][0000:01:00.0] inc() == 6
>nouveau D[    GPIO][0000:01:00.0] created
>nouveau T[  DEVICE][0000:01:00.0] inc() == 7
>nouveau D[     I2C][0000:01:00.0] created
>nouveau T[  DEVICE][0000:01:00.0] inc() == 8
>nouveau D[   CLOCK][0000:01:00.0] created
>nouveau T[   VBIOS][0000:01:00.0] use(+1) == 1
>nouveau T[   VBIOS][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 3
>nouveau T[   VBIOS][0000:01:00.0] resetting...
>nouveau D[   VBIOS][0000:01:00.0] reset
>nouveau D[   VBIOS][0000:01:00.0] initialised
>nouveau T[ DEVINIT][0000:01:00.0] use(+1) == 1
>nouveau T[ DEVINIT][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 4
>nouveau T[ DEVINIT][0000:01:00.0] resetting...
>nouveau D[ DEVINIT][0000:01:00.0] reset
>nouveau T[   VBIOS][0000:01:00.0] 0xeec2[ ]: ZM_CR	C[0x44] = 0x03
>nouveau T[   VBIOS][0000:01:00.0] 0xeec5[ ]: INDEX_IO	I[0x03c4][0x01] &= 0xff |= 0x20
>nouveau T[   VBIOS][0000:01:00.0] 0xeecb[ ]: ZM_CR	C[0x44] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xeece[ ]: INDEX_IO	I[0x03c4][0x01] &= 0xff |= 0x20
>nouveau T[   VBIOS][0000:01:00.0] 0xeed4[ ]: RESET	R[0x00000200] = 0x01100000, 0x05110111
>nouveau T[   VBIOS][0000:01:00.0] 0xeee1[ ]: ZM_REG	R[0x680608] = 0x00010000
>nouveau T[   VBIOS][0000:01:00.0] 0xeeea[ ]: ZM_REG	R[0x680670] = 0x00010000
>nouveau T[   VBIOS][0000:01:00.0] 0xeef3[ ]: NV_REG	R[0x101000] &= 0xffffffff |= 0x80000000
>nouveau T[   VBIOS][0000:01:00.0] 0xef00[ ]: NV_REG	R[0x10100c] &= 0xffffffff |= 0x80000000
>nouveau T[   VBIOS][0000:01:00.0] 0xef0d[ ]: NV_REG	R[0x600818] &= 0xffffffff |= 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xef1a[ ]: NV_REG	R[0x600818] &= 0xffffffff |= 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xef27[ ]: NV_REG	R[0x60081c] &= 0xfffccfff |= 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xef34[ ]: NV_REG	R[0x60081c] &= 0xffffffff |= 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xef41[ ]: CR		C[0x5e] &= 0xff |= 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xef45[ ]: CR		C[0x5d] &= 0xff |= 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xef49[ ]: ZM_REG	R[0x00c000] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xef52[ ]: ZM_REG	R[0x001540] = 0x001f0703
>nouveau T[   VBIOS][0000:01:00.0] 0xef5b[ ]: ZM_REG	R[0x100210] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xef64[ ]: ZM_REG	R[0x00c040] = 0x30000000
>nouveau T[   VBIOS][0000:01:00.0] 0xef6d[ ]: NV_REG	R[0x00c044] &= 0xffffe0e0 |= 0x00001010
>nouveau T[   VBIOS][0000:01:00.0] 0xef7a[ ]: NV_REG	R[0x0015b4] &= 0x03ffffff |= 0x08000000
>nouveau T[   VBIOS][0000:01:00.0] 0xef87[ ]: ZM_REG	R[0x0015b8] = 0x94800000
>nouveau T[   VBIOS][0000:01:00.0] 0xef90[ ]: ZM_REG	R[0x004000] = 0x0000001c
>nouveau T[   VBIOS][0000:01:00.0] 0xef99[ ]: ZM_REG	R[0x004008] = 0x01c00000
>nouveau T[   VBIOS][0000:01:00.0] 0xefa2[ ]: ZM_REG	R[0x680580] = 0x01c0001c
>nouveau T[   VBIOS][0000:01:00.0] 0xefab[ ]: ZM_REG	R[0x004020] = 0x2000001c
>nouveau T[   VBIOS][0000:01:00.0] 0xefb4[ ]: ZM_REG	R[0x004038] = 0x2000001c
>nouveau T[   VBIOS][0000:01:00.0] 0xefbd[ ]: ZM_REG	R[0x100360] = 0x8b303a98
>nouveau T[   VBIOS][0000:01:00.0] 0xefc6[ ]: CONDITION	0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xefc8[ ]: 	[0x00] (R[0x101000] & 0x00000040) == 0x00000040
>nouveau T[   VBIOS][0000:01:00.0] 0xefc8[ ]: ZM_INDEX_IO	I[0x03d4][0x3c] = 0x01
>nouveau T[   VBIOS][0000:01:00.0] 0xefcd[ ]: NOT
>nouveau T[   VBIOS][0000:01:00.0] 0xefce[ ]: ZM_INDEX_IO	I[0x03d4][0x3c] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xefd3[ ]: RESUME
>nouveau T[   VBIOS][0000:01:00.0] 0xefd4[ ]: COPY	0x03d4[0x3c] &= 0x0f |= ((R[0x101000] << 0x02) & 0xf0)
>nouveau T[   VBIOS][0000:01:00.0] 0xefdf[ ]: ZM_REG	R[0x004400] = 0x00000002
>nouveau T[   VBIOS][0000:01:00.0] 0xefe8[ ]: ZM_REG	R[0x00c040] = 0x30000000
>nouveau T[   VBIOS][0000:01:00.0] 0xeff1[ ]: ZM_REG	R[0x680510] = 0x0000001c
>nouveau T[   VBIOS][0000:01:00.0] 0xeffa[ ]: NV_REG	R[0x001580] &= 0xcfffffff |= 0x30000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf007[ ]: ZM_REG	R[0x000140] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf010[ ]: ZM_REG	R[0x000200] = 0x07110111
>nouveau T[   VBIOS][0000:01:00.0] 0xf019[ ]: ZM_REG	R[0x001084] = 0x00205649
>nouveau T[   VBIOS][0000:01:00.0] 0xf022[ ]: PLL2	R[0x004024] =PLL= 200000kHz
>nouveau T[   VBIOS][0000:01:00.0] 0xf02b[ ]: SUB	0x06
>nouveau T[   VBIOS][0000:01:00.0] 0xf02d[ ]: ZM_REG	R[0x10037c] = 0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf036[ ]: ZM_REG	R[0x100388] = 0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf03f[ ]: ZM_REG	R[0x100380] = 0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf048[ ]: ZM_REG	R[0x10038c] = 0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf051[ ]: ZM_REG	R[0x1003ac] = 0x80808080
>nouveau T[   VBIOS][0000:01:00.0] 0xf05a[ ]: ZM_REG	R[0x1003b4] = 0x80808080
>nouveau T[   VBIOS][0000:01:00.0] 0xf063[ ]: ZM_REG	R[0x1003b0] = 0x80808080
>nouveau T[   VBIOS][0000:01:00.0] 0xf06c[ ]: ZM_REG	R[0x1003b8] = 0x80808080
>nouveau T[   VBIOS][0000:01:00.0] 0xf075[ ]: IO_RESTRICT_PROG	R[0x100384] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf080[ ]: 	0x80808080 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf084[ ]: 	0x80808080
>nouveau T[   VBIOS][0000:01:00.0] 0xf088[ ]: 	0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf08c[ ]: 	0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf090[ ]: 	0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf094[ ]: 	0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf098[ ]: 	0x80808080
>nouveau T[   VBIOS][0000:01:00.0] 0xf09c[ ]: 	0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf0a0[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf0a0[ ]: IO_RESTRICT_PROG	R[0x100390] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf0ab[ ]: 	0x80808080 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf0af[ ]: 	0x80808080
>nouveau T[   VBIOS][0000:01:00.0] 0xf0b3[ ]: 	0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf0b7[ ]: 	0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf0bb[ ]: 	0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf0bf[ ]: 	0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf0c3[ ]: 	0x80808080
>nouveau T[   VBIOS][0000:01:00.0] 0xf0c7[ ]: 	0x0f0f0f0f
>nouveau T[   VBIOS][0000:01:00.0] 0xf0cb[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf0cb[ ]: IO_RESTRICT_PROG	R[0x004028] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf0d6[ ]: 	0x00000000 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf0da[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf0de[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf0e2[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf0e6[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf0ea[ ]: 	0x80000cc9
>nouveau T[   VBIOS][0000:01:00.0] 0xf0ee[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf0f2[ ]: 	0x80000cc9
>nouveau T[   VBIOS][0000:01:00.0] 0xf0f6[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf0f6[ ]: IO_RESTRICT_PROG	R[0x004040] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf101[ ]: 	0x00000000 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf105[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf109[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf10d[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf111[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf115[ ]: 	0x80000bb0
>nouveau T[   VBIOS][0000:01:00.0] 0xf119[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf11d[ ]: 	0x80000bb0
>nouveau T[   VBIOS][0000:01:00.0] 0xf121[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf121[ ]: ZM_REG	R[0x00c040] = 0x3003c000
>nouveau T[   VBIOS][0000:01:00.0] 0xf12a[ ]: NV_REG	R[0x00c040] &= 0xffffffff |= 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf137[ ]: IO_RESTRICT_PROG	R[0x100220] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf142[ ]: 	0x04080e0c *
>nouveau T[   VBIOS][0000:01:00.0] 0xf146[ ]: 	0x0b162821
>nouveau T[   VBIOS][0000:01:00.0] 0xf14a[ ]: 	0x09162b1f
>nouveau T[   VBIOS][0000:01:00.0] 0xf14e[ ]: 	0x04080e0c
>nouveau T[   VBIOS][0000:01:00.0] 0xf152[ ]: 	0x04080e0c
>nouveau T[   VBIOS][0000:01:00.0] 0xf156[ ]: 	0x060c1612
>nouveau T[   VBIOS][0000:01:00.0] 0xf15a[ ]: 	0x04080e0c
>nouveau T[   VBIOS][0000:01:00.0] 0xf15e[ ]: 	0x060f1b15
>nouveau T[   VBIOS][0000:01:00.0] 0xf162[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf162[ ]: IO_RESTRICT_PROG	R[0x100224] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf16d[ ]: 	0x05030405 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf171[ ]: 	0x0e010d06
>nouveau T[   VBIOS][0000:01:00.0] 0xf175[ ]: 	0x09010807
>nouveau T[   VBIOS][0000:01:00.0] 0xf179[ ]: 	0x05030405
>nouveau T[   VBIOS][0000:01:00.0] 0xf17d[ ]: 	0x05030405
>nouveau T[   VBIOS][0000:01:00.0] 0xf181[ ]: 	0x09010607
>nouveau T[   VBIOS][0000:01:00.0] 0xf185[ ]: 	0x05030405
>nouveau T[   VBIOS][0000:01:00.0] 0xf189[ ]: 	0x09010509
>nouveau T[   VBIOS][0000:01:00.0] 0xf18d[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf18d[ ]: IO_RESTRICT_PROG	R[0x100228] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf198[ ]: 	0x00220404 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf19c[ ]: 	0x2527080d
>nouveau T[   VBIOS][0000:01:00.0] 0xf1a0[ ]: 	0x2325090c
>nouveau T[   VBIOS][0000:01:00.0] 0xf1a4[ ]: 	0x00220404
>nouveau T[   VBIOS][0000:01:00.0] 0xf1a8[ ]: 	0x00220404
>nouveau T[   VBIOS][0000:01:00.0] 0xf1ac[ ]: 	0x21240507
>nouveau T[   VBIOS][0000:01:00.0] 0xf1b0[ ]: 	0x00220404
>nouveau T[   VBIOS][0000:01:00.0] 0xf1b4[ ]: 	0x20250407
>nouveau T[   VBIOS][0000:01:00.0] 0xf1b8[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf1b8[ ]: IO_RESTRICT_PROG	R[0x10022c] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf1c3[ ]: 	0x0008f172 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf1c7[ ]: 	0x470e7708
>nouveau T[   VBIOS][0000:01:00.0] 0xf1cb[ ]: 	0x460d8607
>nouveau T[   VBIOS][0000:01:00.0] 0xf1cf[ ]: 	0x0008f172
>nouveau T[   VBIOS][0000:01:00.0] 0xf1d3[ ]: 	0x0006f171
>nouveau T[   VBIOS][0000:01:00.0] 0xf1d7[ ]: 	0x540c9405
>nouveau T[   VBIOS][0000:01:00.0] 0xf1db[ ]: 	0x0008f172
>nouveau T[   VBIOS][0000:01:00.0] 0xf1df[ ]: 	0x550d9506
>nouveau T[   VBIOS][0000:01:00.0] 0xf1e3[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf1e3[ ]: IO_RESTRICT_PROG	R[0x100230] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf1ee[ ]: 	0x000001bf *
>nouveau T[   VBIOS][0000:01:00.0] 0xf1f2[ ]: 	0x00000cad
>nouveau T[   VBIOS][0000:01:00.0] 0xf1f6[ ]: 	0x00000c1f
>nouveau T[   VBIOS][0000:01:00.0] 0xf1fa[ ]: 	0x00000cbf
>nouveau T[   VBIOS][0000:01:00.0] 0xf1fe[ ]: 	0x0000001f
>nouveau T[   VBIOS][0000:01:00.0] 0xf202[ ]: 	0x00000c3f
>nouveau T[   VBIOS][0000:01:00.0] 0xf206[ ]: 	0x0000001f
>nouveau T[   VBIOS][0000:01:00.0] 0xf20a[ ]: 	0x00000c3f
>nouveau T[   VBIOS][0000:01:00.0] 0xf20e[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf20e[ ]: IO_RESTRICT_PROG	R[0x100234] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf219[ ]: 	0x00b5ff33 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf21d[ ]: 	0x01167622
>nouveau T[   VBIOS][0000:01:00.0] 0xf221[ ]: 	0x00229255
>nouveau T[   VBIOS][0000:01:00.0] 0xf225[ ]: 	0x00b5ff33
>nouveau T[   VBIOS][0000:01:00.0] 0xf229[ ]: 	0x00b5ff33
>nouveau T[   VBIOS][0000:01:00.0] 0xf22d[ ]: 	0x00b5ff66
>nouveau T[   VBIOS][0000:01:00.0] 0xf231[ ]: 	0x00b5ff33
>nouveau T[   VBIOS][0000:01:00.0] 0xf235[ ]: 	0x00b5ff44
>nouveau T[   VBIOS][0000:01:00.0] 0xf239[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf239[ ]: IO_RESTRICT_PROG	R[0x100238] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf244[ ]: 	0x00000114 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf248[ ]: 	0x003f0115
>nouveau T[   VBIOS][0000:01:00.0] 0xf24c[ ]: 	0x001f0116
>nouveau T[   VBIOS][0000:01:00.0] 0xf250[ ]: 	0x00000114
>nouveau T[   VBIOS][0000:01:00.0] 0xf254[ ]: 	0x00000112
>nouveau T[   VBIOS][0000:01:00.0] 0xf258[ ]: 	0x00200217
>nouveau T[   VBIOS][0000:01:00.0] 0xf25c[ ]: 	0x00000114
>nouveau T[   VBIOS][0000:01:00.0] 0xf260[ ]: 	0x00200219
>nouveau T[   VBIOS][0000:01:00.0] 0xf264[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf264[ ]: DONE
>nouveau T[   VBIOS][0000:01:00.0] 0xf265[ ]: ZM_REG	R[0x100328] = 0x08030114
>nouveau T[   VBIOS][0000:01:00.0] 0xf26e[ ]: ZM_REG	R[0x10032c] = 0xffff3f1f
>nouveau T[   VBIOS][0000:01:00.0] 0xf277[ ]: ZM_REG	R[0x100330] = 0xcccc5044
>nouveau T[   VBIOS][0000:01:00.0] 0xf280[ ]: ZM_REG	R[0x100334] = 0x33332022
>nouveau T[   VBIOS][0000:01:00.0] 0xf289[ ]: ZM_REG	R[0x100338] = 0x0000000e
>nouveau T[   VBIOS][0000:01:00.0] 0xf292[ ]: ZM_REG	R[0x10033c] = 0x00041286
>nouveau T[   VBIOS][0000:01:00.0] 0xf29b[ ]: ZM_REG	R[0x100340] = 0x000001ff
>nouveau T[   VBIOS][0000:01:00.0] 0xf2a4[ ]: ZM_REG	R[0x100344] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf2ad[ ]: ZM_REG	R[0x100348] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf2b6[ ]: ZM_REG	R[0x100350] = 0x0000440a
>nouveau T[   VBIOS][0000:01:00.0] 0xf2bf[ ]: ZM_REG	R[0x100354] = 0x00000806
>nouveau T[   VBIOS][0000:01:00.0] 0xf2c8[ ]: IO_RESTRICT_PROG	R[0x001080] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf2d3[ ]: 	0x00000000 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf2d7[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf2db[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf2df[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf2e3[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf2e7[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf2eb[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf2ef[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf2f3[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf2f3[ ]: ZM_REG	R[0x100210] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf2fc[ ]: ZM_REG	R[0x001220] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf305[ ]: ZM_REG	R[0x001228] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf30e[ ]: ZM_REG	R[0x001210] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf317[ ]: ZM_REG	R[0x001214] = 0x03330204
>nouveau T[   VBIOS][0000:01:00.0] 0xf320[ ]: ZM_REG	R[0x001218] = 0xf0000101
>nouveau T[   VBIOS][0000:01:00.0] 0xf329[ ]: ZM_REG_SEQUENCE	0x03
>nouveau T[   VBIOS][0000:01:00.0] 0xf32f[ ]: 		R[0x001230] = 0x80000a0a
>nouveau T[   VBIOS][0000:01:00.0] 0xf333[ ]: 		R[0x001234] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf337[ ]: 		R[0x001238] = 0xf83e0000
>nouveau T[   VBIOS][0000:01:00.0] 0xf33b[ ]: ZM_REG_SEQUENCE	0x04
>nouveau T[   VBIOS][0000:01:00.0] 0xf341[ ]: 		R[0x001240] = 0x80000a0a
>nouveau T[   VBIOS][0000:01:00.0] 0xf345[ ]: 		R[0x001244] = 0x0001000f
>nouveau T[   VBIOS][0000:01:00.0] 0xf349[ ]: 		R[0x001248] = 0xf83e0000
>nouveau T[   VBIOS][0000:01:00.0] 0xf34d[ ]: 		R[0x00124c] = 0xaa11aa11
>nouveau T[   VBIOS][0000:01:00.0] 0xf351[ ]: TIME	0x07d0
>nouveau T[   VBIOS][0000:01:00.0] 0xf354[ ]: IO_RESTRICT_PROG	R[0x100218] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf35f[ ]: 	0x00000000 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf363[ ]: 	0x00000100
>nouveau T[   VBIOS][0000:01:00.0] 0xf367[ ]: 	0x01000100
>nouveau T[   VBIOS][0000:01:00.0] 0xf36b[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf36f[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf373[ ]: 	0x01000100
>nouveau T[   VBIOS][0000:01:00.0] 0xf377[ ]: 	0x00000100
>nouveau T[   VBIOS][0000:01:00.0] 0xf37b[ ]: 	0x01000100
>nouveau T[   VBIOS][0000:01:00.0] 0xf37f[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf37f[ ]: TIME	0x07d0
>nouveau T[   VBIOS][0000:01:00.0] 0xf382[ ]: MACRO	0x01
>nouveau T[   VBIOS][0000:01:00.0] 0xf382[ ]: 		R[0x10021c] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf384[ ]: TIME	0x07d0
>nouveau T[   VBIOS][0000:01:00.0] 0xf387[ ]: CONDITION	0x03
>nouveau T[   VBIOS][0000:01:00.0] 0xf389[ ]: 	[0x03] (R[0x101000] & 0x00000020) == 0x00000020
>nouveau T[   VBIOS][0000:01:00.0] 0xf389[ ]: IO_RESTRICT_PROG	R[0x100200] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf394[ ]: 	0x03000021 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf398[ ]: 	0x23003021
>nouveau T[   VBIOS][0000:01:00.0] 0xf39c[ ]: 	0x40000021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3a0[ ]: 	0x03000021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3a4[ ]: 	0x04000021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3a8[ ]: 	0x03000021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3ac[ ]: 	0x03000021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3b0[ ]: 	0x03000021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3b4[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf3b4[ ]: NOT
>nouveau T[   VBIOS][0000:01:00.0] 0xf3b5[ ]: IO_RESTRICT_PROG	R[0x100200] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf3c0[ ]: 	0x03000021 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf3c4[ ]: 	0x23003021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3c8[ ]: 	0x40000021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3cc[ ]: 	0x03000021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3d0[ ]: 	0x04000021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3d4[ ]: 	0x43003021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3d8[ ]: 	0x03000021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3dc[ ]: 	0x43003021
>nouveau T[   VBIOS][0000:01:00.0] 0xf3e0[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf3e0[ ]: RESUME
>nouveau T[   VBIOS][0000:01:00.0] 0xf3e1[ ]: TIME	0x07d0
>nouveau T[   VBIOS][0000:01:00.0] 0xf3e4[ ]: IO_RESTRICT_PROG	R[0x100204] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf3ef[ ]: 	0x11449220 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf3f3[ ]: 	0x11449220
>nouveau T[   VBIOS][0000:01:00.0] 0xf3f7[ ]: 	0x06449000
>nouveau T[   VBIOS][0000:01:00.0] 0xf3fb[ ]: 	0x11449220
>nouveau T[   VBIOS][0000:01:00.0] 0xf3ff[ ]: 	0x00449220
>nouveau T[   VBIOS][0000:01:00.0] 0xf403[ ]: 	0x00449000
>nouveau T[   VBIOS][0000:01:00.0] 0xf407[ ]: 	0x11449220
>nouveau T[   VBIOS][0000:01:00.0] 0xf40b[ ]: 	0x00449000
>nouveau T[   VBIOS][0000:01:00.0] 0xf40f[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf40f[ ]: ZM_REG	R[0x100210] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf418[ ]: ZM_REG	R[0x100214] = 0x000000b0
>nouveau T[   VBIOS][0000:01:00.0] 0xf421[ ]: TIME	0x00c8
>nouveau T[   VBIOS][0000:01:00.0] 0xf424[ ]: IO_RESTRICT_PROG	R[0x100218] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf42f[ ]: 	0x00000000 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf433[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf437[ ]: 	0x01000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf43b[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf43f[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf443[ ]: 	0x01000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf447[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf44b[ ]: 	0x01000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf44f[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf44f[ ]: TIME	0x07d0
>nouveau T[   VBIOS][0000:01:00.0] 0xf452[ ]: IO_RESTRICT_PROG	R[0x100218] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf45d[ ]: 	0x00000001 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf461[ ]: 	0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf465[ ]: 	0x01000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf469[ ]: 	0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf46d[ ]: 	0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf471[ ]: 	0x01000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf475[ ]: 	0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf479[ ]: 	0x01000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf47d[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf47d[ ]: TIME	0x07d0
>nouveau T[   VBIOS][0000:01:00.0] 0xf480[ ]: TIME	0x00c8
>nouveau T[   VBIOS][0000:01:00.0] 0xf483[ ]: MACRO	0x03
>nouveau T[   VBIOS][0000:01:00.0] 0xf483[ ]: 		R[0x1002d8] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf485[ ]: MACRO	0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf485[ ]: 		R[0x1002d4] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf487[ ]: IO_FLAG_CONDITION	0x04
>nouveau T[   VBIOS][0000:01:00.0] 0xf489[ ]: IO_RESTRICT_PROG	R[0x1002c0] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf494[ ]: 	0x00000032 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf498[ ]: 	0x00000042
>nouveau T[   VBIOS][0000:01:00.0] 0xf49c[ ]: 	0x00000802
>nouveau T[   VBIOS][0000:01:00.0] 0xf4a0[ ]: 	0x00000032
>nouveau T[   VBIOS][0000:01:00.0] 0xf4a4[ ]: 	0x00000032
>nouveau T[   VBIOS][0000:01:00.0] 0xf4a8[ ]: 	0x00000562
>nouveau T[   VBIOS][0000:01:00.0] 0xf4ac[ ]: 	0x00000042
>nouveau T[   VBIOS][0000:01:00.0] 0xf4b0[ ]: 	0x00000221
>nouveau T[   VBIOS][0000:01:00.0] 0xf4b4[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf4b4[ ]: IO_RESTRICT_PROG	R[0x1002c8] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf4bf[ ]: 	0x00000032 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf4c3[ ]: 	0x00000042
>nouveau T[   VBIOS][0000:01:00.0] 0xf4c7[ ]: 	0x00000802
>nouveau T[   VBIOS][0000:01:00.0] 0xf4cb[ ]: 	0x00000032
>nouveau T[   VBIOS][0000:01:00.0] 0xf4cf[ ]: 	0x00000032
>nouveau T[   VBIOS][0000:01:00.0] 0xf4d3[ ]: 	0x00000562
>nouveau T[   VBIOS][0000:01:00.0] 0xf4d7[ ]: 	0x00000042
>nouveau T[   VBIOS][0000:01:00.0] 0xf4db[ ]: 	0x00000221
>nouveau T[   VBIOS][0000:01:00.0] 0xf4df[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf4df[ ]: RESUME
>nouveau T[   VBIOS][0000:01:00.0] 0xf4e0[ ]: IO_RESTRICT_PROG	R[0x1002c4] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf4eb[ ]: 	0x00100000 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf4ef[ ]: 	0x00100000
>nouveau T[   VBIOS][0000:01:00.0] 0xf4f3[ ]: 	0x0010000c
>nouveau T[   VBIOS][0000:01:00.0] 0xf4f7[ ]: 	0x00100000
>nouveau T[   VBIOS][0000:01:00.0] 0xf4fb[ ]: 	0x00100000
>nouveau T[   VBIOS][0000:01:00.0] 0xf4ff[ ]: 	0x00100038
>nouveau T[   VBIOS][0000:01:00.0] 0xf503[ ]: 	0x00100000
>nouveau T[   VBIOS][0000:01:00.0] 0xf507[ ]: 	0x00100088
>nouveau T[   VBIOS][0000:01:00.0] 0xf50b[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf50b[ ]: IO_RESTRICT_PROG	R[0x1002cc] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf516[ ]: 	0x00100000 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf51a[ ]: 	0x00100000
>nouveau T[   VBIOS][0000:01:00.0] 0xf51e[ ]: 	0x0010000c
>nouveau T[   VBIOS][0000:01:00.0] 0xf522[ ]: 	0x00100000
>nouveau T[   VBIOS][0000:01:00.0] 0xf526[ ]: 	0x00100000
>nouveau T[   VBIOS][0000:01:00.0] 0xf52a[ ]: 	0x00100038
>nouveau T[   VBIOS][0000:01:00.0] 0xf52e[ ]: 	0x00100000
>nouveau T[   VBIOS][0000:01:00.0] 0xf532[ ]: 	0x00100088
>nouveau T[   VBIOS][0000:01:00.0] 0xf536[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf536[ ]: IO_RESTRICT_PROG	R[0x100450] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf541[ ]: 	0x00000100 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf545[ ]: 	0x00003101
>nouveau T[   VBIOS][0000:01:00.0] 0xf549[ ]: 	0x00100110
>nouveau T[   VBIOS][0000:01:00.0] 0xf54d[ ]: 	0x00000100
>nouveau T[   VBIOS][0000:01:00.0] 0xf551[ ]: 	0x00010100
>nouveau T[   VBIOS][0000:01:00.0] 0xf555[ ]: 	0x00110110
>nouveau T[   VBIOS][0000:01:00.0] 0xf559[ ]: 	0x00000100
>nouveau T[   VBIOS][0000:01:00.0] 0xf55d[ ]: 	0x00110110
>nouveau T[   VBIOS][0000:01:00.0] 0xf561[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf561[ ]: IO_RESTRICT_PROG	R[0x100454] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf56c[ ]: 	0x00000000 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf570[ ]: 	0x00000011
>nouveau T[   VBIOS][0000:01:00.0] 0xf574[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf578[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf57c[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf580[ ]: 	0x00000011
>nouveau T[   VBIOS][0000:01:00.0] 0xf584[ ]: 	0x00000011
>nouveau T[   VBIOS][0000:01:00.0] 0xf588[ ]: 	0x00000011
>nouveau T[   VBIOS][0000:01:00.0] 0xf58c[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf58c[ ]: IO_RESTRICT_PROG	R[0x100460] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf597[ ]: 	0x77777777 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf59b[ ]: 	0x77777777
>nouveau T[   VBIOS][0000:01:00.0] 0xf59f[ ]: 	0x77777777
>nouveau T[   VBIOS][0000:01:00.0] 0xf5a3[ ]: 	0x77777777
>nouveau T[   VBIOS][0000:01:00.0] 0xf5a7[ ]: 	0x77777777
>nouveau T[   VBIOS][0000:01:00.0] 0xf5ab[ ]: 	0x77777777
>nouveau T[   VBIOS][0000:01:00.0] 0xf5af[ ]: 	0x77777777
>nouveau T[   VBIOS][0000:01:00.0] 0xf5b3[ ]: 	0x77777777
>nouveau T[   VBIOS][0000:01:00.0] 0xf5b7[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf5b7[ ]: IO_RESTRICT_PROG	R[0x100464] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf5c2[ ]: 	0x88888888 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf5c6[ ]: 	0x88888888
>nouveau T[   VBIOS][0000:01:00.0] 0xf5ca[ ]: 	0x88888888
>nouveau T[   VBIOS][0000:01:00.0] 0xf5ce[ ]: 	0x88888888
>nouveau T[   VBIOS][0000:01:00.0] 0xf5d2[ ]: 	0x88888888
>nouveau T[   VBIOS][0000:01:00.0] 0xf5d6[ ]: 	0x88888888
>nouveau T[   VBIOS][0000:01:00.0] 0xf5da[ ]: 	0x88888888
>nouveau T[   VBIOS][0000:01:00.0] 0xf5de[ ]: 	0x88888888
>nouveau T[   VBIOS][0000:01:00.0] 0xf5e2[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf5e2[ ]: IO_RESTRICT_PROG	R[0x100468] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf5ed[ ]: 	0x66666666 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf5f1[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf5f5[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf5f9[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf5fd[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf601[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf605[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf609[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf60d[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf60d[ ]: IO_RESTRICT_PROG	R[0x10046c] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf618[ ]: 	0x66666666 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf61c[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf620[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf624[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf628[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf62c[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf630[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf634[ ]: 	0x66666666
>nouveau T[   VBIOS][0000:01:00.0] 0xf638[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf638[ ]: ZM_REG	R[0x100480] = 0xbbbbbbbb
>nouveau T[   VBIOS][0000:01:00.0] 0xf641[ ]: ZM_REG	R[0x100484] = 0xbbbbbbbb
>nouveau T[   VBIOS][0000:01:00.0] 0xf64a[ ]: ZM_REG	R[0x100488] = 0xbbbbbbbb
>nouveau T[   VBIOS][0000:01:00.0] 0xf653[ ]: ZM_REG	R[0x10048c] = 0xbbbbbbbb
>nouveau T[   VBIOS][0000:01:00.0] 0xf65c[ ]: ZM_REG	R[0x100490] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf665[ ]: ZM_REG	R[0x100494] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf66e[ ]: ZM_REG	R[0x100498] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf677[ ]: ZM_REG	R[0x10049c] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf680[ ]: IO_RESTRICT_PROG	R[0x100458] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf68b[ ]: 	0x00000000 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf68f[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf693[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf697[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf69b[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf69f[ ]: 	0x00000011
>nouveau T[   VBIOS][0000:01:00.0] 0xf6a3[ ]: 	0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf6a7[ ]: 	0x00000011
>nouveau T[   VBIOS][0000:01:00.0] 0xf6ab[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf6ab[ ]: IO_RESTRICT_PROG	R[0x10045c] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf6b6[ ]: 	0x00001011 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf6ba[ ]: 	0x00001011
>nouveau T[   VBIOS][0000:01:00.0] 0xf6be[ ]: 	0x00001011
>nouveau T[   VBIOS][0000:01:00.0] 0xf6c2[ ]: 	0x00001011
>nouveau T[   VBIOS][0000:01:00.0] 0xf6c6[ ]: 	0x00001011
>nouveau T[   VBIOS][0000:01:00.0] 0xf6ca[ ]: 	0x00001011
>nouveau T[   VBIOS][0000:01:00.0] 0xf6ce[ ]: 	0x00001011
>nouveau T[   VBIOS][0000:01:00.0] 0xf6d2[ ]: 	0x00001011
>nouveau T[   VBIOS][0000:01:00.0] 0xf6d6[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf6d6[ ]: ZM_REG	R[0x100470] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf6df[ ]: IO_RESTRICT_PROG	R[0x100474] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf6ea[ ]: 	0x11111101 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf6ee[ ]: 	0x11113002
>nouveau T[   VBIOS][0000:01:00.0] 0xf6f2[ ]: 	0x11110004
>nouveau T[   VBIOS][0000:01:00.0] 0xf6f6[ ]: 	0x11111101
>nouveau T[   VBIOS][0000:01:00.0] 0xf6fa[ ]: 	0x11111101
>nouveau T[   VBIOS][0000:01:00.0] 0xf6fe[ ]: 	0x11110004
>nouveau T[   VBIOS][0000:01:00.0] 0xf702[ ]: 	0x11111101
>nouveau T[   VBIOS][0000:01:00.0] 0xf706[ ]: 	0x11110004
>nouveau T[   VBIOS][0000:01:00.0] 0xf70a[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf70a[ ]: ZM_REG	R[0x100080] = 0xf0000020
>nouveau T[   VBIOS][0000:01:00.0] 0xf713[ ]: ZM_REG	R[0x100084] = 0x0000001d
>nouveau T[   VBIOS][0000:01:00.0] 0xf71c[ ]: ZM_REG	R[0x100090] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf725[ ]: ZM_REG	R[0x1000a0] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf72e[ ]: ZM_REG	R[0x1000f0] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf737[ ]: DONE
>nouveau T[   VBIOS][0000:01:00.0] 0xf738[ ]: PLL2	R[0x680508] =PLL= 36000kHz
>nouveau T[   VBIOS][0000:01:00.0] 0xf741[ ]: ZM_REG	R[0x001088] = 0x000011f0
>nouveau T[   VBIOS][0000:01:00.0] 0xf74a[ ]: ZM_REG	R[0x00108c] = 0x000000d1
>nouveau T[   VBIOS][0000:01:00.0] 0xf753[ ]: NV_REG	R[0x001530] &= 0xfffff9ff |= 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf760[ ]: NV_REG	R[0x680880] &= 0xffffffff |= 0x10000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf76d[ ]: ZM_REG	R[0x680610] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf776[ ]: ZM_CR_GROUP
>nouveau T[   VBIOS][0000:01:00.0] 0xf778[ ]: 		C[0x38] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf77a[ ]: 		C[0x1a] = 0x3f
>nouveau T[   VBIOS][0000:01:00.0] 0xf77c[ ]: 		C[0x28] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf77e[ ]: 		C[0x33] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf780[ ]: 		C[0x21] = 0xfa
>nouveau T[   VBIOS][0000:01:00.0] 0xf782[ ]: CR		C[0x2b] &= 0x20 |= 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf786[ ]: ZM_CR_GROUP
>nouveau T[   VBIOS][0000:01:00.0] 0xf788[ ]: 		C[0x2c] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf78a[ ]: 		C[0x3a] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf78c[ ]: 		C[0x3b] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf78e[ ]: 		C[0x4a] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf790[ ]: 		C[0x4b] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf792[ ]: 		C[0x4c] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf794[ ]: CR_INDEX_ADDR C[57] C[58]
>nouveau T[   VBIOS][0000:01:00.0] 0xf799[ ]: 		[0x00] = 0x7f
>nouveau T[   VBIOS][0000:01:00.0] 0xf79a[ ]: 		[0x01] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf79b[ ]: 		[0x02] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf79c[ ]: 		[0x03] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf79d[ ]: 		[0x04] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf79e[ ]: 		[0x05] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf79f[ ]: 		[0x06] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf7a0[ ]: ZM_CR	C[0x43] = 0x01
>nouveau T[   VBIOS][0000:01:00.0] 0xf7a3[ ]: INDEX_IO	I[0x03d4][0x85] &= 0x00 |= 0xff
>nouveau T[   VBIOS][0000:01:00.0] 0xf7a9[ ]: INDEX_IO	I[0x03d4][0x86] &= 0x00 |= 0x01
>nouveau T[   VBIOS][0000:01:00.0] 0xf7af[ ]: ZM_CR	C[0x44] = 0x03
>nouveau T[   VBIOS][0000:01:00.0] 0xf7b2[ ]: ZM_CR	C[0x21] = 0xfa
>nouveau T[   VBIOS][0000:01:00.0] 0xf7b5[ ]: INDEX_IO	I[0x03d4][0x85] &= 0x00 |= 0xff
>nouveau T[   VBIOS][0000:01:00.0] 0xf7bb[ ]: INDEX_IO	I[0x03d4][0x86] &= 0x00 |= 0x01
>nouveau T[   VBIOS][0000:01:00.0] 0xf7c1[ ]: CR		C[0x2b] &= 0x10 |= 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf7c5[ ]: ZM_CR_GROUP
>nouveau T[   VBIOS][0000:01:00.0] 0xf7c7[ ]: 		C[0x2c] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf7c9[ ]: 		C[0x3a] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf7cb[ ]: 		C[0x3b] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf7cd[ ]: 		C[0x3c] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf7cf[ ]: 		C[0x4a] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf7d1[ ]: 		C[0x4b] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf7d3[ ]: 		C[0x4c] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf7d5[ ]: CR_INDEX_ADDR C[57] C[58]
>nouveau T[   VBIOS][0000:01:00.0] 0xf7da[ ]: 		[0x00] = 0x7f
>nouveau T[   VBIOS][0000:01:00.0] 0xf7db[ ]: 		[0x01] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf7dc[ ]: 		[0x02] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf7dd[ ]: ZM_CR	C[0x43] = 0x01
>nouveau T[   VBIOS][0000:01:00.0] 0xf7e0[ ]: ZM_CR	C[0x44] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf7e3[ ]: ZM_CR	C[0x52] = 0x04
>nouveau T[   VBIOS][0000:01:00.0] 0xf7e6[ ]: ZM_CR	C[0x53] = 0x40
>nouveau T[   VBIOS][0000:01:00.0] 0xf7e9[ ]: NV_REG	R[0x001584] &= 0xfff00000 |= 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf7f6[ ]: NV_REG	R[0x001588] &= 0xfffffffc |= 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf803[ ]: CONDITION	0x01
>nouveau T[   VBIOS][0000:01:00.0] 0xf805[ ]: 	[0x01] (R[0x000000] & 0x0000000f) == 0x00000002
>nouveau T[   VBIOS][0000:01:00.0] 0xf805[ ]: NV_REG	R[0x00158c] &= 0xfffffffc |= 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf812[ ]: NOT
>nouveau T[   VBIOS][0000:01:00.0] 0xf813[ ]: NV_REG	R[0x00158c] &= 0xfffffffc |= 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf820[ ]: RESUME
>nouveau T[   VBIOS][0000:01:00.0] 0xf821[ ]: ZM_REG	R[0x100210] = 0x80000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf82a[ ]: NV_REG	R[0x68052c] &= 0xfffffeff |= 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf837[ ]: NV_REG	R[0x68252c] &= 0xffffffff |= 0x00000101
>nouveau T[   VBIOS][0000:01:00.0] 0xf844[ ]: NV_REG	R[0x680848] &= 0xffffffff |= 0x00100000
>nouveau T[   VBIOS][0000:01:00.0] 0xf851[ ]: NV_REG	R[0x682848] &= 0xffffffff |= 0x00100000
>nouveau T[   VBIOS][0000:01:00.0] 0xf85e[ ]: ZM_REG	R[0x001200] = 0x0003103c
>nouveau T[   VBIOS][0000:01:00.0] 0xf867[ ]: DONE
>nouveau T[   VBIOS][0000:01:00.0] 0xf8c0[ ]: SUB_DIRECT	0xd4be
>nouveau T[   VBIOS][0000:01:00.0] 0xf8c3[ ]: IO_RESTRICT_PROG	R[0x1002c0] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf8ce[ ]: 	0x00000032 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf8d2[ ]: 	0x00000032
>nouveau T[   VBIOS][0000:01:00.0] 0xf8d6[ ]: 	0x00000802
>nouveau T[   VBIOS][0000:01:00.0] 0xf8da[ ]: 	0x00000032
>nouveau T[   VBIOS][0000:01:00.0] 0xf8de[ ]: 	0x00000032
>nouveau T[   VBIOS][0000:01:00.0] 0xf8e2[ ]: 	0x00000562
>nouveau T[   VBIOS][0000:01:00.0] 0xf8e6[ ]: 	0x00000032
>nouveau T[   VBIOS][0000:01:00.0] 0xf8ea[ ]: 	0x00000372
>nouveau T[   VBIOS][0000:01:00.0] 0xf8ee[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf8ee[ ]: IO_RESTRICT_PROG	R[0x1002c8] = ((0x03d4[0x3c] & 0x70) >> 4) [{
>nouveau T[   VBIOS][0000:01:00.0] 0xf8f9[ ]: 	0x00000032 *
>nouveau T[   VBIOS][0000:01:00.0] 0xf8fd[ ]: 	0x00000032
>nouveau T[   VBIOS][0000:01:00.0] 0xf901[ ]: 	0x00000802
>nouveau T[   VBIOS][0000:01:00.0] 0xf905[ ]: 	0x00000032
>nouveau T[   VBIOS][0000:01:00.0] 0xf909[ ]: 	0x00000032
>nouveau T[   VBIOS][0000:01:00.0] 0xf90d[ ]: 	0x00000562
>nouveau T[   VBIOS][0000:01:00.0] 0xf911[ ]: 	0x00000032
>nouveau T[   VBIOS][0000:01:00.0] 0xf915[ ]: 	0x00000372
>nouveau T[   VBIOS][0000:01:00.0] 0xf919[ ]: }]
>nouveau T[   VBIOS][0000:01:00.0] 0xf919[ ]: TIME	0x03e8
>nouveau T[   VBIOS][0000:01:00.0] 0xf91c[ ]: MACRO	0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf91c[ ]: 		R[0x1002d4] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf91e[ ]: REPEAT	0x0a
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: MACRO	0x02
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: 		R[0x1002d0] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf922[ ]: END_REPEAT
>nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x09
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: MACRO	0x02
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: 		R[0x1002d0] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf922[ ]: END_REPEAT
>nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x08
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: MACRO	0x02
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: 		R[0x1002d0] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf922[ ]: END_REPEAT
>nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x07
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: MACRO	0x02
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: 		R[0x1002d0] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf922[ ]: END_REPEAT
>nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x06
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: MACRO	0x02
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: 		R[0x1002d0] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf922[ ]: END_REPEAT
>nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x05
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: MACRO	0x02
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: 		R[0x1002d0] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf922[ ]: END_REPEAT
>nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x04
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: MACRO	0x02
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: 		R[0x1002d0] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf922[ ]: END_REPEAT
>nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x03
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: MACRO	0x02
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: 		R[0x1002d0] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf922[ ]: END_REPEAT
>nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: MACRO	0x02
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: 		R[0x1002d0] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf922[ ]: END_REPEAT
>nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: MACRO	0x02
>nouveau T[   VBIOS][0000:01:00.0] 0xf920[ ]: 		R[0x1002d0] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf922[ ]: END_REPEAT
>nouveau T[   VBIOS][0000:01:00.0] 0xf923[ ]: SUB	0x08
>nouveau T[   VBIOS][0000:01:00.0] 0xf925[ ]: TIME	0x0064
>nouveau T[   VBIOS][0000:01:00.0] 0xf928[ ]: MACRO	0x04
>nouveau T[   VBIOS][0000:01:00.0] 0xf928[ ]: 		R[0x1002dc] = 0x00000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf92a[ ]: SUB	0x07
>nouveau T[   VBIOS][0000:01:00.0] 0xf92c[ ]: TIME	0x03e8
>nouveau T[   VBIOS][0000:01:00.0] 0xf92f[ ]: MACRO	0x05
>nouveau T[   VBIOS][0000:01:00.0] 0xf92f[ ]: 		R[0x1002dc] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf931[ ]: SUB	0x08
>nouveau T[   VBIOS][0000:01:00.0] 0xf933[ ]: TIME	0x03e8
>nouveau T[   VBIOS][0000:01:00.0] 0xf936[ ]: ZM_REG	R[0x100210] = 0x80000001
>nouveau T[   VBIOS][0000:01:00.0] 0xf93f[ ]: ZM_REG	R[0x70fff0] = 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf948[ ]: COMPUTE_MEM
>nouveau T[   VBIOS][0000:01:00.0] 0xf949[ ]: INDEX_IO	I[0x03c4][0x01] &= 0xdf |= 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0xf94f[ ]: NV_REG	R[0x00c040] &= 0xfffff000 |= 0x0c080333
>nouveau T[   VBIOS][0000:01:00.0] 0xf95c[ ]: NV_REG	R[0x08813c] &= 0xf0ffffff |= 0x07000000
>nouveau T[   VBIOS][0000:01:00.0] 0xf969[ ]: NV_REG	R[0x088138] &= 0xe007ffff |= 0x1ff80000
>nouveau T[   VBIOS][0000:01:00.0] 0xf976[ ]: NV_REG	R[0x011014] &= 0xffff7fff |= 0x00008000
>nouveau T[   VBIOS][0000:01:00.0] 0xf983[ ]: DONE
>nouveau T[   VBIOS][0000:01:00.0] 0xf984[ ]: DONE
>nouveau D[ DEVINIT][0000:01:00.0] initialised
>nouveau T[    GPIO][0000:01:00.0] use(+1) == 1
>nouveau T[    GPIO][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 5
>nouveau T[    GPIO][0000:01:00.0] resetting...
>nouveau D[    GPIO][0000:01:00.0] reset
>nouveau D[    GPIO][0000:01:00.0] initialised
>nouveau T[     I2C][0000:01:00.0] use(+1) == 1
>nouveau T[     I2C][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 6
>nouveau T[     I2C][0000:01:00.0] resetting...
>nouveau D[     I2C][0000:01:00.0] reset
>nouveau D[     I2C][0000:01:00.0] initialised
>nouveau T[   CLOCK][0000:01:00.0] use(+1) == 1
>nouveau T[   CLOCK][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 7
>nouveau T[   CLOCK][0000:01:00.0] resetting...
>nouveau D[   CLOCK][0000:01:00.0] reset
>nouveau D[   CLOCK][0000:01:00.0] initialised
>nouveau T[  DEVICE][0000:01:00.0] inc() == 9
>nouveau D[     PMC][0000:01:00.0] created
>nouveau T[     PMC][0000:01:00.0] use(+1) == 1
>nouveau T[     PMC][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 8
>nouveau T[     PMC][0000:01:00.0] resetting...
>nouveau D[     PMC][0000:01:00.0] reset
>nouveau D[     PMC][0000:01:00.0] initialised
>nouveau T[  DEVICE][0000:01:00.0] inc() == 10
>nouveau D[    PBUS][0000:01:00.0] created
>nouveau T[    PBUS][0000:01:00.0] use(+1) == 1
>nouveau T[    PBUS][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 9
>nouveau T[    PBUS][0000:01:00.0] resetting...
>nouveau D[    PBUS][0000:01:00.0] reset
>nouveau D[    PBUS][0000:01:00.0] initialised
>nouveau T[  DEVICE][0000:01:00.0] inc() == 11
>nouveau D[  PTIMER][0000:01:00.0] created
>nouveau T[  PTIMER][0000:01:00.0] use(+1) == 1
>nouveau T[  PTIMER][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 10
>nouveau T[  PTIMER][0000:01:00.0] resetting...
>nouveau D[  PTIMER][0000:01:00.0] reset
>nouveau D[  PTIMER][0000:01:00.0] input frequency : 27000Hz
>nouveau D[  PTIMER][0000:01:00.0] input multiplier: 3
>nouveau D[  PTIMER][0000:01:00.0] numerator       : 0x00000144
>nouveau D[  PTIMER][0000:01:00.0] denominator     : 0x0000007d
>nouveau D[  PTIMER][0000:01:00.0] timer frequency : 31250Hz
>nouveau D[  PTIMER][0000:01:00.0] initialised
>nouveau T[  DEVICE][0000:01:00.0] inc() == 12
>nouveau  [     PFB][0000:01:00.0] RAM type: GDDR3
>nouveau  [     PFB][0000:01:00.0] RAM size: 128 MiB
>nouveau  [     PFB][0000:01:00.0]    ZCOMP: 378880 tags
>nouveau D[     PFB][0000:01:00.0] created
>nouveau T[     PFB][0000:01:00.0] use(+1) == 1
>nouveau T[     PFB][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 11
>nouveau T[     PFB][0000:01:00.0] resetting...
>nouveau D[     PFB][0000:01:00.0] reset
>nouveau D[     PFB][0000:01:00.0] initialised
>nouveau T[  DEVICE][0000:01:00.0] inc() == 13
>nouveau T[  DEVICE][0000:01:00.0] inc() == 14
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 2
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][df321300] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df321300] inc() == 2
>nouveau T[  DEVICE][0000:01:00.0] inc() == 15
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df321300] dec() == 1
>nouveau D[  DEVICE][0000:01:00.0][0x02000000][df1eaf00] created
>nouveau T[  DEVICE][0000:01:00.0] inc() == 16
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 2
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][df321380] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df321380] inc() == 2
>nouveau T[  DEVICE][0000:01:00.0] inc() == 17
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df321380] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0] inc() == 18
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 2
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][df321400] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df321400] inc() == 2
>nouveau T[  DEVICE][0000:01:00.0] inc() == 19
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df321400] dec() == 1
>nouveau D[  DEVICE][0000:01:00.0][0x02000000][df31c000] created
>nouveau T[  DEVICE][0000:01:00.0] inc() == 20
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 2
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][df321480] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df321480] inc() == 2
>nouveau T[  DEVICE][0000:01:00.0] inc() == 21
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df321480] dec() == 1
>nouveau D[  DEVICE][0000:01:00.0][0x02000000][df31c060] created
>nouveau D[ INSTMEM][0000:01:00.0] created
>nouveau T[ INSTMEM][0000:01:00.0] use(+1) == 1
>nouveau T[ INSTMEM][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 12
>nouveau T[ INSTMEM][0000:01:00.0] resetting...
>nouveau D[ INSTMEM][0000:01:00.0] reset
>nouveau D[ INSTMEM][0000:01:00.0] initialised
>nouveau T[  DEVICE][0000:01:00.0] inc() == 22
>nouveau T[  DEVICE][0000:01:00.0] inc() == 23
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 2
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][df321540] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df321540] inc() == 2
>nouveau T[  DEVICE][0000:01:00.0] inc() == 24
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df321540] dec() == 1
>nouveau D[  DEVICE][0000:01:00.0][0x02000000][df31c0c0] created
>nouveau D[ PCIGART][0000:01:00.0] created
>nouveau D[ PCIGART][0000:01:00.0] created
>nouveau T[ PCIGART][0000:01:00.0] use(+1) == 1
>nouveau T[ PCIGART][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 13
>nouveau T[ PCIGART][0000:01:00.0] resetting...
>nouveau D[ PCIGART][0000:01:00.0] reset
>nouveau D[ PCIGART][0000:01:00.0] initialised
>nouveau T[  DEVICE][0000:01:00.0] inc() == 25
>nouveau D[     I2C][0000:01:00.0] probing monitoring devices on bus: 2
>nouveau D[     I2C][0000:01:00.0] no devices found.
>nouveau  [  PTHERM][0000:01:00.0] FAN control: PWM
>nouveau  [  PTHERM][0000:01:00.0] Thermal management: disabled
>nouveau D[  PTHERM][0000:01:00.0] created
>nouveau T[  PTHERM][0000:01:00.0] use(+1) == 1
>nouveau T[  PTHERM][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 14
>nouveau T[  PTHERM][0000:01:00.0] resetting...
>nouveau D[  PTHERM][0000:01:00.0] reset
>nouveau  [  PTHERM][0000:01:00.0] programmed thresholds [ 90(2), 95(3), 145(2), 135(5) ]
>nouveau D[  PTHERM][0000:01:00.0] initialised
>nouveau T[  DEVICE][0000:01:00.0] inc() == 26
>nouveau D[  DMAOBJ][0000:01:00.0] created
>nouveau T[  DMAOBJ][0000:01:00.0] resetting...
>nouveau D[  DMAOBJ][0000:01:00.0] reset
>nouveau T[  DEVICE][0000:01:00.0] inc() == 27
>nouveau T[  DEVICE][0000:01:00.0][0x0200abcd][df1eaf60] inc() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x02000000][df31c000] inc() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x02000000][df31c060] inc() == 2
>nouveau D[   PFIFO][0000:01:00.0] created
>nouveau T[   PFIFO][0000:01:00.0] resetting...
>nouveau D[   PFIFO][0000:01:00.0] reset
>nouveau T[  DEVICE][0000:01:00.0] inc() == 28
>nouveau D[      SW][0000:01:00.0] created
>nouveau T[      SW][0000:01:00.0] resetting...
>nouveau D[      SW][0000:01:00.0] reset
>nouveau T[  DEVICE][0000:01:00.0] inc() == 29
>nouveau D[  PGRAPH][0000:01:00.0] created
>nouveau T[  PGRAPH][0000:01:00.0] resetting...
>nouveau D[  PGRAPH][0000:01:00.0] reset
>nouveau T[  DEVICE][0000:01:00.0] inc() == 30
>nouveau D[   PMPEG][0000:01:00.0] created
>nouveau T[   PMPEG][0000:01:00.0] resetting...
>nouveau D[   PMPEG][0000:01:00.0] reset
>nouveau T[  DEVICE][0000:01:00.0] inc() == 31
>nouveau D[ DISPLAY][0000:01:00.0] created
>nouveau T[ DISPLAY][0000:01:00.0] resetting...
>nouveau D[ DISPLAY][0000:01:00.0] reset
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1da600] created
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] use(+1) == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] initialising...
>nouveau T[     DRM] use(+1) == 3
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 15
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1da600] initialised
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 2
>nouveau T[     DRM] 0xffffffff:0xdddddddd created
>nouveau T[     DRM] 0xffffffff:0xdddddddd init running
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] use(+1) == 2
>nouveau T[     DRM] 0xffffffff:0xdddddddd init children
>nouveau T[     DRM] 0xffffffff:0xdddddddd init completed
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] use(-1) == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 1
>nouveau T[     DRM] dec() == 4
>nouveau T[     DRM] dec() == 3
>agpgart-via 0000:00:00.0: AGP 2.0 bridge
>agpgart-via 0000:00:00.0: putting AGP V2 device into 4x mode
>nouveau 0000:01:00.0: putting AGP V2 device into 4x mode
>[TTM] Zone  kernel: Available graphics memory: 256202 kiB
>[TTM] Initializing pool allocator
>nouveau  [     DRM] VRAM: 124 MiB
>nouveau  [     DRM] GART: 16 MiB
>nouveau  [     DRM] TMDS table version 1.1
>nouveau  [     DRM] DCB version 3.0
>nouveau  [     DRM] DCB outp 00: 01000300 00000028
>nouveau  [     DRM] DCB outp 01: 01000302 00000000
>nouveau  [     DRM] DCB outp 02: 04010312 00000020
>nouveau  [     DRM] DCB outp 03: 04010310 00000028
>nouveau  [     DRM] DCB outp 04: 020203f1 0080c083
>nouveau  [     DRM] Saving VGA fonts
>[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
>[drm] No driver support for vblank timestamp query.
>nouveau  [     DRM] 0xD434: Parsing digital output script table
>nouveau T[   VBIOS][0000:01:00.0] 0xd434[0]: SUB_DIRECT	0xd45e
>nouveau T[   VBIOS][0000:01:00.0] 0xd45e[1]: NV_REG	R[0x680880] &= 0xdfffffff |= 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xd46b[1]: DONE
>nouveau T[   VBIOS][0000:01:00.0] 0xd437[0]: SUB_DIRECT	0x9619
>nouveau T[   VBIOS][0000:01:00.0] 0x9619[1]: SUB_DIRECT	0x96a5
>nouveau T[   VBIOS][0000:01:00.0] 0x96a5[2]: TMDS_ZM_GROUP	T[0x80]
>nouveau T[   VBIOS][0000:01:00.0] 0x96a8[2]: 	[0x04] = 0x80
>nouveau T[   VBIOS][0000:01:00.0] 0x96aa[2]: 	[0x05] = 0x6e
>nouveau T[   VBIOS][0000:01:00.0] 0x96ac[2]: 	[0x2f] = 0xff
>nouveau T[   VBIOS][0000:01:00.0] 0x96ae[2]: 	[0x30] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0x96b0[2]: 	[0x31] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0x96b2[2]: 	[0x32] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0x96b4[2]: 	[0x33] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0x96b6[2]: TMDS_ZM_GROUP	T[0x81]
>nouveau T[   VBIOS][0000:01:00.0] 0x96b9[2]: 	[0x04] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0x96bb[2]: DONE
>nouveau T[   VBIOS][0000:01:00.0] 0x961c[1]: TMDS_ZM_GROUP	T[0x80]
>nouveau T[   VBIOS][0000:01:00.0] 0x961f[1]: 	[0x00] = 0xcc
>nouveau T[   VBIOS][0000:01:00.0] 0x9621[1]: 	[0x01] = 0x42
>nouveau T[   VBIOS][0000:01:00.0] 0x9623[1]: 	[0x02] = 0x29
>nouveau T[   VBIOS][0000:01:00.0] 0x9625[1]: 	[0x2e] = 0x85
>nouveau T[   VBIOS][0000:01:00.0] 0x9627[1]: SUB_DIRECT	0x96bc
>nouveau T[   VBIOS][0000:01:00.0] 0x96bc[2]: TMDS_ZM_GROUP	T[0x80]
>nouveau T[   VBIOS][0000:01:00.0] 0x96bf[2]: 	[0x2f] = 0x08
>nouveau T[   VBIOS][0000:01:00.0] 0x96c1[2]: TIME	0xc350
>nouveau T[   VBIOS][0000:01:00.0] 0x96c4[2]: TMDS_ZM_GROUP	T[0x80]
>nouveau T[   VBIOS][0000:01:00.0] 0x96c7[2]: 	[0x2f] = 0x21
>nouveau T[   VBIOS][0000:01:00.0] 0x96c9[2]: 	[0x2c] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0x96cb[2]: DONE
>nouveau T[   VBIOS][0000:01:00.0] 0x962a[1]: DONE
>nouveau T[   VBIOS][0000:01:00.0] 0xd43a[0]: DONE
>nouveau  [     DRM] 0xD484: Parsing digital output script table
>nouveau T[   VBIOS][0000:01:00.0] 0xd484[0]: SUB_DIRECT	0xd4ae
>nouveau T[   VBIOS][0000:01:00.0] 0xd4ae[1]: NV_REG	R[0x682880] &= 0xcfffffff |= 0x00000000
>nouveau T[   VBIOS][0000:01:00.0] 0xd4bb[1]: DONE
>nouveau T[   VBIOS][0000:01:00.0] 0xd487[0]: SUB_DIRECT	0x9619
>nouveau T[   VBIOS][0000:01:00.0] 0x9619[1]: SUB_DIRECT	0x96a5
>nouveau T[   VBIOS][0000:01:00.0] 0x96a5[2]: TMDS_ZM_GROUP	T[0x80]
>nouveau T[   VBIOS][0000:01:00.0] 0x96a8[2]: 	[0x04] = 0x80
>nouveau T[   VBIOS][0000:01:00.0] 0x96aa[2]: 	[0x05] = 0x6e
>nouveau T[   VBIOS][0000:01:00.0] 0x96ac[2]: 	[0x2f] = 0xff
>nouveau T[   VBIOS][0000:01:00.0] 0x96ae[2]: 	[0x30] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0x96b0[2]: 	[0x31] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0x96b2[2]: 	[0x32] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0x96b4[2]: 	[0x33] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0x96b6[2]: TMDS_ZM_GROUP	T[0x81]
>nouveau T[   VBIOS][0000:01:00.0] 0x96b9[2]: 	[0x04] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0x96bb[2]: DONE
>nouveau T[   VBIOS][0000:01:00.0] 0x961c[1]: TMDS_ZM_GROUP	T[0x80]
>nouveau T[   VBIOS][0000:01:00.0] 0x961f[1]: 	[0x00] = 0xcc
>nouveau T[   VBIOS][0000:01:00.0] 0x9621[1]: 	[0x01] = 0x42
>nouveau T[   VBIOS][0000:01:00.0] 0x9623[1]: 	[0x02] = 0x29
>nouveau T[   VBIOS][0000:01:00.0] 0x9625[1]: 	[0x2e] = 0x85
>nouveau T[   VBIOS][0000:01:00.0] 0x9627[1]: SUB_DIRECT	0x96bc
>nouveau T[   VBIOS][0000:01:00.0] 0x96bc[2]: TMDS_ZM_GROUP	T[0x80]
>nouveau T[   VBIOS][0000:01:00.0] 0x96bf[2]: 	[0x2f] = 0x08
>nouveau T[   VBIOS][0000:01:00.0] 0x96c1[2]: TIME	0xc350
>nouveau T[   VBIOS][0000:01:00.0] 0x96c4[2]: TMDS_ZM_GROUP	T[0x80]
>nouveau T[   VBIOS][0000:01:00.0] 0x96c7[2]: 	[0x2f] = 0x21
>nouveau T[   VBIOS][0000:01:00.0] 0x96c9[2]: 	[0x2c] = 0x00
>nouveau T[   VBIOS][0000:01:00.0] 0x96cb[2]: DONE
>nouveau T[   VBIOS][0000:01:00.0] 0x962a[1]: DONE
>nouveau T[   VBIOS][0000:01:00.0] 0xd48a[0]: DONE
>nouveau  [     DRM] 2 available performance level(s)
>nouveau  [     DRM] 0: core 300MHz shader 300MHz memory 1000MHz voltage 1300mV fanspeed 100%
>nouveau  [     DRM] 1: core 500MHz shader 500MHz memory 1000MHz voltage 1400mV fanspeed 100%
>nouveau  [     DRM] c: core 100MHz shader 100MHz memory 501MHz voltage 1300mV fanspeed 100%
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 16
>nouveau T[  DMAOBJ][0000:01:00.0] resetting...
>nouveau D[  DMAOBJ][0000:01:00.0] reset
>nouveau D[  DMAOBJ][0000:01:00.0] initialised
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] initialising...
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] use(+1) == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] inc() == 2
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 created
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] use(+1) == 2
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 init children
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1da600] illegal class 0xa06f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1da600] illegal class 0x906f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1da600] illegal class 0x826f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1da600] illegal class 0x506f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 3
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 fini children
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 fini running
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] use(-1) == 0
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] stopping...
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 0
>nouveau T[  DMAOBJ][0000:01:00.0] stopping...
>nouveau T[  DEVICE][0000:01:00.0] use(-1) == 15
>nouveau D[  DMAOBJ][0000:01:00.0] stopped
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] use(-1) == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] stopped
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 fini completed
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 destroy running
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 destroy completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] dec() == 0
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][df318c00] destroying
>nouveau T[  DMAOBJ][0000:01:00.0] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 16
>nouveau T[  DMAOBJ][0000:01:00.0] resetting...
>nouveau D[  DMAOBJ][0000:01:00.0] reset
>nouveau D[  DMAOBJ][0000:01:00.0] initialised
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][df318cc0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318cc0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318cc0] initialising...
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] use(+1) == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][df318cc0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318cc0] inc() == 2
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 created
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318cc0] use(+1) == 2
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 init children
>nouveau T[     DRM] 0xdddddddd:0xbbbb0000 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318cc0] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318cc0] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 3
>nouveau T[   PFIFO][0000:01:00.0] use(+1) == 1
>nouveau T[   PFIFO][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 17
>nouveau T[   PFIFO][0000:01:00.0] resetting...
>nouveau D[   PFIFO][0000:01:00.0] reset
>nouveau D[   PFIFO][0000:01:00.0] initialised
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 4
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 3
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][df318d40] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df318d40] inc() == 2
>nouveau T[   PFIFO][0000:01:00.0] inc() == 2
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df318d40] dec() == 1
>nouveau D[   PFIFO][0000:01:00.0][0x03004013][df31cf00] created
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][df31cf00] inc() == 2
>nouveau T[   PFIFO][0000:01:00.0] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][df318cc0] inc() == 2
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][df31cf00] inc() == 4
>nouveau T[   PFIFO][0000:01:00.0] inc() == 4
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][df31cf00] dec() == 3
>nouveau D[   PFIFO][0000:01:00.0][0x02000000][df31cf60] created
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][df176e00] created
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] use(+1) == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][df31cf00] use(+1) == 1
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][df31cf00] initialising...
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df318d40] use(+1) == 1
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][df318d40] initialising...
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] use(+1) == 3
>nouveau T[ INSTMEM][0000:01:00.0] use(+1) == 2
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][df318d40] initialised
>nouveau T[   PFIFO][0000:01:00.0] use(+1) == 2
>nouveau D[   PFIFO][0000:01:00.0][0x03004013][df31cf00] initialised
>nouveau T[   PFIFO][0000:01:00.0] use(+1) == 3
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][df176e00] initialised
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 2
>nouveau T[     DRM] 0xdddddddd:0xcccc0000 created
>nouveau T[     DRM] 0xdddddddd:0xcccc0000 init running
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] use(+1) == 2
>nouveau T[     DRM] 0xdddddddd:0xcccc0000 init children
>nouveau T[     DRM] 0xdddddddd:0xcccc0000 init completed
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] use(-1) == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][df31cf00] dec() == 2
>nouveau T[   PFIFO][0000:01:00.0] use(-1) == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] dec() == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 2
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][df318f00] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][df318f00] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f000] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][df318f00] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f000] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f000] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f000] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][df318f00] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][df318f00] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] use(+1) == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 3
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][df318f00] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 4
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f000] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f000] inc() == 2
>nouveau T[     DRM] 0xcccc0000:0x80000002 created
>nouveau T[     DRM] 0xcccc0000:0x80000002 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f000] use(+1) == 2
>nouveau T[     DRM] 0xcccc0000:0x80000002 init children
>nouveau T[     DRM] 0xcccc0000:0x80000002 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f000] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f000] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 2
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 4
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 4
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 5
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 5
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][df318fc0] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 6
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][df318fc0] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f060] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][df318fc0] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f060] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f060] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f060] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][df318fc0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][df318fc0] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] use(+1) == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 5
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][df318fc0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 6
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f060] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f060] inc() == 2
>nouveau T[     DRM] 0xcccc0000:0x80000003 created
>nouveau T[     DRM] 0xcccc0000:0x80000003 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f060] use(+1) == 2
>nouveau T[     DRM] 0xcccc0000:0x80000003 init children
>nouveau T[     DRM] 0xcccc0000:0x80000003 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f060] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f060] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 5
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 4
>nouveau T[      SW][0000:01:00.0] use(+1) == 1
>nouveau T[      SW][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 18
>nouveau T[      SW][0000:01:00.0] resetting...
>nouveau D[      SW][0000:01:00.0] reset
>nouveau D[      SW][0000:01:00.0] initialised
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 5
>nouveau T[      SW][0000:01:00.0] inc() == 2
>nouveau D[      SW][0000:01:00.0][0x01000414][df1ddcc0] created
>nouveau T[      SW][0000:01:00.0][0x01000414][df1ddcc0] inc() == 2
>nouveau T[      SW][0000:01:00.0] inc() == 3
>nouveau D[      SW][0000:01:00.0][0x0000016e][df1b1fc0] created
>nouveau T[      SW][0000:01:00.0][0x0000016e][df1b1fc0] use(+1) == 1
>nouveau T[      SW][0000:01:00.0][0x0000016e][df1b1fc0] initialising...
>nouveau T[      SW][0000:01:00.0][0x01000414][df1ddcc0] use(+1) == 1
>nouveau T[      SW][0000:01:00.0][0x01000414][df1ddcc0] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] use(+1) == 4
>nouveau T[      SW][0000:01:00.0] use(+1) == 2
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][df176e00] attached SW context
>nouveau D[      SW][0000:01:00.0][0x01000414][df1ddcc0] initialised
>nouveau T[      SW][0000:01:00.0] use(+1) == 3
>nouveau D[      SW][0000:01:00.0][0x0000016e][df1b1fc0] initialised
>nouveau T[      SW][0000:01:00.0][0x0000016e][df1b1fc0] inc() == 2
>nouveau T[     DRM] 0xcccc0000:0x8000000e created
>nouveau T[     DRM] 0xcccc0000:0x8000000e init running
>nouveau T[      SW][0000:01:00.0][0x0000016e][df1b1fc0] use(+1) == 2
>nouveau T[     DRM] 0xcccc0000:0x8000000e init children
>nouveau T[     DRM] 0xcccc0000:0x8000000e init completed
>nouveau T[      SW][0000:01:00.0][0x0000016e][df1b1fc0] use(-1) == 1
>nouveau T[      SW][0000:01:00.0][0x0000016e][df1b1fc0] dec() == 1
>nouveau T[      SW][0000:01:00.0][0x01000414][df1ddcc0] dec() == 1
>nouveau T[      SW][0000:01:00.0] use(-1) == 2
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 4
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 5
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 7
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 7
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddfa00c0] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 8
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddfa00c0] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f0c0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddfa00c0] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f0c0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f0c0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f0c0] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddfa00c0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddfa00c0] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] use(+1) == 5
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 7
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddfa00c0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 8
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f0c0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f0c0] inc() == 2
>nouveau T[     DRM] 0xcccc0000:0x8000000f created
>nouveau T[     DRM] 0xcccc0000:0x8000000f init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f0c0] use(+1) == 2
>nouveau T[     DRM] 0xcccc0000:0x8000000f init children
>nouveau T[     DRM] 0xcccc0000:0x8000000f init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f0c0] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f0c0] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 6
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 5
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1da600] inc() == 4
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 4
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][ddfa0180] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddfa0180] inc() == 2
>nouveau T[  DEVICE][0000:01:00.0] inc() == 32
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddfa0180] dec() == 1
>nouveau D[  DEVICE][0000:01:00.0][0x02000000][ddf9f120] created
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 6
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 8
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 8
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 9
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddfa0200] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 10
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddfa0200] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f180] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddfa0200] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f180] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f180] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f180] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddfa0200] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddfa0200] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] use(+1) == 6
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 9
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][ddfa0200] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 10
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f180] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f180] inc() == 2
>nouveau T[     DRM] 0xcccc0000:0x80000006 created
>nouveau T[     DRM] 0xcccc0000:0x80000006 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f180] use(+1) == 2
>nouveau T[     DRM] 0xcccc0000:0x80000006 init children
>nouveau T[     DRM] 0xcccc0000:0x80000006 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f180] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddf9f180] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 7
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 7
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][df176e00] illegal class 0xa0b5
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 7
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][df176e00] illegal class 0x90b8
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 7
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][df176e00] illegal class 0x90b5
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 7
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][df176e00] illegal class 0x85b5
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 7
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][df176e00] illegal class 0x74c1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 7
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][df176e00] illegal class 0x9039
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 7
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][df176e00] illegal class 0x5039
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 7
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0] initialising...
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 19
>nouveau T[  PGRAPH][0000:01:00.0] resetting...
>nouveau D[  PGRAPH][0000:01:00.0] reset
>nouveau D[  PGRAPH][0000:01:00.0] initialised
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 8
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 5
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][ddfa02c0] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddfa02c0] inc() == 2
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 2
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddfa02c0] dec() == 1
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] inc() == 3
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 3
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 2
>nouveau D[  PGRAPH][0000:01:00.0][0x02000039][ddf9f1e0] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][ddf9f1e0] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][ddf9f1e0] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] initialising...
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddfa02c0] use(+1) == 1
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddfa02c0] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] use(+1) == 7
>nouveau T[ INSTMEM][0000:01:00.0] use(+1) == 3
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][ddfa02c0] initialised
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 2
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][df176e00] attached PGRAPH context
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] initialised
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 3
>nouveau D[  PGRAPH][0000:01:00.0][0x02000039][ddf9f1e0] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][ddf9f1e0] inc() == 2
>nouveau T[     DRM] 0xcccc0000:0x00000039 created
>nouveau T[     DRM] 0xcccc0000:0x00000039 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][ddf9f1e0] use(+1) == 2
>nouveau T[     DRM] 0xcccc0000:0x00000039 init children
>nouveau T[     DRM] 0xcccc0000:0x00000039 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][ddf9f1e0] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][ddf9f1e0] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 2
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 7
>nouveau  [     DRM] MM: using M2MF for buffer copies
>nouveau  [     DRM] Setting dpms mode 3 on TV encoder (output 4)
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 3
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] inc() == 4
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 4
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 3
>nouveau D[  PGRAPH][0000:01:00.0][0x02000062][ddf9f2a0] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][ddf9f2a0] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][ddf9f2a0] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] use(+1) == 2
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 4
>nouveau D[  PGRAPH][0000:01:00.0][0x02000062][ddf9f2a0] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][ddf9f2a0] inc() == 2
>nouveau T[     DRM] 0xcccc0000:0x80000008 created
>nouveau T[     DRM] 0xcccc0000:0x80000008 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][ddf9f2a0] use(+1) == 2
>nouveau T[     DRM] 0xcccc0000:0x80000008 init children
>nouveau T[     DRM] 0xcccc0000:0x80000008 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][ddf9f2a0] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][ddf9f2a0] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 2
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 4
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] inc() == 5
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 5
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 4
>nouveau D[  PGRAPH][0000:01:00.0][0x02000019][ddf9f300] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000019][ddf9f300] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000019][ddf9f300] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] use(+1) == 3
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 5
>nouveau D[  PGRAPH][0000:01:00.0][0x02000019][ddf9f300] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000019][ddf9f300] inc() == 2
>nouveau T[     DRM] 0xcccc0000:0x8000000b created
>nouveau T[     DRM] 0xcccc0000:0x8000000b init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000019][ddf9f300] use(+1) == 2
>nouveau T[     DRM] 0xcccc0000:0x8000000b init children
>nouveau T[     DRM] 0xcccc0000:0x8000000b init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000019][ddf9f300] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000019][ddf9f300] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 3
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 4
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 5
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] inc() == 6
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 6
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 5
>nouveau D[  PGRAPH][0000:01:00.0][0x02000043][ddf9f360] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000043][ddf9f360] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000043][ddf9f360] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] use(+1) == 4
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 6
>nouveau D[  PGRAPH][0000:01:00.0][0x02000043][ddf9f360] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000043][ddf9f360] inc() == 2
>nouveau T[     DRM] 0xcccc0000:0x80000009 created
>nouveau T[     DRM] 0xcccc0000:0x80000009 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000043][ddf9f360] use(+1) == 2
>nouveau T[     DRM] 0xcccc0000:0x80000009 init children
>nouveau T[     DRM] 0xcccc0000:0x80000009 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000043][ddf9f360] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000043][ddf9f360] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 4
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 5
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 6
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] inc() == 7
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 7
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 6
>nouveau D[  PGRAPH][0000:01:00.0][0x02000044][ddf9f3c0] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000044][ddf9f3c0] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000044][ddf9f3c0] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] use(+1) == 5
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 7
>nouveau D[  PGRAPH][0000:01:00.0][0x02000044][ddf9f3c0] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000044][ddf9f3c0] inc() == 2
>nouveau T[     DRM] 0xcccc0000:0x8000000a created
>nouveau T[     DRM] 0xcccc0000:0x8000000a init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000044][ddf9f3c0] use(+1) == 2
>nouveau T[     DRM] 0xcccc0000:0x8000000a init children
>nouveau T[     DRM] 0xcccc0000:0x8000000a init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000044][ddf9f3c0] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000044][ddf9f3c0] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 5
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 7
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 7
>nouveau D[  PGRAPH][0000:01:00.0][0x0200004a][ddf9f420] created
>nouveau T[  PGRAPH][0000:01:00.0][0x0200004a][ddf9f420] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200004a][ddf9f420] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] use(+1) == 6
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 8
>nouveau D[  PGRAPH][0000:01:00.0][0x0200004a][ddf9f420] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x0200004a][ddf9f420] inc() == 2
>nouveau T[     DRM] 0xcccc0000:0x8000000c created
>nouveau T[     DRM] 0xcccc0000:0x8000000c init running
>nouveau T[  PGRAPH][0000:01:00.0][0x0200004a][ddf9f420] use(+1) == 2
>nouveau T[     DRM] 0xcccc0000:0x8000000c init children
>nouveau T[     DRM] 0xcccc0000:0x8000000c init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x0200004a][ddf9f420] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200004a][ddf9f420] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 6
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 8
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] inc() == 9
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 9
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 8
>nouveau D[  PGRAPH][0000:01:00.0][0x0200009f][ddf9f480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x0200009f][ddf9f480] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200009f][ddf9f480] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] use(+1) == 7
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 9
>nouveau D[  PGRAPH][0000:01:00.0][0x0200009f][ddf9f480] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x0200009f][ddf9f480] inc() == 2
>nouveau T[     DRM] 0xcccc0000:0x8000000d created
>nouveau T[     DRM] 0xcccc0000:0x8000000d init running
>nouveau T[  PGRAPH][0000:01:00.0][0x0200009f][ddf9f480] use(+1) == 2
>nouveau T[     DRM] 0xcccc0000:0x8000000d init children
>nouveau T[     DRM] 0xcccc0000:0x8000000d init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x0200009f][ddf9f480] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200009f][ddf9f480] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1ddc00] dec() == 7
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 8
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][df176e00] dec() == 7
>nouveau  [     DRM] allocated 1280x1024 fb: 0x9000, bo df1dbc00
>fb0: nouveaufb frame buffer device
>drm: registered panic notifier
>[drm] Initialized nouveau 1.1.0 20120801 for 0000:01:00.0 on minor 0
>parport_pc: VIA 686A/8231 detected
>parport_pc: probing current configuration
>parport_pc: Current parallel port base: 0x0
>parport_pc: VIA parallel port disabled in BIOS
>ide-cd driver 5.00
>ide-cd: hdb: ATAPI 40X DVD-ROM DVD-R CD-R/RW drive, 2048kB Cache
>cdrom: Uniform CD-ROM driver Revision: 3.20
>vmalloc: allocation failure: 0 bytes
>modprobe: page allocation failure: order:0, mode:0xd2
>Pid: 119, comm: modprobe Not tainted 3.7.0-small-00147-ga6f3b00 #34
>Call Trace:
> [<c0153724>] ? 0xc0153724
> [<c0144e07>] ? 0xc0144e07
> [<c0169155>] ? 0xc0169155
> [<c0118690>] ? 0xc0118690
> [<c0144e07>] ? 0xc0144e07
> [<c0144e07>] ? 0xc0144e07
> [<c01453dc>] ? 0xc01453dc
> [<c0119574>] ? 0xc0119574
> [<c0145cb8>] ? 0xc0145cb8
> [<c016fe7d>] ? 0xc016fe7d
> [<c02e9608>] ? 0xc02e9608
>Mem-Info:
>DMA per-cpu:
>CPU    0: hi:    0, btch:   1 usd:   0
>Normal per-cpu:
>CPU    0: hi:  186, btch:  31 usd: 111
>active_anon:398 inactive_anon:4 isolated_anon:0
> active_file:854 inactive_file:2168 isolated_file:0
> unevictable:0 dirty:0 writeback:0 unstable:0
> free:122340 slab_reclaimable:216 slab_unreclaimable:360
> mapped:388 shmem:11 pagetables:32 bounce:0
> free_cma:0
>DMA free:13192kB min:84kB low:104kB high:124kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:15804kB mlocked:0kB dirty:0kB writeback:0kB mapped:0kB shmem:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 492 492
>Normal free:476168kB min:2792kB low:3488kB high:4188kB active_anon:1592kB inactive_anon:16kB active_file:3416kB inactive_file:8672kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:503872kB mlocked:0kB dirty:0kB writeback:0kB mapped:1552kB shmem:44kB slab_reclaimable:864kB slab_unreclaimable:1440kB kernel_stack:224kB pagetables:128kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 0 0
>DMA: 2*4kB 2*8kB 1*16kB 5*32kB 5*64kB 3*128kB 2*256kB 1*512kB 1*1024kB 1*2048kB 2*4096kB = 13192kB
>Normal: 16*4kB 5*8kB 0*16kB 1*32kB 2*64kB 2*128kB 2*256kB 0*512kB 2*1024kB 3*2048kB 114*4096kB = 476168kB
>3034 total pagecache pages
>0 pages in swap cache
>Swap cache stats: add 0, delete 0, find 0/0
>Free swap  = 0kB
>Total swap = 0kB
>131040 pages RAM
>2943 pages reserved
>2411 pages shared
>3956 pages non-shared
>ACPI: bus type usb registered
>usbcore: registered new interface driver usbfs
>usbcore: registered new interface driver hub
>usbcore: registered new device driver usb
>ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>ehci_hcd 0000:00:0a.3: EHCI Host Controller
>ehci_hcd 0000:00:0a.3: new USB bus registered, assigned bus number 1
>ehci_hcd 0000:00:0a.3: debug port 1
>ehci_hcd 0000:00:0a.3: irq 18, io mem 0xdffffb00
>ehci_hcd 0000:00:0a.3: USB 2.0 started, EHCI 1.00
>hub 1-0:1.0: USB hub found
>hub 1-0:1.0: 6 ports detected
>uhci_hcd: USB Universal Host Controller Interface driver
>uhci_hcd 0000:00:07.2: UHCI Host Controller
>uhci_hcd 0000:00:07.2: new USB bus registered, assigned bus number 2
>uhci_hcd 0000:00:07.2: irq 11, io base 0x0000bc00
>hub 2-0:1.0: USB hub found
>hub 2-0:1.0: 2 ports detected
>ACPI Warning: 0x00000c00-0x00000c7f SystemIO conflicts with Region \_TZ_.TSN1 1 (20120913/utaddress-251)
>ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
>ACPI: PCI Interrupt Link [LNKC] enabled at IRQ 10
>snd_via82xx 0000:00:07.5: VIA VLink IRQ fixup, from 9 to 10
>snd_via82xx 0000:00:07.5: setting latency timer to 64
>usb 2-2: new low-speed USB device number 2 using uhci_hcd
>ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>ohci_hcd 0000:00:0a.0: OHCI Host Controller
>ohci_hcd 0000:00:0a.0: new USB bus registered, assigned bus number 3
>ohci_hcd 0000:00:0a.0: irq 19, io mem 0xdfffc000
>hub 3-0:1.0: USB hub found
>hub 3-0:1.0: 2 ports detected
>ohci_hcd 0000:00:0a.1: OHCI Host Controller
>ohci_hcd 0000:00:0a.1: new USB bus registered, assigned bus number 4
>ohci_hcd 0000:00:0a.1: irq 16, io mem 0xdfffd000
>hub 4-0:1.0: USB hub found
>hub 4-0:1.0: 2 ports detected
>ohci_hcd 0000:00:0a.2: OHCI Host Controller
>ohci_hcd 0000:00:0a.2: new USB bus registered, assigned bus number 5
>ohci_hcd 0000:00:0a.2: irq 17, io mem 0xdfffe000
>hub 5-0:1.0: USB hub found
>hub 5-0:1.0: 2 ports detected
>vmalloc: allocation failure: 0 bytes
>modprobe: page allocation failure: order:0, mode:0xd2
>Pid: 130, comm: modprobe Not tainted 3.7.0-small-00147-ga6f3b00 #34
>Call Trace:
> [<c0153724>] ? 0xc0153724
> [<c0144e07>] ? 0xc0144e07
> [<c0169155>] ? 0xc0169155
> [<c0118690>] ? 0xc0118690
> [<c0144e07>] ? 0xc0144e07
> [<c0144e07>] ? 0xc0144e07
> [<c01453dc>] ? 0xc01453dc
> [<c0119574>] ? 0xc0119574
> [<c0145cb8>] ? 0xc0145cb8
> [<c016fe7d>] ? 0xc016fe7d
> [<c02e9608>] ? 0xc02e9608
>Mem-Info:
>DMA per-cpu:
>CPU    0: hi:    0, btch:   1 usd:   0
>Normal per-cpu:
>CPU    0: hi:  186, btch:  31 usd: 118
>active_anon:408 inactive_anon:4 isolated_anon:0
> active_file:865 inactive_file:2323 isolated_file:0
> unevictable:0 dirty:0 writeback:0 unstable:0
> free:121990 slab_reclaimable:223 slab_unreclaimable:387
> mapped:388 shmem:12 pagetables:32 bounce:0
> free_cma:0
>DMA free:13192kB min:84kB low:104kB high:124kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:15804kB mlocked:0kB dirty:0kB writeback:0kB mapped:0kB shmem:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 492 492
>Normal free:474768kB min:2792kB low:3488kB high:4188kB active_anon:1632kB inactive_anon:16kB active_file:3460kB inactive_file:9292kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:503872kB mlocked:0kB dirty:0kB writeback:0kB mapped:1552kB shmem:48kB slab_reclaimable:892kB slab_unreclaimable:1548kB kernel_stack:232kB pagetables:128kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 0 0
>DMA: 2*4kB 2*8kB 1*16kB 5*32kB 5*64kB 3*128kB 2*256kB 1*512kB 1*1024kB 1*2048kB 2*4096kB = 13192kB
>Normal: 2*4kB 3*8kB 3*16kB 0*32kB 1*64kB 2*128kB 1*256kB 2*512kB 2*1024kB 2*2048kB 114*4096kB = 474768kB
>3201 total pagecache pages
>0 pages in swap cache
>Swap cache stats: add 0, delete 0, find 0/0
>Free swap  = 0kB
>Total swap = 0kB
>131040 pages RAM
>2943 pages reserved
>2423 pages shared
>4286 pages non-shared
>8139too: 8139too Fast Ethernet driver 0.9.28
>8139too 0000:00:0b.0 eth0: RealTek RTL8139 at 0xe0b14a00, 00:50:ba:5c:f7:df, IRQ 19
>SCSI subsystem initialized
>ACPI: bus type scsi registered
>libata version 3.00 loaded.
>sata_sil 0000:00:0d.0: version 2.4
>sata_sil 0000:00:0d.0: Applying R_ERR on DMA activate FIS errata fix
>scsi0 : sata_sil
>scsi1 : sata_sil
>scsi2 : sata_sil
>scsi3 : sata_sil
>ata1: SATA max UDMA/100 mmio m1024@0xdffffc00 tf 0xdffffc80 irq 17
>ata2: SATA max UDMA/100 mmio m1024@0xdffffc00 tf 0xdffffcc0 irq 17
>ata3: SATA max UDMA/100 mmio m1024@0xdffffc00 tf 0xdffffe80 irq 17
>ata4: SATA max UDMA/100 mmio m1024@0xdffffc00 tf 0xdffffec0 irq 17
>ata1: SATA link down (SStatus 0 SControl 310)
>ata2: SATA link down (SStatus 0 SControl 310)
>ata3: SATA link down (SStatus 0 SControl 310)
>ata4: SATA link down (SStatus 0 SControl 310)
>input: ImPS/2 Generic Wheel Mouse as /devices/platform/i8042/serio1/input/input3
>usbcore: registered new interface driver usbhid
>usbhid: USB HID core driver
>mousedev: PS/2 mouse device common for all mice
>input: HID 04f3:0103 as /devices/pci0000:00/0000:00:07.2/usb2/2-2/2-2:1.0/input/input4
>hid-generic 0003:04F3:0103.0001: input: USB HID v1.10 Keyboard [HID 04f3:0103] on usb-0000:00:07.2-2/input0
>input: HID 04f3:0103 as /devices/pci0000:00/0000:00:07.2/usb2/2-2/2-2:1.1/input/input5
>hid-generic 0003:04F3:0103.0002: input: USB HID v1.10 Device [HID 04f3:0103] on usb-0000:00:07.2-2/input1
>Adding 489976k swap on /dev/hda3.  Priority:-1 extents:1 across:489976k 
>EXT4-fs (hda2): re-mounted. Opts: (null)
>EXT4-fs (hda2): re-mounted. Opts: (null)
>vmalloc: allocation failure: 0 bytes
>modprobe: page allocation failure: order:0, mode:0xd2
>Pid: 239, comm: modprobe Not tainted 3.7.0-small-00147-ga6f3b00 #34
>Call Trace:
> [<c0153724>] ? 0xc0153724
> [<c0144e07>] ? 0xc0144e07
> [<c0169155>] ? 0xc0169155
> [<c0118690>] ? 0xc0118690
> [<c0144e07>] ? 0xc0144e07
> [<c0144e07>] ? 0xc0144e07
> [<c01453dc>] ? 0xc01453dc
> [<c0119574>] ? 0xc0119574
> [<c0145cb8>] ? 0xc0145cb8
> [<c02e9608>] ? 0xc02e9608
>Mem-Info:
>DMA per-cpu:
>CPU    0: hi:    0, btch:   1 usd:   0
>Normal per-cpu:
>CPU    0: hi:  186, btch:  31 usd: 110
>active_anon:360 inactive_anon:27 isolated_anon:0
> active_file:1169 inactive_file:3233 isolated_file:0
> unevictable:0 dirty:0 writeback:0 unstable:0
> free:120387 slab_reclaimable:367 slab_unreclaimable:530
> mapped:366 shmem:31 pagetables:24 bounce:0
> free_cma:0
>DMA free:13192kB min:84kB low:104kB high:124kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:15804kB mlocked:0kB dirty:0kB writeback:0kB mapped:0kB shmem:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 492 492
>Normal free:468356kB min:2792kB low:3488kB high:4188kB active_anon:1440kB inactive_anon:108kB active_file:4676kB inactive_file:12932kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:503872kB mlocked:0kB dirty:0kB writeback:0kB mapped:1464kB shmem:124kB slab_reclaimable:1468kB slab_unreclaimable:2120kB kernel_stack:296kB pagetables:96kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 0 0
>DMA: 2*4kB 2*8kB 1*16kB 5*32kB 5*64kB 3*128kB 2*256kB 1*512kB 1*1024kB 1*2048kB 2*4096kB = 13192kB
>Normal: 11*4kB 5*8kB 3*16kB 2*32kB 3*64kB 2*128kB 1*256kB 1*512kB 2*1024kB 1*2048kB 113*4096kB = 468356kB
>4434 total pagecache pages
>0 pages in swap cache
>Swap cache stats: add 0, delete 0, find 0/0
>Free swap  = 489976kB
>Total swap = 489976kB
>131040 pages RAM
>2943 pages reserved
>2340 pages shared
>5648 pages non-shared
>vmalloc: allocation failure: 0 bytes
>modprobe: page allocation failure: order:0, mode:0xd2
>Pid: 239, comm: modprobe Not tainted 3.7.0-small-00147-ga6f3b00 #34
>Call Trace:
> [<c0153724>] ? 0xc0153724
> [<c0144e07>] ? 0xc0144e07
> [<c0169155>] ? 0xc0169155
> [<c0118690>] ? 0xc0118690
> [<c0144e07>] ? 0xc0144e07
> [<c0144e07>] ? 0xc0144e07
> [<c01453dc>] ? 0xc01453dc
> [<c0145cb8>] ? 0xc0145cb8
> [<c012d6eb>] ? 0xc012d6eb
> [<c02e9608>] ? 0xc02e9608
>Mem-Info:
>DMA per-cpu:
>CPU    0: hi:    0, btch:   1 usd:   0
>Normal per-cpu:
>CPU    0: hi:  186, btch:  31 usd: 106
>active_anon:360 inactive_anon:27 isolated_anon:0
> active_file:1169 inactive_file:3233 isolated_file:0
> unevictable:0 dirty:0 writeback:0 unstable:0
> free:120387 slab_reclaimable:367 slab_unreclaimable:530
> mapped:366 shmem:31 pagetables:24 bounce:0
> free_cma:0
>DMA free:13192kB min:84kB low:104kB high:124kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:15804kB mlocked:0kB dirty:0kB writeback:0kB mapped:0kB shmem:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 492 492
>Normal free:468356kB min:2792kB low:3488kB high:4188kB active_anon:1440kB inactive_anon:108kB active_file:4676kB inactive_file:12932kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:503872kB mlocked:0kB dirty:0kB writeback:0kB mapped:1464kB shmem:124kB slab_reclaimable:1468kB slab_unreclaimable:2120kB kernel_stack:296kB pagetables:96kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 0 0
>DMA: 2*4kB 2*8kB 1*16kB 5*32kB 5*64kB 3*128kB 2*256kB 1*512kB 1*1024kB 1*2048kB 2*4096kB = 13192kB
>Normal: 11*4kB 5*8kB 3*16kB 2*32kB 3*64kB 2*128kB 1*256kB 1*512kB 2*1024kB 1*2048kB 113*4096kB = 468356kB
>4436 total pagecache pages
>0 pages in swap cache
>Swap cache stats: add 0, delete 0, find 0/0
>Free swap  = 489976kB
>Total swap = 489976kB
>131040 pages RAM
>2943 pages reserved
>2342 pages shared
>5650 pages non-shared
>vmalloc: allocation failure: 0 bytes
>modprobe: page allocation failure: order:0, mode:0xd2
>Pid: 239, comm: modprobe Not tainted 3.7.0-small-00147-ga6f3b00 #34
>Call Trace:
> [<c0153724>] ? 0xc0153724
> [<c0144e07>] ? 0xc0144e07
> [<c0169155>] ? 0xc0169155
> [<c0118690>] ? 0xc0118690
> [<c0144e07>] ? 0xc0144e07
> [<c0144e07>] ? 0xc0144e07
> [<c01453dc>] ? 0xc01453dc
> [<c0119574>] ? 0xc0119574
> [<c0145cb8>] ? 0xc0145cb8
> [<c012d6eb>] ? 0xc012d6eb
> [<c02e9608>] ? 0xc02e9608
>Mem-Info:
>DMA per-cpu:
>CPU    0: hi:    0, btch:   1 usd:   0
>Normal per-cpu:
>CPU    0: hi:  186, btch:  31 usd: 100
>active_anon:360 inactive_anon:27 isolated_anon:0
> active_file:1169 inactive_file:3233 isolated_file:0
> unevictable:0 dirty:0 writeback:0 unstable:0
> free:120387 slab_reclaimable:367 slab_unreclaimable:530
> mapped:366 shmem:31 pagetables:24 bounce:0
> free_cma:0
>DMA free:13192kB min:84kB low:104kB high:124kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:15804kB mlocked:0kB dirty:0kB writeback:0kB mapped:0kB shmem:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 492 492
>Normal free:468356kB min:2792kB low:3488kB high:4188kB active_anon:1440kB inactive_anon:108kB active_file:4676kB inactive_file:12932kB unevictable:0kB isolated(anon):0kB isolated(file):0kB present:503872kB mlocked:0kB dirty:0kB writeback:0kB mapped:1464kB shmem:124kB slab_reclaimable:1468kB slab_unreclaimable:2120kB kernel_stack:296kB pagetables:96kB unstable:0kB bounce:0kB free_cma:0kB writeback_tmp:0kB pages_scanned:0 all_unreclaimable? no
>lowmem_reserve[]: 0 0 0
>DMA: 2*4kB 2*8kB 1*16kB 5*32kB 5*64kB 3*128kB 2*256kB 1*512kB 1*1024kB 1*2048kB 2*4096kB = 13192kB
>Normal: 11*4kB 5*8kB 3*16kB 2*32kB 3*64kB 2*128kB 1*256kB 1*512kB 2*1024kB 1*2048kB 113*4096kB = 468356kB
>4438 total pagecache pages
>0 pages in swap cache
>Swap cache stats: add 0, delete 0, find 0/0
>Free swap  = 489976kB
>Total swap = 489976kB
>131040 pages RAM
>2943 pages reserved
>2346 pages shared
>5652 pages non-shared
>Console: switching to colour frame buffer device 160x64
>lp: driver loaded but no devices found
>8139too 0000:00:0b.0 eth1: link up, 100Mbps, full-duplex, lpa 0x41E1
>NET: Registered protocol family 17
>nouveau T[  DEVICE][0000:01:00.0] inc() == 33
>nouveau D[  X[556]] fini running
>nouveau T[  X[556]] 0xffffffff:0xffffffff fini children
>nouveau T[  X[556]] 0xffffffff:0xffffffff fini running
>nouveau T[  X[556]] use(-1) == 1
>nouveau T[  X[556]] 0xffffffff:0xffffffff fini completed
>nouveau D[  X[556]] fini completed with 0
>nouveau T[  X[556]] dec() == 0
>nouveau D[  X[556]] destroying
>nouveau T[  DEVICE][0000:01:00.0] dec() == 32
>nouveau T[  X[556]] 0xffffffff:0xffffffff destroy running
>nouveau T[  X[556]] 0xffffffff:0xffffffff destroy completed
>nouveau T[  X[556]] dec() == -1
>nouveau T[  DEVICE][0000:01:00.0] inc() == 33
>nouveau D[  X[556]] fini running
>nouveau T[  X[556]] 0xffffffff:0xffffffff fini children
>nouveau T[  X[556]] 0xffffffff:0xffffffff fini running
>nouveau T[  X[556]] use(-1) == 1
>nouveau T[  X[556]] 0xffffffff:0xffffffff fini completed
>nouveau D[  X[556]] fini completed with 0
>nouveau T[  X[556]] dec() == 0
>nouveau D[  X[556]] destroying
>nouveau T[  DEVICE][0000:01:00.0] dec() == 32
>nouveau T[  X[556]] 0xffffffff:0xffffffff destroy running
>nouveau T[  X[556]] 0xffffffff:0xffffffff destroy completed
>nouveau T[  X[556]] dec() == -1
>nouveau T[  DEVICE][0000:01:00.0] inc() == 33
>nouveau D[  X[556]] fini running
>nouveau T[  X[556]] 0xffffffff:0xffffffff fini children
>nouveau T[  X[556]] 0xffffffff:0xffffffff fini running
>nouveau T[  X[556]] use(-1) == 1
>nouveau T[  X[556]] 0xffffffff:0xffffffff fini completed
>nouveau D[  X[556]] fini completed with 0
>nouveau T[  X[556]] dec() == 0
>nouveau D[  X[556]] destroying
>nouveau T[  DEVICE][0000:01:00.0] dec() == 32
>nouveau T[  X[556]] 0xffffffff:0xffffffff destroy running
>nouveau T[  X[556]] 0xffffffff:0xffffffff destroy completed
>nouveau T[  X[556]] dec() == -1
>nouveau T[  DEVICE][0000:01:00.0] inc() == 33
>nouveau T[  X[556]] inc() == 3
>nouveau T[  X[556]] inc() == 4
>nouveau T[  X[556]] inc() == 5
>nouveau T[  DEVICE][0000:01:00.0] inc() == 34
>nouveau T[   VBIOS][0000:01:00.0] inc() == 2
>nouveau T[ DEVINIT][0000:01:00.0] inc() == 2
>nouveau T[    GPIO][0000:01:00.0] inc() == 2
>nouveau T[     I2C][0000:01:00.0] inc() == 2
>nouveau T[   CLOCK][0000:01:00.0] inc() == 2
>nouveau T[   VBIOS][0000:01:00.0] use(+1) == 2
>nouveau T[ DEVINIT][0000:01:00.0] use(+1) == 2
>nouveau T[    GPIO][0000:01:00.0] use(+1) == 2
>nouveau T[     I2C][0000:01:00.0] use(+1) == 2
>nouveau T[   CLOCK][0000:01:00.0] use(+1) == 2
>nouveau T[     PMC][0000:01:00.0] inc() == 2
>nouveau T[     PMC][0000:01:00.0] use(+1) == 2
>nouveau T[    PBUS][0000:01:00.0] inc() == 2
>nouveau T[    PBUS][0000:01:00.0] use(+1) == 2
>nouveau T[  PTIMER][0000:01:00.0] inc() == 2
>nouveau T[  PTIMER][0000:01:00.0] use(+1) == 2
>nouveau T[     PFB][0000:01:00.0] inc() == 2
>nouveau T[     PFB][0000:01:00.0] use(+1) == 2
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 6
>nouveau T[ INSTMEM][0000:01:00.0] use(+1) == 4
>nouveau T[ PCIGART][0000:01:00.0] inc() == 2
>nouveau T[ PCIGART][0000:01:00.0] use(+1) == 2
>nouveau T[  PTHERM][0000:01:00.0] inc() == 2
>nouveau T[  PTHERM][0000:01:00.0] use(+1) == 2
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 11
>nouveau T[   PFIFO][0000:01:00.0] inc() == 5
>nouveau T[      SW][0000:01:00.0] inc() == 4
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 10
>nouveau T[   PMPEG][0000:01:00.0] inc() == 2
>nouveau T[ DISPLAY][0000:01:00.0] inc() == 2
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] created
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] use(+1) == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] initialising...
>nouveau T[  X[556]] use(+1) == 3
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 20
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] initialised
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 2
>nouveau T[  X[556]] 0xffffffff:0xdddddddd created
>nouveau T[  X[556]] 0xffffffff:0xdddddddd init running
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] use(+1) == 2
>nouveau T[  X[556]] 0xffffffff:0xdddddddd init children
>nouveau T[  X[556]] 0xffffffff:0xdddddddd init completed
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] use(-1) == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 1
>nouveau T[  X[556]] dec() == 4
>nouveau T[  X[556]] dec() == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 10
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 12
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] initialising...
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] use(+1) == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 11
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] inc() == 2
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 created
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] use(+1) == 2
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 init children
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 10
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] illegal class 0xa06f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] illegal class 0x906f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] illegal class 0x826f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] illegal class 0x506f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 3
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 fini children
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 fini running
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] use(-1) == 0
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] stopping...
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 9
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] use(-1) == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] stopped
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 fini completed
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 destroy running
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 destroy completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] dec() == 0
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb39dc0] destroying
>nouveau T[  DMAOBJ][0000:01:00.0] dec() == 11
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 10
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 12
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb39000] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39000] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39000] initialising...
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] use(+1) == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 11
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb39000] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39000] inc() == 2
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 created
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39000] use(+1) == 2
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 init children
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0000 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39000] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39000] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 10
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 3
>nouveau T[   PFIFO][0000:01:00.0] use(+1) == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 4
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 7
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][ddb39f00] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddb39f00] inc() == 2
>nouveau T[   PFIFO][0000:01:00.0] inc() == 6
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddb39f00] dec() == 1
>nouveau D[   PFIFO][0000:01:00.0][0x03004013][ddb90120] created
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][ddb90120] inc() == 2
>nouveau T[   PFIFO][0000:01:00.0] inc() == 7
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39000] inc() == 2
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][ddb90120] inc() == 4
>nouveau T[   PFIFO][0000:01:00.0] inc() == 8
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][ddb90120] dec() == 3
>nouveau D[   PFIFO][0000:01:00.0][0x02000000][ddb90180] created
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] created
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] use(+1) == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][ddb90120] use(+1) == 1
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][ddb90120] initialising...
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddb39f00] use(+1) == 1
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddb39f00] initialising...
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] use(+1) == 3
>nouveau T[ INSTMEM][0000:01:00.0] use(+1) == 5
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][ddb39f00] initialised
>nouveau T[   PFIFO][0000:01:00.0] use(+1) == 4
>nouveau D[   PFIFO][0000:01:00.0][0x03004013][ddb90120] initialised
>nouveau T[   PFIFO][0000:01:00.0] use(+1) == 5
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] initialised
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 2
>nouveau T[  X[556]] 0xdddddddd:0xcccc0000 created
>nouveau T[  X[556]] 0xdddddddd:0xcccc0000 init running
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] use(+1) == 2
>nouveau T[  X[556]] 0xdddddddd:0xcccc0000 init children
>nouveau T[  X[556]] 0xdddddddd:0xcccc0000 init completed
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] use(-1) == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][ddb90120] dec() == 2
>nouveau T[   PFIFO][0000:01:00.0] use(-1) == 4
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 11
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 13
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb39300] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 14
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb39300] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90840] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb39300] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90840] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90840] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90840] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb39300] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb39300] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] use(+1) == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 12
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][ddb39300] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 13
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90840] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90840] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0xbeef0201 created
>nouveau T[  X[556]] 0xcccc0000:0xbeef0201 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90840] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0xbeef0201 init children
>nouveau T[  X[556]] 0xcccc0000:0xbeef0201 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90840] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90840] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 12
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 2
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 13
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 4
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 5
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 15
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb396c0] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 16
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb396c0] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb907e0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb396c0] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb907e0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb907e0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb907e0] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb396c0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb396c0] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] use(+1) == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 14
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][ddb396c0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 15
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb907e0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb907e0] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0xbeef0202 created
>nouveau T[  X[556]] 0xcccc0000:0xbeef0202 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb907e0] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0xbeef0202 init children
>nouveau T[  X[556]] 0xcccc0000:0xbeef0202 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb907e0] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb907e0] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 14
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 4
>nouveau T[      SW][0000:01:00.0] use(+1) == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 5
>nouveau T[      SW][0000:01:00.0] inc() == 5
>nouveau D[      SW][0000:01:00.0][0x01000414][df1d53c0] created
>nouveau T[      SW][0000:01:00.0][0x01000414][df1d53c0] inc() == 2
>nouveau T[      SW][0000:01:00.0] inc() == 6
>nouveau D[      SW][0000:01:00.0][0x0000016e][ddb5d5c0] created
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb5d5c0] use(+1) == 1
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb5d5c0] initialising...
>nouveau T[      SW][0000:01:00.0][0x01000414][df1d53c0] use(+1) == 1
>nouveau T[      SW][0000:01:00.0][0x01000414][df1d53c0] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] use(+1) == 4
>nouveau T[      SW][0000:01:00.0] use(+1) == 4
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] attached SW context
>nouveau D[      SW][0000:01:00.0][0x01000414][df1d53c0] initialised
>nouveau T[      SW][0000:01:00.0] use(+1) == 5
>nouveau D[      SW][0000:01:00.0][0x0000016e][ddb5d5c0] initialised
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb5d5c0] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x8000000e created
>nouveau T[  X[556]] 0xcccc0000:0x8000000e init running
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb5d5c0] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x8000000e init children
>nouveau T[  X[556]] 0xcccc0000:0x8000000e init completed
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb5d5c0] use(-1) == 1
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb5d5c0] dec() == 1
>nouveau T[      SW][0000:01:00.0][0x01000414][df1d53c0] dec() == 1
>nouveau T[      SW][0000:01:00.0] use(-1) == 4
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 4
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 5
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 15
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 7
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 17
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39c40] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 18
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39c40] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90540] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39c40] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90540] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90540] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90540] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39c40] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb39c40] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] use(+1) == 5
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 16
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb39c40] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 17
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90540] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90540] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x8000000f created
>nouveau T[  X[556]] 0xcccc0000:0x8000000f init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90540] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x8000000f init children
>nouveau T[  X[556]] 0xcccc0000:0x8000000f init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90540] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90540] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 6
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 16
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 5
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 6
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 17
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 19
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb39c80] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 20
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb39c80] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90300] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb39c80] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90300] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90300] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90300] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb39c80] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb39c80] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] use(+1) == 6
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 18
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][ddb39c80] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 19
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90300] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90300] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0xd8000003 created
>nouveau T[  X[556]] 0xcccc0000:0xd8000003 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90300] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0xd8000003 init children
>nouveau T[  X[556]] 0xcccc0000:0xd8000003 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90300] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90300] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 18
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 7
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 8
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][ddb39240] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddb39240] inc() == 2
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 11
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddb39240] dec() == 1
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 3
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 12
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 2
>nouveau D[  PGRAPH][0000:01:00.0][0x02000030][ddb90420] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][ddb90420] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][ddb90420] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] initialising...
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddb39240] use(+1) == 1
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddb39240] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] use(+1) == 7
>nouveau T[ INSTMEM][0000:01:00.0] use(+1) == 6
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][ddb39240] initialised
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 10
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] attached PGRAPH context
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] initialised
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 11
>nouveau D[  PGRAPH][0000:01:00.0][0x02000030][ddb90420] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][ddb90420] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x00000000 created
>nouveau T[  X[556]] 0xcccc0000:0x00000000 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][ddb90420] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x00000000 init children
>nouveau T[  X[556]] 0xcccc0000:0x00000000 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][ddb90420] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][ddb90420] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 10
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 11
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 4
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 13
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 3
>nouveau D[  PGRAPH][0000:01:00.0][0x02000062][ddb90000] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][ddb90000] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][ddb90000] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 2
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 12
>nouveau D[  PGRAPH][0000:01:00.0][0x02000062][ddb90000] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][ddb90000] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000010 created
>nouveau T[  X[556]] 0xcccc0000:0x80000010 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][ddb90000] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000010 init children
>nouveau T[  X[556]] 0xcccc0000:0x80000010 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][ddb90000] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][ddb90000] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 2
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 11
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 12
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 5
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 14
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 4
>nouveau D[  PGRAPH][0000:01:00.0][0x02000012][ddb90060] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000012][ddb90060] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000012][ddb90060] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 3
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 13
>nouveau D[  PGRAPH][0000:01:00.0][0x02000012][ddb90060] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000012][ddb90060] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x8000001b created
>nouveau T[  X[556]] 0xcccc0000:0x8000001b init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000012][ddb90060] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x8000001b init children
>nouveau T[  X[556]] 0xcccc0000:0x8000001b init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000012][ddb90060] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000012][ddb90060] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 3
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 12
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 13
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 6
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 15
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 5
>nouveau D[  PGRAPH][0000:01:00.0][0x02000072][ddb905a0] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000072][ddb905a0] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000072][ddb905a0] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 4
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 14
>nouveau D[  PGRAPH][0000:01:00.0][0x02000072][ddb905a0] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000072][ddb905a0] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x8000001c created
>nouveau T[  X[556]] 0xcccc0000:0x8000001c init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000072][ddb905a0] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x8000001c init children
>nouveau T[  X[556]] 0xcccc0000:0x8000001c init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000072][ddb905a0] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000072][ddb905a0] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 4
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 13
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 14
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 7
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 16
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 6
>nouveau D[  PGRAPH][0000:01:00.0][0x02000044][ddb90660] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000044][ddb90660] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000044][ddb90660] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 5
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 15
>nouveau D[  PGRAPH][0000:01:00.0][0x02000044][ddb90660] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000044][ddb90660] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000012 created
>nouveau T[  X[556]] 0xcccc0000:0x80000012 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000044][ddb90660] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000012 init children
>nouveau T[  X[556]] 0xcccc0000:0x80000012 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000044][ddb90660] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000044][ddb90660] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 5
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 14
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 15
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 17
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 7
>nouveau D[  PGRAPH][0000:01:00.0][0x02000043][ddb904e0] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000043][ddb904e0] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000043][ddb904e0] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 6
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 16
>nouveau D[  PGRAPH][0000:01:00.0][0x02000043][ddb904e0] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000043][ddb904e0] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000011 created
>nouveau T[  X[556]] 0xcccc0000:0x80000011 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000043][ddb904e0] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000011 init children
>nouveau T[  X[556]] 0xcccc0000:0x80000011 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000043][ddb904e0] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000043][ddb904e0] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 6
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 15
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 16
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 9
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 18
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 8
>nouveau D[  PGRAPH][0000:01:00.0][0x0200004a][ddb906c0] created
>nouveau T[  PGRAPH][0000:01:00.0][0x0200004a][ddb906c0] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200004a][ddb906c0] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 7
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 17
>nouveau D[  PGRAPH][0000:01:00.0][0x0200004a][ddb906c0] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x0200004a][ddb906c0] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000016 created
>nouveau T[  X[556]] 0xcccc0000:0x80000016 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x0200004a][ddb906c0] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000016 init children
>nouveau T[  X[556]] 0xcccc0000:0x80000016 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x0200004a][ddb906c0] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200004a][ddb906c0] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 7
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 16
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 17
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 10
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 19
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 9
>nouveau D[  PGRAPH][0000:01:00.0][0x0200009f][ddb90240] created
>nouveau T[  PGRAPH][0000:01:00.0][0x0200009f][ddb90240] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200009f][ddb90240] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 18
>nouveau D[  PGRAPH][0000:01:00.0][0x0200009f][ddb90240] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x0200009f][ddb90240] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000015 created
>nouveau T[  X[556]] 0xcccc0000:0x80000015 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x0200009f][ddb90240] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000015 init children
>nouveau T[  X[556]] 0xcccc0000:0x80000015 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x0200009f][ddb90240] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200009f][ddb90240] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 17
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 18
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 11
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 20
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 10
>nouveau D[  PGRAPH][0000:01:00.0][0x02003089][ddb90600] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][ddb90600] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][ddb90600] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 9
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 19
>nouveau D[  PGRAPH][0000:01:00.0][0x02003089][ddb90600] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][ddb90600] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000017 created
>nouveau T[  X[556]] 0xcccc0000:0x80000017 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][ddb90600] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000017 init children
>nouveau T[  X[556]] 0xcccc0000:0x80000017 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][ddb90600] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][ddb90600] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 9
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 18
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 19
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 12
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 21
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 11
>nouveau D[  PGRAPH][0000:01:00.0][0x02000019][ddb90960] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000019][ddb90960] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000019][ddb90960] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 10
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 20
>nouveau D[  PGRAPH][0000:01:00.0][0x02000019][ddb90960] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000019][ddb90960] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000013 created
>nouveau T[  X[556]] 0xcccc0000:0x80000013 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000019][ddb90960] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000013 init children
>nouveau T[  X[556]] 0xcccc0000:0x80000013 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000019][ddb90960] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000019][ddb90960] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 10
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 19
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 20
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 13
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 22
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 12
>nouveau D[  PGRAPH][0000:01:00.0][0x0200008a][ddb909c0] created
>nouveau T[  PGRAPH][0000:01:00.0][0x0200008a][ddb909c0] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200008a][ddb909c0] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 11
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 21
>nouveau D[  PGRAPH][0000:01:00.0][0x0200008a][ddb909c0] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x0200008a][ddb909c0] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x8000001a created
>nouveau T[  X[556]] 0xcccc0000:0x8000001a init running
>nouveau T[  PGRAPH][0000:01:00.0][0x0200008a][ddb909c0] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x8000001a init children
>nouveau T[  X[556]] 0xcccc0000:0x8000001a init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x0200008a][ddb909c0] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200008a][ddb909c0] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 11
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 20
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 21
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 14
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 23
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 13
>nouveau D[  PGRAPH][0000:01:00.0][0x02000039][ddb90a20] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][ddb90a20] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][ddb90a20] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 12
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 22
>nouveau D[  PGRAPH][0000:01:00.0][0x02000039][ddb90a20] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][ddb90a20] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000018 created
>nouveau T[  X[556]] 0xcccc0000:0x80000018 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][ddb90a20] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000018 init children
>nouveau T[  X[556]] 0xcccc0000:0x80000018 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][ddb90a20] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][ddb90a20] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 12
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 21
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 22
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] inc() == 15
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 24
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 14
>nouveau D[  PGRAPH][0000:01:00.0][0x02004097][ddb90a80] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][ddb90a80] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][ddb90a80] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] use(+1) == 13
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 23
>nouveau D[  PGRAPH][0000:01:00.0][0x02004097][ddb90a80] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][ddb90a80] inc() == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000019 created
>nouveau T[  X[556]] 0xcccc0000:0x80000019 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][ddb90a80] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0000:0x80000019 init children
>nouveau T[  X[556]] 0xcccc0000:0x80000019 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][ddb90a80] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][ddb90a80] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d5480] dec() == 13
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 22
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2a400] dec() == 7
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 19
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 5
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 6
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 21
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] initialising...
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] use(+1) == 4
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 20
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] inc() == 2
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 created
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] use(+1) == 2
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 init children
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 5
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 19
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 4
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 5
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] illegal class 0xa06f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 4
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 5
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] illegal class 0x906f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 4
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 5
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] illegal class 0x826f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 4
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 5
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] illegal class 0x506f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 4
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 5
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 4
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 5
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 fini children
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 fini running
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] use(-1) == 0
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] stopping...
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 18
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] use(-1) == 3
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] stopped
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 fini completed
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 destroy running
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 destroy completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] dec() == 0
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb80e00] destroying
>nouveau T[  DMAOBJ][0000:01:00.0] dec() == 20
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 4
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 19
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 5
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 6
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 21
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb80c40] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80c40] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80c40] initialising...
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] use(+1) == 4
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 20
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb80c40] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80c40] inc() == 2
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 created
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80c40] use(+1) == 2
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 init children
>nouveau T[  X[556]] 0xdddddddd:0xbbbb0001 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80c40] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80c40] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 5
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 19
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 4
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 5
>nouveau T[   PFIFO][0000:01:00.0] use(+1) == 5
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] inc() == 6
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 9
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][ddb80540] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddb80540] inc() == 2
>nouveau T[   PFIFO][0000:01:00.0] inc() == 9
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddb80540] dec() == 1
>nouveau D[   PFIFO][0000:01:00.0][0x03004013][ddb90ba0] created
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][ddb90ba0] inc() == 2
>nouveau T[   PFIFO][0000:01:00.0] inc() == 10
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80c40] inc() == 2
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][ddb90ba0] inc() == 4
>nouveau T[   PFIFO][0000:01:00.0] inc() == 11
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][ddb90ba0] dec() == 3
>nouveau D[   PFIFO][0000:01:00.0][0x02000000][ddb90c00] created
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] created
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] use(+1) == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][ddb90ba0] use(+1) == 1
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][ddb90ba0] initialising...
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddb80540] use(+1) == 1
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddb80540] initialising...
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] use(+1) == 5
>nouveau T[ INSTMEM][0000:01:00.0] use(+1) == 7
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][ddb80540] initialised
>nouveau T[   PFIFO][0000:01:00.0] use(+1) == 6
>nouveau D[   PFIFO][0000:01:00.0][0x03004013][ddb90ba0] initialised
>nouveau T[   PFIFO][0000:01:00.0] use(+1) == 7
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] initialised
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 2
>nouveau T[  X[556]] 0xdddddddd:0xcccc0001 created
>nouveau T[  X[556]] 0xdddddddd:0xcccc0001 init running
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] use(+1) == 2
>nouveau T[  X[556]] 0xdddddddd:0xcccc0001 init children
>nouveau T[  X[556]] 0xdddddddd:0xcccc0001 init completed
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] use(-1) == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][ddb90ba0] dec() == 2
>nouveau T[   PFIFO][0000:01:00.0] use(-1) == 6
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d56c0] dec() == 5
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 20
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 22
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb80980] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 23
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb80980] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90c60] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb80980] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90c60] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90c60] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90c60] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb80980] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb80980] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] use(+1) == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 21
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][ddb80980] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 22
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90c60] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90c60] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef0201 created
>nouveau T[  X[556]] 0xcccc0001:0xbeef0201 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90c60] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef0201 init children
>nouveau T[  X[556]] 0xcccc0001:0xbeef0201 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90c60] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90c60] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 21
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 2
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 22
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 4
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 5
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 24
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb80b00] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 25
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb80b00] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90cc0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb80b00] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90cc0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90cc0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90cc0] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb80b00] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddb80b00] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] use(+1) == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 23
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][ddb80b00] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 24
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90cc0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90cc0] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef0202 created
>nouveau T[  X[556]] 0xcccc0001:0xbeef0202 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90cc0] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef0202 init children
>nouveau T[  X[556]] 0xcccc0001:0xbeef0202 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90cc0] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90cc0] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 23
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 4
>nouveau T[      SW][0000:01:00.0] use(+1) == 5
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 5
>nouveau T[      SW][0000:01:00.0] inc() == 7
>nouveau D[      SW][0000:01:00.0][0x01000414][df1dd6c0] created
>nouveau T[      SW][0000:01:00.0][0x01000414][df1dd6c0] inc() == 2
>nouveau T[      SW][0000:01:00.0] inc() == 8
>nouveau D[      SW][0000:01:00.0][0x0000016e][ddb5dc80] created
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb5dc80] use(+1) == 1
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb5dc80] initialising...
>nouveau T[      SW][0000:01:00.0][0x01000414][df1dd6c0] use(+1) == 1
>nouveau T[      SW][0000:01:00.0][0x01000414][df1dd6c0] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] use(+1) == 4
>nouveau T[      SW][0000:01:00.0] use(+1) == 6
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] attached SW context
>nouveau D[      SW][0000:01:00.0][0x01000414][df1dd6c0] initialised
>nouveau T[      SW][0000:01:00.0] use(+1) == 7
>nouveau D[      SW][0000:01:00.0][0x0000016e][ddb5dc80] initialised
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb5dc80] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0x8000000e created
>nouveau T[  X[556]] 0xcccc0001:0x8000000e init running
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb5dc80] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0x8000000e init children
>nouveau T[  X[556]] 0xcccc0001:0x8000000e init completed
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb5dc80] use(-1) == 1
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb5dc80] dec() == 1
>nouveau T[      SW][0000:01:00.0][0x01000414][df1dd6c0] dec() == 1
>nouveau T[      SW][0000:01:00.0] use(-1) == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 4
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 5
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 24
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 7
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 26
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80ac0] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 27
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80ac0] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90d20] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80ac0] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90d20] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90d20] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90d20] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80ac0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][ddb80ac0] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] use(+1) == 5
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 25
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][ddb80ac0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 26
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][ddb90d20] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90d20] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0x8000000f created
>nouveau T[  X[556]] 0xcccc0001:0x8000000f init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90d20] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0x8000000f init children
>nouveau T[  X[556]] 0xcccc0001:0x8000000f init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90d20] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][ddb90d20] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 6
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 25
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 5
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 6
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 23
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 7
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 10
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][ddbc2d80] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddbc2d80] inc() == 2
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 25
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddbc2d80] dec() == 1
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] inc() == 3
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 26
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] dec() == 2
>nouveau D[  PGRAPH][0000:01:00.0][0x02000030][ddb90f60] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][ddb90f60] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][ddb90f60] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] initialising...
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddbc2d80] use(+1) == 1
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][ddbc2d80] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] use(+1) == 6
>nouveau T[ INSTMEM][0000:01:00.0] use(+1) == 8
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][ddbc2d80] initialised
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 24
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] attached PGRAPH context
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] initialised
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 25
>nouveau D[  PGRAPH][0000:01:00.0][0x02000030][ddb90f60] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][ddb90f60] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0x00000000 created
>nouveau T[  X[556]] 0xcccc0001:0x00000000 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][ddb90f60] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0x00000000 init children
>nouveau T[  X[556]] 0xcccc0001:0x00000000 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][ddb90f60] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][ddb90f60] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 24
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 7
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 26
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 8
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 9
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 28
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc2880] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 29
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc2880] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd9dc8a0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc2880] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd9dc8a0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd9dc8a0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd9dc8a0] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc2880] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc2880] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] use(+1) == 7
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 27
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc2880] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 28
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd9dc8a0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd9dc8a0] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef1e00 created
>nouveau T[  X[556]] 0xcccc0001:0xbeef1e00 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd9dc8a0] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef1e00 init children
>nouveau T[  X[556]] 0xcccc0001:0xbeef1e00 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd9dc8a0] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd9dc8a0] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 8
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 27
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 8
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 28
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 10
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 30
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc21c0] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 31
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc21c0] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dda2aea0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc21c0] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dda2aea0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dda2aea0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dda2aea0] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc21c0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc21c0] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] use(+1) == 8
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 29
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc21c0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 30
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dda2aea0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dda2aea0] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef0301 created
>nouveau T[  X[556]] 0xcccc0001:0xbeef0301 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dda2aea0] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef0301 init children
>nouveau T[  X[556]] 0xcccc0001:0xbeef0301 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dda2aea0] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dda2aea0] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 9
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 29
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 8
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 9
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 30
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 10
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 11
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 32
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc2780] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 33
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc2780] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dda2af60] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc2780] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dda2af60] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dda2af60] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dda2af60] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc2780] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc2780] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] use(+1) == 9
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 31
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][ddbc2780] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 32
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dda2af60] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dda2af60] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef0351 created
>nouveau T[  X[556]] 0xcccc0001:0xbeef0351 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dda2af60] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef0351 init children
>nouveau T[  X[556]] 0xcccc0001:0xbeef0351 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dda2af60] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dda2af60] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 10
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 31
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 10
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 25
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] inc() == 4
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 27
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] dec() == 3
>nouveau D[  PGRAPH][0000:01:00.0][0x02004097][dda2ae40] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][dda2ae40] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][dda2ae40] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] use(+1) == 2
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 26
>nouveau D[  PGRAPH][0000:01:00.0][0x02004097][dda2ae40] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][dda2ae40] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef3097 created
>nouveau T[  X[556]] 0xcccc0001:0xbeef3097 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][dda2ae40] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef3097 init children
>nouveau T[  X[556]] 0xcccc0001:0xbeef3097 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][dda2ae40] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][dda2ae40] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] dec() == 2
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 25
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 10
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 26
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] inc() == 5
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 28
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] dec() == 4
>nouveau D[  PGRAPH][0000:01:00.0][0x02000039][dda2af00] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][dda2af00] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][dda2af00] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] use(+1) == 3
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 27
>nouveau D[  PGRAPH][0000:01:00.0][0x02000039][dda2af00] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][dda2af00] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef3901 created
>nouveau T[  X[556]] 0xcccc0001:0xbeef3901 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][dda2af00] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef3901 init children
>nouveau T[  X[556]] 0xcccc0001:0xbeef3901 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][dda2af00] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][dda2af00] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] dec() == 3
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 26
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 10
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 27
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] inc() == 6
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 29
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] dec() == 5
>nouveau D[  PGRAPH][0000:01:00.0][0x02000062][dda2ad20] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][dda2ad20] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][dda2ad20] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] use(+1) == 4
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 28
>nouveau D[  PGRAPH][0000:01:00.0][0x02000062][dda2ad20] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][dda2ad20] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef6201 created
>nouveau T[  X[556]] 0xcccc0001:0xbeef6201 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][dda2ad20] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef6201 init children
>nouveau T[  X[556]] 0xcccc0001:0xbeef6201 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][dda2ad20] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][dda2ad20] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] dec() == 4
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 27
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 10
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 28
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] inc() == 7
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 30
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] dec() == 6
>nouveau D[  PGRAPH][0000:01:00.0][0x0200309e][dd94cf00] created
>nouveau T[  PGRAPH][0000:01:00.0][0x0200309e][dd94cf00] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200309e][dd94cf00] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] use(+1) == 5
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 29
>nouveau D[  PGRAPH][0000:01:00.0][0x0200309e][dd94cf00] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x0200309e][dd94cf00] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef5201 created
>nouveau T[  X[556]] 0xcccc0001:0xbeef5201 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x0200309e][dd94cf00] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef5201 init children
>nouveau T[  X[556]] 0xcccc0001:0xbeef5201 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x0200309e][dd94cf00] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200309e][dd94cf00] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] dec() == 5
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 28
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] inc() == 10
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 29
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 31
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] dec() == 7
>nouveau D[  PGRAPH][0000:01:00.0][0x02003089][dda74000] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][dda74000] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][dda74000] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] use(+1) == 6
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 30
>nouveau D[  PGRAPH][0000:01:00.0][0x02003089][dda74000] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][dda74000] inc() == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef7701 created
>nouveau T[  X[556]] 0xcccc0001:0xbeef7701 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][dda74000] use(+1) == 2
>nouveau T[  X[556]] 0xcccc0001:0xbeef7701 init children
>nouveau T[  X[556]] 0xcccc0001:0xbeef7701 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][dda74000] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][dda74000] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1dd000] dec() == 6
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 29
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][ddb2bc00] dec() == 9
>nouveau T[  DEVICE][0000:01:00.0] inc() == 35
>nouveau T[glxgears[589]] inc() == 3
>nouveau T[glxgears[589]] inc() == 4
>nouveau T[glxgears[589]] inc() == 5
>nouveau T[  DEVICE][0000:01:00.0] inc() == 36
>nouveau T[   VBIOS][0000:01:00.0] inc() == 3
>nouveau T[ DEVINIT][0000:01:00.0] inc() == 3
>nouveau T[    GPIO][0000:01:00.0] inc() == 3
>nouveau T[     I2C][0000:01:00.0] inc() == 3
>nouveau T[   CLOCK][0000:01:00.0] inc() == 3
>nouveau T[   VBIOS][0000:01:00.0] use(+1) == 3
>nouveau T[ DEVINIT][0000:01:00.0] use(+1) == 3
>nouveau T[    GPIO][0000:01:00.0] use(+1) == 3
>nouveau T[     I2C][0000:01:00.0] use(+1) == 3
>nouveau T[   CLOCK][0000:01:00.0] use(+1) == 3
>nouveau T[     PMC][0000:01:00.0] inc() == 3
>nouveau T[     PMC][0000:01:00.0] use(+1) == 3
>nouveau T[    PBUS][0000:01:00.0] inc() == 3
>nouveau T[    PBUS][0000:01:00.0] use(+1) == 3
>nouveau T[  PTIMER][0000:01:00.0] inc() == 3
>nouveau T[  PTIMER][0000:01:00.0] use(+1) == 3
>nouveau T[     PFB][0000:01:00.0] inc() == 3
>nouveau T[     PFB][0000:01:00.0] use(+1) == 3
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 11
>nouveau T[ INSTMEM][0000:01:00.0] use(+1) == 9
>nouveau T[ PCIGART][0000:01:00.0] inc() == 3
>nouveau T[ PCIGART][0000:01:00.0] use(+1) == 3
>nouveau T[  PTHERM][0000:01:00.0] inc() == 3
>nouveau T[  PTHERM][0000:01:00.0] use(+1) == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 34
>nouveau T[   PFIFO][0000:01:00.0] inc() == 12
>nouveau T[      SW][0000:01:00.0] inc() == 9
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 32
>nouveau T[   PMPEG][0000:01:00.0] inc() == 3
>nouveau T[ DISPLAY][0000:01:00.0] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d1840] created
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] use(+1) == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] initialising...
>nouveau T[glxgears[589]] use(+1) == 3
>nouveau T[  DEVICE][0000:01:00.0] use(+1) == 21
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d1840] initialised
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 2
>nouveau T[glxgears[589]] 0xffffffff:0xdddddddd created
>nouveau T[glxgears[589]] 0xffffffff:0xdddddddd init running
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] use(+1) == 2
>nouveau T[glxgears[589]] 0xffffffff:0xdddddddd init children
>nouveau T[glxgears[589]] 0xffffffff:0xdddddddd init completed
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] use(-1) == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 1
>nouveau T[glxgears[589]] dec() == 4
>nouveau T[glxgears[589]] dec() == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 32
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 35
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] initialising...
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] use(+1) == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 33
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] inc() == 2
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 created
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] use(+1) == 2
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 init children
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 32
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d1840] illegal class 0xa06f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d1840] illegal class 0x906f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d1840] illegal class 0x826f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 3
>nouveau D[  DEVICE][0000:01:00.0][0x80000080][df1d1840] illegal class 0x506f
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 3
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 fini children
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 fini running
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] use(-1) == 0
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] stopping...
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 31
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] use(-1) == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] stopped
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 fini completed
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 destroy running
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 destroy completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] dec() == 0
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][dda8d100] destroying
>nouveau T[  DMAOBJ][0000:01:00.0] dec() == 34
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 32
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 3
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 35
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][dda8d200] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d200] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d200] initialising...
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] use(+1) == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 33
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][dda8d200] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d200] inc() == 2
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 created
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d200] use(+1) == 2
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 init children
>nouveau T[glxgears[589]] 0xdddddddd:0xbbbb0000 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d200] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d200] dec() == 1
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 32
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 2
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 3
>nouveau T[   PFIFO][0000:01:00.0] use(+1) == 7
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] inc() == 4
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 12
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][dda8d280] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][dda8d280] inc() == 2
>nouveau T[   PFIFO][0000:01:00.0] inc() == 13
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][dda8d280] dec() == 1
>nouveau D[   PFIFO][0000:01:00.0][0x03004013][dd063420] created
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][dd063420] inc() == 2
>nouveau T[   PFIFO][0000:01:00.0] inc() == 14
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d200] inc() == 2
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][dd063420] inc() == 4
>nouveau T[   PFIFO][0000:01:00.0] inc() == 15
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][dd063420] dec() == 3
>nouveau D[   PFIFO][0000:01:00.0][0x02000000][dd063480] created
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] created
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] use(+1) == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][dd063420] use(+1) == 1
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][dd063420] initialising...
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][dda8d280] use(+1) == 1
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][dda8d280] initialising...
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] use(+1) == 3
>nouveau T[ INSTMEM][0000:01:00.0] use(+1) == 10
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][dda8d280] initialised
>nouveau T[   PFIFO][0000:01:00.0] use(+1) == 8
>nouveau D[   PFIFO][0000:01:00.0][0x03004013][dd063420] initialised
>nouveau T[   PFIFO][0000:01:00.0] use(+1) == 9
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] initialised
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 2
>nouveau T[glxgears[589]] 0xdddddddd:0xcccc0000 created
>nouveau T[glxgears[589]] 0xdddddddd:0xcccc0000 init running
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] use(+1) == 2
>nouveau T[glxgears[589]] 0xdddddddd:0xcccc0000 init children
>nouveau T[glxgears[589]] 0xdddddddd:0xcccc0000 init completed
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] use(-1) == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0x03004013][dd063420] dec() == 2
>nouveau T[   PFIFO][0000:01:00.0] use(-1) == 8
>nouveau T[  DEVICE][0000:01:00.0][0x80000080][df1d1840] dec() == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 33
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 36
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8d440] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 37
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8d440] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd0634e0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8d440] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd0634e0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0634e0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0634e0] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8d440] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8d440] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] use(+1) == 2
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 34
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][dda8d440] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 35
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd0634e0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0634e0] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0201 created
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0201 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0634e0] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0201 init children
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0201 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0634e0] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0634e0] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 34
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 2
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 35
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 4
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 5
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 38
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8d500] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 39
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8d500] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd063540] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8d500] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd063540] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd063540] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd063540] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8d500] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8d500] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] use(+1) == 3
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 36
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][dda8d500] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 37
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd063540] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd063540] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0202 created
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0202 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd063540] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0202 init children
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0202 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd063540] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd063540] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 4
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 36
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 3
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 4
>nouveau T[      SW][0000:01:00.0] use(+1) == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 5
>nouveau T[      SW][0000:01:00.0] inc() == 10
>nouveau D[      SW][0000:01:00.0][0x01000414][df1d1780] created
>nouveau T[      SW][0000:01:00.0][0x01000414][df1d1780] inc() == 2
>nouveau T[      SW][0000:01:00.0] inc() == 11
>nouveau D[      SW][0000:01:00.0][0x0000016e][ddb6e220] created
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb6e220] use(+1) == 1
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb6e220] initialising...
>nouveau T[      SW][0000:01:00.0][0x01000414][df1d1780] use(+1) == 1
>nouveau T[      SW][0000:01:00.0][0x01000414][df1d1780] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] use(+1) == 4
>nouveau T[      SW][0000:01:00.0] use(+1) == 8
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] attached SW context
>nouveau D[      SW][0000:01:00.0][0x01000414][df1d1780] initialised
>nouveau T[      SW][0000:01:00.0] use(+1) == 9
>nouveau D[      SW][0000:01:00.0][0x0000016e][ddb6e220] initialised
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb6e220] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0x8000000e created
>nouveau T[glxgears[589]] 0xcccc0000:0x8000000e init running
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb6e220] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0x8000000e init children
>nouveau T[glxgears[589]] 0xcccc0000:0x8000000e init completed
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb6e220] use(-1) == 1
>nouveau T[      SW][0000:01:00.0][0x0000016e][ddb6e220] dec() == 1
>nouveau T[      SW][0000:01:00.0][0x01000414][df1d1780] dec() == 1
>nouveau T[      SW][0000:01:00.0] use(-1) == 8
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 4
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 5
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 37
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 7
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 40
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d600] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 41
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d600] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd0635a0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d600] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd0635a0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0635a0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0635a0] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d600] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x00000002][dda8d600] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] use(+1) == 5
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 38
>nouveau D[  DMAOBJ][0000:01:00.0][0x00000002][dda8d600] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 39
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd0635a0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0635a0] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0x8000000f created
>nouveau T[glxgears[589]] 0xcccc0000:0x8000000f init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0635a0] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0x8000000f init children
>nouveau T[glxgears[589]] 0xcccc0000:0x8000000f init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0635a0] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0635a0] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 6
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 38
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 5
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 6
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 30
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 7
>nouveau T[ INSTMEM][0000:01:00.0] inc() == 13
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][dda8dbc0] created
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][dda8dbc0] inc() == 2
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 33
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][dda8dbc0] dec() == 1
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] inc() == 3
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 34
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] dec() == 2
>nouveau D[  PGRAPH][0000:01:00.0][0x02000030][dd063780] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][dd063780] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][dd063780] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] initialising...
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][dda8dbc0] use(+1) == 1
>nouveau T[ INSTMEM][0000:01:00.0][0x04000000][dda8dbc0] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] use(+1) == 6
>nouveau T[ INSTMEM][0000:01:00.0] use(+1) == 11
>nouveau D[ INSTMEM][0000:01:00.0][0x04000000][dda8dbc0] initialised
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 31
>nouveau D[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] attached PGRAPH context
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] initialised
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 32
>nouveau D[  PGRAPH][0000:01:00.0][0x02000030][dd063780] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][dd063780] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0x00000000 created
>nouveau T[glxgears[589]] 0xcccc0000:0x00000000 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][dd063780] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0x00000000 init children
>nouveau T[glxgears[589]] 0xcccc0000:0x00000000 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][dd063780] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000030][dd063780] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 31
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 6
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 7
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 39
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 8
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 9
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 42
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8dd00] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 43
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8dd00] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd0637e0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8dd00] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd0637e0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0637e0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0637e0] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8dd00] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8dd00] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] use(+1) == 7
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 40
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][dda8dd00] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 41
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd0637e0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0637e0] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef1e00 created
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef1e00 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0637e0] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef1e00 init children
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef1e00 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0637e0] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0637e0] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 8
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 40
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 7
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 8
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 41
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 10
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 44
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8de40] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 45
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8de40] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd063840] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8de40] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd063840] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd063840] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd063840] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8de40] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8de40] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] use(+1) == 8
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 42
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][dda8de40] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 43
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd063840] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd063840] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0301 created
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0301 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd063840] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0301 init children
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0301 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd063840] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd063840] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 9
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 42
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 8
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 9
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 43
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 10
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 11
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 46
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8df40] inc() == 3
>nouveau T[  DMAOBJ][0000:01:00.0] inc() == 47
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8df40] dec() == 2
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd0638a0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8df40] dec() == 1
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd0638a0] created
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0638a0] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0638a0] initialising...
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8df40] use(+1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x0000003d][dda8df40] initialising...
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] use(+1) == 9
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 44
>nouveau D[  DMAOBJ][0000:01:00.0][0x0000003d][dda8df40] initialised
>nouveau T[  DMAOBJ][0000:01:00.0] use(+1) == 45
>nouveau D[  DMAOBJ][0000:01:00.0][0x02000000][dd0638a0] initialised
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0638a0] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0351 created
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0351 init running
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0638a0] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0351 init children
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef0351 init completed
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0638a0] use(-1) == 1
>nouveau T[  DMAOBJ][0000:01:00.0][0x02000000][dd0638a0] dec() == 1
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 10
>nouveau T[  DMAOBJ][0000:01:00.0] use(-1) == 44
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 10
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 32
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] inc() == 4
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 35
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] dec() == 3
>nouveau D[  PGRAPH][0000:01:00.0][0x02004097][dd063900] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][dd063900] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][dd063900] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] use(+1) == 2
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 33
>nouveau D[  PGRAPH][0000:01:00.0][0x02004097][dd063900] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][dd063900] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef3097 created
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef3097 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][dd063900] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef3097 init children
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef3097 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][dd063900] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02004097][dd063900] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] dec() == 2
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 32
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 10
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 33
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] inc() == 5
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 36
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] dec() == 4
>nouveau D[  PGRAPH][0000:01:00.0][0x02000039][dd063960] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][dd063960] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][dd063960] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] use(+1) == 3
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 34
>nouveau D[  PGRAPH][0000:01:00.0][0x02000039][dd063960] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][dd063960] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef3901 created
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef3901 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][dd063960] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef3901 init children
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef3901 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][dd063960] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000039][dd063960] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] dec() == 3
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 33
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 10
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 34
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] inc() == 6
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 37
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] dec() == 5
>nouveau D[  PGRAPH][0000:01:00.0][0x02000062][dd0639c0] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][dd0639c0] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][dd0639c0] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] use(+1) == 4
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 35
>nouveau D[  PGRAPH][0000:01:00.0][0x02000062][dd0639c0] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][dd0639c0] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef6201 created
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef6201 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][dd0639c0] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef6201 init children
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef6201 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][dd0639c0] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02000062][dd0639c0] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] dec() == 4
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 34
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 10
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 35
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] inc() == 7
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 38
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] dec() == 6
>nouveau D[  PGRAPH][0000:01:00.0][0x0200309e][dd063a20] created
>nouveau T[  PGRAPH][0000:01:00.0][0x0200309e][dd063a20] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200309e][dd063a20] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] use(+1) == 5
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 36
>nouveau D[  PGRAPH][0000:01:00.0][0x0200309e][dd063a20] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x0200309e][dd063a20] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef5201 created
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef5201 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x0200309e][dd063a20] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef5201 init children
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef5201 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x0200309e][dd063a20] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x0200309e][dd063a20] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] dec() == 5
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 35
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 9
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] inc() == 10
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 36
>nouveau D[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] created
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] inc() == 8
>nouveau T[  PGRAPH][0000:01:00.0] inc() == 39
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] dec() == 7
>nouveau D[  PGRAPH][0000:01:00.0][0x02003089][dd063a80] created
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][dd063a80] use(+1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][dd063a80] initialising...
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] use(+1) == 6
>nouveau T[  PGRAPH][0000:01:00.0] use(+1) == 37
>nouveau D[  PGRAPH][0000:01:00.0][0x02003089][dd063a80] initialised
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][dd063a80] inc() == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef7701 created
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef7701 init running
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][dd063a80] use(+1) == 2
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef7701 init children
>nouveau T[glxgears[589]] 0xcccc0000:0xbeef7701 init completed
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][dd063a80] use(-1) == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x02003089][dd063a80] dec() == 1
>nouveau T[  PGRAPH][0000:01:00.0][0x03004015][df1d1a80] dec() == 6
>nouveau T[  PGRAPH][0000:01:00.0] use(-1) == 36
>nouveau T[   PFIFO][0000:01:00.0][0xc000406e][dd060b80] dec() == 9

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Attachments on bug 58615: 71920 | 71921 | 71922 | 71923 | 71927 | 71928 | 74851 | 83509 | 85161

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