Attachment 74195 Details for Bug 60294 – copy and past startx screen

copy and past startx screen

llvm.err (text/plain), 11.63 KB, created by René Blokland on 2013-02-04 21:34:50 UTC

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Creator: René Blokland

Created: 2013-02-04 21:34:50 UTC

Size: 11.63 KB

patch

obsolete

>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     E
>0000 00000002 TEX/VTX ADDR:4
>0001 80800400 TEX/VTX INST: VTX COUNT:2
>0004 7C000000   INST: VFETCH FETCH_TYPE:0 BUFFER_ID:0
>0005 88CD1001   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0006 00080000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 7C000000   INST: VFETCH FETCH_TYPE:0 BUFFER_ID:0
>0009 88CD1002   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0010 00080010   ENDIAN:0 OFFSET:16
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST: RET COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     E
>0000 00000002 TEX/VTX ADDR:4
>0001 80800400 TEX/VTX INST: VTX COUNT:2
>0004 7C000000   INST: VFETCH FETCH_TYPE:0 BUFFER_ID:0
>0005 88CD1001   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0006 00080000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 7C000000   INST: VFETCH FETCH_TYPE:0 BUFFER_ID:0
>0009 D88D1002   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:1 MODE:1)
>0010 00080010   ENDIAN:0 OFFSET:16
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST: RET COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 12 dw -- 3 gprs ---------------------
>     E
>0000 00000002 TEX/VTX ADDR:4
>0001 80800400 TEX/VTX INST: VTX COUNT:2
>0004 7C000000   INST: VFETCH FETCH_TYPE:0 BUFFER_ID:0
>0005 88CD1001   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)
>0006 00080000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0008 7C000000   INST: VFETCH FETCH_TYPE:0 BUFFER_ID:0
>0009 988D1002   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:0 MODE:1)
>0010 00080010   ENDIAN:0 OFFSET:16
>0011 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST: RET COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>bytecode 8 dw -- 2 gprs ---------------------
> E
>0000 00000002 TEX/VTX ADDR:4
>0001 80800000 TEX/VTX INST: VTX COUNT:1
>0004 7C000000   INST: VFETCH FETCH_TYPE:0 BUFFER_ID:0
>0005 93564001   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:4 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:13 NUM:1 COMP:0 MODE:1)
>0006 00080000   ENDIAN:0 OFFSET:0
>0007 00000000   
>0002 00000000 CF ADDR:0
>0003 85000000 CF INST: RET COND:0 POP_COUNT:0
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = insertelement <4 x float> undef, float %0, i32 0
>  %9 = insertelement <4 x float> %8, float %1, i32 1
>  %10 = insertelement <4 x float> %9, float %2, i32 2
>  %11 = insertelement <4 x float> %10, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1)
>  %12 = insertelement <4 x float> undef, float %4, i32 0
>  %13 = insertelement <4 x float> %12, float %5, i32 1
>  %14 = insertelement <4 x float> %13, float %6, i32 2
>  %15 = insertelement <4 x float> %14, float %7, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2)
>  ret void
>}
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X
>        %T1_X<def> = KILL %T1_X, %T1_XYZW<imp-def>
>        %T1_Y<def> = KILL %T1_Y, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
>        %T1_Z<def> = KILL %T1_Z, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
>        %T1_W<def> = KILL %T1_W, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
>        %T2_X<def> = KILL %T2_X, %T2_XYZW<imp-def>
>        %T2_Y<def> = KILL %T2_Y, %T2_XYZW<imp-use,kill>, %T2_XYZW<imp-def>
>        %T2_Z<def> = KILL %T2_Z, %T2_XYZW<imp-use,kill>, %T2_XYZW<imp-def>
>        %T2_W<def> = KILL %T2_W, %T2_XYZW<imp-use,kill>, %T2_XYZW<imp-def>
>        EG_ExportSwz %T1_XYZW<kill>, 1, 60, 0, 1, 2, 3, 84, 0
>        EG_ExportSwz %T2_XYZW<kill>, 2, 0, 0, 1, 2, 3, 84, 1
>        RETURN
>
># End machine code for function main.
>
>--------------------------------------------------------------
>--------------------------------------------------------------
>bytecode 6 dw -- 3 gprs ---------------------
>     E
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST: CALL_FS COND:0 POP_COUNT:0
>0002 C000A03C EXPORT_DONE GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0003 95000688 EXPORT_DONE SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST: EXPORT_DONE BURST_COUNT:1 EOP:0
>0004 C0014000 EXPORT_DONE GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0005 95200688 EXPORT_DONE SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST: EXPORT_DONE BURST_COUNT:1 EOP:1
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>  0: MOV OUT[0], IN[0]
>  1: END
>STREAMOUT
>  0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.stream.output(<4 x float> %7, i32 0, i32 0, i32 1)
>  %8 = insertelement <4 x float> undef, float %0, i32 0
>  %9 = insertelement <4 x float> %8, float %1, i32 1
>  %10 = insertelement <4 x float> %9, float %2, i32 2
>  %11 = insertelement <4 x float> %10, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1)
>  call void @llvm.R600.store.dummy(i32 2)
>  ret void
>}
>
>declare float @llvm.R600.load.input(i32) readnone
>
>declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32)
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>declare void @llvm.R600.store.dummy(i32)
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %T1_W %T1_Z %T1_Y %T1_X
>        %T1_X<def> = KILL %T1_X, %T1_XYZW<imp-def>
>        %T1_Y<def> = KILL %T1_Y, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
>        %T1_Z<def> = KILL %T1_Z, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
>        %T1_W<def> = KILL %T1_W, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
>        EG_ExportBuf %T1_XYZW, 0, 0, 4095, 1, 64, 0
>        EG_ExportSwz %T1_XYZW<kill>, 1, 60, 0, 1, 2, 3, 84, 0
>        EG_ExportSwz %T0_XYZW<undef>, 2, 0, 7, 7, 7, 7, 84, 1
>        RETURN
>
># End machine code for function main.
>
>--------------------------------------------------------------
>bytecode 8 dw -- 2 gprs ---------------------
>     E
>0000 00000000 CF ADDR:0
>0001 84C00000 CF INST: CALL_FS COND:0 POP_COUNT:0
>0002 00008000 EXPORT MEM_STREAM0_BUF0 GPR:1 ELEM_SIZE:0 ARRAY_BASE:0 TYPE:0
>0003 90001FFF EXPORT MEM_STREAM0_BUF0 ARRAY_SIZE:4095 COMP_MASK:1 BARRIER:1 INST: MEM_STREAM0_BUF0 BURST_COUNT:1 EOP:0
>0004 C000A03C EXPORT_DONE GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1
>0005 95000688 EXPORT_DONE SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST: EXPORT_DONE BURST_COUNT:1 EOP:0
>0006 C0004000 EXPORT_DONE GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2
>0007 95200FFF EXPORT_DONE SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST: EXPORT_DONE BURST_COUNT:1 EOP:1
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  %0 = call float @llvm.R600.interp.input(i32 0, i32 -1)
>  %1 = call float @llvm.R600.interp.input(i32 1, i32 -1)
>  %2 = call float @llvm.R600.interp.input(i32 2, i32 -1)
>  %3 = call float @llvm.R600.interp.input(i32 3, i32 -1)
>  call void @llvm.R600.store.dummy(i32 0)
>  ret void
>}
>
>declare float @llvm.R600.interp.input(i32, i32) readnone
>
>declare void @llvm.R600.store.dummy(i32)
># Machine code for function main: Post SSA, not tracking liveness
>
>BB#0: derived from LLVM BB %main_body
>        EG_ExportSwz %T0_XYZW<undef>, 0, 0, 7, 7, 7, 7, 84, 1
>        RETURN
>
># End machine code for function main.
>
>--------------------------------------------------------------
>bytecode 2 dw -- 1 gprs ---------------------
>     E
>0000 C0000000 EXPORT_DONE GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0
>0001 95200FFF EXPORT_DONE SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST: EPORT_DONE BURST_COUNT:1 EOP:1
>--------------------------------------
>______________________________________________________________
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL TEMP[0]
>IMM[0] FLT32 {    0,5000,     0,2500,    -0,2500,     0,0000}
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[2], IN[1]
>  2: MOV OUT[1], IN[2]
>  3: MUL TEMP[0].x, IN[1].wwww, IMM[0].xxxx
>  4: MUL TEMP[0].y, IN[1].wwww, IMM[0].yyyy
>  5: MOV OUT[3].x, IN[1]
>  6: MAD OUT[3].y, IN[1].yyyy, TEMP[0].xxxx, IMM[0].yyyy
>  7: MAD OUT[3].z, IN[1].yyyy, TEMP[0].yyyy, IMM[0].yyyy
>  8: RCP OUT[3].w, TEMP[0].xxxx
>  9: MOV OUT[4].x, IN[1]
> 10: MAD OUT[4].y, IN[1].yyyy, TEMP[0].xxxx, IMM[0].zzzz
> 11: MAD OUT[4].z, IN[1].yyyy, TEMP[0].yyyy, IMM[0].zzzz
> 12: RCP OUT[4].w, TEMP[0].yyyy
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main() {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = call float @llvm.R600.load.input(i32 12)
>  %9 = call float @llvm.R600.load.input(i32 13)
>  %10 = call float @llvm.R600.load.input(i32 14)
>  %11 = call float @llvm.R600.load.input(i32 15)
>  %12 = fmul float %7, plugin-container: /usr/src/X/llvm/lib/Support/APFloat.cp:286: void interpretDecimal(StringRef::iterator, StringRef::iterator, decimalIn

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Attachments on bug 60294: 74195 | 74198 | 74206 | 74247

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