Attachment 77187 Details for Bug 32934 – intel_reg_dumper connect via Dock+DP

intel_reg_dumper connect via Dock+DP

intel2 (text/plain), 13.79 KB, created by Stefan SF on 2013-03-29 08:04:50 UTC

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Creator: Stefan SF

Created: 2013-03-29 08:04:50 UTC

Size: 13.79 KB

patch

obsolete

>                    PGETBL_CTL: 0x00000008
>               GEN6_INSTDONE_1: 0xfffffffe
>               GEN6_INSTDONE_2: 0xffffffff
>                  CPU_VGACNTRL: 0x80000000 (disabled)
>    DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
>                     RR_HW_CTL: 0x00000000 (low 0, high 0)
>                FDI_PLL_BIOS_0: 0x082b3019
>                FDI_PLL_BIOS_1: 0x00000000
>                FDI_PLL_BIOS_2: 0x00000000
>       DISPLAY_PORT_PLL_BIOS_0: 0x0807012b
>       DISPLAY_PORT_PLL_BIOS_1: 0x00000000
>       DISPLAY_PORT_PLL_BIOS_2: 0x00000000
>              FDI_PLL_FREQ_CTL: 0x00053687
>                     PIPEACONF: 0xc0000050 (enabled, active, pf-pd, rotate 0, 6bpc)
>                      HTOTAL_A: 0x0783059f (1440 active, 1924 total)
>                      HBLANK_A: 0x0783059f (1440 start, 1924 end)
>                       HSYNC_A: 0x05ef05cf (1488 start, 1520 end)
>                      VTOTAL_A: 0x039d0383 (900 active, 926 total)
>                      VBLANK_A: 0x039d0383 (900 start, 926 end)
>                       VSYNC_A: 0x038c0386 (903 start, 909 end)
>                  VSYNCSHIFT_A: 0x00000000
>                      PIPEASRC: 0x059f0383 (1440, 900)
>                 PIPEA_DATA_M1: 0x7e1d5bb4 (TU 64, val 0x1d5bb4 1924020)
>                 PIPEA_DATA_N1: 0x0020f580 (val 0x20f580 2160000)
>                 PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_M1: 0x0001a18a (val 0x1a18a 106890)
>                 PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>                 PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPACNTR: 0xd8004400 (enabled)
>                      DSPABASE: 0x00000000
>                    DSPASTRIDE: 0x00002c00 (176)
>                      DSPASURF: 0x0a023000
>                   DSPATILEOFF: 0x00000000 (0, 0)
>                     PIPEBCONF: 0xc0000000 (enabled, active, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_B: 0x069704ff (1280 active, 1688 total)
>                      HBLANK_B: 0x069704ff (1280 start, 1688 end)
>                       HSYNC_B: 0x059f052f (1328 start, 1440 end)
>                      VTOTAL_B: 0x042903ff (1024 active, 1066 total)
>                      VBLANK_B: 0x042903ff (1024 start, 1066 end)
>                       VSYNC_B: 0x04030400 (1025 start, 1028 end)
>                  VSYNCSHIFT_B: 0x00000000
>                      PIPEBSRC: 0x04ff03ff (1280, 1024)
>                 PIPEB_DATA_M1: 0x7e278d00 (TU 64, val 0x278d00 2592000)
>                 PIPEB_DATA_N1: 0x0041eb00 (val 0x41eb00 4320000)
>                 PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_M1: 0x0001a5e0 (val 0x1a5e0 108000)
>                 PIPEB_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>                 PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPBCNTR: 0xd8004400 (enabled)
>                      DSPBBASE: 0xffff6680
>                    DSPBSTRIDE: 0x00002c00 (176)
>                      DSPBSURF: 0x0a02e000
>                   DSPBTILEOFF: 0x00000020 (32, 0)
>                     PIPECCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_C: 0x00000000 (1 active, 1 total)
>                      HBLANK_C: 0x00000000 (1 start, 1 end)
>                       HSYNC_C: 0x00000000 (1 start, 1 end)
>                      VTOTAL_C: 0x00000000 (1 active, 1 total)
>                      VBLANK_C: 0x00000000 (1 start, 1 end)
>                       VSYNC_C: 0x00000000 (1 start, 1 end)
>                  VSYNCSHIFT_C: 0x00000000
>                      PIPECSRC: 0x00000000 (1, 1)
>                 PIPEC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEC_DATA_N1: 0x00000000 (val 0x0 0)
>                 PIPEC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEC_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_M1: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_N1: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPCCNTR: 0x00000000 (disabled)
>                      DSPCBASE: 0x00000000
>                    DSPCSTRIDE: 0x00000000 (0)
>                      DSPCSURF: 0x00000000
>                   DSPCTILEOFF: 0x00000000 (0, 0)
>                     PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFA_CTL_2: 0x00007e3e (vscale 0.986267)
>                     PFA_CTL_3: 0x00003f1f (vscale initial phase 0.493134)
>                     PFA_CTL_4: 0x00007d30 (hscale 0.978027)
>                   PFA_WIN_POS: 0x00000000 (0, 0)
>                  PFA_WIN_SIZE: 0x00000000 (0, 0)
>                     PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFB_CTL_2: 0x00007e00 (vscale 0.984375)
>                     PFB_CTL_3: 0x00003f00 (vscale initial phase 0.492188)
>                     PFB_CTL_4: 0x00007d80 (hscale 0.980469)
>                   PFB_WIN_POS: 0x00000000 (0, 0)
>                  PFB_WIN_SIZE: 0x00000000 (0, 0)
>                     PFC_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFC_CTL_2: 0x00000000 (vscale 0.000000)
>                     PFC_CTL_3: 0x00000000 (vscale initial phase 0.000000)
>                     PFC_CTL_4: 0x00000000 (hscale 0.000000)
>                   PFC_WIN_POS: 0x00000000 (0, 0)
>                  PFC_WIN_SIZE: 0x00000000 (0, 0)
>              PCH_DREF_CONTROL: 0x00001202 (cpu source disable, ssc_source enable, nonspread_source disable, superspread_source disable, ssc4_mode downspread, ssc1 enable, ssc4 disable)
>               PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>              PCH_DPLL_TMR_CFG: 0x0271186a
>                PCH_SSC4_PARMS: 0x00000000
>            PCH_SSC4_AUX_PARMS: 0x00000000
>                  PCH_DPLL_SEL: 0x00000000 (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>           PCH_DPLL_ANALOG_CTL: 0x00008000
>                    PCH_DPLL_A: 0x89086008 (enable, sdvo high speed no, mode LVDS, p2 Div 7, FPA0 P1 4, FPA1 P1 4, refclk SSC, sdvo/hdmi mul 1)
>                    PCH_DPLL_B: 0xc4040004 (enable, sdvo high speed yes, mode (null), p2 (null), FPA0 P1 3, FPA1 P1 3, refclk default 120Mhz, sdvo/hdmi mul 1)
>                      PCH_FPA0: 0x00021008 (n = 2, m1 = 16, m2 = 8)
>                      PCH_FPA1: 0x00021008 (n = 2, m1 = 16, m2 = 8)
>                      PCH_FPB0: 0x00010c09 (n = 1, m1 = 12, m2 = 9)
>                      PCH_FPB1: 0x00010c09 (n = 1, m1 = 12, m2 = 9)
>                TRANS_HTOTAL_A: 0x0783059f (1440 active, 1924 total)
>                TRANS_HBLANK_A: 0x0783059f (1440 start, 1924 end)
>                 TRANS_HSYNC_A: 0x05ef05cf (1488 start, 1520 end)
>                TRANS_VTOTAL_A: 0x039d0383 (900 active, 926 total)
>                TRANS_VBLANK_A: 0x039d0383 (900 start, 926 end)
>                 TRANS_VSYNC_A: 0x038c0386 (903 start, 909 end)
>            TRANS_VSYNCSHIFT_A: 0x00000000
>                TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_B: 0x069704ff (1280 active, 1688 total)
>                TRANS_HBLANK_B: 0x069704ff (1280 start, 1688 end)
>                 TRANS_HSYNC_B: 0x059f052f (1328 start, 1440 end)
>                TRANS_VTOTAL_B: 0x042903ff (1024 active, 1066 total)
>                TRANS_VBLANK_B: 0x042903ff (1024 start, 1066 end)
>                 TRANS_VSYNC_B: 0x04030400 (1025 start, 1028 end)
>            TRANS_VSYNCSHIFT_B: 0x00000000
>                TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
>                 TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
>                TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_VBLANK_C: 0x00000044 (69 start, 1 end)
>                 TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
>            TRANS_VSYNCSHIFT_C: 0x00000000
>                TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                    TRANSACONF: 0xc0000040 (enable, active, progressive)
>                    TRANSBCONF: 0xc0000000 (enable, active, progressive)
>                    TRANSCCONF: 0x00000000 (disable, inactive, progressive)
>                   FDI_TXA_CTL: 0xb0044000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXB_CTL: 0xb00c4000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable)
>                   FDI_RXA_CTL: 0xb0022050 (enable, train pattern not train, port width X1, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXB_CTL: 0xb0082050 (enable, train pattern not train, port width X2, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXC_CTL: 0x00000000 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing disable, RawClk)
>                  DPAFE_BMFUNC: 0x00100040
>             DPAFE_DL_IREFCAL0: 0x00000000
>             DPAFE_DL_IREFCAL1: 0x0f810880
>              DPAFE_DP_IREFCAL: 0x00100040
>             PCH_DSPCLK_GATE_D: 0x100003a0
>              PCH_DSP_CHICKEN1: 0x00400000
>              PCH_DSP_CHICKEN2: 0x02600000
>              PCH_DSP_CHICKEN3: 0x00000000
>                  FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
>                  FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
>                  FDI_RXC_MISC: 0x00000000 (FDI Delay 0)
>               FDI_RXA_TUSIZE1: 0x7e000000
>               FDI_RXA_TUSIZE2: 0x7e000000
>               FDI_RXB_TUSIZE1: 0x7e000000
>               FDI_RXB_TUSIZE2: 0x7e000000
>               FDI_RXC_TUSIZE1: 0x00000000
>               FDI_RXC_TUSIZE2: 0x00000000
>                 FDI_PLL_CTL_1: 0x33505248
>                 FDI_PLL_CTL_2: 0x00000000
>                   FDI_RXA_IIR: 0x00000000
>                   FDI_RXA_IMR: 0x000000ff
>                   FDI_RXB_IIR: 0x00000000
>                   FDI_RXB_IMR: 0x000000ff
>                      PCH_ADPA: 0x00f40000 (disabled, transcoder A, -hsync, -vsync)
>                         HDMIB: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
>                         HDMIC: 0xc000001c (enabled pipe C 8bpc SDVO DVI audio disabled +vsync +hsync detected)
>                         HDMID: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
>                      PCH_LVDS: 0x8030033e (enabled, pipe A, 18 bit, 2 channels)
>                     CPU_eDP_A: 0x00000018
>                      PCH_DP_B: 0x0000001c
>                      PCH_DP_C: 0x0000001c
>                      PCH_DP_D: 0x0000001c
>                TRANS_DP_CTL_A: 0x00000000 (enabled, pipe A, 18 bit, 2 channels)
>                TRANS_DP_CTL_B: 0x00000000 (enabled, pipe A, 18 bit, 2 channels)
>                TRANS_DP_CTL_C: 0x00000000 (enabled, pipe A, 18 bit, 2 channels)
>              BLC_PWM_CPU_CTL2: 0x80000000
>               BLC_PWM_CPU_CTL: 0x00001155
>              BLC_PWM_PCH_CTL1: 0x80000000
>              BLC_PWM_PCH_CTL2: 0x11551155
>                 PCH_PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>                PCH_PP_CONTROL: 0xabcd0003 (blacklight disabled, power down on reset, panel on)
>              PCH_PP_ON_DELAYS: 0x00fa09c4
>             PCH_PP_OFF_DELAYS: 0x00fa09c4
>                PCH_PP_DIVISOR: 0x00186903
>                      PORT_DBG: 0x00000000 (HW DRRS off)
>            RC6_RESIDENCY_TIME: 0xffffffff
>           RC6p_RESIDENCY_TIME: 0xffffffff
>          RC6pp_RESIDENCY_TIME: 0xffffffff

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Attachments on bug 32934: 41787 | 41788 | 41790 | 41791 | 41792 | 41793 | 41794 | 41795 | 56797 | 56798 | 60319 | 60320 | 60340 | 60341 | 60343 | 60344 | 77186 | 77187

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