Attachment 78993 Details for Bug 64329 – dmesg of the session with drm.debug=6

dmesg of the session with drm.debug=6

dmesg-resume-broken (text/plain), 122.83 KB, created by Vedran Rodic on 2013-05-07 17:31:59 UTC

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Creator: Vedran Rodic

Created: 2013-05-07 17:31:59 UTC

Size: 122.83 KB

patch

obsolete

>[   11.820059] [drm:intel_decrease_pllclock], downclocking LVDS
>[   11.870470] [drm:intel_increase_pllclock], upclocking LVDS
>[   13.820070] [drm:intel_decrease_pllclock], downclocking LVDS
>[   14.208392] [drm:intel_increase_pllclock], upclocking LVDS
>[   14.636676] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 47
>[   14.636685] evbug: Event. Dev: input3, Type: 1, Code: 47, Value: 1
>[   14.636690] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   14.756085] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 47
>[   14.756094] evbug: Event. Dev: input3, Type: 1, Code: 47, Value: 0
>[   14.756099] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   14.825857] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   14.825863] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 1
>[   14.825868] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   14.905352] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   14.905360] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 0
>[   14.905365] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.015494] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 32
>[   15.015502] evbug: Event. Dev: input3, Type: 1, Code: 32, Value: 1
>[   15.015507] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.071010] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 32
>[   15.071019] evbug: Event. Dev: input3, Type: 1, Code: 32, Value: 0
>[   15.071023] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.165920] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 19
>[   15.165926] evbug: Event. Dev: input3, Type: 1, Code: 19, Value: 1
>[   15.165931] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.237197] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 19
>[   15.237205] evbug: Event. Dev: input3, Type: 1, Code: 19, Value: 0
>[   15.237210] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.338370] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 30
>[   15.338376] evbug: Event. Dev: input3, Type: 1, Code: 30, Value: 1
>[   15.338381] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.418502] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 49
>[   15.418510] evbug: Event. Dev: input3, Type: 1, Code: 49, Value: 1
>[   15.418515] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.420051] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 30
>[   15.420058] evbug: Event. Dev: input3, Type: 1, Code: 30, Value: 0
>[   15.420063] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.489383] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 49
>[   15.489390] evbug: Event. Dev: input3, Type: 1, Code: 49, Value: 0
>[   15.489395] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.609985] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 28
>[   15.609991] evbug: Event. Dev: input3, Type: 1, Code: 28, Value: 1
>[   15.609996] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.713232] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 28
>[   15.713242] evbug: Event. Dev: input3, Type: 1, Code: 28, Value: 0
>[   15.713247] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.764540] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 46
>[   15.764546] evbug: Event. Dev: input3, Type: 1, Code: 46, Value: 1
>[   15.764551] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.808076] [drm:intel_decrease_pllclock], downclocking LVDS
>[   15.860108] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 19
>[   15.860115] evbug: Event. Dev: input3, Type: 1, Code: 19, Value: 1
>[   15.860120] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.863833] [drm:intel_increase_pllclock], upclocking LVDS
>[   15.908018] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 46
>[   15.908025] evbug: Event. Dev: input3, Type: 1, Code: 46, Value: 0
>[   15.908030] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   15.922871] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 49
>[   15.922877] evbug: Event. Dev: input3, Type: 1, Code: 49, Value: 1
>[   15.922882] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   16.025092] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 23
>[   16.025103] evbug: Event. Dev: input3, Type: 1, Code: 23, Value: 1
>[   16.025108] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   16.026501] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 19
>[   16.026509] evbug: Event. Dev: input3, Type: 1, Code: 19, Value: 0
>[   16.026514] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   16.056074] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 49
>[   16.056084] evbug: Event. Dev: input3, Type: 1, Code: 49, Value: 0
>[   16.056089] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   16.095347] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 23
>[   16.095353] evbug: Event. Dev: input3, Type: 1, Code: 23, Value: 0
>[   16.095358] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   16.119551] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X
>[   16.197602] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 7
>[   16.197608] evbug: Event. Dev: input3, Type: 1, Code: 7, Value: 1
>[   16.197613] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   16.220240] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X
>[   16.220795] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
>[   16.299385] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 10
>[   16.299393] evbug: Event. Dev: input3, Type: 1, Code: 10, Value: 1
>[   16.299398] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   16.300928] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 7
>[   16.300936] evbug: Event. Dev: input3, Type: 1, Code: 7, Value: 0
>[   16.300941] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   16.364381] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 10
>[   16.364388] evbug: Event. Dev: input3, Type: 1, Code: 10, Value: 0
>[   16.364393] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   16.451076] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 28
>[   16.451082] evbug: Event. Dev: input3, Type: 1, Code: 28, Value: 1
>[   16.451087] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   16.562398] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 28
>[   16.562409] evbug: Event. Dev: input3, Type: 1, Code: 28, Value: 0
>[   16.562414] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   17.664988] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   17.665004] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[   17.665049] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes :
>[   17.665055] [drm:drm_mode_debug_printmodeline], Modeline 18:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa
>[   17.665065] [drm:drm_mode_debug_printmodeline], Modeline 22:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   17.665074] [drm:drm_mode_debug_printmodeline], Modeline 19:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   17.665083] [drm:drm_mode_debug_printmodeline], Modeline 20:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   17.665092] [drm:drm_mode_debug_printmodeline], Modeline 21:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   17.665105] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   17.665838] [drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[   17.665847] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1]
>[   17.680058] [drm:intel_crt_detect], CRT not detected via hotplug
>[   17.684106] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[   17.684120] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   17.684127] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   17.684132] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[   17.684411] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   17.684416] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[   17.684422] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[   17.684430] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1] disconnected
>[   17.684451] [drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[   17.684458] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1]
>[   17.700058] [drm:intel_crt_detect], CRT not detected via hotplug
>[   17.704050] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[   17.704064] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   17.704071] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   17.704076] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[   17.704354] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   17.704359] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[   17.704365] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[   17.704372] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1] disconnected
>[   17.808054] [drm:intel_decrease_pllclock], downclocking LVDS
>[   18.929630] [drm:intel_increase_pllclock], upclocking LVDS
>[   20.820139] [drm:intel_decrease_pllclock], downclocking LVDS
>[   21.804577] [drm:intel_increase_pllclock], upclocking LVDS
>[   22.402658] IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready
>[   22.816048] [drm:intel_decrease_pllclock], downclocking LVDS
>[   23.004468] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X
>[   23.108203] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X
>[   23.108765] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
>[   23.602003] IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready
>[   24.248491] [drm:intel_increase_pllclock], upclocking LVDS
>[   25.820055] [drm:intel_decrease_pllclock], downclocking LVDS
>[   26.843005] evbug: Event. Dev: input7, Type: 2, Code: 0, Value: -1
>[   26.843016] evbug: Event. Dev: input7, Type: 0, Code: 0, Value: 0
>[   28.547177] [drm:intel_increase_pllclock], upclocking LVDS
>[   28.940760] wlan0: authenticate with 00:14:7f:24:8f:d8
>[   28.944450] wlan0: send auth to 00:14:7f:24:8f:d8 (try 1/3)
>[   28.946486] wlan0: authenticated
>[   28.948034] wlan0: associate with 00:14:7f:24:8f:d8 (try 1/3)
>[   28.950734] wlan0: RX AssocResp from 00:14:7f:24:8f:d8 (capab=0x431 status=0 aid=3)
>[   28.955375] wlan0: associated
>[   28.955408] IPv6: ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready
>[   29.820059] [drm:intel_decrease_pllclock], downclocking LVDS
>[   30.960130] evbug: Event. Dev: input0, Type: 5, Code: 0, Value: 1
>[   30.960140] evbug: Event. Dev: input0, Type: 0, Code: 0, Value: 0
>[   33.526556] [drm:intel_crtc_cursor_set], cursor off
>[   33.527367] [drm:intel_increase_pllclock], upclocking LVDS
>[   34.808045] [drm:intel_decrease_pllclock], downclocking LVDS
>[   35.114936] wlan0: deauthenticating from 00:14:7f:24:8f:d8 by local choice (reason=3)
>[   35.137210] cfg80211: Calling CRDA to update world regulatory domain
>[   35.147807] cfg80211: World regulatory domain updated:
>[   35.147818] cfg80211:   (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
>[   35.147824] cfg80211:   (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
>[   35.147830] cfg80211:   (2457000 KHz - 2482000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
>[   35.147836] cfg80211:   (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
>[   35.147841] cfg80211:   (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
>[   35.147847] cfg80211:   (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
>[   35.226952] IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready
>[   35.580459] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X
>[   35.684189] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X
>[   35.684734] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
>[   35.951403] IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready
>[   36.052814] IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready
>[   36.410312] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X
>[   36.512195] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X
>[   36.512742] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
>[   36.760346] PM: Syncing filesystems ... done.
>[   36.765429] Freezing user space processes ... (elapsed 0.01 seconds) done.
>[   36.780124] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
>[   36.796135] Suspending console(s) (use no_console_suspend to debug)
>[   36.798184] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[   36.798727] sd 0:0:0:0: [sda] Stopping disk
>[   36.860350] nsc-ircc 00:09: disabled
>[   36.861957] [drm:i915_get_vblank_counter], trying to get vblank count for disabled pipe A
>[   36.861971] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   37.188880] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   37.188887] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   37.188892] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   37.188896] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   37.188900] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   37.188903] [drm:i9xx_update_wm], memory self refresh disabled
>[   37.204095] i915 0000:00:02.0: power state changed by ACPI to D3hot
>[   37.204176] PM: suspend of devices complete after 407.659 msecs
>[   37.204536] PM: late suspend of devices complete after 0.354 msecs
>[   37.220182] pcieport 0000:00:1c.0: System wakeup enabled by ACPI
>[   37.236245] ehci-pci 0000:00:1d.7: System wakeup enabled by ACPI
>[   37.252035] ehci-pci 0000:00:1d.7: power state changed by ACPI to D3hot
>[   37.252161] uhci_hcd 0000:00:1d.2: System wakeup enabled by ACPI
>[   37.252169] uhci_hcd 0000:00:1d.2: power state changed by ACPI to D2
>[   37.252239] uhci_hcd 0000:00:1d.1: System wakeup enabled by ACPI
>[   37.253035] uhci_hcd 0000:00:1d.0: System wakeup enabled by ACPI
>[   37.253045] uhci_hcd 0000:00:1d.0: power state changed by ACPI to D2
>[   37.253357] PM: noirq suspend of devices complete after 48.816 msecs
>[   37.253800] ACPI: Preparing to enter system sleep state S3
>[   37.258589] PM: Saving platform NVS memory
>[   37.258863] Disabling non-boot CPUs ...
>[   37.260626] smpboot: CPU 1 is now offline
>[   37.261073] ACPI: Low-level resume complete
>[   37.261073] PM: Restoring platform NVS memory
>[   37.261073] Enabling non-boot CPUs ...
>[   37.261073] smpboot: Booting Node 0 Processor 1 APIC 0x1
>[   37.260600] Initializing CPU#1
>[   37.260600] Disabled fast string operations
>[   37.288157] CPU1 is up
>[   37.289903] ACPI: Waking up from system sleep state S3
>[   37.361498] i915 0000:00:02.0: power state changed by ACPI to D0
>[   37.392441] uhci_hcd 0000:00:1d.0: power state changed by ACPI to D0
>[   37.393251] uhci_hcd 0000:00:1d.0: System wakeup disabled by ACPI
>[   37.393330] uhci_hcd 0000:00:1d.1: System wakeup disabled by ACPI
>[   37.393338] uhci_hcd 0000:00:1d.2: power state changed by ACPI to D0
>[   37.393413] uhci_hcd 0000:00:1d.2: System wakeup disabled by ACPI
>[   37.393449] ehci-pci 0000:00:1d.7: power state changed by ACPI to D0
>[   37.408149] ehci-pci 0000:00:1d.7: System wakeup disabled by ACPI
>[   37.488395] PM: noirq resume of devices complete after 126.963 msecs
>[   37.488438] pciehp 0000:00:1c.0:pcie04: Card present on Slot(2)
>[   37.488618] PM: early resume of devices complete after 0.150 msecs
>[   37.488717] i915 0000:00:02.0: setting latency timer to 64
>[   37.488944] snd_hda_intel 0000:00:1b.0: irq 44 for MSI/MSI-X
>[   37.489064] evbug: Event. Dev: input0, Type: 5, Code: 0, Value: 0
>[   37.489066] evbug: Event. Dev: input0, Type: 0, Code: 0, Value: 0
>[   37.489298] uhci_hcd 0000:00:1d.0: setting latency timer to 64
>[   37.489332] usb usb2: root hub lost power or was reset
>[   37.489388] uhci_hcd 0000:00:1d.1: setting latency timer to 64
>[   37.489418] usb usb3: root hub lost power or was reset
>[   37.489473] uhci_hcd 0000:00:1d.2: setting latency timer to 64
>[   37.489502] usb usb4: root hub lost power or was reset
>[   37.489556] uhci_hcd 0000:00:1d.3: setting latency timer to 64
>[   37.489587] usb usb5: root hub lost power or was reset
>[   37.489644] ehci-pci 0000:00:1d.7: setting latency timer to 64
>[   37.489673] pci 0000:00:1e.0: setting latency timer to 64
>[   37.489724] ata_piix 0000:00:1f.2: setting latency timer to 64
>[   37.489873] sdhci-pci 0000:15:00.2: Will use DMA mode even though HW doesn't fully claim to support it.
>[   37.490913] sdhci-pci 0000:15:00.2: Will use DMA mode even though HW doesn't fully claim to support it.
>[   37.503172] [drm:i915_redisable_vga], Something enabled VGA plane, disabling it
>[   37.503486] [drm:intel_opregion_setup], graphic opregion physical addr: 0x0
>[   37.503488] [drm:intel_opregion_setup], ACPI OpRegion not supported!
>[   37.503763] [drm:intel_modeset_setup_hw_state], [CRTC:3] hw state readout: disabled
>[   37.503766] [drm:intel_modeset_setup_hw_state], [CRTC:4] hw state readout: disabled
>[   37.503770] [drm:intel_modeset_setup_hw_state], [ENCODER:6:LVDS-6] hw state readout: disabled, pipe=0
>[   37.503774] [drm:intel_modeset_setup_hw_state], [ENCODER:17:DAC-17] hw state readout: disabled, pipe=0
>[   37.503778] [drm:intel_modeset_setup_hw_state], [CONNECTOR:5:LVDS-1] hw state readout: disabled
>[   37.503781] [drm:intel_modeset_setup_hw_state], [CONNECTOR:16:VGA-1] hw state readout: disabled
>[   37.503787] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[   37.503791] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   37.503797] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   37.503800] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   37.503803] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   37.503808] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   37.504453] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   37.504458] [drm:drm_mode_debug_printmodeline], Modeline 0:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa
>[   37.504468] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   37.568061] [drm:intel_wait_for_vblank], vblank wait timed out
>[   37.568068] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   37.568072] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   37.568076] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   37.568080] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   37.568084] [drm:i9xx_update_wm], memory self refresh disabled
>[   37.568089] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:1024x768]
>[   37.568095] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   37.568099] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   37.568102] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   37.568106] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   37.568110] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   37.568113] [drm:i9xx_update_wm], self-refresh entries: 64
>[   37.568118] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   37.568121] [drm:i9xx_update_wm], memory self refresh enabled
>[   37.568574] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   37.592085] pciehp 0000:00:1c.0:pcie04: Device 0000:02:00.0 already exists at 0000:02:00, cannot hot-add
>[   37.592090] pciehp 0000:00:1c.0:pcie04: Device 0000:02:00.0 already exists at 0000:02:00, cannot hot-add
>[   37.592094] pciehp 0000:00:1c.0:pcie04: Cannot add device at 0000:02:00
>[   37.592097] pciehp 0000:00:1c.0:pcie04: Cannot add device at 0000:02:00
>[   37.592126] pciehp 0000:00:1c.1:pcie04: Device 0000:03:00.0 already exists at 0000:03:00, cannot hot-add
>[   37.592130] pciehp 0000:00:1c.1:pcie04: Cannot add device at 0000:03:00
>[   37.592178] pcieport 0000:00:1c.0: System wakeup disabled by ACPI
>[   37.592201] e1000e 0000:02:00.0: Disabling ASPM L0s L1
>[   37.592315] e1000e 0000:02:00.0: irq 46 for MSI/MSI-X
>[   37.592692] nsc-ircc 00:09: activated
>[   37.600105] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   37.600114] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   37.600120] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   37.600125] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   37.600128] [drm:intel_modeset_check_state], [CRTC:3]
>[   37.600133] [drm:intel_modeset_check_state], [CRTC:4]
>[   37.600143] [drm:intel_resume_hotplug], running encoder hotplug functions
>[   37.616058] [drm:intel_crt_detect], CRT not detected via hotplug
>[   37.620053] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[   37.620058] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   37.620061] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   37.620065] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[   37.620343] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   37.620346] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[   37.620348] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[   37.620351] [drm:drm_helper_hpd_irq_event], [CONNECTOR:16:VGA-1] status updated from 3 to 2
>[   38.477335] firewire_core 0000:15:00.1: rediscovered device fw0
>[   38.477674] ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded
>[   38.477678] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out
>[   38.477682] ata1.00: ACPI cmd ef/03:45:00:00:00:a0 (SET FEATURES) filtered out
>[   38.477685] ata1.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out
>[   38.477688] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out
>[   38.492399] ata1.00: configured for UDMA/133
>[   38.492461] sd 0:0:0:0: [sda] Starting disk
>[   38.500204] tpm_tis 00:0a: TPM is disabled/deactivated (0x6)
>[   38.500266] evbug: Event. Dev: input1, Type: 0, Code: 0, Value: 1
>[   38.500277] evbug: Event. Dev: input2, Type: 0, Code: 0, Value: 1
>[   38.503557] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 1
>[   38.503584] evbug: Event. Dev: input4, Type: 0, Code: 0, Value: 1
>[   38.576072] usb 5-1: reset full-speed USB device number 2 using uhci_hcd
>[   38.722449] btusb 5-1:1.0: no reset_resume for driver btusb?
>[   38.722453] btusb 5-1:1.1: no reset_resume for driver btusb?
>[   38.807943] thinkpad_acpi: ACPI backlight control delay disabled
>[   38.809662] evbug: Event. Dev: input6, Type: 0, Code: 0, Value: 1
>[   38.809799] evbug: Event. Dev: input7, Type: 0, Code: 0, Value: 1
>[   38.809830] evbug: Event. Dev: input8, Type: 0, Code: 0, Value: 1
>[   38.820085] usb 5-2: reset full-speed USB device number 3 using uhci_hcd
>[   38.969514] PM: resume of devices complete after 1480.889 msecs
>[   38.970319] Restarting tasks ... 
>[   38.972389] [drm:drm_mode_setcrtc], [CRTC:3]
>[   38.972400] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[   38.972419] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   38.972443] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   38.972448] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[   38.972478] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes :
>[   38.972482] [drm:drm_mode_debug_printmodeline], Modeline 18:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa
>[   38.972488] [drm:drm_mode_debug_printmodeline], Modeline 22:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   38.972494] [drm:drm_mode_debug_printmodeline], Modeline 19:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   38.972499] [drm:drm_mode_debug_printmodeline], Modeline 20:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   38.972504] [drm:drm_mode_debug_printmodeline], Modeline 21:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   38.972514] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   38.972994] [drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[   38.973000] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1]
>[   38.979181] done.
>[   38.988057] [drm:intel_crt_detect], CRT not detected via hotplug
>[   38.991786] video LNXVIDEO:00: Restoring backlight state
>[   38.993099] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[   38.993106] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   38.993111] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   38.993114] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[   38.993383] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   38.993386] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[   38.993390] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[   38.993395] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1] disconnected
>[   38.993412] [drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[   38.993416] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1]
>[   39.008078] [drm:intel_crt_detect], CRT not detected via hotplug
>[   39.012039] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[   39.012051] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   39.012055] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   39.012059] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[   39.012331] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   39.012334] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[   39.012337] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[   39.012343] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1] disconnected
>[   39.012541] [drm:drm_mode_setcrtc], [CRTC:3]
>[   39.012546] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[   39.012553] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   39.012567] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   39.012571] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[   39.012600] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes :
>[   39.012604] [drm:drm_mode_debug_printmodeline], Modeline 18:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa
>[   39.012610] [drm:drm_mode_debug_printmodeline], Modeline 22:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   39.012615] [drm:drm_mode_debug_printmodeline], Modeline 19:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   39.012620] [drm:drm_mode_debug_printmodeline], Modeline 20:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   39.012625] [drm:drm_mode_debug_printmodeline], Modeline 21:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   39.012634] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[   39.013111] [drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[   39.013116] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1]
>[   39.031145] [drm:intel_crt_detect], CRT not detected via hotplug
>[   39.033172] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[   39.033178] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   39.033183] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   39.033186] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[   39.033459] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   39.033463] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[   39.033466] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[   39.033471] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1] disconnected
>[   39.033487] [drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[   39.033492] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1]
>[   39.044026] [drm:intel_crt_detect], CRT not detected via hotplug
>[   39.050068] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[   39.050074] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   39.050078] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   39.050082] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[   39.050352] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   39.050355] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[   39.050359] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[   39.050364] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1] disconnected
>[   39.056813] sdhci-pci 0000:15:00.2: Will use DMA mode even though HW doesn't fully claim to support it.
>[   39.119030] sdhci-pci 0000:15:00.2: Will use DMA mode even though HW doesn't fully claim to support it.
>[   39.182554] sdhci-pci 0000:15:00.2: Will use DMA mode even though HW doesn't fully claim to support it.
>[   39.242371] sdhci-pci 0000:15:00.2: Will use DMA mode even though HW doesn't fully claim to support it.
>[   39.299607] uhci_hcd 0000:00:1d.2: power state changed by ACPI to D2
>[   39.312085] ehci-pci 0000:00:1d.7: power state changed by ACPI to D3cold
>[   39.373538] ehci-pci 0000:00:1d.7: power state changed by ACPI to D0
>[   39.476329] ehci-pci 0000:00:1d.7: setting latency timer to 64
>[   39.505082] uhci_hcd 0000:00:1d.1: setting latency timer to 64
>[   39.530497] uhci_hcd 0000:00:1d.2: power state changed by ACPI to D0
>[   39.530715] uhci_hcd 0000:00:1d.2: setting latency timer to 64
>[   41.708228] e1000e 0000:02:00.0: Disabling ASPM L0s L1
>[   41.708357] e1000e 0000:02:00.0: irq 46 for MSI/MSI-X
>[   41.884057] [drm:intel_crt_detect], CRT not detected via hotplug
>[   41.888076] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[   41.888086] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   41.888092] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   41.888098] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[   41.888374] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   41.888379] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[   41.888385] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[   41.908064] [drm:intel_crt_detect], CRT not detected via hotplug
>[   41.912068] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[   41.912078] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   41.912084] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   41.912089] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[   41.912387] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   41.912392] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[   41.912398] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[   41.920166] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 200
>[   41.920173] evbug: Event. Dev: input3, Type: 1, Code: 103, Value: 1
>[   41.920179] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   41.936070] [drm:intel_crt_detect], CRT not detected via hotplug
>[   41.940065] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[   41.940075] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   41.940081] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   41.940086] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[   41.940361] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   41.940366] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[   41.940371] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[   41.943512] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   42.024261] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 200
>[   42.024269] evbug: Event. Dev: input3, Type: 1, Code: 103, Value: 0
>[   42.024274] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   42.268873] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   42.268884] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   42.268890] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   42.268896] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   42.268902] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   42.268908] [drm:i9xx_update_wm], memory self refresh disabled
>[   42.268917] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   42.268923] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   42.268929] [drm:intel_modeset_check_state], [CRTC:3]
>[   42.268935] [drm:intel_modeset_check_state], [CRTC:4]
>[   42.269047] [drm:drm_mode_setcrtc], [CRTC:4]
>[   42.269056] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   42.269065] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   42.269071] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   42.269076] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   42.269083] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   42.269094] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   42.269101] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   42.269107] [drm:intel_modeset_check_state], [CRTC:3]
>[   42.269112] [drm:intel_modeset_check_state], [CRTC:4]
>[   42.270946] [drm:drm_mode_setcrtc], [CRTC:4]
>[   42.270953] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   42.271048] [drm:drm_mode_setcrtc], [CRTC:4]
>[   42.271060] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   42.271066] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   42.271073] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   42.271079] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   42.271085] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   42.271091] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   42.271097] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   42.271102] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   42.271544] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   42.271555] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   42.271563] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   42.271568] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   42.271578] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   42.272473] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   42.272479] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   42.272511] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   42.272520] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   42.272526] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   42.272532] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   42.272537] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   42.272543] [drm:i9xx_update_wm], memory self refresh disabled
>[   42.272549] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   42.272556] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   42.272562] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   42.272567] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   42.272573] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   42.272578] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   42.272584] [drm:i9xx_update_wm], self-refresh entries: 64
>[   42.272589] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   42.272595] [drm:i9xx_update_wm], memory self refresh enabled
>[   42.273050] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   42.624057] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   42.624073] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   42.624081] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   42.624088] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   42.624094] [drm:intel_modeset_check_state], [CRTC:3]
>[   42.624100] [drm:intel_modeset_check_state], [CRTC:4]
>[   42.630061] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   42.679919] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   42.679930] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   42.679937] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   42.679942] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   42.679948] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   42.679955] [drm:i9xx_update_wm], memory self refresh disabled
>[   42.679963] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   42.679969] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   42.679975] [drm:intel_modeset_check_state], [CRTC:3]
>[   42.679981] [drm:intel_modeset_check_state], [CRTC:4]
>[   42.680044] [drm:drm_mode_setcrtc], [CRTC:4]
>[   42.680053] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   42.680062] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   42.680068] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   42.680073] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   42.680079] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   42.680092] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   42.680098] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   42.680104] [drm:intel_modeset_check_state], [CRTC:3]
>[   42.680109] [drm:intel_modeset_check_state], [CRTC:4]
>[   42.681919] [drm:drm_mode_setcrtc], [CRTC:4]
>[   42.681926] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   44.052601] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 203
>[   44.052611] evbug: Event. Dev: input3, Type: 1, Code: 105, Value: 1
>[   44.052616] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   44.052791] [drm:drm_mode_setcrtc], [CRTC:4]
>[   44.052807] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   44.052814] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   44.052823] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   44.052829] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   44.052835] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   44.052841] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   44.052846] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   44.052851] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   44.052862] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   44.052872] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   44.052880] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   44.052885] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   44.052897] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   44.053754] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   44.053759] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   44.053774] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   44.053784] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.053790] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.053796] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   44.053801] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   44.053807] [drm:i9xx_update_wm], memory self refresh disabled
>[   44.053813] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   44.053820] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.053826] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   44.053831] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   44.053836] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.053842] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   44.053847] [drm:i9xx_update_wm], self-refresh entries: 64
>[   44.053852] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   44.053858] [drm:i9xx_update_wm], memory self refresh enabled
>[   44.054314] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   44.084086] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   44.084097] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   44.084104] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   44.084110] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   44.084116] [drm:intel_modeset_check_state], [CRTC:3]
>[   44.084122] [drm:intel_modeset_check_state], [CRTC:4]
>[   44.089290] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   44.139910] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   44.139920] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.139927] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.139932] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   44.139938] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   44.139944] [drm:i9xx_update_wm], memory self refresh disabled
>[   44.139952] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   44.139958] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   44.139964] [drm:intel_modeset_check_state], [CRTC:3]
>[   44.139970] [drm:intel_modeset_check_state], [CRTC:4]
>[   44.140023] [drm:drm_mode_setcrtc], [CRTC:4]
>[   44.140029] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   44.140037] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   44.140042] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   44.140047] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   44.140053] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   44.140064] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   44.140071] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   44.140076] [drm:intel_modeset_check_state], [CRTC:3]
>[   44.140082] [drm:intel_modeset_check_state], [CRTC:4]
>[   44.141735] [drm:drm_mode_setcrtc], [CRTC:4]
>[   44.141742] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   44.268423] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 203
>[   44.268431] evbug: Event. Dev: input3, Type: 1, Code: 105, Value: 0
>[   44.268436] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   44.268570] [drm:drm_mode_setcrtc], [CRTC:4]
>[   44.268583] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   44.268589] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   44.268597] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   44.268603] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   44.268608] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   44.268614] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   44.268619] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   44.268624] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   44.268634] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   44.268643] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   44.268649] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   44.268654] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   44.268664] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   44.269519] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   44.269524] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   44.269538] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   44.269547] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.269553] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.269558] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   44.269564] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   44.269569] [drm:i9xx_update_wm], memory self refresh disabled
>[   44.269575] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   44.269582] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.269588] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   44.269593] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   44.269598] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.269603] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   44.269609] [drm:i9xx_update_wm], self-refresh entries: 64
>[   44.269614] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   44.269620] [drm:i9xx_update_wm], memory self refresh enabled
>[   44.270075] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   44.428054] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   44.428066] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   44.428074] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   44.428080] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   44.428086] [drm:intel_modeset_check_state], [CRTC:3]
>[   44.428092] [drm:intel_modeset_check_state], [CRTC:4]
>[   44.432216] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   44.475899] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   44.475909] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.475915] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.475921] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   44.475927] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   44.475933] [drm:i9xx_update_wm], memory self refresh disabled
>[   44.475940] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   44.475946] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   44.475952] [drm:intel_modeset_check_state], [CRTC:3]
>[   44.475958] [drm:intel_modeset_check_state], [CRTC:4]
>[   44.475996] [drm:drm_mode_setcrtc], [CRTC:4]
>[   44.476017] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   44.476024] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   44.476029] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   44.476034] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   44.476040] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   44.476050] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   44.476057] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   44.476062] [drm:intel_modeset_check_state], [CRTC:3]
>[   44.476068] [drm:intel_modeset_check_state], [CRTC:4]
>[   44.477672] [drm:drm_mode_setcrtc], [CRTC:4]
>[   44.477679] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   44.578003] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 203
>[   44.578009] evbug: Event. Dev: input3, Type: 1, Code: 105, Value: 1
>[   44.578014] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   44.578140] [drm:drm_mode_setcrtc], [CRTC:4]
>[   44.578152] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   44.578158] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   44.578166] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   44.578171] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   44.578177] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   44.578183] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   44.578188] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   44.578192] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   44.578202] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   44.578210] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   44.578217] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   44.578222] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   44.578231] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   44.579086] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   44.579091] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   44.579104] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   44.579112] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.579119] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.579124] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   44.579130] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   44.579135] [drm:i9xx_update_wm], memory self refresh disabled
>[   44.579141] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   44.579148] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.579154] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   44.579159] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   44.579164] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.579169] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   44.579175] [drm:i9xx_update_wm], self-refresh entries: 64
>[   44.579180] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   44.579186] [drm:i9xx_update_wm], memory self refresh enabled
>[   44.579641] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   44.745369] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 203
>[   44.745377] evbug: Event. Dev: input3, Type: 1, Code: 105, Value: 0
>[   44.745382] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   44.832065] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   44.832078] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   44.832085] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   44.832092] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   44.832098] [drm:intel_modeset_check_state], [CRTC:3]
>[   44.832104] [drm:intel_modeset_check_state], [CRTC:4]
>[   44.838018] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   44.868884] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   44.868894] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.868901] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.868906] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   44.868912] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   44.868918] [drm:i9xx_update_wm], memory self refresh disabled
>[   44.868926] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   44.868932] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   44.868938] [drm:intel_modeset_check_state], [CRTC:3]
>[   44.868944] [drm:intel_modeset_check_state], [CRTC:4]
>[   44.868991] [drm:drm_mode_setcrtc], [CRTC:4]
>[   44.868998] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   44.869005] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   44.869010] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   44.869016] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   44.869022] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   44.869033] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   44.869039] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   44.869045] [drm:intel_modeset_check_state], [CRTC:3]
>[   44.869050] [drm:intel_modeset_check_state], [CRTC:4]
>[   44.870747] [drm:drm_mode_setcrtc], [CRTC:4]
>[   44.870751] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   44.870915] [drm:drm_mode_setcrtc], [CRTC:4]
>[   44.870923] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   44.870926] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   44.870931] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   44.870934] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   44.870938] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   44.870941] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   44.870944] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   44.870947] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   44.870954] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   44.870959] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   44.870964] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   44.870967] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   44.870974] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   44.871607] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   44.871610] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   44.871620] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   44.871625] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.871629] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.871632] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   44.871636] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   44.871639] [drm:i9xx_update_wm], memory self refresh disabled
>[   44.871643] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   44.871647] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.871651] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   44.871654] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   44.871657] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.871660] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   44.871663] [drm:i9xx_update_wm], self-refresh entries: 64
>[   44.871666] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   44.871670] [drm:i9xx_update_wm], memory self refresh enabled
>[   44.872123] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   45.232086] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   45.232108] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   45.232117] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   45.232124] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   45.232130] [drm:intel_modeset_check_state], [CRTC:3]
>[   45.232136] [drm:intel_modeset_check_state], [CRTC:4]
>[   45.237714] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   45.279927] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   45.279943] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   45.279949] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   45.279955] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   45.279961] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   45.279967] [drm:i9xx_update_wm], memory self refresh disabled
>[   45.279977] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   45.279984] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   45.279989] [drm:intel_modeset_check_state], [CRTC:3]
>[   45.279996] [drm:intel_modeset_check_state], [CRTC:4]
>[   45.280121] [drm:drm_mode_setcrtc], [CRTC:4]
>[   45.280129] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   45.280138] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   45.280143] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   45.280149] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   45.280155] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   45.280168] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   45.280174] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   45.280180] [drm:intel_modeset_check_state], [CRTC:3]
>[   45.280185] [drm:intel_modeset_check_state], [CRTC:4]
>[   45.414307] IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready
>[   45.519224] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 203
>[   45.519235] evbug: Event. Dev: input3, Type: 1, Code: 105, Value: 1
>[   45.519240] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   45.519445] [drm:drm_mode_setcrtc], [CRTC:4]
>[   45.519460] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   45.519466] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   45.519475] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   45.519482] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   45.519487] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   45.519493] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   45.519498] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   45.519504] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   45.519514] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   45.519524] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   45.519532] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   45.519537] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   45.519549] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   45.520442] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   45.520448] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   45.520464] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   45.520474] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   45.520480] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   45.520485] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   45.520491] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   45.520497] [drm:i9xx_update_wm], memory self refresh disabled
>[   45.520503] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   45.520510] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   45.520517] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   45.520522] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   45.520527] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   45.520533] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   45.520538] [drm:i9xx_update_wm], self-refresh entries: 64
>[   45.520543] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   45.520549] [drm:i9xx_update_wm], memory self refresh enabled
>[   45.521005] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   45.632078] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   45.632099] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   45.632107] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   45.632115] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   45.632121] [drm:intel_modeset_check_state], [CRTC:3]
>[   45.632127] [drm:intel_modeset_check_state], [CRTC:4]
>[   45.637638] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   45.638908] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 203
>[   45.638915] evbug: Event. Dev: input3, Type: 1, Code: 105, Value: 0
>[   45.638920] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   45.668869] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   45.668879] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   45.668886] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   45.668891] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   45.668897] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   45.668903] [drm:i9xx_update_wm], memory self refresh disabled
>[   45.668911] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   45.668918] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   45.668923] [drm:intel_modeset_check_state], [CRTC:3]
>[   45.668929] [drm:intel_modeset_check_state], [CRTC:4]
>[   45.669016] [drm:drm_mode_setcrtc], [CRTC:4]
>[   45.669023] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   45.669031] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   45.669037] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   45.669042] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   45.669048] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   45.669059] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   45.669065] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   45.669071] [drm:intel_modeset_check_state], [CRTC:3]
>[   45.669077] [drm:intel_modeset_check_state], [CRTC:4]
>[   45.670660] [drm:drm_mode_setcrtc], [CRTC:4]
>[   45.670667] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   45.670754] [drm:drm_mode_setcrtc], [CRTC:4]
>[   45.670765] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   45.670770] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   45.670778] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   45.670783] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   45.670789] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   45.670795] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   45.670800] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   45.670805] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   45.670815] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   45.670824] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   45.670831] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   45.670836] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   45.670846] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   45.671703] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   45.671708] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   45.671723] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   45.671732] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   45.671738] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   45.671743] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   45.671748] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   45.671754] [drm:i9xx_update_wm], memory self refresh disabled
>[   45.671760] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   45.671767] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   45.671773] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   45.671778] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   45.671783] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   45.671789] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   45.671794] [drm:i9xx_update_wm], self-refresh entries: 64
>[   45.671800] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   45.671805] [drm:i9xx_update_wm], memory self refresh enabled
>[   45.672262] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   45.758407] e1000e 0000:02:00.0: irq 46 for MSI/MSI-X
>[   45.860197] e1000e 0000:02:00.0: irq 46 for MSI/MSI-X
>[   45.860737] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
>[   46.032521] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   46.032543] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   46.032551] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   46.032557] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   46.032563] [drm:intel_modeset_check_state], [CRTC:3]
>[   46.032570] [drm:intel_modeset_check_state], [CRTC:4]
>[   46.037404] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   46.075272] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 205
>[   46.075282] evbug: Event. Dev: input3, Type: 1, Code: 106, Value: 1
>[   46.075287] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   46.079897] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   46.079908] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   46.079914] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   46.079920] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   46.079925] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   46.079931] [drm:i9xx_update_wm], memory self refresh disabled
>[   46.079941] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   46.079947] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   46.079953] [drm:intel_modeset_check_state], [CRTC:3]
>[   46.079959] [drm:intel_modeset_check_state], [CRTC:4]
>[   46.080084] [drm:drm_mode_setcrtc], [CRTC:4]
>[   46.080091] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   46.080100] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   46.080105] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   46.080111] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   46.080117] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   46.080129] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   46.080135] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   46.080141] [drm:intel_modeset_check_state], [CRTC:3]
>[   46.080146] [drm:intel_modeset_check_state], [CRTC:4]
>[   46.082429] [drm:drm_mode_setcrtc], [CRTC:4]
>[   46.082437] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   46.082534] [drm:drm_mode_setcrtc], [CRTC:4]
>[   46.082545] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   46.082551] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   46.082558] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   46.082564] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   46.082570] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   46.082575] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   46.082580] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   46.082585] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   46.082596] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   46.082605] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   46.082612] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   46.082617] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   46.082628] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   46.083485] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   46.083490] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   46.083505] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   46.083514] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   46.083520] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   46.083526] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   46.083531] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   46.083537] [drm:i9xx_update_wm], memory self refresh disabled
>[   46.083543] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   46.083550] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   46.083556] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   46.083561] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   46.083566] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   46.083571] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   46.083577] [drm:i9xx_update_wm], self-refresh entries: 64
>[   46.083582] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   46.083588] [drm:i9xx_update_wm], memory self refresh enabled
>[   46.084042] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   46.118265] IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready
>[   46.282698] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 205
>[   46.282708] evbug: Event. Dev: input3, Type: 1, Code: 106, Value: 0
>[   46.282713] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   46.338311] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 203
>[   46.338317] evbug: Event. Dev: input3, Type: 1, Code: 105, Value: 1
>[   46.338322] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   46.436069] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   46.436085] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   46.436093] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   46.436100] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   46.436106] [drm:intel_modeset_check_state], [CRTC:3]
>[   46.436112] [drm:intel_modeset_check_state], [CRTC:4]
>[   46.441327] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   46.472865] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   46.472876] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   46.472882] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   46.472888] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   46.472894] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   46.472900] [drm:i9xx_update_wm], memory self refresh disabled
>[   46.472908] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   46.472914] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   46.472920] [drm:intel_modeset_check_state], [CRTC:3]
>[   46.472926] [drm:intel_modeset_check_state], [CRTC:4]
>[   46.472985] [drm:drm_mode_setcrtc], [CRTC:4]
>[   46.472994] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   46.473002] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   46.473008] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   46.473013] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   46.473020] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   46.473032] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   46.473038] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   46.473044] [drm:intel_modeset_check_state], [CRTC:3]
>[   46.473049] [drm:intel_modeset_check_state], [CRTC:4]
>[   46.474954] [drm:drm_mode_setcrtc], [CRTC:4]
>[   46.474962] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   46.475195] [drm:drm_mode_setcrtc], [CRTC:4]
>[   46.475207] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   46.475213] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   46.475220] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   46.475226] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   46.475232] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   46.475237] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   46.475242] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   46.475247] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   46.475258] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   46.475267] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   46.475274] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   46.475279] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   46.475289] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   46.476145] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   46.476151] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   46.476183] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   46.476192] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   46.476198] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   46.476204] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   46.476209] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   46.476215] [drm:i9xx_update_wm], memory self refresh disabled
>[   46.476221] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   46.476228] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   46.476234] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   46.476239] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   46.476245] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   46.476250] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   46.476256] [drm:i9xx_update_wm], self-refresh entries: 64
>[   46.476261] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   46.476267] [drm:i9xx_update_wm], memory self refresh enabled
>[   46.476722] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   46.545389] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 203
>[   46.545396] evbug: Event. Dev: input3, Type: 1, Code: 105, Value: 0
>[   46.545401] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   46.783495] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 200
>[   46.783501] evbug: Event. Dev: input3, Type: 1, Code: 103, Value: 1
>[   46.783506] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   46.823071] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 200
>[   46.823077] evbug: Event. Dev: input3, Type: 1, Code: 103, Value: 0
>[   46.823081] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   46.836063] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   46.836075] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   46.836083] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   46.836090] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   46.836096] [drm:intel_modeset_check_state], [CRTC:3]
>[   46.836102] [drm:intel_modeset_check_state], [CRTC:4]
>[   46.840700] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   46.883903] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   46.883912] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   46.883919] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   46.883924] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   46.883930] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   46.883936] [drm:i9xx_update_wm], memory self refresh disabled
>[   46.883943] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   46.883950] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   46.883955] [drm:intel_modeset_check_state], [CRTC:3]
>[   46.883961] [drm:intel_modeset_check_state], [CRTC:4]
>[   46.883996] [drm:drm_mode_setcrtc], [CRTC:4]
>[   46.884014] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   46.884022] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   46.884027] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   46.884032] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   46.884038] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   46.884048] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   46.884054] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   46.884060] [drm:intel_modeset_check_state], [CRTC:3]
>[   46.884066] [drm:intel_modeset_check_state], [CRTC:4]
>[   46.884135] [drm:drm_mode_setcrtc], [CRTC:4]
>[   46.884145] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   46.884150] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   46.884157] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   46.884163] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   46.884168] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   46.884174] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   46.884179] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   46.884184] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   46.884193] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   46.884201] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   46.884207] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   46.884212] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   46.884221] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   46.885075] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   46.885080] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   46.885093] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   46.885101] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   46.885107] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   46.885113] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   46.885118] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   46.885124] [drm:i9xx_update_wm], memory self refresh disabled
>[   46.885130] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   46.885136] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   46.885142] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   46.885147] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   46.885152] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   46.885158] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   46.885163] [drm:i9xx_update_wm], self-refresh entries: 64
>[   46.885168] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   46.885174] [drm:i9xx_update_wm], memory self refresh enabled
>[   46.885629] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   47.013158] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 200
>[   47.013167] evbug: Event. Dev: input3, Type: 1, Code: 103, Value: 1
>[   47.013172] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   47.108464] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 200
>[   47.108470] evbug: Event. Dev: input3, Type: 1, Code: 103, Value: 0
>[   47.108475] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   47.236053] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   47.236069] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   47.236078] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   47.236084] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   47.236090] [drm:intel_modeset_check_state], [CRTC:3]
>[   47.236097] [drm:intel_modeset_check_state], [CRTC:4]
>[   47.241524] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   47.272851] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   47.272862] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   47.272868] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   47.272874] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   47.272880] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   47.272886] [drm:i9xx_update_wm], memory self refresh disabled
>[   47.272894] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   47.272901] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   47.272906] [drm:intel_modeset_check_state], [CRTC:3]
>[   47.272913] [drm:intel_modeset_check_state], [CRTC:4]
>[   47.272973] [drm:drm_mode_setcrtc], [CRTC:4]
>[   47.272983] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   47.272992] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   47.272997] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   47.273003] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   47.273009] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   47.273021] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   47.273027] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   47.273033] [drm:intel_modeset_check_state], [CRTC:3]
>[   47.273039] [drm:intel_modeset_check_state], [CRTC:4]
>[   47.275074] [drm:drm_mode_setcrtc], [CRTC:4]
>[   47.275082] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   47.275332] [drm:drm_mode_setcrtc], [CRTC:4]
>[   47.275345] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   47.275351] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   47.275359] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   47.275364] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   47.275370] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   47.275376] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   47.275380] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   47.275386] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   47.275396] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   47.275405] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   47.275412] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   47.275417] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   47.275428] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   47.276284] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   47.276290] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   47.276321] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   47.276331] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   47.276337] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   47.276343] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   47.276348] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   47.276354] [drm:i9xx_update_wm], memory self refresh disabled
>[   47.276360] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   47.276367] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   47.276373] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   47.276378] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   47.276383] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   47.276389] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   47.276394] [drm:i9xx_update_wm], self-refresh entries: 64
>[   47.276399] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   47.276405] [drm:i9xx_update_wm], memory self refresh enabled
>[   47.276861] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   47.636065] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   47.636077] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   47.636084] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   47.636091] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   47.636096] [drm:intel_modeset_check_state], [CRTC:3]
>[   47.636102] [drm:intel_modeset_check_state], [CRTC:4]
>[   47.640926] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   47.683890] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   47.683899] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   47.683906] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   47.683911] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   47.683917] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   47.683923] [drm:i9xx_update_wm], memory self refresh disabled
>[   47.683930] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   47.683936] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   47.683942] [drm:intel_modeset_check_state], [CRTC:3]
>[   47.683948] [drm:intel_modeset_check_state], [CRTC:4]
>[   47.683986] [drm:drm_mode_setcrtc], [CRTC:4]
>[   47.683992] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   47.683999] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   47.684021] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   47.684026] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   47.684032] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   47.684042] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   47.684049] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   47.684054] [drm:intel_modeset_check_state], [CRTC:3]
>[   47.684060] [drm:intel_modeset_check_state], [CRTC:4]
>[   47.684295] [drm:drm_mode_setcrtc], [CRTC:4]
>[   47.684306] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   47.684312] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   47.684319] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   47.684324] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   47.684330] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   47.684336] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   47.684341] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   47.684346] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   47.684356] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   47.684363] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   47.684370] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   47.684375] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   47.684383] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   47.685237] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   47.685242] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   47.685256] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   47.685264] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   47.685270] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   47.685275] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   47.685281] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   47.685287] [drm:i9xx_update_wm], memory self refresh disabled
>[   47.685292] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   47.685299] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   47.685305] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   47.685310] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   47.685315] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   47.685320] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   47.685326] [drm:i9xx_update_wm], self-refresh entries: 64
>[   47.685331] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   47.685337] [drm:i9xx_update_wm], memory self refresh enabled
>[   47.685792] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   47.706107] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 56
>[   47.706114] evbug: Event. Dev: input3, Type: 1, Code: 56, Value: 1
>[   47.706119] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   47.722119] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 29
>[   47.722125] evbug: Event. Dev: input3, Type: 1, Code: 29, Value: 1
>[   47.722130] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   47.973235] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 29
>[   47.973242] evbug: Event. Dev: input3, Type: 1, Code: 29, Value: 2
>[   47.973246] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   48.007711] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 29
>[   48.007718] evbug: Event. Dev: input3, Type: 1, Code: 29, Value: 2
>[   48.007722] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   48.036068] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   48.036079] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   48.036086] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   48.036093] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   48.036098] [drm:intel_modeset_check_state], [CRTC:3]
>[   48.036104] [drm:intel_modeset_check_state], [CRTC:4]
>[   48.039867] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   48.041651] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 29
>[   48.041658] evbug: Event. Dev: input3, Type: 1, Code: 29, Value: 2
>[   48.041663] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   48.071897] [drm:i9xx_pfit_disable], disabling pfit, current: 0x00000008
>[   48.071906] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   48.071913] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   48.071918] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   48.071924] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   48.071930] [drm:i9xx_update_wm], memory self refresh disabled
>[   48.071937] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   48.071943] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   48.071948] [drm:intel_modeset_check_state], [CRTC:3]
>[   48.071954] [drm:intel_modeset_check_state], [CRTC:4]
>[   48.072025] [drm:drm_mode_setcrtc], [CRTC:4]
>[   48.072032] [drm:intel_crtc_set_config], [CRTC:4] [NOFB]
>[   48.072039] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [NOCRTC]
>[   48.072044] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   48.072049] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   48.072055] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[   48.072065] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   48.072071] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   48.072076] [drm:intel_modeset_check_state], [CRTC:3]
>[   48.072082] [drm:intel_modeset_check_state], [CRTC:4]
>[   48.072151] [drm:drm_mode_setcrtc], [CRTC:4]
>[   48.072161] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
>[   48.072166] [drm:intel_crtc_set_config], [CRTC:4] [FB:10] #connectors=1 (x y) (0 0)
>[   48.072173] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   48.072179] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   48.072185] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   48.072190] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   48.072195] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   48.072200] [drm:drm_mode_debug_printmodeline], Modeline 11:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   48.072210] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   48.072217] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18)
>[   48.072224] [drm:intel_modeset_pipe_config], [CRTC:4]
>[   48.072229] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   48.072237] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz
>[   48.073091] [drm:i9xx_crtc_mode_set], Mode for pipe B:
>[   48.073096] [drm:drm_mode_debug_printmodeline], Modeline 0:"pV\xffffffb9F" 0 54160 1024 1048 1184 1344 768 771 777 806 0x0 0xa
>[   48.073109] [drm:i9xx_update_plane], Writing base 00400000 00000000 0 0 4096
>[   48.073117] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   48.073123] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   48.073129] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29
>[   48.073134] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1
>[   48.073140] [drm:i9xx_update_wm], memory self refresh disabled
>[   48.073146] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:pV\xffffffb9F]
>[   48.073152] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   48.073158] [drm:intel_calculate_wm], FIFO entries required for mode: 17
>[   48.073163] [drm:intel_calculate_wm], FIFO watermark level: 9
>[   48.073168] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   48.073173] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29
>[   48.073179] [drm:i9xx_update_wm], self-refresh entries: 64
>[   48.073184] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63
>[   48.073190] [drm:i9xx_update_wm], memory self refresh enabled
>[   48.073645] [drm:i9xx_pfit_enable], applying panel-fitter: 8, 0
>[   48.075001] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 29
>[   48.075008] evbug: Event. Dev: input3, Type: 1, Code: 29, Value: 2
>[   48.075012] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   48.108330] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 29
>[   48.108337] evbug: Event. Dev: input3, Type: 1, Code: 29, Value: 2
>[   48.108341] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   48.143160] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 29
>[   48.143166] evbug: Event. Dev: input3, Type: 1, Code: 29, Value: 2
>[   48.143171] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   48.177075] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 29
>[   48.177081] evbug: Event. Dev: input3, Type: 1, Code: 29, Value: 2
>[   48.177084] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   48.211580] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 29
>[   48.211591] evbug: Event. Dev: input3, Type: 1, Code: 29, Value: 2
>[   48.211596] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   48.246260] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 29
>[   48.246269] evbug: Event. Dev: input3, Type: 1, Code: 29, Value: 2
>[   48.246274] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   48.260723] wlan0: authenticate with 00:14:7f:24:8f:d8
>[   48.260855] wlan0: send auth to 00:14:7f:24:8f:d8 (try 1/3)
>[   48.265160] wlan0: authenticated
>[   48.268042] wlan0: associate with 00:14:7f:24:8f:d8 (try 1/3)
>[   48.273341] wlan0: RX AssocResp from 00:14:7f:24:8f:d8 (capab=0x431 status=0 aid=3)
>[   48.275225] wlan0: associated
>[   48.275255] IPv6: ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready
>[   48.280777] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 29
>[   48.280783] evbug: Event. Dev: input3, Type: 1, Code: 29, Value: 2
>[   48.280788] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   48.297231] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 59
>[   48.297237] evbug: Event. Dev: input3, Type: 1, Code: 59, Value: 1
>[   48.297242] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   48.440071] [drm:intel_panel_actually_set_backlight], set backlight PWM = 17359
>[   48.440089] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1]
>[   48.440097] [drm:intel_modeset_check_state], [ENCODER:6:LVDS-6]
>[   48.440104] [drm:intel_modeset_check_state], [ENCODER:17:DAC-17]
>[   48.440110] [drm:intel_modeset_check_state], [CRTC:3]
>[   48.440117] [drm:intel_modeset_check_state], [CRTC:4]
>[   48.464707] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 59
>[   48.464717] evbug: Event. Dev: input3, Type: 1, Code: 59, Value: 0
>[   48.464722] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   48.504448] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[   48.504457] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   48.504463] [drm:intel_crtc_set_config], [CRTC:4] [FB:9] #connectors=1 (x y) (0 0)
>[   48.504469] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   48.504481] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
>[   48.520057] [drm:drm_fb_helper_hotplug_event], 
>[   48.520062] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[   48.520099] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes :
>[   48.520108] [drm:drm_mode_debug_printmodeline], Modeline 18:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa
>[   48.520115] [drm:drm_mode_debug_printmodeline], Modeline 22:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   48.520122] [drm:drm_mode_debug_printmodeline], Modeline 19:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   48.520128] [drm:drm_mode_debug_printmodeline], Modeline 20:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   48.520135] [drm:drm_mode_debug_printmodeline], Modeline 21:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   48.520140] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1]
>[   48.536065] [drm:intel_crt_detect], CRT not detected via hotplug
>[   48.540067] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[   48.540071] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   48.540075] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[   48.540079] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[   48.540352] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[   48.540355] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[   48.540359] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[   48.540363] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:VGA-1] disconnected
>[   48.540367] [drm:drm_setup_crtcs], 
>[   48.540371] [drm:drm_enable_connectors], connector 5 enabled? yes
>[   48.540374] [drm:drm_enable_connectors], connector 16 enabled? no
>[   48.540379] [drm:drm_target_preferred], looking for cmdline mode on connector 5
>[   48.540382] [drm:drm_target_preferred], looking for preferred mode on connector 5
>[   48.540385] [drm:drm_target_preferred], found mode 1024x768
>[   48.540389] [drm:drm_setup_crtcs], picking CRTCs for 4096x4096 config
>[   48.540393] [drm:drm_setup_crtcs], desired mode 1024x768 set on crtc 4
>[   48.540401] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[   48.540406] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   48.540411] [drm:intel_crtc_set_config], [CRTC:4] [FB:9] #connectors=1 (x y) (0 0)
>[   48.540416] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   48.540422] [drm:intel_crtc_set_config], [CRTC:4] [FB:9] #connectors=1 (x y) (0 0)
>[   48.540426] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   48.540446] [drm:intel_crtc_set_config], [CRTC:4] [FB:9] #connectors=1 (x y) (0 0)
>[   48.540451] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4]
>[   49.101488] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 29
>[   49.101496] evbug: Event. Dev: input3, Type: 1, Code: 29, Value: 0
>[   49.101501] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   49.155647] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 56
>[   49.155653] evbug: Event. Dev: input3, Type: 1, Code: 56, Value: 0
>[   49.155657] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   49.820073] [drm:intel_decrease_pllclock], downclocking LVDS
>[   50.549546] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 28
>[   50.549554] evbug: Event. Dev: input3, Type: 1, Code: 28, Value: 1
>[   50.549559] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   50.628704] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 28
>[   50.628710] evbug: Event. Dev: input3, Type: 1, Code: 28, Value: 0
>[   50.628715] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   50.984201] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 19
>[   50.984210] evbug: Event. Dev: input3, Type: 1, Code: 19, Value: 1
>[   50.984215] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   51.111836] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 19
>[   51.111846] evbug: Event. Dev: input3, Type: 1, Code: 19, Value: 0
>[   51.111851] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   51.135549] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 24
>[   51.135554] evbug: Event. Dev: input3, Type: 1, Code: 24, Value: 1
>[   51.135559] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   51.182878] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 24
>[   51.182883] evbug: Event. Dev: input3, Type: 1, Code: 24, Value: 0
>[   51.182888] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   51.277119] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 24
>[   51.277125] evbug: Event. Dev: input3, Type: 1, Code: 24, Value: 1
>[   51.277130] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   51.322529] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 20
>[   51.322539] evbug: Event. Dev: input3, Type: 1, Code: 20, Value: 1
>[   51.322544] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   51.348097] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 24
>[   51.348105] evbug: Event. Dev: input3, Type: 1, Code: 24, Value: 0
>[   51.348110] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   51.401423] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 20
>[   51.401434] evbug: Event. Dev: input3, Type: 1, Code: 20, Value: 0
>[   51.401439] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   51.514141] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 28
>[   51.514151] evbug: Event. Dev: input3, Type: 1, Code: 28, Value: 1
>[   51.514156] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   51.609715] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 28
>[   51.609724] evbug: Event. Dev: input3, Type: 1, Code: 28, Value: 0
>[   51.609729] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   51.933650] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 50
>[   51.933656] evbug: Event. Dev: input3, Type: 1, Code: 50, Value: 1
>[   51.933661] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   52.013315] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 50
>[   52.013325] evbug: Event. Dev: input3, Type: 1, Code: 50, Value: 0
>[   52.013330] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   52.115475] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 23
>[   52.115485] evbug: Event. Dev: input3, Type: 1, Code: 23, Value: 1
>[   52.115490] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   52.210998] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 23
>[   52.211004] evbug: Event. Dev: input3, Type: 1, Code: 23, Value: 0
>[   52.211009] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   52.255551] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 31
>[   52.255557] evbug: Event. Dev: input3, Type: 1, Code: 31, Value: 1
>[   52.255561] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   52.358811] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 31
>[   52.358817] evbug: Event. Dev: input3, Type: 1, Code: 31, Value: 0
>[   52.358822] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   52.407329] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 37
>[   52.407335] evbug: Event. Dev: input3, Type: 1, Code: 37, Value: 1
>[   52.407340] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   52.444596] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   52.444601] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 1
>[   52.444606] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   52.477753] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 37
>[   52.477758] evbug: Event. Dev: input3, Type: 1, Code: 37, Value: 0
>[   52.477763] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   52.506845] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   52.506851] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 0
>[   52.506856] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   52.657368] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 46
>[   52.657374] evbug: Event. Dev: input3, Type: 1, Code: 46, Value: 1
>[   52.657379] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   52.745181] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 46
>[   52.745187] evbug: Event. Dev: input3, Type: 1, Code: 46, Value: 0
>[   52.745192] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   52.945918] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 28
>[   52.945924] evbug: Event. Dev: input3, Type: 1, Code: 28, Value: 1
>[   52.945928] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   53.033437] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 28
>[   53.033447] evbug: Event. Dev: input3, Type: 1, Code: 28, Value: 0
>[   53.033452] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   53.603878] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 32
>[   53.603887] evbug: Event. Dev: input3, Type: 1, Code: 32, Value: 1
>[   53.603892] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   53.745908] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 50
>[   53.745914] evbug: Event. Dev: input3, Type: 1, Code: 50, Value: 1
>[   53.745919] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   53.747317] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 32
>[   53.747322] evbug: Event. Dev: input3, Type: 1, Code: 32, Value: 0
>[   53.747327] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   53.824868] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   53.824874] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 1
>[   53.824878] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   53.840995] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 50
>[   53.841000] evbug: Event. Dev: input3, Type: 1, Code: 50, Value: 0
>[   53.841005] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   53.919523] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   53.919529] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 0
>[   53.919533] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   53.980796] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 31
>[   53.980802] evbug: Event. Dev: input3, Type: 1, Code: 31, Value: 1
>[   53.980807] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   54.164548] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 34
>[   54.164557] evbug: Event. Dev: input3, Type: 1, Code: 34, Value: 1
>[   54.164562] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   54.187427] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 31
>[   54.187433] evbug: Event. Dev: input3, Type: 1, Code: 31, Value: 0
>[   54.187438] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   54.283209] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 34
>[   54.283214] evbug: Event. Dev: input3, Type: 1, Code: 34, Value: 0
>[   54.283219] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   54.491682] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 57
>[   54.491688] evbug: Event. Dev: input3, Type: 1, Code: 57, Value: 1
>[   54.491693] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   54.603416] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 57
>[   54.603422] evbug: Event. Dev: input3, Type: 1, Code: 57, Value: 0
>[   54.603427] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   54.644369] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 54
>[   54.644375] evbug: Event. Dev: input3, Type: 1, Code: 54, Value: 1
>[   54.644379] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   54.751249] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 52
>[   54.751255] evbug: Event. Dev: input3, Type: 1, Code: 52, Value: 1
>[   54.751260] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   54.835127] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 54
>[   54.835132] evbug: Event. Dev: input3, Type: 1, Code: 54, Value: 0
>[   54.835137] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   54.877787] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 52
>[   54.877792] evbug: Event. Dev: input3, Type: 1, Code: 52, Value: 0
>[   54.877797] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   54.909258] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 57
>[   54.909264] evbug: Event. Dev: input3, Type: 1, Code: 57, Value: 1
>[   54.909268] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   55.012729] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 57
>[   55.012735] evbug: Event. Dev: input3, Type: 1, Code: 57, Value: 0
>[   55.012740] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   55.034393] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 53
>[   55.034398] evbug: Event. Dev: input3, Type: 1, Code: 53, Value: 1
>[   55.034403] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   55.185522] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 53
>[   55.185528] evbug: Event. Dev: input3, Type: 1, Code: 53, Value: 0
>[   55.185533] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   55.334292] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 35
>[   55.334298] evbug: Event. Dev: input3, Type: 1, Code: 35, Value: 1
>[   55.334303] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   55.437370] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 35
>[   55.437376] evbug: Event. Dev: input3, Type: 1, Code: 35, Value: 0
>[   55.437381] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   55.438137] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 15
>[   55.438142] evbug: Event. Dev: input3, Type: 1, Code: 15, Value: 1
>[   55.438147] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   55.554000] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 15
>[   55.554009] evbug: Event. Dev: input3, Type: 1, Code: 15, Value: 0
>[   55.554015] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   55.713272] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 47
>[   55.713277] evbug: Event. Dev: input3, Type: 1, Code: 47, Value: 1
>[   55.713282] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   55.832186] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 47
>[   55.832192] evbug: Event. Dev: input3, Type: 1, Code: 47, Value: 0
>[   55.832196] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   55.832957] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   55.832962] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 1
>[   55.832967] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   55.926530] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   55.926536] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 0
>[   55.926541] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   56.043659] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 15
>[   56.043666] evbug: Event. Dev: input3, Type: 1, Code: 15, Value: 1
>[   56.043671] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   56.106938] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 15
>[   56.106946] evbug: Event. Dev: input3, Type: 1, Code: 15, Value: 0
>[   56.106951] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   56.265935] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 32
>[   56.265941] evbug: Event. Dev: input3, Type: 1, Code: 32, Value: 1
>[   56.265946] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   56.361597] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 32
>[   56.361603] evbug: Event. Dev: input3, Type: 1, Code: 32, Value: 0
>[   56.361608] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   56.376975] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 50
>[   56.376981] evbug: Event. Dev: input3, Type: 1, Code: 50, Value: 1
>[   56.376985] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   56.464530] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 50
>[   56.464536] evbug: Event. Dev: input3, Type: 1, Code: 50, Value: 0
>[   56.464541] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   56.484880] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 15
>[   56.484885] evbug: Event. Dev: input3, Type: 1, Code: 15, Value: 1
>[   56.484890] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   56.564218] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 15
>[   56.564226] evbug: Event. Dev: input3, Type: 1, Code: 15, Value: 0
>[   56.564231] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   57.670094] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   57.670102] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 1
>[   57.670107] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   57.921519] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   57.921525] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 2
>[   57.921530] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   57.956125] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   57.956131] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 2
>[   57.956136] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   57.990165] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   57.990170] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 2
>[   57.990175] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.024211] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.024217] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 2
>[   58.024222] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.057922] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.057927] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 2
>[   58.057932] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.091087] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.091093] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 2
>[   58.091098] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.124740] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.124746] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 2
>[   58.124751] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.158888] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.158894] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 2
>[   58.158899] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.193041] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.193047] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 2
>[   58.193052] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.227531] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.227537] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 2
>[   58.227542] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.252213] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.252218] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 0
>[   58.252223] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.418873] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.418878] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 1
>[   58.418883] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.473844] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.473851] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 0
>[   58.473855] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.575708] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.575713] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 1
>[   58.575718] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.639774] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.639780] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 0
>[   58.639785] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.725608] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.725614] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 1
>[   58.725619] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.780866] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.780871] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 0
>[   58.780876] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.891286] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.891292] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 1
>[   58.891297] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   58.979054] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   58.979061] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 0
>[   58.979065] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   59.365514] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 46
>[   59.365520] evbug: Event. Dev: input3, Type: 1, Code: 46, Value: 1
>[   59.365525] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   59.485210] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 46
>[   59.485217] evbug: Event. Dev: input3, Type: 1, Code: 46, Value: 0
>[   59.485222] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   60.317413] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   60.317420] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 1
>[   60.317425] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   60.428942] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 14
>[   60.428948] evbug: Event. Dev: input3, Type: 1, Code: 14, Value: 0
>[   60.428953] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   61.614828] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 19
>[   61.614835] evbug: Event. Dev: input3, Type: 1, Code: 19, Value: 1
>[   61.614840] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   61.701384] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   61.701391] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 1
>[   61.701396] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   61.733675] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 19
>[   61.733680] evbug: Event. Dev: input3, Type: 1, Code: 19, Value: 0
>[   61.733685] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   61.771777] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   61.771782] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 0
>[   61.771787] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   61.897448] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 31
>[   61.897454] evbug: Event. Dev: input3, Type: 1, Code: 31, Value: 1
>[   61.897459] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   61.984928] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 22
>[   61.984934] evbug: Event. Dev: input3, Type: 1, Code: 22, Value: 1
>[   61.984939] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   61.986363] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 31
>[   61.986369] evbug: Event. Dev: input3, Type: 1, Code: 31, Value: 0
>[   61.986373] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   62.048755] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 22
>[   62.048765] evbug: Event. Dev: input3, Type: 1, Code: 22, Value: 0
>[   62.048770] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   62.238480] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 50
>[   62.238488] evbug: Event. Dev: input3, Type: 1, Code: 50, Value: 1
>[   62.238494] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   62.332562] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   62.332568] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 1
>[   62.332573] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   62.356870] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 50
>[   62.356876] evbug: Event. Dev: input3, Type: 1, Code: 50, Value: 0
>[   62.356881] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   62.426756] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   62.426762] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 0
>[   62.426766] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   63.882088] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 12
>[   63.882095] evbug: Event. Dev: input3, Type: 1, Code: 12, Value: 1
>[   63.882100] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   64.041382] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 12
>[   64.041388] evbug: Event. Dev: input3, Type: 1, Code: 12, Value: 0
>[   64.041393] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   66.218644] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 48
>[   66.218651] evbug: Event. Dev: input3, Type: 1, Code: 48, Value: 1
>[   66.218656] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   66.306072] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 48
>[   66.306078] evbug: Event. Dev: input3, Type: 1, Code: 48, Value: 0
>[   66.306083] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   66.391999] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 19
>[   66.392005] evbug: Event. Dev: input3, Type: 1, Code: 19, Value: 1
>[   66.392009] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   66.456608] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 24
>[   66.456614] evbug: Event. Dev: input3, Type: 1, Code: 24, Value: 1
>[   66.456619] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   66.494865] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 19
>[   66.494871] evbug: Event. Dev: input3, Type: 1, Code: 19, Value: 0
>[   66.494876] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   66.535504] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 24
>[   66.535509] evbug: Event. Dev: input3, Type: 1, Code: 24, Value: 0
>[   66.535514] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   66.636780] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 37
>[   66.636786] evbug: Event. Dev: input3, Type: 1, Code: 37, Value: 1
>[   66.636791] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   66.738564] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 37
>[   66.738569] evbug: Event. Dev: input3, Type: 1, Code: 37, Value: 0
>[   66.738574] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   66.739710] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   66.739715] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 1
>[   66.739720] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   66.848957] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 18
>[   66.848963] evbug: Event. Dev: input3, Type: 1, Code: 18, Value: 0
>[   66.848968] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   66.911858] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 49
>[   66.911864] evbug: Event. Dev: input3, Type: 1, Code: 49, Value: 1
>[   66.911868] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   67.024157] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 49
>[   67.024167] evbug: Event. Dev: input3, Type: 1, Code: 49, Value: 0
>[   67.024172] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0
>[   67.215389] evbug: Event. Dev: input3, Type: 4, Code: 4, Value: 28
>[   67.215397] evbug: Event. Dev: input3, Type: 1, Code: 28, Value: 1
>[   67.215403] evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 0

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Attachments on bug 64329: 78993 | 78994 | 79677 | 79678 | 79679 | 79680 | 79705 | 79706 | 79707

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