Attachment 83060 Details for Bug 67062 – try eLLC default age of 3

[patch] try eLLC default age of 3

0001-drm-i915-hsw-Use-eLLC-age-3-as-default.patch (text/plain), 1.29 KB, created by Ben Widawsky on 2013-07-26 21:28:03 UTC

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Creator: Ben Widawsky

Created: 2013-07-26 21:28:03 UTC

Size: 1.29 KB

patch

obsolete

>From 9358b42b852552f557d9c82f1bd5a5a0e1db1afe Mon Sep 17 00:00:00 2001
>From: Ben Widawsky <ben@bwidawsk.net>
>Date: Fri, 26 Jul 2013 14:13:42 -0700
>Subject: [PATCH 1/2] drm/i915/hsw: Use eLLC age 3 as default
>
>Replaces the old default of age 0.
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67062
>
>Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>index 3b639a9..7971bf8 100644
>--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>@@ -53,7 +53,9 @@
> #define HSW_CACHEABILITY_CONTROL(bits)	((((bits) & 0x7) << 1) | \
> 					 (((bits) & 0x8) << (11 - 3)))
> #define HSW_WB_LLC_AGE0			HSW_CACHEABILITY_CONTROL(0x3)
>+#define HSW_WB_ELLC_LLC_AGE3		HSW_CACHEABILITY_CONTROL(0x8)
> #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
>+#define HSW_ELLC			HSW_WB_ELLC_LLC_AGE3
> 
> static gen6_gtt_pte_t gen6_pte_encode(dma_addr_t addr,
> 				      enum i915_cache_level level)
>@@ -117,7 +119,7 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
> 	pte |= HSW_PTE_ADDR_ENCODE(addr);
> 
> 	if (level != I915_CACHE_NONE)
>-		pte |= HSW_WB_ELLC_LLC_AGE0;
>+		pte |= HSW_ELLC;
> 
> 	return pte;
> }
>-- 
>1.8.3.4
>

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