Attachment 84175 Details for Bug 68224 – shader dump from Serious Sam 3 with RADEON_DUMP_SHADERS=1

shader dump from Serious Sam 3 with RADEON_DUMP_SHADERS=1

ss3-shaderdump.txt (text/plain), 836.35 KB, created by Laurent carlier on 2013-08-17 15:35:11 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Laurent carlier

Created: 2013-08-17 15:35:11 UTC

Size: 836.35 KB

patch

obsolete

>cat: /etc/debian_version: Aucun fichier ou dossier de ce type
>Setting breakpad minidump AppID = 41070
>Steam_SetMinidumpSteamID:  Caching Steam ID:  76561197992653503 [API loaded no]
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
># Machine code for function main: Post SSA, not tracking liveness
>
>BB#0: derived from LLVM BB %main_body
>	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
>	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR6 in %vreg3
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR6
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
>	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR6 in %vreg3
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR6
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
>	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR6_SGPR7 %VGPR0
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%19](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
>	S_WAITCNT 1904
>	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 15
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	S_WAITCNT 1904
>	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
># Machine code for function main: Post SSA, not tracking liveness
>
>BB#0: derived from LLVM BB %main_body
>	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
>	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
>	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	EXP 15, 0, 0, 1, 1, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>f800180f
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
>  %36 = bitcast i32 %35 to float
>  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
>  %38 = bitcast i32 %37 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
>	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL IN[1], GENERIC[20], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {   32.0000,   -16.0000,     1.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MAD TEMP[1].x, TEMP[0].wwww, IMM[0].xxxx, IMM[0].yyyy
>  3: EX2 TEMP[1].x, TEMP[1].xxxx
>  4: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[1].xxxx
>  5: MOV TEMP[1].w, IMM[0].zzzz
>  6: FSGE TEMP[2].x, CONST[0].xxxx, IMM[0].wwww
>  7: UIF TEMP[2].xxxx :0
>  8:   MOV TEMP[1], TEMP[1]
>  9: ELSE :0
> 10:   MOV TEMP[1], TEMP[0]
> 11: ENDIF
> 12: MUL TEMP[0], TEMP[1], IN[0]
> 13: MOV OUT[0], TEMP[0]
> 14: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %24 = load <32 x i8> addrspace(2)* %23, !tbaa !0
>  %25 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %26 = load <16 x i8> addrspace(2)* %25, !tbaa !0
>  %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %24, <16 x i8> %26, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %41, 3.200000e+01
>  %43 = fadd float %42, -1.600000e+01
>  %44 = call float @llvm.AMDIL.exp.(float %43)
>  %45 = fmul float %38, %44
>  %46 = fmul float %39, %44
>  %47 = fmul float %40, %44
>  %48 = fcmp oge float %22, 0.000000e+00
>  %49 = sext i1 %48 to i32
>  %50 = bitcast i32 %49 to float
>  %51 = bitcast float %50 to i32
>  %52 = icmp ne i32 %51, 0
>  %. = select i1 %52, float %45, float %38
>  %.12 = select i1 %52, float %46, float %39
>  %.13 = select i1 %52, float %47, float %40
>  %.14 = select i1 %52, float 1.000000e+00, float %41
>  %53 = fmul float %., %27
>  %54 = fmul float %.12, %28
>  %55 = fmul float %.13, %29
>  %56 = fmul float %.14, %30
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %53, float %54, float %55, float %56)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%28](align=8)(tbaa=!"const")
>	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%25](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MOV_B32_e32 -1.600000e+01, %EXEC<imp-use>
>	%VGPR7<def> = V_MOV_B32_e32 3.200000e+01, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR6<def> = V_MAD_F32 %VGPR5, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_EXP_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR4, %VGPR6, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %SGPR0<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR7<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR7<kill>, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR3, %VGPR6, %EXEC<imp-use>
>	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR3, %VGPR8<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR2, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR6<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR5, 1.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
>	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	EXP 15, 0, 0, 1, 1, %VGPR6<kill>, %VGPR8<kill>, %VGPR7<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c80c0500
>c80d0501
>c8080400
>c8090401
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>7e0c02ff
>c1800000
>7e0e02ff
>42000000
>bf8c0770
>d2820006
>041a0f05
>7e0c4b06
>100e0d04
>c0800100
>bf8c007f
>c2000100
>bf8c007f
>d00c0000
>02010000
>d2000007
>00020f04
>c8200200
>c8210201
>100e1107
>10100d03
>d2000008
>00021103
>c8240100
>c8250101
>10101308
>100c0d02
>d2000006
>00020d02
>c8240000
>c8250001
>100c1306
>d2000002
>0001e505
>c80c0300
>c80d0301
>10000702
>f800180f
>00070806
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], CLIPVERTEX
>DCL OUT[2], GENERIC[19]
>DCL OUT[3], GENERIC[20]
>DCL CONST[0..5]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
>  0: DP4 TEMP[0].x, IN[0], CONST[0]
>  1: DP4 TEMP[1].x, IN[0], CONST[1]
>  2: MOV TEMP[0].y, TEMP[1].xxxx
>  3: DP4 TEMP[1].x, IN[0], CONST[2]
>  4: MOV TEMP[0].z, TEMP[1].xxxx
>  5: DP4 TEMP[1].x, IN[0], CONST[3]
>  6: MOV TEMP[0].w, TEMP[1].xxxx
>  7: FSGE TEMP[1].x, CONST[4].zzzz, IMM[0].xxxx
>  8: UIF TEMP[1].xxxx :0
>  9:   MOV TEMP[1], IN[2].zyxw
> 10: ELSE :0
> 11:   MOV TEMP[1], CONST[5]
> 12: ENDIF
> 13: MOV TEMP[2].w, TEMP[1].wwww
> 14: POW TEMP[3].x, TEMP[1].xxxx, CONST[4].xxxx
> 15: POW TEMP[3].y, TEMP[1].yyyy, CONST[4].xxxx
> 16: POW TEMP[3].z, TEMP[1].zzzz, CONST[4].xxxx
> 17: MUL TEMP[2].xyz, TEMP[3].xyzz, CONST[4].yyyy
> 18: MUL TEMP[0], TEMP[0], CONST[4].wwww
> 19: MOV TEMP[1].xy, IN[1].xyxx
> 20: MOV OUT[3], TEMP[1]
> 21: MOV OUT[2], TEMP[2]
> 22: MOV OUT[0], TEMP[0]
> 23: MOV OUT[1], TEMP[0]
> 24: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
>  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %5)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
>  %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %5)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = extractelement <4 x float> %44, i32 1
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = fmul float %38, %11
>  %55 = fmul float %39, %12
>  %56 = fadd float %54, %55
>  %57 = fmul float %40, %13
>  %58 = fadd float %56, %57
>  %59 = fmul float %41, %14
>  %60 = fadd float %58, %59
>  %61 = fmul float %38, %15
>  %62 = fmul float %39, %16
>  %63 = fadd float %61, %62
>  %64 = fmul float %40, %17
>  %65 = fadd float %63, %64
>  %66 = fmul float %41, %18
>  %67 = fadd float %65, %66
>  %68 = fmul float %38, %19
>  %69 = fmul float %39, %20
>  %70 = fadd float %68, %69
>  %71 = fmul float %40, %21
>  %72 = fadd float %70, %71
>  %73 = fmul float %41, %22
>  %74 = fadd float %72, %73
>  %75 = fmul float %38, %23
>  %76 = fmul float %39, %24
>  %77 = fadd float %75, %76
>  %78 = fmul float %40, %25
>  %79 = fadd float %77, %78
>  %80 = fmul float %41, %26
>  %81 = fadd float %79, %80
>  %82 = fcmp oge float %29, 0.000000e+00
>  %83 = sext i1 %82 to i32
>  %84 = bitcast i32 %83 to float
>  %85 = bitcast float %84 to i32
>  %86 = icmp ne i32 %85, 0
>  %. = select i1 %86, float %52, float %31
>  %.16 = select i1 %86, float %51, float %32
>  %.17 = select i1 %86, float %50, float %33
>  %.18 = select i1 %86, float %53, float %34
>  %87 = call float @llvm.pow.f32(float %., float %27)
>  %88 = call float @llvm.pow.f32(float %.16, float %27)
>  %89 = call float @llvm.pow.f32(float %.17, float %27)
>  %90 = fmul float %87, %28
>  %91 = fmul float %88, %28
>  %92 = fmul float %89, %28
>  %93 = fmul float %60, %30
>  %94 = fmul float %67, %30
>  %95 = fmul float %74, %30
>  %96 = fmul float %81, %30
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %90, float %91, float %92, float %.18)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %45, float %46, float %.17, float %.18)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %93, float %94, float %95, float %96)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%54](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %SGPR4<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR8<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR5<kill>, %VGPR4, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR8<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR1, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_LOG_F32_e32 %VGPR6, %EXEC<imp-use>
>	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MUL_LEGACY_F32_e32 %SGPR8, %VGPR7<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_EXP_F32_e32 %VGPR7<kill>, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MUL_F32_e32 %SGPR9, %VGPR7<kill>, %EXEC<imp-use>
>	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR10<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR2, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_LOG_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_LEGACY_F32_e32 %SGPR8, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_EXP_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %SGPR9, %VGPR8<kill>, %EXEC<imp-use>
>	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR10<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, %VGPR3, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
>	%VGPR1<def> = V_LOG_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_MUL_LEGACY_F32_e32 %SGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_EXP_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_MUL_F32_e32 %SGPR9<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR8<kill>, %VGPR7<kill>, %VGPR5, %EXEC<imp-use>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%47](align=8)(tbaa=!"const")
>	S_WAITCNT 15
>	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
>	S_WAITCNT 1904
>	EXP 15, 33, 0, 0, 0, %VGPR1, %VGPR2, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%38](align=8)(tbaa=!"const")
>	S_WAITCNT 15
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
>	S_WAITCNT 112
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e64 %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR0, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MUL_F32_e32 %SGPR4, %VGPR4<kill>, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR0, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e32 %SGPR4, %VGPR5<kill>, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e64 %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR0, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %SGPR4, %VGPR6<kill>, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e64 %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR0, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	%VGPR0<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020112
>bf8c007f
>d00c0004
>02010004
>c2040117
>bf8c007f
>7e0a0208
>d2000005
>00120905
>c2040116
>bf8c007f
>7e0c0208
>d2000006
>00120306
>7e0e4f06
>c2040110
>bf8c007f
>0e0e0e08
>7e0e4b07
>c2048111
>bf8c007f
>100e0e09
>c2050115
>bf8c007f
>7e10020a
>d2000008
>00120508
>7e104f08
>0e101008
>7e104b08
>10101009
>c2050114
>bf8c007f
>7e12020a
>d2000001
>00120709
>7e024f01
>0e020208
>7e024b01
>10020209
>f800020f
>05070801
>c0840704
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>05060201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c202010d
>bf8c0070
>7e080204
>d2100004
>02020901
>c202010c
>bf8c007f
>7e0a0204
>d2820004
>04120b00
>c202010e
>bf8c007f
>7e0a0204
>d2820004
>04120b02
>c202010f
>bf8c007f
>7e0a0204
>d2820004
>04120b03
>c2020113
>bf8c007f
>10080804
>c2028109
>bf8c007f
>7e0a0205
>d2100005
>02020b01
>c2028108
>bf8c007f
>7e0c0205
>d2820005
>04160d00
>c202810a
>bf8c007f
>7e0c0205
>d2820005
>04160d02
>c202810b
>bf8c007f
>7e0c0205
>d2820005
>04160d03
>100a0a04
>c2028105
>bf8c007f
>7e0c0205
>d2100006
>02020d01
>c2028104
>bf8c007f
>7e0e0205
>d2820006
>041a0f00
>c2028106
>bf8c007f
>7e0e0205
>d2820006
>041a0f02
>c2028107
>bf8c007f
>7e0e0205
>d2820006
>041a0f03
>100c0c04
>c2028101
>bf8c007f
>7e0e0205
>d2100007
>02020f01
>c2028100
>bf8c007f
>7e100205
>d2820007
>041e1100
>c2028102
>bf8c007f
>7e100205
>d2820007
>041e1102
>c2000103
>bf8c007f
>7e100200
>d2820000
>041e1103
>10000004
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL IN[1], GENERIC[20], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {   32.0000,   -16.0000,     1.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MAD TEMP[1].x, TEMP[0].wwww, IMM[0].xxxx, IMM[0].yyyy
>  3: EX2 TEMP[1].x, TEMP[1].xxxx
>  4: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[1].xxxx
>  5: MOV TEMP[1].w, IMM[0].zzzz
>  6: FSGE TEMP[2].x, CONST[0].xxxx, IMM[0].wwww
>  7: UIF TEMP[2].xxxx :0
>  8:   MOV TEMP[1], TEMP[1]
>  9: ELSE :0
> 10:   MOV TEMP[1], TEMP[0]
> 11: ENDIF
> 12: MUL TEMP[0], TEMP[1], IN[0]
> 13: MOV OUT[0], TEMP[0]
> 14: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %24 = load <32 x i8> addrspace(2)* %23, !tbaa !0
>  %25 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %26 = load <16 x i8> addrspace(2)* %25, !tbaa !0
>  %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %24, <16 x i8> %26, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %41, 3.200000e+01
>  %43 = fadd float %42, -1.600000e+01
>  %44 = call float @llvm.AMDIL.exp.(float %43)
>  %45 = fmul float %38, %44
>  %46 = fmul float %39, %44
>  %47 = fmul float %40, %44
>  %48 = fcmp oge float %22, 0.000000e+00
>  %49 = sext i1 %48 to i32
>  %50 = bitcast i32 %49 to float
>  %51 = bitcast float %50 to i32
>  %52 = icmp ne i32 %51, 0
>  %. = select i1 %52, float %45, float %38
>  %.12 = select i1 %52, float %46, float %39
>  %.13 = select i1 %52, float %47, float %40
>  %.14 = select i1 %52, float 1.000000e+00, float %41
>  %53 = fmul float %., %27
>  %54 = fmul float %.12, %28
>  %55 = fmul float %.13, %29
>  %56 = fmul float %.14, %30
>  %57 = call i32 @llvm.SI.packf16(float %53, float %54)
>  %58 = bitcast i32 %57 to float
>  %59 = call i32 @llvm.SI.packf16(float %55, float %56)
>  %60 = bitcast i32 %59 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %58, float %60, float %58, float %60)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%28](align=8)(tbaa=!"const")
>	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%25](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MOV_B32_e32 -1.600000e+01, %EXEC<imp-use>
>	%VGPR7<def> = V_MOV_B32_e32 3.200000e+01, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR6<def> = V_MAD_F32 %VGPR5, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_EXP_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR3, %VGPR6, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %SGPR0<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR3, %VGPR7<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR7<kill>, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR2, %VGPR6, %EXEC<imp-use>
>	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR8<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR4, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR6<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR5, 1.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
>	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR6<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR7<kill>, %VGPR0<kill>, %VGPR7, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c80c0500
>c80d0501
>c8080400
>c8090401
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>7e0c02ff
>c1800000
>7e0e02ff
>42000000
>bf8c0770
>d2820006
>041a0f05
>7e0c4b06
>100e0d03
>c0800100
>bf8c007f
>c2000100
>bf8c007f
>d00c0000
>02010000
>d2000007
>00020f03
>c8200100
>c8210101
>100e1107
>10100d02
>d2000008
>00021102
>c8240000
>c8250001
>10101308
>5e0e0f08
>100c0d04
>d2000006
>00020d04
>c8200200
>c8210201
>100c1106
>d2000002
>0001e505
>c80c0300
>c80d0301
>10000702
>5e000106
>f8001c0f
>00070007
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
>  %25 = bitcast i32 %24 to float
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR6 in %vreg3
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR6
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>5e000101
>c8060102
>c80a0002
>5e020302
>f8001c0f
>00010001
>bf810000
>AL lib: pulseaudio.c:612: Context did not connect: Access denied
>AL lib: pulseaudio.c:612: Context did not connect: Access denied
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
>	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	EXP 15, 0, 0, 1, 1, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>f800180f
>03020100
>bf810000
>AL lib: pulseaudio.c:612: Context did not connect: Access denied
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
>  %25 = bitcast i32 %24 to float
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR6 in %vreg3
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR6
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>5e000101
>c8060102
>c80a0002
>5e020302
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR6_SGPR7 %VGPR0
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%19](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
>	S_WAITCNT 1904
>	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 15
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	S_WAITCNT 1904
>	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %31 = fdiv float %28, %30
>  %32 = fdiv float %29, %30
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, %24
>  %43 = fmul float %39, %25
>  %44 = fmul float %40, %26
>  %45 = fmul float %41, %27
>  %46 = call i32 @llvm.SI.packf16(float %42, float %43)
>  %47 = bitcast i32 %46 to float
>  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %49 = bitcast i32 %48 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_RCP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
>	%SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR5, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR4, %VGPR7<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR7<kill>, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR3, %VGPR7<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
>	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR8<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR6<kill>, %VGPR0, %VGPR6, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e065503
>100a0702
>c8080400
>c8090401
>10080702
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020204
>c8180300
>c8190301
>bf8c0770
>100c0d05
>c81c0200
>c81d0201
>100e0f04
>5e0c0d07
>c81c0100
>c81d0101
>100e0f03
>c8200000
>c8210001
>10001102
>5e000f00
>f8001c0f
>06000600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
>  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
>  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
>  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = extractelement <4 x float> %59, i32 3
>  %64 = fmul float %46, %11
>  %65 = fmul float %46, %12
>  %66 = fmul float %46, %13
>  %67 = fmul float %46, %14
>  %68 = fmul float %47, %15
>  %69 = fadd float %68, %64
>  %70 = fmul float %47, %16
>  %71 = fadd float %70, %65
>  %72 = fmul float %47, %17
>  %73 = fadd float %72, %66
>  %74 = fmul float %47, %18
>  %75 = fadd float %74, %67
>  %76 = fmul float %48, %19
>  %77 = fadd float %76, %69
>  %78 = fmul float %48, %20
>  %79 = fadd float %78, %71
>  %80 = fmul float %48, %21
>  %81 = fadd float %80, %73
>  %82 = fmul float %48, %22
>  %83 = fadd float %82, %75
>  %84 = fmul float %49, %23
>  %85 = fadd float %84, %77
>  %86 = fmul float %49, %24
>  %87 = fadd float %86, %79
>  %88 = fmul float %49, %25
>  %89 = fadd float %88, %81
>  %90 = fmul float %49, %26
>  %91 = fadd float %90, %83
>  %92 = fmul float %60, %27
>  %93 = fmul float %60, %28
>  %94 = fmul float %60, %29
>  %95 = fmul float %60, %30
>  %96 = fmul float %61, %31
>  %97 = fadd float %96, %92
>  %98 = fmul float %61, %32
>  %99 = fadd float %98, %93
>  %100 = fmul float %61, %33
>  %101 = fadd float %100, %94
>  %102 = fmul float %61, %34
>  %103 = fadd float %102, %95
>  %104 = fmul float %62, %35
>  %105 = fadd float %104, %97
>  %106 = fmul float %62, %36
>  %107 = fadd float %106, %99
>  %108 = fmul float %62, %37
>  %109 = fadd float %108, %101
>  %110 = fmul float %62, %38
>  %111 = fadd float %110, %103
>  %112 = fmul float %63, %39
>  %113 = fadd float %112, %105
>  %114 = fmul float %63, %40
>  %115 = fadd float %114, %107
>  %116 = fmul float %63, %41
>  %117 = fadd float %116, %109
>  %118 = fmul float %63, %42
>  %119 = fadd float %118, %111
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %53, float %54, float %55, float %56)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %113, float %115, float %117, float %119)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %85, float %87, float %89, float %91)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%55](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
>	S_WAITCNT 1904
>	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%64](align=8)(tbaa=!"const")
>	S_WAITCNT 15
>	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR4, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e64 %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR4, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e64 %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR4, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e64 %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR2, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR3, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR4, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
>	EXP 15, 33, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%46](align=8)(tbaa=!"const")
>	S_WAITCNT 15
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	S_WAITCNT 112
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e64 %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR1, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e64 %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR1, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR1, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e64 %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR1, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0840708
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>7e0a0204
>d2100005
>02020b01
>c2020117
>bf8c007f
>7e0c0204
>d2820005
>04160d02
>c202011b
>bf8c007f
>7e0c0204
>d2820005
>04160d03
>c202011f
>bf8c007f
>7e0c0204
>d2820005
>04160d04
>c2020112
>bf8c007f
>7e0c0204
>d2100006
>02020d01
>c2020116
>bf8c007f
>7e0e0204
>d2820006
>041a0f02
>c202011a
>bf8c007f
>7e0e0204
>d2820006
>041a0f03
>c202011e
>bf8c007f
>7e0e0204
>d2820006
>041a0f04
>c2020111
>bf8c007f
>7e0e0204
>d2100007
>02020f01
>c2020115
>bf8c007f
>7e100204
>d2820007
>041e1102
>c2020119
>bf8c007f
>7e100204
>d2820007
>041e1103
>c202011d
>bf8c007f
>7e100204
>d2820007
>041e1104
>c2020110
>bf8c007f
>7e100204
>d2100008
>02021101
>c2020114
>bf8c007f
>7e120204
>d2820008
>04221302
>c2020118
>bf8c007f
>7e120204
>d2820008
>04221303
>c202011c
>bf8c007f
>7e120204
>d2820001
>04221304
>f800021f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>7e080204
>d2100004
>02020900
>c2020107
>bf8c007f
>7e0a0204
>d2820004
>04120b01
>c202010b
>bf8c007f
>7e0a0204
>d2820004
>04120b02
>c202010f
>bf8c007f
>7e0a0204
>d2820004
>04120b03
>c2020102
>bf8c007f
>7e0a0204
>d2100005
>02020b00
>c2020106
>bf8c007f
>7e0c0204
>d2820005
>04160d01
>c202010a
>bf8c007f
>7e0c0204
>d2820005
>04160d02
>c202010e
>bf8c007f
>7e0c0204
>d2820005
>04160d03
>c2020101
>bf8c007f
>7e0c0204
>d2100006
>02020d00
>c2020105
>bf8c007f
>7e0e0204
>d2820006
>041a0f01
>c2020109
>bf8c007f
>7e0e0204
>d2820006
>041a0f02
>c202010d
>bf8c007f
>7e0e0204
>d2820006
>041a0f03
>c2020100
>bf8c007f
>7e0e0204
>d2100007
>02020f00
>c2020104
>bf8c007f
>7e100204
>d2820007
>041e1101
>c2020108
>bf8c007f
>7e100204
>d2820007
>041e1102
>c200010c
>bf8c007f
>7e100200
>d2820000
>041e1103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], CONST[4]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
>  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %33 = fdiv float %30, %32
>  %34 = fdiv float %31, %32
>  %35 = bitcast float %33 to i32
>  %36 = bitcast float %34 to i32
>  %37 = insertelement <2 x i32> undef, i32 %35, i32 0
>  %38 = insertelement <2 x i32> %37, i32 %36, i32 1
>  %39 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %38, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %40 = extractelement <4 x float> %39, i32 0
>  %41 = extractelement <4 x float> %39, i32 1
>  %42 = extractelement <4 x float> %39, i32 2
>  %43 = extractelement <4 x float> %39, i32 3
>  %44 = fmul float %40, %22
>  %45 = fmul float %41, %23
>  %46 = fmul float %42, %24
>  %47 = fmul float %43, %25
>  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %49 = bitcast i32 %48 to float
>  %50 = call i32 @llvm.SI.packf16(float %46, float %47)
>  %51 = bitcast i32 %50 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %49, float %51, float %49, float %51)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_RCP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
>	%VGPR4<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%31](align=8)(tbaa=!"const")
>	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%28](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e64 %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 16; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MUL_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0300
>c80d0301
>7e065503
>100a0702
>c8080000
>c8090001
>10080702
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430004
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>7e080204
>d2100004
>02020903
>c2020112
>bf8c007f
>7e0a0204
>d2100005
>02020b02
>5e080905
>c2020111
>bf8c007f
>7e0a0204
>d2100005
>02020b01
>c2000110
>bf8c007f
>7e0c0200
>d2100000
>02020d00
>5e000b00
>f8001c0f
>04000400
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MUL TEMP[0], IN[1].xxxx, CONST[4]
>  5: MAD TEMP[0], IN[1].yyyy, CONST[5], TEMP[0]
>  6: MAD TEMP[0], IN[1].zzzz, CONST[6], TEMP[0]
>  7: MAD OUT[1], IN[1].wwww, CONST[7], TEMP[0]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = fmul float %46, %11
>  %58 = fmul float %46, %12
>  %59 = fmul float %46, %13
>  %60 = fmul float %46, %14
>  %61 = fmul float %47, %15
>  %62 = fadd float %61, %57
>  %63 = fmul float %47, %16
>  %64 = fadd float %63, %58
>  %65 = fmul float %47, %17
>  %66 = fadd float %65, %59
>  %67 = fmul float %47, %18
>  %68 = fadd float %67, %60
>  %69 = fmul float %48, %19
>  %70 = fadd float %69, %62
>  %71 = fmul float %48, %20
>  %72 = fadd float %71, %64
>  %73 = fmul float %48, %21
>  %74 = fadd float %73, %66
>  %75 = fmul float %48, %22
>  %76 = fadd float %75, %68
>  %77 = fmul float %49, %23
>  %78 = fadd float %77, %70
>  %79 = fmul float %49, %24
>  %80 = fadd float %79, %72
>  %81 = fmul float %49, %25
>  %82 = fadd float %81, %74
>  %83 = fmul float %49, %26
>  %84 = fadd float %83, %76
>  %85 = fmul float %53, %27
>  %86 = fmul float %53, %28
>  %87 = fmul float %53, %29
>  %88 = fmul float %53, %30
>  %89 = fmul float %54, %31
>  %90 = fadd float %89, %85
>  %91 = fmul float %54, %32
>  %92 = fadd float %91, %86
>  %93 = fmul float %54, %33
>  %94 = fadd float %93, %87
>  %95 = fmul float %54, %34
>  %96 = fadd float %95, %88
>  %97 = fmul float %55, %35
>  %98 = fadd float %97, %90
>  %99 = fmul float %55, %36
>  %100 = fadd float %99, %92
>  %101 = fmul float %55, %37
>  %102 = fadd float %101, %94
>  %103 = fmul float %55, %38
>  %104 = fadd float %103, %96
>  %105 = fmul float %56, %39
>  %106 = fadd float %105, %98
>  %107 = fmul float %56, %40
>  %108 = fadd float %107, %100
>  %109 = fmul float %56, %41
>  %110 = fadd float %109, %102
>  %111 = fmul float %56, %42
>  %112 = fadd float %111, %104
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %106, float %108, float %110, float %112)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %78, float %80, float %82, float %84)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%55](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR4, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e64 %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR4, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e64 %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR4, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e64 %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR2, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR3, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR4, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
>	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%46](align=8)(tbaa=!"const")
>	S_WAITCNT 15
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	S_WAITCNT 112
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e64 %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR1, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e64 %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR1, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR1, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e64 %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR1, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>7e0a0204
>d2100005
>02020b01
>c2020117
>bf8c007f
>7e0c0204
>d2820005
>04160d02
>c202011b
>bf8c007f
>7e0c0204
>d2820005
>04160d03
>c202011f
>bf8c007f
>7e0c0204
>d2820005
>04160d04
>c2020112
>bf8c007f
>7e0c0204
>d2100006
>02020d01
>c2020116
>bf8c007f
>7e0e0204
>d2820006
>041a0f02
>c202011a
>bf8c007f
>7e0e0204
>d2820006
>041a0f03
>c202011e
>bf8c007f
>7e0e0204
>d2820006
>041a0f04
>c2020111
>bf8c007f
>7e0e0204
>d2100007
>02020f01
>c2020115
>bf8c007f
>7e100204
>d2820007
>041e1102
>c2020119
>bf8c007f
>7e100204
>d2820007
>041e1103
>c202011d
>bf8c007f
>7e100204
>d2820007
>041e1104
>c2020110
>bf8c007f
>7e100204
>d2100008
>02021101
>c2020114
>bf8c007f
>7e120204
>d2820008
>04221302
>c2020118
>bf8c007f
>7e120204
>d2820008
>04221303
>c202011c
>bf8c007f
>7e120204
>d2820001
>04221304
>f800020f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>7e080204
>d2100004
>02020900
>c2020107
>bf8c007f
>7e0a0204
>d2820004
>04120b01
>c202010b
>bf8c007f
>7e0a0204
>d2820004
>04120b02
>c202010f
>bf8c007f
>7e0a0204
>d2820004
>04120b03
>c2020102
>bf8c007f
>7e0a0204
>d2100005
>02020b00
>c2020106
>bf8c007f
>7e0c0204
>d2820005
>04160d01
>c202010a
>bf8c007f
>7e0c0204
>d2820005
>04160d02
>c202010e
>bf8c007f
>7e0c0204
>d2820005
>04160d03
>c2020101
>bf8c007f
>7e0c0204
>d2100006
>02020d00
>c2020105
>bf8c007f
>7e0e0204
>d2820006
>041a0f01
>c2020109
>bf8c007f
>7e0e0204
>d2820006
>041a0f02
>c202010d
>bf8c007f
>7e0e0204
>d2820006
>041a0f03
>c2020100
>bf8c007f
>7e0e0204
>d2100007
>02020f00
>c2020104
>bf8c007f
>7e100204
>d2820007
>041e1101
>c2020108
>bf8c007f
>7e100204
>d2820007
>041e1102
>c200010c
>bf8c007f
>7e100200
>d2820000
>041e1103
>f80008cf
>04050600
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
>  %36 = bitcast i32 %35 to float
>  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
>  %38 = bitcast i32 %37 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
>	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR6_SGPR7 %VGPR0
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%19](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
>	S_WAITCNT 1904
>	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 15
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	S_WAITCNT 1904
>	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR6 in %vreg3
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR6
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
>	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL IN[1], GENERIC[20], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.2500,     0.0000,     0.0000,     0.0000}
>  0: MIN TEMP[0], IN[0], CONST[0].zwzw
>  1: MAX TEMP[0], TEMP[0], CONST[0].xyxy
>  2: MOV TEMP[1].xy, TEMP[0].xyyy
>  3: TEX TEMP[1], TEMP[1], SAMP[0], 2D
>  4: MUL TEMP[1], TEMP[1], IMM[0].xxxx
>  5: MOV TEMP[0].xy, TEMP[0].zwww
>  6: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  7: MAD TEMP[1], TEMP[0], IMM[0].xxxx, TEMP[1]
>  8: MIN TEMP[0], IN[1], CONST[0].zwzw
>  9: MAX TEMP[0], TEMP[0], CONST[0].xyxy
> 10: MOV TEMP[2].xy, TEMP[0].xyyy
> 11: TEX TEMP[2], TEMP[2], SAMP[0], 2D
> 12: MAD TEMP[1], TEMP[2], IMM[0].xxxx, TEMP[1]
> 13: MOV TEMP[0].xy, TEMP[0].zwww
> 14: TEX TEMP[0], TEMP[0], SAMP[0], 2D
> 15: MAD TEMP[0], TEMP[0], IMM[0].xxxx, TEMP[1]
> 16: MOV OUT[0], TEMP[0]
> 17: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %38 = fcmp uge float %30, %24
>  %39 = select i1 %38, float %24, float %30
>  %40 = fcmp uge float %31, %25
>  %41 = select i1 %40, float %25, float %31
>  %42 = fcmp uge float %32, %24
>  %43 = select i1 %42, float %24, float %32
>  %44 = fcmp uge float %33, %25
>  %45 = select i1 %44, float %25, float %33
>  %46 = fcmp uge float %39, %22
>  %47 = select i1 %46, float %39, float %22
>  %48 = fcmp uge float %41, %23
>  %49 = select i1 %48, float %41, float %23
>  %50 = fcmp uge float %43, %22
>  %51 = select i1 %50, float %43, float %22
>  %52 = fcmp uge float %45, %23
>  %53 = select i1 %52, float %45, float %23
>  %54 = bitcast float %47 to i32
>  %55 = bitcast float %49 to i32
>  %56 = insertelement <2 x i32> undef, i32 %54, i32 0
>  %57 = insertelement <2 x i32> %56, i32 %55, i32 1
>  %58 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %57, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %59 = extractelement <4 x float> %58, i32 0
>  %60 = extractelement <4 x float> %58, i32 1
>  %61 = extractelement <4 x float> %58, i32 2
>  %62 = extractelement <4 x float> %58, i32 3
>  %63 = fmul float %59, 2.500000e-01
>  %64 = fmul float %60, 2.500000e-01
>  %65 = fmul float %61, 2.500000e-01
>  %66 = fmul float %62, 2.500000e-01
>  %67 = bitcast float %51 to i32
>  %68 = bitcast float %53 to i32
>  %69 = insertelement <2 x i32> undef, i32 %67, i32 0
>  %70 = insertelement <2 x i32> %69, i32 %68, i32 1
>  %71 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %70, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %72 = extractelement <4 x float> %71, i32 0
>  %73 = extractelement <4 x float> %71, i32 1
>  %74 = extractelement <4 x float> %71, i32 2
>  %75 = extractelement <4 x float> %71, i32 3
>  %76 = fmul float %72, 2.500000e-01
>  %77 = fadd float %76, %63
>  %78 = fmul float %73, 2.500000e-01
>  %79 = fadd float %78, %64
>  %80 = fmul float %74, 2.500000e-01
>  %81 = fadd float %80, %65
>  %82 = fmul float %75, 2.500000e-01
>  %83 = fadd float %82, %66
>  %84 = fcmp uge float %34, %24
>  %85 = select i1 %84, float %24, float %34
>  %86 = fcmp uge float %35, %25
>  %87 = select i1 %86, float %25, float %35
>  %88 = fcmp uge float %36, %24
>  %89 = select i1 %88, float %24, float %36
>  %90 = fcmp uge float %37, %25
>  %91 = select i1 %90, float %25, float %37
>  %92 = fcmp uge float %85, %22
>  %93 = select i1 %92, float %85, float %22
>  %94 = fcmp uge float %87, %23
>  %95 = select i1 %94, float %87, float %23
>  %96 = fcmp uge float %89, %22
>  %97 = select i1 %96, float %89, float %22
>  %98 = fcmp uge float %91, %23
>  %99 = select i1 %98, float %91, float %23
>  %100 = bitcast float %93 to i32
>  %101 = bitcast float %95 to i32
>  %102 = insertelement <2 x i32> undef, i32 %100, i32 0
>  %103 = insertelement <2 x i32> %102, i32 %101, i32 1
>  %104 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %103, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %105 = extractelement <4 x float> %104, i32 0
>  %106 = extractelement <4 x float> %104, i32 1
>  %107 = extractelement <4 x float> %104, i32 2
>  %108 = extractelement <4 x float> %104, i32 3
>  %109 = fmul float %105, 2.500000e-01
>  %110 = fadd float %109, %77
>  %111 = fmul float %106, 2.500000e-01
>  %112 = fadd float %111, %79
>  %113 = fmul float %107, 2.500000e-01
>  %114 = fadd float %113, %81
>  %115 = fmul float %108, 2.500000e-01
>  %116 = fadd float %115, %83
>  %117 = bitcast float %97 to i32
>  %118 = bitcast float %99 to i32
>  %119 = insertelement <2 x i32> undef, i32 %117, i32 0
>  %120 = insertelement <2 x i32> %119, i32 %118, i32 1
>  %121 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %120, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %122 = extractelement <4 x float> %121, i32 0
>  %123 = extractelement <4 x float> %121, i32 1
>  %124 = extractelement <4 x float> %121, i32 2
>  %125 = extractelement <4 x float> %121, i32 3
>  %126 = fmul float %122, 2.500000e-01
>  %127 = fadd float %126, %110
>  %128 = fmul float %123, 2.500000e-01
>  %129 = fadd float %128, %112
>  %130 = fmul float %124, 2.500000e-01
>  %131 = fadd float %130, %114
>  %132 = fmul float %125, 2.500000e-01
>  %133 = fadd float %132, %116
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %127, float %129, float %131, float %133)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%SGPR12_SGPR13<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MOV_B32_e32 %SGPR0, %EXEC<imp-use>
>	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR3, %SGPR12_SGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%SGPR12_SGPR13<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR1, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR2<kill>, %SGPR12_SGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%SGPR12_SGPR13<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR7, %EXEC<imp-use>
>	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR7, %SGPR12_SGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%SGPR10_SGPR11<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR8, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR8, %EXEC<imp-use>
>	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR8, %VGPR2<kill>, %SGPR10_SGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%31](align=8)(tbaa=!"const")
>	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%28](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR9_VGPR10_VGPR11_VGPR12<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
>	%VGPR2<def> = V_MOV_B32_e32 2.500000e-01, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR5<def> = V_MUL_F32_e32 %VGPR12, %VGPR2, %EXEC<imp-use>
>	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR3, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR14<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR6<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
>	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR7, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR8, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_CNDMASK_B32_e64 %VGPR8, %VGPR6<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
>	%VGPR13_VGPR14_VGPR15_VGPR16<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR5<def> = V_MAD_F32 %VGPR16, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR3, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR18<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR6<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18<imp-def>
>	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR7, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR8, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_CNDMASK_B32_e64 %VGPR8, %VGPR6<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18<imp-use,kill>, %VGPR17_VGPR18<imp-def>
>	%VGPR17_VGPR18_VGPR19_VGPR20<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR17_VGPR18<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR5<def> = V_MAD_F32 %VGPR20, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR3<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR4<kill>, %VGPR3<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
>	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 2, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 2, 1, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR7<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR0, %SGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR0<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
>	%VGPR21_VGPR22_VGPR23_VGPR24<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR0<def> = V_MAD_F32 %VGPR24, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_MUL_F32_e32 %VGPR11, %VGPR2, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR15, %VGPR2, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR19, %VGPR2, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR23, %VGPR2, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %VGPR10, %VGPR2, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR14, %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR18, %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR22, %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e32 %VGPR9, %VGPR2, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
>	%VGPR4<def> = V_MAD_F32 %VGPR13, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
>	%VGPR4<def> = V_MAD_F32 %VGPR17, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>
>	%VGPR2<def> = V_MAD_F32 %VGPR21, %VGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23_VGPR24<imp-use,kill>
>	EXP 15, 0, 0, 1, 1, %VGPR2<kill>, %VGPR3<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c0840100
>bf8c007f
>c2000903
>bf8c007f
>d00c000c
>02000102
>7e060200
>d2000002
>00320702
>c2008901
>bf8c007f
>d00c000c
>02000302
>7e080201
>d2000006
>00320504
>c8080000
>c8090001
>c2038902
>bf8c007f
>d00c000c
>02000f02
>7e0e0207
>d2000002
>00320f02
>c2040900
>bf8c007f
>d00c000a
>02001102
>7e100208
>d2000005
>002a0508
>c0860300
>c0c80500
>bf8c007f
>f0800f00
>00640905
>7e0402ff
>3e800000
>bf8c0770
>100a050c
>c8180300
>c8190301
>d00c0002
>02000106
>d2000006
>000a0706
>d00c0002
>02000306
>d200000e
>000a0d04
>c8180200
>c8190201
>d00c0002
>02000f06
>d2000006
>000a0f06
>d00c0002
>02001106
>d200000d
>000a0d08
>f0800f00
>00640d0d
>bf8c0770
>d2820005
>04160510
>c8180500
>c8190501
>d00c0002
>02000106
>d2000006
>000a0706
>d00c0002
>02000306
>d2000012
>000a0d04
>c8180400
>c8190401
>d00c0002
>02000f06
>d2000006
>000a0f06
>d00c0002
>02001106
>d2000011
>000a0d08
>f0800f00
>00641111
>bf8c0770
>d2820005
>04160514
>c8180700
>c8190701
>d00c0002
>02000106
>d2000003
>000a0706
>d00c0000
>02000303
>d2000004
>00020704
>c8180600
>c8190601
>d00c0000
>02000f06
>d2000000
>00020f06
>d00c0000
>02001100
>d2000003
>00020108
>f0800f00
>00641503
>bf8c0770
>d2820000
>04160518
>1002050b
>d2820001
>0406050f
>d2820001
>04060513
>d2820001
>04060517
>1006050a
>d2820003
>040e050e
>d2820003
>040e0512
>d2820003
>040e0516
>10080509
>d2820004
>0412050d
>d2820004
>04120511
>d2820002
>04120515
>f800180f
>00010302
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], CLIPVERTEX
>DCL OUT[2], GENERIC[19]
>DCL OUT[3], GENERIC[20]
>DCL CONST[0..1]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.5000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MUL TEMP[2].xy, CONST[1].xyyy, IMM[0].zzzz
>  4: ADD TEMP[1].xy, TEMP[1].xyyy, -TEMP[2].xyyy
>  5: MOV TEMP[2].xy, TEMP[1].xyxx
>  6: ADD TEMP[1].x, TEMP[1].xxxx, CONST[1].xxxx
>  7: MOV TEMP[2].zw, TEMP[1].yyxy
>  8: ADD TEMP[3].x, TEMP[1].yyyy, CONST[1].yyyy
>  9: MOV TEMP[1].y, TEMP[3].xxxx
> 10: MOV TEMP[3].zw, TEMP[1].yyxy
> 11: ADD TEMP[1].x, TEMP[1].xxxx, -CONST[1].xxxx
> 12: MOV TEMP[3].xy, TEMP[1].xyxx
> 13: MOV OUT[2], TEMP[2]
> 14: MOV OUT[3], TEMP[3]
> 15: MOV OUT[0], TEMP[0]
> 16: MOV OUT[1], TEMP[0]
> 17: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
>  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %5)
>  %20 = extractelement <4 x float> %19, i32 0
>  %21 = extractelement <4 x float> %19, i32 1
>  %22 = extractelement <4 x float> %19, i32 2
>  %23 = extractelement <4 x float> %19, i32 3
>  %24 = fmul float %22, %11
>  %25 = fadd float %24, %13
>  %26 = fmul float %23, %12
>  %27 = fadd float %26, %14
>  %28 = fmul float %15, 5.000000e-01
>  %29 = fmul float %16, 5.000000e-01
>  %30 = fsub float -0.000000e+00, %28
>  %31 = fadd float %25, %30
>  %32 = fsub float -0.000000e+00, %29
>  %33 = fadd float %27, %32
>  %34 = fadd float %31, %15
>  %35 = fadd float %33, %16
>  %36 = fsub float -0.000000e+00, %15
>  %37 = fadd float %34, %36
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %31, float %33, float %34, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %37, float %35, float %34, float %35)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %20, float %21, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%20](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MUL_F32_e64 %SGPR4, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MUL_F32_e64 %SGPR0, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_ADD_F32_e32 %SGPR0, %VGPR5, %EXEC<imp-use>
>	EXP 15, 32, 0, 0, 0, %VGPR5<kill>, %VGPR4, %VGPR6, %VGPR4, %EXEC<imp-use>
>	S_WAITCNT 1807
>	%VGPR4<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_SUBREV_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
>	EXP 15, 33, 0, 0, 0, %VGPR5<kill>, %VGPR4<kill>, %VGPR6<kill>, %VGPR4, %EXEC<imp-use>
>	S_WAITCNT 1807
>	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
>	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
>	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>7e080204
>c2020101
>bf8c007f
>7e0a0204
>d2820004
>04120b03
>c2020105
>bf8c007f
>d2100005
>0201e004
>08080b04
>c2028102
>bf8c007f
>7e0a0205
>c2028100
>bf8c007f
>7e0c0205
>d2820005
>04160d02
>c2000104
>bf8c007f
>d2100006
>0201e000
>080a0d05
>060c0a00
>f800020f
>04060405
>bf8c070f
>06080804
>0a0a0c00
>f800021f
>04060405
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR6 in %vreg3
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR6
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
>	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], POSITION, LINEAR
>DCL IN[1], GENERIC[19], PERSPECTIVE
>DCL IN[2], GENERIC[20], PERSPECTIVE
>DCL IN[3], GENERIC[21], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL CONST[8]
>DCL CONST[0..3]
>DCL TEMP[0]
>DCL TEMP[1..5], LOCAL
>IMM[0] FLT32 {    0.0000,     0.0000,     2.0000,    -1.0000}
>  0: MOV TEMP[0], IN[0]
>  1: MAD TEMP[0].y, IN[0], CONST[8].xxxx, CONST[8].yyyy
>  2: MOV TEMP[1].xy, IN[1].zwww
>  3: TEX TEMP[1].w, TEMP[1], SAMP[2], 2D
>  4: MUL TEMP[1].x, TEMP[1].wwww, IN[3].wwww
>  5: MUL TEMP[2].x, CONST[0].xxxx, TEMP[1].xxxx
>  6: MUL TEMP[1].x, CONST[0].yyyy, TEMP[1].xxxx
>  7: DP3 TEMP[3].x, IN[2].xyzz, IN[2].xyzz
>  8: RSQ TEMP[3].x, TEMP[3].xxxx
>  9: MUL TEMP[3].xyz, IN[2].xyzz, TEMP[3].xxxx
> 10: ABS TEMP[4].x, TEMP[3].zzzz
> 11: ADD_SAT TEMP[4].x, TEMP[4].xxxx, -CONST[2].zzzz
> 12: MAD TEMP[4].x, TEMP[4].xxxx, CONST[2].yyyy, IMM[0].xxxx
> 13: POW TEMP[4].x, TEMP[4].xxxx, CONST[2].xxxx
> 14: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[4].xxxx
> 15: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[4].xxxx
> 16: MOV TEMP[4].xy, IN[1].xyyy
> 17: TEX TEMP[4], TEMP[4], SAMP[1], 2D
> 18: FSLT TEMP[5].x, IMM[0].yyyy, TEMP[4].zzzz
> 19: UIF TEMP[5].xxxx :2
> 20:   MOV TEMP[5].xy, TEMP[4].ywyy
> 21: ELSE :2
> 22:   MOV TEMP[5].xy, TEMP[4].xyxx
> 23: ENDIF
> 24: MAD TEMP[4].xy, TEMP[5].xyyy, IMM[0].zzzz, IMM[0].wwww
> 25: MUL TEMP[2].xy, TEMP[2].xxxx, TEMP[3].xyyy
> 26: MAD TEMP[1].xy, TEMP[1].xxxx, -TEMP[4].xyyy, TEMP[2].xyyy
> 27: MUL TEMP[2].xy, TEMP[0].xyyy, CONST[3].xyyy
> 28: MOV TEMP[3].xy, TEMP[2].xyyy
> 29: TEX TEMP[3].x, TEMP[3], SAMP[3], 2D
> 30: ABS TEMP[3].x, TEMP[3].xxxx
> 31: MAD TEMP[3].x, TEMP[3].xxxx, CONST[3].wwww, -CONST[3].zzzz
> 32: ADD TEMP[3].x, TEMP[3].xxxx, -IN[2].wwww
> 33: MUL_SAT TEMP[3].x, TEMP[3].xxxx, CONST[2].wwww
> 34: MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[3].xxxx
> 35: ADD_SAT TEMP[2].xy, TEMP[2].xyyy, TEMP[1].xyyy
> 36: MOV TEMP[2].xy, TEMP[2].xyyy
> 37: TEX TEMP[2].x, TEMP[2], SAMP[3], 2D
> 38: ABS TEMP[2].x, TEMP[2].xxxx
> 39: MAD TEMP[2].x, TEMP[2].xxxx, CONST[3].wwww, -CONST[3].zzzz
> 40: ADD TEMP[2].x, TEMP[2].xxxx, -IN[2].wwww
> 41: MUL_SAT TEMP[2].x, TEMP[2].xxxx, CONST[2].wwww
> 42: MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[2].xxxx
> 43: MAD TEMP[1].xy, TEMP[0].xyyy, CONST[0].zwww, TEMP[1].xyyy
> 44: MIN TEMP[1].xy, TEMP[1].xyyy, CONST[1].zwww
> 45: MAX TEMP[1].xy, TEMP[1].xyyy, CONST[1].xyyy
> 46: MOV TEMP[1].xy, TEMP[1].xyyy
> 47: TEX TEMP[1], TEMP[1], SAMP[0], 2D
> 48: MOV TEMP[2].w, TEMP[1].wwww
> 49: MUL TEMP[2].xyz, TEMP[1].xyzz, IN[3].xyzz
> 50: MOV OUT[0], TEMP[2]
> 51: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 28)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
>  %40 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
>  %42 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
>  %44 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %45 = load <32 x i8> addrspace(2)* %44, !tbaa !0
>  %46 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
>  %48 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %49 = load <32 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
>  %53 = load <32 x i8> addrspace(2)* %52, !tbaa !0
>  %54 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %57 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %58 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %59 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %60 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %61 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %62 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
>  %63 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %64 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %65 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %66 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
>  %67 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %68 = fmul float %13, %38
>  %69 = fadd float %68, %39
>  %70 = bitcast float %58 to i32
>  %71 = bitcast float %59 to i32
>  %72 = insertelement <2 x i32> undef, i32 %70, i32 0
>  %73 = insertelement <2 x i32> %72, i32 %71, i32 1
>  %74 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %73, <32 x i8> %49, <16 x i8> %51, i32 2)
>  %75 = extractelement <4 x float> %74, i32 3
>  %76 = fmul float %75, %67
>  %77 = fmul float %22, %76
>  %78 = fmul float %23, %76
>  %79 = fmul float %60, %60
>  %80 = fmul float %61, %61
>  %81 = fadd float %80, %79
>  %82 = fmul float %62, %62
>  %83 = fadd float %81, %82
>  %84 = call float @llvm.AMDGPU.rsq(float %83)
>  %85 = fmul float %60, %84
>  %86 = fmul float %61, %84
>  %87 = fmul float %62, %84
>  %88 = call float @fabs(float %87)
>  %89 = fsub float -0.000000e+00, %32
>  %90 = fadd float %88, %89
>  %91 = call float @llvm.AMDIL.clamp.(float %90, float 0.000000e+00, float 1.000000e+00)
>  %92 = fmul float %91, %31
>  %93 = fadd float %92, 0x3EE4F8B580000000
>  %94 = call float @llvm.pow.f32(float %93, float %30)
>  %95 = fmul float %78, %94
>  %96 = fmul float %77, %94
>  %97 = bitcast float %56 to i32
>  %98 = bitcast float %57 to i32
>  %99 = insertelement <2 x i32> undef, i32 %97, i32 0
>  %100 = insertelement <2 x i32> %99, i32 %98, i32 1
>  %101 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %100, <32 x i8> %45, <16 x i8> %47, i32 2)
>  %102 = extractelement <4 x float> %101, i32 0
>  %103 = extractelement <4 x float> %101, i32 1
>  %104 = extractelement <4 x float> %101, i32 2
>  %105 = extractelement <4 x float> %101, i32 3
>  %106 = fcmp olt float 0.000000e+00, %104
>  %107 = sext i1 %106 to i32
>  %108 = bitcast i32 %107 to float
>  %109 = bitcast float %108 to i32
>  %110 = icmp ne i32 %109, 0
>  %. = select i1 %110, float %103, float %102
>  %.24 = select i1 %110, float %105, float %103
>  %111 = fmul float %., 2.000000e+00
>  %112 = fadd float %111, -1.000000e+00
>  %113 = fmul float %.24, 2.000000e+00
>  %114 = fadd float %113, -1.000000e+00
>  %115 = fmul float %96, %85
>  %116 = fmul float %96, %86
>  %117 = fsub float -0.000000e+00, %112
>  %118 = fmul float %95, %117
>  %119 = fadd float %118, %115
>  %120 = fsub float -0.000000e+00, %114
>  %121 = fmul float %95, %120
>  %122 = fadd float %121, %116
>  %123 = fmul float %12, %34
>  %124 = fmul float %69, %35
>  %125 = bitcast float %123 to i32
>  %126 = bitcast float %124 to i32
>  %127 = insertelement <2 x i32> undef, i32 %125, i32 0
>  %128 = insertelement <2 x i32> %127, i32 %126, i32 1
>  %129 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %128, <32 x i8> %53, <16 x i8> %55, i32 2)
>  %130 = extractelement <4 x float> %129, i32 0
>  %131 = call float @fabs(float %130)
>  %132 = fsub float -0.000000e+00, %36
>  %133 = fmul float %131, %37
>  %134 = fadd float %133, %132
>  %135 = fsub float -0.000000e+00, %63
>  %136 = fadd float %134, %135
>  %137 = fmul float %136, %33
>  %138 = call float @llvm.AMDIL.clamp.(float %137, float 0.000000e+00, float 1.000000e+00)
>  %139 = fmul float %119, %138
>  %140 = fmul float %122, %138
>  %141 = fadd float %123, %139
>  %142 = fadd float %124, %140
>  %143 = call float @llvm.AMDIL.clamp.(float %141, float 0.000000e+00, float 1.000000e+00)
>  %144 = call float @llvm.AMDIL.clamp.(float %142, float 0.000000e+00, float 1.000000e+00)
>  %145 = bitcast float %143 to i32
>  %146 = bitcast float %144 to i32
>  %147 = insertelement <2 x i32> undef, i32 %145, i32 0
>  %148 = insertelement <2 x i32> %147, i32 %146, i32 1
>  %149 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %148, <32 x i8> %53, <16 x i8> %55, i32 2)
>  %150 = extractelement <4 x float> %149, i32 0
>  %151 = call float @fabs(float %150)
>  %152 = fsub float -0.000000e+00, %36
>  %153 = fmul float %151, %37
>  %154 = fadd float %153, %152
>  %155 = fsub float -0.000000e+00, %63
>  %156 = fadd float %154, %155
>  %157 = fmul float %156, %33
>  %158 = call float @llvm.AMDIL.clamp.(float %157, float 0.000000e+00, float 1.000000e+00)
>  %159 = fmul float %139, %158
>  %160 = fmul float %140, %158
>  %161 = fmul float %12, %24
>  %162 = fadd float %161, %159
>  %163 = fmul float %69, %25
>  %164 = fadd float %163, %160
>  %165 = fcmp uge float %162, %28
>  %166 = select i1 %165, float %28, float %162
>  %167 = fcmp uge float %164, %29
>  %168 = select i1 %167, float %29, float %164
>  %169 = fcmp uge float %166, %26
>  %170 = select i1 %169, float %166, float %26
>  %171 = fcmp uge float %168, %27
>  %172 = select i1 %171, float %168, float %27
>  %173 = bitcast float %170 to i32
>  %174 = bitcast float %172 to i32
>  %175 = insertelement <2 x i32> undef, i32 %173, i32 0
>  %176 = insertelement <2 x i32> %175, i32 %174, i32 1
>  %177 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %176, <32 x i8> %41, <16 x i8> %43, i32 2)
>  %178 = extractelement <4 x float> %177, i32 0
>  %179 = extractelement <4 x float> %177, i32 1
>  %180 = extractelement <4 x float> %177, i32 2
>  %181 = extractelement <4 x float> %177, i32 3
>  %182 = fmul float %178, %64
>  %183 = fmul float %179, %65
>  %184 = fmul float %180, %66
>  %185 = call i32 @llvm.SI.packf16(float %182, float %183)
>  %186 = bitcast i32 %185 to float
>  %187 = call i32 @llvm.SI.packf16(float %184, float %181)
>  %188 = bitcast i32 %187 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %186, float %188, float %186, float %188)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
>	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
>	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
>	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%51](align=8)(tbaa=!"const")
>	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%48](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR4_VGPR5_VGPR6_VGPR7<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR8_SGPR9<def> = V_CMP_GT_F32_e64 %VGPR6, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR5, %VGPR7, %SGPR8_SGPR9, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_ADD_F32_e32 %VGPR8<kill>, %VGPR8, %EXEC<imp-use>
>	%VGPR8<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
>	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
>	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
>	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%57](align=8)(tbaa=!"const")
>	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%54](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR9<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR9_VGPR10<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
>	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR10<kill>, %EXEC<imp-use>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
>	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR13<def> = V_MUL_F32_e32 %VGPR12, %VGPR12, %EXEC<imp-use>
>	%VGPR13<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 2, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 2, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR13<def> = V_MAD_F32 %VGPR14, %VGPR14, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_RSQ_LEGACY_F32_e32 %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR13, %EXEC<imp-use>
>	%VGPR14<def> = V_ADD_F32_e64 %VGPR14<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR14<def> = V_SUBREV_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_ADD_F32_e64 %VGPR14<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9; mem:LD4[<unknown>]
>	%VGPR15<def> = V_MOV_B32_e32 1.000000e-05, %EXEC<imp-use>
>	S_WAITCNT 127
>	%VGPR14<def> = V_MAD_F32 %VGPR14<kill>, %SGPR0<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR14<def> = V_LOG_F32_e32 %VGPR14<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR14<def> = V_MUL_LEGACY_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_EXP_F32_e32 %VGPR14<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR10, %VGPR8<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR14<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR13, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %VGPR9, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 32; mem:LD4[<unknown>]
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 33; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR14<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR15<def> = V_MUL_F32_e32 %SGPR0, %VGPR3, %EXEC<imp-use>, %VGPR14_VGPR15<imp-def>
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR14<def> = V_MUL_F32_e32 %SGPR1, %VGPR2, %EXEC<imp-use>, %VGPR14_VGPR15<imp-use,kill>, %VGPR14_VGPR15<imp-def>
>	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 12; mem:LD16[%63](align=8)(tbaa=!"const")
>	%SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 24; mem:LD32[%60](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR14<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR14_VGPR15<kill>, %SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27, %SGPR16_SGPR17_SGPR18_SGPR19, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR14<def> = V_ADD_F32_e64 %VGPR14<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR14<def> = V_MUL_F32_e32 %SGPR7, %VGPR14<kill>, %EXEC<imp-use>
>	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR14<def> = V_SUBREV_F32_e32 %SGPR10, %VGPR14<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_SUB_F32_e32 %VGPR14<kill>, %VGPR11, %EXEC<imp-use>
>	%SGPR11<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR14<def> = V_MUL_F32_e32 %SGPR11, %VGPR14<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_ADD_F32_e64 %VGPR14<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR15<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR16<def> = V_ADD_F32_e64 %VGPR15<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR15_VGPR16<imp-def>
>	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR5, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR4, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR1<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_ADD_F32_e64 %VGPR5<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
>	%VGPR5<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR15_VGPR16<kill>, %SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27<kill>, %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR5<def> = V_ADD_F32_e64 %VGPR5<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_SUBREV_F32_e32 %SGPR10<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e32 %SGPR11<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_ADD_F32_e64 %VGPR5<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR5, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR6<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR3<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
>	%VGPR3<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR3<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR2<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%45](align=8)(tbaa=!"const")
>	%SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%42](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR6_VGPR7<kill>, %SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
>	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR4, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR6<kill>, %VGPR5, %EXEC<imp-use>
>	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
>	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR3, %VGPR7<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
>	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR8<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR6<kill>, %VGPR0, %VGPR6, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8140100
>c8150101
>c8100000
>c8110001
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430404
>bf8c0770
>d0080008
>02010106
>d2000008
>00220f05
>06101108
>061010f3
>c8280300
>c8290301
>c8240200
>c8250201
>c0860308
>c0c80510
>bf8c007f
>f0800800
>00640909
>c8280b00
>c8290b01
>bf8c0770
>10121509
>c0860100
>bf8c007f
>c2000d01
>bf8c007f
>10141200
>c82c0500
>c82d0501
>c8300400
>c8310401
>101a190c
>d282000d
>0436170b
>c8380600
>c8390601
>d282000d
>04361d0e
>7e1a5b0d
>101c1b0e
>d206010e
>0201010e
>c2000d0a
>bf8c007f
>0a1c1c00
>d206080e
>0201010e
>c2000d09
>7e1e02ff
>3727c5ac
>bf8c007f
>d282000e
>043c010e
>7e1c4f0e
>c2000d08
>bf8c007f
>0e1c1c00
>7e1c4b0e
>10141d0a
>1010110a
>c2000d00
>bf8c007f
>10121200
>10121d09
>10161b0b
>10161709
>0810110b
>c82c0700
>c82d0701
>c2000d20
>c2008d21
>bf8c007f
>7e1c0201
>d2820003
>04380103
>c2000d0d
>bf8c007f
>101e0600
>c2008d0c
>bf8c007f
>101c0401
>c088030c
>c0ca0518
>bf8c007f
>f0800100
>00850e0e
>bf8c0770
>d206010e
>0201010e
>c2038d0f
>bf8c007f
>101c1c07
>c2050d0e
>bf8c007f
>0a1c1c0a
>081c170e
>c2058d0b
>bf8c007f
>101c1c0b
>d206080e
>0201010e
>10101d08
>d282000f
>04200103
>d2060810
>0201010f
>d2000004
>00220b04
>06080904
>060808f3
>1008090a
>100a1b0c
>100a0b09
>08080905
>10081d04
>d2820005
>04100302
>d206080f
>02010105
>f0800100
>0085050f
>bf8c0770
>d2060105
>02010105
>100a0a07
>0a0a0a0a
>080a1705
>100a0a0b
>d2060805
>02010105
>100c0b08
>c2000d03
>bf8c007f
>d2820003
>04180103
>c2000d07
>bf8c007f
>d00c0008
>02000103
>7e0c0200
>d2000003
>00220d03
>c2000d05
>bf8c007f
>d00c0008
>02000103
>7e0c0200
>d2000007
>00220706
>10060b04
>c2000d02
>bf8c007f
>d2820002
>040c0102
>c2000d06
>bf8c007f
>d00c0008
>02000102
>7e060200
>d2000002
>00220702
>c2000d04
>bf8c007f
>d00c0008
>02000102
>7e060200
>d2000006
>00220503
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020206
>c8180a00
>c8190a01
>bf8c0770
>100c0d04
>5e0c0b06
>c81c0900
>c81d0901
>100e0f03
>c8200800
>c8210801
>10001102
>5e000f00
>f8001c0f
>06000600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL IN[6]
>DCL OUT[0], POSITION
>DCL OUT[1], CLIPVERTEX
>DCL OUT[2], GENERIC[19]
>DCL OUT[3], GENERIC[20]
>DCL OUT[4], GENERIC[21]
>DCL CONST[0..240]
>DCL TEMP[0..9], LOCAL
>DCL ADDR[0]
>IMM[0] FLT32 {    0.0010,     1.0000,   255.0100,    -0.1000}
>IMM[1] INT32 {3, 41, 42, 43}
>  0: MAD TEMP[0].xyz, IN[1].xyzz, CONST[10].zzzz, CONST[10].wwww
>  1: MOV TEMP[1].xz, TEMP[0].xxzx
>  2: ADD TEMP[0].x, TEMP[0].yyyy, IMM[0].xxxx
>  3: MOV TEMP[1].y, TEMP[0].xxxx
>  4: MOV TEMP[0], IN[0]
>  5: MOV TEMP[2].xyz, TEMP[1].xyzx
>  6: UIF CONST[240].xxxx :0
>  7:   DP3 TEMP[3].x, IN[4].xyzz, IMM[0].yyyy
>  8:   ADD TEMP[3].x, IMM[0].yyyy, -TEMP[3].xxxx
>  9:   MUL TEMP[4], IN[3], IMM[0].zzzz
> 10:   F2I TEMP[4], TEMP[4]
> 11:   UMAD TEMP[5].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].yyyy
> 12:   UMAD TEMP[6].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].yyyy
> 13:   UMAD TEMP[7].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].yyyy
> 14:   UMAD TEMP[8].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].yyyy
> 15:   UARL ADDR[0].x, TEMP[8].xxxx
> 16:   MUL TEMP[8], CONST[ADDR[0].x], IN[4].xxxx
> 17:   UARL ADDR[0].x, TEMP[7].xxxx
> 18:   MAD TEMP[7], CONST[ADDR[0].x], IN[4].yyyy, TEMP[8]
> 19:   UARL ADDR[0].x, TEMP[6].xxxx
> 20:   MAD TEMP[6], CONST[ADDR[0].x], IN[4].zzzz, TEMP[7]
> 21:   UARL ADDR[0].x, TEMP[5].xxxx
> 22:   UARL ADDR[0].x, TEMP[5].xxxx
> 23:   MAD TEMP[5], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[6]
> 24:   UMAD TEMP[6].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].zzzz
> 25:   UMAD TEMP[7].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].zzzz
> 26:   UMAD TEMP[8].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].zzzz
> 27:   UMAD TEMP[9].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].zzzz
> 28:   UARL ADDR[0].x, TEMP[9].xxxx
> 29:   MUL TEMP[9], CONST[ADDR[0].x], IN[4].xxxx
> 30:   UARL ADDR[0].x, TEMP[8].xxxx
> 31:   MAD TEMP[8], CONST[ADDR[0].x], IN[4].yyyy, TEMP[9]
> 32:   UARL ADDR[0].x, TEMP[7].xxxx
> 33:   MAD TEMP[7], CONST[ADDR[0].x], IN[4].zzzz, TEMP[8]
> 34:   UARL ADDR[0].x, TEMP[6].xxxx
> 35:   UARL ADDR[0].x, TEMP[6].xxxx
> 36:   MAD TEMP[6], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[7]
> 37:   UMAD TEMP[7].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].wwww
> 38:   UMAD TEMP[8].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].wwww
> 39:   UMAD TEMP[9].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].wwww
> 40:   UMAD TEMP[4].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].wwww
> 41:   UARL ADDR[0].x, TEMP[4].xxxx
> 42:   MUL TEMP[4], CONST[ADDR[0].x], IN[4].xxxx
> 43:   UARL ADDR[0].x, TEMP[9].xxxx
> 44:   MAD TEMP[4], CONST[ADDR[0].x], IN[4].yyyy, TEMP[4]
> 45:   UARL ADDR[0].x, TEMP[8].xxxx
> 46:   MAD TEMP[4], CONST[ADDR[0].x], IN[4].zzzz, TEMP[4]
> 47:   UARL ADDR[0].x, TEMP[7].xxxx
> 48:   UARL ADDR[0].x, TEMP[7].xxxx
> 49:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[4]
> 50:   DP4 TEMP[4].x, IN[0], TEMP[5]
> 51:   DP4 TEMP[7].x, IN[0], TEMP[6]
> 52:   MOV TEMP[4].y, TEMP[7].xxxx
> 53:   DP4 TEMP[7].x, IN[0], TEMP[3]
> 54:   MOV TEMP[4].z, TEMP[7].xxxx
> 55:   MOV TEMP[0].xyz, TEMP[4].xyzx
> 56:   DP3 TEMP[4].x, TEMP[1].xyzz, TEMP[5].xyzz
> 57:   DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[6].xyzz
> 58:   MOV TEMP[4].y, TEMP[5].xxxx
> 59:   DP3 TEMP[1].x, TEMP[1].xyzz, TEMP[3].xyzz
> 60:   MOV TEMP[4].z, TEMP[1].xxxx
> 61:   MOV TEMP[2].xyz, TEMP[4].xyzx
> 62: ENDIF
> 63: DP4 TEMP[1].x, TEMP[0], CONST[0]
> 64: DP4 TEMP[3].x, TEMP[0], CONST[1]
> 65: MOV TEMP[1].y, TEMP[3].xxxx
> 66: DP4 TEMP[3].x, TEMP[0], CONST[2]
> 67: MOV TEMP[1].z, TEMP[3].xxxx
> 68: DP4 TEMP[3].x, TEMP[0], CONST[3]
> 69: MOV TEMP[1].w, TEMP[3].xxxx
> 70: DP3 TEMP[3].x, TEMP[2].xyzz, CONST[4].xyzz
> 71: DP3 TEMP[4].x, TEMP[2].xyzz, CONST[5].xyzz
> 72: DP3 TEMP[2].x, TEMP[2].xyzz, CONST[6].xyzz
> 73: MOV TEMP[3].z, TEMP[2].xxxx
> 74: MOV TEMP[2].xz, TEMP[3].xxzx
> 75: MOV TEMP[2].y, -TEMP[4].xxxx
> 76: DP4 TEMP[0].x, TEMP[0], CONST[9]
> 77: ADD TEMP[0].x, TEMP[0].xxxx, IMM[0].wwww
> 78: MOV TEMP[2].w, TEMP[0].xxxx
> 79: DP4 TEMP[0].x, IN[2], CONST[7]
> 80: DP4 TEMP[3].x, IN[2], CONST[8]
> 81: MOV TEMP[0].y, TEMP[3].xxxx
> 82: MOV TEMP[0].xy, TEMP[0].xyxx
> 83: MOV TEMP[0].zw, IN[5].yyxy
> 84: MAD TEMP[3], IN[6].zyxw, CONST[10].xxxx, CONST[10].yyyy
> 85: MOV TEMP[4].w, TEMP[3].wwww
> 86: MUL TEMP[4].xyz, TEMP[3].xyzz, TEMP[3].xyzz
> 87: LRP TEMP[4].xyz, TEMP[3].wwww, TEMP[4].xyzz, IMM[0].yyyy
> 88: MOV OUT[2], TEMP[0]
> 89: MOV OUT[3], TEMP[2]
> 90: MOV OUT[0], TEMP[1]
> 91: MOV OUT[4], TEMP[4]
> 92: MOV OUT[1], TEMP[1]
> 93: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 3840)
>  %53 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %54 = load <16 x i8> addrspace(2)* %53, !tbaa !0
>  %55 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %54, i32 0, i32 %5)
>  %56 = extractelement <4 x float> %55, i32 0
>  %57 = extractelement <4 x float> %55, i32 1
>  %58 = extractelement <4 x float> %55, i32 2
>  %59 = extractelement <4 x float> %55, i32 3
>  %60 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
>  %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %5)
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = extractelement <4 x float> %62, i32 1
>  %65 = extractelement <4 x float> %62, i32 2
>  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
>  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
>  %69 = extractelement <4 x float> %68, i32 0
>  %70 = extractelement <4 x float> %68, i32 1
>  %71 = extractelement <4 x float> %68, i32 2
>  %72 = extractelement <4 x float> %68, i32 3
>  %73 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %74 = load <16 x i8> addrspace(2)* %73, !tbaa !0
>  %75 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %74, i32 0, i32 %5)
>  %76 = extractelement <4 x float> %75, i32 0
>  %77 = extractelement <4 x float> %75, i32 1
>  %78 = extractelement <4 x float> %75, i32 2
>  %79 = extractelement <4 x float> %75, i32 3
>  %80 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %81 = load <16 x i8> addrspace(2)* %80, !tbaa !0
>  %82 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %81, i32 0, i32 %5)
>  %83 = extractelement <4 x float> %82, i32 0
>  %84 = extractelement <4 x float> %82, i32 1
>  %85 = extractelement <4 x float> %82, i32 2
>  %86 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %87 = load <16 x i8> addrspace(2)* %86, !tbaa !0
>  %88 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %87, i32 0, i32 %5)
>  %89 = extractelement <4 x float> %88, i32 0
>  %90 = extractelement <4 x float> %88, i32 1
>  %91 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
>  %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0
>  %93 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %92, i32 0, i32 %5)
>  %94 = extractelement <4 x float> %93, i32 0
>  %95 = extractelement <4 x float> %93, i32 1
>  %96 = extractelement <4 x float> %93, i32 2
>  %97 = extractelement <4 x float> %93, i32 3
>  %98 = fmul float %63, %50
>  %99 = fadd float %98, %51
>  %100 = fmul float %64, %50
>  %101 = fadd float %100, %51
>  %102 = fmul float %65, %50
>  %103 = fadd float %102, %51
>  %104 = fadd float %101, 0x3F50624DE0000000
>  %105 = bitcast float %52 to i32
>  %106 = icmp ne i32 %105, 0
>  br i1 %106, label %IF, label %ENDIF
>
>IF:                                               ; preds = %main_body
>  %107 = fmul float %83, 1.000000e+00
>  %108 = fmul float %84, 1.000000e+00
>  %109 = fadd float %108, %107
>  %110 = fmul float %85, 1.000000e+00
>  %111 = fadd float %109, %110
>  %112 = fsub float -0.000000e+00, %111
>  %113 = fadd float 1.000000e+00, %112
>  %114 = fmul float %76, 0x406FE051E0000000
>  %115 = fmul float %77, 0x406FE051E0000000
>  %116 = fmul float %78, 0x406FE051E0000000
>  %117 = fmul float %79, 0x406FE051E0000000
>  %118 = fptosi float %114 to i32
>  %119 = fptosi float %115 to i32
>  %120 = fptosi float %116 to i32
>  %121 = fptosi float %117 to i32
>  %122 = bitcast i32 %118 to float
>  %123 = bitcast i32 %119 to float
>  %124 = bitcast i32 %120 to float
>  %125 = bitcast i32 %121 to float
>  %126 = bitcast float %125 to i32
>  %127 = mul i32 %126, 3
>  %128 = add i32 %127, 41
>  %129 = bitcast i32 %128 to float
>  %130 = bitcast float %124 to i32
>  %131 = mul i32 %130, 3
>  %132 = add i32 %131, 41
>  %133 = bitcast i32 %132 to float
>  %134 = bitcast float %123 to i32
>  %135 = mul i32 %134, 3
>  %136 = add i32 %135, 41
>  %137 = bitcast i32 %136 to float
>  %138 = bitcast float %122 to i32
>  %139 = mul i32 %138, 3
>  %140 = add i32 %139, 41
>  %141 = bitcast i32 %140 to float
>  %142 = bitcast float %141 to i32
>  %143 = shl i32 %142, 4
>  %144 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %143)
>  %145 = fmul float %144, %83
>  %146 = shl i32 %142, 4
>  %147 = add i32 %146, 4
>  %148 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %147)
>  %149 = fmul float %148, %83
>  %150 = shl i32 %142, 4
>  %151 = add i32 %150, 8
>  %152 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %151)
>  %153 = fmul float %152, %83
>  %154 = shl i32 %142, 4
>  %155 = add i32 %154, 12
>  %156 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %155)
>  %157 = fmul float %156, %83
>  %158 = bitcast float %137 to i32
>  %159 = shl i32 %158, 4
>  %160 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %159)
>  %161 = fmul float %160, %84
>  %162 = fadd float %161, %145
>  %163 = shl i32 %158, 4
>  %164 = add i32 %163, 4
>  %165 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %164)
>  %166 = fmul float %165, %84
>  %167 = fadd float %166, %149
>  %168 = shl i32 %158, 4
>  %169 = add i32 %168, 8
>  %170 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %169)
>  %171 = fmul float %170, %84
>  %172 = fadd float %171, %153
>  %173 = shl i32 %158, 4
>  %174 = add i32 %173, 12
>  %175 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %174)
>  %176 = fmul float %175, %84
>  %177 = fadd float %176, %157
>  %178 = bitcast float %133 to i32
>  %179 = shl i32 %178, 4
>  %180 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %179)
>  %181 = fmul float %180, %85
>  %182 = fadd float %181, %162
>  %183 = shl i32 %178, 4
>  %184 = add i32 %183, 4
>  %185 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %184)
>  %186 = fmul float %185, %85
>  %187 = fadd float %186, %167
>  %188 = shl i32 %178, 4
>  %189 = add i32 %188, 8
>  %190 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %189)
>  %191 = fmul float %190, %85
>  %192 = fadd float %191, %172
>  %193 = shl i32 %178, 4
>  %194 = add i32 %193, 12
>  %195 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %194)
>  %196 = fmul float %195, %85
>  %197 = fadd float %196, %177
>  %198 = bitcast float %129 to i32
>  %199 = shl i32 %198, 4
>  %200 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %199)
>  %201 = fmul float %200, %113
>  %202 = fadd float %201, %182
>  %203 = shl i32 %198, 4
>  %204 = add i32 %203, 4
>  %205 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %204)
>  %206 = fmul float %205, %113
>  %207 = fadd float %206, %187
>  %208 = shl i32 %198, 4
>  %209 = add i32 %208, 8
>  %210 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %209)
>  %211 = fmul float %210, %113
>  %212 = fadd float %211, %192
>  %213 = shl i32 %198, 4
>  %214 = add i32 %213, 12
>  %215 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %214)
>  %216 = fmul float %215, %113
>  %217 = fadd float %216, %197
>  %218 = bitcast float %125 to i32
>  %219 = mul i32 %218, 3
>  %220 = add i32 %219, 42
>  %221 = bitcast i32 %220 to float
>  %222 = bitcast float %124 to i32
>  %223 = mul i32 %222, 3
>  %224 = add i32 %223, 42
>  %225 = bitcast i32 %224 to float
>  %226 = bitcast float %123 to i32
>  %227 = mul i32 %226, 3
>  %228 = add i32 %227, 42
>  %229 = bitcast i32 %228 to float
>  %230 = bitcast float %122 to i32
>  %231 = mul i32 %230, 3
>  %232 = add i32 %231, 42
>  %233 = bitcast i32 %232 to float
>  %234 = bitcast float %233 to i32
>  %235 = shl i32 %234, 4
>  %236 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %235)
>  %237 = fmul float %236, %83
>  %238 = shl i32 %234, 4
>  %239 = add i32 %238, 4
>  %240 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %239)
>  %241 = fmul float %240, %83
>  %242 = shl i32 %234, 4
>  %243 = add i32 %242, 8
>  %244 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %243)
>  %245 = fmul float %244, %83
>  %246 = shl i32 %234, 4
>  %247 = add i32 %246, 12
>  %248 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %247)
>  %249 = fmul float %248, %83
>  %250 = bitcast float %229 to i32
>  %251 = shl i32 %250, 4
>  %252 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %251)
>  %253 = fmul float %252, %84
>  %254 = fadd float %253, %237
>  %255 = shl i32 %250, 4
>  %256 = add i32 %255, 4
>  %257 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %256)
>  %258 = fmul float %257, %84
>  %259 = fadd float %258, %241
>  %260 = shl i32 %250, 4
>  %261 = add i32 %260, 8
>  %262 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %261)
>  %263 = fmul float %262, %84
>  %264 = fadd float %263, %245
>  %265 = shl i32 %250, 4
>  %266 = add i32 %265, 12
>  %267 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %266)
>  %268 = fmul float %267, %84
>  %269 = fadd float %268, %249
>  %270 = bitcast float %225 to i32
>  %271 = shl i32 %270, 4
>  %272 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %271)
>  %273 = fmul float %272, %85
>  %274 = fadd float %273, %254
>  %275 = shl i32 %270, 4
>  %276 = add i32 %275, 4
>  %277 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %276)
>  %278 = fmul float %277, %85
>  %279 = fadd float %278, %259
>  %280 = shl i32 %270, 4
>  %281 = add i32 %280, 8
>  %282 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %281)
>  %283 = fmul float %282, %85
>  %284 = fadd float %283, %264
>  %285 = shl i32 %270, 4
>  %286 = add i32 %285, 12
>  %287 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %286)
>  %288 = fmul float %287, %85
>  %289 = fadd float %288, %269
>  %290 = bitcast float %221 to i32
>  %291 = shl i32 %290, 4
>  %292 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %291)
>  %293 = fmul float %292, %113
>  %294 = fadd float %293, %274
>  %295 = shl i32 %290, 4
>  %296 = add i32 %295, 4
>  %297 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %296)
>  %298 = fmul float %297, %113
>  %299 = fadd float %298, %279
>  %300 = shl i32 %290, 4
>  %301 = add i32 %300, 8
>  %302 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %301)
>  %303 = fmul float %302, %113
>  %304 = fadd float %303, %284
>  %305 = shl i32 %290, 4
>  %306 = add i32 %305, 12
>  %307 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %306)
>  %308 = fmul float %307, %113
>  %309 = fadd float %308, %289
>  %310 = bitcast float %125 to i32
>  %311 = mul i32 %310, 3
>  %312 = add i32 %311, 43
>  %313 = bitcast i32 %312 to float
>  %314 = bitcast float %124 to i32
>  %315 = mul i32 %314, 3
>  %316 = add i32 %315, 43
>  %317 = bitcast i32 %316 to float
>  %318 = bitcast float %123 to i32
>  %319 = mul i32 %318, 3
>  %320 = add i32 %319, 43
>  %321 = bitcast i32 %320 to float
>  %322 = bitcast float %122 to i32
>  %323 = mul i32 %322, 3
>  %324 = add i32 %323, 43
>  %325 = bitcast i32 %324 to float
>  %326 = bitcast float %325 to i32
>  %327 = shl i32 %326, 4
>  %328 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %327)
>  %329 = fmul float %328, %83
>  %330 = shl i32 %326, 4
>  %331 = add i32 %330, 4
>  %332 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %331)
>  %333 = fmul float %332, %83
>  %334 = shl i32 %326, 4
>  %335 = add i32 %334, 8
>  %336 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %335)
>  %337 = fmul float %336, %83
>  %338 = shl i32 %326, 4
>  %339 = add i32 %338, 12
>  %340 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %339)
>  %341 = fmul float %340, %83
>  %342 = bitcast float %321 to i32
>  %343 = shl i32 %342, 4
>  %344 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %343)
>  %345 = fmul float %344, %84
>  %346 = fadd float %345, %329
>  %347 = shl i32 %342, 4
>  %348 = add i32 %347, 4
>  %349 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %348)
>  %350 = fmul float %349, %84
>  %351 = fadd float %350, %333
>  %352 = shl i32 %342, 4
>  %353 = add i32 %352, 8
>  %354 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %353)
>  %355 = fmul float %354, %84
>  %356 = fadd float %355, %337
>  %357 = shl i32 %342, 4
>  %358 = add i32 %357, 12
>  %359 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %358)
>  %360 = fmul float %359, %84
>  %361 = fadd float %360, %341
>  %362 = bitcast float %317 to i32
>  %363 = shl i32 %362, 4
>  %364 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %363)
>  %365 = fmul float %364, %85
>  %366 = fadd float %365, %346
>  %367 = shl i32 %362, 4
>  %368 = add i32 %367, 4
>  %369 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %368)
>  %370 = fmul float %369, %85
>  %371 = fadd float %370, %351
>  %372 = shl i32 %362, 4
>  %373 = add i32 %372, 8
>  %374 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %373)
>  %375 = fmul float %374, %85
>  %376 = fadd float %375, %356
>  %377 = shl i32 %362, 4
>  %378 = add i32 %377, 12
>  %379 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %378)
>  %380 = fmul float %379, %85
>  %381 = fadd float %380, %361
>  %382 = bitcast float %313 to i32
>  %383 = shl i32 %382, 4
>  %384 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %383)
>  %385 = fmul float %384, %113
>  %386 = fadd float %385, %366
>  %387 = shl i32 %382, 4
>  %388 = add i32 %387, 4
>  %389 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %388)
>  %390 = fmul float %389, %113
>  %391 = fadd float %390, %371
>  %392 = shl i32 %382, 4
>  %393 = add i32 %392, 8
>  %394 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %393)
>  %395 = fmul float %394, %113
>  %396 = fadd float %395, %376
>  %397 = shl i32 %382, 4
>  %398 = add i32 %397, 12
>  %399 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %398)
>  %400 = fmul float %399, %113
>  %401 = fadd float %400, %381
>  %402 = fmul float %56, %202
>  %403 = fmul float %57, %207
>  %404 = fadd float %402, %403
>  %405 = fmul float %58, %212
>  %406 = fadd float %404, %405
>  %407 = fmul float %59, %217
>  %408 = fadd float %406, %407
>  %409 = fmul float %56, %294
>  %410 = fmul float %57, %299
>  %411 = fadd float %409, %410
>  %412 = fmul float %58, %304
>  %413 = fadd float %411, %412
>  %414 = fmul float %59, %309
>  %415 = fadd float %413, %414
>  %416 = fmul float %56, %386
>  %417 = fmul float %57, %391
>  %418 = fadd float %416, %417
>  %419 = fmul float %58, %396
>  %420 = fadd float %418, %419
>  %421 = fmul float %59, %401
>  %422 = fadd float %420, %421
>  %423 = fmul float %99, %202
>  %424 = fmul float %104, %207
>  %425 = fadd float %424, %423
>  %426 = fmul float %103, %212
>  %427 = fadd float %425, %426
>  %428 = fmul float %99, %294
>  %429 = fmul float %104, %299
>  %430 = fadd float %429, %428
>  %431 = fmul float %103, %304
>  %432 = fadd float %430, %431
>  %433 = fmul float %99, %386
>  %434 = fmul float %104, %391
>  %435 = fadd float %434, %433
>  %436 = fmul float %103, %396
>  %437 = fadd float %435, %436
>  br label %ENDIF
>
>ENDIF:                                            ; preds = %main_body, %IF
>  %temp.0 = phi float [ %408, %IF ], [ %56, %main_body ]
>  %temp1.0 = phi float [ %415, %IF ], [ %57, %main_body ]
>  %temp2.0 = phi float [ %422, %IF ], [ %58, %main_body ]
>  %temp8.0 = phi float [ %427, %IF ], [ %99, %main_body ]
>  %temp9.0 = phi float [ %432, %IF ], [ %104, %main_body ]
>  %temp10.0 = phi float [ %437, %IF ], [ %103, %main_body ]
>  %438 = fmul float %temp.0, %11
>  %439 = fmul float %temp1.0, %12
>  %440 = fadd float %438, %439
>  %441 = fmul float %temp2.0, %13
>  %442 = fadd float %440, %441
>  %443 = fmul float %59, %14
>  %444 = fadd float %442, %443
>  %445 = fmul float %temp.0, %15
>  %446 = fmul float %temp1.0, %16
>  %447 = fadd float %445, %446
>  %448 = fmul float %temp2.0, %17
>  %449 = fadd float %447, %448
>  %450 = fmul float %59, %18
>  %451 = fadd float %449, %450
>  %452 = fmul float %temp.0, %19
>  %453 = fmul float %temp1.0, %20
>  %454 = fadd float %452, %453
>  %455 = fmul float %temp2.0, %21
>  %456 = fadd float %454, %455
>  %457 = fmul float %59, %22
>  %458 = fadd float %456, %457
>  %459 = fmul float %temp.0, %23
>  %460 = fmul float %temp1.0, %24
>  %461 = fadd float %459, %460
>  %462 = fmul float %temp2.0, %25
>  %463 = fadd float %461, %462
>  %464 = fmul float %59, %26
>  %465 = fadd float %463, %464
>  %466 = fmul float %temp8.0, %27
>  %467 = fmul float %temp9.0, %28
>  %468 = fadd float %467, %466
>  %469 = fmul float %temp10.0, %29
>  %470 = fadd float %468, %469
>  %471 = fmul float %temp8.0, %30
>  %472 = fmul float %temp9.0, %31
>  %473 = fadd float %472, %471
>  %474 = fmul float %temp10.0, %32
>  %475 = fadd float %473, %474
>  %476 = fmul float %temp8.0, %33
>  %477 = fmul float %temp9.0, %34
>  %478 = fadd float %477, %476
>  %479 = fmul float %temp10.0, %35
>  %480 = fadd float %478, %479
>  %481 = fsub float -0.000000e+00, %475
>  %482 = fmul float %temp.0, %44
>  %483 = fmul float %temp1.0, %45
>  %484 = fadd float %482, %483
>  %485 = fmul float %temp2.0, %46
>  %486 = fadd float %484, %485
>  %487 = fmul float %59, %47
>  %488 = fadd float %486, %487
>  %489 = fadd float %488, 0xBFB99999A0000000
>  %490 = fmul float %69, %36
>  %491 = fmul float %70, %37
>  %492 = fadd float %490, %491
>  %493 = fmul float %71, %38
>  %494 = fadd float %492, %493
>  %495 = fmul float %72, %39
>  %496 = fadd float %494, %495
>  %497 = fmul float %69, %40
>  %498 = fmul float %70, %41
>  %499 = fadd float %497, %498
>  %500 = fmul float %71, %42
>  %501 = fadd float %499, %500
>  %502 = fmul float %72, %43
>  %503 = fadd float %501, %502
>  %504 = fmul float %96, %48
>  %505 = fadd float %504, %49
>  %506 = fmul float %95, %48
>  %507 = fadd float %506, %49
>  %508 = fmul float %94, %48
>  %509 = fadd float %508, %49
>  %510 = fmul float %97, %48
>  %511 = fadd float %510, %49
>  %512 = fmul float %505, %505
>  %513 = fmul float %507, %507
>  %514 = fmul float %509, %509
>  %515 = call float @llvm.AMDGPU.lrp(float %511, float %512, float 1.000000e+00)
>  %516 = call float @llvm.AMDGPU.lrp(float %511, float %513, float 1.000000e+00)
>  %517 = call float @llvm.AMDGPU.lrp(float %511, float %514, float 1.000000e+00)
>  %518 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
>  %519 = load <16 x i8> addrspace(2)* %518, !tbaa !0
>  %520 = call float @llvm.SI.load.const(<16 x i8> %519, i32 0)
>  %521 = fmul float %520, %444
>  %522 = call float @llvm.SI.load.const(<16 x i8> %519, i32 4)
>  %523 = fmul float %522, %451
>  %524 = fadd float %521, %523
>  %525 = call float @llvm.SI.load.const(<16 x i8> %519, i32 8)
>  %526 = fmul float %525, %458
>  %527 = fadd float %524, %526
>  %528 = call float @llvm.SI.load.const(<16 x i8> %519, i32 12)
>  %529 = fmul float %528, %465
>  %530 = fadd float %527, %529
>  %531 = call float @llvm.SI.load.const(<16 x i8> %519, i32 16)
>  %532 = fmul float %531, %444
>  %533 = call float @llvm.SI.load.const(<16 x i8> %519, i32 20)
>  %534 = fmul float %533, %451
>  %535 = fadd float %532, %534
>  %536 = call float @llvm.SI.load.const(<16 x i8> %519, i32 24)
>  %537 = fmul float %536, %458
>  %538 = fadd float %535, %537
>  %539 = call float @llvm.SI.load.const(<16 x i8> %519, i32 28)
>  %540 = fmul float %539, %465
>  %541 = fadd float %538, %540
>  %542 = call float @llvm.SI.load.const(<16 x i8> %519, i32 32)
>  %543 = fmul float %542, %444
>  %544 = call float @llvm.SI.load.const(<16 x i8> %519, i32 36)
>  %545 = fmul float %544, %451
>  %546 = fadd float %543, %545
>  %547 = call float @llvm.SI.load.const(<16 x i8> %519, i32 40)
>  %548 = fmul float %547, %458
>  %549 = fadd float %546, %548
>  %550 = call float @llvm.SI.load.const(<16 x i8> %519, i32 44)
>  %551 = fmul float %550, %465
>  %552 = fadd float %549, %551
>  %553 = call float @llvm.SI.load.const(<16 x i8> %519, i32 48)
>  %554 = fmul float %553, %444
>  %555 = call float @llvm.SI.load.const(<16 x i8> %519, i32 52)
>  %556 = fmul float %555, %451
>  %557 = fadd float %554, %556
>  %558 = call float @llvm.SI.load.const(<16 x i8> %519, i32 56)
>  %559 = fmul float %558, %458
>  %560 = fadd float %557, %559
>  %561 = call float @llvm.SI.load.const(<16 x i8> %519, i32 60)
>  %562 = fmul float %561, %465
>  %563 = fadd float %560, %562
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %496, float %503, float %89, float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %470, float %481, float %480, float %489)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %515, float %516, float %517, float %511)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %444, float %451, float %458, float %465)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 13, i32 0, float %530, float %541, float %552, float %563)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.lrp(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg77, %SGPR6_SGPR7 in %vreg80, %VGPR0 in %vreg82
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%65](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR23_VGPR24_VGPR25_VGPR26<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 43; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR27<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
>	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR28<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR25, %VGPR28, %VGPR27, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR23, %VGPR28, %VGPR27, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 24; mem:LD16[%106](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%99](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%VGPR10_VGPR11_VGPR12_VGPR13<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 16; mem:LD16[%91](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%VGPR18_VGPR19_VGPR20_VGPR21<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%82](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%VGPR60_VGPR61_VGPR62_VGPR63<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%73](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%VGPR14_VGPR15_VGPR16_VGPR17<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%56](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR24, %VGPR28<kill>, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR23_VGPR24_VGPR25_VGPR26<imp-use,kill>
>	%VGPR59<def> = V_ADD_F32_e32 1.000000e-03, %VGPR0<kill>, %EXEC<imp-use>
>	%SGPR2<def> = S_MOV_B32 3840
>	%SGPR2<def> = S_BUFFER_LOAD_DWORD_SGPR %SGPR8_SGPR9_SGPR10_SGPR11, %SGPR2<kill>; mem:LD4[<unknown>]
>	S_WAITCNT 112
>	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %SGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41; mem:LD4[<unknown>]
>	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40; mem:LD4[<unknown>]
>	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 39; mem:LD4[<unknown>]
>	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 38; mem:LD4[<unknown>]
>	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 37; mem:LD4[<unknown>]
>	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 36; mem:LD4[<unknown>]
>	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 35; mem:LD4[<unknown>]
>	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34; mem:LD4[<unknown>]
>	%SGPR16<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33; mem:LD4[<unknown>]
>	%SGPR17<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32; mem:LD4[<unknown>]
>	%SGPR18<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31; mem:LD4[<unknown>]
>	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30; mem:LD4[<unknown>]
>	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29; mem:LD4[<unknown>]
>	%SGPR21<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28; mem:LD4[<unknown>]
>	%SGPR22<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26; mem:LD4[<unknown>]
>	%SGPR23<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25; mem:LD4[<unknown>]
>	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24; mem:LD4[<unknown>]
>	%SGPR25<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22; mem:LD4[<unknown>]
>	%SGPR26<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21; mem:LD4[<unknown>]
>	%SGPR27<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20; mem:LD4[<unknown>]
>	%SGPR28<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18; mem:LD4[<unknown>]
>	%SGPR29<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17; mem:LD4[<unknown>]
>	%SGPR30<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16; mem:LD4[<unknown>]
>	%SGPR31<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 15; mem:LD4[<unknown>]
>	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 14; mem:LD4[<unknown>]
>	%SGPR33<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 13; mem:LD4[<unknown>]
>	%SGPR34<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 12; mem:LD4[<unknown>]
>	%SGPR35<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 11; mem:LD4[<unknown>]
>	%SGPR36<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 10; mem:LD4[<unknown>]
>	%SGPR37<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 9; mem:LD4[<unknown>]
>	%SGPR38<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 8; mem:LD4[<unknown>]
>	%SGPR39<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 7; mem:LD4[<unknown>]
>	%SGPR40<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 6; mem:LD4[<unknown>]
>	%SGPR41<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 5; mem:LD4[<unknown>]
>	%SGPR42<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 4; mem:LD4[<unknown>]
>	%SGPR43<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 3; mem:LD4[<unknown>]
>	%SGPR44<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2; mem:LD4[<unknown>]
>	%SGPR45<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1; mem:LD4[<unknown>]
>	%SGPR46<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_MOV_B32_e32 %SGPR6<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MOV_B32_e32 %SGPR7<kill>, %EXEC<imp-use>
>	%VGPR33<def> = V_MOV_B32_e32 %SGPR12<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_MOV_B32_e32 %SGPR13<kill>, %EXEC<imp-use>
>	%VGPR46<def> = V_MOV_B32_e32 %SGPR14<kill>, %EXEC<imp-use>
>	%VGPR50<def> = V_MOV_B32_e32 %SGPR15<kill>, %EXEC<imp-use>
>	%VGPR57<def> = V_MOV_B32_e32 %SGPR16<kill>, %EXEC<imp-use>
>	%VGPR56<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>
>	%VGPR45<def> = V_MOV_B32_e32 %SGPR18<kill>, %EXEC<imp-use>
>	%VGPR49<def> = V_MOV_B32_e32 %SGPR19<kill>, %EXEC<imp-use>
>	%VGPR55<def> = V_MOV_B32_e32 %SGPR20<kill>, %EXEC<imp-use>
>	%VGPR54<def> = V_MOV_B32_e32 %SGPR21<kill>, %EXEC<imp-use>
>	%VGPR44<def> = V_MOV_B32_e32 %SGPR22<kill>, %EXEC<imp-use>
>	%VGPR48<def> = V_MOV_B32_e32 %SGPR23<kill>, %EXEC<imp-use>
>	%VGPR52<def> = V_MOV_B32_e32 %SGPR24<kill>, %EXEC<imp-use>
>	%VGPR42<def> = V_MOV_B32_e32 %SGPR25<kill>, %EXEC<imp-use>
>	%VGPR43<def> = V_MOV_B32_e32 %SGPR26<kill>, %EXEC<imp-use>
>	%VGPR47<def> = V_MOV_B32_e32 %SGPR27<kill>, %EXEC<imp-use>
>	%VGPR51<def> = V_MOV_B32_e32 %SGPR28<kill>, %EXEC<imp-use>
>	%VGPR53<def> = V_MOV_B32_e32 %SGPR29<kill>, %EXEC<imp-use>
>	%VGPR58<def> = V_MOV_B32_e32 %SGPR30<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MOV_B32_e32 %SGPR31<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MOV_B32_e32 %SGPR32<kill>, %EXEC<imp-use>
>	%VGPR41<def> = V_MOV_B32_e32 %SGPR33<kill>, %EXEC<imp-use>
>	%VGPR40<def> = V_MOV_B32_e32 %SGPR34<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MOV_B32_e32 %SGPR35<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_MOV_B32_e32 %SGPR36<kill>, %EXEC<imp-use>
>	%VGPR39<def> = V_MOV_B32_e32 %SGPR37<kill>, %EXEC<imp-use>
>	%VGPR38<def> = V_MOV_B32_e32 %SGPR38<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_MOV_B32_e32 %SGPR39<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MOV_B32_e32 %SGPR40<kill>, %EXEC<imp-use>
>	%VGPR37<def> = V_MOV_B32_e32 %SGPR41<kill>, %EXEC<imp-use>
>	%VGPR36<def> = V_MOV_B32_e32 %SGPR42<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MOV_B32_e32 %SGPR43<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MOV_B32_e32 %SGPR44<kill>, %EXEC<imp-use>
>	%VGPR35<def> = V_MOV_B32_e32 %SGPR45<kill>, %EXEC<imp-use>
>	%VGPR34<def> = V_MOV_B32_e32 %SGPR46<kill>, %EXEC<imp-use>
>	%VGPR66<def> = V_MOV_B32_e32 %VGPR5, %EXEC<imp-use>
>	%VGPR65<def> = V_MOV_B32_e32 %VGPR6, %EXEC<imp-use>
>	%VGPR64<def> = V_MOV_B32_e32 %VGPR7, %EXEC<imp-use>
>	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
>	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
>	S_CBRANCH_EXECZ <BB#2>, %EXEC
>    Successors according to CFG: BB#1(16) BB#2(16)
>
>BB#1: derived from LLVM BB %IF
>    Live Ins: %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR34 %VGPR35 %VGPR28 %VGPR23 %VGPR36 %VGPR37 %VGPR29 %VGPR24 %VGPR38 %VGPR39 %VGPR30 %VGPR25 %VGPR40 %VGPR41 %VGPR31 %VGPR26 %VGPR58 %VGPR53 %VGPR51 %VGPR47 %VGPR43 %VGPR42 %VGPR52 %VGPR48 %VGPR44 %VGPR54 %VGPR55 %VGPR49 %VGPR45 %VGPR56 %VGPR57 %VGPR50 %VGPR46 %VGPR32 %VGPR33 %VGPR27 %VGPR0 %SGPR2 %SGPR3 %SGPR0_SGPR1 %VGPR1_VGPR2_VGPR3_VGPR4 %VGPR10_VGPR11_VGPR12_VGPR13 %VGPR18_VGPR19_VGPR20_VGPR21 %VGPR60_VGPR61_VGPR62_VGPR63 %VGPR14_VGPR15_VGPR16_VGPR17 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR4_SGPR5 %VGPR9 %VGPR59 %VGPR22
>    Predecessors according to CFG: BB#0
>	%VGPR64<def> = V_MOV_B32_e32 2.550100e+02, %EXEC<imp-use>
>	%VGPR65<def> = V_MUL_F32_e32 %VGPR61, %VGPR64, %EXEC<imp-use>
>	%VGPR65<def> = V_CVT_I32_F32_e32 %VGPR65<kill>, %EXEC<imp-use>
>	%VGPR65<def> = V_MUL_LO_I32 %VGPR65<kill>, 3, 0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR66<def> = V_ADD_I32_e32 43, %VGPR65, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR66<def> = V_LSHLREV_B32_e32 4, %VGPR66<kill>, %EXEC<imp-use>
>	%VGPR67<def> = V_OR_B32_e32 4, %VGPR66, %EXEC<imp-use>
>	%VGPR67<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR67<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR68<def> = V_MUL_F32_e32 %VGPR60, %VGPR64, %EXEC<imp-use>
>	%VGPR68<def> = V_CVT_I32_F32_e32 %VGPR68<kill>, %EXEC<imp-use>
>	%VGPR68<def> = V_MUL_LO_I32 %VGPR68<kill>, 3, 0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR69<def> = V_ADD_I32_e32 43, %VGPR68, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR69<def> = V_LSHLREV_B32_e32 4, %VGPR69<kill>, %EXEC<imp-use>
>	%VGPR70<def> = V_OR_B32_e32 4, %VGPR69, %EXEC<imp-use>
>	%VGPR70<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR70<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR70<def> = V_MUL_F32_e32 %VGPR18, %VGPR70<kill>, %EXEC<imp-use>
>	%VGPR67<def> = V_MAD_F32 %VGPR67<kill>, %VGPR19, %VGPR70<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR70<def> = V_MUL_F32_e32 %VGPR62, %VGPR64, %EXEC<imp-use>
>	%VGPR70<def> = V_CVT_I32_F32_e32 %VGPR70<kill>, %EXEC<imp-use>
>	%VGPR70<def> = V_MUL_LO_I32 %VGPR70<kill>, 3, 0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR71<def> = V_ADD_I32_e32 43, %VGPR70, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR71<def> = V_LSHLREV_B32_e32 4, %VGPR71<kill>, %EXEC<imp-use>
>	%VGPR72<def> = V_OR_B32_e32 4, %VGPR71, %EXEC<imp-use>
>	%VGPR72<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR72<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR67<def> = V_MAD_F32 %VGPR72<kill>, %VGPR20, %VGPR67<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR60<def> = V_MUL_F32_e32 %VGPR63, %VGPR64<kill>, %EXEC<imp-use>, %VGPR60_VGPR61_VGPR62_VGPR63<imp-use,kill>
>	%VGPR60<def> = V_CVT_I32_F32_e32 %VGPR60<kill>, %EXEC<imp-use>
>	%VGPR60<def> = V_MUL_LO_I32 %VGPR60<kill>, 3, 0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR61<def> = V_ADD_I32_e32 43, %VGPR60, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR61<def> = V_LSHLREV_B32_e32 4, %VGPR61<kill>, %EXEC<imp-use>
>	%VGPR62<def> = V_OR_B32_e32 4, %VGPR61, %EXEC<imp-use>
>	%VGPR62<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR62<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR63<def> = V_ADD_F32_e64 %VGPR19, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR63<def> = V_ADD_F32_e32 %VGPR20, %VGPR63<kill>, %EXEC<imp-use>
>	%VGPR63<def> = V_SUB_F32_e32 1.000000e+00, %VGPR63<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR62<def> = V_MAD_F32 %VGPR62<kill>, %VGPR63, %VGPR67<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR64<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR66, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR67<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR69, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR67<def> = V_MUL_F32_e32 %VGPR18, %VGPR67<kill>, %EXEC<imp-use>
>	%VGPR64<def> = V_MAD_F32 %VGPR64<kill>, %VGPR19, %VGPR67<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR67<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR71, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR64<def> = V_MAD_F32 %VGPR67<kill>, %VGPR20, %VGPR64<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR67<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR61, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR64<def> = V_MAD_F32 %VGPR67<kill>, %VGPR63, %VGPR64<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR67<def> = V_MUL_F32_e32 %VGPR9, %VGPR64, %EXEC<imp-use>
>	%VGPR67<def> = V_MAD_F32 %VGPR59, %VGPR62, %VGPR67<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR72<def> = V_OR_B32_e32 8, %VGPR66, %EXEC<imp-use>
>	%VGPR72<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR72<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR73<def> = V_OR_B32_e32 8, %VGPR69, %EXEC<imp-use>
>	%VGPR73<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR73<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR73<def> = V_MUL_F32_e32 %VGPR18, %VGPR73<kill>, %EXEC<imp-use>
>	%VGPR72<def> = V_MAD_F32 %VGPR72<kill>, %VGPR19, %VGPR73<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR73<def> = V_OR_B32_e32 8, %VGPR71, %EXEC<imp-use>
>	%VGPR73<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR73<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR72<def> = V_MAD_F32 %VGPR73<kill>, %VGPR20, %VGPR72<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR73<def> = V_OR_B32_e32 8, %VGPR61, %EXEC<imp-use>
>	%VGPR73<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR73<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR72<def> = V_MAD_F32 %VGPR73<kill>, %VGPR63, %VGPR72<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR67<def> = V_MAD_F32 %VGPR22, %VGPR72, %VGPR67<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR73<def> = V_ADD_I32_e32 42, %VGPR65, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR73<def> = V_LSHLREV_B32_e32 4, %VGPR73<kill>, %EXEC<imp-use>
>	%VGPR74<def> = V_OR_B32_e32 4, %VGPR73, %EXEC<imp-use>
>	%VGPR74<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR74<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR75<def> = V_ADD_I32_e32 42, %VGPR68, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR75<def> = V_LSHLREV_B32_e32 4, %VGPR75<kill>, %EXEC<imp-use>
>	%VGPR76<def> = V_OR_B32_e32 4, %VGPR75, %EXEC<imp-use>
>	%VGPR76<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR76<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR76<def> = V_MUL_F32_e32 %VGPR18, %VGPR76<kill>, %EXEC<imp-use>
>	%VGPR74<def> = V_MAD_F32 %VGPR74<kill>, %VGPR19, %VGPR76<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR76<def> = V_ADD_I32_e32 42, %VGPR70, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR76<def> = V_LSHLREV_B32_e32 4, %VGPR76<kill>, %EXEC<imp-use>
>	%VGPR77<def> = V_OR_B32_e32 4, %VGPR76, %EXEC<imp-use>
>	%VGPR77<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR77<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR74<def> = V_MAD_F32 %VGPR77<kill>, %VGPR20, %VGPR74<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR77<def> = V_ADD_I32_e32 42, %VGPR60, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR77<def> = V_LSHLREV_B32_e32 4, %VGPR77<kill>, %EXEC<imp-use>
>	%VGPR78<def> = V_OR_B32_e32 4, %VGPR77, %EXEC<imp-use>
>	%VGPR78<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR78<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR74<def> = V_MAD_F32 %VGPR78<kill>, %VGPR63, %VGPR74<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR78<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR73, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR79<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR75, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR79<def> = V_MUL_F32_e32 %VGPR18, %VGPR79<kill>, %EXEC<imp-use>
>	%VGPR78<def> = V_MAD_F32 %VGPR78<kill>, %VGPR19, %VGPR79<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR79<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR76, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR78<def> = V_MAD_F32 %VGPR79<kill>, %VGPR20, %VGPR78<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR79<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR77, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR78<def> = V_MAD_F32 %VGPR79<kill>, %VGPR63, %VGPR78<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR79<def> = V_MUL_F32_e32 %VGPR9, %VGPR78, %EXEC<imp-use>
>	%VGPR79<def> = V_MAD_F32 %VGPR59, %VGPR74, %VGPR79<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR80<def> = V_OR_B32_e32 8, %VGPR73, %EXEC<imp-use>
>	%VGPR80<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR80<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR81<def> = V_OR_B32_e32 8, %VGPR75, %EXEC<imp-use>
>	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR81<def> = V_MUL_F32_e32 %VGPR18, %VGPR81<kill>, %EXEC<imp-use>
>	%VGPR80<def> = V_MAD_F32 %VGPR80<kill>, %VGPR19, %VGPR81<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR81<def> = V_OR_B32_e32 8, %VGPR76, %EXEC<imp-use>
>	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR80<def> = V_MAD_F32 %VGPR81<kill>, %VGPR20, %VGPR80<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR81<def> = V_OR_B32_e32 8, %VGPR77, %EXEC<imp-use>
>	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR80<def> = V_MAD_F32 %VGPR81<kill>, %VGPR63, %VGPR80<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR79<def> = V_MAD_F32 %VGPR22, %VGPR80, %VGPR79<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR65<def> = V_ADD_I32_e32 41, %VGPR65<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR81<def> = V_LSHLREV_B32_e32 4, %VGPR65<kill>, %EXEC<imp-use>
>	%VGPR65<def> = V_OR_B32_e32 4, %VGPR81, %EXEC<imp-use>
>	%VGPR65<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR65<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR68<def> = V_ADD_I32_e32 41, %VGPR68<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR68<def> = V_LSHLREV_B32_e32 4, %VGPR68<kill>, %EXEC<imp-use>
>	%VGPR82<def> = V_OR_B32_e32 4, %VGPR68, %EXEC<imp-use>
>	%VGPR82<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR82<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR82<def> = V_MUL_F32_e32 %VGPR18, %VGPR82<kill>, %EXEC<imp-use>
>	%VGPR65<def> = V_MAD_F32 %VGPR65<kill>, %VGPR19, %VGPR82<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR70<def> = V_ADD_I32_e32 41, %VGPR70<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR70<def> = V_LSHLREV_B32_e32 4, %VGPR70<kill>, %EXEC<imp-use>
>	%VGPR82<def> = V_OR_B32_e32 4, %VGPR70, %EXEC<imp-use>
>	%VGPR82<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR82<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR65<def> = V_MAD_F32 %VGPR82<kill>, %VGPR20, %VGPR65<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR60<def> = V_ADD_I32_e32 41, %VGPR60<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR60<def> = V_LSHLREV_B32_e32 4, %VGPR60<kill>, %EXEC<imp-use>
>	%VGPR82<def> = V_OR_B32_e32 4, %VGPR60, %EXEC<imp-use>
>	%VGPR82<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR82<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR82<def> = V_MAD_F32 %VGPR82<kill>, %VGPR63, %VGPR65<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR65<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR81, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR83<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR68, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR83<def> = V_MUL_F32_e32 %VGPR18, %VGPR83<kill>, %EXEC<imp-use>
>	%VGPR65<def> = V_MAD_F32 %VGPR65<kill>, %VGPR19, %VGPR83<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR83<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR70, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR65<def> = V_MAD_F32 %VGPR83<kill>, %VGPR20, %VGPR65<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR83<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR60, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR83<def> = V_MAD_F32 %VGPR83<kill>, %VGPR63, %VGPR65<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR83, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR59<kill>, %VGPR82, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR59<def> = V_OR_B32_e32 8, %VGPR81, %EXEC<imp-use>
>	%VGPR59<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR59<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR65<def> = V_OR_B32_e32 8, %VGPR68, %EXEC<imp-use>
>	%VGPR65<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR65<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR65<def> = V_MUL_F32_e32 %VGPR18, %VGPR65<kill>, %EXEC<imp-use>
>	%VGPR59<def> = V_MAD_F32 %VGPR59<kill>, %VGPR19, %VGPR65<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR65<def> = V_OR_B32_e32 8, %VGPR70, %EXEC<imp-use>
>	%VGPR65<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR65<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR59<def> = V_MAD_F32 %VGPR65<kill>, %VGPR20, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR65<def> = V_OR_B32_e32 8, %VGPR60, %EXEC<imp-use>
>	%VGPR65<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR65<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR59<def> = V_MAD_F32 %VGPR65<kill>, %VGPR63, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR22<kill>, %VGPR59, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_MUL_F32_e32 %VGPR6, %VGPR62<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR5, %VGPR64<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR7, %VGPR72<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR62<def> = V_OR_B32_e32 12, %VGPR66<kill>, %EXEC<imp-use>
>	%VGPR62<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR62<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR64<def> = V_OR_B32_e32 12, %VGPR69<kill>, %EXEC<imp-use>
>	%VGPR64<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR64<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR64<def> = V_MUL_F32_e32 %VGPR18, %VGPR64<kill>, %EXEC<imp-use>
>	%VGPR62<def> = V_MAD_F32 %VGPR62<kill>, %VGPR19, %VGPR64<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR64<def> = V_OR_B32_e32 12, %VGPR71<kill>, %EXEC<imp-use>
>	%VGPR64<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR64<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR62<def> = V_MAD_F32 %VGPR64<kill>, %VGPR20, %VGPR62<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR61<def> = V_OR_B32_e32 12, %VGPR61<kill>, %EXEC<imp-use>
>	%VGPR61<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR61<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR61<def> = V_MAD_F32 %VGPR61<kill>, %VGPR63, %VGPR62<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR64<def> = V_MAD_F32 %VGPR8, %VGPR61<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_MUL_F32_e32 %VGPR6, %VGPR74<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR5, %VGPR78<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR7, %VGPR80<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR61<def> = V_OR_B32_e32 12, %VGPR73<kill>, %EXEC<imp-use>
>	%VGPR61<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR61<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR62<def> = V_OR_B32_e32 12, %VGPR75<kill>, %EXEC<imp-use>
>	%VGPR62<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR62<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR62<def> = V_MUL_F32_e32 %VGPR18, %VGPR62<kill>, %EXEC<imp-use>
>	%VGPR61<def> = V_MAD_F32 %VGPR61<kill>, %VGPR19, %VGPR62<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR62<def> = V_OR_B32_e32 12, %VGPR76<kill>, %EXEC<imp-use>
>	%VGPR62<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR62<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR61<def> = V_MAD_F32 %VGPR62<kill>, %VGPR20, %VGPR61<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR62<def> = V_OR_B32_e32 12, %VGPR77<kill>, %EXEC<imp-use>
>	%VGPR62<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR62<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR61<def> = V_MAD_F32 %VGPR62<kill>, %VGPR63, %VGPR61<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR65<def> = V_MAD_F32 %VGPR8, %VGPR61<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_MUL_F32_e32 %VGPR6, %VGPR82<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR5, %VGPR83<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR7, %VGPR59<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR59<def> = V_OR_B32_e32 12, %VGPR81<kill>, %EXEC<imp-use>
>	%VGPR59<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR59<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR61<def> = V_OR_B32_e32 12, %VGPR68<kill>, %EXEC<imp-use>
>	%VGPR61<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR61<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR61<def> = V_MUL_F32_e32 %VGPR18, %VGPR61<kill>, %EXEC<imp-use>
>	%VGPR59<def> = V_MAD_F32 %VGPR59<kill>, %VGPR19, %VGPR61<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR61<def> = V_OR_B32_e32 12, %VGPR70<kill>, %EXEC<imp-use>
>	%VGPR61<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR61<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR18<def> = V_MAD_F32 %VGPR61<kill>, %VGPR20, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>
>	%VGPR19<def> = V_OR_B32_e32 12, %VGPR60<kill>, %EXEC<imp-use>
>	%VGPR19<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR19<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR18<def> = V_MAD_F32 %VGPR19<kill>, %VGPR63<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR66<def> = V_MAD_F32 %VGPR8, %VGPR18<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use,kill>
>	%VGPR59<def> = V_MOV_B32_e32 %VGPR79<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MOV_B32_e32 %VGPR67<kill>, %EXEC<imp-use>
>    Successors according to CFG: BB#2
>
>BB#2: derived from LLVM BB %ENDIF
>    Live Ins: %VGPR34 %VGPR35 %VGPR28 %VGPR23 %VGPR36 %VGPR37 %VGPR29 %VGPR24 %VGPR38 %VGPR39 %VGPR30 %VGPR25 %VGPR40 %VGPR41 %VGPR31 %VGPR26 %VGPR58 %VGPR53 %VGPR51 %VGPR47 %VGPR43 %VGPR42 %VGPR52 %VGPR48 %VGPR44 %VGPR54 %VGPR55 %VGPR49 %VGPR45 %VGPR56 %VGPR57 %VGPR50 %VGPR46 %VGPR32 %VGPR33 %VGPR27 %VGPR0 %SGPR2 %SGPR3 %SGPR0_SGPR1 %VGPR1_VGPR2_VGPR3_VGPR4 %VGPR10_VGPR11_VGPR12_VGPR13 %VGPR14_VGPR15_VGPR16_VGPR17 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR4_SGPR5 %VGPR66 %VGPR65 %VGPR64 %VGPR9 %VGPR59 %VGPR22
>    Predecessors according to CFG: BB#0 BB#1
>	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
>	%VGPR18<def> = V_MUL_F32_e64 %VGPR15, %VGPR57<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR18<def> = V_MAD_F32 %VGPR14, %VGPR56<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR18<def> = V_MAD_F32 %VGPR16, %VGPR50<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR18<def> = V_MAD_F32 %VGPR17, %VGPR46<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR19<def> = V_MUL_F32_e64 %VGPR15, %VGPR55<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR19<def> = V_MAD_F32 %VGPR14, %VGPR54<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR19<def> = V_MAD_F32 %VGPR16, %VGPR49<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR14<def> = V_MAD_F32 %VGPR17, %VGPR45<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>
>	EXP 15, 32, 0, 0, 0, %VGPR14<kill>, %VGPR18<kill>, %VGPR10, %VGPR11, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>
>	S_WAITCNT 1807
>	%VGPR10<def> = V_MUL_F32_e64 %VGPR9, %VGPR52<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_MAD_F32 %VGPR59, %VGPR48<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_MAD_F32 %VGPR22, %VGPR44<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e64 %VGPR9, %VGPR58<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MAD_F32 %VGPR59, %VGPR53<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MAD_F32 %VGPR22, %VGPR51<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e64 %VGPR9<kill>, %VGPR47<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR59<kill>, %VGPR43<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR22<kill>, %VGPR42<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_ADD_F32_e64 %VGPR9<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e64 %VGPR65, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR66, %VGPR32<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR64, %VGPR27<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR8, %VGPR0<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e32 -1.000000e-01, %VGPR0<kill>, %EXEC<imp-use>
>	EXP 15, 33, 0, 0, 0, %VGPR11<kill>, %VGPR9<kill>, %VGPR10<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	S_WAITCNT 1807
>	%VGPR0<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_MAD_F32 %VGPR4, %VGPR9, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_SUB_F32_e32 1.000000e+00, %VGPR10, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR1, %VGPR9, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR12, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR10, %VGPR12<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_MAD_F32 %VGPR2, %VGPR9, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR13, %EXEC<imp-use>
>	%VGPR13<def> = V_MAD_F32 %VGPR10, %VGPR13<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
>	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR10, %VGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 34, 0, 0, 0, %VGPR0<kill>, %VGPR13<kill>, %VGPR12<kill>, %VGPR10<kill>, %EXEC<imp-use>
>	S_WAITCNT 1807
>	%VGPR0<def> = V_MUL_F32_e64 %VGPR65, %VGPR41<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR66, %VGPR40<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR64, %VGPR31<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR8, %VGPR26<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_MUL_F32_e64 %VGPR65, %VGPR39<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR66, %VGPR38<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR64, %VGPR30<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR8, %VGPR25<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e64 %VGPR65, %VGPR37<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_MAD_F32 %VGPR66, %VGPR36<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_MAD_F32 %VGPR64, %VGPR29<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_MAD_F32 %VGPR8, %VGPR24<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e64 %VGPR65<kill>, %VGPR35<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR66<kill>, %VGPR34<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR64<kill>, %VGPR28<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR8, %VGPR23<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
>	EXP 15, 12, 0, 0, 0, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%538](align=8)(tbaa=!"const")
>	S_WAITCNT 15
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR1<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 13, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80021700
>c0840100
>bf8c0070
>c201092b
>bf8c007f
>7e360202
>c201092a
>bf8c007f
>7e380202
>d2820016
>046e3919
>d2820009
>046e3917
>c0860718
>bf8c007f
>e00c2000
>80030100
>c0860714
>bf8c0070
>e00c2000
>80030a00
>c0860710
>bf8c0070
>e00c2000
>80031200
>c086070c
>bf8c0070
>e00c2000
>80033c00
>c0860708
>bf8c0070
>e00c2000
>80030e00
>c0820700
>bf8c0070
>e00c2000
>80010500
>d2820000
>046e3918
>067600ff
>3a83126f
>be8203ff
>00000f00
>c2010802
>bf8c0070
>d10a0004
>02010002
>c2018929
>c2010928
>c2030927
>c2038926
>c2060925
>c2068924
>c2070923
>c2078922
>c2080921
>c2088920
>c209091f
>c209891e
>c20a091d
>c20a891c
>c20b091a
>c20b8919
>c20c0918
>c20c8916
>c20d0915
>c20d8914
>c20e0912
>c20e8911
>c20f0910
>c20f890f
>c210090e
>c210890d
>c211090c
>c211890b
>c212090a
>c2128909
>c2130908
>c2138907
>c2140906
>c2148905
>c2150904
>c2158903
>c2160902
>c2168901
>c2170900
>bf8c007f
>7e000206
>7e360207
>7e42020c
>7e40020d
>7e5c020e
>7e64020f
>7e720210
>7e700211
>7e5a0212
>7e620213
>7e6e0214
>7e6c0215
>7e580216
>7e600217
>7e680218
>7e540219
>7e56021a
>7e5e021b
>7e66021c
>7e6a021d
>7e74021e
>7e34021f
>7e3e0220
>7e520221
>7e500222
>7e320223
>7e3c0224
>7e4e0225
>7e4c0226
>7e300227
>7e3a0228
>7e4a0229
>7e48022a
>7e2e022b
>7e38022c
>7e46022d
>7e44022e
>7e840305
>7e820306
>7e800307
>be842404
>8984047e
>bf880150
>7e8002ff
>437f028f
>1082813d
>7e821141
>d2d60041
>02010741
>4a8482ab
>34848484
>38868484
>e0301000
>80024343
>1088813c
>7e881144
>d2d60044
>02010744
>4a8a88ab
>348a8a84
>388c8a84
>e0301000
>80024646
>bf8c0770
>108c8d12
>d2820043
>051a2743
>108c813e
>7e8c1146
>d2d60046
>02010746
>4a8e8cab
>348e8e84
>38908e84
>e0301000
>80024848
>bf8c0770
>d2820043
>050e2948
>1078813f
>7e78113c
>d2d6003c
>0201073c
>4a7a78ab
>347a7a84
>387c7a84
>e0301000
>80023e3e
>d206003f
>02022513
>067e7f14
>087e7ef2
>bf8c0770
>d282003e
>050e7f3e
>e0301000
>80024042
>e0301000
>80024345
>bf8c0770
>10868712
>d2820040
>050e2740
>e0301000
>80024347
>bf8c0770
>d2820040
>05022943
>e0301000
>8002433d
>bf8c0770
>d2820040
>05027f43
>10868109
>d2820043
>050e7d3b
>38908488
>e0301000
>80024848
>38928a88
>e0301000
>80024949
>bf8c0770
>10929312
>d2820048
>05262748
>38928e88
>e0301000
>80024949
>bf8c0770
>d2820048
>05222949
>38927a88
>e0301000
>80024949
>bf8c0770
>d2820048
>05227f49
>d2820043
>050e9116
>4a9282aa
>34929284
>38949284
>e0301000
>80024a4a
>4a9688aa
>34969684
>38989684
>e0301000
>80024c4c
>bf8c0770
>10989912
>d282004a
>0532274a
>4a988caa
>34989884
>389a9884
>e0301000
>80024d4d
>bf8c0770
>d282004a
>052a294d
>4a9a78aa
>349a9a84
>389c9a84
>e0301000
>80024e4e
>bf8c0770
>d282004a
>052a7f4e
>e0301000
>80024e49
>e0301000
>80024f4b
>bf8c0770
>109e9f12
>d282004e
>053e274e
>e0301000
>80024f4c
>bf8c0770
>d282004e
>053a294f
>e0301000
>80024f4d
>bf8c0770
>d282004e
>053a7f4f
>109e9d09
>d282004f
>053e953b
>38a09288
>e0301000
>80025050
>38a29688
>e0301000
>80025151
>bf8c0770
>10a2a312
>d2820050
>05462750
>38a29888
>e0301000
>80025151
>bf8c0770
>d2820050
>05422951
>38a29a88
>e0301000
>80025151
>bf8c0770
>d2820050
>05427f51
>d282004f
>053ea116
>4a8282a9
>34a28284
>3882a284
>e0301000
>80024141
>4a8888a9
>34888884
>38a48884
>e0301000
>80025252
>bf8c0770
>10a4a512
>d2820041
>054a2741
>4a8c8ca9
>348c8c84
>38a48c84
>e0301000
>80025252
>bf8c0770
>d2820041
>05062952
>4a7878a9
>34787884
>38a47884
>e0301000
>80025252
>bf8c0770
>d2820052
>05067f52
>e0301000
>80024151
>e0301000
>80025344
>bf8c0770
>10a6a712
>d2820041
>054e2741
>e0301000
>80025346
>bf8c0770
>d2820041
>05062953
>e0301000
>8002533c
>bf8c0770
>d2820053
>05067f53
>1012a709
>d2820009
>0426a53b
>3876a288
>e0301000
>80023b3b
>38828888
>e0301000
>80024141
>bf8c0770
>10828312
>d282003b
>0506273b
>38828c88
>e0301000
>80024141
>bf8c0770
>d282003b
>04ee2941
>38827888
>e0301000
>80024141
>bf8c0770
>d282003b
>04ee7f41
>d2820009
>04267716
>102c7d06
>d2820016
>045a8105
>d2820016
>045a9107
>387c848c
>e0301000
>80023e3e
>38808a8c
>e0301000
>80024040
>bf8c0770
>10808112
>d282003e
>0502273e
>38808e8c
>e0301000
>80024040
>bf8c0770
>d282003e
>04fa2940
>387a7a8c
>e0301000
>80023d3d
>bf8c0770
>d282003d
>04fa7f3d
>d2820040
>045a7b08
>102c9506
>d2820016
>045a9d05
>d2820016
>045aa107
>387a928c
>e0301000
>80023d3d
>387c968c
>e0301000
>80023e3e
>bf8c0770
>107c7d12
>d282003d
>04fa273d
>387c988c
>e0301000
>80023e3e
>bf8c0770
>d282003d
>04f6293e
>387c9a8c
>e0301000
>80023e3e
>bf8c0770
>d282003d
>04f67f3e
>d2820041
>045a7b08
>102ca506
>d2820016
>045aa705
>d2820016
>045a7707
>3876a28c
>e0301000
>80023b3b
>387a888c
>e0301000
>80023d3d
>bf8c0770
>107a7b12
>d282003b
>04f6273b
>387a8c8c
>e0301000
>80023d3d
>bf8c0770
>d2820012
>04ee293d
>3826788c
>e0301000
>80021313
>bf8c0770
>d2820012
>044a7f13
>d2820042
>045a2508
>7e76034f
>7e2c0343
>88fe047e
>d2100012
>0202730f
>d2820012
>044a710e
>d2820012
>044a6510
>d2820012
>044a5d11
>d2100013
>02026f0f
>d2820013
>044e6d0e
>d2820013
>044e6310
>d282000e
>044e5b11
>f800020f
>0b0a120e
>bf8c070f
>d210000a
>02026909
>d282000a
>042a613b
>d282000a
>042a5916
>d210000b
>02027509
>d282000b
>042e6b3b
>d282000b
>042e6716
>d2100009
>02025f09
>d2820009
>0426573b
>d2820009
>04265516
>d2060009
>22010109
>d210000c
>02024341
>d282000c
>04324142
>d282000c
>04323740
>d2820000
>04320108
>060000ff
>bdcccccd
>f800021f
>000a090b
>bf8c070f
>7e000203
>7e120202
>d282000a
>04021304
>081614f2
>d282000c
>04021301
>1018190c
>d282000c
>042e190a
>d282000d
>04021302
>101a1b0d
>d282000d
>042e1b0a
>d2820000
>04021303
>10000100
>d2820000
>042e010a
>f800022f
>0a0c0d00
>bf8c070f
>d2100000
>02025341
>d2820000
>04025142
>d2820000
>04023f40
>d2820000
>04023508
>d2100001
>02024f41
>d2820001
>04064d42
>d2820001
>04063d40
>d2820001
>04063308
>d2100002
>02024b41
>d2820002
>040a4942
>d2820002
>040a3b40
>d2820002
>040a3108
>d2100003
>02024741
>d2820003
>040e4542
>d2820003
>040e3940
>d2820003
>040e2f08
>f80000cf
>00010203
>c0800104
>bf8c000f
>c202010d
>bf8c007f
>10080404
>c202010c
>bf8c007f
>d2820004
>04120604
>c202010e
>bf8c007f
>d2820004
>04120204
>c202010f
>bf8c007f
>d2820004
>04120004
>c2020109
>bf8c007f
>100a0404
>c2020108
>bf8c007f
>d2820005
>04160604
>c202010a
>bf8c007f
>d2820005
>04160204
>c202010b
>bf8c007f
>d2820005
>04160004
>c2020105
>bf8c007f
>100c0404
>c2020104
>bf8c007f
>d2820006
>041a0604
>c2020106
>bf8c007f
>d2820006
>041a0204
>c2020107
>bf8c007f
>d2820006
>041a0004
>c2020101
>bf8c007f
>10040404
>c2020100
>bf8c007f
>d2820002
>040a0604
>c2020102
>bf8c007f
>d2820001
>040a0204
>c2000103
>bf8c007f
>d2820000
>04060000
>f80008df
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL OUT[0], COLOR
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV OUT[0], IMM[0].xxxx
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 1.000000e+00)
>  %21 = bitcast i32 %20 to float
>  %22 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 1.000000e+00)
>  %23 = bitcast i32 %22 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %21, float %23, float %21, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
># Machine code for function main: Post SSA, not tracking liveness
>
>BB#0: derived from LLVM BB %main_body
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 1.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>d25e0000
>0201e4f2
>f8001c0f
>00000000
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL CONST[0..6]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: DP4 TEMP[0].x, IN[0], CONST[0]
>  1: DP4 TEMP[1].x, IN[0], CONST[1]
>  2: MOV TEMP[0].y, TEMP[1].xxxx
>  3: DP4 TEMP[1].x, IN[0], CONST[2]
>  4: MOV TEMP[0].z, TEMP[1].xxxx
>  5: MOV TEMP[0].xyz, TEMP[0].xyzx
>  6: MOV TEMP[0].w, IMM[0].xxxx
>  7: DP4 TEMP[1].x, TEMP[0], CONST[3]
>  8: DP4 TEMP[2].x, TEMP[0], CONST[4]
>  9: MOV TEMP[1].y, TEMP[2].xxxx
> 10: DP4 TEMP[2].x, TEMP[0], CONST[5]
> 11: MOV TEMP[1].z, TEMP[2].xxxx
> 12: DP4 TEMP[0].x, TEMP[0], CONST[6]
> 13: MOV TEMP[1].w, TEMP[0].xxxx
> 14: MOV OUT[0], TEMP[1]
> 15: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
>  %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %40, i32 0, i32 %5)
>  %42 = extractelement <4 x float> %41, i32 0
>  %43 = extractelement <4 x float> %41, i32 1
>  %44 = extractelement <4 x float> %41, i32 2
>  %45 = extractelement <4 x float> %41, i32 3
>  %46 = fmul float %42, %11
>  %47 = fmul float %43, %12
>  %48 = fadd float %46, %47
>  %49 = fmul float %44, %13
>  %50 = fadd float %48, %49
>  %51 = fmul float %45, %14
>  %52 = fadd float %50, %51
>  %53 = fmul float %42, %15
>  %54 = fmul float %43, %16
>  %55 = fadd float %53, %54
>  %56 = fmul float %44, %17
>  %57 = fadd float %55, %56
>  %58 = fmul float %45, %18
>  %59 = fadd float %57, %58
>  %60 = fmul float %42, %19
>  %61 = fmul float %43, %20
>  %62 = fadd float %60, %61
>  %63 = fmul float %44, %21
>  %64 = fadd float %62, %63
>  %65 = fmul float %45, %22
>  %66 = fadd float %64, %65
>  %67 = fmul float %52, %23
>  %68 = fmul float %59, %24
>  %69 = fadd float %67, %68
>  %70 = fmul float %66, %25
>  %71 = fadd float %69, %70
>  %72 = fmul float 1.000000e+00, %26
>  %73 = fadd float %71, %72
>  %74 = fmul float %52, %27
>  %75 = fmul float %59, %28
>  %76 = fadd float %74, %75
>  %77 = fmul float %66, %29
>  %78 = fadd float %76, %77
>  %79 = fmul float 1.000000e+00, %30
>  %80 = fadd float %78, %79
>  %81 = fmul float %52, %31
>  %82 = fmul float %59, %32
>  %83 = fadd float %81, %82
>  %84 = fmul float %66, %33
>  %85 = fadd float %83, %84
>  %86 = fmul float 1.000000e+00, %34
>  %87 = fadd float %85, %86
>  %88 = fmul float %52, %35
>  %89 = fmul float %59, %36
>  %90 = fadd float %88, %89
>  %91 = fmul float %66, %37
>  %92 = fadd float %90, %91
>  %93 = fmul float 1.000000e+00, %38
>  %94 = fadd float %92, %93
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %73, float %80, float %87, float %94)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%42](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e64 %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR0, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR0, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e64 %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR0, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR1<def> = V_MAD_F32 %VGPR0, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR1<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MAD_F32 %VGPR0, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_MAD_F32 %VGPR0, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MAD_F32 %VGPR4<kill>, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 15; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020101
>bf8c007f
>7e080204
>d2100004
>02020901
>c2020100
>bf8c007f
>7e0a0204
>d2820004
>04120b00
>c2020102
>bf8c007f
>7e0a0204
>d2820004
>04120b02
>c2020103
>bf8c007f
>7e0a0204
>d2820004
>04120b03
>c2020105
>bf8c007f
>7e0a0204
>d2100005
>02020b01
>c2020104
>bf8c007f
>7e0c0204
>d2820005
>04160d00
>c2020106
>bf8c007f
>7e0c0204
>d2820005
>04160d02
>c2020107
>bf8c007f
>7e0c0204
>d2820005
>04160d03
>c2020119
>bf8c007f
>100c0a04
>c2020118
>bf8c007f
>d2820006
>04180904
>c2020109
>bf8c007f
>7e0e0204
>d2100007
>02020f01
>c2020108
>bf8c007f
>7e100204
>d2820007
>041e1100
>c202010a
>bf8c007f
>7e100204
>d2820007
>041e1102
>c202010b
>bf8c007f
>7e100204
>d2820000
>041e1103
>c202011a
>bf8c007f
>d2820001
>04180900
>c202011b
>bf8c007f
>06020204
>c2020115
>bf8c007f
>10040a04
>c2020114
>bf8c007f
>d2820002
>04080904
>c2020116
>bf8c007f
>d2820002
>04080900
>c2020117
>bf8c007f
>06040404
>c2020111
>bf8c007f
>10060a04
>c2020110
>bf8c007f
>d2820003
>040c0904
>c2020112
>bf8c007f
>d2820003
>040c0900
>c2020113
>bf8c007f
>06060604
>c202010d
>bf8c007f
>100a0a04
>c202010c
>bf8c007f
>d2820004
>04140904
>c202010e
>bf8c007f
>d2820000
>04100900
>c200010f
>bf8c007f
>06000000
>f80008cf
>01020300
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {32767.0000,     7.9688,     0.0000,   128.0000}
>IMM[1] FLT32 {    0.0039,     0.0000,    32.0000,   -16.0000}
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
>  2: MIN TEMP[0].xyz, TEMP[0].xyzz, IMM[0].xxxx
>  3: MAX TEMP[1].x, TEMP[0].xxxx, TEMP[0].yyyy
>  4: MAX TEMP[1].x, TEMP[1].xxxx, TEMP[0].zzzz
>  5: ADD TEMP[1].x, TEMP[1].xxxx, IMM[0].zzzz
>  6: LG2 TEMP[1].x, TEMP[1].xxxx
>  7: MAD TEMP[1].x, IMM[0].yyyy, TEMP[1].xxxx, IMM[0].wwww
>  8: CEIL TEMP[1].x, TEMP[1].xxxx
>  9: MUL TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx
> 10: MAX TEMP[1].x, TEMP[1].xxxx, IMM[1].yyyy
> 11: MAD TEMP[2].x, TEMP[1].xxxx, IMM[1].zzzz, IMM[1].wwww
> 12: EX2 TEMP[2].x, TEMP[2].xxxx
> 13: RCP TEMP[2].x, TEMP[2].xxxx
> 14: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
> 15: MOV TEMP[0].w, TEMP[1].xxxx
> 16: MOV OUT[0], TEMP[0]
> 17: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = fcmp uge float %31, 3.276700e+04
>  %35 = select i1 %34, float 3.276700e+04, float %31
>  %36 = fcmp uge float %32, 3.276700e+04
>  %37 = select i1 %36, float 3.276700e+04, float %32
>  %38 = fcmp uge float %33, 3.276700e+04
>  %39 = select i1 %38, float 3.276700e+04, float %33
>  %40 = fcmp uge float %35, %37
>  %41 = select i1 %40, float %35, float %37
>  %42 = fcmp uge float %41, %39
>  %43 = select i1 %42, float %41, float %39
>  %44 = fadd float %43, 0x3EE0000000000000
>  %45 = call float @llvm.log2.f32(float %44)
>  %46 = fmul float 7.968750e+00, %45
>  %47 = fadd float %46, 1.280000e+02
>  %48 = call float @ceil(float %47)
>  %49 = fmul float %48, 0x3F70101020000000
>  %50 = fcmp uge float %49, 0.000000e+00
>  %51 = select i1 %50, float %49, float 0.000000e+00
>  %52 = fmul float %51, 3.200000e+01
>  %53 = fadd float %52, -1.600000e+01
>  %54 = call float @llvm.AMDIL.exp.(float %53)
>  %55 = fdiv float 1.000000e+00, %54
>  %56 = fmul float %35, %55
>  %57 = fmul float %37, %55
>  %58 = fmul float %39, %55
>  %59 = call i32 @llvm.SI.packf16(float %56, float %57)
>  %60 = bitcast i32 %59 to float
>  %61 = call i32 @llvm.SI.packf16(float %58, float %51)
>  %62 = bitcast i32 %61 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %60, float %62, float %60, float %62)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readonly
>declare float @llvm.log2.f32(float) #2
>
>; Function Attrs: readonly
>declare float @ceil(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #4
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { nounwind readonly }
>attributes #3 = { readonly }
>attributes #4 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
>	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2<def> = IMAGE_SAMPLE_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MOV_B32_e32 3.276700e+04, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR1, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR1, %VGPR3, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR0, %VGPR3, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR5, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR3<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2<imp-use,kill>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR6, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR0, %VGPR6<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_ADD_F32_e32 7.629395e-06, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_LOG_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MOV_B32_e32 1.280000e+02, %EXEC<imp-use>
>	%VGPR3<def> = V_MOV_B32_e32 7.968750e+00, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CEIL_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_MUL_F32_e32 3.921569e-03, %VGPR1<kill>, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR1, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR1<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_MOV_B32_e32 -1.600000e+01, %EXEC<imp-use>
>	%VGPR3<def> = V_MOV_B32_e32 3.200000e+01, %EXEC<imp-use>
>	%VGPR2<def> = V_MAD_F32 %VGPR1, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_EXP_F32_e32 %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_RCP_F32_e32 %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR2, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800700
>00010002
>7e0602ff
>46fffe00
>bf8c0770
>d00c0000
>02020701
>d2000004
>00020701
>d00c0000
>02020700
>d2000005
>00020700
>d00c0000
>02020905
>d2000006
>00020b04
>d00c0000
>02020702
>d2000000
>00020702
>d00c0000
>02020106
>d2000001
>00020d00
>060202ff
>37000000
>7e024f01
>7e0402ff
>43000000
>7e0602ff
>40ff0000
>d2820001
>040a0701
>7e024501
>100202ff
>3b808081
>d00c0000
>02010101
>d2000001
>00020280
>7e0402ff
>c1800000
>7e0602ff
>42000000
>d2820002
>040a0701
>7e044b02
>7e045502
>10000500
>5e000300
>10020504
>10040505
>5e020302
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	S_WAITCNT 1807
>	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
>	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
>	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020107
>bf8c007f
>7e080204
>c2020105
>bf8c007f
>7e0a0204
>d2820004
>04120b03
>c2020106
>bf8c007f
>7e0a0204
>c2020104
>bf8c007f
>7e0c0204
>d2820005
>04160d02
>c2020103
>bf8c007f
>7e0c0204
>c2020101
>bf8c007f
>7e0e0204
>d2820006
>041a0f03
>c2020102
>bf8c007f
>7e0e0204
>c2000100
>bf8c007f
>7e100200
>d2820007
>041e1102
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	S_WAITCNT 1807
>	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
>	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
>	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020107
>bf8c007f
>7e080204
>c2020105
>bf8c007f
>7e0a0204
>d2820004
>04120b03
>c2020106
>bf8c007f
>7e0a0204
>c2020104
>bf8c007f
>7e0c0204
>d2820005
>04160d02
>c2020103
>bf8c007f
>7e0c0204
>c2020101
>bf8c007f
>7e0e0204
>d2820006
>041a0f03
>c2020102
>bf8c007f
>7e0e0204
>c2000100
>bf8c007f
>7e100200
>d2820007
>041e1102
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL CONST[0..13]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.2500, -2048.0000}
>IMM[1] FLT32 {   -0.0005,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].w, IMM[0].xxxx
>  1: MOV TEMP[0].z, IMM[0].yyyy
>  2: MAD TEMP[0].x, IN[0].zzzz, CONST[0].zzzz, CONST[0].yyyy
>  3: MOV_SAT TEMP[0].x, TEMP[0].xxxx
>  4: MOV TEMP[0].x, TEMP[0].xxxx
>  5: POW TEMP[1].x, TEMP[0].xxxx, IMM[0].zzzz
>  6: MUL TEMP[0].x, TEMP[1].xxxx, CONST[0].wwww
>  7: MUL TEMP[1].x, TEMP[0].xxxx, IMM[0].wwww
>  8: FRC TEMP[1].x, TEMP[1].xxxx
>  9: MOV TEMP[0].y, TEMP[1].xxxx
> 10: MUL TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx
> 11: ADD TEMP[0].x, TEMP[0].xxxx, -TEMP[1].xxxx
> 12: MOV OUT[0], TEMP[0]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %25 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %26 = fmul float %25, %23
>  %27 = fadd float %26, %22
>  %28 = call float @llvm.AMDIL.clamp.(float %27, float 0.000000e+00, float 1.000000e+00)
>  %29 = call float @llvm.pow.f32(float %28, float 2.500000e-01)
>  %30 = fmul float %29, %24
>  %31 = fmul float %30, -2.048000e+03
>  %32 = call float @llvm.AMDIL.fraction.(float %31)
>  %33 = fmul float %32, 0xBF40000000000000
>  %34 = fsub float -0.000000e+00, %33
>  %35 = fadd float %30, %34
>  %36 = call i32 @llvm.SI.packf16(float %35, float %32)
>  %37 = bitcast i32 %36 to float
>  %38 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 1.000000e+00)
>  %39 = bitcast i32 %38 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %37, float %39, float %37, float %39)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.fraction.(float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR2<kill>, %SGPR4<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_LOG_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MUL_LEGACY_F32_e32 2.500000e-01, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_EXP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR1<def> = V_MUL_F32_e32 %SGPR0, %VGPR0, %EXEC<imp-use>
>	%VGPR1<def> = V_MUL_F32_e32 -2.048000e+03, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_FRACT_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 4.882812e-04, %VGPR1, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR1<kill>, %VGPR0, %VGPR1, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8080200
>c8090201
>c0800100
>bf8c007f
>c2020102
>c2028101
>bf8c007f
>7e000205
>d2820000
>04000902
>d2060800
>02010100
>7e004f00
>0e0000ff
>3e800000
>7e004b00
>c2000103
>bf8c007f
>10020000
>100202ff
>c5000000
>7e024101
>100402ff
>3a000000
>d2820000
>04080100
>5e000300
>d25e0001
>0201e480
>f8001c0f
>01000100
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], CLIPVERTEX
>DCL OUT[2], GENERIC[19]
>DCL CONST[0..240]
>DCL TEMP[0..7], LOCAL
>DCL ADDR[0]
>IMM[0] FLT32 {    1.0000,   255.0100,     0.0000,     0.0000}
>IMM[1] INT32 {3, 41, 42, 43}
>  0: MOV TEMP[0], IN[0]
>  1: UIF CONST[240].xxxx :0
>  2:   DP3 TEMP[1].x, IN[3].xyzz, IMM[0].xxxx
>  3:   ADD TEMP[1].x, IMM[0].xxxx, -TEMP[1].xxxx
>  4:   MUL TEMP[2], IN[2], IMM[0].yyyy
>  5:   F2I TEMP[2], TEMP[2]
>  6:   UMAD TEMP[3].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].yyyy
>  7:   UMAD TEMP[4].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].yyyy
>  8:   UMAD TEMP[5].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].yyyy
>  9:   UMAD TEMP[6].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].yyyy
> 10:   UARL ADDR[0].x, TEMP[6].xxxx
> 11:   MUL TEMP[6], CONST[ADDR[0].x], IN[3].xxxx
> 12:   UARL ADDR[0].x, TEMP[5].xxxx
> 13:   MAD TEMP[5], CONST[ADDR[0].x], IN[3].yyyy, TEMP[6]
> 14:   UARL ADDR[0].x, TEMP[4].xxxx
> 15:   MAD TEMP[4], CONST[ADDR[0].x], IN[3].zzzz, TEMP[5]
> 16:   UARL ADDR[0].x, TEMP[3].xxxx
> 17:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[4]
> 18:   DP4 TEMP[3].x, IN[0], TEMP[3]
> 19:   UMAD TEMP[4].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].zzzz
> 20:   UMAD TEMP[5].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].zzzz
> 21:   UMAD TEMP[6].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].zzzz
> 22:   UMAD TEMP[7].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].zzzz
> 23:   UARL ADDR[0].x, TEMP[7].xxxx
> 24:   MUL TEMP[7], CONST[ADDR[0].x], IN[3].xxxx
> 25:   UARL ADDR[0].x, TEMP[6].xxxx
> 26:   MAD TEMP[6], CONST[ADDR[0].x], IN[3].yyyy, TEMP[7]
> 27:   UARL ADDR[0].x, TEMP[5].xxxx
> 28:   MAD TEMP[5], CONST[ADDR[0].x], IN[3].zzzz, TEMP[6]
> 29:   UARL ADDR[0].x, TEMP[4].xxxx
> 30:   MAD TEMP[4], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[5]
> 31:   DP4 TEMP[4].x, IN[0], TEMP[4]
> 32:   MOV TEMP[3].y, TEMP[4].xxxx
> 33:   UMAD TEMP[4].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].wwww
> 34:   UMAD TEMP[5].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].wwww
> 35:   UMAD TEMP[6].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].wwww
> 36:   UMAD TEMP[2].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].wwww
> 37:   UARL ADDR[0].x, TEMP[2].xxxx
> 38:   MUL TEMP[2], CONST[ADDR[0].x], IN[3].xxxx
> 39:   UARL ADDR[0].x, TEMP[6].xxxx
> 40:   MAD TEMP[2], CONST[ADDR[0].x], IN[3].yyyy, TEMP[2]
> 41:   UARL ADDR[0].x, TEMP[5].xxxx
> 42:   MAD TEMP[2], CONST[ADDR[0].x], IN[3].zzzz, TEMP[2]
> 43:   UARL ADDR[0].x, TEMP[4].xxxx
> 44:   MAD TEMP[1], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[2]
> 45:   DP4 TEMP[1].x, IN[0], TEMP[1]
> 46:   MOV TEMP[3].z, TEMP[1].xxxx
> 47:   MOV TEMP[0].xyz, TEMP[3].xyzx
> 48: ENDIF
> 49: DP4 TEMP[1].x, TEMP[0], CONST[0]
> 50: DP4 TEMP[2].x, TEMP[0], CONST[1]
> 51: MOV TEMP[1].y, TEMP[2].xxxx
> 52: DP4 TEMP[2].x, TEMP[0], CONST[2]
> 53: MOV TEMP[1].z, TEMP[2].xxxx
> 54: DP4 TEMP[2].x, TEMP[0], CONST[3]
> 55: MOV TEMP[1].w, TEMP[2].xxxx
> 56: DP4 TEMP[0].x, TEMP[0], CONST[9]
> 57: MOV TEMP[0].z, TEMP[0].xxxx
> 58: DP4 TEMP[2].x, IN[1], CONST[7]
> 59: DP4 TEMP[3].x, IN[1], CONST[8]
> 60: MOV TEMP[2].y, TEMP[3].xxxx
> 61: MOV TEMP[0].xy, TEMP[2].xyxx
> 62: MOV TEMP[0].w, IMM[0].xxxx
> 63: MOV OUT[0], TEMP[1]
> 64: MOV OUT[2], TEMP[0]
> 65: MOV OUT[1], TEMP[1]
> 66: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 3840)
>  %40 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0
>  %42 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %41, i32 0, i32 %5)
>  %43 = extractelement <4 x float> %42, i32 0
>  %44 = extractelement <4 x float> %42, i32 1
>  %45 = extractelement <4 x float> %42, i32 2
>  %46 = extractelement <4 x float> %42, i32 3
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = extractelement <4 x float> %56, i32 3
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 0
>  %65 = extractelement <4 x float> %63, i32 1
>  %66 = extractelement <4 x float> %63, i32 2
>  %67 = bitcast float %39 to i32
>  %68 = icmp ne i32 %67, 0
>  br i1 %68, label %IF, label %ENDIF
>
>IF:                                               ; preds = %main_body
>  %69 = fmul float %64, 1.000000e+00
>  %70 = fmul float %65, 1.000000e+00
>  %71 = fadd float %70, %69
>  %72 = fmul float %66, 1.000000e+00
>  %73 = fadd float %71, %72
>  %74 = fsub float -0.000000e+00, %73
>  %75 = fadd float 1.000000e+00, %74
>  %76 = fmul float %57, 0x406FE051E0000000
>  %77 = fmul float %58, 0x406FE051E0000000
>  %78 = fmul float %59, 0x406FE051E0000000
>  %79 = fmul float %60, 0x406FE051E0000000
>  %80 = fptosi float %76 to i32
>  %81 = fptosi float %77 to i32
>  %82 = fptosi float %78 to i32
>  %83 = fptosi float %79 to i32
>  %84 = bitcast i32 %80 to float
>  %85 = bitcast i32 %81 to float
>  %86 = bitcast i32 %82 to float
>  %87 = bitcast i32 %83 to float
>  %88 = bitcast float %87 to i32
>  %89 = mul i32 %88, 3
>  %90 = add i32 %89, 41
>  %91 = bitcast i32 %90 to float
>  %92 = bitcast float %86 to i32
>  %93 = mul i32 %92, 3
>  %94 = add i32 %93, 41
>  %95 = bitcast i32 %94 to float
>  %96 = bitcast float %85 to i32
>  %97 = mul i32 %96, 3
>  %98 = add i32 %97, 41
>  %99 = bitcast i32 %98 to float
>  %100 = bitcast float %84 to i32
>  %101 = mul i32 %100, 3
>  %102 = add i32 %101, 41
>  %103 = bitcast i32 %102 to float
>  %104 = bitcast float %103 to i32
>  %105 = shl i32 %104, 4
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %105)
>  %107 = fmul float %106, %64
>  %108 = shl i32 %104, 4
>  %109 = add i32 %108, 4
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %109)
>  %111 = fmul float %110, %64
>  %112 = shl i32 %104, 4
>  %113 = add i32 %112, 8
>  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %113)
>  %115 = fmul float %114, %64
>  %116 = shl i32 %104, 4
>  %117 = add i32 %116, 12
>  %118 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %117)
>  %119 = fmul float %118, %64
>  %120 = bitcast float %99 to i32
>  %121 = shl i32 %120, 4
>  %122 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %121)
>  %123 = fmul float %122, %65
>  %124 = fadd float %123, %107
>  %125 = shl i32 %120, 4
>  %126 = add i32 %125, 4
>  %127 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %126)
>  %128 = fmul float %127, %65
>  %129 = fadd float %128, %111
>  %130 = shl i32 %120, 4
>  %131 = add i32 %130, 8
>  %132 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %131)
>  %133 = fmul float %132, %65
>  %134 = fadd float %133, %115
>  %135 = shl i32 %120, 4
>  %136 = add i32 %135, 12
>  %137 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %136)
>  %138 = fmul float %137, %65
>  %139 = fadd float %138, %119
>  %140 = bitcast float %95 to i32
>  %141 = shl i32 %140, 4
>  %142 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %141)
>  %143 = fmul float %142, %66
>  %144 = fadd float %143, %124
>  %145 = shl i32 %140, 4
>  %146 = add i32 %145, 4
>  %147 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %146)
>  %148 = fmul float %147, %66
>  %149 = fadd float %148, %129
>  %150 = shl i32 %140, 4
>  %151 = add i32 %150, 8
>  %152 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %151)
>  %153 = fmul float %152, %66
>  %154 = fadd float %153, %134
>  %155 = shl i32 %140, 4
>  %156 = add i32 %155, 12
>  %157 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %156)
>  %158 = fmul float %157, %66
>  %159 = fadd float %158, %139
>  %160 = bitcast float %91 to i32
>  %161 = shl i32 %160, 4
>  %162 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %161)
>  %163 = fmul float %162, %75
>  %164 = fadd float %163, %144
>  %165 = shl i32 %160, 4
>  %166 = add i32 %165, 4
>  %167 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %166)
>  %168 = fmul float %167, %75
>  %169 = fadd float %168, %149
>  %170 = shl i32 %160, 4
>  %171 = add i32 %170, 8
>  %172 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %171)
>  %173 = fmul float %172, %75
>  %174 = fadd float %173, %154
>  %175 = shl i32 %160, 4
>  %176 = add i32 %175, 12
>  %177 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %176)
>  %178 = fmul float %177, %75
>  %179 = fadd float %178, %159
>  %180 = fmul float %43, %164
>  %181 = fmul float %44, %169
>  %182 = fadd float %180, %181
>  %183 = fmul float %45, %174
>  %184 = fadd float %182, %183
>  %185 = fmul float %46, %179
>  %186 = fadd float %184, %185
>  %187 = bitcast float %87 to i32
>  %188 = mul i32 %187, 3
>  %189 = add i32 %188, 42
>  %190 = bitcast i32 %189 to float
>  %191 = bitcast float %86 to i32
>  %192 = mul i32 %191, 3
>  %193 = add i32 %192, 42
>  %194 = bitcast i32 %193 to float
>  %195 = bitcast float %85 to i32
>  %196 = mul i32 %195, 3
>  %197 = add i32 %196, 42
>  %198 = bitcast i32 %197 to float
>  %199 = bitcast float %84 to i32
>  %200 = mul i32 %199, 3
>  %201 = add i32 %200, 42
>  %202 = bitcast i32 %201 to float
>  %203 = bitcast float %202 to i32
>  %204 = shl i32 %203, 4
>  %205 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %204)
>  %206 = fmul float %205, %64
>  %207 = shl i32 %203, 4
>  %208 = add i32 %207, 4
>  %209 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %208)
>  %210 = fmul float %209, %64
>  %211 = shl i32 %203, 4
>  %212 = add i32 %211, 8
>  %213 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %212)
>  %214 = fmul float %213, %64
>  %215 = shl i32 %203, 4
>  %216 = add i32 %215, 12
>  %217 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %216)
>  %218 = fmul float %217, %64
>  %219 = bitcast float %198 to i32
>  %220 = shl i32 %219, 4
>  %221 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %220)
>  %222 = fmul float %221, %65
>  %223 = fadd float %222, %206
>  %224 = shl i32 %219, 4
>  %225 = add i32 %224, 4
>  %226 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %225)
>  %227 = fmul float %226, %65
>  %228 = fadd float %227, %210
>  %229 = shl i32 %219, 4
>  %230 = add i32 %229, 8
>  %231 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %230)
>  %232 = fmul float %231, %65
>  %233 = fadd float %232, %214
>  %234 = shl i32 %219, 4
>  %235 = add i32 %234, 12
>  %236 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %235)
>  %237 = fmul float %236, %65
>  %238 = fadd float %237, %218
>  %239 = bitcast float %194 to i32
>  %240 = shl i32 %239, 4
>  %241 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %240)
>  %242 = fmul float %241, %66
>  %243 = fadd float %242, %223
>  %244 = shl i32 %239, 4
>  %245 = add i32 %244, 4
>  %246 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %245)
>  %247 = fmul float %246, %66
>  %248 = fadd float %247, %228
>  %249 = shl i32 %239, 4
>  %250 = add i32 %249, 8
>  %251 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %250)
>  %252 = fmul float %251, %66
>  %253 = fadd float %252, %233
>  %254 = shl i32 %239, 4
>  %255 = add i32 %254, 12
>  %256 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %255)
>  %257 = fmul float %256, %66
>  %258 = fadd float %257, %238
>  %259 = bitcast float %190 to i32
>  %260 = shl i32 %259, 4
>  %261 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %260)
>  %262 = fmul float %261, %75
>  %263 = fadd float %262, %243
>  %264 = shl i32 %259, 4
>  %265 = add i32 %264, 4
>  %266 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %265)
>  %267 = fmul float %266, %75
>  %268 = fadd float %267, %248
>  %269 = shl i32 %259, 4
>  %270 = add i32 %269, 8
>  %271 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %270)
>  %272 = fmul float %271, %75
>  %273 = fadd float %272, %253
>  %274 = shl i32 %259, 4
>  %275 = add i32 %274, 12
>  %276 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %275)
>  %277 = fmul float %276, %75
>  %278 = fadd float %277, %258
>  %279 = fmul float %43, %263
>  %280 = fmul float %44, %268
>  %281 = fadd float %279, %280
>  %282 = fmul float %45, %273
>  %283 = fadd float %281, %282
>  %284 = fmul float %46, %278
>  %285 = fadd float %283, %284
>  %286 = bitcast float %87 to i32
>  %287 = mul i32 %286, 3
>  %288 = add i32 %287, 43
>  %289 = bitcast i32 %288 to float
>  %290 = bitcast float %86 to i32
>  %291 = mul i32 %290, 3
>  %292 = add i32 %291, 43
>  %293 = bitcast i32 %292 to float
>  %294 = bitcast float %85 to i32
>  %295 = mul i32 %294, 3
>  %296 = add i32 %295, 43
>  %297 = bitcast i32 %296 to float
>  %298 = bitcast float %84 to i32
>  %299 = mul i32 %298, 3
>  %300 = add i32 %299, 43
>  %301 = bitcast i32 %300 to float
>  %302 = bitcast float %301 to i32
>  %303 = shl i32 %302, 4
>  %304 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %303)
>  %305 = fmul float %304, %64
>  %306 = shl i32 %302, 4
>  %307 = add i32 %306, 4
>  %308 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %307)
>  %309 = fmul float %308, %64
>  %310 = shl i32 %302, 4
>  %311 = add i32 %310, 8
>  %312 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %311)
>  %313 = fmul float %312, %64
>  %314 = shl i32 %302, 4
>  %315 = add i32 %314, 12
>  %316 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %315)
>  %317 = fmul float %316, %64
>  %318 = bitcast float %297 to i32
>  %319 = shl i32 %318, 4
>  %320 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %319)
>  %321 = fmul float %320, %65
>  %322 = fadd float %321, %305
>  %323 = shl i32 %318, 4
>  %324 = add i32 %323, 4
>  %325 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %324)
>  %326 = fmul float %325, %65
>  %327 = fadd float %326, %309
>  %328 = shl i32 %318, 4
>  %329 = add i32 %328, 8
>  %330 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %329)
>  %331 = fmul float %330, %65
>  %332 = fadd float %331, %313
>  %333 = shl i32 %318, 4
>  %334 = add i32 %333, 12
>  %335 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %334)
>  %336 = fmul float %335, %65
>  %337 = fadd float %336, %317
>  %338 = bitcast float %293 to i32
>  %339 = shl i32 %338, 4
>  %340 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %339)
>  %341 = fmul float %340, %66
>  %342 = fadd float %341, %322
>  %343 = shl i32 %338, 4
>  %344 = add i32 %343, 4
>  %345 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %344)
>  %346 = fmul float %345, %66
>  %347 = fadd float %346, %327
>  %348 = shl i32 %338, 4
>  %349 = add i32 %348, 8
>  %350 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %349)
>  %351 = fmul float %350, %66
>  %352 = fadd float %351, %332
>  %353 = shl i32 %338, 4
>  %354 = add i32 %353, 12
>  %355 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %354)
>  %356 = fmul float %355, %66
>  %357 = fadd float %356, %337
>  %358 = bitcast float %289 to i32
>  %359 = shl i32 %358, 4
>  %360 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %359)
>  %361 = fmul float %360, %75
>  %362 = fadd float %361, %342
>  %363 = shl i32 %358, 4
>  %364 = add i32 %363, 4
>  %365 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %364)
>  %366 = fmul float %365, %75
>  %367 = fadd float %366, %347
>  %368 = shl i32 %358, 4
>  %369 = add i32 %368, 8
>  %370 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %369)
>  %371 = fmul float %370, %75
>  %372 = fadd float %371, %352
>  %373 = shl i32 %358, 4
>  %374 = add i32 %373, 12
>  %375 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %374)
>  %376 = fmul float %375, %75
>  %377 = fadd float %376, %357
>  %378 = fmul float %43, %362
>  %379 = fmul float %44, %367
>  %380 = fadd float %378, %379
>  %381 = fmul float %45, %372
>  %382 = fadd float %380, %381
>  %383 = fmul float %46, %377
>  %384 = fadd float %382, %383
>  br label %ENDIF
>
>ENDIF:                                            ; preds = %main_body, %IF
>  %temp.0 = phi float [ %186, %IF ], [ %43, %main_body ]
>  %temp1.0 = phi float [ %285, %IF ], [ %44, %main_body ]
>  %temp2.0 = phi float [ %384, %IF ], [ %45, %main_body ]
>  %385 = fmul float %temp.0, %11
>  %386 = fmul float %temp1.0, %12
>  %387 = fadd float %385, %386
>  %388 = fmul float %temp2.0, %13
>  %389 = fadd float %387, %388
>  %390 = fmul float %46, %14
>  %391 = fadd float %389, %390
>  %392 = fmul float %temp.0, %15
>  %393 = fmul float %temp1.0, %16
>  %394 = fadd float %392, %393
>  %395 = fmul float %temp2.0, %17
>  %396 = fadd float %394, %395
>  %397 = fmul float %46, %18
>  %398 = fadd float %396, %397
>  %399 = fmul float %temp.0, %19
>  %400 = fmul float %temp1.0, %20
>  %401 = fadd float %399, %400
>  %402 = fmul float %temp2.0, %21
>  %403 = fadd float %401, %402
>  %404 = fmul float %46, %22
>  %405 = fadd float %403, %404
>  %406 = fmul float %temp.0, %23
>  %407 = fmul float %temp1.0, %24
>  %408 = fadd float %406, %407
>  %409 = fmul float %temp2.0, %25
>  %410 = fadd float %408, %409
>  %411 = fmul float %46, %26
>  %412 = fadd float %410, %411
>  %413 = fmul float %temp.0, %35
>  %414 = fmul float %temp1.0, %36
>  %415 = fadd float %413, %414
>  %416 = fmul float %temp2.0, %37
>  %417 = fadd float %415, %416
>  %418 = fmul float %46, %38
>  %419 = fadd float %417, %418
>  %420 = fmul float %50, %27
>  %421 = fmul float %51, %28
>  %422 = fadd float %420, %421
>  %423 = fmul float %52, %29
>  %424 = fadd float %422, %423
>  %425 = fmul float %53, %30
>  %426 = fadd float %424, %425
>  %427 = fmul float %50, %31
>  %428 = fmul float %51, %32
>  %429 = fadd float %427, %428
>  %430 = fmul float %52, %33
>  %431 = fadd float %429, %430
>  %432 = fmul float %53, %34
>  %433 = fadd float %431, %432
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %426, float %433, float %419, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %391, float %398, float %405, float %412)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg51, %SGPR6_SGPR7 in %vreg54, %VGPR0 in %vreg56
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%70](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%61](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%VGPR41_VGPR42_VGPR43_VGPR44<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%52](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%VGPR4_VGPR5_VGPR6_VGPR7<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%43](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	%SGPR4<def> = S_MOV_B32 3840
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_SGPR %SGPR0_SGPR1_SGPR2_SGPR3, %SGPR4<kill>; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %SGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 39; mem:LD4[<unknown>]
>	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 38; mem:LD4[<unknown>]
>	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 37; mem:LD4[<unknown>]
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 36; mem:LD4[<unknown>]
>	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 35; mem:LD4[<unknown>]
>	%SGPR11<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 34; mem:LD4[<unknown>]
>	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 33; mem:LD4[<unknown>]
>	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 32; mem:LD4[<unknown>]
>	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31; mem:LD4[<unknown>]
>	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30; mem:LD4[<unknown>]
>	%SGPR16<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29; mem:LD4[<unknown>]
>	%SGPR17<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28; mem:LD4[<unknown>]
>	%SGPR18<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
>	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
>	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
>	%SGPR21<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
>	%SGPR22<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
>	%SGPR23<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
>	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
>	%SGPR25<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
>	%SGPR26<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	%SGPR27<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	%SGPR28<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	%SGPR29<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	%SGPR30<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	%SGPR31<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	%SGPR33<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR22<def> = V_MOV_B32_e32 %SGPR6<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MOV_B32_e32 %SGPR7<kill>, %EXEC<imp-use>
>	%VGPR39<def> = V_MOV_B32_e32 %SGPR8<kill>, %EXEC<imp-use>
>	%VGPR38<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR21<def> = V_MOV_B32_e32 %SGPR10<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_MOV_B32_e32 %SGPR11<kill>, %EXEC<imp-use>
>	%VGPR37<def> = V_MOV_B32_e32 %SGPR12<kill>, %EXEC<imp-use>
>	%VGPR36<def> = V_MOV_B32_e32 %SGPR13<kill>, %EXEC<imp-use>
>	%VGPR20<def> = V_MOV_B32_e32 %SGPR14<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MOV_B32_e32 %SGPR15<kill>, %EXEC<imp-use>
>	%VGPR35<def> = V_MOV_B32_e32 %SGPR16<kill>, %EXEC<imp-use>
>	%VGPR34<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>
>	%VGPR15<def> = V_MOV_B32_e32 %SGPR18<kill>, %EXEC<imp-use>
>	%VGPR19<def> = V_MOV_B32_e32 %SGPR19<kill>, %EXEC<imp-use>
>	%VGPR33<def> = V_MOV_B32_e32 %SGPR20<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_MOV_B32_e32 %SGPR21<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_MOV_B32_e32 %SGPR22<kill>, %EXEC<imp-use>
>	%VGPR18<def> = V_MOV_B32_e32 %SGPR23<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MOV_B32_e32 %SGPR24<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_MOV_B32_e32 %SGPR25<kill>, %EXEC<imp-use>
>	%VGPR13<def> = V_MOV_B32_e32 %SGPR26<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_MOV_B32_e32 %SGPR27<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MOV_B32_e32 %SGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MOV_B32_e32 %SGPR29<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MOV_B32_e32 %SGPR30<kill>, %EXEC<imp-use>
>	%VGPR16<def> = V_MOV_B32_e32 %SGPR31<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MOV_B32_e32 %SGPR32<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MOV_B32_e32 %SGPR33<kill>, %EXEC<imp-use>
>	%VGPR46<def> = V_MOV_B32_e32 %VGPR0, %EXEC<imp-use>
>	%VGPR45<def> = V_MOV_B32_e32 %VGPR1, %EXEC<imp-use>
>	%VGPR40<def> = V_MOV_B32_e32 %VGPR2, %EXEC<imp-use>
>	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
>	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
>	S_CBRANCH_EXECZ <BB#2>, %EXEC
>    Successors according to CFG: BB#1(16) BB#2(16)
>
>BB#1: derived from LLVM BB %IF
>    Live Ins: %SGPR0_SGPR1_SGPR2_SGPR3 %VGPR26 %VGPR27 %VGPR16 %VGPR12 %VGPR28 %VGPR29 %VGPR17 %VGPR13 %VGPR30 %VGPR31 %VGPR18 %VGPR14 %VGPR32 %VGPR33 %VGPR19 %VGPR15 %VGPR34 %VGPR35 %VGPR23 %VGPR20 %VGPR36 %VGPR37 %VGPR24 %VGPR21 %VGPR38 %VGPR39 %VGPR25 %VGPR22 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR41_VGPR42_VGPR43_VGPR44 %VGPR4_VGPR5_VGPR6_VGPR7 %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR4_SGPR5
>    Predecessors according to CFG: BB#0
>	%VGPR40<def> = V_MOV_B32_e32 2.550100e+02, %EXEC<imp-use>
>	%VGPR45<def> = V_MUL_F32_e32 %VGPR42, %VGPR40, %EXEC<imp-use>
>	%VGPR45<def> = V_CVT_I32_F32_e32 %VGPR45<kill>, %EXEC<imp-use>
>	%VGPR46<def> = V_MUL_LO_I32 %VGPR45<kill>, 3, 0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR45<def> = V_ADD_I32_e32 43, %VGPR46, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR45<def> = V_LSHLREV_B32_e32 4, %VGPR45<kill>, %EXEC<imp-use>
>	%VGPR47<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR45, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR48<def> = V_MUL_F32_e32 %VGPR41, %VGPR40, %EXEC<imp-use>
>	%VGPR48<def> = V_CVT_I32_F32_e32 %VGPR48<kill>, %EXEC<imp-use>
>	%VGPR48<def> = V_MUL_LO_I32 %VGPR48<kill>, 3, 0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR49<def> = V_ADD_I32_e32 43, %VGPR48, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR49<def> = V_LSHLREV_B32_e32 4, %VGPR49<kill>, %EXEC<imp-use>
>	%VGPR50<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR50<def> = V_MUL_F32_e32 %VGPR8, %VGPR50<kill>, %EXEC<imp-use>
>	%VGPR47<def> = V_MAD_F32 %VGPR47<kill>, %VGPR9, %VGPR50<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR50<def> = V_MUL_F32_e32 %VGPR43, %VGPR40, %EXEC<imp-use>
>	%VGPR50<def> = V_CVT_I32_F32_e32 %VGPR50<kill>, %EXEC<imp-use>
>	%VGPR50<def> = V_MUL_LO_I32 %VGPR50<kill>, 3, 0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR51<def> = V_ADD_I32_e32 43, %VGPR50, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR51<def> = V_LSHLREV_B32_e32 4, %VGPR51<kill>, %EXEC<imp-use>
>	%VGPR52<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR47<def> = V_MAD_F32 %VGPR52<kill>, %VGPR10, %VGPR47<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR40<def> = V_MUL_F32_e32 %VGPR44, %VGPR40<kill>, %EXEC<imp-use>, %VGPR41_VGPR42_VGPR43_VGPR44<imp-use,kill>
>	%VGPR40<def> = V_CVT_I32_F32_e32 %VGPR40<kill>, %EXEC<imp-use>
>	%VGPR41<def> = V_MUL_LO_I32 %VGPR40<kill>, 3, 0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR40<def> = V_ADD_I32_e32 43, %VGPR41, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR40<def> = V_LSHLREV_B32_e32 4, %VGPR40<kill>, %EXEC<imp-use>
>	%VGPR42<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR43<def> = V_ADD_F32_e64 %VGPR9, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR43<def> = V_ADD_F32_e32 %VGPR10, %VGPR43<kill>, %EXEC<imp-use>
>	%VGPR43<def> = V_SUB_F32_e32 1.000000e+00, %VGPR43<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR42<def> = V_MAD_F32 %VGPR42<kill>, %VGPR43, %VGPR47<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR44<def> = V_OR_B32_e32 4, %VGPR45, %EXEC<imp-use>
>	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR47<def> = V_OR_B32_e32 4, %VGPR49, %EXEC<imp-use>
>	%VGPR47<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR47<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR47<def> = V_MUL_F32_e32 %VGPR8, %VGPR47<kill>, %EXEC<imp-use>
>	%VGPR44<def> = V_MAD_F32 %VGPR44<kill>, %VGPR9, %VGPR47<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR47<def> = V_OR_B32_e32 4, %VGPR51, %EXEC<imp-use>
>	%VGPR47<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR47<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR44<def> = V_MAD_F32 %VGPR47<kill>, %VGPR10, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR47<def> = V_OR_B32_e32 4, %VGPR40, %EXEC<imp-use>
>	%VGPR47<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR47<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR44<def> = V_MAD_F32 %VGPR47<kill>, %VGPR43, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR44<def> = V_MUL_F32_e32 %VGPR1, %VGPR44<kill>, %EXEC<imp-use>
>	%VGPR42<def> = V_MAD_F32 %VGPR0, %VGPR42<kill>, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR44<def> = V_OR_B32_e32 8, %VGPR45, %EXEC<imp-use>
>	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR47<def> = V_OR_B32_e32 8, %VGPR49, %EXEC<imp-use>
>	%VGPR47<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR47<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR47<def> = V_MUL_F32_e32 %VGPR8, %VGPR47<kill>, %EXEC<imp-use>
>	%VGPR44<def> = V_MAD_F32 %VGPR44<kill>, %VGPR9, %VGPR47<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR47<def> = V_OR_B32_e32 8, %VGPR51, %EXEC<imp-use>
>	%VGPR47<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR47<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR44<def> = V_MAD_F32 %VGPR47<kill>, %VGPR10, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR47<def> = V_OR_B32_e32 8, %VGPR40, %EXEC<imp-use>
>	%VGPR47<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR47<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR44<def> = V_MAD_F32 %VGPR47<kill>, %VGPR43, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR42<def> = V_MAD_F32 %VGPR2, %VGPR44<kill>, %VGPR42<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR44<def> = V_OR_B32_e32 12, %VGPR45<kill>, %EXEC<imp-use>
>	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR45<def> = V_OR_B32_e32 12, %VGPR49<kill>, %EXEC<imp-use>
>	%VGPR45<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR45<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR45<def> = V_MUL_F32_e32 %VGPR8, %VGPR45<kill>, %EXEC<imp-use>
>	%VGPR44<def> = V_MAD_F32 %VGPR44<kill>, %VGPR9, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR45<def> = V_OR_B32_e32 12, %VGPR51<kill>, %EXEC<imp-use>
>	%VGPR45<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR45<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR44<def> = V_MAD_F32 %VGPR45<kill>, %VGPR10, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR40<def> = V_OR_B32_e32 12, %VGPR40<kill>, %EXEC<imp-use>
>	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR40<def> = V_MAD_F32 %VGPR40<kill>, %VGPR43, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR40<def> = V_MAD_F32 %VGPR3, %VGPR40<kill>, %VGPR42<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR42<def> = V_ADD_I32_e32 42, %VGPR46, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR42<def> = V_LSHLREV_B32_e32 4, %VGPR42<kill>, %EXEC<imp-use>
>	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR42, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR45<def> = V_ADD_I32_e32 42, %VGPR48, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR45<def> = V_LSHLREV_B32_e32 4, %VGPR45<kill>, %EXEC<imp-use>
>	%VGPR47<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR45, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR47<def> = V_MUL_F32_e32 %VGPR8, %VGPR47<kill>, %EXEC<imp-use>
>	%VGPR44<def> = V_MAD_F32 %VGPR44<kill>, %VGPR9, %VGPR47<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR47<def> = V_ADD_I32_e32 42, %VGPR50, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR47<def> = V_LSHLREV_B32_e32 4, %VGPR47<kill>, %EXEC<imp-use>
>	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR47, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR44<def> = V_MAD_F32 %VGPR49<kill>, %VGPR10, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR49<def> = V_ADD_I32_e32 42, %VGPR41, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR49<def> = V_LSHLREV_B32_e32 4, %VGPR49<kill>, %EXEC<imp-use>
>	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR44<def> = V_MAD_F32 %VGPR51<kill>, %VGPR43, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR51<def> = V_OR_B32_e32 4, %VGPR42, %EXEC<imp-use>
>	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR52<def> = V_OR_B32_e32 4, %VGPR45, %EXEC<imp-use>
>	%VGPR52<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR52<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR52<def> = V_MUL_F32_e32 %VGPR8, %VGPR52<kill>, %EXEC<imp-use>
>	%VGPR51<def> = V_MAD_F32 %VGPR51<kill>, %VGPR9, %VGPR52<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR52<def> = V_OR_B32_e32 4, %VGPR47, %EXEC<imp-use>
>	%VGPR52<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR52<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR51<def> = V_MAD_F32 %VGPR52<kill>, %VGPR10, %VGPR51<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR52<def> = V_OR_B32_e32 4, %VGPR49, %EXEC<imp-use>
>	%VGPR52<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR52<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR51<def> = V_MAD_F32 %VGPR52<kill>, %VGPR43, %VGPR51<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR51<def> = V_MUL_F32_e32 %VGPR1, %VGPR51<kill>, %EXEC<imp-use>
>	%VGPR44<def> = V_MAD_F32 %VGPR0, %VGPR44<kill>, %VGPR51<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR51<def> = V_OR_B32_e32 8, %VGPR42, %EXEC<imp-use>
>	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR52<def> = V_OR_B32_e32 8, %VGPR45, %EXEC<imp-use>
>	%VGPR52<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR52<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR52<def> = V_MUL_F32_e32 %VGPR8, %VGPR52<kill>, %EXEC<imp-use>
>	%VGPR51<def> = V_MAD_F32 %VGPR51<kill>, %VGPR9, %VGPR52<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR52<def> = V_OR_B32_e32 8, %VGPR47, %EXEC<imp-use>
>	%VGPR52<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR52<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR51<def> = V_MAD_F32 %VGPR52<kill>, %VGPR10, %VGPR51<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR52<def> = V_OR_B32_e32 8, %VGPR49, %EXEC<imp-use>
>	%VGPR52<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR52<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR51<def> = V_MAD_F32 %VGPR52<kill>, %VGPR43, %VGPR51<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR44<def> = V_MAD_F32 %VGPR2, %VGPR51<kill>, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR42<def> = V_OR_B32_e32 12, %VGPR42<kill>, %EXEC<imp-use>
>	%VGPR42<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR42<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR45<def> = V_OR_B32_e32 12, %VGPR45<kill>, %EXEC<imp-use>
>	%VGPR45<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR45<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR45<def> = V_MUL_F32_e32 %VGPR8, %VGPR45<kill>, %EXEC<imp-use>
>	%VGPR42<def> = V_MAD_F32 %VGPR42<kill>, %VGPR9, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR45<def> = V_OR_B32_e32 12, %VGPR47<kill>, %EXEC<imp-use>
>	%VGPR45<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR45<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR42<def> = V_MAD_F32 %VGPR45<kill>, %VGPR10, %VGPR42<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR45<def> = V_OR_B32_e32 12, %VGPR49<kill>, %EXEC<imp-use>
>	%VGPR45<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR45<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR42<def> = V_MAD_F32 %VGPR45<kill>, %VGPR43, %VGPR42<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR45<def> = V_MAD_F32 %VGPR3, %VGPR42<kill>, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR42<def> = V_ADD_I32_e32 41, %VGPR46<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR42<def> = V_LSHLREV_B32_e32 4, %VGPR42<kill>, %EXEC<imp-use>
>	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR42, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR46<def> = V_ADD_I32_e32 41, %VGPR48<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR46<def> = V_LSHLREV_B32_e32 4, %VGPR46<kill>, %EXEC<imp-use>
>	%VGPR47<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR46, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR47<def> = V_MUL_F32_e32 %VGPR8, %VGPR47<kill>, %EXEC<imp-use>
>	%VGPR44<def> = V_MAD_F32 %VGPR44<kill>, %VGPR9, %VGPR47<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR47<def> = V_ADD_I32_e32 41, %VGPR50<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR47<def> = V_LSHLREV_B32_e32 4, %VGPR47<kill>, %EXEC<imp-use>
>	%VGPR48<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR47, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR44<def> = V_MAD_F32 %VGPR48<kill>, %VGPR10, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR41<def> = V_ADD_I32_e32 41, %VGPR41<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
>	%VGPR41<def> = V_LSHLREV_B32_e32 4, %VGPR41<kill>, %EXEC<imp-use>
>	%VGPR48<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR41, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR44<def> = V_MAD_F32 %VGPR48<kill>, %VGPR43, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR48<def> = V_OR_B32_e32 4, %VGPR42, %EXEC<imp-use>
>	%VGPR48<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR48<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR49<def> = V_OR_B32_e32 4, %VGPR46, %EXEC<imp-use>
>	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR49<def> = V_MUL_F32_e32 %VGPR8, %VGPR49<kill>, %EXEC<imp-use>
>	%VGPR48<def> = V_MAD_F32 %VGPR48<kill>, %VGPR9, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR49<def> = V_OR_B32_e32 4, %VGPR47, %EXEC<imp-use>
>	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR48<def> = V_MAD_F32 %VGPR49<kill>, %VGPR10, %VGPR48<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR49<def> = V_OR_B32_e32 4, %VGPR41, %EXEC<imp-use>
>	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR48<def> = V_MAD_F32 %VGPR49<kill>, %VGPR43, %VGPR48<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR48<def> = V_MUL_F32_e32 %VGPR1, %VGPR48<kill>, %EXEC<imp-use>
>	%VGPR44<def> = V_MAD_F32 %VGPR0, %VGPR44<kill>, %VGPR48<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR48<def> = V_OR_B32_e32 8, %VGPR42, %EXEC<imp-use>
>	%VGPR48<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR48<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR49<def> = V_OR_B32_e32 8, %VGPR46, %EXEC<imp-use>
>	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR49<def> = V_MUL_F32_e32 %VGPR8, %VGPR49<kill>, %EXEC<imp-use>
>	%VGPR48<def> = V_MAD_F32 %VGPR48<kill>, %VGPR9, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR49<def> = V_OR_B32_e32 8, %VGPR47, %EXEC<imp-use>
>	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR48<def> = V_MAD_F32 %VGPR49<kill>, %VGPR10, %VGPR48<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR49<def> = V_OR_B32_e32 8, %VGPR41, %EXEC<imp-use>
>	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR48<def> = V_MAD_F32 %VGPR49<kill>, %VGPR43, %VGPR48<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR44<def> = V_MAD_F32 %VGPR2, %VGPR48<kill>, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR42<def> = V_OR_B32_e32 12, %VGPR42<kill>, %EXEC<imp-use>
>	%VGPR42<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR42<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	%VGPR46<def> = V_OR_B32_e32 12, %VGPR46<kill>, %EXEC<imp-use>
>	%VGPR46<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR46<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR46<def> = V_MUL_F32_e32 %VGPR8, %VGPR46<kill>, %EXEC<imp-use>
>	%VGPR42<def> = V_MAD_F32 %VGPR42<kill>, %VGPR9, %VGPR46<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR46<def> = V_OR_B32_e32 12, %VGPR47<kill>, %EXEC<imp-use>
>	%VGPR46<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR46<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR8<def> = V_MAD_F32 %VGPR46<kill>, %VGPR10, %VGPR42<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
>	%VGPR9<def> = V_OR_B32_e32 12, %VGPR41<kill>, %EXEC<imp-use>
>	%VGPR9<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR9<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
>	S_WAITCNT 1904
>	%VGPR8<def> = V_MAD_F32 %VGPR9<kill>, %VGPR43<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR46<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use,kill>
>    Successors according to CFG: BB#2
>
>BB#2: derived from LLVM BB %ENDIF
>    Live Ins: %VGPR26 %VGPR27 %VGPR16 %VGPR12 %VGPR28 %VGPR29 %VGPR17 %VGPR13 %VGPR30 %VGPR31 %VGPR18 %VGPR14 %VGPR32 %VGPR33 %VGPR19 %VGPR15 %VGPR34 %VGPR35 %VGPR23 %VGPR20 %VGPR36 %VGPR37 %VGPR24 %VGPR21 %VGPR38 %VGPR39 %VGPR25 %VGPR22 %VGPR4_VGPR5_VGPR6_VGPR7 %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR4_SGPR5 %VGPR46 %VGPR45 %VGPR40
>    Predecessors according to CFG: BB#0 BB#1
>	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
>	%VGPR8<def> = V_MUL_F32_e64 %VGPR45, %VGPR39<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR46, %VGPR38<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR40, %VGPR25<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR3, %VGPR22<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e64 %VGPR5, %VGPR37<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR4, %VGPR36<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR6, %VGPR24<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR7, %VGPR21<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_MUL_F32_e64 %VGPR5, %VGPR35<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_MAD_F32 %VGPR4, %VGPR34<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_MAD_F32 %VGPR6, %VGPR23<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR7, %VGPR20<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
>	%VGPR5<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
>	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR9<kill>, %VGPR8<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	S_WAITCNT 1807
>	%VGPR4<def> = V_MUL_F32_e64 %VGPR45, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR46, %VGPR32<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR40, %VGPR19<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR15<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e64 %VGPR45, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR46, %VGPR30<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR40, %VGPR18<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR14<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e64 %VGPR45, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR46, %VGPR28<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR40, %VGPR17<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR13<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e64 %VGPR45<kill>, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR46<kill>, %VGPR26<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR40<kill>, %VGPR16<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR12<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c084070c
>bf8c007f
>e00c2000
>80020800
>c0840708
>bf8c0070
>e00c2000
>80022900
>c0840704
>bf8c0070
>e00c2000
>80020400
>c0820700
>bf8c0070
>e00c2000
>80010000
>c0800100
>be8403ff
>00000f00
>bf8c0070
>c2020004
>bf8c007f
>d10a0004
>02010004
>c2030127
>c2038126
>c2040125
>c2048124
>c2050123
>c2058122
>c2060121
>c2068120
>c207011f
>c207811e
>c208011d
>c208811c
>c209010f
>c209810e
>c20a010d
>c20a810c
>c20b010b
>c20b810a
>c20c0109
>c20c8108
>c20d0107
>c20d8106
>c20e0105
>c20e8104
>c20f0103
>c20f8102
>c2100101
>c2108100
>bf8c007f
>7e2c0206
>7e320207
>7e4e0208
>7e4c0209
>7e2a020a
>7e30020b
>7e4a020c
>7e48020d
>7e28020e
>7e2e020f
>7e460210
>7e440211
>7e1e0212
>7e260213
>7e420214
>7e400215
>7e1c0216
>7e240217
>7e3e0218
>7e3c0219
>7e1a021a
>7e22021b
>7e3a021c
>7e38021d
>7e18021e
>7e20021f
>7e360220
>7e340221
>7e5c0300
>7e5a0301
>7e500302
>be842404
>8984047e
>bf88013f
>7e5002ff
>437f028f
>105a512a
>7e5a112d
>d2d6002e
>0201072d
>4a5a5cab
>345a5a84
>e0301000
>80002f2d
>10605129
>7e601130
>d2d60030
>02010730
>4a6260ab
>34626284
>e0301000
>80003231
>bf8c0770
>10646508
>d282002f
>04ca132f
>1064512b
>7e641132
>d2d60032
>02010732
>4a6664ab
>34666684
>e0301000
>80003433
>bf8c0770
>d282002f
>04be1534
>1050512c
>7e501128
>d2d60029
>02010728
>4a5052ab
>34505084
>e0301000
>80002a28
>d206002b
>02021109
>0656570a
>085656f2
>bf8c0770
>d282002a
>04be572a
>38585a84
>e0301000
>80002c2c
>385e6284
>e0301000
>80002f2f
>bf8c0770
>105e5f08
>d282002c
>04be132c
>385e6684
>e0301000
>80002f2f
>bf8c0770
>d282002c
>04b2152f
>385e5084
>e0301000
>80002f2f
>bf8c0770
>d282002c
>04b2572f
>10585901
>d282002a
>04b25500
>38585a88
>e0301000
>80002c2c
>385e6288
>e0301000
>80002f2f
>bf8c0770
>105e5f08
>d282002c
>04be132c
>385e6688
>e0301000
>80002f2f
>bf8c0770
>d282002c
>04b2152f
>385e5088
>e0301000
>80002f2f
>bf8c0770
>d282002c
>04b2572f
>d282002a
>04aa5902
>38585a8c
>e0301000
>80002c2c
>385a628c
>e0301000
>80002d2d
>bf8c0770
>105a5b08
>d282002c
>04b6132c
>385a668c
>e0301000
>80002d2d
>bf8c0770
>d282002c
>04b2152d
>3850508c
>e0301000
>80002828
>bf8c0770
>d2820028
>04b25728
>d2820028
>04aa5103
>4a545caa
>34545484
>e0301000
>80002c2a
>4a5a60aa
>345a5a84
>e0301000
>80002f2d
>bf8c0770
>105e5f08
>d282002c
>04be132c
>4a5e64aa
>345e5e84
>e0301000
>8000312f
>bf8c0770
>d282002c
>04b21531
>4a6252aa
>34626284
>e0301000
>80003331
>bf8c0770
>d282002c
>04b25733
>38665484
>e0301000
>80003333
>38685a84
>e0301000
>80003434
>bf8c0770
>10686908
>d2820033
>04d21333
>38685e84
>e0301000
>80003434
>bf8c0770
>d2820033
>04ce1534
>38686284
>e0301000
>80003434
>bf8c0770
>d2820033
>04ce5734
>10666701
>d282002c
>04ce5900
>38665488
>e0301000
>80003333
>38685a88
>e0301000
>80003434
>bf8c0770
>10686908
>d2820033
>04d21333
>38685e88
>e0301000
>80003434
>bf8c0770
>d2820033
>04ce1534
>38686288
>e0301000
>80003434
>bf8c0770
>d2820033
>04ce5734
>d282002c
>04b26702
>3854548c
>e0301000
>80002a2a
>385a5a8c
>e0301000
>80002d2d
>bf8c0770
>105a5b08
>d282002a
>04b6132a
>385a5e8c
>e0301000
>80002d2d
>bf8c0770
>d282002a
>04aa152d
>385a628c
>e0301000
>80002d2d
>bf8c0770
>d282002a
>04aa572d
>d282002d
>04b25503
>4a545ca9
>34545484
>e0301000
>80002c2a
>4a5c60a9
>345c5c84
>e0301000
>80002f2e
>bf8c0770
>105e5f08
>d282002c
>04be132c
>4a5e64a9
>345e5e84
>e0301000
>8000302f
>bf8c0770
>d282002c
>04b21530
>4a5252a9
>34525284
>e0301000
>80003029
>bf8c0770
>d282002c
>04b25730
>38605484
>e0301000
>80003030
>38625c84
>e0301000
>80003131
>bf8c0770
>10626308
>d2820030
>04c61330
>38625e84
>e0301000
>80003131
>bf8c0770
>d2820030
>04c21531
>38625284
>e0301000
>80003131
>bf8c0770
>d2820030
>04c25731
>10606101
>d282002c
>04c25900
>38605488
>e0301000
>80003030
>38625c88
>e0301000
>80003131
>bf8c0770
>10626308
>d2820030
>04c61330
>38625e88
>e0301000
>80003131
>bf8c0770
>d2820030
>04c21531
>38625288
>e0301000
>80003131
>bf8c0770
>d2820030
>04c25731
>d282002c
>04b26102
>3854548c
>e0301000
>80002a2a
>385c5c8c
>e0301000
>80002e2e
>bf8c0770
>105c5d08
>d282002a
>04ba132a
>385c5e8c
>e0301000
>80002e2e
>bf8c0770
>d2820008
>04aa152e
>3812528c
>e0301000
>80000909
>bf8c0770
>d2820008
>04225709
>d282002e
>04b21103
>88fe047e
>d2100008
>02024f2d
>d2820008
>04224d2e
>d2820008
>04223328
>d2820008
>04222d03
>d2100009
>02024b05
>d2820009
>04264904
>d2820009
>04263106
>d2820009
>04262b07
>d210000a
>02024705
>d282000a
>042a4504
>d282000a
>042a2f06
>d2820004
>042a2907
>7e0a02f2
>f800020f
>05080904
>bf8c070f
>d2100004
>0202432d
>d2820004
>0412412e
>d2820004
>04122728
>d2820004
>04121f03
>d2100005
>02023f2d
>d2820005
>04163d2e
>d2820005
>04162528
>d2820005
>04161d03
>d2100006
>02023b2d
>d2820006
>041a392e
>d2820006
>041a2328
>d2820006
>041a1b03
>d2100007
>0202372d
>d2820007
>041e352e
>d2820007
>041e2128
>d2820000
>041e1903
>f80008cf
>04050600
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
>  %25 = bitcast i32 %24 to float
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR6 in %vreg3
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR6
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>5e000101
>c8060102
>c80a0002
>5e020302
>f8001c0f
>00010001
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL TEMP[0..2], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
>  2: DP3 TEMP[0].x, TEMP[0].xyzz, CONST[0].xyzz
>  3: ABS TEMP[1].x, TEMP[0].xxxx
>  4: POW TEMP[1].x, TEMP[1].xxxx, CONST[0].wwww
>  5: SSG TEMP[2].x, TEMP[0].xxxx
>  6: MUL TEMP[0].x, TEMP[1].xxxx, TEMP[2].xxxx
>  7: MOV OUT[0], TEMP[0].xxxx
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %32 = bitcast float %30 to i32
>  %33 = bitcast float %31 to i32
>  %34 = insertelement <2 x i32> undef, i32 %32, i32 0
>  %35 = insertelement <2 x i32> %34, i32 %33, i32 1
>  %36 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = fmul float %37, %22
>  %41 = fmul float %38, %23
>  %42 = fadd float %41, %40
>  %43 = fmul float %39, %24
>  %44 = fadd float %42, %43
>  %45 = call float @fabs(float %44)
>  %46 = call float @llvm.pow.f32(float %45, float %25)
>  %47 = fcmp ugt float %44, 0.000000e+00
>  %48 = select i1 %47, float 1.000000e+00, float %44
>  %49 = fcmp uge float %48, 0.000000e+00
>  %50 = select i1 %49, float %48, float -1.000000e+00
>  %51 = fmul float %46, %50
>  %52 = call i32 @llvm.SI.packf16(float %51, float %51)
>  %53 = bitcast i32 %52 to float
>  %54 = call i32 @llvm.SI.packf16(float %51, float %51)
>  %55 = bitcast i32 %54 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %53, float %55, float %53, float %55)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #3
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%31](align=8)(tbaa=!"const")
>	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%28](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2<def> = IMAGE_SAMPLE_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e64 %VGPR0, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR1, %VGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR2, %VGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2<imp-use,kill>
>	%SGPR4_SGPR5<def> = V_CMP_GT_F32_e64 %VGPR0, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR0, 1.000000e+00, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR1, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 -1.000000e+00, %VGPR1<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_LOG_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_MUL_LEGACY_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_EXP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430002
>c0800100
>bf8c0070
>c2020100
>bf8c007f
>7e060204
>d2100003
>02020700
>c2020101
>bf8c007f
>7e080204
>d2820003
>040e0901
>c2020102
>bf8c007f
>7e080204
>d2820000
>040e0902
>d0080004
>02010100
>d2000001
>0011e500
>d00c0004
>02010101
>d2000001
>001202f3
>d2060100
>02010100
>7e004f00
>c2000103
>bf8c007f
>0e000000
>7e004b00
>10000300
>5e000100
>f8001c0f
>00000000
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	S_WAITCNT 1807
>	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
>	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
>	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020107
>bf8c007f
>7e080204
>c2020105
>bf8c007f
>7e0a0204
>d2820004
>04120b03
>c2020106
>bf8c007f
>7e0a0204
>c2020104
>bf8c007f
>7e0c0204
>d2820005
>04160d02
>c2020103
>bf8c007f
>7e0c0204
>c2020101
>bf8c007f
>7e0e0204
>d2820006
>041a0f03
>c2020102
>bf8c007f
>7e0e0204
>c2000100
>bf8c007f
>7e100200
>d2820007
>041e1102
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL TEMP[0..2], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
>  2: DP3 TEMP[0].x, TEMP[0].xyzz, CONST[0].xyzz
>  3: ABS TEMP[1].x, TEMP[0].xxxx
>  4: POW TEMP[1].x, TEMP[1].xxxx, CONST[0].wwww
>  5: SSG TEMP[2].x, TEMP[0].xxxx
>  6: MUL TEMP[0].x, TEMP[1].xxxx, TEMP[2].xxxx
>  7: MOV OUT[0], TEMP[0].xxxx
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %32 = bitcast float %30 to i32
>  %33 = bitcast float %31 to i32
>  %34 = insertelement <2 x i32> undef, i32 %32, i32 0
>  %35 = insertelement <2 x i32> %34, i32 %33, i32 1
>  %36 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = fmul float %37, %22
>  %41 = fmul float %38, %23
>  %42 = fadd float %41, %40
>  %43 = fmul float %39, %24
>  %44 = fadd float %42, %43
>  %45 = call float @fabs(float %44)
>  %46 = call float @llvm.pow.f32(float %45, float %25)
>  %47 = fcmp ugt float %44, 0.000000e+00
>  %48 = select i1 %47, float 1.000000e+00, float %44
>  %49 = fcmp uge float %48, 0.000000e+00
>  %50 = select i1 %49, float %48, float -1.000000e+00
>  %51 = fmul float %46, %50
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %51, float %51, float %51, float %51)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%31](align=8)(tbaa=!"const")
>	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%28](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2<def> = IMAGE_SAMPLE_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e64 %VGPR0, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR1, %VGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR2, %VGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2<imp-use,kill>
>	%SGPR4_SGPR5<def> = V_CMP_GT_F32_e64 %VGPR0, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR0, 1.000000e+00, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR1, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 -1.000000e+00, %VGPR1<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_LOG_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_MUL_LEGACY_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_EXP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	EXP 15, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430002
>c0800100
>bf8c0070
>c2020100
>bf8c007f
>7e060204
>d2100003
>02020700
>c2020101
>bf8c007f
>7e080204
>d2820003
>040e0901
>c2020102
>bf8c007f
>7e080204
>d2820000
>040e0902
>d0080004
>02010100
>d2000001
>0011e500
>d00c0004
>02010101
>d2000001
>001202f3
>d2060100
>02010100
>7e004f00
>c2000103
>bf8c007f
>0e000000
>7e004b00
>10000300
>f800180f
>00000000
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL CONST[0..6]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: DP4 TEMP[0].x, IN[0], CONST[0]
>  1: DP4 TEMP[1].x, IN[0], CONST[1]
>  2: MOV TEMP[0].y, TEMP[1].xxxx
>  3: DP4 TEMP[1].x, IN[0], CONST[2]
>  4: MOV TEMP[0].z, TEMP[1].xxxx
>  5: MOV TEMP[0].xyz, TEMP[0].xyzx
>  6: MOV TEMP[0].w, IMM[0].xxxx
>  7: DP4 TEMP[1].x, TEMP[0], CONST[3]
>  8: DP4 TEMP[2].x, TEMP[0], CONST[4]
>  9: MOV TEMP[1].y, TEMP[2].xxxx
> 10: DP4 TEMP[2].x, TEMP[0], CONST[5]
> 11: MOV TEMP[1].z, TEMP[2].xxxx
> 12: DP4 TEMP[0].x, TEMP[0], CONST[6]
> 13: MOV TEMP[1].w, TEMP[0].xxxx
> 14: MOV OUT[0], TEMP[1]
> 15: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
>  %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %40, i32 0, i32 %5)
>  %42 = extractelement <4 x float> %41, i32 0
>  %43 = extractelement <4 x float> %41, i32 1
>  %44 = extractelement <4 x float> %41, i32 2
>  %45 = extractelement <4 x float> %41, i32 3
>  %46 = fmul float %42, %11
>  %47 = fmul float %43, %12
>  %48 = fadd float %46, %47
>  %49 = fmul float %44, %13
>  %50 = fadd float %48, %49
>  %51 = fmul float %45, %14
>  %52 = fadd float %50, %51
>  %53 = fmul float %42, %15
>  %54 = fmul float %43, %16
>  %55 = fadd float %53, %54
>  %56 = fmul float %44, %17
>  %57 = fadd float %55, %56
>  %58 = fmul float %45, %18
>  %59 = fadd float %57, %58
>  %60 = fmul float %42, %19
>  %61 = fmul float %43, %20
>  %62 = fadd float %60, %61
>  %63 = fmul float %44, %21
>  %64 = fadd float %62, %63
>  %65 = fmul float %45, %22
>  %66 = fadd float %64, %65
>  %67 = fmul float %52, %23
>  %68 = fmul float %59, %24
>  %69 = fadd float %67, %68
>  %70 = fmul float %66, %25
>  %71 = fadd float %69, %70
>  %72 = fmul float 1.000000e+00, %26
>  %73 = fadd float %71, %72
>  %74 = fmul float %52, %27
>  %75 = fmul float %59, %28
>  %76 = fadd float %74, %75
>  %77 = fmul float %66, %29
>  %78 = fadd float %76, %77
>  %79 = fmul float 1.000000e+00, %30
>  %80 = fadd float %78, %79
>  %81 = fmul float %52, %31
>  %82 = fmul float %59, %32
>  %83 = fadd float %81, %82
>  %84 = fmul float %66, %33
>  %85 = fadd float %83, %84
>  %86 = fmul float 1.000000e+00, %34
>  %87 = fadd float %85, %86
>  %88 = fmul float %52, %35
>  %89 = fmul float %59, %36
>  %90 = fadd float %88, %89
>  %91 = fmul float %66, %37
>  %92 = fadd float %90, %91
>  %93 = fmul float 1.000000e+00, %38
>  %94 = fadd float %92, %93
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %73, float %80, float %87, float %94)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%42](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e64 %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR0, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR0, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e64 %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR0, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR1<def> = V_MAD_F32 %VGPR0, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR1<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MAD_F32 %VGPR0, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_MAD_F32 %VGPR0, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MAD_F32 %VGPR4<kill>, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 15; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020101
>bf8c007f
>7e080204
>d2100004
>02020901
>c2020100
>bf8c007f
>7e0a0204
>d2820004
>04120b00
>c2020102
>bf8c007f
>7e0a0204
>d2820004
>04120b02
>c2020103
>bf8c007f
>7e0a0204
>d2820004
>04120b03
>c2020105
>bf8c007f
>7e0a0204
>d2100005
>02020b01
>c2020104
>bf8c007f
>7e0c0204
>d2820005
>04160d00
>c2020106
>bf8c007f
>7e0c0204
>d2820005
>04160d02
>c2020107
>bf8c007f
>7e0c0204
>d2820005
>04160d03
>c2020119
>bf8c007f
>100c0a04
>c2020118
>bf8c007f
>d2820006
>04180904
>c2020109
>bf8c007f
>7e0e0204
>d2100007
>02020f01
>c2020108
>bf8c007f
>7e100204
>d2820007
>041e1100
>c202010a
>bf8c007f
>7e100204
>d2820007
>041e1102
>c202010b
>bf8c007f
>7e100204
>d2820000
>041e1103
>c202011a
>bf8c007f
>d2820001
>04180900
>c202011b
>bf8c007f
>06020204
>c2020115
>bf8c007f
>10040a04
>c2020114
>bf8c007f
>d2820002
>04080904
>c2020116
>bf8c007f
>d2820002
>04080900
>c2020117
>bf8c007f
>06040404
>c2020111
>bf8c007f
>10060a04
>c2020110
>bf8c007f
>d2820003
>040c0904
>c2020112
>bf8c007f
>d2820003
>040c0900
>c2020113
>bf8c007f
>06060604
>c202010d
>bf8c007f
>100a0a04
>c202010c
>bf8c007f
>d2820004
>04140904
>c202010e
>bf8c007f
>d2820000
>04100900
>c200010f
>bf8c007f
>06000000
>f80008cf
>01020300
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[0..223]
>DCL TEMP[0..26], LOCAL
>IMM[0] FLT32 {    0.0000,     0.5000,     0.9500,    -1.0000}
>IMM[1] FLT32 {    2.0000,    -2.0000,    -1.0000,     1.0000}
>IMM[2] FLT32 {    0.2500,     0.5000,    -0.5000,     4.0000}
>IMM[3] FLT32 {    0.0000,     1.0000,     2.0000,     3.0000}
>IMM[4] INT32 {1, -1, 0, 0}
>IMM[5] FLT32 {   16.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].x, IMM[0].xxxx
>  1: MAD TEMP[1].xy, IN[0].xyyy, CONST[4].xyyy, IMM[0].yyyy
>  2: FRC TEMP[2].xy, TEMP[1].xyyy
>  3: ADD TEMP[1].xy, TEMP[1].xyyy, -TEMP[2].xyyy
>  4: ADD TEMP[1].xy, TEMP[1].xyyy, IMM[0].yyyy
>  5: MUL TEMP[1].xy, TEMP[1].xyyy, CONST[4].zwww
>  6: MOV TEMP[2].xy, TEMP[1].xyyy
>  7: TEX TEMP[2].x, TEMP[2], SAMP[0], 2D
>  8: ABS TEMP[3].x, TEMP[2].xxxx
>  9: MAD TEMP[3].x, TEMP[3].xxxx, CONST[1].yyyy, -CONST[1].xxxx
> 10: FSLT TEMP[4].x, TEMP[2].xxxx, IMM[0].zzzz
> 11: UIF TEMP[4].xxxx :0
> 12:   MOV TEMP[4].z, TEMP[3].xxxx
> 13:   MAD TEMP[4].xy, TEMP[1].xyyy, IMM[1].xyyy, IMM[1].zwww
> 14:   ADD TEMP[5].xy, TEMP[4].xyyy, CONST[2].ywww
> 15:   MUL TEMP[5].xy, -TEMP[3].xxxx, TEMP[5].xyyy
> 16:   RCP TEMP[6].x, CONST[2].xxxx
> 17:   RCP TEMP[6].y, CONST[2].zzzz
> 18:   MUL TEMP[4].xy, TEMP[5].xyyy, TEMP[6].xyyy
> 19:   MOV TEMP[5].y, IMM[0].xxxx
> 20:   MOV TEMP[5].x, -CONST[4].zzzz
> 21:   MOV TEMP[5].z, CONST[4].zzzz
> 22:   ADD TEMP[5].xyz, TEMP[1].xyxx, TEMP[5].xyzz
> 23:   MOV TEMP[6].x, IMM[0].xxxx
> 24:   MOV TEMP[6].y, -CONST[4].wwww
> 25:   MOV TEMP[6].z, CONST[4].wwww
> 26:   ADD TEMP[6].xyz, TEMP[1].xyyy, TEMP[6].xyzz
> 27:   MOV TEMP[7].xy, TEMP[5].xyyy
> 28:   TEX TEMP[7].x, TEMP[7], SAMP[0], 2D
> 29:   MOV TEMP[7].x, TEMP[7].xxxx
> 30:   MOV TEMP[8].xy, TEMP[5].zyyy
> 31:   TEX TEMP[8].x, TEMP[8], SAMP[0], 2D
> 32:   MOV TEMP[7].y, TEMP[8].xxxx
> 33:   MOV TEMP[8].xy, TEMP[6].xyyy
> 34:   TEX TEMP[8].x, TEMP[8], SAMP[0], 2D
> 35:   MOV TEMP[7].z, TEMP[8].xxxx
> 36:   MOV TEMP[8].xy, TEMP[6].xzzz
> 37:   TEX TEMP[8].x, TEMP[8], SAMP[0], 2D
> 38:   MOV TEMP[7].w, TEMP[8].xxxx
> 39:   ABS TEMP[7], TEMP[7]
> 40:   MAD TEMP[7], TEMP[7], CONST[1].yyyy, -CONST[1].xxxx
> 41:   ADD TEMP[8], TEMP[7], -TEMP[3].xxxx
> 42:   ABS TEMP[8], TEMP[8]
> 43:   MOV TEMP[9].w, IMM[0].wwww
> 44:   MOV TEMP[9].xy, TEMP[5].xyxx
> 45:   MOV TEMP[9].z, TEMP[7].xxxx
> 46:   MOV TEMP[10].w, IMM[1].wwww
> 47:   MOV TEMP[10].xy, TEMP[5].zyzz
> 48:   MOV TEMP[10].z, TEMP[7].yyyy
> 49:   MOV TEMP[5].w, IMM[0].wwww
> 50:   MOV TEMP[5].xy, TEMP[6].xyxx
> 51:   MOV TEMP[5].z, TEMP[7].zzzz
> 52:   MOV TEMP[11].w, IMM[1].wwww
> 53:   MOV TEMP[11].xy, TEMP[6].xzxx
> 54:   MOV TEMP[11].z, TEMP[7].wwww
> 55:   FSLT TEMP[6].x, TEMP[8].xxxx, TEMP[8].yyyy
> 56:   UIF TEMP[6].xxxx :0
> 57:     MOV TEMP[6], TEMP[9]
> 58:   ELSE :0
> 59:     MOV TEMP[6], TEMP[10]
> 60:   ENDIF
> 61:   FSLT TEMP[7].x, TEMP[8].zzzz, TEMP[8].wwww
> 62:   UIF TEMP[7].xxxx :0
> 63:     MOV TEMP[5], TEMP[5]
> 64:   ELSE :0
> 65:     MOV TEMP[5], TEMP[11]
> 66:   ENDIF
> 67:   MOV TEMP[7].z, TEMP[6].zzzz
> 68:   MAD TEMP[7].xy, TEMP[6].xyyy, IMM[1].xyyy, IMM[1].zwww
> 69:   ADD TEMP[8].xy, TEMP[7].xyyy, CONST[2].ywww
> 70:   MUL TEMP[8].xy, -TEMP[6].zzzz, TEMP[8].xyyy
> 71:   RCP TEMP[9].x, CONST[2].xxxx
> 72:   RCP TEMP[9].y, CONST[2].zzzz
> 73:   MUL TEMP[7].xy, TEMP[8].xyyy, TEMP[9].xyyy
> 74:   MOV TEMP[8].z, TEMP[5].zzzz
> 75:   MAD TEMP[8].xy, TEMP[5].xyyy, IMM[1].xyyy, IMM[1].zwww
> 76:   ADD TEMP[9].xy, TEMP[8].xyyy, CONST[2].ywww
> 77:   MUL TEMP[9].xy, -TEMP[5].zzzz, TEMP[9].xyyy
> 78:   RCP TEMP[10].x, CONST[2].xxxx
> 79:   RCP TEMP[10].y, CONST[2].zzzz
> 80:   MUL TEMP[8].xy, TEMP[9].xyyy, TEMP[10].xyyy
> 81:   ADD TEMP[7].xyz, TEMP[7].xyzz, -TEMP[4].xyzz
> 82:   MUL TEMP[6].xyz, TEMP[7].xyzz, TEMP[6].wwww
> 83:   ADD TEMP[7].xyz, TEMP[8].xyzz, -TEMP[4].xyzz
> 84:   MUL TEMP[5].xyz, TEMP[7].xyzz, TEMP[5].wwww
> 85:   MUL TEMP[7].xyz, TEMP[5].zxyy, TEMP[6].yzxx
> 86:   MAD TEMP[5].xyz, TEMP[5].yzxx, TEMP[6].zxyy, -TEMP[7].xyzz
> 87:   DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
> 88:   RSQ TEMP[6].x, TEMP[6].xxxx
> 89:   MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx
> 90:   MUL TEMP[6].xyz, TEMP[5].xyzz, TEMP[3].xxxx
> 91:   MUL TEMP[6].xyz, TEMP[6].xyzz, CONST[0].zzzz
> 92:   ADD TEMP[4].xyz, TEMP[4].xyzz, -TEMP[6].xyzz
> 93:   MUL TEMP[6].xy, CONST[3].xyyy, IMM[2].xxxx
> 94:   MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[6].xyyy
> 95:   MOV TEMP[1].xy, TEMP[1].xyyy
> 96:   TEX TEMP[1].xyz, TEMP[1], SAMP[1], 2D
> 97:   MAD TEMP[1].xyz, TEMP[1].xyzz, IMM[1].xxxx, IMM[0].wwww
> 98:   MUL TEMP[1].xyz, TEMP[1].xyzz, CONST[0].wwww
> 99:   ADD TEMP[6].x, -TEMP[3].xxxx, -CONST[5].xxxx
>100:   MUL_SAT TEMP[6].x, TEMP[6].xxxx, CONST[5].wwww
>101:   MAD TEMP[6].x, CONST[5].zzzz, TEMP[6].xxxx, IMM[1].wwww
>102:   MUL_SAT TEMP[3].x, -TEMP[3].xxxx, CONST[5].yyyy
>103:   MUL TEMP[3].x, TEMP[6].xxxx, TEMP[3].xxxx
>104:   FSLT TEMP[6].x, TEMP[2].xxxx, IMM[0].xxxx
>105:   UIF TEMP[6].xxxx :0
>106:     MOV TEMP[6].x, CONST[6].xxxx
>107:   ELSE :0
>108:     MOV TEMP[6].x, TEMP[3].xxxx
>109:   ENDIF
>110:   MUL TEMP[3].x, TEMP[6].xxxx, CONST[6].zzzz
>111:   MUL TEMP[6].x, CONST[0].yyyy, TEMP[3].xxxx
>112:   FSGE TEMP[7].x, TEMP[2].xxxx, IMM[0].xxxx
>113:   AND TEMP[7].x, TEMP[7].xxxx, IMM[1].wwww
>114:   MUL TEMP[8], TEMP[6].xxxx, IMM[3]
>115:   MAD TEMP[3], CONST[0].xxxx, TEMP[3].xxxx, -TEMP[8]
>116:   DP3 TEMP[8].x, TEMP[1].xyzz, CONST[7].xyzz
>117:   MUL TEMP[8].xyz, TEMP[8].xxxx, TEMP[1].xyzz
>118:   MUL TEMP[8].xyz, IMM[1].xxxx, TEMP[8].xyzz
>119:   ADD TEMP[8].xyz, CONST[7].xyzz, -TEMP[8].xyzz
>120:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[3].xxxx
>121:   DP3 TEMP[9].x, TEMP[1].xyzz, CONST[8].xyzz
>122:   MUL TEMP[9].xyz, TEMP[9].xxxx, TEMP[1].xyzz
>123:   MUL TEMP[9].xyz, IMM[1].xxxx, TEMP[9].xyzz
>124:   ADD TEMP[9].xyz, CONST[8].xyzz, -TEMP[9].xyzz
>125:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[3].yyyy
>126:   DP3 TEMP[10].x, TEMP[1].xyzz, CONST[9].xyzz
>127:   MUL TEMP[10].xyz, TEMP[10].xxxx, TEMP[1].xyzz
>128:   MUL TEMP[10].xyz, IMM[1].xxxx, TEMP[10].xyzz
>129:   ADD TEMP[10].xyz, CONST[9].xyzz, -TEMP[10].xyzz
>130:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[3].zzzz
>131:   DP3 TEMP[11].x, TEMP[1].xyzz, CONST[10].xyzz
>132:   MUL TEMP[11].xyz, TEMP[11].xxxx, TEMP[1].xyzz
>133:   MUL TEMP[11].xyz, IMM[1].xxxx, TEMP[11].xyzz
>134:   ADD TEMP[11].xyz, CONST[10].xyzz, -TEMP[11].xyzz
>135:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[3].wwww
>136:   DP3 TEMP[12].x, TEMP[8].xyzz, TEMP[5].xyzz
>137:   DP3 TEMP[13].x, TEMP[9].xyzz, TEMP[5].xyzz
>138:   DP3 TEMP[14].x, TEMP[10].xyzz, TEMP[5].xyzz
>139:   DP3 TEMP[15].x, TEMP[11].xyzz, TEMP[5].xyzz
>140:   FSGE TEMP[12].x, TEMP[12].xxxx, IMM[0].xxxx
>141:   UIF TEMP[12].xxxx :0
>142:     MOV TEMP[12].x, IMM[4].xxxx
>143:   ELSE :0
>144:     MOV TEMP[12].x, IMM[4].yyyy
>145:   ENDIF
>146:   I2F TEMP[12].x, TEMP[12].xxxx
>147:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[12].xxxx
>148:   FSGE TEMP[12].x, TEMP[13].xxxx, IMM[0].xxxx
>149:   UIF TEMP[12].xxxx :0
>150:     MOV TEMP[12].x, IMM[4].xxxx
>151:   ELSE :0
>152:     MOV TEMP[12].x, IMM[4].yyyy
>153:   ENDIF
>154:   I2F TEMP[12].x, TEMP[12].xxxx
>155:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[12].xxxx
>156:   FSGE TEMP[12].x, TEMP[14].xxxx, IMM[0].xxxx
>157:   UIF TEMP[12].xxxx :0
>158:     MOV TEMP[12].x, IMM[4].xxxx
>159:   ELSE :0
>160:     MOV TEMP[12].x, IMM[4].yyyy
>161:   ENDIF
>162:   I2F TEMP[12].x, TEMP[12].xxxx
>163:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[12].xxxx
>164:   FSGE TEMP[12].x, TEMP[15].xxxx, IMM[0].xxxx
>165:   UIF TEMP[12].xxxx :0
>166:     MOV TEMP[12].x, IMM[4].xxxx
>167:   ELSE :0
>168:     MOV TEMP[12].x, IMM[4].yyyy
>169:   ENDIF
>170:   I2F TEMP[12].x, TEMP[12].xxxx
>171:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[12].xxxx
>172:   ADD TEMP[12].xy, TEMP[4].xyyy, TEMP[8].xyyy
>173:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[9].xyyy
>174:   MOV TEMP[12].zw, TEMP[13].yyxy
>175:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[10].xyyy
>176:   ADD TEMP[14].xy, TEMP[4].xyyy, TEMP[11].xyyy
>177:   MOV TEMP[13].zw, TEMP[14].yyxy
>178:   ADD TEMP[14].x, TEMP[4].zzzz, TEMP[8].zzzz
>179:   ADD TEMP[15].x, TEMP[4].zzzz, TEMP[9].zzzz
>180:   MOV TEMP[14].y, TEMP[15].xxxx
>181:   ADD TEMP[16].x, TEMP[4].zzzz, TEMP[10].zzzz
>182:   MOV TEMP[14].z, TEMP[16].xxxx
>183:   ADD TEMP[17].x, TEMP[4].zzzz, TEMP[11].zzzz
>184:   MOV TEMP[14].w, TEMP[17].xxxx
>185:   RCP TEMP[18].xy, -TEMP[14].xxxx
>186:   RCP TEMP[18].zw, -TEMP[15].xxxx
>187:   MUL TEMP[15], TEMP[12], TEMP[18]
>188:   MAD TEMP[15], TEMP[15], CONST[2].xzxz, -CONST[2].ywyw
>189:   RCP TEMP[16].xy, -TEMP[16].xxxx
>190:   RCP TEMP[16].zw, -TEMP[17].xxxx
>191:   MUL TEMP[16], TEMP[13], TEMP[16]
>192:   MAD TEMP[16], TEMP[16], CONST[2].xzxz, -CONST[2].ywyw
>193:   MAD TEMP[15], TEMP[15], IMM[2].yzyz, IMM[0].yyyy
>194:   MAD TEMP[16], TEMP[16], IMM[2].yzyz, IMM[0].yyyy
>195:   MOV_SAT TEMP[17], TEMP[15]
>196:   MOV_SAT TEMP[18], TEMP[16]
>197:   MOV TEMP[19].xy, TEMP[17].xyyy
>198:   TEX TEMP[19].x, TEMP[19], SAMP[0], 2D
>199:   MOV TEMP[20].x, TEMP[19].xxxx
>200:   MOV TEMP[17].xy, TEMP[17].zwww
>201:   TEX TEMP[17].x, TEMP[17], SAMP[0], 2D
>202:   MOV TEMP[20].y, TEMP[17].xxxx
>203:   MOV TEMP[21].xy, TEMP[18].xyyy
>204:   TEX TEMP[21].x, TEMP[21], SAMP[0], 2D
>205:   MOV TEMP[20].z, TEMP[21].xxxx
>206:   MOV TEMP[18].xy, TEMP[18].zwww
>207:   TEX TEMP[18].x, TEMP[18], SAMP[0], 2D
>208:   MOV TEMP[20].w, TEMP[18].xxxx
>209:   ABS TEMP[20], TEMP[20]
>210:   MAD TEMP[20], TEMP[20], CONST[1].yyyy, -CONST[1].xxxx
>211:   ADD TEMP[22], TEMP[20], -TEMP[14]
>212:   MUL TEMP[23], TEMP[3], IMM[1].xxxx
>213:   FSGE TEMP[24].x, TEMP[22].xxxx, TEMP[23].xxxx
>214:   AND TEMP[24].x, TEMP[24].xxxx, IMM[1].wwww
>215:   FSGE TEMP[25].x, TEMP[22].yyyy, TEMP[23].yyyy
>216:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
>217:   MOV TEMP[24].y, TEMP[25].xxxx
>218:   FSGE TEMP[25].x, TEMP[22].zzzz, TEMP[23].zzzz
>219:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
>220:   MOV TEMP[24].z, TEMP[25].xxxx
>221:   FSGE TEMP[23].x, TEMP[22].wwww, TEMP[23].wwww
>222:   AND TEMP[23].x, TEMP[23].xxxx, IMM[1].wwww
>223:   MOV TEMP[24].w, TEMP[23].xxxx
>224:   FSEQ TEMP[23].x, TEMP[20].xxxx, IMM[0].xxxx
>225:   UIF TEMP[23].xxxx :0
>226:     MOV TEMP[23].x, IMM[4].xxxx
>227:   ELSE :0
>228:     MOV TEMP[23].x, IMM[4].zzzz
>229:   ENDIF
>230:   FSEQ TEMP[25].x, TEMP[20].yyyy, IMM[0].xxxx
>231:   UIF TEMP[25].xxxx :0
>232:     MOV TEMP[25].x, IMM[4].xxxx
>233:   ELSE :0
>234:     MOV TEMP[25].x, IMM[4].zzzz
>235:   ENDIF
>236:   FSEQ TEMP[26].x, TEMP[20].zzzz, IMM[0].xxxx
>237:   UIF TEMP[26].xxxx :0
>238:     MOV TEMP[26].x, IMM[4].xxxx
>239:   ELSE :0
>240:     MOV TEMP[26].x, IMM[4].zzzz
>241:   ENDIF
>242:   FSEQ TEMP[20].x, TEMP[20].wwww, IMM[0].xxxx
>243:   UIF TEMP[20].xxxx :0
>244:     MOV TEMP[20].x, IMM[4].xxxx
>245:   ELSE :0
>246:     MOV TEMP[20].x, IMM[4].zzzz
>247:   ENDIF
>248:   I2F TEMP[23].x, TEMP[23].xxxx
>249:   I2F TEMP[25].x, TEMP[25].xxxx
>250:   MOV TEMP[23].y, TEMP[25].xxxx
>251:   I2F TEMP[25].x, TEMP[26].xxxx
>252:   MOV TEMP[23].z, TEMP[25].xxxx
>253:   I2F TEMP[20].x, TEMP[20].xxxx
>254:   MOV TEMP[23].w, TEMP[20].xxxx
>255:   FSGE TEMP[19].x, IMM[0].xxxx, TEMP[19].xxxx
>256:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>257:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[17].xxxx
>258:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>259:   MOV TEMP[19].y, TEMP[17].xxxx
>260:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[21].xxxx
>261:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>262:   MOV TEMP[19].z, TEMP[17].xxxx
>263:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[18].xxxx
>264:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>265:   MOV TEMP[19].w, TEMP[17].xxxx
>266:   ADD TEMP[17], TEMP[24], TEMP[23]
>267:   MAD_SAT TEMP[17], TEMP[19], TEMP[7].xxxx, TEMP[17]
>268:   DP4 TEMP[2].x, TEMP[17], IMM[1].wwww
>269:   FSGE TEMP[18].x, TEMP[22].xxxx, IMM[0].xxxx
>270:   AND TEMP[18].x, TEMP[18].xxxx, IMM[1].wwww
>271:   FSGE TEMP[19].x, TEMP[22].yyyy, IMM[0].xxxx
>272:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>273:   MOV TEMP[18].y, TEMP[19].xxxx
>274:   FSGE TEMP[19].x, TEMP[22].zzzz, IMM[0].xxxx
>275:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>276:   MOV TEMP[18].z, TEMP[19].xxxx
>277:   FSGE TEMP[19].x, TEMP[22].wwww, IMM[0].xxxx
>278:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>279:   MOV TEMP[18].w, TEMP[19].xxxx
>280:   ADD TEMP[17], IMM[1].wwww, -TEMP[17]
>281:   MUL TEMP[17], TEMP[18], TEMP[17]
>282:   DP4 TEMP[0].x, TEMP[17], IMM[1].wwww
>283:   MUL TEMP[17].x, TEMP[6].xxxx, IMM[2].wwww
>284:   ADD TEMP[3], TEMP[3], -TEMP[17].xxxx
>285:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[11].xyzz
>286:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>287:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>288:   ADD TEMP[17].xyz, CONST[11].xyzz, -TEMP[17].xyzz
>289:   MUL TEMP[8].xyz, TEMP[17].xyzz, TEMP[3].xxxx
>290:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[12].xyzz
>291:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>292:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>293:   ADD TEMP[17].xyz, CONST[12].xyzz, -TEMP[17].xyzz
>294:   MUL TEMP[9].xyz, TEMP[17].xyzz, TEMP[3].yyyy
>295:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[13].xyzz
>296:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>297:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>298:   ADD TEMP[17].xyz, CONST[13].xyzz, -TEMP[17].xyzz
>299:   MUL TEMP[10].xyz, TEMP[17].xyzz, TEMP[3].zzzz
>300:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[14].xyzz
>301:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>302:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>303:   ADD TEMP[17].xyz, CONST[14].xyzz, -TEMP[17].xyzz
>304:   MUL TEMP[11].xyz, TEMP[17].xyzz, TEMP[3].wwww
>305:   DP3 TEMP[17].x, TEMP[8].xyzz, TEMP[5].xyzz
>306:   DP3 TEMP[18].x, TEMP[9].xyzz, TEMP[5].xyzz
>307:   DP3 TEMP[19].x, TEMP[10].xyzz, TEMP[5].xyzz
>308:   DP3 TEMP[20].x, TEMP[11].xyzz, TEMP[5].xyzz
>309:   FSGE TEMP[17].x, TEMP[17].xxxx, IMM[0].xxxx
>310:   UIF TEMP[17].xxxx :0
>311:     MOV TEMP[17].x, IMM[4].xxxx
>312:   ELSE :0
>313:     MOV TEMP[17].x, IMM[4].yyyy
>314:   ENDIF
>315:   I2F TEMP[17].x, TEMP[17].xxxx
>316:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[17].xxxx
>317:   FSGE TEMP[17].x, TEMP[18].xxxx, IMM[0].xxxx
>318:   UIF TEMP[17].xxxx :0
>319:     MOV TEMP[17].x, IMM[4].xxxx
>320:   ELSE :0
>321:     MOV TEMP[17].x, IMM[4].yyyy
>322:   ENDIF
>323:   I2F TEMP[17].x, TEMP[17].xxxx
>324:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[17].xxxx
>325:   FSGE TEMP[17].x, TEMP[19].xxxx, IMM[0].xxxx
>326:   UIF TEMP[17].xxxx :0
>327:     MOV TEMP[17].x, IMM[4].xxxx
>328:   ELSE :0
>329:     MOV TEMP[17].x, IMM[4].yyyy
>330:   ENDIF
>331:   I2F TEMP[17].x, TEMP[17].xxxx
>332:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[17].xxxx
>333:   FSGE TEMP[17].x, TEMP[20].xxxx, IMM[0].xxxx
>334:   UIF TEMP[17].xxxx :0
>335:     MOV TEMP[17].x, IMM[4].xxxx
>336:   ELSE :0
>337:     MOV TEMP[17].x, IMM[4].yyyy
>338:   ENDIF
>339:   I2F TEMP[17].x, TEMP[17].xxxx
>340:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[17].xxxx
>341:   ADD TEMP[12].xy, TEMP[4].xyyy, TEMP[8].xyyy
>342:   ADD TEMP[17].xy, TEMP[4].xyyy, TEMP[9].xyyy
>343:   MOV TEMP[12].zw, TEMP[17].yyxy
>344:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[10].xyyy
>345:   ADD TEMP[17].xy, TEMP[4].xyyy, TEMP[11].xyyy
>346:   MOV TEMP[13].zw, TEMP[17].yyxy
>347:   ADD TEMP[14].x, TEMP[4].zzzz, TEMP[8].zzzz
>348:   ADD TEMP[17].x, TEMP[4].zzzz, TEMP[9].zzzz
>349:   MOV TEMP[14].y, TEMP[17].xxxx
>350:   ADD TEMP[18].x, TEMP[4].zzzz, TEMP[10].zzzz
>351:   MOV TEMP[14].z, TEMP[18].xxxx
>352:   ADD TEMP[19].x, TEMP[4].zzzz, TEMP[11].zzzz
>353:   MOV TEMP[14].w, TEMP[19].xxxx
>354:   RCP TEMP[20].xy, -TEMP[14].xxxx
>355:   RCP TEMP[20].zw, -TEMP[17].xxxx
>356:   MUL TEMP[17], TEMP[12], TEMP[20]
>357:   MAD TEMP[15], TEMP[17], CONST[2].xzxz, -CONST[2].ywyw
>358:   RCP TEMP[17].xy, -TEMP[18].xxxx
>359:   RCP TEMP[17].zw, -TEMP[19].xxxx
>360:   MUL TEMP[17], TEMP[13], TEMP[17]
>361:   MAD TEMP[16], TEMP[17], CONST[2].xzxz, -CONST[2].ywyw
>362:   MAD TEMP[15], TEMP[15], IMM[2].yzyz, IMM[0].yyyy
>363:   MAD TEMP[16], TEMP[16], IMM[2].yzyz, IMM[0].yyyy
>364:   MOV_SAT TEMP[17], TEMP[15]
>365:   MOV_SAT TEMP[18], TEMP[16]
>366:   MOV TEMP[19].xy, TEMP[17].xyyy
>367:   TEX TEMP[19].x, TEMP[19], SAMP[0], 2D
>368:   MOV TEMP[20].x, TEMP[19].xxxx
>369:   MOV TEMP[17].xy, TEMP[17].zwww
>370:   TEX TEMP[17].x, TEMP[17], SAMP[0], 2D
>371:   MOV TEMP[20].y, TEMP[17].xxxx
>372:   MOV TEMP[21].xy, TEMP[18].xyyy
>373:   TEX TEMP[21].x, TEMP[21], SAMP[0], 2D
>374:   MOV TEMP[20].z, TEMP[21].xxxx
>375:   MOV TEMP[18].xy, TEMP[18].zwww
>376:   TEX TEMP[18].x, TEMP[18], SAMP[0], 2D
>377:   MOV TEMP[20].w, TEMP[18].xxxx
>378:   ABS TEMP[20], TEMP[20]
>379:   MAD TEMP[20], TEMP[20], CONST[1].yyyy, -CONST[1].xxxx
>380:   ADD TEMP[22], TEMP[20], -TEMP[14]
>381:   MUL TEMP[23], TEMP[3], IMM[1].xxxx
>382:   FSGE TEMP[24].x, TEMP[22].xxxx, TEMP[23].xxxx
>383:   AND TEMP[24].x, TEMP[24].xxxx, IMM[1].wwww
>384:   FSGE TEMP[25].x, TEMP[22].yyyy, TEMP[23].yyyy
>385:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
>386:   MOV TEMP[24].y, TEMP[25].xxxx
>387:   FSGE TEMP[25].x, TEMP[22].zzzz, TEMP[23].zzzz
>388:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
>389:   MOV TEMP[24].z, TEMP[25].xxxx
>390:   FSGE TEMP[23].x, TEMP[22].wwww, TEMP[23].wwww
>391:   AND TEMP[23].x, TEMP[23].xxxx, IMM[1].wwww
>392:   MOV TEMP[24].w, TEMP[23].xxxx
>393:   FSEQ TEMP[23].x, TEMP[20].xxxx, IMM[0].xxxx
>394:   UIF TEMP[23].xxxx :0
>395:     MOV TEMP[23].x, IMM[4].xxxx
>396:   ELSE :0
>397:     MOV TEMP[23].x, IMM[4].zzzz
>398:   ENDIF
>399:   FSEQ TEMP[25].x, TEMP[20].yyyy, IMM[0].xxxx
>400:   UIF TEMP[25].xxxx :0
>401:     MOV TEMP[25].x, IMM[4].xxxx
>402:   ELSE :0
>403:     MOV TEMP[25].x, IMM[4].zzzz
>404:   ENDIF
>405:   FSEQ TEMP[26].x, TEMP[20].zzzz, IMM[0].xxxx
>406:   UIF TEMP[26].xxxx :0
>407:     MOV TEMP[26].x, IMM[4].xxxx
>408:   ELSE :0
>409:     MOV TEMP[26].x, IMM[4].zzzz
>410:   ENDIF
>411:   FSEQ TEMP[20].x, TEMP[20].wwww, IMM[0].xxxx
>412:   UIF TEMP[20].xxxx :0
>413:     MOV TEMP[20].x, IMM[4].xxxx
>414:   ELSE :0
>415:     MOV TEMP[20].x, IMM[4].zzzz
>416:   ENDIF
>417:   I2F TEMP[23].x, TEMP[23].xxxx
>418:   I2F TEMP[25].x, TEMP[25].xxxx
>419:   MOV TEMP[23].y, TEMP[25].xxxx
>420:   I2F TEMP[25].x, TEMP[26].xxxx
>421:   MOV TEMP[23].z, TEMP[25].xxxx
>422:   I2F TEMP[20].x, TEMP[20].xxxx
>423:   MOV TEMP[23].w, TEMP[20].xxxx
>424:   FSGE TEMP[19].x, IMM[0].xxxx, TEMP[19].xxxx
>425:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>426:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[17].xxxx
>427:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>428:   MOV TEMP[19].y, TEMP[17].xxxx
>429:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[21].xxxx
>430:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>431:   MOV TEMP[19].z, TEMP[17].xxxx
>432:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[18].xxxx
>433:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>434:   MOV TEMP[19].w, TEMP[17].xxxx
>435:   ADD TEMP[17], TEMP[24], TEMP[23]
>436:   MAD_SAT TEMP[17], TEMP[19], TEMP[7].xxxx, TEMP[17]
>437:   DP4 TEMP[18].x, TEMP[17], IMM[1].wwww
>438:   ADD TEMP[2].x, TEMP[2].xxxx, TEMP[18].xxxx
>439:   FSGE TEMP[18].x, TEMP[22].xxxx, IMM[0].xxxx
>440:   AND TEMP[18].x, TEMP[18].xxxx, IMM[1].wwww
>441:   FSGE TEMP[19].x, TEMP[22].yyyy, IMM[0].xxxx
>442:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>443:   MOV TEMP[18].y, TEMP[19].xxxx
>444:   FSGE TEMP[19].x, TEMP[22].zzzz, IMM[0].xxxx
>445:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>446:   MOV TEMP[18].z, TEMP[19].xxxx
>447:   FSGE TEMP[19].x, TEMP[22].wwww, IMM[0].xxxx
>448:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>449:   MOV TEMP[18].w, TEMP[19].xxxx
>450:   ADD TEMP[17], IMM[1].wwww, -TEMP[17]
>451:   MUL TEMP[17], TEMP[18], TEMP[17]
>452:   DP4 TEMP[17].x, TEMP[17], IMM[1].wwww
>453:   ADD TEMP[0].x, TEMP[0].xxxx, TEMP[17].xxxx
>454:   MUL TEMP[17].x, TEMP[6].xxxx, IMM[2].wwww
>455:   ADD TEMP[3], TEMP[3], -TEMP[17].xxxx
>456:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[15].xyzz
>457:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>458:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>459:   ADD TEMP[17].xyz, CONST[15].xyzz, -TEMP[17].xyzz
>460:   MUL TEMP[8].xyz, TEMP[17].xyzz, TEMP[3].xxxx
>461:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[16].xyzz
>462:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>463:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>464:   ADD TEMP[17].xyz, CONST[16].xyzz, -TEMP[17].xyzz
>465:   MUL TEMP[9].xyz, TEMP[17].xyzz, TEMP[3].yyyy
>466:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[17].xyzz
>467:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>468:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>469:   ADD TEMP[17].xyz, CONST[17].xyzz, -TEMP[17].xyzz
>470:   MUL TEMP[10].xyz, TEMP[17].xyzz, TEMP[3].zzzz
>471:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[18].xyzz
>472:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>473:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>474:   ADD TEMP[17].xyz, CONST[18].xyzz, -TEMP[17].xyzz
>475:   MUL TEMP[11].xyz, TEMP[17].xyzz, TEMP[3].wwww
>476:   DP3 TEMP[17].x, TEMP[8].xyzz, TEMP[5].xyzz
>477:   DP3 TEMP[18].x, TEMP[9].xyzz, TEMP[5].xyzz
>478:   DP3 TEMP[19].x, TEMP[10].xyzz, TEMP[5].xyzz
>479:   DP3 TEMP[20].x, TEMP[11].xyzz, TEMP[5].xyzz
>480:   FSGE TEMP[17].x, TEMP[17].xxxx, IMM[0].xxxx
>481:   UIF TEMP[17].xxxx :0
>482:     MOV TEMP[17].x, IMM[4].xxxx
>483:   ELSE :0
>484:     MOV TEMP[17].x, IMM[4].yyyy
>485:   ENDIF
>486:   I2F TEMP[17].x, TEMP[17].xxxx
>487:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[17].xxxx
>488:   FSGE TEMP[17].x, TEMP[18].xxxx, IMM[0].xxxx
>489:   UIF TEMP[17].xxxx :0
>490:     MOV TEMP[17].x, IMM[4].xxxx
>491:   ELSE :0
>492:     MOV TEMP[17].x, IMM[4].yyyy
>493:   ENDIF
>494:   I2F TEMP[17].x, TEMP[17].xxxx
>495:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[17].xxxx
>496:   FSGE TEMP[17].x, TEMP[19].xxxx, IMM[0].xxxx
>497:   UIF TEMP[17].xxxx :0
>498:     MOV TEMP[17].x, IMM[4].xxxx
>499:   ELSE :0
>500:     MOV TEMP[17].x, IMM[4].yyyy
>501:   ENDIF
>502:   I2F TEMP[17].x, TEMP[17].xxxx
>503:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[17].xxxx
>504:   FSGE TEMP[17].x, TEMP[20].xxxx, IMM[0].xxxx
>505:   UIF TEMP[17].xxxx :0
>506:     MOV TEMP[17].x, IMM[4].xxxx
>507:   ELSE :0
>508:     MOV TEMP[17].x, IMM[4].yyyy
>509:   ENDIF
>510:   I2F TEMP[17].x, TEMP[17].xxxx
>511:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[17].xxxx
>512:   ADD TEMP[12].xy, TEMP[4].xyyy, TEMP[8].xyyy
>513:   ADD TEMP[17].xy, TEMP[4].xyyy, TEMP[9].xyyy
>514:   MOV TEMP[12].zw, TEMP[17].yyxy
>515:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[10].xyyy
>516:   ADD TEMP[17].xy, TEMP[4].xyyy, TEMP[11].xyyy
>517:   MOV TEMP[13].zw, TEMP[17].yyxy
>518:   ADD TEMP[14].x, TEMP[4].zzzz, TEMP[8].zzzz
>519:   ADD TEMP[17].x, TEMP[4].zzzz, TEMP[9].zzzz
>520:   MOV TEMP[14].y, TEMP[17].xxxx
>521:   ADD TEMP[18].x, TEMP[4].zzzz, TEMP[10].zzzz
>522:   MOV TEMP[14].z, TEMP[18].xxxx
>523:   ADD TEMP[19].x, TEMP[4].zzzz, TEMP[11].zzzz
>524:   MOV TEMP[14].w, TEMP[19].xxxx
>525:   RCP TEMP[20].xy, -TEMP[14].xxxx
>526:   RCP TEMP[20].zw, -TEMP[17].xxxx
>527:   MUL TEMP[17], TEMP[12], TEMP[20]
>528:   MAD TEMP[15], TEMP[17], CONST[2].xzxz, -CONST[2].ywyw
>529:   RCP TEMP[17].xy, -TEMP[18].xxxx
>530:   RCP TEMP[17].zw, -TEMP[19].xxxx
>531:   MUL TEMP[17], TEMP[13], TEMP[17]
>532:   MAD TEMP[16], TEMP[17], CONST[2].xzxz, -CONST[2].ywyw
>533:   MAD TEMP[15], TEMP[15], IMM[2].yzyz, IMM[0].yyyy
>534:   MAD TEMP[16], TEMP[16], IMM[2].yzyz, IMM[0].yyyy
>535:   MOV_SAT TEMP[17], TEMP[15]
>536:   MOV_SAT TEMP[18], TEMP[16]
>537:   MOV TEMP[19].xy, TEMP[17].xyyy
>538:   TEX TEMP[19].x, TEMP[19], SAMP[0], 2D
>539:   MOV TEMP[20].x, TEMP[19].xxxx
>540:   MOV TEMP[17].xy, TEMP[17].zwww
>541:   TEX TEMP[17].x, TEMP[17], SAMP[0], 2D
>542:   MOV TEMP[20].y, TEMP[17].xxxx
>543:   MOV TEMP[21].xy, TEMP[18].xyyy
>544:   TEX TEMP[21].x, TEMP[21], SAMP[0], 2D
>545:   MOV TEMP[20].z, TEMP[21].xxxx
>546:   MOV TEMP[18].xy, TEMP[18].zwww
>547:   TEX TEMP[18].x, TEMP[18], SAMP[0], 2D
>548:   MOV TEMP[20].w, TEMP[18].xxxx
>549:   ABS TEMP[20], TEMP[20]
>550:   MAD TEMP[20], TEMP[20], CONST[1].yyyy, -CONST[1].xxxx
>551:   ADD TEMP[22], TEMP[20], -TEMP[14]
>552:   MUL TEMP[23], TEMP[3], IMM[1].xxxx
>553:   FSGE TEMP[24].x, TEMP[22].xxxx, TEMP[23].xxxx
>554:   AND TEMP[24].x, TEMP[24].xxxx, IMM[1].wwww
>555:   FSGE TEMP[25].x, TEMP[22].yyyy, TEMP[23].yyyy
>556:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
>557:   MOV TEMP[24].y, TEMP[25].xxxx
>558:   FSGE TEMP[25].x, TEMP[22].zzzz, TEMP[23].zzzz
>559:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
>560:   MOV TEMP[24].z, TEMP[25].xxxx
>561:   FSGE TEMP[23].x, TEMP[22].wwww, TEMP[23].wwww
>562:   AND TEMP[23].x, TEMP[23].xxxx, IMM[1].wwww
>563:   MOV TEMP[24].w, TEMP[23].xxxx
>564:   FSEQ TEMP[23].x, TEMP[20].xxxx, IMM[0].xxxx
>565:   UIF TEMP[23].xxxx :0
>566:     MOV TEMP[23].x, IMM[4].xxxx
>567:   ELSE :0
>568:     MOV TEMP[23].x, IMM[4].zzzz
>569:   ENDIF
>570:   FSEQ TEMP[25].x, TEMP[20].yyyy, IMM[0].xxxx
>571:   UIF TEMP[25].xxxx :0
>572:     MOV TEMP[25].x, IMM[4].xxxx
>573:   ELSE :0
>574:     MOV TEMP[25].x, IMM[4].zzzz
>575:   ENDIF
>576:   FSEQ TEMP[26].x, TEMP[20].zzzz, IMM[0].xxxx
>577:   UIF TEMP[26].xxxx :0
>578:     MOV TEMP[26].x, IMM[4].xxxx
>579:   ELSE :0
>580:     MOV TEMP[26].x, IMM[4].zzzz
>581:   ENDIF
>582:   FSEQ TEMP[20].x, TEMP[20].wwww, IMM[0].xxxx
>583:   UIF TEMP[20].xxxx :0
>584:     MOV TEMP[20].x, IMM[4].xxxx
>585:   ELSE :0
>586:     MOV TEMP[20].x, IMM[4].zzzz
>587:   ENDIF
>588:   I2F TEMP[23].x, TEMP[23].xxxx
>589:   I2F TEMP[25].x, TEMP[25].xxxx
>590:   MOV TEMP[23].y, TEMP[25].xxxx
>591:   I2F TEMP[25].x, TEMP[26].xxxx
>592:   MOV TEMP[23].z, TEMP[25].xxxx
>593:   I2F TEMP[20].x, TEMP[20].xxxx
>594:   MOV TEMP[23].w, TEMP[20].xxxx
>595:   FSGE TEMP[19].x, IMM[0].xxxx, TEMP[19].xxxx
>596:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>597:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[17].xxxx
>598:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>599:   MOV TEMP[19].y, TEMP[17].xxxx
>600:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[21].xxxx
>601:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>602:   MOV TEMP[19].z, TEMP[17].xxxx
>603:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[18].xxxx
>604:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>605:   MOV TEMP[19].w, TEMP[17].xxxx
>606:   ADD TEMP[17], TEMP[24], TEMP[23]
>607:   MAD_SAT TEMP[17], TEMP[19], TEMP[7].xxxx, TEMP[17]
>608:   DP4 TEMP[18].x, TEMP[17], IMM[1].wwww
>609:   ADD TEMP[2].x, TEMP[2].xxxx, TEMP[18].xxxx
>610:   FSGE TEMP[18].x, TEMP[22].xxxx, IMM[0].xxxx
>611:   AND TEMP[18].x, TEMP[18].xxxx, IMM[1].wwww
>612:   FSGE TEMP[19].x, TEMP[22].yyyy, IMM[0].xxxx
>613:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>614:   MOV TEMP[18].y, TEMP[19].xxxx
>615:   FSGE TEMP[19].x, TEMP[22].zzzz, IMM[0].xxxx
>616:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>617:   MOV TEMP[18].z, TEMP[19].xxxx
>618:   FSGE TEMP[19].x, TEMP[22].wwww, IMM[0].xxxx
>619:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>620:   MOV TEMP[18].w, TEMP[19].xxxx
>621:   ADD TEMP[17], IMM[1].wwww, -TEMP[17]
>622:   MUL TEMP[17], TEMP[18], TEMP[17]
>623:   DP4 TEMP[17].x, TEMP[17], IMM[1].wwww
>624:   ADD TEMP[0].x, TEMP[0].xxxx, TEMP[17].xxxx
>625:   MUL TEMP[6].x, TEMP[6].xxxx, IMM[2].wwww
>626:   ADD TEMP[3], TEMP[3], -TEMP[6].xxxx
>627:   DP3 TEMP[6].x, TEMP[1].xyzz, CONST[19].xyzz
>628:   MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[1].xyzz
>629:   MUL TEMP[6].xyz, IMM[1].xxxx, TEMP[6].xyzz
>630:   ADD TEMP[6].xyz, CONST[19].xyzz, -TEMP[6].xyzz
>631:   MUL TEMP[8].xyz, TEMP[6].xyzz, TEMP[3].xxxx
>632:   DP3 TEMP[6].x, TEMP[1].xyzz, CONST[20].xyzz
>633:   MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[1].xyzz
>634:   MUL TEMP[6].xyz, IMM[1].xxxx, TEMP[6].xyzz
>635:   ADD TEMP[6].xyz, CONST[20].xyzz, -TEMP[6].xyzz
>636:   MUL TEMP[9].xyz, TEMP[6].xyzz, TEMP[3].yyyy
>637:   DP3 TEMP[6].x, TEMP[1].xyzz, CONST[21].xyzz
>638:   MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[1].xyzz
>639:   MUL TEMP[6].xyz, IMM[1].xxxx, TEMP[6].xyzz
>640:   ADD TEMP[6].xyz, CONST[21].xyzz, -TEMP[6].xyzz
>641:   MUL TEMP[10].xyz, TEMP[6].xyzz, TEMP[3].zzzz
>642:   DP3 TEMP[6].x, TEMP[1].xyzz, CONST[22].xyzz
>643:   MUL TEMP[1].xyz, TEMP[6].xxxx, TEMP[1].xyzz
>644:   MUL TEMP[1].xyz, IMM[1].xxxx, TEMP[1].xyzz
>645:   ADD TEMP[1].xyz, CONST[22].xyzz, -TEMP[1].xyzz
>646:   MUL TEMP[11].xyz, TEMP[1].xyzz, TEMP[3].wwww
>647:   DP3 TEMP[1].x, TEMP[8].xyzz, TEMP[5].xyzz
>648:   DP3 TEMP[6].x, TEMP[9].xyzz, TEMP[5].xyzz
>649:   DP3 TEMP[17].x, TEMP[10].xyzz, TEMP[5].xyzz
>650:   DP3 TEMP[5].x, TEMP[11].xyzz, TEMP[5].xyzz
>651:   FSGE TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx
>652:   UIF TEMP[1].xxxx :0
>653:     MOV TEMP[1].x, IMM[4].xxxx
>654:   ELSE :0
>655:     MOV TEMP[1].x, IMM[4].yyyy
>656:   ENDIF
>657:   I2F TEMP[1].x, TEMP[1].xxxx
>658:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[1].xxxx
>659:   FSGE TEMP[1].x, TEMP[6].xxxx, IMM[0].xxxx
>660:   UIF TEMP[1].xxxx :0
>661:     MOV TEMP[1].x, IMM[4].xxxx
>662:   ELSE :0
>663:     MOV TEMP[1].x, IMM[4].yyyy
>664:   ENDIF
>665:   I2F TEMP[1].x, TEMP[1].xxxx
>666:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[1].xxxx
>667:   FSGE TEMP[1].x, TEMP[17].xxxx, IMM[0].xxxx
>668:   UIF TEMP[1].xxxx :0
>669:     MOV TEMP[1].x, IMM[4].xxxx
>670:   ELSE :0
>671:     MOV TEMP[1].x, IMM[4].yyyy
>672:   ENDIF
>673:   I2F TEMP[1].x, TEMP[1].xxxx
>674:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[1].xxxx
>675:   FSGE TEMP[1].x, TEMP[5].xxxx, IMM[0].xxxx
>676:   UIF TEMP[1].xxxx :0
>677:     MOV TEMP[1].x, IMM[4].xxxx
>678:   ELSE :0
>679:     MOV TEMP[1].x, IMM[4].yyyy
>680:   ENDIF
>681:   I2F TEMP[1].x, TEMP[1].xxxx
>682:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[1].xxxx
>683:   ADD TEMP[12].xy, TEMP[4].xyyy, TEMP[8].xyyy
>684:   ADD TEMP[1].xy, TEMP[4].xyyy, TEMP[9].xyyy
>685:   MOV TEMP[12].zw, TEMP[1].yyxy
>686:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[10].xyyy
>687:   ADD TEMP[1].xy, TEMP[4].xyyy, TEMP[11].xyyy
>688:   MOV TEMP[13].zw, TEMP[1].yyxy
>689:   ADD TEMP[14].x, TEMP[4].zzzz, TEMP[8].zzzz
>690:   ADD TEMP[1].x, TEMP[4].zzzz, TEMP[9].zzzz
>691:   MOV TEMP[14].y, TEMP[1].xxxx
>692:   ADD TEMP[5].x, TEMP[4].zzzz, TEMP[10].zzzz
>693:   MOV TEMP[14].z, TEMP[5].xxxx
>694:   ADD TEMP[4].x, TEMP[4].zzzz, TEMP[11].zzzz
>695:   MOV TEMP[14].w, TEMP[4].xxxx
>696:   RCP TEMP[6].xy, -TEMP[14].xxxx
>697:   RCP TEMP[6].zw, -TEMP[1].xxxx
>698:   MUL TEMP[1], TEMP[12], TEMP[6]
>699:   MAD TEMP[15], TEMP[1], CONST[2].xzxz, -CONST[2].ywyw
>700:   RCP TEMP[1].xy, -TEMP[5].xxxx
>701:   RCP TEMP[1].zw, -TEMP[4].xxxx
>702:   MUL TEMP[1], TEMP[13], TEMP[1]
>703:   MAD TEMP[16], TEMP[1], CONST[2].xzxz, -CONST[2].ywyw
>704:   MAD TEMP[15], TEMP[15], IMM[2].yzyz, IMM[0].yyyy
>705:   MAD TEMP[16], TEMP[16], IMM[2].yzyz, IMM[0].yyyy
>706:   MOV_SAT TEMP[1], TEMP[15]
>707:   MOV_SAT TEMP[4], TEMP[16]
>708:   MOV TEMP[5].xy, TEMP[1].xyyy
>709:   TEX TEMP[5].x, TEMP[5], SAMP[0], 2D
>710:   MOV TEMP[6].x, TEMP[5].xxxx
>711:   MOV TEMP[1].xy, TEMP[1].zwww
>712:   TEX TEMP[1].x, TEMP[1], SAMP[0], 2D
>713:   MOV TEMP[6].y, TEMP[1].xxxx
>714:   MOV TEMP[8].xy, TEMP[4].xyyy
>715:   TEX TEMP[8].x, TEMP[8], SAMP[0], 2D
>716:   MOV TEMP[6].z, TEMP[8].xxxx
>717:   MOV TEMP[4].xy, TEMP[4].zwww
>718:   TEX TEMP[4].x, TEMP[4], SAMP[0], 2D
>719:   MOV TEMP[6].w, TEMP[4].xxxx
>720:   ABS TEMP[6], TEMP[6]
>721:   MAD TEMP[6], TEMP[6], CONST[1].yyyy, -CONST[1].xxxx
>722:   ADD TEMP[9], TEMP[6], -TEMP[14]
>723:   MUL TEMP[3], TEMP[3], IMM[1].xxxx
>724:   FSGE TEMP[10].x, TEMP[9].xxxx, TEMP[3].xxxx
>725:   AND TEMP[10].x, TEMP[10].xxxx, IMM[1].wwww
>726:   FSGE TEMP[11].x, TEMP[9].yyyy, TEMP[3].yyyy
>727:   AND TEMP[11].x, TEMP[11].xxxx, IMM[1].wwww
>728:   MOV TEMP[10].y, TEMP[11].xxxx
>729:   FSGE TEMP[11].x, TEMP[9].zzzz, TEMP[3].zzzz
>730:   AND TEMP[11].x, TEMP[11].xxxx, IMM[1].wwww
>731:   MOV TEMP[10].z, TEMP[11].xxxx
>732:   FSGE TEMP[3].x, TEMP[9].wwww, TEMP[3].wwww
>733:   AND TEMP[3].x, TEMP[3].xxxx, IMM[1].wwww
>734:   MOV TEMP[10].w, TEMP[3].xxxx
>735:   FSEQ TEMP[3].x, TEMP[6].xxxx, IMM[0].xxxx
>736:   UIF TEMP[3].xxxx :0
>737:     MOV TEMP[3].x, IMM[4].xxxx
>738:   ELSE :0
>739:     MOV TEMP[3].x, IMM[4].zzzz
>740:   ENDIF
>741:   FSEQ TEMP[11].x, TEMP[6].yyyy, IMM[0].xxxx
>742:   UIF TEMP[11].xxxx :0
>743:     MOV TEMP[11].x, IMM[4].xxxx
>744:   ELSE :0
>745:     MOV TEMP[11].x, IMM[4].zzzz
>746:   ENDIF
>747:   FSEQ TEMP[12].x, TEMP[6].zzzz, IMM[0].xxxx
>748:   UIF TEMP[12].xxxx :0
>749:     MOV TEMP[12].x, IMM[4].xxxx
>750:   ELSE :0
>751:     MOV TEMP[12].x, IMM[4].zzzz
>752:   ENDIF
>753:   FSEQ TEMP[6].x, TEMP[6].wwww, IMM[0].xxxx
>754:   UIF TEMP[6].xxxx :0
>755:     MOV TEMP[6].x, IMM[4].xxxx
>756:   ELSE :0
>757:     MOV TEMP[6].x, IMM[4].zzzz
>758:   ENDIF
>759:   I2F TEMP[3].x, TEMP[3].xxxx
>760:   I2F TEMP[11].x, TEMP[11].xxxx
>761:   MOV TEMP[3].y, TEMP[11].xxxx
>762:   I2F TEMP[11].x, TEMP[12].xxxx
>763:   MOV TEMP[3].z, TEMP[11].xxxx
>764:   I2F TEMP[6].x, TEMP[6].xxxx
>765:   MOV TEMP[3].w, TEMP[6].xxxx
>766:   FSGE TEMP[5].x, IMM[0].xxxx, TEMP[5].xxxx
>767:   AND TEMP[5].x, TEMP[5].xxxx, IMM[1].wwww
>768:   FSGE TEMP[1].x, IMM[0].xxxx, TEMP[1].xxxx
>769:   AND TEMP[1].x, TEMP[1].xxxx, IMM[1].wwww
>770:   MOV TEMP[5].y, TEMP[1].xxxx
>771:   FSGE TEMP[1].x, IMM[0].xxxx, TEMP[8].xxxx
>772:   AND TEMP[1].x, TEMP[1].xxxx, IMM[1].wwww
>773:   MOV TEMP[5].z, TEMP[1].xxxx
>774:   FSGE TEMP[1].x, IMM[0].xxxx, TEMP[4].xxxx
>775:   AND TEMP[1].x, TEMP[1].xxxx, IMM[1].wwww
>776:   MOV TEMP[5].w, TEMP[1].xxxx
>777:   ADD TEMP[1], TEMP[10], TEMP[3]
>778:   MAD_SAT TEMP[1], TEMP[5], TEMP[7].xxxx, TEMP[1]
>779:   DP4 TEMP[3].x, TEMP[1], IMM[1].wwww
>780:   ADD TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
>781:   FSGE TEMP[3].x, TEMP[9].xxxx, IMM[0].xxxx
>782:   AND TEMP[3].x, TEMP[3].xxxx, IMM[1].wwww
>783:   FSGE TEMP[4].x, TEMP[9].yyyy, IMM[0].xxxx
>784:   AND TEMP[4].x, TEMP[4].xxxx, IMM[1].wwww
>785:   MOV TEMP[3].y, TEMP[4].xxxx
>786:   FSGE TEMP[4].x, TEMP[9].zzzz, IMM[0].xxxx
>787:   AND TEMP[4].x, TEMP[4].xxxx, IMM[1].wwww
>788:   MOV TEMP[3].z, TEMP[4].xxxx
>789:   FSGE TEMP[4].x, TEMP[9].wwww, IMM[0].xxxx
>790:   AND TEMP[4].x, TEMP[4].xxxx, IMM[1].wwww
>791:   MOV TEMP[3].w, TEMP[4].xxxx
>792:   ADD TEMP[1], IMM[1].wwww, -TEMP[1]
>793:   MUL TEMP[1], TEMP[3], TEMP[1]
>794:   DP4 TEMP[1].x, TEMP[1], IMM[1].wwww
>795:   ADD TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
>796:   ADD TEMP[1].x, IMM[5].xxxx, -TEMP[2].xxxx
>797:   RCP TEMP[1].x, TEMP[1].xxxx
>798:   MUL TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
>799: ENDIF
>800: MUL_SAT TEMP[0].x, TEMP[0].xxxx, CONST[6].yyyy
>801: ADD TEMP[0].x, IMM[1].wwww, -TEMP[0].xxxx
>802: MOV TEMP[1].xyz, IMM[0].xxxx
>803: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx
>804: MOV TEMP[1].w, TEMP[0].xxxx
>805: MOV OUT[0], TEMP[1]
>806: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %21, i32 92)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %21, i32 100)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %21, i32 104)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %21, i32 116)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %21, i32 120)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %21, i32 136)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %21, i32 144)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %21, i32 148)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %21, i32 152)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %21, i32 160)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %21, i32 168)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %21, i32 180)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %21, i32 208)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %21, i32 212)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %21, i32 216)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %21, i32 224)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %21, i32 228)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %21, i32 232)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %21, i32 240)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %21, i32 244)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %21, i32 248)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %21, i32 264)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %21, i32 304)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %21, i32 308)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %21, i32 312)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %21, i32 320)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %21, i32 324)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %21, i32 328)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %21, i32 336)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %21, i32 340)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %21, i32 344)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %21, i32 360)
>  %93 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %94 = load <32 x i8> addrspace(2)* %93, !tbaa !0
>  %95 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %96 = load <16 x i8> addrspace(2)* %95, !tbaa !0
>  %97 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %98 = load <32 x i8> addrspace(2)* %97, !tbaa !0
>  %99 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %100 = load <16 x i8> addrspace(2)* %99, !tbaa !0
>  %101 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %102 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %103 = fmul float %101, %34
>  %104 = fadd float %103, 5.000000e-01
>  %105 = fmul float %102, %35
>  %106 = fadd float %105, 5.000000e-01
>  %107 = call float @llvm.AMDIL.fraction.(float %104)
>  %108 = call float @llvm.AMDIL.fraction.(float %106)
>  %109 = fsub float -0.000000e+00, %107
>  %110 = fadd float %104, %109
>  %111 = fsub float -0.000000e+00, %108
>  %112 = fadd float %106, %111
>  %113 = fadd float %110, 5.000000e-01
>  %114 = fadd float %112, 5.000000e-01
>  %115 = fmul float %113, %36
>  %116 = fmul float %114, %37
>  %117 = bitcast float %115 to i32
>  %118 = bitcast float %116 to i32
>  %119 = insertelement <2 x i32> undef, i32 %117, i32 0
>  %120 = insertelement <2 x i32> %119, i32 %118, i32 1
>  %121 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %120, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %122 = extractelement <4 x float> %121, i32 0
>  %123 = call float @fabs(float %122)
>  %124 = fsub float -0.000000e+00, %26
>  %125 = fmul float %123, %27
>  %126 = fadd float %125, %124
>  %127 = fcmp olt float %122, 0x3FEE666660000000
>  %128 = sext i1 %127 to i32
>  %129 = bitcast i32 %128 to float
>  %130 = bitcast float %129 to i32
>  %131 = icmp ne i32 %130, 0
>  br i1 %131, label %IF, label %ENDIF
>
>IF:                                               ; preds = %main_body
>  %132 = fmul float %115, 2.000000e+00
>  %133 = fadd float %132, -1.000000e+00
>  %134 = fmul float %116, -2.000000e+00
>  %135 = fadd float %134, 1.000000e+00
>  %136 = fadd float %133, %29
>  %137 = fadd float %135, %31
>  %138 = fsub float -0.000000e+00, %126
>  %139 = fmul float %138, %136
>  %140 = fsub float -0.000000e+00, %126
>  %141 = fmul float %140, %137
>  %142 = fdiv float 1.000000e+00, %28
>  %143 = fdiv float 1.000000e+00, %30
>  %144 = fmul float %139, %142
>  %145 = fmul float %141, %143
>  %146 = fsub float -0.000000e+00, %36
>  %147 = fadd float %115, %146
>  %148 = fadd float %116, 0.000000e+00
>  %149 = fadd float %115, %36
>  %150 = fsub float -0.000000e+00, %37
>  %151 = fadd float %115, 0.000000e+00
>  %152 = fadd float %116, %150
>  %153 = fadd float %116, %37
>  %154 = bitcast float %147 to i32
>  %155 = bitcast float %148 to i32
>  %156 = insertelement <2 x i32> undef, i32 %154, i32 0
>  %157 = insertelement <2 x i32> %156, i32 %155, i32 1
>  %158 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %157, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %159 = extractelement <4 x float> %158, i32 0
>  %160 = bitcast float %149 to i32
>  %161 = bitcast float %148 to i32
>  %162 = insertelement <2 x i32> undef, i32 %160, i32 0
>  %163 = insertelement <2 x i32> %162, i32 %161, i32 1
>  %164 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %163, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %165 = extractelement <4 x float> %164, i32 0
>  %166 = bitcast float %151 to i32
>  %167 = bitcast float %152 to i32
>  %168 = insertelement <2 x i32> undef, i32 %166, i32 0
>  %169 = insertelement <2 x i32> %168, i32 %167, i32 1
>  %170 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %169, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %171 = extractelement <4 x float> %170, i32 0
>  %172 = bitcast float %151 to i32
>  %173 = bitcast float %153 to i32
>  %174 = insertelement <2 x i32> undef, i32 %172, i32 0
>  %175 = insertelement <2 x i32> %174, i32 %173, i32 1
>  %176 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %175, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %177 = extractelement <4 x float> %176, i32 0
>  %178 = call float @fabs(float %159)
>  %179 = call float @fabs(float %165)
>  %180 = call float @fabs(float %171)
>  %181 = call float @fabs(float %177)
>  %182 = fsub float -0.000000e+00, %26
>  %183 = fmul float %178, %27
>  %184 = fadd float %183, %182
>  %185 = fsub float -0.000000e+00, %26
>  %186 = fmul float %179, %27
>  %187 = fadd float %186, %185
>  %188 = fsub float -0.000000e+00, %26
>  %189 = fmul float %180, %27
>  %190 = fadd float %189, %188
>  %191 = fsub float -0.000000e+00, %26
>  %192 = fmul float %181, %27
>  %193 = fadd float %192, %191
>  %194 = fsub float -0.000000e+00, %126
>  %195 = fadd float %184, %194
>  %196 = fsub float -0.000000e+00, %126
>  %197 = fadd float %187, %196
>  %198 = fsub float -0.000000e+00, %126
>  %199 = fadd float %190, %198
>  %200 = fsub float -0.000000e+00, %126
>  %201 = fadd float %193, %200
>  %202 = call float @fabs(float %195)
>  %203 = call float @fabs(float %197)
>  %204 = call float @fabs(float %199)
>  %205 = call float @fabs(float %201)
>  %206 = fcmp olt float %202, %203
>  %207 = sext i1 %206 to i32
>  %208 = bitcast i32 %207 to float
>  %209 = bitcast float %208 to i32
>  %210 = icmp ne i32 %209, 0
>  %. = select i1 %210, float %147, float %149
>  %.213 = select i1 %210, float %184, float %187
>  %.214 = select i1 %210, float -1.000000e+00, float 1.000000e+00
>  %211 = fcmp olt float %204, %205
>  %212 = sext i1 %211 to i32
>  %213 = bitcast i32 %212 to float
>  %214 = bitcast float %213 to i32
>  %215 = icmp ne i32 %214, 0
>  %temp21.0 = select i1 %215, float %152, float %153
>  %temp22.0 = select i1 %215, float %190, float %193
>  %temp23.0 = select i1 %215, float -1.000000e+00, float 1.000000e+00
>  %216 = fmul float %., 2.000000e+00
>  %217 = fadd float %216, -1.000000e+00
>  %218 = fmul float %148, -2.000000e+00
>  %219 = fadd float %218, 1.000000e+00
>  %220 = fadd float %217, %29
>  %221 = fadd float %219, %31
>  %222 = fsub float -0.000000e+00, %.213
>  %223 = fmul float %222, %220
>  %224 = fsub float -0.000000e+00, %.213
>  %225 = fmul float %224, %221
>  %226 = fdiv float 1.000000e+00, %28
>  %227 = fdiv float 1.000000e+00, %30
>  %228 = fmul float %223, %226
>  %229 = fmul float %225, %227
>  %230 = fmul float %151, 2.000000e+00
>  %231 = fadd float %230, -1.000000e+00
>  %232 = fmul float %temp21.0, -2.000000e+00
>  %233 = fadd float %232, 1.000000e+00
>  %234 = fadd float %231, %29
>  %235 = fadd float %233, %31
>  %236 = fsub float -0.000000e+00, %temp22.0
>  %237 = fmul float %236, %234
>  %238 = fsub float -0.000000e+00, %temp22.0
>  %239 = fmul float %238, %235
>  %240 = fdiv float 1.000000e+00, %28
>  %241 = fdiv float 1.000000e+00, %30
>  %242 = fmul float %237, %240
>  %243 = fmul float %239, %241
>  %244 = fsub float -0.000000e+00, %144
>  %245 = fadd float %228, %244
>  %246 = fsub float -0.000000e+00, %145
>  %247 = fadd float %229, %246
>  %248 = fsub float -0.000000e+00, %126
>  %249 = fadd float %.213, %248
>  %250 = fmul float %245, %.214
>  %251 = fmul float %247, %.214
>  %252 = fmul float %249, %.214
>  %253 = fsub float -0.000000e+00, %144
>  %254 = fadd float %242, %253
>  %255 = fsub float -0.000000e+00, %145
>  %256 = fadd float %243, %255
>  %257 = fsub float -0.000000e+00, %126
>  %258 = fadd float %temp22.0, %257
>  %259 = fmul float %254, %temp23.0
>  %260 = fmul float %256, %temp23.0
>  %261 = fmul float %258, %temp23.0
>  %262 = fmul float %261, %251
>  %263 = fmul float %259, %252
>  %264 = fmul float %260, %250
>  %265 = fsub float -0.000000e+00, %262
>  %266 = fmul float %260, %252
>  %267 = fadd float %266, %265
>  %268 = fsub float -0.000000e+00, %263
>  %269 = fmul float %261, %250
>  %270 = fadd float %269, %268
>  %271 = fsub float -0.000000e+00, %264
>  %272 = fmul float %259, %251
>  %273 = fadd float %272, %271
>  %274 = fmul float %267, %267
>  %275 = fmul float %270, %270
>  %276 = fadd float %275, %274
>  %277 = fmul float %273, %273
>  %278 = fadd float %276, %277
>  %279 = call float @llvm.AMDGPU.rsq(float %278)
>  %280 = fmul float %267, %279
>  %281 = fmul float %270, %279
>  %282 = fmul float %273, %279
>  %283 = fmul float %280, %126
>  %284 = fmul float %281, %126
>  %285 = fmul float %282, %126
>  %286 = fmul float %283, %24
>  %287 = fmul float %284, %24
>  %288 = fmul float %285, %24
>  %289 = fsub float -0.000000e+00, %286
>  %290 = fadd float %144, %289
>  %291 = fsub float -0.000000e+00, %287
>  %292 = fadd float %145, %291
>  %293 = fsub float -0.000000e+00, %288
>  %294 = fadd float %126, %293
>  %295 = fmul float %32, 2.500000e-01
>  %296 = fmul float %33, 2.500000e-01
>  %297 = fmul float %115, %295
>  %298 = fmul float %116, %296
>  %299 = bitcast float %297 to i32
>  %300 = bitcast float %298 to i32
>  %301 = insertelement <2 x i32> undef, i32 %299, i32 0
>  %302 = insertelement <2 x i32> %301, i32 %300, i32 1
>  %303 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %302, <32 x i8> %98, <16 x i8> %100, i32 2)
>  %304 = extractelement <4 x float> %303, i32 0
>  %305 = extractelement <4 x float> %303, i32 1
>  %306 = extractelement <4 x float> %303, i32 2
>  %307 = fmul float %304, 2.000000e+00
>  %308 = fadd float %307, -1.000000e+00
>  %309 = fmul float %305, 2.000000e+00
>  %310 = fadd float %309, -1.000000e+00
>  %311 = fmul float %306, 2.000000e+00
>  %312 = fadd float %311, -1.000000e+00
>  %313 = fmul float %308, %25
>  %314 = fmul float %310, %25
>  %315 = fmul float %312, %25
>  %316 = fsub float -0.000000e+00, %126
>  %317 = fsub float -0.000000e+00, %38
>  %318 = fadd float %316, %317
>  %319 = fmul float %318, %41
>  %320 = call float @llvm.AMDIL.clamp.(float %319, float 0.000000e+00, float 1.000000e+00)
>  %321 = fmul float %40, %320
>  %322 = fadd float %321, 1.000000e+00
>  %323 = fsub float -0.000000e+00, %126
>  %324 = fmul float %323, %39
>  %325 = call float @llvm.AMDIL.clamp.(float %324, float 0.000000e+00, float 1.000000e+00)
>  %326 = fmul float %322, %325
>  %327 = fcmp olt float %122, 0.000000e+00
>  %328 = sext i1 %327 to i32
>  %329 = bitcast i32 %328 to float
>  %330 = bitcast float %329 to i32
>  %331 = icmp ne i32 %330, 0
>  %.215 = select i1 %331, float %42, float %326
>  %332 = fmul float %.215, %44
>  %333 = fmul float %23, %332
>  %334 = fcmp oge float %122, 0.000000e+00
>  %335 = sext i1 %334 to i32
>  %336 = bitcast i32 %335 to float
>  %337 = bitcast float %336 to i32
>  %338 = and i32 %337, 1065353216
>  %339 = bitcast i32 %338 to float
>  %340 = fmul float %333, 0.000000e+00
>  %341 = fmul float %333, 1.000000e+00
>  %342 = fmul float %333, 2.000000e+00
>  %343 = fmul float %333, 3.000000e+00
>  %344 = fsub float -0.000000e+00, %340
>  %345 = fmul float %22, %332
>  %346 = fadd float %345, %344
>  %347 = fsub float -0.000000e+00, %341
>  %348 = fmul float %22, %332
>  %349 = fadd float %348, %347
>  %350 = fsub float -0.000000e+00, %342
>  %351 = fmul float %22, %332
>  %352 = fadd float %351, %350
>  %353 = fsub float -0.000000e+00, %343
>  %354 = fmul float %22, %332
>  %355 = fadd float %354, %353
>  %356 = fmul float %313, %45
>  %357 = fmul float %314, %46
>  %358 = fadd float %357, %356
>  %359 = fmul float %315, %47
>  %360 = fadd float %358, %359
>  %361 = fmul float %360, %313
>  %362 = fmul float %360, %314
>  %363 = fmul float %360, %315
>  %364 = fmul float 2.000000e+00, %361
>  %365 = fmul float 2.000000e+00, %362
>  %366 = fmul float 2.000000e+00, %363
>  %367 = fsub float -0.000000e+00, %364
>  %368 = fadd float %45, %367
>  %369 = fsub float -0.000000e+00, %365
>  %370 = fadd float %46, %369
>  %371 = fsub float -0.000000e+00, %366
>  %372 = fadd float %47, %371
>  %373 = fmul float %368, %346
>  %374 = fmul float %370, %346
>  %375 = fmul float %372, %346
>  %376 = fmul float %313, %48
>  %377 = fmul float %314, %49
>  %378 = fadd float %377, %376
>  %379 = fmul float %315, %50
>  %380 = fadd float %378, %379
>  %381 = fmul float %380, %313
>  %382 = fmul float %380, %314
>  %383 = fmul float %380, %315
>  %384 = fmul float 2.000000e+00, %381
>  %385 = fmul float 2.000000e+00, %382
>  %386 = fmul float 2.000000e+00, %383
>  %387 = fsub float -0.000000e+00, %384
>  %388 = fadd float %48, %387
>  %389 = fsub float -0.000000e+00, %385
>  %390 = fadd float %49, %389
>  %391 = fsub float -0.000000e+00, %386
>  %392 = fadd float %50, %391
>  %393 = fmul float %388, %349
>  %394 = fmul float %390, %349
>  %395 = fmul float %392, %349
>  %396 = fmul float %313, %51
>  %397 = fmul float %314, %52
>  %398 = fadd float %397, %396
>  %399 = fmul float %315, %53
>  %400 = fadd float %398, %399
>  %401 = fmul float %400, %313
>  %402 = fmul float %400, %314
>  %403 = fmul float %400, %315
>  %404 = fmul float 2.000000e+00, %401
>  %405 = fmul float 2.000000e+00, %402
>  %406 = fmul float 2.000000e+00, %403
>  %407 = fsub float -0.000000e+00, %404
>  %408 = fadd float %51, %407
>  %409 = fsub float -0.000000e+00, %405
>  %410 = fadd float %52, %409
>  %411 = fsub float -0.000000e+00, %406
>  %412 = fadd float %53, %411
>  %413 = fmul float %408, %352
>  %414 = fmul float %410, %352
>  %415 = fmul float %412, %352
>  %416 = fmul float %313, %54
>  %417 = fmul float %314, %55
>  %418 = fadd float %417, %416
>  %419 = fmul float %315, %56
>  %420 = fadd float %418, %419
>  %421 = fmul float %420, %313
>  %422 = fmul float %420, %314
>  %423 = fmul float %420, %315
>  %424 = fmul float 2.000000e+00, %421
>  %425 = fmul float 2.000000e+00, %422
>  %426 = fmul float 2.000000e+00, %423
>  %427 = fsub float -0.000000e+00, %424
>  %428 = fadd float %54, %427
>  %429 = fsub float -0.000000e+00, %425
>  %430 = fadd float %55, %429
>  %431 = fsub float -0.000000e+00, %426
>  %432 = fadd float %56, %431
>  %433 = fmul float %428, %355
>  %434 = fmul float %430, %355
>  %435 = fmul float %432, %355
>  %436 = fmul float %373, %280
>  %437 = fmul float %374, %281
>  %438 = fadd float %437, %436
>  %439 = fmul float %375, %282
>  %440 = fadd float %438, %439
>  %441 = fmul float %393, %280
>  %442 = fmul float %394, %281
>  %443 = fadd float %442, %441
>  %444 = fmul float %395, %282
>  %445 = fadd float %443, %444
>  %446 = fmul float %413, %280
>  %447 = fmul float %414, %281
>  %448 = fadd float %447, %446
>  %449 = fmul float %415, %282
>  %450 = fadd float %448, %449
>  %451 = fmul float %433, %280
>  %452 = fmul float %434, %281
>  %453 = fadd float %452, %451
>  %454 = fmul float %435, %282
>  %455 = fadd float %453, %454
>  %456 = fcmp oge float %440, 0.000000e+00
>  %457 = sext i1 %456 to i32
>  %458 = bitcast i32 %457 to float
>  %459 = bitcast float %458 to i32
>  %460 = icmp ne i32 %459, 0
>  %temp48.0 = select i1 %460, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %461 = bitcast float %temp48.0 to i32
>  %462 = sitofp i32 %461 to float
>  %463 = fmul float %373, %462
>  %464 = fmul float %374, %462
>  %465 = fmul float %375, %462
>  %466 = fcmp oge float %445, 0.000000e+00
>  %467 = sext i1 %466 to i32
>  %468 = bitcast i32 %467 to float
>  %469 = bitcast float %468 to i32
>  %470 = icmp ne i32 %469, 0
>  %.216 = select i1 %470, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %471 = bitcast float %.216 to i32
>  %472 = sitofp i32 %471 to float
>  %473 = fmul float %393, %472
>  %474 = fmul float %394, %472
>  %475 = fmul float %395, %472
>  %476 = fcmp oge float %450, 0.000000e+00
>  %477 = sext i1 %476 to i32
>  %478 = bitcast i32 %477 to float
>  %479 = bitcast float %478 to i32
>  %480 = icmp ne i32 %479, 0
>  %temp48.2 = select i1 %480, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %481 = bitcast float %temp48.2 to i32
>  %482 = sitofp i32 %481 to float
>  %483 = fmul float %413, %482
>  %484 = fmul float %414, %482
>  %485 = fmul float %415, %482
>  %486 = fcmp oge float %455, 0.000000e+00
>  %487 = sext i1 %486 to i32
>  %488 = bitcast i32 %487 to float
>  %489 = bitcast float %488 to i32
>  %490 = icmp ne i32 %489, 0
>  %.217 = select i1 %490, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %491 = bitcast float %.217 to i32
>  %492 = sitofp i32 %491 to float
>  %493 = fmul float %433, %492
>  %494 = fmul float %434, %492
>  %495 = fmul float %435, %492
>  %496 = fadd float %290, %463
>  %497 = fadd float %292, %464
>  %498 = fadd float %290, %473
>  %499 = fadd float %292, %474
>  %500 = fadd float %290, %483
>  %501 = fadd float %292, %484
>  %502 = fadd float %290, %493
>  %503 = fadd float %292, %494
>  %504 = fadd float %294, %465
>  %505 = fadd float %294, %475
>  %506 = fadd float %294, %485
>  %507 = fadd float %294, %495
>  %508 = fsub float -0.000000e+00, %504
>  %509 = fdiv float 1.000000e+00, %508
>  %510 = fsub float -0.000000e+00, %505
>  %511 = fdiv float 1.000000e+00, %510
>  %512 = fmul float %496, %509
>  %513 = fmul float %497, %509
>  %514 = fmul float %498, %511
>  %515 = fmul float %499, %511
>  %516 = fsub float -0.000000e+00, %29
>  %517 = fmul float %512, %28
>  %518 = fadd float %517, %516
>  %519 = fsub float -0.000000e+00, %31
>  %520 = fmul float %513, %30
>  %521 = fadd float %520, %519
>  %522 = fsub float -0.000000e+00, %29
>  %523 = fmul float %514, %28
>  %524 = fadd float %523, %522
>  %525 = fsub float -0.000000e+00, %31
>  %526 = fmul float %515, %30
>  %527 = fadd float %526, %525
>  %528 = fsub float -0.000000e+00, %506
>  %529 = fdiv float 1.000000e+00, %528
>  %530 = fsub float -0.000000e+00, %507
>  %531 = fdiv float 1.000000e+00, %530
>  %532 = fmul float %500, %529
>  %533 = fmul float %501, %529
>  %534 = fmul float %502, %531
>  %535 = fmul float %503, %531
>  %536 = fsub float -0.000000e+00, %29
>  %537 = fmul float %532, %28
>  %538 = fadd float %537, %536
>  %539 = fsub float -0.000000e+00, %31
>  %540 = fmul float %533, %30
>  %541 = fadd float %540, %539
>  %542 = fsub float -0.000000e+00, %29
>  %543 = fmul float %534, %28
>  %544 = fadd float %543, %542
>  %545 = fsub float -0.000000e+00, %31
>  %546 = fmul float %535, %30
>  %547 = fadd float %546, %545
>  %548 = fmul float %518, 5.000000e-01
>  %549 = fadd float %548, 5.000000e-01
>  %550 = fmul float %521, -5.000000e-01
>  %551 = fadd float %550, 5.000000e-01
>  %552 = fmul float %524, 5.000000e-01
>  %553 = fadd float %552, 5.000000e-01
>  %554 = fmul float %527, -5.000000e-01
>  %555 = fadd float %554, 5.000000e-01
>  %556 = fmul float %538, 5.000000e-01
>  %557 = fadd float %556, 5.000000e-01
>  %558 = fmul float %541, -5.000000e-01
>  %559 = fadd float %558, 5.000000e-01
>  %560 = fmul float %544, 5.000000e-01
>  %561 = fadd float %560, 5.000000e-01
>  %562 = fmul float %547, -5.000000e-01
>  %563 = fadd float %562, 5.000000e-01
>  %564 = call float @llvm.AMDIL.clamp.(float %549, float 0.000000e+00, float 1.000000e+00)
>  %565 = call float @llvm.AMDIL.clamp.(float %551, float 0.000000e+00, float 1.000000e+00)
>  %566 = call float @llvm.AMDIL.clamp.(float %553, float 0.000000e+00, float 1.000000e+00)
>  %567 = call float @llvm.AMDIL.clamp.(float %555, float 0.000000e+00, float 1.000000e+00)
>  %568 = call float @llvm.AMDIL.clamp.(float %557, float 0.000000e+00, float 1.000000e+00)
>  %569 = call float @llvm.AMDIL.clamp.(float %559, float 0.000000e+00, float 1.000000e+00)
>  %570 = call float @llvm.AMDIL.clamp.(float %561, float 0.000000e+00, float 1.000000e+00)
>  %571 = call float @llvm.AMDIL.clamp.(float %563, float 0.000000e+00, float 1.000000e+00)
>  %572 = bitcast float %564 to i32
>  %573 = bitcast float %565 to i32
>  %574 = insertelement <2 x i32> undef, i32 %572, i32 0
>  %575 = insertelement <2 x i32> %574, i32 %573, i32 1
>  %576 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %575, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %577 = extractelement <4 x float> %576, i32 0
>  %578 = bitcast float %566 to i32
>  %579 = bitcast float %567 to i32
>  %580 = insertelement <2 x i32> undef, i32 %578, i32 0
>  %581 = insertelement <2 x i32> %580, i32 %579, i32 1
>  %582 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %581, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %583 = extractelement <4 x float> %582, i32 0
>  %584 = bitcast float %568 to i32
>  %585 = bitcast float %569 to i32
>  %586 = insertelement <2 x i32> undef, i32 %584, i32 0
>  %587 = insertelement <2 x i32> %586, i32 %585, i32 1
>  %588 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %587, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %589 = extractelement <4 x float> %588, i32 0
>  %590 = bitcast float %570 to i32
>  %591 = bitcast float %571 to i32
>  %592 = insertelement <2 x i32> undef, i32 %590, i32 0
>  %593 = insertelement <2 x i32> %592, i32 %591, i32 1
>  %594 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %593, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %595 = extractelement <4 x float> %594, i32 0
>  %596 = call float @fabs(float %577)
>  %597 = call float @fabs(float %583)
>  %598 = call float @fabs(float %589)
>  %599 = call float @fabs(float %595)
>  %600 = fsub float -0.000000e+00, %26
>  %601 = fmul float %596, %27
>  %602 = fadd float %601, %600
>  %603 = fsub float -0.000000e+00, %26
>  %604 = fmul float %597, %27
>  %605 = fadd float %604, %603
>  %606 = fsub float -0.000000e+00, %26
>  %607 = fmul float %598, %27
>  %608 = fadd float %607, %606
>  %609 = fsub float -0.000000e+00, %26
>  %610 = fmul float %599, %27
>  %611 = fadd float %610, %609
>  %612 = fsub float -0.000000e+00, %504
>  %613 = fadd float %602, %612
>  %614 = fsub float -0.000000e+00, %505
>  %615 = fadd float %605, %614
>  %616 = fsub float -0.000000e+00, %506
>  %617 = fadd float %608, %616
>  %618 = fsub float -0.000000e+00, %507
>  %619 = fadd float %611, %618
>  %620 = fmul float %346, 2.000000e+00
>  %621 = fmul float %349, 2.000000e+00
>  %622 = fmul float %352, 2.000000e+00
>  %623 = fmul float %355, 2.000000e+00
>  %624 = fcmp oge float %613, %620
>  %625 = sext i1 %624 to i32
>  %626 = bitcast i32 %625 to float
>  %627 = bitcast float %626 to i32
>  %628 = and i32 %627, 1065353216
>  %629 = bitcast i32 %628 to float
>  %630 = fcmp oge float %615, %621
>  %631 = sext i1 %630 to i32
>  %632 = bitcast i32 %631 to float
>  %633 = bitcast float %632 to i32
>  %634 = and i32 %633, 1065353216
>  %635 = bitcast i32 %634 to float
>  %636 = fcmp oge float %617, %622
>  %637 = sext i1 %636 to i32
>  %638 = bitcast i32 %637 to float
>  %639 = bitcast float %638 to i32
>  %640 = and i32 %639, 1065353216
>  %641 = bitcast i32 %640 to float
>  %642 = fcmp oge float %619, %623
>  %643 = sext i1 %642 to i32
>  %644 = bitcast i32 %643 to float
>  %645 = bitcast float %644 to i32
>  %646 = and i32 %645, 1065353216
>  %647 = bitcast i32 %646 to float
>  %648 = fcmp oeq float %602, 0.000000e+00
>  %649 = sext i1 %648 to i32
>  %650 = bitcast i32 %649 to float
>  %651 = bitcast float %650 to i32
>  %652 = icmp ne i32 %651, 0
>  %temp92.0 = select i1 %652, float 0x36A0000000000000, float 0.000000e+00
>  %653 = fcmp oeq float %605, 0.000000e+00
>  %654 = sext i1 %653 to i32
>  %655 = bitcast i32 %654 to float
>  %656 = bitcast float %655 to i32
>  %657 = icmp ne i32 %656, 0
>  %.218 = select i1 %657, float 0x36A0000000000000, float 0.000000e+00
>  %658 = fcmp oeq float %608, 0.000000e+00
>  %659 = sext i1 %658 to i32
>  %660 = bitcast i32 %659 to float
>  %661 = bitcast float %660 to i32
>  %662 = icmp ne i32 %661, 0
>  %temp104.0 = select i1 %662, float 0x36A0000000000000, float 0.000000e+00
>  %663 = fcmp oeq float %611, 0.000000e+00
>  %664 = sext i1 %663 to i32
>  %665 = bitcast i32 %664 to float
>  %666 = bitcast float %665 to i32
>  %667 = icmp ne i32 %666, 0
>  %.219 = select i1 %667, float 0x36A0000000000000, float 0.000000e+00
>  %668 = bitcast float %temp92.0 to i32
>  %669 = sitofp i32 %668 to float
>  %670 = bitcast float %.218 to i32
>  %671 = sitofp i32 %670 to float
>  %672 = bitcast float %temp104.0 to i32
>  %673 = sitofp i32 %672 to float
>  %674 = bitcast float %.219 to i32
>  %675 = sitofp i32 %674 to float
>  %676 = fcmp oge float 0.000000e+00, %577
>  %677 = sext i1 %676 to i32
>  %678 = bitcast i32 %677 to float
>  %679 = bitcast float %678 to i32
>  %680 = and i32 %679, 1065353216
>  %681 = bitcast i32 %680 to float
>  %682 = fcmp oge float 0.000000e+00, %583
>  %683 = sext i1 %682 to i32
>  %684 = bitcast i32 %683 to float
>  %685 = bitcast float %684 to i32
>  %686 = and i32 %685, 1065353216
>  %687 = bitcast i32 %686 to float
>  %688 = fcmp oge float 0.000000e+00, %589
>  %689 = sext i1 %688 to i32
>  %690 = bitcast i32 %689 to float
>  %691 = bitcast float %690 to i32
>  %692 = and i32 %691, 1065353216
>  %693 = bitcast i32 %692 to float
>  %694 = fcmp oge float 0.000000e+00, %595
>  %695 = sext i1 %694 to i32
>  %696 = bitcast i32 %695 to float
>  %697 = bitcast float %696 to i32
>  %698 = and i32 %697, 1065353216
>  %699 = bitcast i32 %698 to float
>  %700 = fadd float %629, %669
>  %701 = fadd float %635, %671
>  %702 = fadd float %641, %673
>  %703 = fadd float %647, %675
>  %704 = fmul float %681, %339
>  %705 = fadd float %704, %700
>  %706 = fmul float %687, %339
>  %707 = fadd float %706, %701
>  %708 = fmul float %693, %339
>  %709 = fadd float %708, %702
>  %710 = fmul float %699, %339
>  %711 = fadd float %710, %703
>  %712 = call float @llvm.AMDIL.clamp.(float %705, float 0.000000e+00, float 1.000000e+00)
>  %713 = call float @llvm.AMDIL.clamp.(float %707, float 0.000000e+00, float 1.000000e+00)
>  %714 = call float @llvm.AMDIL.clamp.(float %709, float 0.000000e+00, float 1.000000e+00)
>  %715 = call float @llvm.AMDIL.clamp.(float %711, float 0.000000e+00, float 1.000000e+00)
>  %716 = fmul float %712, 1.000000e+00
>  %717 = fmul float %713, 1.000000e+00
>  %718 = fadd float %716, %717
>  %719 = fmul float %714, 1.000000e+00
>  %720 = fadd float %718, %719
>  %721 = fmul float %715, 1.000000e+00
>  %722 = fadd float %720, %721
>  %723 = fcmp oge float %613, 0.000000e+00
>  %724 = sext i1 %723 to i32
>  %725 = bitcast i32 %724 to float
>  %726 = bitcast float %725 to i32
>  %727 = and i32 %726, 1065353216
>  %728 = bitcast i32 %727 to float
>  %729 = fcmp oge float %615, 0.000000e+00
>  %730 = sext i1 %729 to i32
>  %731 = bitcast i32 %730 to float
>  %732 = bitcast float %731 to i32
>  %733 = and i32 %732, 1065353216
>  %734 = bitcast i32 %733 to float
>  %735 = fcmp oge float %617, 0.000000e+00
>  %736 = sext i1 %735 to i32
>  %737 = bitcast i32 %736 to float
>  %738 = bitcast float %737 to i32
>  %739 = and i32 %738, 1065353216
>  %740 = bitcast i32 %739 to float
>  %741 = fcmp oge float %619, 0.000000e+00
>  %742 = sext i1 %741 to i32
>  %743 = bitcast i32 %742 to float
>  %744 = bitcast float %743 to i32
>  %745 = and i32 %744, 1065353216
>  %746 = bitcast i32 %745 to float
>  %747 = fsub float -0.000000e+00, %712
>  %748 = fadd float 1.000000e+00, %747
>  %749 = fsub float -0.000000e+00, %713
>  %750 = fadd float 1.000000e+00, %749
>  %751 = fsub float -0.000000e+00, %714
>  %752 = fadd float 1.000000e+00, %751
>  %753 = fsub float -0.000000e+00, %715
>  %754 = fadd float 1.000000e+00, %753
>  %755 = fmul float %728, %748
>  %756 = fmul float %734, %750
>  %757 = fmul float %740, %752
>  %758 = fmul float %746, %754
>  %759 = fmul float %755, 1.000000e+00
>  %760 = fmul float %756, 1.000000e+00
>  %761 = fadd float %759, %760
>  %762 = fmul float %757, 1.000000e+00
>  %763 = fadd float %761, %762
>  %764 = fmul float %758, 1.000000e+00
>  %765 = fadd float %763, %764
>  %766 = fmul float %333, 4.000000e+00
>  %767 = fsub float -0.000000e+00, %766
>  %768 = fadd float %346, %767
>  %769 = fsub float -0.000000e+00, %766
>  %770 = fadd float %349, %769
>  %771 = fsub float -0.000000e+00, %766
>  %772 = fadd float %352, %771
>  %773 = fsub float -0.000000e+00, %766
>  %774 = fadd float %355, %773
>  %775 = fmul float %313, %57
>  %776 = fmul float %314, %58
>  %777 = fadd float %776, %775
>  %778 = fmul float %315, %59
>  %779 = fadd float %777, %778
>  %780 = fmul float %779, %313
>  %781 = fmul float %779, %314
>  %782 = fmul float %779, %315
>  %783 = fmul float 2.000000e+00, %780
>  %784 = fmul float 2.000000e+00, %781
>  %785 = fmul float 2.000000e+00, %782
>  %786 = fsub float -0.000000e+00, %783
>  %787 = fadd float %57, %786
>  %788 = fsub float -0.000000e+00, %784
>  %789 = fadd float %58, %788
>  %790 = fsub float -0.000000e+00, %785
>  %791 = fadd float %59, %790
>  %792 = fmul float %787, %768
>  %793 = fmul float %789, %768
>  %794 = fmul float %791, %768
>  %795 = fmul float %313, %60
>  %796 = fmul float %314, %61
>  %797 = fadd float %796, %795
>  %798 = fmul float %315, %62
>  %799 = fadd float %797, %798
>  %800 = fmul float %799, %313
>  %801 = fmul float %799, %314
>  %802 = fmul float %799, %315
>  %803 = fmul float 2.000000e+00, %800
>  %804 = fmul float 2.000000e+00, %801
>  %805 = fmul float 2.000000e+00, %802
>  %806 = fsub float -0.000000e+00, %803
>  %807 = fadd float %60, %806
>  %808 = fsub float -0.000000e+00, %804
>  %809 = fadd float %61, %808
>  %810 = fsub float -0.000000e+00, %805
>  %811 = fadd float %62, %810
>  %812 = fmul float %807, %770
>  %813 = fmul float %809, %770
>  %814 = fmul float %811, %770
>  %815 = fmul float %313, %63
>  %816 = fmul float %314, %64
>  %817 = fadd float %816, %815
>  %818 = fmul float %315, %65
>  %819 = fadd float %817, %818
>  %820 = fmul float %819, %313
>  %821 = fmul float %819, %314
>  %822 = fmul float %819, %315
>  %823 = fmul float 2.000000e+00, %820
>  %824 = fmul float 2.000000e+00, %821
>  %825 = fmul float 2.000000e+00, %822
>  %826 = fsub float -0.000000e+00, %823
>  %827 = fadd float %63, %826
>  %828 = fsub float -0.000000e+00, %824
>  %829 = fadd float %64, %828
>  %830 = fsub float -0.000000e+00, %825
>  %831 = fadd float %65, %830
>  %832 = fmul float %827, %772
>  %833 = fmul float %829, %772
>  %834 = fmul float %831, %772
>  %835 = fmul float %313, %66
>  %836 = fmul float %314, %67
>  %837 = fadd float %836, %835
>  %838 = fmul float %315, %68
>  %839 = fadd float %837, %838
>  %840 = fmul float %839, %313
>  %841 = fmul float %839, %314
>  %842 = fmul float %839, %315
>  %843 = fmul float 2.000000e+00, %840
>  %844 = fmul float 2.000000e+00, %841
>  %845 = fmul float 2.000000e+00, %842
>  %846 = fsub float -0.000000e+00, %843
>  %847 = fadd float %66, %846
>  %848 = fsub float -0.000000e+00, %844
>  %849 = fadd float %67, %848
>  %850 = fsub float -0.000000e+00, %845
>  %851 = fadd float %68, %850
>  %852 = fmul float %847, %774
>  %853 = fmul float %849, %774
>  %854 = fmul float %851, %774
>  %855 = fmul float %792, %280
>  %856 = fmul float %793, %281
>  %857 = fadd float %856, %855
>  %858 = fmul float %794, %282
>  %859 = fadd float %857, %858
>  %860 = fmul float %812, %280
>  %861 = fmul float %813, %281
>  %862 = fadd float %861, %860
>  %863 = fmul float %814, %282
>  %864 = fadd float %862, %863
>  %865 = fmul float %832, %280
>  %866 = fmul float %833, %281
>  %867 = fadd float %866, %865
>  %868 = fmul float %834, %282
>  %869 = fadd float %867, %868
>  %870 = fmul float %852, %280
>  %871 = fmul float %853, %281
>  %872 = fadd float %871, %870
>  %873 = fmul float %854, %282
>  %874 = fadd float %872, %873
>  %875 = fcmp oge float %859, 0.000000e+00
>  %876 = sext i1 %875 to i32
>  %877 = bitcast i32 %876 to float
>  %878 = bitcast float %877 to i32
>  %879 = icmp ne i32 %878, 0
>  %temp68.0 = select i1 %879, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %880 = bitcast float %temp68.0 to i32
>  %881 = sitofp i32 %880 to float
>  %882 = fmul float %792, %881
>  %883 = fmul float %793, %881
>  %884 = fmul float %794, %881
>  %885 = fcmp oge float %864, 0.000000e+00
>  %886 = sext i1 %885 to i32
>  %887 = bitcast i32 %886 to float
>  %888 = bitcast float %887 to i32
>  %889 = icmp ne i32 %888, 0
>  %.220 = select i1 %889, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %890 = bitcast float %.220 to i32
>  %891 = sitofp i32 %890 to float
>  %892 = fmul float %812, %891
>  %893 = fmul float %813, %891
>  %894 = fmul float %814, %891
>  %895 = fcmp oge float %869, 0.000000e+00
>  %896 = sext i1 %895 to i32
>  %897 = bitcast i32 %896 to float
>  %898 = bitcast float %897 to i32
>  %899 = icmp ne i32 %898, 0
>  %temp68.2 = select i1 %899, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %900 = bitcast float %temp68.2 to i32
>  %901 = sitofp i32 %900 to float
>  %902 = fmul float %832, %901
>  %903 = fmul float %833, %901
>  %904 = fmul float %834, %901
>  %905 = fcmp oge float %874, 0.000000e+00
>  %906 = sext i1 %905 to i32
>  %907 = bitcast i32 %906 to float
>  %908 = bitcast float %907 to i32
>  %909 = icmp ne i32 %908, 0
>  %.221 = select i1 %909, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %910 = bitcast float %.221 to i32
>  %911 = sitofp i32 %910 to float
>  %912 = fmul float %852, %911
>  %913 = fmul float %853, %911
>  %914 = fmul float %854, %911
>  %915 = fadd float %290, %882
>  %916 = fadd float %292, %883
>  %917 = fadd float %290, %892
>  %918 = fadd float %292, %893
>  %919 = fadd float %290, %902
>  %920 = fadd float %292, %903
>  %921 = fadd float %290, %912
>  %922 = fadd float %292, %913
>  %923 = fadd float %294, %884
>  %924 = fadd float %294, %894
>  %925 = fadd float %294, %904
>  %926 = fadd float %294, %914
>  %927 = fsub float -0.000000e+00, %923
>  %928 = fdiv float 1.000000e+00, %927
>  %929 = fsub float -0.000000e+00, %924
>  %930 = fdiv float 1.000000e+00, %929
>  %931 = fmul float %915, %928
>  %932 = fmul float %916, %928
>  %933 = fmul float %917, %930
>  %934 = fmul float %918, %930
>  %935 = fsub float -0.000000e+00, %29
>  %936 = fmul float %931, %28
>  %937 = fadd float %936, %935
>  %938 = fsub float -0.000000e+00, %31
>  %939 = fmul float %932, %30
>  %940 = fadd float %939, %938
>  %941 = fsub float -0.000000e+00, %29
>  %942 = fmul float %933, %28
>  %943 = fadd float %942, %941
>  %944 = fsub float -0.000000e+00, %31
>  %945 = fmul float %934, %30
>  %946 = fadd float %945, %944
>  %947 = fsub float -0.000000e+00, %925
>  %948 = fdiv float 1.000000e+00, %947
>  %949 = fsub float -0.000000e+00, %926
>  %950 = fdiv float 1.000000e+00, %949
>  %951 = fmul float %919, %948
>  %952 = fmul float %920, %948
>  %953 = fmul float %921, %950
>  %954 = fmul float %922, %950
>  %955 = fsub float -0.000000e+00, %29
>  %956 = fmul float %951, %28
>  %957 = fadd float %956, %955
>  %958 = fsub float -0.000000e+00, %31
>  %959 = fmul float %952, %30
>  %960 = fadd float %959, %958
>  %961 = fsub float -0.000000e+00, %29
>  %962 = fmul float %953, %28
>  %963 = fadd float %962, %961
>  %964 = fsub float -0.000000e+00, %31
>  %965 = fmul float %954, %30
>  %966 = fadd float %965, %964
>  %967 = fmul float %937, 5.000000e-01
>  %968 = fadd float %967, 5.000000e-01
>  %969 = fmul float %940, -5.000000e-01
>  %970 = fadd float %969, 5.000000e-01
>  %971 = fmul float %943, 5.000000e-01
>  %972 = fadd float %971, 5.000000e-01
>  %973 = fmul float %946, -5.000000e-01
>  %974 = fadd float %973, 5.000000e-01
>  %975 = fmul float %957, 5.000000e-01
>  %976 = fadd float %975, 5.000000e-01
>  %977 = fmul float %960, -5.000000e-01
>  %978 = fadd float %977, 5.000000e-01
>  %979 = fmul float %963, 5.000000e-01
>  %980 = fadd float %979, 5.000000e-01
>  %981 = fmul float %966, -5.000000e-01
>  %982 = fadd float %981, 5.000000e-01
>  %983 = call float @llvm.AMDIL.clamp.(float %968, float 0.000000e+00, float 1.000000e+00)
>  %984 = call float @llvm.AMDIL.clamp.(float %970, float 0.000000e+00, float 1.000000e+00)
>  %985 = call float @llvm.AMDIL.clamp.(float %972, float 0.000000e+00, float 1.000000e+00)
>  %986 = call float @llvm.AMDIL.clamp.(float %974, float 0.000000e+00, float 1.000000e+00)
>  %987 = call float @llvm.AMDIL.clamp.(float %976, float 0.000000e+00, float 1.000000e+00)
>  %988 = call float @llvm.AMDIL.clamp.(float %978, float 0.000000e+00, float 1.000000e+00)
>  %989 = call float @llvm.AMDIL.clamp.(float %980, float 0.000000e+00, float 1.000000e+00)
>  %990 = call float @llvm.AMDIL.clamp.(float %982, float 0.000000e+00, float 1.000000e+00)
>  %991 = bitcast float %983 to i32
>  %992 = bitcast float %984 to i32
>  %993 = insertelement <2 x i32> undef, i32 %991, i32 0
>  %994 = insertelement <2 x i32> %993, i32 %992, i32 1
>  %995 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %994, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %996 = extractelement <4 x float> %995, i32 0
>  %997 = bitcast float %985 to i32
>  %998 = bitcast float %986 to i32
>  %999 = insertelement <2 x i32> undef, i32 %997, i32 0
>  %1000 = insertelement <2 x i32> %999, i32 %998, i32 1
>  %1001 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1000, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1002 = extractelement <4 x float> %1001, i32 0
>  %1003 = bitcast float %987 to i32
>  %1004 = bitcast float %988 to i32
>  %1005 = insertelement <2 x i32> undef, i32 %1003, i32 0
>  %1006 = insertelement <2 x i32> %1005, i32 %1004, i32 1
>  %1007 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1006, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1008 = extractelement <4 x float> %1007, i32 0
>  %1009 = bitcast float %989 to i32
>  %1010 = bitcast float %990 to i32
>  %1011 = insertelement <2 x i32> undef, i32 %1009, i32 0
>  %1012 = insertelement <2 x i32> %1011, i32 %1010, i32 1
>  %1013 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1012, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1014 = extractelement <4 x float> %1013, i32 0
>  %1015 = call float @fabs(float %996)
>  %1016 = call float @fabs(float %1002)
>  %1017 = call float @fabs(float %1008)
>  %1018 = call float @fabs(float %1014)
>  %1019 = fsub float -0.000000e+00, %26
>  %1020 = fmul float %1015, %27
>  %1021 = fadd float %1020, %1019
>  %1022 = fsub float -0.000000e+00, %26
>  %1023 = fmul float %1016, %27
>  %1024 = fadd float %1023, %1022
>  %1025 = fsub float -0.000000e+00, %26
>  %1026 = fmul float %1017, %27
>  %1027 = fadd float %1026, %1025
>  %1028 = fsub float -0.000000e+00, %26
>  %1029 = fmul float %1018, %27
>  %1030 = fadd float %1029, %1028
>  %1031 = fsub float -0.000000e+00, %923
>  %1032 = fadd float %1021, %1031
>  %1033 = fsub float -0.000000e+00, %924
>  %1034 = fadd float %1024, %1033
>  %1035 = fsub float -0.000000e+00, %925
>  %1036 = fadd float %1027, %1035
>  %1037 = fsub float -0.000000e+00, %926
>  %1038 = fadd float %1030, %1037
>  %1039 = fmul float %768, 2.000000e+00
>  %1040 = fmul float %770, 2.000000e+00
>  %1041 = fmul float %772, 2.000000e+00
>  %1042 = fmul float %774, 2.000000e+00
>  %1043 = fcmp oge float %1032, %1039
>  %1044 = sext i1 %1043 to i32
>  %1045 = bitcast i32 %1044 to float
>  %1046 = bitcast float %1045 to i32
>  %1047 = and i32 %1046, 1065353216
>  %1048 = bitcast i32 %1047 to float
>  %1049 = fcmp oge float %1034, %1040
>  %1050 = sext i1 %1049 to i32
>  %1051 = bitcast i32 %1050 to float
>  %1052 = bitcast float %1051 to i32
>  %1053 = and i32 %1052, 1065353216
>  %1054 = bitcast i32 %1053 to float
>  %1055 = fcmp oge float %1036, %1041
>  %1056 = sext i1 %1055 to i32
>  %1057 = bitcast i32 %1056 to float
>  %1058 = bitcast float %1057 to i32
>  %1059 = and i32 %1058, 1065353216
>  %1060 = bitcast i32 %1059 to float
>  %1061 = fcmp oge float %1038, %1042
>  %1062 = sext i1 %1061 to i32
>  %1063 = bitcast i32 %1062 to float
>  %1064 = bitcast float %1063 to i32
>  %1065 = and i32 %1064, 1065353216
>  %1066 = bitcast i32 %1065 to float
>  %1067 = fcmp oeq float %1021, 0.000000e+00
>  %1068 = sext i1 %1067 to i32
>  %1069 = bitcast i32 %1068 to float
>  %1070 = bitcast float %1069 to i32
>  %1071 = icmp ne i32 %1070, 0
>  %temp92.1 = select i1 %1071, float 0x36A0000000000000, float 0.000000e+00
>  %1072 = fcmp oeq float %1024, 0.000000e+00
>  %1073 = sext i1 %1072 to i32
>  %1074 = bitcast i32 %1073 to float
>  %1075 = bitcast float %1074 to i32
>  %1076 = icmp ne i32 %1075, 0
>  %.222 = select i1 %1076, float 0x36A0000000000000, float 0.000000e+00
>  %1077 = fcmp oeq float %1027, 0.000000e+00
>  %1078 = sext i1 %1077 to i32
>  %1079 = bitcast i32 %1078 to float
>  %1080 = bitcast float %1079 to i32
>  %1081 = icmp ne i32 %1080, 0
>  %temp104.1 = select i1 %1081, float 0x36A0000000000000, float 0.000000e+00
>  %1082 = fcmp oeq float %1030, 0.000000e+00
>  %1083 = sext i1 %1082 to i32
>  %1084 = bitcast i32 %1083 to float
>  %1085 = bitcast float %1084 to i32
>  %1086 = icmp ne i32 %1085, 0
>  %.223 = select i1 %1086, float 0x36A0000000000000, float 0.000000e+00
>  %1087 = bitcast float %temp92.1 to i32
>  %1088 = sitofp i32 %1087 to float
>  %1089 = bitcast float %.222 to i32
>  %1090 = sitofp i32 %1089 to float
>  %1091 = bitcast float %temp104.1 to i32
>  %1092 = sitofp i32 %1091 to float
>  %1093 = bitcast float %.223 to i32
>  %1094 = sitofp i32 %1093 to float
>  %1095 = fcmp oge float 0.000000e+00, %996
>  %1096 = sext i1 %1095 to i32
>  %1097 = bitcast i32 %1096 to float
>  %1098 = bitcast float %1097 to i32
>  %1099 = and i32 %1098, 1065353216
>  %1100 = bitcast i32 %1099 to float
>  %1101 = fcmp oge float 0.000000e+00, %1002
>  %1102 = sext i1 %1101 to i32
>  %1103 = bitcast i32 %1102 to float
>  %1104 = bitcast float %1103 to i32
>  %1105 = and i32 %1104, 1065353216
>  %1106 = bitcast i32 %1105 to float
>  %1107 = fcmp oge float 0.000000e+00, %1008
>  %1108 = sext i1 %1107 to i32
>  %1109 = bitcast i32 %1108 to float
>  %1110 = bitcast float %1109 to i32
>  %1111 = and i32 %1110, 1065353216
>  %1112 = bitcast i32 %1111 to float
>  %1113 = fcmp oge float 0.000000e+00, %1014
>  %1114 = sext i1 %1113 to i32
>  %1115 = bitcast i32 %1114 to float
>  %1116 = bitcast float %1115 to i32
>  %1117 = and i32 %1116, 1065353216
>  %1118 = bitcast i32 %1117 to float
>  %1119 = fadd float %1048, %1088
>  %1120 = fadd float %1054, %1090
>  %1121 = fadd float %1060, %1092
>  %1122 = fadd float %1066, %1094
>  %1123 = fmul float %1100, %339
>  %1124 = fadd float %1123, %1119
>  %1125 = fmul float %1106, %339
>  %1126 = fadd float %1125, %1120
>  %1127 = fmul float %1112, %339
>  %1128 = fadd float %1127, %1121
>  %1129 = fmul float %1118, %339
>  %1130 = fadd float %1129, %1122
>  %1131 = call float @llvm.AMDIL.clamp.(float %1124, float 0.000000e+00, float 1.000000e+00)
>  %1132 = call float @llvm.AMDIL.clamp.(float %1126, float 0.000000e+00, float 1.000000e+00)
>  %1133 = call float @llvm.AMDIL.clamp.(float %1128, float 0.000000e+00, float 1.000000e+00)
>  %1134 = call float @llvm.AMDIL.clamp.(float %1130, float 0.000000e+00, float 1.000000e+00)
>  %1135 = fmul float %1131, 1.000000e+00
>  %1136 = fmul float %1132, 1.000000e+00
>  %1137 = fadd float %1135, %1136
>  %1138 = fmul float %1133, 1.000000e+00
>  %1139 = fadd float %1137, %1138
>  %1140 = fmul float %1134, 1.000000e+00
>  %1141 = fadd float %1139, %1140
>  %1142 = fadd float %722, %1141
>  %1143 = fcmp oge float %1032, 0.000000e+00
>  %1144 = sext i1 %1143 to i32
>  %1145 = bitcast i32 %1144 to float
>  %1146 = bitcast float %1145 to i32
>  %1147 = and i32 %1146, 1065353216
>  %1148 = bitcast i32 %1147 to float
>  %1149 = fcmp oge float %1034, 0.000000e+00
>  %1150 = sext i1 %1149 to i32
>  %1151 = bitcast i32 %1150 to float
>  %1152 = bitcast float %1151 to i32
>  %1153 = and i32 %1152, 1065353216
>  %1154 = bitcast i32 %1153 to float
>  %1155 = fcmp oge float %1036, 0.000000e+00
>  %1156 = sext i1 %1155 to i32
>  %1157 = bitcast i32 %1156 to float
>  %1158 = bitcast float %1157 to i32
>  %1159 = and i32 %1158, 1065353216
>  %1160 = bitcast i32 %1159 to float
>  %1161 = fcmp oge float %1038, 0.000000e+00
>  %1162 = sext i1 %1161 to i32
>  %1163 = bitcast i32 %1162 to float
>  %1164 = bitcast float %1163 to i32
>  %1165 = and i32 %1164, 1065353216
>  %1166 = bitcast i32 %1165 to float
>  %1167 = fsub float -0.000000e+00, %1131
>  %1168 = fadd float 1.000000e+00, %1167
>  %1169 = fsub float -0.000000e+00, %1132
>  %1170 = fadd float 1.000000e+00, %1169
>  %1171 = fsub float -0.000000e+00, %1133
>  %1172 = fadd float 1.000000e+00, %1171
>  %1173 = fsub float -0.000000e+00, %1134
>  %1174 = fadd float 1.000000e+00, %1173
>  %1175 = fmul float %1148, %1168
>  %1176 = fmul float %1154, %1170
>  %1177 = fmul float %1160, %1172
>  %1178 = fmul float %1166, %1174
>  %1179 = fmul float %1175, 1.000000e+00
>  %1180 = fmul float %1176, 1.000000e+00
>  %1181 = fadd float %1179, %1180
>  %1182 = fmul float %1177, 1.000000e+00
>  %1183 = fadd float %1181, %1182
>  %1184 = fmul float %1178, 1.000000e+00
>  %1185 = fadd float %1183, %1184
>  %1186 = fadd float %765, %1185
>  %1187 = fmul float %333, 4.000000e+00
>  %1188 = fsub float -0.000000e+00, %1187
>  %1189 = fadd float %768, %1188
>  %1190 = fsub float -0.000000e+00, %1187
>  %1191 = fadd float %770, %1190
>  %1192 = fsub float -0.000000e+00, %1187
>  %1193 = fadd float %772, %1192
>  %1194 = fsub float -0.000000e+00, %1187
>  %1195 = fadd float %774, %1194
>  %1196 = fmul float %313, %69
>  %1197 = fmul float %314, %70
>  %1198 = fadd float %1197, %1196
>  %1199 = fmul float %315, %71
>  %1200 = fadd float %1198, %1199
>  %1201 = fmul float %1200, %313
>  %1202 = fmul float %1200, %314
>  %1203 = fmul float %1200, %315
>  %1204 = fmul float 2.000000e+00, %1201
>  %1205 = fmul float 2.000000e+00, %1202
>  %1206 = fmul float 2.000000e+00, %1203
>  %1207 = fsub float -0.000000e+00, %1204
>  %1208 = fadd float %69, %1207
>  %1209 = fsub float -0.000000e+00, %1205
>  %1210 = fadd float %70, %1209
>  %1211 = fsub float -0.000000e+00, %1206
>  %1212 = fadd float %71, %1211
>  %1213 = fmul float %1208, %1189
>  %1214 = fmul float %1210, %1189
>  %1215 = fmul float %1212, %1189
>  %1216 = fmul float %313, %72
>  %1217 = fmul float %314, %73
>  %1218 = fadd float %1217, %1216
>  %1219 = fmul float %315, %74
>  %1220 = fadd float %1218, %1219
>  %1221 = fmul float %1220, %313
>  %1222 = fmul float %1220, %314
>  %1223 = fmul float %1220, %315
>  %1224 = fmul float 2.000000e+00, %1221
>  %1225 = fmul float 2.000000e+00, %1222
>  %1226 = fmul float 2.000000e+00, %1223
>  %1227 = fsub float -0.000000e+00, %1224
>  %1228 = fadd float %72, %1227
>  %1229 = fsub float -0.000000e+00, %1225
>  %1230 = fadd float %73, %1229
>  %1231 = fsub float -0.000000e+00, %1226
>  %1232 = fadd float %74, %1231
>  %1233 = fmul float %1228, %1191
>  %1234 = fmul float %1230, %1191
>  %1235 = fmul float %1232, %1191
>  %1236 = fmul float %313, %75
>  %1237 = fmul float %314, %76
>  %1238 = fadd float %1237, %1236
>  %1239 = fmul float %315, %77
>  %1240 = fadd float %1238, %1239
>  %1241 = fmul float %1240, %313
>  %1242 = fmul float %1240, %314
>  %1243 = fmul float %1240, %315
>  %1244 = fmul float 2.000000e+00, %1241
>  %1245 = fmul float 2.000000e+00, %1242
>  %1246 = fmul float 2.000000e+00, %1243
>  %1247 = fsub float -0.000000e+00, %1244
>  %1248 = fadd float %75, %1247
>  %1249 = fsub float -0.000000e+00, %1245
>  %1250 = fadd float %76, %1249
>  %1251 = fsub float -0.000000e+00, %1246
>  %1252 = fadd float %77, %1251
>  %1253 = fmul float %1248, %1193
>  %1254 = fmul float %1250, %1193
>  %1255 = fmul float %1252, %1193
>  %1256 = fmul float %313, %78
>  %1257 = fmul float %314, %79
>  %1258 = fadd float %1257, %1256
>  %1259 = fmul float %315, %80
>  %1260 = fadd float %1258, %1259
>  %1261 = fmul float %1260, %313
>  %1262 = fmul float %1260, %314
>  %1263 = fmul float %1260, %315
>  %1264 = fmul float 2.000000e+00, %1261
>  %1265 = fmul float 2.000000e+00, %1262
>  %1266 = fmul float 2.000000e+00, %1263
>  %1267 = fsub float -0.000000e+00, %1264
>  %1268 = fadd float %78, %1267
>  %1269 = fsub float -0.000000e+00, %1265
>  %1270 = fadd float %79, %1269
>  %1271 = fsub float -0.000000e+00, %1266
>  %1272 = fadd float %80, %1271
>  %1273 = fmul float %1268, %1195
>  %1274 = fmul float %1270, %1195
>  %1275 = fmul float %1272, %1195
>  %1276 = fmul float %1213, %280
>  %1277 = fmul float %1214, %281
>  %1278 = fadd float %1277, %1276
>  %1279 = fmul float %1215, %282
>  %1280 = fadd float %1278, %1279
>  %1281 = fmul float %1233, %280
>  %1282 = fmul float %1234, %281
>  %1283 = fadd float %1282, %1281
>  %1284 = fmul float %1235, %282
>  %1285 = fadd float %1283, %1284
>  %1286 = fmul float %1253, %280
>  %1287 = fmul float %1254, %281
>  %1288 = fadd float %1287, %1286
>  %1289 = fmul float %1255, %282
>  %1290 = fadd float %1288, %1289
>  %1291 = fmul float %1273, %280
>  %1292 = fmul float %1274, %281
>  %1293 = fadd float %1292, %1291
>  %1294 = fmul float %1275, %282
>  %1295 = fadd float %1293, %1294
>  %1296 = fcmp oge float %1280, 0.000000e+00
>  %1297 = sext i1 %1296 to i32
>  %1298 = bitcast i32 %1297 to float
>  %1299 = bitcast float %1298 to i32
>  %1300 = icmp ne i32 %1299, 0
>  %temp68.4 = select i1 %1300, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1301 = bitcast float %temp68.4 to i32
>  %1302 = sitofp i32 %1301 to float
>  %1303 = fmul float %1213, %1302
>  %1304 = fmul float %1214, %1302
>  %1305 = fmul float %1215, %1302
>  %1306 = fcmp oge float %1285, 0.000000e+00
>  %1307 = sext i1 %1306 to i32
>  %1308 = bitcast i32 %1307 to float
>  %1309 = bitcast float %1308 to i32
>  %1310 = icmp ne i32 %1309, 0
>  %.224 = select i1 %1310, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1311 = bitcast float %.224 to i32
>  %1312 = sitofp i32 %1311 to float
>  %1313 = fmul float %1233, %1312
>  %1314 = fmul float %1234, %1312
>  %1315 = fmul float %1235, %1312
>  %1316 = fcmp oge float %1290, 0.000000e+00
>  %1317 = sext i1 %1316 to i32
>  %1318 = bitcast i32 %1317 to float
>  %1319 = bitcast float %1318 to i32
>  %1320 = icmp ne i32 %1319, 0
>  %temp68.6 = select i1 %1320, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1321 = bitcast float %temp68.6 to i32
>  %1322 = sitofp i32 %1321 to float
>  %1323 = fmul float %1253, %1322
>  %1324 = fmul float %1254, %1322
>  %1325 = fmul float %1255, %1322
>  %1326 = fcmp oge float %1295, 0.000000e+00
>  %1327 = sext i1 %1326 to i32
>  %1328 = bitcast i32 %1327 to float
>  %1329 = bitcast float %1328 to i32
>  %1330 = icmp ne i32 %1329, 0
>  %.225 = select i1 %1330, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1331 = bitcast float %.225 to i32
>  %1332 = sitofp i32 %1331 to float
>  %1333 = fmul float %1273, %1332
>  %1334 = fmul float %1274, %1332
>  %1335 = fmul float %1275, %1332
>  %1336 = fadd float %290, %1303
>  %1337 = fadd float %292, %1304
>  %1338 = fadd float %290, %1313
>  %1339 = fadd float %292, %1314
>  %1340 = fadd float %290, %1323
>  %1341 = fadd float %292, %1324
>  %1342 = fadd float %290, %1333
>  %1343 = fadd float %292, %1334
>  %1344 = fadd float %294, %1305
>  %1345 = fadd float %294, %1315
>  %1346 = fadd float %294, %1325
>  %1347 = fadd float %294, %1335
>  %1348 = fsub float -0.000000e+00, %1344
>  %1349 = fdiv float 1.000000e+00, %1348
>  %1350 = fsub float -0.000000e+00, %1345
>  %1351 = fdiv float 1.000000e+00, %1350
>  %1352 = fmul float %1336, %1349
>  %1353 = fmul float %1337, %1349
>  %1354 = fmul float %1338, %1351
>  %1355 = fmul float %1339, %1351
>  %1356 = fsub float -0.000000e+00, %29
>  %1357 = fmul float %1352, %28
>  %1358 = fadd float %1357, %1356
>  %1359 = fsub float -0.000000e+00, %31
>  %1360 = fmul float %1353, %30
>  %1361 = fadd float %1360, %1359
>  %1362 = fsub float -0.000000e+00, %29
>  %1363 = fmul float %1354, %28
>  %1364 = fadd float %1363, %1362
>  %1365 = fsub float -0.000000e+00, %31
>  %1366 = fmul float %1355, %30
>  %1367 = fadd float %1366, %1365
>  %1368 = fsub float -0.000000e+00, %1346
>  %1369 = fdiv float 1.000000e+00, %1368
>  %1370 = fsub float -0.000000e+00, %1347
>  %1371 = fdiv float 1.000000e+00, %1370
>  %1372 = fmul float %1340, %1369
>  %1373 = fmul float %1341, %1369
>  %1374 = fmul float %1342, %1371
>  %1375 = fmul float %1343, %1371
>  %1376 = fsub float -0.000000e+00, %29
>  %1377 = fmul float %1372, %28
>  %1378 = fadd float %1377, %1376
>  %1379 = fsub float -0.000000e+00, %31
>  %1380 = fmul float %1373, %30
>  %1381 = fadd float %1380, %1379
>  %1382 = fsub float -0.000000e+00, %29
>  %1383 = fmul float %1374, %28
>  %1384 = fadd float %1383, %1382
>  %1385 = fsub float -0.000000e+00, %31
>  %1386 = fmul float %1375, %30
>  %1387 = fadd float %1386, %1385
>  %1388 = fmul float %1358, 5.000000e-01
>  %1389 = fadd float %1388, 5.000000e-01
>  %1390 = fmul float %1361, -5.000000e-01
>  %1391 = fadd float %1390, 5.000000e-01
>  %1392 = fmul float %1364, 5.000000e-01
>  %1393 = fadd float %1392, 5.000000e-01
>  %1394 = fmul float %1367, -5.000000e-01
>  %1395 = fadd float %1394, 5.000000e-01
>  %1396 = fmul float %1378, 5.000000e-01
>  %1397 = fadd float %1396, 5.000000e-01
>  %1398 = fmul float %1381, -5.000000e-01
>  %1399 = fadd float %1398, 5.000000e-01
>  %1400 = fmul float %1384, 5.000000e-01
>  %1401 = fadd float %1400, 5.000000e-01
>  %1402 = fmul float %1387, -5.000000e-01
>  %1403 = fadd float %1402, 5.000000e-01
>  %1404 = call float @llvm.AMDIL.clamp.(float %1389, float 0.000000e+00, float 1.000000e+00)
>  %1405 = call float @llvm.AMDIL.clamp.(float %1391, float 0.000000e+00, float 1.000000e+00)
>  %1406 = call float @llvm.AMDIL.clamp.(float %1393, float 0.000000e+00, float 1.000000e+00)
>  %1407 = call float @llvm.AMDIL.clamp.(float %1395, float 0.000000e+00, float 1.000000e+00)
>  %1408 = call float @llvm.AMDIL.clamp.(float %1397, float 0.000000e+00, float 1.000000e+00)
>  %1409 = call float @llvm.AMDIL.clamp.(float %1399, float 0.000000e+00, float 1.000000e+00)
>  %1410 = call float @llvm.AMDIL.clamp.(float %1401, float 0.000000e+00, float 1.000000e+00)
>  %1411 = call float @llvm.AMDIL.clamp.(float %1403, float 0.000000e+00, float 1.000000e+00)
>  %1412 = bitcast float %1404 to i32
>  %1413 = bitcast float %1405 to i32
>  %1414 = insertelement <2 x i32> undef, i32 %1412, i32 0
>  %1415 = insertelement <2 x i32> %1414, i32 %1413, i32 1
>  %1416 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1415, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1417 = extractelement <4 x float> %1416, i32 0
>  %1418 = bitcast float %1406 to i32
>  %1419 = bitcast float %1407 to i32
>  %1420 = insertelement <2 x i32> undef, i32 %1418, i32 0
>  %1421 = insertelement <2 x i32> %1420, i32 %1419, i32 1
>  %1422 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1421, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1423 = extractelement <4 x float> %1422, i32 0
>  %1424 = bitcast float %1408 to i32
>  %1425 = bitcast float %1409 to i32
>  %1426 = insertelement <2 x i32> undef, i32 %1424, i32 0
>  %1427 = insertelement <2 x i32> %1426, i32 %1425, i32 1
>  %1428 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1427, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1429 = extractelement <4 x float> %1428, i32 0
>  %1430 = bitcast float %1410 to i32
>  %1431 = bitcast float %1411 to i32
>  %1432 = insertelement <2 x i32> undef, i32 %1430, i32 0
>  %1433 = insertelement <2 x i32> %1432, i32 %1431, i32 1
>  %1434 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1433, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1435 = extractelement <4 x float> %1434, i32 0
>  %1436 = call float @fabs(float %1417)
>  %1437 = call float @fabs(float %1423)
>  %1438 = call float @fabs(float %1429)
>  %1439 = call float @fabs(float %1435)
>  %1440 = fsub float -0.000000e+00, %26
>  %1441 = fmul float %1436, %27
>  %1442 = fadd float %1441, %1440
>  %1443 = fsub float -0.000000e+00, %26
>  %1444 = fmul float %1437, %27
>  %1445 = fadd float %1444, %1443
>  %1446 = fsub float -0.000000e+00, %26
>  %1447 = fmul float %1438, %27
>  %1448 = fadd float %1447, %1446
>  %1449 = fsub float -0.000000e+00, %26
>  %1450 = fmul float %1439, %27
>  %1451 = fadd float %1450, %1449
>  %1452 = fsub float -0.000000e+00, %1344
>  %1453 = fadd float %1442, %1452
>  %1454 = fsub float -0.000000e+00, %1345
>  %1455 = fadd float %1445, %1454
>  %1456 = fsub float -0.000000e+00, %1346
>  %1457 = fadd float %1448, %1456
>  %1458 = fsub float -0.000000e+00, %1347
>  %1459 = fadd float %1451, %1458
>  %1460 = fmul float %1189, 2.000000e+00
>  %1461 = fmul float %1191, 2.000000e+00
>  %1462 = fmul float %1193, 2.000000e+00
>  %1463 = fmul float %1195, 2.000000e+00
>  %1464 = fcmp oge float %1453, %1460
>  %1465 = sext i1 %1464 to i32
>  %1466 = bitcast i32 %1465 to float
>  %1467 = bitcast float %1466 to i32
>  %1468 = and i32 %1467, 1065353216
>  %1469 = bitcast i32 %1468 to float
>  %1470 = fcmp oge float %1455, %1461
>  %1471 = sext i1 %1470 to i32
>  %1472 = bitcast i32 %1471 to float
>  %1473 = bitcast float %1472 to i32
>  %1474 = and i32 %1473, 1065353216
>  %1475 = bitcast i32 %1474 to float
>  %1476 = fcmp oge float %1457, %1462
>  %1477 = sext i1 %1476 to i32
>  %1478 = bitcast i32 %1477 to float
>  %1479 = bitcast float %1478 to i32
>  %1480 = and i32 %1479, 1065353216
>  %1481 = bitcast i32 %1480 to float
>  %1482 = fcmp oge float %1459, %1463
>  %1483 = sext i1 %1482 to i32
>  %1484 = bitcast i32 %1483 to float
>  %1485 = bitcast float %1484 to i32
>  %1486 = and i32 %1485, 1065353216
>  %1487 = bitcast i32 %1486 to float
>  %1488 = fcmp oeq float %1442, 0.000000e+00
>  %1489 = sext i1 %1488 to i32
>  %1490 = bitcast i32 %1489 to float
>  %1491 = bitcast float %1490 to i32
>  %1492 = icmp ne i32 %1491, 0
>  %temp92.2 = select i1 %1492, float 0x36A0000000000000, float 0.000000e+00
>  %1493 = fcmp oeq float %1445, 0.000000e+00
>  %1494 = sext i1 %1493 to i32
>  %1495 = bitcast i32 %1494 to float
>  %1496 = bitcast float %1495 to i32
>  %1497 = icmp ne i32 %1496, 0
>  %.226 = select i1 %1497, float 0x36A0000000000000, float 0.000000e+00
>  %1498 = fcmp oeq float %1448, 0.000000e+00
>  %1499 = sext i1 %1498 to i32
>  %1500 = bitcast i32 %1499 to float
>  %1501 = bitcast float %1500 to i32
>  %1502 = icmp ne i32 %1501, 0
>  %temp104.2 = select i1 %1502, float 0x36A0000000000000, float 0.000000e+00
>  %1503 = fcmp oeq float %1451, 0.000000e+00
>  %1504 = sext i1 %1503 to i32
>  %1505 = bitcast i32 %1504 to float
>  %1506 = bitcast float %1505 to i32
>  %1507 = icmp ne i32 %1506, 0
>  %.227 = select i1 %1507, float 0x36A0000000000000, float 0.000000e+00
>  %1508 = bitcast float %temp92.2 to i32
>  %1509 = sitofp i32 %1508 to float
>  %1510 = bitcast float %.226 to i32
>  %1511 = sitofp i32 %1510 to float
>  %1512 = bitcast float %temp104.2 to i32
>  %1513 = sitofp i32 %1512 to float
>  %1514 = bitcast float %.227 to i32
>  %1515 = sitofp i32 %1514 to float
>  %1516 = fcmp oge float 0.000000e+00, %1417
>  %1517 = sext i1 %1516 to i32
>  %1518 = bitcast i32 %1517 to float
>  %1519 = bitcast float %1518 to i32
>  %1520 = and i32 %1519, 1065353216
>  %1521 = bitcast i32 %1520 to float
>  %1522 = fcmp oge float 0.000000e+00, %1423
>  %1523 = sext i1 %1522 to i32
>  %1524 = bitcast i32 %1523 to float
>  %1525 = bitcast float %1524 to i32
>  %1526 = and i32 %1525, 1065353216
>  %1527 = bitcast i32 %1526 to float
>  %1528 = fcmp oge float 0.000000e+00, %1429
>  %1529 = sext i1 %1528 to i32
>  %1530 = bitcast i32 %1529 to float
>  %1531 = bitcast float %1530 to i32
>  %1532 = and i32 %1531, 1065353216
>  %1533 = bitcast i32 %1532 to float
>  %1534 = fcmp oge float 0.000000e+00, %1435
>  %1535 = sext i1 %1534 to i32
>  %1536 = bitcast i32 %1535 to float
>  %1537 = bitcast float %1536 to i32
>  %1538 = and i32 %1537, 1065353216
>  %1539 = bitcast i32 %1538 to float
>  %1540 = fadd float %1469, %1509
>  %1541 = fadd float %1475, %1511
>  %1542 = fadd float %1481, %1513
>  %1543 = fadd float %1487, %1515
>  %1544 = fmul float %1521, %339
>  %1545 = fadd float %1544, %1540
>  %1546 = fmul float %1527, %339
>  %1547 = fadd float %1546, %1541
>  %1548 = fmul float %1533, %339
>  %1549 = fadd float %1548, %1542
>  %1550 = fmul float %1539, %339
>  %1551 = fadd float %1550, %1543
>  %1552 = call float @llvm.AMDIL.clamp.(float %1545, float 0.000000e+00, float 1.000000e+00)
>  %1553 = call float @llvm.AMDIL.clamp.(float %1547, float 0.000000e+00, float 1.000000e+00)
>  %1554 = call float @llvm.AMDIL.clamp.(float %1549, float 0.000000e+00, float 1.000000e+00)
>  %1555 = call float @llvm.AMDIL.clamp.(float %1551, float 0.000000e+00, float 1.000000e+00)
>  %1556 = fmul float %1552, 1.000000e+00
>  %1557 = fmul float %1553, 1.000000e+00
>  %1558 = fadd float %1556, %1557
>  %1559 = fmul float %1554, 1.000000e+00
>  %1560 = fadd float %1558, %1559
>  %1561 = fmul float %1555, 1.000000e+00
>  %1562 = fadd float %1560, %1561
>  %1563 = fadd float %1142, %1562
>  %1564 = fcmp oge float %1453, 0.000000e+00
>  %1565 = sext i1 %1564 to i32
>  %1566 = bitcast i32 %1565 to float
>  %1567 = bitcast float %1566 to i32
>  %1568 = and i32 %1567, 1065353216
>  %1569 = bitcast i32 %1568 to float
>  %1570 = fcmp oge float %1455, 0.000000e+00
>  %1571 = sext i1 %1570 to i32
>  %1572 = bitcast i32 %1571 to float
>  %1573 = bitcast float %1572 to i32
>  %1574 = and i32 %1573, 1065353216
>  %1575 = bitcast i32 %1574 to float
>  %1576 = fcmp oge float %1457, 0.000000e+00
>  %1577 = sext i1 %1576 to i32
>  %1578 = bitcast i32 %1577 to float
>  %1579 = bitcast float %1578 to i32
>  %1580 = and i32 %1579, 1065353216
>  %1581 = bitcast i32 %1580 to float
>  %1582 = fcmp oge float %1459, 0.000000e+00
>  %1583 = sext i1 %1582 to i32
>  %1584 = bitcast i32 %1583 to float
>  %1585 = bitcast float %1584 to i32
>  %1586 = and i32 %1585, 1065353216
>  %1587 = bitcast i32 %1586 to float
>  %1588 = fsub float -0.000000e+00, %1552
>  %1589 = fadd float 1.000000e+00, %1588
>  %1590 = fsub float -0.000000e+00, %1553
>  %1591 = fadd float 1.000000e+00, %1590
>  %1592 = fsub float -0.000000e+00, %1554
>  %1593 = fadd float 1.000000e+00, %1592
>  %1594 = fsub float -0.000000e+00, %1555
>  %1595 = fadd float 1.000000e+00, %1594
>  %1596 = fmul float %1569, %1589
>  %1597 = fmul float %1575, %1591
>  %1598 = fmul float %1581, %1593
>  %1599 = fmul float %1587, %1595
>  %1600 = fmul float %1596, 1.000000e+00
>  %1601 = fmul float %1597, 1.000000e+00
>  %1602 = fadd float %1600, %1601
>  %1603 = fmul float %1598, 1.000000e+00
>  %1604 = fadd float %1602, %1603
>  %1605 = fmul float %1599, 1.000000e+00
>  %1606 = fadd float %1604, %1605
>  %1607 = fadd float %1186, %1606
>  %1608 = fmul float %333, 4.000000e+00
>  %1609 = fsub float -0.000000e+00, %1608
>  %1610 = fadd float %1189, %1609
>  %1611 = fsub float -0.000000e+00, %1608
>  %1612 = fadd float %1191, %1611
>  %1613 = fsub float -0.000000e+00, %1608
>  %1614 = fadd float %1193, %1613
>  %1615 = fsub float -0.000000e+00, %1608
>  %1616 = fadd float %1195, %1615
>  %1617 = fmul float %313, %81
>  %1618 = fmul float %314, %82
>  %1619 = fadd float %1618, %1617
>  %1620 = fmul float %315, %83
>  %1621 = fadd float %1619, %1620
>  %1622 = fmul float %1621, %313
>  %1623 = fmul float %1621, %314
>  %1624 = fmul float %1621, %315
>  %1625 = fmul float 2.000000e+00, %1622
>  %1626 = fmul float 2.000000e+00, %1623
>  %1627 = fmul float 2.000000e+00, %1624
>  %1628 = fsub float -0.000000e+00, %1625
>  %1629 = fadd float %81, %1628
>  %1630 = fsub float -0.000000e+00, %1626
>  %1631 = fadd float %82, %1630
>  %1632 = fsub float -0.000000e+00, %1627
>  %1633 = fadd float %83, %1632
>  %1634 = fmul float %1629, %1610
>  %1635 = fmul float %1631, %1610
>  %1636 = fmul float %1633, %1610
>  %1637 = fmul float %313, %84
>  %1638 = fmul float %314, %85
>  %1639 = fadd float %1638, %1637
>  %1640 = fmul float %315, %86
>  %1641 = fadd float %1639, %1640
>  %1642 = fmul float %1641, %313
>  %1643 = fmul float %1641, %314
>  %1644 = fmul float %1641, %315
>  %1645 = fmul float 2.000000e+00, %1642
>  %1646 = fmul float 2.000000e+00, %1643
>  %1647 = fmul float 2.000000e+00, %1644
>  %1648 = fsub float -0.000000e+00, %1645
>  %1649 = fadd float %84, %1648
>  %1650 = fsub float -0.000000e+00, %1646
>  %1651 = fadd float %85, %1650
>  %1652 = fsub float -0.000000e+00, %1647
>  %1653 = fadd float %86, %1652
>  %1654 = fmul float %1649, %1612
>  %1655 = fmul float %1651, %1612
>  %1656 = fmul float %1653, %1612
>  %1657 = fmul float %313, %87
>  %1658 = fmul float %314, %88
>  %1659 = fadd float %1658, %1657
>  %1660 = fmul float %315, %89
>  %1661 = fadd float %1659, %1660
>  %1662 = fmul float %1661, %313
>  %1663 = fmul float %1661, %314
>  %1664 = fmul float %1661, %315
>  %1665 = fmul float 2.000000e+00, %1662
>  %1666 = fmul float 2.000000e+00, %1663
>  %1667 = fmul float 2.000000e+00, %1664
>  %1668 = fsub float -0.000000e+00, %1665
>  %1669 = fadd float %87, %1668
>  %1670 = fsub float -0.000000e+00, %1666
>  %1671 = fadd float %88, %1670
>  %1672 = fsub float -0.000000e+00, %1667
>  %1673 = fadd float %89, %1672
>  %1674 = fmul float %1669, %1614
>  %1675 = fmul float %1671, %1614
>  %1676 = fmul float %1673, %1614
>  %1677 = fmul float %313, %90
>  %1678 = fmul float %314, %91
>  %1679 = fadd float %1678, %1677
>  %1680 = fmul float %315, %92
>  %1681 = fadd float %1679, %1680
>  %1682 = fmul float %1681, %313
>  %1683 = fmul float %1681, %314
>  %1684 = fmul float %1681, %315
>  %1685 = fmul float 2.000000e+00, %1682
>  %1686 = fmul float 2.000000e+00, %1683
>  %1687 = fmul float 2.000000e+00, %1684
>  %1688 = fsub float -0.000000e+00, %1685
>  %1689 = fadd float %90, %1688
>  %1690 = fsub float -0.000000e+00, %1686
>  %1691 = fadd float %91, %1690
>  %1692 = fsub float -0.000000e+00, %1687
>  %1693 = fadd float %92, %1692
>  %1694 = fmul float %1689, %1616
>  %1695 = fmul float %1691, %1616
>  %1696 = fmul float %1693, %1616
>  %1697 = fmul float %1634, %280
>  %1698 = fmul float %1635, %281
>  %1699 = fadd float %1698, %1697
>  %1700 = fmul float %1636, %282
>  %1701 = fadd float %1699, %1700
>  %1702 = fmul float %1654, %280
>  %1703 = fmul float %1655, %281
>  %1704 = fadd float %1703, %1702
>  %1705 = fmul float %1656, %282
>  %1706 = fadd float %1704, %1705
>  %1707 = fmul float %1674, %280
>  %1708 = fmul float %1675, %281
>  %1709 = fadd float %1708, %1707
>  %1710 = fmul float %1676, %282
>  %1711 = fadd float %1709, %1710
>  %1712 = fmul float %1694, %280
>  %1713 = fmul float %1695, %281
>  %1714 = fadd float %1713, %1712
>  %1715 = fmul float %1696, %282
>  %1716 = fadd float %1714, %1715
>  %1717 = fcmp oge float %1701, 0.000000e+00
>  %1718 = sext i1 %1717 to i32
>  %1719 = bitcast i32 %1718 to float
>  %1720 = bitcast float %1719 to i32
>  %1721 = icmp ne i32 %1720, 0
>  %temp4.0 = select i1 %1721, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1722 = bitcast float %temp4.0 to i32
>  %1723 = sitofp i32 %1722 to float
>  %1724 = fmul float %1634, %1723
>  %1725 = fmul float %1635, %1723
>  %1726 = fmul float %1636, %1723
>  %1727 = fcmp oge float %1706, 0.000000e+00
>  %1728 = sext i1 %1727 to i32
>  %1729 = bitcast i32 %1728 to float
>  %1730 = bitcast float %1729 to i32
>  %1731 = icmp ne i32 %1730, 0
>  %.228 = select i1 %1731, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1732 = bitcast float %.228 to i32
>  %1733 = sitofp i32 %1732 to float
>  %1734 = fmul float %1654, %1733
>  %1735 = fmul float %1655, %1733
>  %1736 = fmul float %1656, %1733
>  %1737 = fcmp oge float %1711, 0.000000e+00
>  %1738 = sext i1 %1737 to i32
>  %1739 = bitcast i32 %1738 to float
>  %1740 = bitcast float %1739 to i32
>  %1741 = icmp ne i32 %1740, 0
>  %temp4.2 = select i1 %1741, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1742 = bitcast float %temp4.2 to i32
>  %1743 = sitofp i32 %1742 to float
>  %1744 = fmul float %1674, %1743
>  %1745 = fmul float %1675, %1743
>  %1746 = fmul float %1676, %1743
>  %1747 = fcmp oge float %1716, 0.000000e+00
>  %1748 = sext i1 %1747 to i32
>  %1749 = bitcast i32 %1748 to float
>  %1750 = bitcast float %1749 to i32
>  %1751 = icmp ne i32 %1750, 0
>  %.229 = select i1 %1751, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1752 = bitcast float %.229 to i32
>  %1753 = sitofp i32 %1752 to float
>  %1754 = fmul float %1694, %1753
>  %1755 = fmul float %1695, %1753
>  %1756 = fmul float %1696, %1753
>  %1757 = fadd float %290, %1724
>  %1758 = fadd float %292, %1725
>  %1759 = fadd float %290, %1734
>  %1760 = fadd float %292, %1735
>  %1761 = fadd float %290, %1744
>  %1762 = fadd float %292, %1745
>  %1763 = fadd float %290, %1754
>  %1764 = fadd float %292, %1755
>  %1765 = fadd float %294, %1726
>  %1766 = fadd float %294, %1736
>  %1767 = fadd float %294, %1746
>  %1768 = fadd float %294, %1756
>  %1769 = fsub float -0.000000e+00, %1765
>  %1770 = fdiv float 1.000000e+00, %1769
>  %1771 = fsub float -0.000000e+00, %1766
>  %1772 = fdiv float 1.000000e+00, %1771
>  %1773 = fmul float %1757, %1770
>  %1774 = fmul float %1758, %1770
>  %1775 = fmul float %1759, %1772
>  %1776 = fmul float %1760, %1772
>  %1777 = fsub float -0.000000e+00, %29
>  %1778 = fmul float %1773, %28
>  %1779 = fadd float %1778, %1777
>  %1780 = fsub float -0.000000e+00, %31
>  %1781 = fmul float %1774, %30
>  %1782 = fadd float %1781, %1780
>  %1783 = fsub float -0.000000e+00, %29
>  %1784 = fmul float %1775, %28
>  %1785 = fadd float %1784, %1783
>  %1786 = fsub float -0.000000e+00, %31
>  %1787 = fmul float %1776, %30
>  %1788 = fadd float %1787, %1786
>  %1789 = fsub float -0.000000e+00, %1767
>  %1790 = fdiv float 1.000000e+00, %1789
>  %1791 = fsub float -0.000000e+00, %1768
>  %1792 = fdiv float 1.000000e+00, %1791
>  %1793 = fmul float %1761, %1790
>  %1794 = fmul float %1762, %1790
>  %1795 = fmul float %1763, %1792
>  %1796 = fmul float %1764, %1792
>  %1797 = fsub float -0.000000e+00, %29
>  %1798 = fmul float %1793, %28
>  %1799 = fadd float %1798, %1797
>  %1800 = fsub float -0.000000e+00, %31
>  %1801 = fmul float %1794, %30
>  %1802 = fadd float %1801, %1800
>  %1803 = fsub float -0.000000e+00, %29
>  %1804 = fmul float %1795, %28
>  %1805 = fadd float %1804, %1803
>  %1806 = fsub float -0.000000e+00, %31
>  %1807 = fmul float %1796, %30
>  %1808 = fadd float %1807, %1806
>  %1809 = fmul float %1779, 5.000000e-01
>  %1810 = fadd float %1809, 5.000000e-01
>  %1811 = fmul float %1782, -5.000000e-01
>  %1812 = fadd float %1811, 5.000000e-01
>  %1813 = fmul float %1785, 5.000000e-01
>  %1814 = fadd float %1813, 5.000000e-01
>  %1815 = fmul float %1788, -5.000000e-01
>  %1816 = fadd float %1815, 5.000000e-01
>  %1817 = fmul float %1799, 5.000000e-01
>  %1818 = fadd float %1817, 5.000000e-01
>  %1819 = fmul float %1802, -5.000000e-01
>  %1820 = fadd float %1819, 5.000000e-01
>  %1821 = fmul float %1805, 5.000000e-01
>  %1822 = fadd float %1821, 5.000000e-01
>  %1823 = fmul float %1808, -5.000000e-01
>  %1824 = fadd float %1823, 5.000000e-01
>  %1825 = call float @llvm.AMDIL.clamp.(float %1810, float 0.000000e+00, float 1.000000e+00)
>  %1826 = call float @llvm.AMDIL.clamp.(float %1812, float 0.000000e+00, float 1.000000e+00)
>  %1827 = call float @llvm.AMDIL.clamp.(float %1814, float 0.000000e+00, float 1.000000e+00)
>  %1828 = call float @llvm.AMDIL.clamp.(float %1816, float 0.000000e+00, float 1.000000e+00)
>  %1829 = call float @llvm.AMDIL.clamp.(float %1818, float 0.000000e+00, float 1.000000e+00)
>  %1830 = call float @llvm.AMDIL.clamp.(float %1820, float 0.000000e+00, float 1.000000e+00)
>  %1831 = call float @llvm.AMDIL.clamp.(float %1822, float 0.000000e+00, float 1.000000e+00)
>  %1832 = call float @llvm.AMDIL.clamp.(float %1824, float 0.000000e+00, float 1.000000e+00)
>  %1833 = bitcast float %1825 to i32
>  %1834 = bitcast float %1826 to i32
>  %1835 = insertelement <2 x i32> undef, i32 %1833, i32 0
>  %1836 = insertelement <2 x i32> %1835, i32 %1834, i32 1
>  %1837 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1836, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1838 = extractelement <4 x float> %1837, i32 0
>  %1839 = bitcast float %1827 to i32
>  %1840 = bitcast float %1828 to i32
>  %1841 = insertelement <2 x i32> undef, i32 %1839, i32 0
>  %1842 = insertelement <2 x i32> %1841, i32 %1840, i32 1
>  %1843 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1842, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1844 = extractelement <4 x float> %1843, i32 0
>  %1845 = bitcast float %1829 to i32
>  %1846 = bitcast float %1830 to i32
>  %1847 = insertelement <2 x i32> undef, i32 %1845, i32 0
>  %1848 = insertelement <2 x i32> %1847, i32 %1846, i32 1
>  %1849 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1848, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1850 = extractelement <4 x float> %1849, i32 0
>  %1851 = bitcast float %1831 to i32
>  %1852 = bitcast float %1832 to i32
>  %1853 = insertelement <2 x i32> undef, i32 %1851, i32 0
>  %1854 = insertelement <2 x i32> %1853, i32 %1852, i32 1
>  %1855 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1854, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1856 = extractelement <4 x float> %1855, i32 0
>  %1857 = call float @fabs(float %1838)
>  %1858 = call float @fabs(float %1844)
>  %1859 = call float @fabs(float %1850)
>  %1860 = call float @fabs(float %1856)
>  %1861 = fsub float -0.000000e+00, %26
>  %1862 = fmul float %1857, %27
>  %1863 = fadd float %1862, %1861
>  %1864 = fsub float -0.000000e+00, %26
>  %1865 = fmul float %1858, %27
>  %1866 = fadd float %1865, %1864
>  %1867 = fsub float -0.000000e+00, %26
>  %1868 = fmul float %1859, %27
>  %1869 = fadd float %1868, %1867
>  %1870 = fsub float -0.000000e+00, %26
>  %1871 = fmul float %1860, %27
>  %1872 = fadd float %1871, %1870
>  %1873 = fsub float -0.000000e+00, %1765
>  %1874 = fadd float %1863, %1873
>  %1875 = fsub float -0.000000e+00, %1766
>  %1876 = fadd float %1866, %1875
>  %1877 = fsub float -0.000000e+00, %1767
>  %1878 = fadd float %1869, %1877
>  %1879 = fsub float -0.000000e+00, %1768
>  %1880 = fadd float %1872, %1879
>  %1881 = fmul float %1610, 2.000000e+00
>  %1882 = fmul float %1612, 2.000000e+00
>  %1883 = fmul float %1614, 2.000000e+00
>  %1884 = fmul float %1616, 2.000000e+00
>  %1885 = fcmp oge float %1874, %1881
>  %1886 = sext i1 %1885 to i32
>  %1887 = bitcast i32 %1886 to float
>  %1888 = bitcast float %1887 to i32
>  %1889 = and i32 %1888, 1065353216
>  %1890 = bitcast i32 %1889 to float
>  %1891 = fcmp oge float %1876, %1882
>  %1892 = sext i1 %1891 to i32
>  %1893 = bitcast i32 %1892 to float
>  %1894 = bitcast float %1893 to i32
>  %1895 = and i32 %1894, 1065353216
>  %1896 = bitcast i32 %1895 to float
>  %1897 = fcmp oge float %1878, %1883
>  %1898 = sext i1 %1897 to i32
>  %1899 = bitcast i32 %1898 to float
>  %1900 = bitcast float %1899 to i32
>  %1901 = and i32 %1900, 1065353216
>  %1902 = bitcast i32 %1901 to float
>  %1903 = fcmp oge float %1880, %1884
>  %1904 = sext i1 %1903 to i32
>  %1905 = bitcast i32 %1904 to float
>  %1906 = bitcast float %1905 to i32
>  %1907 = and i32 %1906, 1065353216
>  %1908 = bitcast i32 %1907 to float
>  %1909 = fcmp oeq float %1863, 0.000000e+00
>  %1910 = sext i1 %1909 to i32
>  %1911 = bitcast i32 %1910 to float
>  %1912 = bitcast float %1911 to i32
>  %1913 = icmp ne i32 %1912, 0
>  %temp12.0 = select i1 %1913, float 0x36A0000000000000, float 0.000000e+00
>  %1914 = fcmp oeq float %1866, 0.000000e+00
>  %1915 = sext i1 %1914 to i32
>  %1916 = bitcast i32 %1915 to float
>  %1917 = bitcast float %1916 to i32
>  %1918 = icmp ne i32 %1917, 0
>  %.230 = select i1 %1918, float 0x36A0000000000000, float 0.000000e+00
>  %1919 = fcmp oeq float %1869, 0.000000e+00
>  %1920 = sext i1 %1919 to i32
>  %1921 = bitcast i32 %1920 to float
>  %1922 = bitcast float %1921 to i32
>  %1923 = icmp ne i32 %1922, 0
>  %temp48.4 = select i1 %1923, float 0x36A0000000000000, float 0.000000e+00
>  %1924 = fcmp oeq float %1872, 0.000000e+00
>  %1925 = sext i1 %1924 to i32
>  %1926 = bitcast i32 %1925 to float
>  %1927 = bitcast float %1926 to i32
>  %1928 = icmp ne i32 %1927, 0
>  %.231 = select i1 %1928, float 0x36A0000000000000, float 0.000000e+00
>  %1929 = bitcast float %temp12.0 to i32
>  %1930 = sitofp i32 %1929 to float
>  %1931 = bitcast float %.230 to i32
>  %1932 = sitofp i32 %1931 to float
>  %1933 = bitcast float %temp48.4 to i32
>  %1934 = sitofp i32 %1933 to float
>  %1935 = bitcast float %.231 to i32
>  %1936 = sitofp i32 %1935 to float
>  %1937 = fcmp oge float 0.000000e+00, %1838
>  %1938 = sext i1 %1937 to i32
>  %1939 = bitcast i32 %1938 to float
>  %1940 = bitcast float %1939 to i32
>  %1941 = and i32 %1940, 1065353216
>  %1942 = bitcast i32 %1941 to float
>  %1943 = fcmp oge float 0.000000e+00, %1844
>  %1944 = sext i1 %1943 to i32
>  %1945 = bitcast i32 %1944 to float
>  %1946 = bitcast float %1945 to i32
>  %1947 = and i32 %1946, 1065353216
>  %1948 = bitcast i32 %1947 to float
>  %1949 = fcmp oge float 0.000000e+00, %1850
>  %1950 = sext i1 %1949 to i32
>  %1951 = bitcast i32 %1950 to float
>  %1952 = bitcast float %1951 to i32
>  %1953 = and i32 %1952, 1065353216
>  %1954 = bitcast i32 %1953 to float
>  %1955 = fcmp oge float 0.000000e+00, %1856
>  %1956 = sext i1 %1955 to i32
>  %1957 = bitcast i32 %1956 to float
>  %1958 = bitcast float %1957 to i32
>  %1959 = and i32 %1958, 1065353216
>  %1960 = bitcast i32 %1959 to float
>  %1961 = fadd float %1890, %1930
>  %1962 = fadd float %1896, %1932
>  %1963 = fadd float %1902, %1934
>  %1964 = fadd float %1908, %1936
>  %1965 = fmul float %1942, %339
>  %1966 = fadd float %1965, %1961
>  %1967 = fmul float %1948, %339
>  %1968 = fadd float %1967, %1962
>  %1969 = fmul float %1954, %339
>  %1970 = fadd float %1969, %1963
>  %1971 = fmul float %1960, %339
>  %1972 = fadd float %1971, %1964
>  %1973 = call float @llvm.AMDIL.clamp.(float %1966, float 0.000000e+00, float 1.000000e+00)
>  %1974 = call float @llvm.AMDIL.clamp.(float %1968, float 0.000000e+00, float 1.000000e+00)
>  %1975 = call float @llvm.AMDIL.clamp.(float %1970, float 0.000000e+00, float 1.000000e+00)
>  %1976 = call float @llvm.AMDIL.clamp.(float %1972, float 0.000000e+00, float 1.000000e+00)
>  %1977 = fmul float %1973, 1.000000e+00
>  %1978 = fmul float %1974, 1.000000e+00
>  %1979 = fadd float %1977, %1978
>  %1980 = fmul float %1975, 1.000000e+00
>  %1981 = fadd float %1979, %1980
>  %1982 = fmul float %1976, 1.000000e+00
>  %1983 = fadd float %1981, %1982
>  %1984 = fadd float %1563, %1983
>  %1985 = fcmp oge float %1874, 0.000000e+00
>  %1986 = sext i1 %1985 to i32
>  %1987 = bitcast i32 %1986 to float
>  %1988 = bitcast float %1987 to i32
>  %1989 = and i32 %1988, 1065353216
>  %1990 = bitcast i32 %1989 to float
>  %1991 = fcmp oge float %1876, 0.000000e+00
>  %1992 = sext i1 %1991 to i32
>  %1993 = bitcast i32 %1992 to float
>  %1994 = bitcast float %1993 to i32
>  %1995 = and i32 %1994, 1065353216
>  %1996 = bitcast i32 %1995 to float
>  %1997 = fcmp oge float %1878, 0.000000e+00
>  %1998 = sext i1 %1997 to i32
>  %1999 = bitcast i32 %1998 to float
>  %2000 = bitcast float %1999 to i32
>  %2001 = and i32 %2000, 1065353216
>  %2002 = bitcast i32 %2001 to float
>  %2003 = fcmp oge float %1880, 0.000000e+00
>  %2004 = sext i1 %2003 to i32
>  %2005 = bitcast i32 %2004 to float
>  %2006 = bitcast float %2005 to i32
>  %2007 = and i32 %2006, 1065353216
>  %2008 = bitcast i32 %2007 to float
>  %2009 = fsub float -0.000000e+00, %1973
>  %2010 = fadd float 1.000000e+00, %2009
>  %2011 = fsub float -0.000000e+00, %1974
>  %2012 = fadd float 1.000000e+00, %2011
>  %2013 = fsub float -0.000000e+00, %1975
>  %2014 = fadd float 1.000000e+00, %2013
>  %2015 = fsub float -0.000000e+00, %1976
>  %2016 = fadd float 1.000000e+00, %2015
>  %2017 = fmul float %1990, %2010
>  %2018 = fmul float %1996, %2012
>  %2019 = fmul float %2002, %2014
>  %2020 = fmul float %2008, %2016
>  %2021 = fmul float %2017, 1.000000e+00
>  %2022 = fmul float %2018, 1.000000e+00
>  %2023 = fadd float %2021, %2022
>  %2024 = fmul float %2019, 1.000000e+00
>  %2025 = fadd float %2023, %2024
>  %2026 = fmul float %2020, 1.000000e+00
>  %2027 = fadd float %2025, %2026
>  %2028 = fadd float %1607, %2027
>  %2029 = fsub float -0.000000e+00, %1984
>  %2030 = fadd float 1.600000e+01, %2029
>  %2031 = fdiv float 1.000000e+00, %2030
>  %2032 = fmul float %2028, %2031
>  br label %ENDIF
>
>ENDIF:                                            ; preds = %main_body, %IF
>  %temp.0 = phi float [ %2032, %IF ], [ 0.000000e+00, %main_body ]
>  %2033 = fmul float %temp.0, %43
>  %2034 = call float @llvm.AMDIL.clamp.(float %2033, float 0.000000e+00, float 1.000000e+00)
>  %2035 = fsub float -0.000000e+00, %2034
>  %2036 = fadd float 1.000000e+00, %2035
>  %2037 = fmul float %2036, %2036
>  %2038 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
>  %2039 = bitcast i32 %2038 to float
>  %2040 = call i32 @llvm.SI.packf16(float 0.000000e+00, float %2037)
>  %2041 = bitcast i32 %2040 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %2039, float %2041, float %2039, float %2041)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.fraction.(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg80, %SGPR2_SGPR3 in %vreg81, %SGPR4_SGPR5 in %vreg82, %SGPR6 in %vreg83, %VGPR0 in %vreg84, %VGPR1 in %vreg85
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%SGPR24_SGPR25_SGPR26_SGPR27<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 17; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_FRACT_F32_e32 %VGPR2, %EXEC<imp-use>
>	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_ADD_F32_e32 5.000000e-01, %VGPR2<kill>, %EXEC<imp-use>
>	%SGPR21<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 19; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MUL_F32_e32 %SGPR21, %VGPR2<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 16; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_FRACT_F32_e32 %VGPR0, %EXEC<imp-use>
>	%VGPR0<def> = V_SUB_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e32 5.000000e-01, %VGPR0<kill>, %EXEC<imp-use>
>	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 18; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_MUL_F32_e32 %SGPR20, %VGPR0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%98](align=8)(tbaa=!"const")
>	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%95](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR1<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR0<def> = V_ADD_F32_e64 %VGPR1, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_MUL_F32_e32 %SGPR6, %VGPR0<kill>, %EXEC<imp-use>
>	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MOV_B32_e32 9.500000e-01, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_LT_F32_e64 %VGPR1, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR22<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 25; mem:LD4[<unknown>]
>	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
>	S_WAITCNT 127
>	%VGPR0<def> = V_MOV_B32_e32 %SGPR22<kill>, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC<imp-def>, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = S_XOR_B64 %EXEC, %SGPR0_SGPR1
>	S_CBRANCH_EXECZ <BB#2>, %EXEC
>    Successors according to CFG: BB#1(16) BB#2(16)
>
>BB#1: derived from LLVM BB %IF
>    Live Ins: %SGPR7 %SGPR6 %SGPR20 %SGPR21 %VGPR0 %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR1 %VGPR2 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR24_SGPR25_SGPR26_SGPR27 %VGPR3_VGPR4 %SGPR0_SGPR1
>    Predecessors according to CFG: BB#0
>	%SGPR28_SGPR29_SGPR30_SGPR31<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%104](align=8)(tbaa=!"const")
>	%SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%101](tbaa=!"const")
>	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 90; mem:LD4[<unknown>]
>	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 89; mem:LD4[<unknown>]
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 88; mem:LD4[<unknown>]
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 86; mem:LD4[<unknown>]
>	%SGPR22<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 85; mem:LD4[<unknown>]
>	%SGPR23<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 84; mem:LD4[<unknown>]
>	%SGPR40<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 82; mem:LD4[<unknown>]
>	%SGPR41<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 81; mem:LD4[<unknown>]
>	%SGPR42<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 80; mem:LD4[<unknown>]
>	%SGPR43<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 78; mem:LD4[<unknown>]
>	%SGPR44<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 77; mem:LD4[<unknown>]
>	%SGPR45<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 76; mem:LD4[<unknown>]
>	%SGPR46<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 74; mem:LD4[<unknown>]
>	%SGPR47<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 73; mem:LD4[<unknown>]
>	%SGPR48<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 72; mem:LD4[<unknown>]
>	%SGPR49<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 70; mem:LD4[<unknown>]
>	%SGPR50<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 69; mem:LD4[<unknown>]
>	%SGPR51<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 68; mem:LD4[<unknown>]
>	%SGPR52<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 66; mem:LD4[<unknown>]
>	%SGPR53<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 65; mem:LD4[<unknown>]
>	%SGPR54<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 64; mem:LD4[<unknown>]
>	%SGPR55<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 62; mem:LD4[<unknown>]
>	%SGPR56<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 61; mem:LD4[<unknown>]
>	%SGPR57<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 60; mem:LD4[<unknown>]
>	%SGPR58<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 58; mem:LD4[<unknown>]
>	%SGPR59<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 57; mem:LD4[<unknown>]
>	%SGPR60<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 56; mem:LD4[<unknown>]
>	%SGPR61<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 54; mem:LD4[<unknown>]
>	%SGPR62<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 53; mem:LD4[<unknown>]
>	%SGPR63<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 52; mem:LD4[<unknown>]
>	%SGPR64<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 50; mem:LD4[<unknown>]
>	%SGPR65<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 49; mem:LD4[<unknown>]
>	%SGPR66<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 48; mem:LD4[<unknown>]
>	%SGPR67<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 46; mem:LD4[<unknown>]
>	%SGPR68<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 45; mem:LD4[<unknown>]
>	%SGPR69<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 44; mem:LD4[<unknown>]
>	%SGPR70<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 42; mem:LD4[<unknown>]
>	%SGPR71<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 41; mem:LD4[<unknown>]
>	%SGPR72<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 40; mem:LD4[<unknown>]
>	%SGPR73<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 38; mem:LD4[<unknown>]
>	%SGPR74<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 37; mem:LD4[<unknown>]
>	%SGPR75<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 36; mem:LD4[<unknown>]
>	%SGPR76<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 34; mem:LD4[<unknown>]
>	%SGPR77<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 33; mem:LD4[<unknown>]
>	%SGPR78<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 32; mem:LD4[<unknown>]
>	%SGPR79<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 30; mem:LD4[<unknown>]
>	%SGPR80<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 29; mem:LD4[<unknown>]
>	%SGPR81<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 28; mem:LD4[<unknown>]
>	%SGPR82<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 26; mem:LD4[<unknown>]
>	%SGPR83<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 24; mem:LD4[<unknown>]
>	%SGPR84<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 23; mem:LD4[<unknown>]
>	%SGPR85<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 22; mem:LD4[<unknown>]
>	%SGPR86<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 21; mem:LD4[<unknown>]
>	%SGPR87<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 20; mem:LD4[<unknown>]
>	%SGPR88<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 13; mem:LD4[<unknown>]
>	%SGPR89<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 12; mem:LD4[<unknown>]
>	%SGPR90<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 11; mem:LD4[<unknown>]
>	%SGPR91<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 10; mem:LD4[<unknown>]
>	%SGPR92<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 9; mem:LD4[<unknown>]
>	%SGPR93<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 8; mem:LD4[<unknown>]
>	%SGPR94<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 3; mem:LD4[<unknown>]
>	%SGPR95<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 2; mem:LD4[<unknown>]
>	%SGPR96<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27, 1; mem:LD4[<unknown>]
>	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR24_SGPR25_SGPR26_SGPR27<kill>, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR83<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR21<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_ADD_F32_e64 %VGPR4, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
>	%VGPR7<def> = V_ADD_F32_e64 %VGPR3, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
>	%VGPR9<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR9<def> = V_ADD_F32_e64 %VGPR9<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e32 %SGPR6, %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_SUBREV_F32_e32 %VGPR2, %VGPR9, %EXEC<imp-use>
>	%VGPR10<def> = V_ADD_F32_e64 %VGPR10<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_SUB_F32_e64 %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MOV_B32_e32 %VGPR7, %EXEC<imp-use>, %VGPR11_VGPR12<imp-def>
>	%VGPR12<def> = V_MOV_B32_e32 %VGPR8, %EXEC<imp-use>
>	%VGPR12<def> = V_MOV_B32_e32 %VGPR6, %EXEC<imp-use>, %VGPR11_VGPR12<imp-def>
>	%VGPR11<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR11_VGPR12<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %SGPR6, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_SUBREV_F32_e32 %VGPR2, %VGPR11, %EXEC<imp-use>
>	%VGPR12<def> = V_ADD_F32_e64 %VGPR12<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%SGPR26_SGPR27<def> = V_CMP_LT_F32_e64 %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, %VGPR11<kill>, %SGPR26_SGPR27, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_ADD_F32_e64 %VGPR9, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR11<def> = V_ADD_F32_e32 %VGPR7, %VGPR7, %EXEC<imp-use>
>	%VGPR11<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_ADD_F32_e32 %SGPR92, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %VGPR10, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_RCP_F32_e32 %SGPR93, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR12, %EXEC<imp-use>
>	%VGPR13<def> = V_ADD_F32_e64 %VGPR3, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR13<def> = V_ADD_F32_e32 %SGPR92, %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_ADD_F32_e64 %VGPR2, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR13<def> = V_MUL_F32_e32 %VGPR14, %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR12, %EXEC<imp-use>
>	%VGPR11<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR13, %EXEC<imp-use>
>	%VGPR15<def> = V_CNDMASK_B32_e64 1.000000e+00, -1.000000e+00, %SGPR26_SGPR27, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR15, %EXEC<imp-use>
>	%VGPR16<def> = V_MOV_B32_e32 %SGPR20<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_ADD_F32_e64 %VGPR3, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18<imp-def>
>	%VGPR18<def> = V_ADD_F32_e64 %VGPR4, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18<imp-use,kill>, %VGPR17_VGPR18<imp-def>
>	%VGPR19<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR17_VGPR18, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR19<def> = V_ADD_F32_e64 %VGPR19<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR19<def> = V_MUL_F32_e32 %SGPR6, %VGPR19<kill>, %EXEC<imp-use>
>	%VGPR19<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR19<kill>, %EXEC<imp-use>
>	%VGPR20<def> = V_SUBREV_F32_e32 %VGPR2, %VGPR19, %EXEC<imp-use>
>	%VGPR20<def> = V_ADD_F32_e64 %VGPR20<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR21<def> = V_SUB_F32_e64 %VGPR3, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22<imp-def>
>	%VGPR22<def> = V_MOV_B32_e32 %VGPR18, %EXEC<imp-use>, %VGPR21_VGPR22<imp-def>
>	%VGPR16<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR21_VGPR22, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR16<def> = V_ADD_F32_e64 %VGPR16<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR16<def> = V_MUL_F32_e32 %SGPR6, %VGPR16<kill>, %EXEC<imp-use>
>	%VGPR16<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR16<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_SUBREV_F32_e32 %VGPR2, %VGPR16, %EXEC<imp-use>
>	%VGPR23<def> = V_ADD_F32_e64 %VGPR23<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LT_F32_e64 %VGPR23<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR16<def> = V_CNDMASK_B32_e64 %VGPR19<kill>, %VGPR16<kill>, %SGPR20_SGPR21, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR19<def> = V_SUBREV_F32_e32 %VGPR2, %VGPR16, %EXEC<imp-use>
>	%VGPR20<def> = V_CNDMASK_B32_e64 1.000000e+00, -1.000000e+00, %SGPR20_SGPR21, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR19<def> = V_MUL_F32_e32 %VGPR19<kill>, %VGPR20, %EXEC<imp-use>
>	%VGPR23<def> = V_MUL_F32_e32 %VGPR11, %VGPR19, %EXEC<imp-use>
>	%VGPR9<def> = V_SUBREV_F32_e32 %VGPR2, %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR15, %EXEC<imp-use>
>	%VGPR21<def> = V_CNDMASK_B32_e64 %VGPR17, %VGPR21, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22<imp-use,kill>
>	%VGPR21<def> = V_ADD_F32_e32 %VGPR21<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR21<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR21<kill>, %EXEC<imp-use>
>	%VGPR21<def> = V_ADD_F32_e32 %SGPR92, %VGPR21<kill>, %EXEC<imp-use>
>	%VGPR16<def> = V_ADD_F32_e64 %VGPR16<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR21<def> = V_MUL_F32_e32 %VGPR16, %VGPR21<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR21<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %VGPR12<kill>, %VGPR13, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR20, %EXEC<imp-use>
>	%VGPR21<def> = V_MUL_F32_e32 %VGPR9, %VGPR12, %EXEC<imp-use>
>	%VGPR21<def> = V_SUB_F32_e32 %VGPR21<kill>, %VGPR23<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_MAD_F32 %VGPR18, -2.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18<imp-use,kill>
>	%VGPR17<def> = V_ADD_F32_e32 %SGPR90, %VGPR17<kill>, %EXEC<imp-use>
>	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR17<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_RCP_F32_e32 %SGPR91, %EXEC<imp-use>
>	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR17, %EXEC<imp-use>
>	%VGPR18<def> = V_MAD_F32 %VGPR4, -2.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR18<def> = V_ADD_F32_e32 %SGPR90, %VGPR18<kill>, %EXEC<imp-use>
>	%VGPR18<def> = V_MUL_F32_e32 %VGPR14, %VGPR18<kill>, %EXEC<imp-use>
>	%VGPR18<def> = V_MUL_F32_e32 %VGPR18<kill>, %VGPR17, %EXEC<imp-use>
>	%VGPR16<def> = V_SUB_F32_e32 %VGPR16<kill>, %VGPR18, %EXEC<imp-use>
>	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR20<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR16, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR8, %VGPR6<kill>, %SGPR26_SGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>
>	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, -2.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_ADD_F32_e32 %SGPR90, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR17<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_SUB_F32_e32 %VGPR6<kill>, %VGPR18, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR15<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR6, %VGPR19<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_SUB_F32_e32 %VGPR7<kill>, %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR7, %VGPR7, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR21, %VGPR21, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR16<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_SUB_F32_e32 %VGPR9<kill>, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR6, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_RSQ_LEGACY_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e32 %VGPR21<kill>, %VGPR8, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR7<kill>, %VGPR8, %EXEC<imp-use>
>	%VGPR10<def> = V_MOV_B32_e32 2.500000e-01, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %SGPR88<kill>, %VGPR10, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR4, %VGPR11<kill>, %EXEC<imp-use>, %VGPR11_VGPR12<imp-def>
>	%VGPR10<def> = V_MUL_F32_e32 %SGPR89<kill>, %VGPR10<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %VGPR3, %VGPR10<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR11_VGPR12<imp-use,kill>, %VGPR11_VGPR12<imp-def>
>	%VGPR10_VGPR11_VGPR12<def> = IMAGE_SAMPLE_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR11_VGPR12<kill>, %SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39<kill>, %SGPR28_SGPR29_SGPR30_SGPR31<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR3<def> = V_ADD_F32_e32 %VGPR11, %VGPR11, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %SGPR94, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR10, %VGPR10, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e32 %SGPR94, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR15<def> = V_MUL_F32_e32 %SGPR66, %VGPR4, %EXEC<imp-use>
>	%VGPR15<def> = V_MAD_F32 %VGPR3, %SGPR65, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_ADD_F32_e32 %VGPR12, %VGPR12, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12<imp-use,kill>
>	%VGPR10<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR10<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_MUL_F32_e32 %SGPR94<kill>, %VGPR10<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_MAD_F32 %VGPR10, %SGPR64, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR11, %VGPR4, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR11, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %SGPR66<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR15<def> = V_SUBREV_F32_e32 %SGPR87<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR15<def> = V_MUL_F32_e32 %SGPR84<kill>, %VGPR15<kill>, %EXEC<imp-use>
>	%VGPR15<def> = V_ADD_F32_e64 %VGPR15<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_MAD_F32 %SGPR85<kill>, %VGPR15<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR14<def> = V_MUL_F32_e32 %SGPR86<kill>, %VGPR14<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_ADD_F32_e64 %VGPR14<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR14<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LT_F32_e64 %VGPR1, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR14<kill>, %VGPR5<kill>, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e32 %SGPR82<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_MUL_F32_e32 %SGPR96, %VGPR5, %EXEC<imp-use>
>	%VGPR15<def> = V_MUL_F32_e32 %SGPR24, %VGPR5, %EXEC<imp-use>
>	%VGPR16<def> = V_SUB_F32_e32 %VGPR15, %VGPR14, %EXEC<imp-use>
>	%VGPR17<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR17, %EXEC<imp-use>
>	%VGPR19<def> = V_MUL_F32_e32 %VGPR12, %VGPR7, %EXEC<imp-use>
>	%VGPR20<def> = V_MUL_F32_e32 %VGPR11, %VGPR3, %EXEC<imp-use>
>	%VGPR20<def> = V_MAD_F32 %VGPR11, %VGPR3, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR20<def> = V_SUB_F32_e32 %SGPR65<kill>, %VGPR20<kill>, %EXEC<imp-use>
>	%VGPR20<def> = V_MUL_F32_e32 %VGPR20<kill>, %VGPR17, %EXEC<imp-use>
>	%VGPR19<def> = V_MAD_F32 %VGPR20, %VGPR9, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR11, %VGPR10, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR11<kill>, %VGPR10, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_SUB_F32_e32 %SGPR64<kill>, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR17, %EXEC<imp-use>
>	%VGPR11<def> = V_MAD_F32 %VGPR8, %VGPR6, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR11<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_CVT_F32_I32_e32 %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR19<def> = V_MUL_F32_e32 %VGPR2, %VGPR9, %EXEC<imp-use>
>	%VGPR19<def> = V_MUL_F32_e32 %SGPR95, %VGPR19<kill>, %EXEC<imp-use>
>	%VGPR18<def> = V_SUB_F32_e32 %VGPR18<kill>, %VGPR19<kill>, %EXEC<imp-use>
>	%VGPR19<def> = V_MAD_F32 %VGPR20<kill>, %VGPR11, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR20<def> = V_MUL_F32_e32 %VGPR2, %VGPR6, %EXEC<imp-use>
>	%VGPR20<def> = V_MUL_F32_e32 %SGPR95, %VGPR20<kill>, %EXEC<imp-use>
>	%VGPR20<def> = V_SUB_F32_e32 %VGPR2, %VGPR20<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR8<kill>, %VGPR11, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR21<def> = V_ADD_F32_e64 %VGPR8, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR21<def> = V_RCP_F32_e32 %VGPR21<kill>, %EXEC<imp-use>
>	%VGPR19<def> = V_MUL_F32_e32 %VGPR19<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR19<def> = V_MUL_F32_e32 %SGPR91, %VGPR19<kill>, %EXEC<imp-use>
>	%VGPR19<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR19<kill>, %EXEC<imp-use>
>	%VGPR19<def> = V_MAD_F32 %VGPR19<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR23<def> = V_ADD_F32_e64 %VGPR19<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR22_VGPR23<imp-def>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR7, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %SGPR95<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_SUB_F32_e32 %VGPR13<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_MAD_F32 %VGPR12<kill>, %VGPR11<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR21<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %SGPR93, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR22_VGPR23<imp-use,kill>, %VGPR22_VGPR23<imp-def>
>	%VGPR11<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR22_VGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR12<def> = V_ADD_F32_e64 %VGPR11, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %SGPR6, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR12<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR12, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_CVT_F32_I32_e32 %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_SUB_F32_e32 %VGPR12<kill>, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_ADD_F32_e32 %VGPR17, %VGPR17, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_ADD_F32_e32 %VGPR12<kill>, %VGPR13<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR11<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_AND_B32_e32 1065353216, %VGPR11<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR1<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_AND_B32_e32 1065353216, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 1.000000e+00, %VGPR11, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR8<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_AND_B32_e32 1065353216, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %SGPR69, %VGPR4, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR3, %SGPR68, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR67, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_MUL_F32_e32 %VGPR12, %VGPR4, %EXEC<imp-use>
>	%VGPR13<def> = V_MAD_F32 %VGPR12, %VGPR4, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_SUB_F32_e32 %SGPR69<kill>, %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR19<def> = V_MUL_F32_e32 0.000000e+00, %VGPR14, %EXEC<imp-use>
>	%VGPR19<def> = V_SUB_F32_e32 %VGPR15, %VGPR19<kill>, %EXEC<imp-use>
>	%VGPR21<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR22<def> = V_MUL_F32_e32 %VGPR13, %VGPR7, %EXEC<imp-use>
>	%VGPR23<def> = V_MUL_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>
>	%VGPR23<def> = V_MAD_F32 %VGPR12, %VGPR3, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR23<def> = V_SUB_F32_e32 %SGPR68<kill>, %VGPR23<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MUL_F32_e32 %VGPR23<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR23, %VGPR9, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_MUL_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %SGPR67<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR12, %VGPR6, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR22<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_CVT_F32_I32_e32 %VGPR22<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MAD_F32 %VGPR23<kill>, %VGPR22, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR22, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_ADD_F32_e64 %VGPR12, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR24<def> = V_RCP_F32_e32 %VGPR24<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MUL_F32_e32 %VGPR23<kill>, %VGPR24, %EXEC<imp-use>
>	%VGPR23<def> = V_MUL_F32_e32 %SGPR91, %VGPR23<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR23<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MAD_F32 %VGPR23<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_ADD_F32_e64 %VGPR23<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26<imp-def>
>	%VGPR13<def> = V_MAD_F32 %VGPR13<kill>, %VGPR22<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR24<kill>, %EXEC<imp-use>
>	%VGPR13<def> = V_MUL_F32_e32 %SGPR93, %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR13<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR13<def> = V_MAD_F32 %VGPR13<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR25<def> = V_ADD_F32_e64 %VGPR13<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26<imp-use,kill>, %VGPR25_VGPR26<imp-def>
>	%VGPR13<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR22<def> = V_ADD_F32_e64 %VGPR13, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_MUL_F32_e32 %SGPR6, %VGPR22<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR22<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR22, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR23<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR23<def> = V_CVT_F32_I32_e32 %VGPR23<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %VGPR22<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_ADD_F32_e32 %VGPR21, %VGPR21, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_AND_B32_e32 1065353216, %VGPR22<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_ADD_F32_e32 %VGPR22<kill>, %VGPR23<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR13<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_AND_B32_e32 1065353216, %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR13<def> = V_MAD_F32 %VGPR13<kill>, %VGPR1, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_ADD_F32_e64 %VGPR13<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_SUB_F32_e32 1.000000e+00, %VGPR13, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR12<kill>, %VGPR22<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %SGPR63, %VGPR4, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR3, %SGPR62, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR61, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_MUL_F32_e32 %VGPR12, %VGPR4, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR12, %VGPR4, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_SUB_F32_e32 %SGPR63<kill>, %VGPR22<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MAD_F32 %SGPR96<kill>, %VGPR5, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR23<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_MUL_F32_e32 %VGPR22<kill>, %VGPR23, %EXEC<imp-use>
>	%VGPR24<def> = V_MUL_F32_e32 %VGPR22, %VGPR7, %EXEC<imp-use>
>	%VGPR25<def> = V_MUL_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>
>	%VGPR25<def> = V_MAD_F32 %VGPR12, %VGPR3, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR25<def> = V_SUB_F32_e32 %SGPR62<kill>, %VGPR25<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR23, %EXEC<imp-use>
>	%VGPR24<def> = V_MAD_F32 %VGPR25, %VGPR9, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %SGPR61<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR23, %EXEC<imp-use>
>	%VGPR24<def> = V_MAD_F32 %VGPR12, %VGPR6, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR24<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_CVT_F32_I32_e32 %VGPR24<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MAD_F32 %VGPR25<kill>, %VGPR24, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR24, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_ADD_F32_e64 %VGPR12, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR26<def> = V_RCP_F32_e32 %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR26, %EXEC<imp-use>
>	%VGPR25<def> = V_MUL_F32_e32 %SGPR91, %VGPR25<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR25<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MAD_F32 %VGPR25<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_ADD_F32_e64 %VGPR25<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR27_VGPR28<imp-def>
>	%VGPR22<def> = V_MAD_F32 %VGPR22<kill>, %VGPR24<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_MUL_F32_e32 %VGPR22<kill>, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MUL_F32_e32 %SGPR93, %VGPR22<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR22<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR22<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_ADD_F32_e64 %VGPR22<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR27_VGPR28<imp-use,kill>, %VGPR27_VGPR28<imp-def>
>	%VGPR22<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR24<def> = V_ADD_F32_e64 %VGPR22, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_MUL_F32_e32 %SGPR6, %VGPR24<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR24<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR24, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR25<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR25<def> = V_CVT_F32_I32_e32 %VGPR25<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %VGPR24<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_ADD_F32_e32 %VGPR23, %VGPR23, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_AND_B32_e32 1065353216, %VGPR24<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_ADD_F32_e32 %VGPR24<kill>, %VGPR25<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR22<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_AND_B32_e32 1065353216, %VGPR22<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR22<kill>, %VGPR1, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_ADD_F32_e64 %VGPR22<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_SUB_F32_e32 1.000000e+00, %VGPR22, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR12<kill>, %VGPR24<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %SGPR60, %VGPR4, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR3, %SGPR59, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR58, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_MUL_F32_e32 %VGPR12, %VGPR4, %EXEC<imp-use>
>	%VGPR24<def> = V_MAD_F32 %VGPR12, %VGPR4, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_SUB_F32_e32 %SGPR60<kill>, %VGPR24<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MUL_F32_e32 -3.000000e+00, %VGPR14, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %SGPR24<kill>, %VGPR5<kill>, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR25<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR25, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %VGPR24, %VGPR7, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR12, %VGPR3, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %SGPR59<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR25, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR27, %VGPR9, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %SGPR58<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR25, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR12, %VGPR6, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR26<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_CVT_F32_I32_e32 %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR26, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR26, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_ADD_F32_e64 %VGPR12, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR28<def> = V_RCP_F32_e32 %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR28, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR91, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_ADD_F32_e64 %VGPR27<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR29_VGPR30<imp-def>
>	%VGPR24<def> = V_MAD_F32 %VGPR24<kill>, %VGPR26<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_MUL_F32_e32 %SGPR93, %VGPR24<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR24<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_MAD_F32 %VGPR24<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_ADD_F32_e64 %VGPR24<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR29_VGPR30<imp-use,kill>, %VGPR29_VGPR30<imp-def>
>	%VGPR24<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR29_VGPR30<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR26<def> = V_ADD_F32_e64 %VGPR24, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %SGPR6, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR26<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR26, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CVT_F32_I32_e32 %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %VGPR26<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_ADD_F32_e32 %VGPR25, %VGPR25, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_ADD_F32_e32 %VGPR26<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR24<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_AND_B32_e32 1065353216, %VGPR24<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_MAD_F32 %VGPR24<kill>, %VGPR1, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_ADD_F32_e64 %VGPR24<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_SUB_F32_e32 1.000000e+00, %VGPR24, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR12<kill>, %VGPR26<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %SGPR78, %VGPR4, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR3, %SGPR77, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR76, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %VGPR12, %VGPR4, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR12, %VGPR4, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_SUB_F32_e32 %SGPR78<kill>, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR16, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR26, %VGPR7, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR12, %VGPR3, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_SUB_F32_e32 %SGPR77<kill>, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR16, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR28, %VGPR9, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %SGPR76<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR16, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR12, %VGPR6, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CVT_F32_I32_e32 %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, %VGPR27, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR27, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_ADD_F32_e64 %VGPR12, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR29<def> = V_RCP_F32_e32 %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR29, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %SGPR91, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_ADD_F32_e64 %VGPR28<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
>	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR27<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %SGPR93, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_ADD_F32_e64 %VGPR26<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR30_VGPR31<imp-def>
>	%VGPR26<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR30_VGPR31<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR27<def> = V_ADD_F32_e64 %VGPR26, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR6, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR27<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR27, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_CVT_F32_I32_e32 %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %VGPR27<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR16<def> = V_ADD_F32_e32 %VGPR16<kill>, %VGPR16, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR16<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR16<def> = V_AND_B32_e32 1065353216, %VGPR16<kill>, %EXEC<imp-use>
>	%VGPR16<def> = V_ADD_F32_e32 %VGPR16<kill>, %VGPR28<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR26<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR16<def> = V_MAD_F32 %VGPR26<kill>, %VGPR1, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR16<def> = V_ADD_F32_e64 %VGPR16<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_SUB_F32_e32 1.000000e+00, %VGPR16, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %SGPR81, %VGPR4, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR3, %SGPR80, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR10, %SGPR79, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR26, %VGPR4, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR26, %VGPR4, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %SGPR81<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR19, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR27, %VGPR7, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR26, %VGPR3, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR26, %VGPR3, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_SUB_F32_e32 %SGPR80<kill>, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR19, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR29, %VGPR9, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %VGPR26, %VGPR10, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR10, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_SUB_F32_e32 %SGPR79<kill>, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR19, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR26, %VGPR6, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR28<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_CVT_F32_I32_e32 %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, %VGPR28, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR28, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_ADD_F32_e64 %VGPR26, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR30<def> = V_RCP_F32_e32 %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR30, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %SGPR91, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_ADD_F32_e64 %VGPR29<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR28<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR93, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_ADD_F32_e64 %VGPR27<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR31_VGPR32<imp-def>
>	%VGPR27<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR31_VGPR32<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR28<def> = V_ADD_F32_e64 %VGPR27, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %SGPR6, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR28<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR28, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_CVT_F32_I32_e32 %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_SUB_F32_e32 %VGPR28<kill>, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR19<def> = V_ADD_F32_e32 %VGPR19<kill>, %VGPR19, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR26, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR19<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR19<def> = V_AND_B32_e32 1065353216, %VGPR19<kill>, %EXEC<imp-use>
>	%VGPR19<def> = V_ADD_F32_e32 %VGPR19<kill>, %VGPR29<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR19<def> = V_MAD_F32 %VGPR27<kill>, %VGPR1, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR19<def> = V_ADD_F32_e64 %VGPR19<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 1.000000e+00, %VGPR19, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR26<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR26<kill>, %VGPR27<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %SGPR75, %VGPR4, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR3, %SGPR74, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR10, %SGPR73, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR26, %VGPR4, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR26, %VGPR4, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %SGPR75<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR15, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR27, %VGPR7, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR26, %VGPR3, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR26, %VGPR3, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_SUB_F32_e32 %SGPR74<kill>, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR15, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR29, %VGPR9, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %VGPR26, %VGPR10, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR10, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_SUB_F32_e32 %SGPR73<kill>, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR15, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR26, %VGPR6, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR28<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_CVT_F32_I32_e32 %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, %VGPR28, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR28, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_ADD_F32_e64 %VGPR26, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR30<def> = V_RCP_F32_e32 %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR30, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %SGPR91, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_ADD_F32_e64 %VGPR29<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR28<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR93, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_ADD_F32_e64 %VGPR27<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR31_VGPR32<imp-def>
>	%VGPR27<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR31_VGPR32<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR28<def> = V_ADD_F32_e64 %VGPR27, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %SGPR6, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR28<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR28, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_CVT_F32_I32_e32 %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_SUB_F32_e32 %VGPR28<kill>, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR15<def> = V_ADD_F32_e32 %VGPR15<kill>, %VGPR15, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR26, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_AND_B32_e32 1065353216, %VGPR15<kill>, %EXEC<imp-use>
>	%VGPR15<def> = V_ADD_F32_e32 %VGPR15<kill>, %VGPR29<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR15<def> = V_MAD_F32 %VGPR27<kill>, %VGPR1, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_ADD_F32_e64 %VGPR15<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 1.000000e+00, %VGPR15, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR26<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR26<kill>, %VGPR27<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %SGPR72, %VGPR4, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR3, %SGPR71, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR10, %SGPR70, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR26, %VGPR4, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR26, %VGPR4, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %SGPR72<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR5, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR27, %VGPR7, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR26, %VGPR3, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR26, %VGPR3, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_SUB_F32_e32 %SGPR71<kill>, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR5, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR29, %VGPR9, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %VGPR26, %VGPR10, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR10, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_SUB_F32_e32 %SGPR70<kill>, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR5, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR26, %VGPR6, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR28<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_CVT_F32_I32_e32 %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, %VGPR28, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR28, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_ADD_F32_e64 %VGPR26, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR30<def> = V_RCP_F32_e32 %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR30, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %SGPR91, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_ADD_F32_e64 %VGPR29<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR28<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR93, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_ADD_F32_e64 %VGPR27<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR31_VGPR32<imp-def>
>	%VGPR27<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR31_VGPR32<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR28<def> = V_ADD_F32_e64 %VGPR27, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %SGPR6, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR28<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR28, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_CVT_F32_I32_e32 %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_SUB_F32_e32 %VGPR28<kill>, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_ADD_F32_e32 %VGPR5<kill>, %VGPR5, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR26, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_AND_B32_e32 1065353216, %VGPR5<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_ADD_F32_e32 %VGPR5<kill>, %VGPR29<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR27<kill>, %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_ADD_F32_e64 %VGPR5<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 1.000000e+00, %VGPR5, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR26<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR26<kill>, %VGPR27<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_ADD_F32_e32 %VGPR12<kill>, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %SGPR54, %VGPR4, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR3, %SGPR53, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR52, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %VGPR12, %VGPR4, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR12, %VGPR4, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_SUB_F32_e32 %SGPR54<kill>, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR17, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR26, %VGPR7, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR12, %VGPR3, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_SUB_F32_e32 %SGPR53<kill>, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR17, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR28, %VGPR9, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %SGPR52<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR17, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR12, %VGPR6, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CVT_F32_I32_e32 %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, %VGPR27, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR27, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_ADD_F32_e64 %VGPR12, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR29<def> = V_RCP_F32_e32 %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR29, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %SGPR91, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_ADD_F32_e64 %VGPR28<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
>	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR27<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %SGPR93, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_ADD_F32_e64 %VGPR26<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR30_VGPR31<imp-def>
>	%VGPR26<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR30_VGPR31<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR27<def> = V_ADD_F32_e64 %VGPR26, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR6, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR27<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR27, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_CVT_F32_I32_e32 %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %VGPR27<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_ADD_F32_e32 %VGPR17, %VGPR17, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_ADD_F32_e32 %VGPR27<kill>, %VGPR28<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR26<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR1, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_ADD_F32_e64 %VGPR26<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 1.000000e+00, %VGPR26, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR57, %VGPR4, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR3, %SGPR56, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR10, %SGPR55, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR27, %VGPR4, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR27, %VGPR4, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_SUB_F32_e32 %SGPR57<kill>, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR21<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR28, %VGPR7, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %VGPR27, %VGPR3, %EXEC<imp-use>
>	%VGPR30<def> = V_MAD_F32 %VGPR27, %VGPR3, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_SUB_F32_e32 %SGPR56<kill>, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR30, %VGPR9, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR27, %VGPR10, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR10, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %SGPR55<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR27, %VGPR6, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR29<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_CVT_F32_I32_e32 %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_MAD_F32 %VGPR30<kill>, %VGPR29, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR29, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_ADD_F32_e64 %VGPR27, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR31<def> = V_RCP_F32_e32 %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR31, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %SGPR91, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_MAD_F32 %VGPR30<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_ADD_F32_e64 %VGPR30<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR32_VGPR33<imp-def>
>	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, %VGPR29<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %SGPR93, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_ADD_F32_e64 %VGPR28<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
>	%VGPR28<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR32_VGPR33<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR29<def> = V_ADD_F32_e64 %VGPR28, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %SGPR6, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR29<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR29, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_CVT_F32_I32_e32 %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %VGPR29<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_ADD_F32_e32 %VGPR21, %VGPR21, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR27, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_AND_B32_e32 1065353216, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_ADD_F32_e32 %VGPR29<kill>, %VGPR30<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR28<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_AND_B32_e32 1065353216, %VGPR28<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, %VGPR1, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR28<def> = V_ADD_F32_e64 %VGPR28<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_SUB_F32_e32 1.000000e+00, %VGPR28, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR27<kill>, %VGPR29<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR51, %VGPR4, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR3, %SGPR50, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR10, %SGPR49, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR27, %VGPR4, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR27, %VGPR4, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_SUB_F32_e32 %SGPR51<kill>, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR23, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %VGPR29, %VGPR7, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR27, %VGPR3, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR27, %VGPR3, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_SUB_F32_e32 %SGPR50<kill>, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR23, %EXEC<imp-use>
>	%VGPR30<def> = V_MAD_F32 %VGPR31, %VGPR9, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %VGPR27, %VGPR10, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR10, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %SGPR49<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR23, %EXEC<imp-use>
>	%VGPR30<def> = V_MAD_F32 %VGPR27, %VGPR6, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR30<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_CVT_F32_I32_e32 %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR31<kill>, %VGPR30, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR30, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_ADD_F32_e64 %VGPR27, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR32<def> = V_RCP_F32_e32 %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR32, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %SGPR91, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR31<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR34<def> = V_ADD_F32_e64 %VGPR31<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR33_VGPR34<imp-def>
>	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, %VGPR30<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %SGPR93, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_ADD_F32_e64 %VGPR29<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
>	%VGPR29<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR33_VGPR34<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR30<def> = V_ADD_F32_e64 %VGPR29, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %SGPR6, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR30<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR30, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_CVT_F32_I32_e32 %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %VGPR30<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR23, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR27, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_AND_B32_e32 1065353216, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_ADD_F32_e32 %VGPR30<kill>, %VGPR31<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR29<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_AND_B32_e32 1065353216, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, %VGPR1, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_ADD_F32_e64 %VGPR29<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_SUB_F32_e32 1.000000e+00, %VGPR29, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR27<kill>, %VGPR30<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR48, %VGPR4, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR3, %SGPR47, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR10, %SGPR46, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %VGPR27, %VGPR4, %EXEC<imp-use>
>	%VGPR30<def> = V_MAD_F32 %VGPR27, %VGPR4, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_SUB_F32_e32 %SGPR48<kill>, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR25, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR30, %VGPR7, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %VGPR27, %VGPR3, %EXEC<imp-use>
>	%VGPR32<def> = V_MAD_F32 %VGPR27, %VGPR3, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_SUB_F32_e32 %SGPR47<kill>, %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR25, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR32, %VGPR9, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_MUL_F32_e32 %VGPR27, %VGPR10, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR10, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %SGPR46<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR25, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR27, %VGPR6, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR31<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_CVT_F32_I32_e32 %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_MAD_F32 %VGPR32<kill>, %VGPR31, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR31, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_ADD_F32_e64 %VGPR27, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR33<def> = V_RCP_F32_e32 %VGPR33<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR33, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %SGPR91, %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_MAD_F32 %VGPR32<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR35<def> = V_ADD_F32_e64 %VGPR32<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR34_VGPR35<imp-def>
>	%VGPR30<def> = V_MAD_F32 %VGPR30<kill>, %VGPR31<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR33<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %SGPR93, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_MAD_F32 %VGPR30<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR34<def> = V_ADD_F32_e64 %VGPR30<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR34_VGPR35<imp-use,kill>, %VGPR34_VGPR35<imp-def>
>	%VGPR30<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR34_VGPR35<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR31<def> = V_ADD_F32_e64 %VGPR30, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %SGPR6, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR31<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR31, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_CVT_F32_I32_e32 %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_ADD_F32_e32 %VGPR25, %VGPR25, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR27, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_AND_B32_e32 1065353216, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_ADD_F32_e32 %VGPR31<kill>, %VGPR32<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR30<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_AND_B32_e32 1065353216, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR30<def> = V_MAD_F32 %VGPR30<kill>, %VGPR1, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_ADD_F32_e64 %VGPR30<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_SUB_F32_e32 1.000000e+00, %VGPR30, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR27<kill>, %VGPR31<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_ADD_F32_e32 %VGPR8<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %SGPR42, %VGPR4, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR3, %SGPR41, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR40, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR12, %VGPR4, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR12, %VGPR4, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %SGPR42<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR17, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR27, %VGPR7, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>
>	%VGPR32<def> = V_MAD_F32 %VGPR12, %VGPR3, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_SUB_F32_e32 %SGPR41<kill>, %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR17, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR32, %VGPR9, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_MUL_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %SGPR40<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR17, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR12, %VGPR6, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR31<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_CVT_F32_I32_e32 %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_MAD_F32 %VGPR32<kill>, %VGPR31, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR31, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_ADD_F32_e64 %VGPR12, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR33<def> = V_RCP_F32_e32 %VGPR33<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR33, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %SGPR91, %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_MAD_F32 %VGPR32<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR35<def> = V_ADD_F32_e64 %VGPR32<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR34_VGPR35<imp-def>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR31<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR33<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR93, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR34<def> = V_ADD_F32_e64 %VGPR27<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR34_VGPR35<imp-use,kill>, %VGPR34_VGPR35<imp-def>
>	%VGPR27<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR34_VGPR35<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR31<def> = V_ADD_F32_e64 %VGPR27, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %SGPR6, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR31<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR31, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_CVT_F32_I32_e32 %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_ADD_F32_e32 %VGPR17<kill>, %VGPR17, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_AND_B32_e32 1065353216, %VGPR17<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_ADD_F32_e32 %VGPR17<kill>, %VGPR32<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_MAD_F32 %VGPR27<kill>, %VGPR1, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_ADD_F32_e64 %VGPR17<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 1.000000e+00, %VGPR17, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR45, %VGPR4, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR3, %SGPR44, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR10, %SGPR43, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR27, %VGPR4, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR27, %VGPR4, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_SUB_F32_e32 %SGPR45<kill>, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR21<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %VGPR31, %VGPR7, %EXEC<imp-use>
>	%VGPR33<def> = V_MUL_F32_e32 %VGPR27, %VGPR3, %EXEC<imp-use>
>	%VGPR33<def> = V_MAD_F32 %VGPR27, %VGPR3, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_SUB_F32_e32 %SGPR44<kill>, %VGPR33<kill>, %EXEC<imp-use>
>	%VGPR33<def> = V_MUL_F32_e32 %VGPR33<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR32<def> = V_MAD_F32 %VGPR33, %VGPR9, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR34<def> = V_MUL_F32_e32 %VGPR27, %VGPR10, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR10, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %SGPR43<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR32<def> = V_MAD_F32 %VGPR27, %VGPR6, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR32<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_CVT_F32_I32_e32 %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR33<def> = V_MAD_F32 %VGPR33<kill>, %VGPR32, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR32, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR34<def> = V_ADD_F32_e64 %VGPR27, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR34<def> = V_RCP_F32_e32 %VGPR34<kill>, %EXEC<imp-use>
>	%VGPR33<def> = V_MUL_F32_e32 %VGPR33<kill>, %VGPR34, %EXEC<imp-use>
>	%VGPR33<def> = V_MUL_F32_e32 %SGPR91, %VGPR33<kill>, %EXEC<imp-use>
>	%VGPR33<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR33<kill>, %EXEC<imp-use>
>	%VGPR33<def> = V_MAD_F32 %VGPR33<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR36<def> = V_ADD_F32_e64 %VGPR33<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR35_VGPR36<imp-def>
>	%VGPR31<def> = V_MAD_F32 %VGPR31<kill>, %VGPR32<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR34<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %SGPR93, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR31<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR35<def> = V_ADD_F32_e64 %VGPR31<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR35_VGPR36<imp-use,kill>, %VGPR35_VGPR36<imp-def>
>	%VGPR31<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR35_VGPR36<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR32<def> = V_ADD_F32_e64 %VGPR31, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %SGPR6, %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR32<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR32, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_CVT_F32_I32_e32 %VGPR33<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %VGPR32<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR21<def> = V_ADD_F32_e32 %VGPR21<kill>, %VGPR21, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR27, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR21<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR21<def> = V_AND_B32_e32 1065353216, %VGPR21<kill>, %EXEC<imp-use>
>	%VGPR21<def> = V_ADD_F32_e32 %VGPR21<kill>, %VGPR33<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR31<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_AND_B32_e32 1065353216, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR21<def> = V_MAD_F32 %VGPR31<kill>, %VGPR1, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR21<def> = V_ADD_F32_e64 %VGPR21<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_SUB_F32_e32 1.000000e+00, %VGPR21, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR27<kill>, %VGPR31<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR23, %VGPR4, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR3, %SGPR22, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR10, %SGPR5, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR27, %VGPR4, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR27, %VGPR4, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_SUB_F32_e32 %SGPR23<kill>, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR23, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %VGPR31, %VGPR7, %EXEC<imp-use>
>	%VGPR33<def> = V_MUL_F32_e32 %VGPR27, %VGPR3, %EXEC<imp-use>
>	%VGPR33<def> = V_MAD_F32 %VGPR27, %VGPR3, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_SUB_F32_e32 %SGPR22<kill>, %VGPR33<kill>, %EXEC<imp-use>
>	%VGPR33<def> = V_MUL_F32_e32 %VGPR33<kill>, %VGPR23, %EXEC<imp-use>
>	%VGPR32<def> = V_MAD_F32 %VGPR33, %VGPR9, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR34<def> = V_MUL_F32_e32 %VGPR27, %VGPR10, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR10, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %SGPR5<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR23, %EXEC<imp-use>
>	%VGPR32<def> = V_MAD_F32 %VGPR27, %VGPR6, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR32<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_CVT_F32_I32_e32 %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR33<def> = V_MAD_F32 %VGPR33<kill>, %VGPR32, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR32, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR34<def> = V_ADD_F32_e64 %VGPR27, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR34<def> = V_RCP_F32_e32 %VGPR34<kill>, %EXEC<imp-use>
>	%VGPR33<def> = V_MUL_F32_e32 %VGPR33<kill>, %VGPR34, %EXEC<imp-use>
>	%VGPR33<def> = V_MUL_F32_e32 %SGPR91, %VGPR33<kill>, %EXEC<imp-use>
>	%VGPR33<def> = V_SUBREV_F32_e32 %SGPR90, %VGPR33<kill>, %EXEC<imp-use>
>	%VGPR33<def> = V_MAD_F32 %VGPR33<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR36<def> = V_ADD_F32_e64 %VGPR33<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR35_VGPR36<imp-def>
>	%VGPR31<def> = V_MAD_F32 %VGPR31<kill>, %VGPR32<kill>, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR34<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %SGPR93, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_SUBREV_F32_e32 %SGPR92, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR31<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR35<def> = V_ADD_F32_e64 %VGPR31<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR35_VGPR36<imp-use,kill>, %VGPR35_VGPR36<imp-def>
>	%VGPR31<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR35_VGPR36<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR32<def> = V_ADD_F32_e64 %VGPR31, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %SGPR6, %VGPR32<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_SUBREV_F32_e32 %SGPR7, %VGPR32<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_EQ_F32_e64 %VGPR32, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_CVT_F32_I32_e32 %VGPR33<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_SUB_F32_e32 %VGPR32<kill>, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_ADD_F32_e32 %VGPR23<kill>, %VGPR23, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR27, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR23<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR23<def> = V_AND_B32_e32 1065353216, %VGPR23<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_ADD_F32_e32 %VGPR23<kill>, %VGPR33<kill>, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_LE_F32_e64 %VGPR31<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_AND_B32_e32 1065353216, %VGPR31<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MAD_F32 %VGPR31<kill>, %VGPR1, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR23<def> = V_ADD_F32_e64 %VGPR23<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_SUB_F32_e32 1.000000e+00, %VGPR23, %EXEC<imp-use>
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR27<kill>, %VGPR31<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %SGPR4, %VGPR4, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR3, %SGPR3, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR10, %SGPR2, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %VGPR27, %VGPR4, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR27, %VGPR4<kill>, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_MAD_F32 %VGPR14<kill>, -4.000000e+00, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR4, %VGPR7<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MUL_F32_e32 %VGPR27, %VGPR3, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR27, %VGPR3<kill>, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR3, %VGPR9<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e32 %VGPR27, %VGPR10, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR27<kill>, %VGPR10<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR9, %VGPR6<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_CVT_F32_I32_e32 %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %VGPR6, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR9<kill>, %VGPR6, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_ADD_F32_e64 %VGPR7, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR9<def> = V_RCP_F32_e32 %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR9, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %SGPR91<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR90<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR32<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
>	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR6<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %SGPR93<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_SUBREV_F32_e32 %SGPR92<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR31_VGPR32<imp-def>
>	%VGPR2<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR31_VGPR32<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR3<def> = V_ADD_F32_e64 %VGPR2, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR7<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR3, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_CVT_F32_I32_e32 %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR7<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_ADD_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_AND_B32_e32 1065353216, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR6<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_AND_B32_e32 1065353216, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_ADD_F32_e64 %VGPR1<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_SUB_F32_e32 1.000000e+00, %VGPR1, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR3<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_AND_B32_e32 1065353216, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MAD_F32 %VGPR3<kill>, %VGPR2<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_ADD_F32_e32 %VGPR8<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e32 %VGPR13<kill>, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR22<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR24<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR19<kill>, %VGPR16<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR15<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR28<kill>, %VGPR26<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR29<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR30<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR21<kill>, %VGPR17<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR23<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_SUB_F32_e32 1.600000e+01, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_RCP_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use,kill>
>    Successors according to CFG: BB#2
>
>BB#2: derived from LLVM BB %ENDIF
>    Live Ins: %VGPR0 %SGPR0_SGPR1 %VGPR5
>    Predecessors according to CFG: BB#0 BB#1
>	%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1
>	%VGPR0<def> = V_MUL_F32_e64 %VGPR5<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_SUB_F32_e32 1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 0.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c08c0100
>bf8c007f
>c2001911
>bf8c007f
>d2820002
>03c00102
>7e064102
>08040702
>060404f0
>c20a9913
>bf8c007f
>10080415
>c8080000
>c8090001
>c2001910
>bf8c007f
>d2820000
>03c00102
>7e024100
>08000300
>060000f0
>c20a1912
>bf8c007f
>10060014
>c0840300
>c0c60500
>bf8c007f
>f0800100
>00430103
>bf8c0770
>d2060100
>02010101
>c2031905
>bf8c007f
>10000006
>c2039904
>bf8c007f
>0a040007
>7e0002ff
>3f733333
>d0020000
>02020101
>c20b1919
>7e0a0280
>bf8c007f
>7e000216
>be802400
>8980007e
>bf8806d8
>c08e0304
>c0d00508
>c201195a
>c2019959
>c2021958
>c2029956
>c20b1955
>c20b9954
>c2141952
>c2149951
>c2151950
>c215994e
>c216194d
>c216994c
>c217194a
>c2179949
>c2181948
>c2189946
>c2191945
>c2199944
>c21a1942
>c21a9941
>c21b1940
>c21b993e
>c21c193d
>c21c993c
>c21d193a
>c21d9939
>c21e1938
>c21e9936
>c21f1935
>c21f9934
>c2201932
>c2209931
>c2211930
>c221992e
>c222192d
>c222992c
>c223192a
>c2239929
>c2241928
>c2249926
>c2251925
>c2259924
>c2261922
>c2269921
>c2271920
>c227991e
>c228191d
>c228991c
>c229191a
>c2299918
>c22a1917
>c22a9916
>c22b1915
>c22b9914
>c22c190d
>c22c990c
>c22d190b
>c22d990a
>c22e1909
>c22e9908
>c22f1903
>c22f9902
>c2301901
>c20c1900
>bf8c007f
>7e0a0253
>7e0c0215
>d2060008
>02020d04
>d2060007
>02010103
>f0800100
>00430907
>bf8c0770
>d2060109
>02010109
>10121206
>0a121207
>0a141302
>d206010a
>0201010a
>d2080006
>02020d04
>7e160307
>7e180308
>7e180306
>f0800100
>00430b0b
>bf8c0770
>d206010b
>0201010b
>10161606
>0a161607
>0a181702
>d206010c
>0201010c
>d002001a
>0202150c
>d2000009
>006a1709
>d206000a
>22010109
>06160f07
>061616f3
>0616165c
>1016170a
>7e18545d
>1016190b
>d206000d
>02020703
>061a1af3
>061a1a5c
>d206000e
>22010102
>101a1b0e
>101a190d
>08161b0b
>d200000f
>0069e6f2
>10161f0b
>7e200214
>d2060011
>02022103
>d2060012
>02010104
>f0800100
>00431311
>bf8c0770
>d2060113
>02010113
>10262606
>0a262607
>0a282702
>d2060114
>02010114
>d2080015
>02022103
>7e2c0312
>f0800100
>00431015
>bf8c0770
>d2060110
>02010110
>10202006
>0a202007
>0a2e2102
>d2060117
>02010117
>d0020014
>02022917
>d2000010
>00522113
>0a262102
>d2000014
>0051e6f2
>10262913
>102e270b
>0a121302
>10121f09
>d2000015
>00522b11
>062a2b15
>062a2af3
>062a2a5c
>d2060010
>22010110
>102a2b10
>10181915
>08181b0c
>1018290c
>102a1909
>082a2f15
>d2820011
>03c9eb12
>0622225a
>10202310
>7e22545b
>10202310
>d2820012
>03c9eb04
>0624245a
>1024250e
>10242312
>08202510
>10202910
>10122109
>d2000006
>006a0d08
>d2820006
>03c9eb06
>060c0c5a
>100c0d0a
>100c2306
>080c2506
>100c1f06
>100e2706
>080e1307
>10100f07
>d2820008
>04222b15
>1012210b
>100c1906
>080c0d09
>d2820008
>04220d06
>7e105b08
>10121115
>100e1107
>7e1402ff
>3e800000
>10161458
>10181704
>10141459
>10161503
>f0800700
>00e80a0b
>bf8c0770
>0606170b
>060606f3
>1006065e
>0608150a
>060808f3
>1008085e
>101e0842
>d282000f
>043c8303
>0614190c
>061414f3
>1014145e
>d282000b
>043c810a
>1018090b
>d282000c
>0432090b
>08181842
>0a1e1c57
>101e1e54
>d206080f
>0201010f
>d282000f
>03ca1e55
>101c1c56
>d206080e
>0201010e
>101c1d0f
>d0020014
>02010101
>d2000005
>00520b0e
>100a0a52
>101c0a60
>101e0a18
>08201d0f
>d2820011
>0441ef0e
>1018230c
>10260f0c
>1028070b
>d2820014
>0452070b
>08282841
>10282314
>d2820013
>044e1314
>100c1106
>1010150b
>d2820008
>0422150b
>08101040
>10102308
>d282000b
>044e0d08
>d00c0014
>0201010b
>d200000b
>005102c1
>7e160b0b
>10261302
>1026265f
>08242712
>d2820013
>044a1714
>10280d02
>1028285f
>08282902
>d2820008
>04521708
>d2060015
>22010108
>7e2a5515
>10262b13
>1026265b
>0a26265a
>d2820013
>03c1e313
>d2060817
>02010113
>10040f02
>1004045f
>0804050d
>d282000b
>040a170c
>10162b0b
>1016165d
>0a16165c
>d282000b
>03c1e10b
>d2060816
>0201010b
>f0800100
>00430b16
>bf8c0770
>d206010c
>0201010b
>10181806
>0a181807
>d0040014
>0201010c
>d200000d
>00510280
>7e1a0b0d
>0810110c
>06182311
>d00c0014
>02021908
>d200000c
>00518280
>361818f2
>06181b0c
>d0060014
>0201010b
>d200000b
>00518280
>361616f2
>d00c0014
>02010101
>d2000001
>00518280
>360202f2
>d282000b
>0432030b
>d206080b
>0201010b
>081816f2
>d00c0014
>02010108
>d2000008
>00518280
>361010f2
>10101908
>10180845
>d282000c
>04308903
>d282000c
>0430870a
>101a090c
>d282000d
>0436090c
>081a1a45
>10261c80
>0826270f
>d2820015
>044def0e
>101a2b0d
>102c0f0d
>102e070c
>d2820017
>045e070c
>082e2e44
>102e2b17
>d2820016
>045a1317
>1030150c
>d282000c
>0462150c
>08181843
>10182b0c
>d2820016
>045a0d0c
>d00c0014
>02010116
>d2000016
>005102c1
>7e2c0b16
>d2820017
>044a2d17
>d282000c
>04522d0c
>d2060018
>2201010c
>7e305518
>102e3117
>102e2e5b
>0a2e2e5a
>d2820017
>03c1e317
>d206081a
>02010117
>d282000d
>040a2d0d
>101a310d
>101a1a5d
>0a1a1a5c
>d282000d
>03c1e10d
>d2060819
>0201010d
>f0800100
>00430d19
>bf8c0770
>d2060116
>0201010d
>102c2c06
>0a2c2c07
>d0040014
>02010116
>d2000017
>00510280
>7e2e0b17
>08181916
>062c2b15
>d00c0014
>02022d0c
>d2000016
>00518280
>362c2cf2
>062c2f16
>d0060014
>0201010d
>d200000d
>00518280
>361a1af2
>d282000d
>045a030d
>d206080d
>0201010d
>082c1af2
>d00c0014
>0201010c
>d200000c
>00518280
>361818f2
>d2820008
>04222d0c
>1018083f
>d282000c
>04307d03
>d282000c
>04307b0a
>102c090c
>d2820016
>045a090c
>082c2c3f
>d2820017
>043a0a60
>081e2f0f
>d2820017
>043def0e
>102c2f16
>10300f16
>1032070c
>d2820019
>0466070c
>0832323e
>10322f19
>d2820018
>04621319
>1034150c
>d282000c
>046a150c
>0818183d
>10182f0c
>d2820018
>04620d0c
>d00c0014
>02010118
>d2000018
>005102c1
>7e300b18
>d2820019
>044a3119
>d282000c
>0452310c
>d206001a
>2201010c
>7e34551a
>10323519
>1032325b
>0a32325a
>d2820019
>03c1e319
>d206081c
>02010119
>d2820016
>040a3116
>102c3516
>102c2c5d
>0a2c2c5c
>d2820016
>03c1e116
>d206081b
>02010116
>f0800100
>0043161b
>bf8c0770
>d2060118
>02010116
>10303006
>0a303007
>d0040014
>02010118
>d2000019
>00510280
>7e320b19
>08181918
>06302f17
>d00c0014
>0202310c
>d2000018
>00518280
>363030f2
>06303318
>d0060014
>02010116
>d2000016
>00518280
>362c2cf2
>d2820016
>04620316
>d2060816
>02010116
>08302cf2
>d00c0014
>0201010c
>d200000c
>00518280
>361818f2
>d2820008
>0422310c
>1018083c
>d282000c
>04307703
>d282000c
>0430750a
>1030090c
>d2820018
>0462090c
>0830303c
>10321cff
>c0400000
>d2820005
>04660a18
>d2820019
>0415ef0e
>10303318
>10340f18
>1036070c
>d282001b
>046e070c
>0836363b
>1036331b
>d282001a
>046a131b
>1038150c
>d282000c
>0472150c
>0818183a
>1018330c
>d282001a
>046a0d0c
>d00c0014
>0201011a
>d200001a
>005102c1
>7e340b1a
>d282001b
>044a351b
>d282000c
>0452350c
>d206001c
>2201010c
>7e38551c
>1036391b
>1036365b
>0a36365a
>d282001b
>03c1e31b
>d206081e
>0201011b
>d2820018
>040a3518
>10303918
>1030305d
>0a30305c
>d2820018
>03c1e118
>d206081d
>02010118
>f0800100
>0043181d
>bf8c0770
>d206011a
>02010118
>10343406
>0a343407
>d0040014
>0201011a
>d200001b
>00510280
>7e360b1b
>0818191a
>06343319
>d00c0014
>0202350c
>d200001a
>00518280
>363434f2
>0634371a
>d0060014
>02010118
>d2000018
>00518280
>363030f2
>d2820018
>046a0318
>d2060818
>02010118
>083430f2
>d00c0014
>0201010c
>d200000c
>00518280
>361818f2
>d2820008
>0422350c
>1018084e
>d282000c
>04309b03
>d282000c
>0430990a
>1034090c
>d282001a
>046a090c
>0834344e
>1034211a
>10360f1a
>1038070c
>d282001c
>0472070c
>0838384d
>1038211c
>d282001b
>046e131c
>103a150c
>d282000c
>0476150c
>0818184c
>1018210c
>d282001b
>046e0d0c
>d00c0014
>0201011b
>d200001b
>005102c1
>7e360b1b
>d282001c
>044a371c
>d282000c
>0452370c
>d206001d
>2201010c
>7e3a551d
>10383b1c
>1038385b
>0a38385a
>d282001c
>03c1e31c
>d206081f
>0201011c
>d282001a
>040a371a
>10343b1a
>1034345d
>0a34345c
>d282001a
>03c1e11a
>d206081e
>0201011a
>f0800100
>00431a1e
>bf8c0770
>d206011b
>0201011a
>10363606
>0a363607
>d0040014
>0201011b
>d200001c
>00510280
>7e380b1c
>0818191b
>06202110
>d00c0014
>0202210c
>d2000010
>00518280
>362020f2
>06203910
>d0060014
>0201011a
>d200001a
>00518280
>363434f2
>d2820010
>0442031a
>d2060810
>02010110
>083420f2
>d00c0014
>0201010c
>d200000c
>00518280
>361818f2
>1018350c
>10340851
>d282001a
>0468a103
>d282001a
>04689f0a
>1036091a
>d282001b
>046e091a
>08363651
>1036271b
>10380f1b
>103a071a
>d282001d
>0476071a
>083a3a50
>103a271d
>d282001c
>0472131d
>103c151a
>d282001a
>047a151a
>0834344f
>1034271a
>d282001c
>04720d1a
>d00c0014
>0201011c
>d200001c
>005102c1
>7e380b1c
>d282001d
>044a391d
>d282001a
>0452391a
>d206001e
>2201011a
>7e3c551e
>103a3d1d
>103a3a5b
>0a3a3a5a
>d282001d
>03c1e31d
>d2060820
>0201011d
>d282001b
>040a391b
>10363d1b
>1036365d
>0a36365c
>d282001b
>03c1e11b
>d206081f
>0201011b
>f0800100
>00431b1f
>bf8c0770
>d206011c
>0201011b
>10383806
>0a383807
>d0040014
>0201011c
>d200001d
>00510280
>7e3a0b1d
>0834351c
>06262713
>d00c0014
>0202271a
>d2000013
>00518280
>362626f2
>06263b13
>d0060014
>0201011b
>d200001b
>00518280
>363636f2
>d2820013
>044e031b
>d2060813
>02010113
>083626f2
>d00c0014
>0201011a
>d200001a
>00518280
>363434f2
>d282000c
>0432371a
>1034084b
>d282001a
>04689503
>d282001a
>0468930a
>1036091a
>d282001b
>046e091a
>0836364b
>10361f1b
>10380f1b
>103a071a
>d282001d
>0476071a
>083a3a4a
>103a1f1d
>d282001c
>0472131d
>103c151a
>d282001a
>047a151a
>08343449
>10341f1a
>d282001c
>04720d1a
>d00c0014
>0201011c
>d200001c
>005102c1
>7e380b1c
>d282001d
>044a391d
>d282001a
>0452391a
>d206001e
>2201011a
>7e3c551e
>103a3d1d
>103a3a5b
>0a3a3a5a
>d282001d
>03c1e31d
>d2060820
>0201011d
>d282001b
>040a391b
>10363d1b
>1036365d
>0a36365c
>d282001b
>03c1e11b
>d206081f
>0201011b
>f0800100
>00431b1f
>bf8c0770
>d206011c
>0201011b
>10383806
>0a383807
>d0040014
>0201011c
>d200001d
>00510280
>7e3a0b1d
>0834351c
>061e1f0f
>d00c0014
>02021f1a
>d200000f
>00518280
>361e1ef2
>061e3b0f
>d0060014
>0201011b
>d200001b
>00518280
>363636f2
>d282000f
>043e031b
>d206080f
>0201010f
>08361ef2
>d00c0014
>0201011a
>d200001a
>00518280
>363434f2
>d282000c
>0432371a
>10340848
>d282001a
>04688f03
>d282001a
>04688d0a
>1036091a
>d282001b
>046e091a
>08363648
>10360b1b
>10380f1b
>103a071a
>d282001d
>0476071a
>083a3a47
>103a0b1d
>d282001c
>0472131d
>103c151a
>d282001a
>047a151a
>08343446
>10340b1a
>d282001c
>04720d1a
>d00c0014
>0201011c
>d200001c
>005102c1
>7e380b1c
>d282001d
>044a391d
>d282001a
>0452391a
>d206001e
>2201011a
>7e3c551e
>103a3d1d
>103a3a5b
>0a3a3a5a
>d282001d
>03c1e31d
>d2060820
>0201011d
>d282001b
>040a391b
>10363d1b
>1036365d
>0a36365c
>d282001b
>03c1e11b
>d206081f
>0201011b
>f0800100
>00431b1f
>bf8c0770
>d206011c
>0201011b
>10383806
>0a383807
>d0040014
>0201011c
>d200001d
>00510280
>7e3a0b1d
>0834351c
>060a0b05
>d00c0014
>02020b1a
>d2000005
>00518280
>360a0af2
>060a3b05
>d0060014
>0201011b
>d200001b
>00518280
>363636f2
>d2820005
>0416031b
>d2060805
>02010105
>08360af2
>d00c0014
>0201011a
>d200001a
>00518280
>363434f2
>d282000c
>0432371a
>0610110c
>10180836
>d282000c
>04306b03
>d282000c
>0430690a
>1034090c
>d282001a
>046a090c
>08343436
>d2820011
>0445ef0e
>1034231a
>10360f1a
>1038070c
>d282001c
>0472070c
>08383835
>1038231c
>d282001b
>046e131c
>103a150c
>d282000c
>0476150c
>08181834
>1018230c
>d282001b
>046e0d0c
>d00c0014
>0201011b
>d200001b
>005102c1
>7e360b1b
>d282001c
>044a371c
>d282000c
>0452370c
>d206001d
>2201010c
>7e3a551d
>10383b1c
>1038385b
>0a38385a
>d282001c
>03c1e31c
>d206081f
>0201011c
>d282001a
>040a371a
>10343b1a
>1034345d
>0a34345c
>d282001a
>03c1e11a
>d206081e
>0201011a
>f0800100
>00431a1e
>bf8c0770
>d206011b
>0201011a
>10363606
>0a363607
>d0040014
>0201011b
>d200001c
>00510280
>7e380b1c
>0818191b
>06362311
>d00c0014
>0202370c
>d200001b
>00518280
>363636f2
>0636391b
>d0060014
>0201011a
>d200001a
>00518280
>363434f2
>d282001a
>046e031a
>d206081a
>0201011a
>083634f2
>d00c0014
>0201010c
>d200000c
>00518280
>361818f2
>1018370c
>10360839
>d282001b
>046c7103
>d282001b
>046c6f0a
>1038091b
>d282001c
>0472091b
>08383839
>d2820015
>0455ef0e
>10382b1c
>103a0f1c
>103c071b
>d282001e
>047a071b
>083c3c38
>103c2b1e
>d282001d
>0476131e
>103e151b
>d282001b
>047e151b
>08363637
>10362b1b
>d282001d
>04760d1b
>d00c0014
>0201011d
>d200001d
>005102c1
>7e3a0b1d
>d282001e
>044a3b1e
>d282001b
>04523b1b
>d206001f
>2201011b
>7e3e551f
>103c3f1e
>103c3c5b
>0a3c3c5a
>d282001e
>03c1e31e
>d2060821
>0201011e
>d282001c
>040a3b1c
>10383f1c
>1038385d
>0a38385c
>d282001c
>03c1e11c
>d2060820
>0201011c
>f0800100
>00431c20
>bf8c0770
>d206011d
>0201011c
>103a3a06
>0a3a3a07
>d0040014
>0201011d
>d200001e
>00510280
>7e3c0b1e
>0836371d
>063a2b15
>d00c0014
>02023b1b
>d200001d
>00518280
>363a3af2
>063a3d1d
>d0060014
>0201011c
>d200001c
>00518280
>363838f2
>d282001c
>0476031c
>d206081c
>0201011c
>083a38f2
>d00c0014
>0201011b
>d200001b
>00518280
>363636f2
>d282000c
>04323b1b
>10360833
>d282001b
>046c6503
>d282001b
>046c630a
>103a091b
>d282001d
>0476091b
>083a3a33
>d2820017
>045def0e
>103a2f1d
>103c0f1d
>103e071b
>d282001f
>047e071b
>083e3e32
>103e2f1f
>d282001e
>047a131f
>1040151b
>d282001b
>0482151b
>08363631
>10362f1b
>d282001e
>047a0d1b
>d00c0014
>0201011e
>d200001e
>005102c1
>7e3c0b1e
>d282001f
>044a3d1f
>d282001b
>04523d1b
>d2060020
>2201011b
>7e405520
>103e411f
>103e3e5b
>0a3e3e5a
>d282001f
>03c1e31f
>d2060822
>0201011f
>d282001d
>040a3d1d
>103a411d
>103a3a5d
>0a3a3a5c
>d282001d
>03c1e11d
>d2060821
>0201011d
>f0800100
>00431d21
>bf8c0770
>d206011e
>0201011d
>103c3c06
>0a3c3c07
>d0040014
>0201011e
>d200001f
>00510280
>7e3e0b1f
>0836371e
>063c2f17
>d00c0014
>02023d1b
>d200001e
>00518280
>363c3cf2
>063c3f1e
>d0060014
>0201011d
>d200001d
>00518280
>363a3af2
>d282001d
>047a031d
>d206081d
>0201011d
>083c3af2
>d00c0014
>0201011b
>d200001b
>00518280
>363636f2
>d282000c
>04323d1b
>10360830
>d282001b
>046c5f03
>d282001b
>046c5d0a
>103c091b
>d282001e
>047a091b
>083c3c30
>d2820019
>0465ef0e
>103c331e
>103e0f1e
>1040071b
>d2820020
>0482071b
>0840402f
>10403320
>d282001f
>047e1320
>1042151b
>d282001b
>0486151b
>0836362e
>1036331b
>d282001f
>047e0d1b
>d00c0014
>0201011f
>d200001f
>005102c1
>7e3e0b1f
>d2820020
>044a3f20
>d282001b
>04523f1b
>d2060021
>2201011b
>7e425521
>10404320
>1040405b
>0a40405a
>d2820020
>03c1e320
>d2060823
>02010120
>d282001e
>040a3f1e
>103c431e
>103c3c5d
>0a3c3c5c
>d282001e
>03c1e11e
>d2060822
>0201011e
>f0800100
>00431e22
>bf8c0770
>d206011f
>0201011e
>103e3e06
>0a3e3e07
>d0040014
>0201011f
>d2000020
>00510280
>7e400b20
>0836371f
>063e3319
>d00c0014
>02023f1b
>d200001f
>00518280
>363e3ef2
>063e411f
>d0060014
>0201011e
>d200001e
>00518280
>363c3cf2
>d282001e
>047e031e
>d206081e
>0201011e
>083e3cf2
>d00c0014
>0201011b
>d200001b
>00518280
>363636f2
>d282000c
>04323f1b
>06101908
>1018082a
>d282000c
>04305303
>d282000c
>0430510a
>1036090c
>d282001b
>046e090c
>0836362a
>d2820011
>0445ef0e
>1036231b
>103e0f1b
>1040070c
>d2820020
>0482070c
>08404029
>10402320
>d282001f
>047e1320
>1042150c
>d282000c
>0486150c
>08181828
>1018230c
>d282001f
>047e0d0c
>d00c0014
>0201011f
>d200001f
>005102c1
>7e3e0b1f
>d2820020
>044a3f20
>d282000c
>04523f0c
>d2060021
>2201010c
>7e425521
>10404320
>1040405b
>0a40405a
>d2820020
>03c1e320
>d2060823
>02010120
>d282001b
>040a3f1b
>1036431b
>1036365d
>0a36365c
>d282001b
>03c1e11b
>d2060822
>0201011b
>f0800100
>00431b22
>bf8c0770
>d206011f
>0201011b
>103e3e06
>0a3e3e07
>d0040014
>0201011f
>d2000020
>00510280
>7e400b20
>0818191f
>06222311
>d00c0014
>0202230c
>d2000011
>00518280
>362222f2
>06224111
>d0060014
>0201011b
>d200001b
>00518280
>363636f2
>d2820011
>0446031b
>d2060811
>02010111
>083622f2
>d00c0014
>0201010c
>d200000c
>00518280
>361818f2
>1018370c
>1036082d
>d282001b
>046c5903
>d282001b
>046c570a
>103e091b
>d282001f
>047e091b
>083e3e2d
>d2820015
>0455ef0e
>103e2b1f
>10400f1f
>1042071b
>d2820021
>0486071b
>0842422c
>10422b21
>d2820020
>04821321
>1044151b
>d282001b
>048a151b
>0836362b
>10362b1b
>d2820020
>04820d1b
>d00c0014
>02010120
>d2000020
>005102c1
>7e400b20
>d2820021
>044a4121
>d282001b
>0452411b
>d2060022
>2201011b
>7e445522
>10424521
>1042425b
>0a42425a
>d2820021
>03c1e321
>d2060824
>02010121
>d282001f
>040a411f
>103e451f
>103e3e5d
>0a3e3e5c
>d282001f
>03c1e11f
>d2060823
>0201011f
>f0800100
>00431f23
>bf8c0770
>d2060120
>0201011f
>10404006
>0a404007
>d0040014
>02010120
>d2000021
>00510280
>7e420b21
>08363720
>062a2b15
>d00c0014
>02022b1b
>d2000015
>00518280
>362a2af2
>062a4315
>d0060014
>0201011f
>d200001f
>00518280
>363e3ef2
>d2820015
>0456031f
>d2060815
>02010115
>083e2af2
>d00c0014
>0201011b
>d200001b
>00518280
>363636f2
>d282000c
>04323f1b
>10360817
>d282001b
>046c2d03
>d282001b
>046c0b0a
>103e091b
>d282001f
>047e091b
>083e3e17
>d2820017
>045def0e
>103e2f1f
>10400f1f
>1042071b
>d2820021
>0486071b
>08424216
>10422f21
>d2820020
>04821321
>1044151b
>d282001b
>048a151b
>08363605
>10362f1b
>d2820020
>04820d1b
>d00c0014
>02010120
>d2000020
>005102c1
>7e400b20
>d2820021
>044a4121
>d282001b
>0452411b
>d2060022
>2201011b
>7e445522
>10424521
>1042425b
>0a42425a
>d2820021
>03c1e321
>d2060824
>02010121
>d282001f
>040a411f
>103e451f
>103e3e5d
>0a3e3e5c
>d282001f
>03c1e11f
>d2060823
>0201011f
>f0800100
>00431f23
>bf8c0770
>d2060120
>0201011f
>10404006
>0a404007
>d0040014
>02010120
>d2000021
>00510280
>7e420b21
>08363720
>062e2f17
>d00c0014
>02022f1b
>d2000017
>00518280
>362e2ef2
>062e4317
>d0060014
>0201011f
>d200001f
>00518280
>363e3ef2
>d2820017
>045e031f
>d2060817
>02010117
>083e2ef2
>d00c0014
>0201011b
>d200001b
>00518280
>363636f2
>d282000c
>04323f1b
>10360804
>d282001b
>046c0703
>d282001b
>046c050a
>103e091b
>d2820004
>047e091b
>08080804
>d282000e
>0465ef0e
>10081d04
>100e0f04
>1032071b
>d2820003
>0466071b
>08060603
>10061d03
>d2820007
>041e1303
>1012151b
>d2820009
>0426151b
>08121202
>10121d09
>d2820006
>041e0d09
>d00c0002
>02010106
>d2000006
>000902c1
>7e0c0b06
>d2820003
>044a0d03
>d2820007
>04520d09
>d2060009
>22010107
>7e125509
>10061303
>1006065b
>0a06065a
>d2820003
>03c1e303
>d2060820
>02010103
>d2820002
>040a0d04
>10041302
>1004045d
>0a04045c
>d2820002
>03c1e102
>d206081f
>02010102
>f0800100
>0043021f
>bf8c0770
>d2060103
>02010102
>10060606
>0a060607
>d0040002
>02010103
>d2000004
>00090280
>7e080b04
>08060f03
>060c1d0e
>d00c0002
>02020d03
>d2000006
>00098280
>360c0cf2
>06080906
>d0060002
>02010102
>d2000002
>00098280
>360404f2
>d2820001
>04120302
>d2060801
>02010101
>080402f2
>d00c0002
>02010103
>d2000003
>00098280
>360606f2
>d2820002
>04320503
>06040508
>0606170d
>06062d03
>06063103
>06082113
>06081f04
>06080b04
>06060704
>0608351c
>06083b04
>06083d04
>06060903
>06082315
>06082f04
>06020304
>06020303
>080202ff
>41800000
>7e025501
>100a0302
>88fe007e
>d2100000
>02020105
>d2060800
>02010100
>080000f2
>10000100
>5e000080
>d25e0001
>02010080
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	S_WAITCNT 1807
>	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
>	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
>	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020107
>bf8c007f
>7e080204
>c2020105
>bf8c007f
>7e0a0204
>d2820004
>04120b03
>c2020106
>bf8c007f
>7e0a0204
>c2020104
>bf8c007f
>7e0c0204
>d2820005
>04160d02
>c2020103
>bf8c007f
>7e0c0204
>c2020101
>bf8c007f
>7e0e0204
>d2820006
>041a0f03
>c2020102
>bf8c007f
>7e0e0204
>c2000100
>bf8c007f
>7e100200
>d2820007
>041e1102
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0..223]
>DCL TEMP[0..11], LOCAL
>IMM[0] FLT32 {   -1.0000,     0.0000,     1.0000,     0.0000}
>  0: MAD TEMP[0], CONST[3].zwzw, IMM[0].xxyx, IN[0].xyxy
>  1: MOV TEMP[1].xy, TEMP[0].xyyy
>  2: TEX TEMP[1].w, TEMP[1], SAMP[0], 2D
>  3: MOV TEMP[0].xy, TEMP[0].zwww
>  4: TEX TEMP[0].w, TEMP[0], SAMP[0], 2D
>  5: MAD TEMP[2], CONST[3].zwzw, IMM[0].zxxy, IN[0].xyxy
>  6: MOV TEMP[3].xy, TEMP[2].xyyy
>  7: TEX TEMP[3].w, TEMP[3], SAMP[0], 2D
>  8: MOV TEMP[2].xy, TEMP[2].zwww
>  9: TEX TEMP[2].w, TEMP[2], SAMP[0], 2D
> 10: MOV TEMP[4].xy, IN[0].xyyy
> 11: TEX TEMP[4].w, TEMP[4], SAMP[0], 2D
> 12: MAD TEMP[5], CONST[3].zwzw, IMM[0].zyxz, IN[0].xyxy
> 13: MOV TEMP[6].xy, TEMP[5].xyyy
> 14: TEX TEMP[6].w, TEMP[6], SAMP[0], 2D
> 15: MAD TEMP[7], CONST[3].zwzw, IMM[0].yzzz, IN[0].xyxy
> 16: MOV TEMP[8].xy, TEMP[7].xyyy
> 17: TEX TEMP[8].w, TEMP[8], SAMP[0], 2D
> 18: MOV TEMP[7].xy, TEMP[7].zwww
> 19: TEX TEMP[7].w, TEMP[7], SAMP[0], 2D
> 20: MIN TEMP[9].x, TEMP[1].wwww, TEMP[2].wwww
> 21: MIN TEMP[10].x, TEMP[0].wwww, TEMP[4].wwww
> 22: MAX TEMP[0].x, TEMP[0].wwww, TEMP[4].wwww
> 23: MAX TEMP[4].x, TEMP[3].wwww, TEMP[6].wwww
> 24: MAX TEMP[11].x, TEMP[9].xxxx, TEMP[10].xxxx
> 25: MIN TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx
> 26: MIN TEMP[3].x, TEMP[3].wwww, TEMP[6].wwww
> 27: MAX TEMP[3].x, TEMP[9].xxxx, TEMP[3].xxxx
> 28: MIN TEMP[6].x, TEMP[0].xxxx, TEMP[4].xxxx
> 29: MAX TEMP[1].x, TEMP[1].wwww, TEMP[2].wwww
> 30: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[4].xxxx
> 31: MIN TEMP[0].x, TEMP[1].xxxx, TEMP[0].xxxx
> 32: MIN TEMP[1].x, TEMP[11].xxxx, TEMP[3].xxxx
> 33: MIN TEMP[2].x, TEMP[0].xxxx, TEMP[6].xxxx
> 34: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[6].xxxx
> 35: MAX TEMP[4].x, TEMP[1].xxxx, TEMP[2].xxxx
> 36: MIN TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
> 37: MOV TEMP[2].xy, TEMP[5].zwww
> 38: TEX TEMP[2].w, TEMP[2], SAMP[0], 2D
> 39: MAX TEMP[1].x, TEMP[1].xxxx, TEMP[2].wwww
> 40: MIN TEMP[2].x, TEMP[0].xxxx, TEMP[1].xxxx
> 41: MAX TEMP[3].x, TEMP[11].xxxx, TEMP[3].xxxx
> 42: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
> 43: MIN TEMP[0].x, TEMP[3].xxxx, TEMP[0].xxxx
> 44: MIN TEMP[1].x, TEMP[0].xxxx, TEMP[4].xxxx
> 45: MIN TEMP[3].x, TEMP[2].xxxx, TEMP[8].wwww
> 46: MAX TEMP[1].x, TEMP[1].xxxx, TEMP[3].xxxx
> 47: MOV TEMP[3].xyz, IMM[0].yyyy
> 48: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[4].xxxx
> 49: MAX TEMP[2].x, TEMP[2].xxxx, TEMP[8].wwww
> 50: MIN TEMP[0].x, TEMP[0].xxxx, TEMP[2].xxxx
> 51: MAX TEMP[2].x, TEMP[1].xxxx, TEMP[7].wwww
> 52: MIN TEMP[0].x, TEMP[0].xxxx, TEMP[2].xxxx
> 53: MIN TEMP[1].x, TEMP[1].xxxx, TEMP[7].wwww
> 54: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
> 55: MOV TEMP[3].w, TEMP[0].xxxx
> 56: MOV OUT[0], TEMP[3]
> 57: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = fmul float %22, -1.000000e+00
>  %31 = fadd float %30, %28
>  %32 = fmul float %23, -1.000000e+00
>  %33 = fadd float %32, %29
>  %34 = fmul float %22, 0.000000e+00
>  %35 = fadd float %34, %28
>  %36 = fmul float %23, -1.000000e+00
>  %37 = fadd float %36, %29
>  %38 = bitcast float %31 to i32
>  %39 = bitcast float %33 to i32
>  %40 = insertelement <2 x i32> undef, i32 %38, i32 0
>  %41 = insertelement <2 x i32> %40, i32 %39, i32 1
>  %42 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %41, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %43 = extractelement <4 x float> %42, i32 3
>  %44 = bitcast float %35 to i32
>  %45 = bitcast float %37 to i32
>  %46 = insertelement <2 x i32> undef, i32 %44, i32 0
>  %47 = insertelement <2 x i32> %46, i32 %45, i32 1
>  %48 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %47, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %49 = extractelement <4 x float> %48, i32 3
>  %50 = fmul float %22, 1.000000e+00
>  %51 = fadd float %50, %28
>  %52 = fmul float %23, -1.000000e+00
>  %53 = fadd float %52, %29
>  %54 = fmul float %22, -1.000000e+00
>  %55 = fadd float %54, %28
>  %56 = fmul float %23, 0.000000e+00
>  %57 = fadd float %56, %29
>  %58 = bitcast float %51 to i32
>  %59 = bitcast float %53 to i32
>  %60 = insertelement <2 x i32> undef, i32 %58, i32 0
>  %61 = insertelement <2 x i32> %60, i32 %59, i32 1
>  %62 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %61, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %63 = extractelement <4 x float> %62, i32 3
>  %64 = bitcast float %55 to i32
>  %65 = bitcast float %57 to i32
>  %66 = insertelement <2 x i32> undef, i32 %64, i32 0
>  %67 = insertelement <2 x i32> %66, i32 %65, i32 1
>  %68 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %67, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %69 = extractelement <4 x float> %68, i32 3
>  %70 = bitcast float %28 to i32
>  %71 = bitcast float %29 to i32
>  %72 = insertelement <2 x i32> undef, i32 %70, i32 0
>  %73 = insertelement <2 x i32> %72, i32 %71, i32 1
>  %74 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %73, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %75 = extractelement <4 x float> %74, i32 3
>  %76 = fmul float %22, 1.000000e+00
>  %77 = fadd float %76, %28
>  %78 = fmul float %23, 0.000000e+00
>  %79 = fadd float %78, %29
>  %80 = fmul float %22, -1.000000e+00
>  %81 = fadd float %80, %28
>  %82 = fmul float %23, 1.000000e+00
>  %83 = fadd float %82, %29
>  %84 = bitcast float %77 to i32
>  %85 = bitcast float %79 to i32
>  %86 = insertelement <2 x i32> undef, i32 %84, i32 0
>  %87 = insertelement <2 x i32> %86, i32 %85, i32 1
>  %88 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %87, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %89 = extractelement <4 x float> %88, i32 3
>  %90 = fmul float %22, 0.000000e+00
>  %91 = fadd float %90, %28
>  %92 = fmul float %23, 1.000000e+00
>  %93 = fadd float %92, %29
>  %94 = fmul float %22, 1.000000e+00
>  %95 = fadd float %94, %28
>  %96 = fmul float %23, 1.000000e+00
>  %97 = fadd float %96, %29
>  %98 = bitcast float %91 to i32
>  %99 = bitcast float %93 to i32
>  %100 = insertelement <2 x i32> undef, i32 %98, i32 0
>  %101 = insertelement <2 x i32> %100, i32 %99, i32 1
>  %102 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %101, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %103 = extractelement <4 x float> %102, i32 3
>  %104 = bitcast float %95 to i32
>  %105 = bitcast float %97 to i32
>  %106 = insertelement <2 x i32> undef, i32 %104, i32 0
>  %107 = insertelement <2 x i32> %106, i32 %105, i32 1
>  %108 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %107, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %109 = extractelement <4 x float> %108, i32 3
>  %110 = fcmp uge float %43, %69
>  %111 = select i1 %110, float %69, float %43
>  %112 = fcmp uge float %49, %75
>  %113 = select i1 %112, float %75, float %49
>  %114 = fcmp uge float %49, %75
>  %115 = select i1 %114, float %49, float %75
>  %116 = fcmp uge float %63, %89
>  %117 = select i1 %116, float %63, float %89
>  %118 = fcmp uge float %111, %113
>  %119 = select i1 %118, float %111, float %113
>  %120 = fcmp uge float %111, %113
>  %121 = select i1 %120, float %113, float %111
>  %122 = fcmp uge float %63, %89
>  %123 = select i1 %122, float %89, float %63
>  %124 = fcmp uge float %121, %123
>  %125 = select i1 %124, float %121, float %123
>  %126 = fcmp uge float %115, %117
>  %127 = select i1 %126, float %117, float %115
>  %128 = fcmp uge float %43, %69
>  %129 = select i1 %128, float %43, float %69
>  %130 = fcmp uge float %115, %117
>  %131 = select i1 %130, float %115, float %117
>  %132 = fcmp uge float %129, %131
>  %133 = select i1 %132, float %131, float %129
>  %134 = fcmp uge float %119, %125
>  %135 = select i1 %134, float %125, float %119
>  %136 = fcmp uge float %133, %127
>  %137 = select i1 %136, float %127, float %133
>  %138 = fcmp uge float %133, %127
>  %139 = select i1 %138, float %133, float %127
>  %140 = fcmp uge float %135, %137
>  %141 = select i1 %140, float %135, float %137
>  %142 = fcmp uge float %135, %137
>  %143 = select i1 %142, float %137, float %135
>  %144 = bitcast float %81 to i32
>  %145 = bitcast float %83 to i32
>  %146 = insertelement <2 x i32> undef, i32 %144, i32 0
>  %147 = insertelement <2 x i32> %146, i32 %145, i32 1
>  %148 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %147, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %149 = extractelement <4 x float> %148, i32 3
>  %150 = fcmp uge float %143, %149
>  %151 = select i1 %150, float %143, float %149
>  %152 = fcmp uge float %139, %151
>  %153 = select i1 %152, float %151, float %139
>  %154 = fcmp uge float %119, %125
>  %155 = select i1 %154, float %119, float %125
>  %156 = fcmp uge float %139, %151
>  %157 = select i1 %156, float %139, float %151
>  %158 = fcmp uge float %155, %157
>  %159 = select i1 %158, float %157, float %155
>  %160 = fcmp uge float %159, %141
>  %161 = select i1 %160, float %141, float %159
>  %162 = fcmp uge float %153, %103
>  %163 = select i1 %162, float %103, float %153
>  %164 = fcmp uge float %161, %163
>  %165 = select i1 %164, float %161, float %163
>  %166 = fcmp uge float %159, %141
>  %167 = select i1 %166, float %159, float %141
>  %168 = fcmp uge float %153, %103
>  %169 = select i1 %168, float %153, float %103
>  %170 = fcmp uge float %167, %169
>  %171 = select i1 %170, float %169, float %167
>  %172 = fcmp uge float %165, %109
>  %173 = select i1 %172, float %165, float %109
>  %174 = fcmp uge float %171, %173
>  %175 = select i1 %174, float %173, float %171
>  %176 = fcmp uge float %165, %109
>  %177 = select i1 %176, float %109, float %165
>  %178 = fcmp uge float %175, %177
>  %179 = select i1 %178, float %175, float %177
>  %180 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
>  %181 = bitcast i32 %180 to float
>  %182 = call i32 @llvm.SI.packf16(float 0.000000e+00, float %179)
>  %183 = bitcast i32 %182 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %181, float %183, float %181, float %183)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 15; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MAD_F32 %SGPR0, 0.000000e+00, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 14; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_ADD_F32_e32 %SGPR1, %VGPR2, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%29](align=8)(tbaa=!"const")
>	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%26](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	%VGPR7<def> = V_SUBREV_F32_e32 %SGPR0, %VGPR3, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
>	%VGPR8<def> = V_MOV_B32_e32 %VGPR4, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
>	%VGPR9<def> = V_MOV_B32_e32 %VGPR5, %EXEC<imp-use>
>	%VGPR9<def> = V_MOV_B32_e32 %VGPR7, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
>	%VGPR1<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR8_VGPR9<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR1, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR0, %VGPR1, %SGPR2_SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %SGPR1, 0.000000e+00, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
>	%VGPR10<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR6_VGPR7, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR10, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_CNDMASK_B32_e64 %VGPR9, %VGPR10, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR11, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_CNDMASK_B32_e64 %VGPR8, %VGPR11, %SGPR6_SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_SUBREV_F32_e32 %SGPR1<kill>, %VGPR2, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
>	%VGPR14<def> = V_MOV_B32_e32 %VGPR5, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
>	%VGPR15<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	%VGPR14<def> = V_MOV_B32_e32 %VGPR7, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
>	%VGPR16<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR16, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_CNDMASK_B32_e64 %VGPR15, %VGPR16, %SGPR20_SGPR21, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR22_SGPR23<def> = V_CMP_GE_F32_e64 %VGPR17, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_CNDMASK_B32_e64 %VGPR17<kill>, %VGPR12<kill>, %SGPR22_SGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR11<kill>, %VGPR8<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_CNDMASK_B32_e64 %VGPR12, %VGPR8, %SGPR6_SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_CNDMASK_B32_e64 %VGPR10<kill>, %VGPR9<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_CNDMASK_B32_e64 %VGPR16<kill>, %VGPR15<kill>, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR10, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_CNDMASK_B32_e64 %VGPR10, %VGPR9, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR1<kill>, %VGPR0<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR15, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR15<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, %VGPR10<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR1, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_CNDMASK_B32_e64 %VGPR1, %VGPR0, %SGPR2_SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR9, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_CNDMASK_B32_e64 %VGPR9, %VGPR11, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR14<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
>	%VGPR2<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR10, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR10<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR12<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR3, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR3, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR8<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR11<kill>, %VGPR9<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR0, %VGPR1, %SGPR2_SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR2<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_MOV_B32_e32 %VGPR14, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
>	%VGPR3<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR6_VGPR7<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR3, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR8, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR8<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_MOV_B32_e32 %VGPR14, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
>	%VGPR4<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR6, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR6, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR1<kill>, %VGPR0<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR2<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR5<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR4<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR1<kill>, %VGPR0<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 0.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c0840100
>bf8c007f
>c200090f
>bf8c007f
>d2820005
>040d0000
>c8080000
>c8090001
>c200890e
>bf8c007f
>06080401
>c0840300
>c0c60500
>bf8c007f
>f0800800
>00430004
>0a0e0600
>7e100304
>7e120305
>7e120307
>f0800800
>00430108
>bf8c0770
>d00c0002
>02020101
>d2000008
>000a0300
>f0800800
>00430902
>d2820006
>04090001
>f0800800
>00430a06
>bf8c0770
>d00c0004
>0202130a
>d200000b
>00121509
>d00c0006
>0202110b
>d200000c
>001a1708
>0a1a0401
>7e1c0305
>f0800800
>00430f0d
>7e1c0307
>f0800800
>0043100d
>bf8c0770
>d00c0014
>02021f10
>d2000011
>0052210f
>d00c0016
>02021911
>d200000c
>005a1911
>d2000008
>001a110b
>d00c0006
>0202110c
>d200000b
>001a110c
>d2000009
>0012130a
>d200000a
>00521f10
>d00c0004
>0202130a
>d200000f
>0012130a
>d2000000
>000a0101
>d00c0002
>0202010f
>d2000000
>000a1f00
>d2000001
>00121509
>d00c0002
>02020101
>d2000009
>000a0101
>d00c0004
>02021709
>d200000a
>00121709
>061c0600
>f0800800
>0043020d
>bf8c0770
>d00c0000
>0202050a
>d2000002
>00021502
>d2000003
>001a1908
>d00c0000
>02020503
>d2000008
>00020702
>d2000000
>000a0300
>d00c0002
>02021100
>d2000000
>000a1100
>d2000001
>0012130b
>d00c0002
>02020300
>d2000008
>000a0300
>d2000002
>00020503
>7e0e030e
>f0800800
>00430306
>bf8c0770
>d00c0000
>02020702
>d2000006
>00020702
>d00c0004
>02020d08
>d2000006
>00121106
>7e0a030e
>f0800800
>00430404
>bf8c0770
>d00c0004
>02020906
>d2000005
>00120d04
>d2000000
>000a0101
>d2000001
>00020503
>d00c0000
>02020300
>d2000000
>00020300
>d00c0000
>02020b00
>d2000000
>00020b00
>d2000001
>00120906
>d00c0000
>02020300
>d2000000
>00020101
>5e000080
>d25e0001
>02010080
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	S_WAITCNT 1807
>	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
>	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
>	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020107
>bf8c007f
>7e080204
>c2020105
>bf8c007f
>7e0a0204
>d2820004
>04120b03
>c2020106
>bf8c007f
>7e0a0204
>c2020104
>bf8c007f
>7e0c0204
>d2820005
>04160d02
>c2020103
>bf8c007f
>7e0c0204
>c2020101
>bf8c007f
>7e0e0204
>d2820006
>041a0f03
>c2020102
>bf8c007f
>7e0e0204
>c2000100
>bf8c007f
>7e100200
>d2820007
>041e1102
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[0..3]
>DCL TEMP[0..13], LOCAL
>IMM[0] FLT32 {    0.0000,     0.9500,     1.0000,     0.2216}
>IMM[1] FLT32 {   -1.5000,     1.5000,    -1.0000,     1.0000}
>IMM[2] FLT32 {   -2.0000,     2.0000,     0.1899,     0.1196}
>IMM[3] FLT32 {    0.0553,     0.0188,     0.0000,     0.0000}
>  0: MOV TEMP[0].xyz, IMM[0].xxxx
>  1: MOV TEMP[1].xy, IN[0].xyyy
>  2: TEX TEMP[1].w, TEMP[1], SAMP[1], 2D
>  3: MOV TEMP[0].w, TEMP[1].wwww
>  4: MOV TEMP[2].xy, IN[0].zwww
>  5: TEX TEMP[2].x, TEMP[2], SAMP[0], 2D
>  6: FSLT TEMP[3].x, IMM[0].yyyy, TEMP[2].xxxx
>  7: UIF TEMP[3].xxxx :0
>  8:   MOV TEMP[3], TEMP[0]
>  9: ELSE :0
> 10:   ABS TEMP[4].x, TEMP[2].xxxx
> 11:   MAD TEMP[4].x, TEMP[4].xxxx, CONST[1].yyyy, -CONST[1].xxxx
> 12:   ADD TEMP[5].x, -TEMP[4].xxxx, -CONST[3].xxxx
> 13:   MUL_SAT TEMP[5].x, TEMP[5].xxxx, CONST[3].wwww
> 14:   MAD TEMP[5].x, CONST[3].zzzz, TEMP[5].xxxx, IMM[0].zzzz
> 15:   MUL_SAT TEMP[6].x, -TEMP[4].xxxx, CONST[3].yyyy
> 16:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
> 17:   FSLT TEMP[2].x, TEMP[2].xxxx, IMM[0].xxxx
> 18:   UIF TEMP[2].xxxx :0
> 19:     MOV TEMP[2].x, CONST[0].yyyy
> 20:   ELSE :0
> 21:     MOV TEMP[2].x, TEMP[5].xxxx
> 22:   ENDIF
> 23:   MUL TEMP[2].x, TEMP[2].xxxx, CONST[0].zzzz
> 24:   MUL TEMP[2].x, CONST[0].xxxx, TEMP[2].xxxx
> 25:   MUL TEMP[5].x, TEMP[1].wwww, IMM[0].wwww
> 26:   MAD TEMP[6], CONST[2].xyxy, IMM[1].xxyy, IN[0].xyxy
> 27:   MAD TEMP[7], CONST[2].zwzw, IMM[1].zzww, IN[0].zwzw
> 28:   MAD TEMP[8], CONST[2].zwzw, IMM[2].xxyy, IN[0].zwzw
> 29:   MOV TEMP[9].xy, TEMP[7].xyyy
> 30:   TEX TEMP[9].x, TEMP[9], SAMP[0], 2D
> 31:   MOV TEMP[9].x, TEMP[9].xxxx
> 32:   MOV TEMP[10].xy, TEMP[7].zwww
> 33:   TEX TEMP[10].x, TEMP[10], SAMP[0], 2D
> 34:   MOV TEMP[9].y, TEMP[10].xxxx
> 35:   MOV TEMP[10].xy, TEMP[8].xyyy
> 36:   TEX TEMP[10].x, TEMP[10], SAMP[0], 2D
> 37:   MOV TEMP[9].z, TEMP[10].xxxx
> 38:   MOV TEMP[10].xy, TEMP[8].zwww
> 39:   TEX TEMP[10].x, TEMP[10], SAMP[0], 2D
> 40:   MOV TEMP[9].w, TEMP[10].xxxx
> 41:   MOV TEMP[10].xy, TEMP[6].xyyy
> 42:   TEX TEMP[10].w, TEMP[10], SAMP[1], 2D
> 43:   MOV TEMP[10].x, TEMP[10].wwww
> 44:   MOV TEMP[11].xy, TEMP[6].zwww
> 45:   TEX TEMP[11].w, TEMP[11], SAMP[1], 2D
> 46:   MOV TEMP[10].y, TEMP[11].wwww
> 47:   ABS TEMP[11], TEMP[9]
> 48:   MAD TEMP[11], TEMP[11], CONST[1].yyyy, -CONST[1].xxxx
> 49:   ADD TEMP[11], TEMP[11], -TEMP[4].xxxx
> 50:   ABS TEMP[11], TEMP[11]
> 51:   FSGE TEMP[12].x, TEMP[11].xxxx, TEMP[2].xxxx
> 52:   UIF TEMP[12].xxxx :0
> 53:     MOV TEMP[12].x, IMM[0].xxxx
> 54:   ELSE :0
> 55:     MOV TEMP[12].x, IMM[2].zzzz
> 56:   ENDIF
> 57:   MOV TEMP[12].x, TEMP[12].xxxx
> 58:   FSGE TEMP[13].x, TEMP[11].yyyy, TEMP[2].xxxx
> 59:   UIF TEMP[13].xxxx :0
> 60:     MOV TEMP[13].x, IMM[0].xxxx
> 61:   ELSE :0
> 62:     MOV TEMP[13].x, IMM[2].zzzz
> 63:   ENDIF
> 64:   MOV TEMP[12].y, TEMP[13].xxxx
> 65:   FSGE TEMP[13].x, TEMP[11].zzzz, TEMP[2].xxxx
> 66:   UIF TEMP[13].xxxx :0
> 67:     MOV TEMP[13].x, IMM[0].xxxx
> 68:   ELSE :0
> 69:     MOV TEMP[13].x, IMM[2].wwww
> 70:   ENDIF
> 71:   MOV TEMP[12].z, TEMP[13].xxxx
> 72:   FSGE TEMP[11].x, TEMP[11].wwww, TEMP[2].xxxx
> 73:   UIF TEMP[11].xxxx :0
> 74:     MOV TEMP[11].x, IMM[0].xxxx
> 75:   ELSE :0
> 76:     MOV TEMP[11].x, IMM[2].wwww
> 77:   ENDIF
> 78:   MOV TEMP[12].w, TEMP[11].xxxx
> 79:   DP4 TEMP[11].x, TEMP[10].xyxy, TEMP[12]
> 80:   ADD TEMP[5].x, TEMP[5].xxxx, TEMP[11].xxxx
> 81:   ADD TEMP[1], IMM[0].wxxx, TEMP[12]
> 82:   MAD TEMP[6], CONST[2].xyxy, IMM[2].xxyy, TEMP[6]
> 83:   MAD TEMP[7], CONST[2].zwzw, IMM[2].xxyy, TEMP[7]
> 84:   MAD TEMP[8], CONST[2].zwzw, IMM[2].xxyy, TEMP[8]
> 85:   MOV TEMP[11].xy, TEMP[7].xyyy
> 86:   TEX TEMP[11].x, TEMP[11], SAMP[0], 2D
> 87:   MOV TEMP[9].x, TEMP[11].xxxx
> 88:   MOV TEMP[7].xy, TEMP[7].zwww
> 89:   TEX TEMP[7].x, TEMP[7], SAMP[0], 2D
> 90:   MOV TEMP[9].y, TEMP[7].xxxx
> 91:   MOV TEMP[7].xy, TEMP[8].xyyy
> 92:   TEX TEMP[7].x, TEMP[7], SAMP[0], 2D
> 93:   MOV TEMP[9].z, TEMP[7].xxxx
> 94:   MOV TEMP[7].xy, TEMP[8].zwww
> 95:   TEX TEMP[7].x, TEMP[7], SAMP[0], 2D
> 96:   MOV TEMP[9].w, TEMP[7].xxxx
> 97:   MOV TEMP[7].xy, TEMP[6].xyyy
> 98:   TEX TEMP[7].w, TEMP[7], SAMP[1], 2D
> 99:   MOV TEMP[10].x, TEMP[7].wwww
>100:   MOV TEMP[6].xy, TEMP[6].zwww
>101:   TEX TEMP[6].w, TEMP[6], SAMP[1], 2D
>102:   MOV TEMP[10].y, TEMP[6].wwww
>103:   ABS TEMP[6], TEMP[9]
>104:   MAD TEMP[6], TEMP[6], CONST[1].yyyy, -CONST[1].xxxx
>105:   ADD TEMP[4], TEMP[6], -TEMP[4].xxxx
>106:   ABS TEMP[4], TEMP[4]
>107:   FSGE TEMP[6].x, TEMP[4].xxxx, TEMP[2].xxxx
>108:   UIF TEMP[6].xxxx :0
>109:     MOV TEMP[6].x, IMM[0].xxxx
>110:   ELSE :0
>111:     MOV TEMP[6].x, IMM[3].xxxx
>112:   ENDIF
>113:   MOV TEMP[12].x, TEMP[6].xxxx
>114:   FSGE TEMP[6].x, TEMP[4].yyyy, TEMP[2].xxxx
>115:   UIF TEMP[6].xxxx :0
>116:     MOV TEMP[6].x, IMM[0].xxxx
>117:   ELSE :0
>118:     MOV TEMP[6].x, IMM[3].xxxx
>119:   ENDIF
>120:   MOV TEMP[12].y, TEMP[6].xxxx
>121:   FSGE TEMP[6].x, TEMP[4].zzzz, TEMP[2].xxxx
>122:   UIF TEMP[6].xxxx :0
>123:     MOV TEMP[6].x, IMM[0].xxxx
>124:   ELSE :0
>125:     MOV TEMP[6].x, IMM[3].yyyy
>126:   ENDIF
>127:   MOV TEMP[12].z, TEMP[6].xxxx
>128:   FSGE TEMP[2].x, TEMP[4].wwww, TEMP[2].xxxx
>129:   UIF TEMP[2].xxxx :0
>130:     MOV TEMP[2].x, IMM[0].xxxx
>131:   ELSE :0
>132:     MOV TEMP[2].x, IMM[3].yyyy
>133:   ENDIF
>134:   MOV TEMP[12].w, TEMP[2].xxxx
>135:   DP4 TEMP[2].x, TEMP[10].xyxy, TEMP[12]
>136:   ADD TEMP[2].x, TEMP[5].xxxx, TEMP[2].xxxx
>137:   ADD TEMP[1], TEMP[1], TEMP[12]
>138:   DP4 TEMP[1].x, TEMP[1], IMM[0].zzzz
>139:   RCP TEMP[1].x, TEMP[1].xxxx
>140:   MUL TEMP[1].x, TEMP[2].xxxx, TEMP[1].xxxx
>141:   MOV TEMP[0].w, TEMP[1].xxxx
>142:   MOV TEMP[3], TEMP[0]
>143: ENDIF
>144: MOV OUT[0], TEMP[3]
>145: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
>  %35 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %36 = load <32 x i8> addrspace(2)* %35, !tbaa !0
>  %37 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
>  %39 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %40 = load <32 x i8> addrspace(2)* %39, !tbaa !0
>  %41 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %46 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %47 = bitcast float %43 to i32
>  %48 = bitcast float %44 to i32
>  %49 = insertelement <2 x i32> undef, i32 %47, i32 0
>  %50 = insertelement <2 x i32> %49, i32 %48, i32 1
>  %51 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %50, <32 x i8> %40, <16 x i8> %42, i32 2)
>  %52 = extractelement <4 x float> %51, i32 3
>  %53 = bitcast float %45 to i32
>  %54 = bitcast float %46 to i32
>  %55 = insertelement <2 x i32> undef, i32 %53, i32 0
>  %56 = insertelement <2 x i32> %55, i32 %54, i32 1
>  %57 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %56, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %58 = extractelement <4 x float> %57, i32 0
>  %59 = fcmp olt float 0x3FEE666660000000, %58
>  %60 = sext i1 %59 to i32
>  %61 = bitcast i32 %60 to float
>  %62 = bitcast float %61 to i32
>  %63 = icmp ne i32 %62, 0
>  br i1 %63, label %ENDIF, label %ELSE
>
>ELSE:                                             ; preds = %main_body
>  %64 = call float @fabs(float %58)
>  %65 = fsub float -0.000000e+00, %25
>  %66 = fmul float %64, %26
>  %67 = fadd float %66, %65
>  %68 = fsub float -0.000000e+00, %67
>  %69 = fsub float -0.000000e+00, %31
>  %70 = fadd float %68, %69
>  %71 = fmul float %70, %34
>  %72 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %73 = fmul float %33, %72
>  %74 = fadd float %73, 1.000000e+00
>  %75 = fsub float -0.000000e+00, %67
>  %76 = fmul float %75, %32
>  %77 = call float @llvm.AMDIL.clamp.(float %76, float 0.000000e+00, float 1.000000e+00)
>  %78 = fmul float %74, %77
>  %79 = fcmp olt float %58, 0.000000e+00
>  %80 = sext i1 %79 to i32
>  %81 = bitcast i32 %80 to float
>  %82 = bitcast float %81 to i32
>  %83 = icmp ne i32 %82, 0
>  %. = select i1 %83, float %23, float %78
>  %84 = fmul float %., %24
>  %85 = fmul float %22, %84
>  %86 = fmul float %52, 0x3FCC5E8920000000
>  %87 = fmul float %27, -1.500000e+00
>  %88 = fadd float %87, %43
>  %89 = fmul float %28, -1.500000e+00
>  %90 = fadd float %89, %44
>  %91 = fmul float %27, 1.500000e+00
>  %92 = fadd float %91, %43
>  %93 = fmul float %28, 1.500000e+00
>  %94 = fadd float %93, %44
>  %95 = fmul float %29, -1.000000e+00
>  %96 = fadd float %95, %45
>  %97 = fmul float %30, -1.000000e+00
>  %98 = fadd float %97, %46
>  %99 = fmul float %29, 1.000000e+00
>  %100 = fadd float %99, %45
>  %101 = fmul float %30, 1.000000e+00
>  %102 = fadd float %101, %46
>  %103 = fmul float %29, -2.000000e+00
>  %104 = fadd float %103, %45
>  %105 = fmul float %30, -2.000000e+00
>  %106 = fadd float %105, %46
>  %107 = fmul float %29, 2.000000e+00
>  %108 = fadd float %107, %45
>  %109 = fmul float %30, 2.000000e+00
>  %110 = fadd float %109, %46
>  %111 = bitcast float %96 to i32
>  %112 = bitcast float %98 to i32
>  %113 = insertelement <2 x i32> undef, i32 %111, i32 0
>  %114 = insertelement <2 x i32> %113, i32 %112, i32 1
>  %115 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %114, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %116 = extractelement <4 x float> %115, i32 0
>  %117 = bitcast float %100 to i32
>  %118 = bitcast float %102 to i32
>  %119 = insertelement <2 x i32> undef, i32 %117, i32 0
>  %120 = insertelement <2 x i32> %119, i32 %118, i32 1
>  %121 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %120, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %122 = extractelement <4 x float> %121, i32 0
>  %123 = bitcast float %104 to i32
>  %124 = bitcast float %106 to i32
>  %125 = insertelement <2 x i32> undef, i32 %123, i32 0
>  %126 = insertelement <2 x i32> %125, i32 %124, i32 1
>  %127 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %126, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %128 = extractelement <4 x float> %127, i32 0
>  %129 = bitcast float %108 to i32
>  %130 = bitcast float %110 to i32
>  %131 = insertelement <2 x i32> undef, i32 %129, i32 0
>  %132 = insertelement <2 x i32> %131, i32 %130, i32 1
>  %133 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %132, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %134 = extractelement <4 x float> %133, i32 0
>  %135 = bitcast float %88 to i32
>  %136 = bitcast float %90 to i32
>  %137 = insertelement <2 x i32> undef, i32 %135, i32 0
>  %138 = insertelement <2 x i32> %137, i32 %136, i32 1
>  %139 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %138, <32 x i8> %40, <16 x i8> %42, i32 2)
>  %140 = extractelement <4 x float> %139, i32 3
>  %141 = bitcast float %92 to i32
>  %142 = bitcast float %94 to i32
>  %143 = insertelement <2 x i32> undef, i32 %141, i32 0
>  %144 = insertelement <2 x i32> %143, i32 %142, i32 1
>  %145 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %144, <32 x i8> %40, <16 x i8> %42, i32 2)
>  %146 = extractelement <4 x float> %145, i32 3
>  %147 = call float @fabs(float %116)
>  %148 = call float @fabs(float %122)
>  %149 = call float @fabs(float %128)
>  %150 = call float @fabs(float %134)
>  %151 = fsub float -0.000000e+00, %25
>  %152 = fmul float %147, %26
>  %153 = fadd float %152, %151
>  %154 = fsub float -0.000000e+00, %25
>  %155 = fmul float %148, %26
>  %156 = fadd float %155, %154
>  %157 = fsub float -0.000000e+00, %25
>  %158 = fmul float %149, %26
>  %159 = fadd float %158, %157
>  %160 = fsub float -0.000000e+00, %25
>  %161 = fmul float %150, %26
>  %162 = fadd float %161, %160
>  %163 = fsub float -0.000000e+00, %67
>  %164 = fadd float %153, %163
>  %165 = fsub float -0.000000e+00, %67
>  %166 = fadd float %156, %165
>  %167 = fsub float -0.000000e+00, %67
>  %168 = fadd float %159, %167
>  %169 = fsub float -0.000000e+00, %67
>  %170 = fadd float %162, %169
>  %171 = call float @fabs(float %164)
>  %172 = call float @fabs(float %166)
>  %173 = call float @fabs(float %168)
>  %174 = call float @fabs(float %170)
>  %175 = fcmp oge float %171, %85
>  %176 = sext i1 %175 to i32
>  %177 = bitcast i32 %176 to float
>  %178 = bitcast float %177 to i32
>  %179 = icmp ne i32 %178, 0
>  %temp48.0 = select i1 %179, float 0.000000e+00, float 0x3FC84FF440000000
>  %180 = fcmp oge float %172, %85
>  %181 = sext i1 %180 to i32
>  %182 = bitcast i32 %181 to float
>  %183 = bitcast float %182 to i32
>  %184 = icmp ne i32 %183, 0
>  %.83 = select i1 %184, float 0.000000e+00, float 0x3FC84FF440000000
>  %185 = fcmp oge float %173, %85
>  %186 = sext i1 %185 to i32
>  %187 = bitcast i32 %186 to float
>  %188 = bitcast float %187 to i32
>  %189 = icmp ne i32 %188, 0
>  %temp52.1 = select i1 %189, float 0.000000e+00, float 0x3FBE9AE500000000
>  %190 = fcmp oge float %174, %85
>  %191 = sext i1 %190 to i32
>  %192 = bitcast i32 %191 to float
>  %193 = bitcast float %192 to i32
>  %194 = icmp ne i32 %193, 0
>  %.84 = select i1 %194, float 0.000000e+00, float 0x3FBE9AE500000000
>  %195 = fmul float %140, %temp48.0
>  %196 = fmul float %146, %.83
>  %197 = fadd float %195, %196
>  %198 = fmul float %140, %temp52.1
>  %199 = fadd float %197, %198
>  %200 = fmul float %146, %.84
>  %201 = fadd float %199, %200
>  %202 = fadd float %86, %201
>  %203 = fadd float 0x3FCC5E8920000000, %temp48.0
>  %204 = fadd float 0.000000e+00, %.83
>  %205 = fadd float 0.000000e+00, %temp52.1
>  %206 = fadd float 0.000000e+00, %.84
>  %207 = fmul float %27, -2.000000e+00
>  %208 = fadd float %207, %88
>  %209 = fmul float %28, -2.000000e+00
>  %210 = fadd float %209, %90
>  %211 = fmul float %27, 2.000000e+00
>  %212 = fadd float %211, %92
>  %213 = fmul float %28, 2.000000e+00
>  %214 = fadd float %213, %94
>  %215 = fmul float %29, -2.000000e+00
>  %216 = fadd float %215, %96
>  %217 = fmul float %30, -2.000000e+00
>  %218 = fadd float %217, %98
>  %219 = fmul float %29, 2.000000e+00
>  %220 = fadd float %219, %100
>  %221 = fmul float %30, 2.000000e+00
>  %222 = fadd float %221, %102
>  %223 = fmul float %29, -2.000000e+00
>  %224 = fadd float %223, %104
>  %225 = fmul float %30, -2.000000e+00
>  %226 = fadd float %225, %106
>  %227 = fmul float %29, 2.000000e+00
>  %228 = fadd float %227, %108
>  %229 = fmul float %30, 2.000000e+00
>  %230 = fadd float %229, %110
>  %231 = bitcast float %216 to i32
>  %232 = bitcast float %218 to i32
>  %233 = insertelement <2 x i32> undef, i32 %231, i32 0
>  %234 = insertelement <2 x i32> %233, i32 %232, i32 1
>  %235 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %234, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %236 = extractelement <4 x float> %235, i32 0
>  %237 = bitcast float %220 to i32
>  %238 = bitcast float %222 to i32
>  %239 = insertelement <2 x i32> undef, i32 %237, i32 0
>  %240 = insertelement <2 x i32> %239, i32 %238, i32 1
>  %241 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %240, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %242 = extractelement <4 x float> %241, i32 0
>  %243 = bitcast float %224 to i32
>  %244 = bitcast float %226 to i32
>  %245 = insertelement <2 x i32> undef, i32 %243, i32 0
>  %246 = insertelement <2 x i32> %245, i32 %244, i32 1
>  %247 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %246, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %248 = extractelement <4 x float> %247, i32 0
>  %249 = bitcast float %228 to i32
>  %250 = bitcast float %230 to i32
>  %251 = insertelement <2 x i32> undef, i32 %249, i32 0
>  %252 = insertelement <2 x i32> %251, i32 %250, i32 1
>  %253 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %252, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %254 = extractelement <4 x float> %253, i32 0
>  %255 = bitcast float %208 to i32
>  %256 = bitcast float %210 to i32
>  %257 = insertelement <2 x i32> undef, i32 %255, i32 0
>  %258 = insertelement <2 x i32> %257, i32 %256, i32 1
>  %259 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %258, <32 x i8> %40, <16 x i8> %42, i32 2)
>  %260 = extractelement <4 x float> %259, i32 3
>  %261 = bitcast float %212 to i32
>  %262 = bitcast float %214 to i32
>  %263 = insertelement <2 x i32> undef, i32 %261, i32 0
>  %264 = insertelement <2 x i32> %263, i32 %262, i32 1
>  %265 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %264, <32 x i8> %40, <16 x i8> %42, i32 2)
>  %266 = extractelement <4 x float> %265, i32 3
>  %267 = call float @fabs(float %236)
>  %268 = call float @fabs(float %242)
>  %269 = call float @fabs(float %248)
>  %270 = call float @fabs(float %254)
>  %271 = fsub float -0.000000e+00, %25
>  %272 = fmul float %267, %26
>  %273 = fadd float %272, %271
>  %274 = fsub float -0.000000e+00, %25
>  %275 = fmul float %268, %26
>  %276 = fadd float %275, %274
>  %277 = fsub float -0.000000e+00, %25
>  %278 = fmul float %269, %26
>  %279 = fadd float %278, %277
>  %280 = fsub float -0.000000e+00, %25
>  %281 = fmul float %270, %26
>  %282 = fadd float %281, %280
>  %283 = fsub float -0.000000e+00, %67
>  %284 = fadd float %273, %283
>  %285 = fsub float -0.000000e+00, %67
>  %286 = fadd float %276, %285
>  %287 = fsub float -0.000000e+00, %67
>  %288 = fadd float %279, %287
>  %289 = fsub float -0.000000e+00, %67
>  %290 = fadd float %282, %289
>  %291 = call float @fabs(float %284)
>  %292 = call float @fabs(float %286)
>  %293 = call float @fabs(float %288)
>  %294 = call float @fabs(float %290)
>  %295 = fcmp oge float %291, %85
>  %296 = sext i1 %295 to i32
>  %297 = bitcast i32 %296 to float
>  %298 = bitcast float %297 to i32
>  %299 = icmp ne i32 %298, 0
>  %temp24.0 = select i1 %299, float 0.000000e+00, float 0x3FAC4BB500000000
>  %300 = fcmp oge float %292, %85
>  %301 = sext i1 %300 to i32
>  %302 = bitcast i32 %301 to float
>  %303 = bitcast float %302 to i32
>  %304 = icmp ne i32 %303, 0
>  %.85 = select i1 %304, float 0.000000e+00, float 0x3FAC4BB500000000
>  %305 = fcmp oge float %293, %85
>  %306 = sext i1 %305 to i32
>  %307 = bitcast i32 %306 to float
>  %308 = bitcast float %307 to i32
>  %309 = icmp ne i32 %308, 0
>  %temp24.2 = select i1 %309, float 0.000000e+00, float 0x3F9336A260000000
>  %310 = fcmp oge float %294, %85
>  %311 = sext i1 %310 to i32
>  %312 = bitcast i32 %311 to float
>  %313 = bitcast float %312 to i32
>  %314 = icmp ne i32 %313, 0
>  %.86 = select i1 %314, float 0.000000e+00, float 0x3F9336A260000000
>  %315 = fmul float %260, %temp24.0
>  %316 = fmul float %266, %.85
>  %317 = fadd float %315, %316
>  %318 = fmul float %260, %temp24.2
>  %319 = fadd float %317, %318
>  %320 = fmul float %266, %.86
>  %321 = fadd float %319, %320
>  %322 = fadd float %202, %321
>  %323 = fadd float %203, %temp24.0
>  %324 = fadd float %204, %.85
>  %325 = fadd float %205, %temp24.2
>  %326 = fadd float %206, %.86
>  %327 = fmul float %323, 1.000000e+00
>  %328 = fmul float %324, 1.000000e+00
>  %329 = fadd float %327, %328
>  %330 = fmul float %325, 1.000000e+00
>  %331 = fadd float %329, %330
>  %332 = fmul float %326, 1.000000e+00
>  %333 = fadd float %331, %332
>  %334 = fdiv float 1.000000e+00, %333
>  %335 = fmul float %322, %334
>  br label %ENDIF
>
>ENDIF:                                            ; preds = %main_body, %ELSE
>  %temp15.0 = phi float [ %335, %ELSE ], [ %52, %main_body ]
>  %336 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
>  %337 = bitcast i32 %336 to float
>  %338 = call i32 @llvm.SI.packf16(float 0.000000e+00, float %temp15.0)
>  %339 = bitcast i32 %338 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %337, float %339, float %337, float %339)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg26, %SGPR2_SGPR3 in %vreg27, %SGPR4_SGPR5 in %vreg28, %SGPR6 in %vreg29, %VGPR0 in %vreg30, %VGPR1 in %vreg31
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
>	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
>	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
>	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
>	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%46](align=8)(tbaa=!"const")
>	%SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%43](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR2<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR20_SGPR21_SGPR22_SGPR23, %EXEC<imp-use>
>	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
>	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%40](align=8)(tbaa=!"const")
>	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%37](tbaa=!"const")
>	S_WAITCNT 112
>	%VGPR0<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	%VGPR1<def> = V_MOV_B32_e32 9.500000e-01, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR2_SGPR3<def> = V_CMP_GT_F32_e64 %VGPR0, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_EQ_I32_e64 %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
>	S_CBRANCH_EXECZ <BB#2>, %EXEC
>    Successors according to CFG: BB#1(16) BB#2(16)
>
>BB#1: derived from LLVM BB %ELSE
>    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR0 %SGPR0_SGPR1 %VGPR5_VGPR6 %VGPR3_VGPR4 %SGPR2_SGPR3 %VGPR2
>    Predecessors according to CFG: BB#0
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 15; mem:LD4[<unknown>]
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 14; mem:LD4[<unknown>]
>	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 13; mem:LD4[<unknown>]
>	%SGPR33<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 12; mem:LD4[<unknown>]
>	%SGPR34<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 11; mem:LD4[<unknown>]
>	%SGPR35<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 10; mem:LD4[<unknown>]
>	%SGPR36<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 9; mem:LD4[<unknown>]
>	%SGPR37<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 8; mem:LD4[<unknown>]
>	%SGPR38<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 5; mem:LD4[<unknown>]
>	%SGPR39<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 4; mem:LD4[<unknown>]
>	%SGPR40<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 2; mem:LD4[<unknown>]
>	%SGPR41<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 1; mem:LD4[<unknown>]
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7<kill>, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR1<def> = V_MOV_B32_e32 %SGPR36<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR37<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR41<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_ADD_F32_e64 %SGPR34, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
>	%VGPR11<def> = V_MOV_B32_e32 %SGPR34, %EXEC<imp-use>
>	%VGPR12<def> = V_ADD_F32_e64 %SGPR34, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR14<def> = V_ADD_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
>	%VGPR9<def> = V_ADD_F32_e64 %SGPR35, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
>	%VGPR15<def> = V_MOV_B32_e32 %SGPR35, %EXEC<imp-use>
>	%VGPR16<def> = V_ADD_F32_e64 %SGPR35, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_ADD_F32_e32 %VGPR16, %VGPR9, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
>	%VGPR13<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR13<def> = V_ADD_F32_e64 %VGPR13<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_MUL_F32_e32 %SGPR38, %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR13<def> = V_SUBREV_F32_e32 %SGPR39, %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_ADD_F32_e64 %VGPR0, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR14<def> = V_MUL_F32_e32 %SGPR38, %VGPR14<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_SUBREV_F32_e32 %SGPR39, %VGPR14<kill>, %EXEC<imp-use>
>	%VGPR13<def> = V_SUB_F32_e32 %VGPR13<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR13<def> = V_ADD_F32_e64 %VGPR13<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_ADD_F32_e64 %VGPR14, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR18<def> = V_SUBREV_F32_e32 %SGPR33<kill>, %VGPR17, %EXEC<imp-use>
>	%VGPR18<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR18<kill>, %EXEC<imp-use>
>	%VGPR18<def> = V_ADD_F32_e64 %VGPR18<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR18<def> = V_MAD_F32 %SGPR1<kill>, %VGPR18<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_MUL_F32_e32 %SGPR32<kill>, %VGPR17<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_ADD_F32_e64 %VGPR17<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_MUL_F32_e32 %VGPR18<kill>, %VGPR17<kill>, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_LT_F32_e64 %VGPR0<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR17<kill>, %VGPR8<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_MUL_F32_e32 %SGPR40<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR13<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_MOV_B32_e32 5.526510e-02, %EXEC<imp-use>
>	%VGPR13<def> = V_CNDMASK_B32_e64 %VGPR8, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
>	%VGPR19<def> = V_MAD_F32 %VGPR1, %VGPR17, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19<imp-def>
>	%VGPR20<def> = V_ADD_F32_e64 %VGPR1, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR21<def> = V_ADD_F32_e32 %VGPR20<kill>, %VGPR19, %EXEC<imp-use>, %VGPR20_VGPR21<imp-def>
>	%VGPR18<def> = V_MAD_F32 %VGPR7, %VGPR17<kill>, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19<imp-use,kill>, %VGPR18_VGPR19<imp-def>
>	%VGPR17<def> = V_ADD_F32_e64 %VGPR7, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR20<def> = V_ADD_F32_e32 %VGPR17<kill>, %VGPR18, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
>	%VGPR17<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR20_VGPR21<kill>, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR20_SGPR21_SGPR22_SGPR23, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR20<def> = V_MUL_F32_e32 %VGPR17, %VGPR13, %EXEC<imp-use>
>	%VGPR22<def> = V_SUB_F32_e64 %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22<imp-def>
>	%VGPR24<def> = V_MAD_F32 %SGPR34, -2.000000e+00, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR23_VGPR24<imp-def>
>	%VGPR21<def> = V_SUB_F32_e64 %VGPR3, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22<imp-use,kill>, %VGPR21_VGPR22<imp-def>
>	%VGPR23<def> = V_MAD_F32 %SGPR35, -2.000000e+00, %VGPR21, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR23_VGPR24<imp-use,kill>, %VGPR23_VGPR24<imp-def>
>	%VGPR11<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR23_VGPR24<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %SGPR38, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_SUBREV_F32_e32 %SGPR39, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR11<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MOV_B32_e32 -1.500000e+00, %EXEC<imp-use>
>	%VGPR24<def> = V_MAD_F32 %VGPR1, %VGPR11, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR23_VGPR24<imp-def>
>	%VGPR26<def> = V_MAD_F32 %VGPR1<kill>, -2.000000e+00, %VGPR24, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26<imp-def>
>	%VGPR23<def> = V_MAD_F32 %VGPR7, %VGPR11<kill>, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR23_VGPR24<imp-use,kill>, %VGPR23_VGPR24<imp-def>
>	%VGPR25<def> = V_MAD_F32 %VGPR7<kill>, -2.000000e+00, %VGPR23, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26<imp-use,kill>, %VGPR25_VGPR26<imp-def>
>	%VGPR1<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26<kill>, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR20_SGPR21_SGPR22_SGPR23, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR5<def> = V_MAD_F32 %VGPR1, %VGPR8, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %SGPR34, -2.000000e+00, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
>	%VGPR26<def> = V_MAD_F32 %SGPR34<kill>, -2.000000e+00, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26<imp-def>
>	%VGPR6<def> = V_MAD_F32 %SGPR35, -2.000000e+00, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
>	%VGPR25<def> = V_MAD_F32 %SGPR35<kill>, -2.000000e+00, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26<imp-use,kill>, %VGPR25_VGPR26<imp-def>
>	%VGPR11<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %SGPR38, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_SUBREV_F32_e32 %SGPR39, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR11<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MOV_B32_e32 1.876310e-02, %EXEC<imp-use>
>	%VGPR15<def> = V_CNDMASK_B32_e64 %VGPR11, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, %VGPR15, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_ADD_F32_e32 %VGPR4, %VGPR12, %EXEC<imp-use>, %VGPR25_VGPR26<imp-def>
>	%VGPR28<def> = V_ADD_F32_e32 %VGPR12<kill>, %VGPR26, %EXEC<imp-use>, %VGPR27_VGPR28<imp-def>
>	%VGPR25<def> = V_ADD_F32_e32 %VGPR3, %VGPR16, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR25_VGPR26<imp-use,kill>, %VGPR25_VGPR26<imp-def>
>	%VGPR27<def> = V_ADD_F32_e32 %VGPR16<kill>, %VGPR25, %EXEC<imp-use>, %VGPR27_VGPR28<imp-use,kill>, %VGPR27_VGPR28<imp-def>
>	%VGPR3<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %SGPR38, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR39, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR3<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR11<kill>, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR17<kill>, %VGPR3, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR9_VGPR10<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e32 %SGPR38, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_SUBREV_F32_e32 %SGPR39, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR4<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_MOV_B32_e32 1.899400e-01, %EXEC<imp-use>
>	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR4, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR18_VGPR19<kill>, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR20_SGPR21_SGPR22_SGPR23, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR10<def> = V_MUL_F32_e32 %VGPR9, %VGPR5, %EXEC<imp-use>
>	%VGPR11<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR21_VGPR22<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %SGPR38, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_SUBREV_F32_e32 %SGPR39, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR11<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR4<kill>, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = IMAGE_SAMPLE_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR23_VGPR24<kill>, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31<kill>, %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR10<def> = V_MAD_F32 %VGPR11, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR6_VGPR7<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR6<def> = V_ADD_F32_e64 %VGPR6<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %SGPR38, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_SUBREV_F32_e32 %SGPR39, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_SUB_F32_e32 %VGPR6<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR6<def> = V_ADD_F32_e64 %VGPR6<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR6<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MOV_B32_e32 1.195510e-01, %EXEC<imp-use>
>	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR6, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_MAD_F32 %VGPR11<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = IMAGE_SAMPLE_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 %SGPR38<kill>, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_SUBREV_F32_e32 %SGPR39<kill>, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR14<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR11<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR9<kill>, %VGPR0, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MOV_B32_e32 2.216350e-01, %EXEC<imp-use>
>	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %VGPR9<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_ADD_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_ADD_F32_e32 0.000000e+00, %VGPR5<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_ADD_F32_e32 %VGPR2<kill>, %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 2.216350e-01, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 0.000000e+00, %VGPR7<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR15<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_ADD_F32_e32 %VGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e32 0.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e32 %VGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e32 %VGPR2<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_RCP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
>    Successors according to CFG: BB#2
>
>BB#2: derived from LLVM BB %ENDIF
>    Live Ins: %SGPR2_SGPR3 %VGPR2
>    Predecessors according to CFG: BB#0 BB#1
>	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c8180100
>c8190101
>c8140000
>c8150001
>c08a0304
>c0cc0508
>bf8c007f
>f0800800
>00a60205
>c8100300
>c8110301
>c80c0200
>c80d0201
>c0840300
>c0c60500
>bf8c0070
>f0800100
>00430003
>7e0202ff
>3f733333
>bf8c0770
>d0080002
>02020300
>d2000001
>00098280
>d1040002
>02010101
>be822402
>8982027e
>bf880104
>c0820100
>bf8c007f
>c200050f
>c200850e
>c210050d
>c210850c
>c211050b
>c211850a
>c2120509
>c2128508
>c2130505
>c2138504
>c2140502
>c2148501
>c2020500
>bf8c007f
>7e020224
>7e0e0225
>7e100229
>d206000a
>02020822
>7e160222
>d206000c
>02021622
>061c150c
>d2060009
>02020623
>7e1e0223
>d2060010
>02021e23
>061a1310
>f0800100
>00430d0d
>bf8c0770
>d206010d
>0201010d
>101a1a26
>0a1a1a27
>d206010e
>02010100
>101c1c26
>0a1c1c27
>081a1d0d
>d206010d
>0201010d
>d2060011
>2201010e
>0a242221
>10242400
>d2060812
>02010112
>d2820012
>03ca2401
>10222220
>d2060811
>02010111
>10222312
>d0020000
>02010100
>d2000000
>00021111
>10000028
>10000004
>d00c0000
>0202010d
>7e1002ff
>3d625da8
>d200000d
>00010108
>7e2202ff
>3fc00000
>d2820013
>041a2301
>d2060014
>02020301
>062a2714
>d2820012
>04162307
>d2060011
>02020f07
>06282511
>f0800800
>00a61114
>bf8c0770
>10281b11
>d2080016
>02021704
>d2820018
>0459ea22
>d2080015
>02021f03
>d2820017
>0455ea23
>f0800100
>00430b17
>bf8c0770
>d206010b
>0201010b
>10161626
>0a161627
>08161d0b
>d206010b
>0201010b
>d00c0000
>0202010b
>d2000008
>00010108
>7e1602ff
>bfc00000
>d2820018
>041a1701
>d282001a
>0461eb01
>d2820017
>04161707
>d2820019
>045deb07
>f0800800
>00a60119
>bf8c0770
>d2820005
>04521101
>d2820007
>0411ea22
>d282001a
>041dea22
>d2820006
>040dea23
>d2820019
>0419ea23
>f0800100
>00430b19
>bf8c0770
>d206010b
>0201010b
>10161626
>0a161627
>08161d0b
>d206010b
>0201010b
>d00c0000
>0202010b
>7e1602ff
>3c99b513
>d200000f
>0001010b
>d2820001
>04161f01
>06341904
>0638350c
>06322103
>06363310
>f0800100
>0043031b
>bf8c0770
>d2060103
>02010103
>10060626
>0a060627
>08061d03
>d2060103
>02010103
>d00c0000
>02020103
>d2000003
>0001010b
>d2820001
>04060711
>f0800100
>00430409
>bf8c0770
>d2060104
>02010104
>10080826
>0a080827
>08081d04
>d2060104
>02010104
>d00c0000
>02020104
>7e0802ff
>3e427fa2
>d2000005
>00010104
>f0800800
>00a60912
>bf8c0770
>10140b09
>f0800100
>00430b15
>bf8c0770
>d206010b
>0201010b
>10161626
>0a161627
>08161d0b
>d206010b
>0201010b
>d00c0000
>0202010b
>d2000004
>00010104
>f0800800
>00a60b17
>bf8c0770
>d282000a
>042a090b
>f0800100
>00430606
>bf8c0770
>d2060106
>02010106
>100c0c26
>0a0c0c27
>080c1d06
>d2060106
>02010106
>d00c0000
>02020106
>7e0c02ff
>3df4d728
>d2000007
>00010106
>d282000a
>042a0f0b
>f0800100
>00430b19
>bf8c0770
>d206010b
>0201010b
>10161626
>0a161627
>08161d0b
>d206010b
>0201010b
>d00c0000
>0202010b
>d2000000
>00010106
>d2820006
>042a0109
>7e1202ff
>3e62f449
>d2820002
>041a1302
>06020302
>06040a80
>06041b02
>060808ff
>3e62f449
>06081104
>06040504
>06080e80
>06081f04
>06040902
>06000080
>06000700
>06000102
>7e005500
>10040101
>88fe027e
>d25e0000
>02020480
>d25e0001
>02010080
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	S_WAITCNT 1807
>	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
>	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
>	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020107
>bf8c007f
>7e080204
>c2020105
>bf8c007f
>7e0a0204
>d2820004
>04120b03
>c2020106
>bf8c007f
>7e0a0204
>c2020104
>bf8c007f
>7e0c0204
>d2820005
>04160d02
>c2020103
>bf8c007f
>7e0c0204
>c2020101
>bf8c007f
>7e0e0204
>d2820006
>041a0f03
>c2020102
>bf8c007f
>7e0e0204
>c2000100
>bf8c007f
>7e100200
>d2820007
>041e1102
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL IN[1], GENERIC[20], PERSPECTIVE
>DCL IN[2], GENERIC[21], PERSPECTIVE
>DCL IN[3], GENERIC[22], PERSPECTIVE
>DCL IN[4], GENERIC[23], PERSPECTIVE
>DCL IN[5], GENERIC[24], PERSPECTIVE
>DCL IN[6], GENERIC[25], PERSPECTIVE
>DCL IN[7], GENERIC[26], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL SAMP[4]
>DCL SAMP[5]
>DCL CONST[0..12]
>DCL TEMP[0..7], LOCAL
>IMM[0] FLT32 {    0.0000,     2.0000,    -1.0000,     1.0001}
>IMM[1] FLT32 {   32.0000,   -16.0000,     1.0000, 65504.0000}
>IMM[2] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].x, IN[5].wwww
>  1: MOV TEMP[0].yz, IN[6].yxyy
>  2: MOV TEMP[1].xy, IN[6].zwzz
>  3: MOV TEMP[1].z, IN[7].xxxx
>  4: MOV TEMP[2].xy, IN[4].xyyy
>  5: TEX TEMP[2].xw, TEMP[2], SAMP[1], 2D
>  6: MUL TEMP[2].xy, TEMP[2].wxxx, IN[4].zwww
>  7: RCP TEMP[3].xy, IN[1].wwww
>  8: MUL TEMP[3].xy, IN[0].xyyy, TEMP[3].xyyy
>  9: MOV TEMP[4].xy, IN[2].xyyy
> 10: TEX TEMP[4], TEMP[4], SAMP[2], 2D
> 11: FSLT TEMP[5].x, IMM[0].xxxx, TEMP[4].zzzz
> 12: UIF TEMP[5].xxxx :0
> 13:   MOV TEMP[5].xy, TEMP[4].ywyy
> 14: ELSE :0
> 15:   MOV TEMP[5].xy, TEMP[4].xyxx
> 16: ENDIF
> 17: MOV TEMP[4].xy, TEMP[5].xyxx
> 18: MOV TEMP[5].xy, IN[2].zwww
> 19: TEX TEMP[5], TEMP[5], SAMP[3], 2D
> 20: FSLT TEMP[6].x, IMM[0].xxxx, TEMP[5].zzzz
> 21: UIF TEMP[6].xxxx :0
> 22:   MOV TEMP[6].xy, TEMP[5].ywyy
> 23: ELSE :0
> 24:   MOV TEMP[6].xy, TEMP[5].xyxx
> 25: ENDIF
> 26: MOV TEMP[4].zw, TEMP[6].yyxy
> 27: MOV TEMP[5].xy, IN[3].xyyy
> 28: TEX TEMP[5], TEMP[5], SAMP[4], 2D
> 29: FSLT TEMP[6].x, IMM[0].xxxx, TEMP[5].zzzz
> 30: UIF TEMP[6].xxxx :0
> 31:   MOV TEMP[6].xy, TEMP[5].ywyy
> 32: ELSE :0
> 33:   MOV TEMP[6].xy, TEMP[5].xyxx
> 34: ENDIF
> 35: MOV TEMP[5].xy, TEMP[6].xyxx
> 36: MOV TEMP[6].xy, IN[3].zwww
> 37: TEX TEMP[6], TEMP[6], SAMP[5], 2D
> 38: FSLT TEMP[7].x, IMM[0].xxxx, TEMP[6].zzzz
> 39: UIF TEMP[7].xxxx :0
> 40:   MOV TEMP[7].xy, TEMP[6].ywyy
> 41: ELSE :0
> 42:   MOV TEMP[7].xy, TEMP[6].xyxx
> 43: ENDIF
> 44: MOV TEMP[5].zw, TEMP[7].yyxy
> 45: MAD TEMP[6], TEMP[4], IMM[0].yyyy, IMM[0].zzzz
> 46: MOV TEMP[4], -TEMP[6]
> 47: MAD TEMP[6], TEMP[5], IMM[0].yyyy, IMM[0].zzzz
> 48: MOV TEMP[5], -TEMP[6]
> 49: MUL TEMP[4], TEMP[4], CONST[1].xxyy
> 50: MUL TEMP[5], TEMP[5], CONST[1].zzww
> 51: ADD TEMP[4], TEMP[4], TEMP[5]
> 52: ADD TEMP[4].xy, TEMP[4].xyyy, TEMP[4].zwww
> 53: MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[2].xxxx
> 54: MOV TEMP[5].xy, TEMP[4].xyxx
> 55: DP2 TEMP[6].x, TEMP[4].xyyy, TEMP[4].xyyy
> 56: ADD_SAT TEMP[6].x, IMM[0].wwww, -TEMP[6].xxxx
> 57: RSQ TEMP[7].x, TEMP[6].xxxx
> 58: MUL TEMP[7].x, TEMP[7].xxxx, TEMP[6].xxxx
> 59: CMP TEMP[7].x, -TEMP[6].xxxx, TEMP[7].xxxx, IMM[0].xxxx
> 60: MOV TEMP[5].z, TEMP[7].xxxx
> 61: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
> 62: RSQ TEMP[6].x, TEMP[6].xxxx
> 63: MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx
> 64: ADD TEMP[6].xyz, CONST[12].xyzz, -IN[1].xyzz
> 65: MUL TEMP[7].xyz, IN[5].xyzz, TEMP[5].xxxx
> 66: MAD TEMP[0].xyz, TEMP[0].xyzz, TEMP[5].yyyy, TEMP[7].xyzz
> 67: MAD TEMP[0].xyz, TEMP[1].xyzz, TEMP[5].zzzz, TEMP[0].xyzz
> 68: ADD TEMP[1].xy, TEMP[3].xyyy, TEMP[4].xyyy
> 69: MOV TEMP[1].xy, TEMP[1].xyyy
> 70: MOV TEMP[1].w, CONST[2].zzzz
> 71: TXL TEMP[1], TEMP[1], SAMP[0], 2D
> 72: MAD TEMP[3].x, TEMP[1].wwww, IMM[1].xxxx, IMM[1].yyyy
> 73: EX2 TEMP[3].x, TEMP[3].xxxx
> 74: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[3].xxxx
> 75: MUL TEMP[1].xyz, CONST[0].xyzz, TEMP[1].xyzz
> 76: MOV TEMP[1].w, IMM[1].zzzz
> 77: MUL TEMP[2].x, CONST[0].wwww, TEMP[2].yyyy
> 78: DP3 TEMP[3].x, TEMP[6].xyzz, TEMP[6].xyzz
> 79: RSQ TEMP[3].x, TEMP[3].xxxx
> 80: MUL TEMP[3].xyz, TEMP[6].xyzz, TEMP[3].xxxx
> 81: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz
> 82: RSQ TEMP[4].x, TEMP[4].xxxx
> 83: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx
> 84: DP3_SAT TEMP[0].x, TEMP[3].xyzz, TEMP[0].xyzz
> 85: ADD TEMP[0].x, IMM[1].zzzz, -TEMP[0].xxxx
> 86: POW TEMP[0].x, TEMP[0].xxxx, CONST[2].xxxx
> 87: MUL TEMP[0].x, TEMP[2].xxxx, TEMP[0].xxxx
> 88: MOV TEMP[2].xz, IN[0].zzwz
> 89: MUL TEMP[3].xy, IN[0].zwww, IN[0].zwww
> 90: MAD TEMP[3].xy, IMM[0].yyyy, IN[0].zwww, -TEMP[3].xyyy
> 91: MOV TEMP[2].yw, TEMP[3].yxyy
> 92: MUL TEMP[2], TEMP[2], CONST[5]
> 93: ADD TEMP[0].x, IMM[1].zzzz, -TEMP[0].xxxx
> 94: MUL TEMP[0], CONST[3].zzzw, TEMP[0].xxxx
> 95: LRP TEMP[0], TEMP[0], CONST[3].xxxy, TEMP[1]
> 96: LRP TEMP[0], TEMP[2].zzzw, CONST[7], TEMP[0]
> 97: LRP TEMP[0], TEMP[2].xxxy, CONST[6], TEMP[0]
> 98: MIN TEMP[2].xyz, TEMP[0].xyzz, IMM[1].wwww
> 99: MAX TEMP[1].xyz, TEMP[2].xyzz, IMM[2].xxxx
>100: MAD_SAT TEMP[0].x, TEMP[0].wwww, CONST[4].xxxx, CONST[4].yyyy
>101: MOV TEMP[1].w, TEMP[0].xxxx
>102: MOV OUT[0], TEMP[1]
>103: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 28)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %21, i32 92)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %21, i32 100)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %21, i32 104)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %21, i32 108)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %21, i32 116)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %21, i32 120)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %21, i32 124)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
>  %53 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %54 = load <32 x i8> addrspace(2)* %53, !tbaa !0
>  %55 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
>  %57 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %58 = load <32 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
>  %61 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %62 = load <32 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %64 = load <16 x i8> addrspace(2)* %63, !tbaa !0
>  %65 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
>  %66 = load <32 x i8> addrspace(2)* %65, !tbaa !0
>  %67 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
>  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
>  %69 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
>  %70 = load <32 x i8> addrspace(2)* %69, !tbaa !0
>  %71 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
>  %74 = load <32 x i8> addrspace(2)* %73, !tbaa !0
>  %75 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
>  %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0
>  %77 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %78 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %79 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %80 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %81 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %82 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %83 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
>  %84 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %85 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %86 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %87 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
>  %88 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %89 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %90 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %91 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
>  %92 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %93 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %94 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %95 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
>  %96 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %97 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
>  %98 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
>  %99 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
>  %100 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %3, <2 x i32> %5)
>  %101 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %5)
>  %102 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %5)
>  %103 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %3, <2 x i32> %5)
>  %104 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %3, <2 x i32> %5)
>  %105 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %3, <2 x i32> %5)
>  %106 = bitcast float %93 to i32
>  %107 = bitcast float %94 to i32
>  %108 = insertelement <2 x i32> undef, i32 %106, i32 0
>  %109 = insertelement <2 x i32> %108, i32 %107, i32 1
>  %110 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %109, <32 x i8> %58, <16 x i8> %60, i32 2)
>  %111 = extractelement <4 x float> %110, i32 0
>  %112 = extractelement <4 x float> %110, i32 3
>  %113 = fmul float %112, %95
>  %114 = fmul float %111, %96
>  %115 = fdiv float 1.000000e+00, %84
>  %116 = fmul float %77, %115
>  %117 = fmul float %78, %115
>  %118 = bitcast float %85 to i32
>  %119 = bitcast float %86 to i32
>  %120 = insertelement <2 x i32> undef, i32 %118, i32 0
>  %121 = insertelement <2 x i32> %120, i32 %119, i32 1
>  %122 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %121, <32 x i8> %62, <16 x i8> %64, i32 2)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = extractelement <4 x float> %122, i32 1
>  %125 = extractelement <4 x float> %122, i32 2
>  %126 = extractelement <4 x float> %122, i32 3
>  %127 = fcmp olt float 0.000000e+00, %125
>  %128 = sext i1 %127 to i32
>  %129 = bitcast i32 %128 to float
>  %130 = bitcast float %129 to i32
>  %131 = icmp ne i32 %130, 0
>  %. = select i1 %131, float %124, float %123
>  %.41 = select i1 %131, float %126, float %124
>  %132 = bitcast float %87 to i32
>  %133 = bitcast float %88 to i32
>  %134 = insertelement <2 x i32> undef, i32 %132, i32 0
>  %135 = insertelement <2 x i32> %134, i32 %133, i32 1
>  %136 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %135, <32 x i8> %66, <16 x i8> %68, i32 2)
>  %137 = extractelement <4 x float> %136, i32 0
>  %138 = extractelement <4 x float> %136, i32 1
>  %139 = extractelement <4 x float> %136, i32 2
>  %140 = extractelement <4 x float> %136, i32 3
>  %141 = fcmp olt float 0.000000e+00, %139
>  %142 = sext i1 %141 to i32
>  %143 = bitcast i32 %142 to float
>  %144 = bitcast float %143 to i32
>  %145 = icmp ne i32 %144, 0
>  %temp24.0 = select i1 %145, float %138, float %137
>  %temp25.0 = select i1 %145, float %140, float %138
>  %146 = bitcast float %89 to i32
>  %147 = bitcast float %90 to i32
>  %148 = insertelement <2 x i32> undef, i32 %146, i32 0
>  %149 = insertelement <2 x i32> %148, i32 %147, i32 1
>  %150 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %149, <32 x i8> %70, <16 x i8> %72, i32 2)
>  %151 = extractelement <4 x float> %150, i32 0
>  %152 = extractelement <4 x float> %150, i32 1
>  %153 = extractelement <4 x float> %150, i32 2
>  %154 = extractelement <4 x float> %150, i32 3
>  %155 = fcmp olt float 0.000000e+00, %153
>  %156 = sext i1 %155 to i32
>  %157 = bitcast i32 %156 to float
>  %158 = bitcast float %157 to i32
>  %159 = icmp ne i32 %158, 0
>  %.42 = select i1 %159, float %152, float %151
>  %.43 = select i1 %159, float %154, float %152
>  %160 = bitcast float %91 to i32
>  %161 = bitcast float %92 to i32
>  %162 = insertelement <2 x i32> undef, i32 %160, i32 0
>  %163 = insertelement <2 x i32> %162, i32 %161, i32 1
>  %164 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %163, <32 x i8> %74, <16 x i8> %76, i32 2)
>  %165 = extractelement <4 x float> %164, i32 0
>  %166 = extractelement <4 x float> %164, i32 1
>  %167 = extractelement <4 x float> %164, i32 2
>  %168 = extractelement <4 x float> %164, i32 3
>  %169 = fcmp olt float 0.000000e+00, %167
>  %170 = sext i1 %169 to i32
>  %171 = bitcast i32 %170 to float
>  %172 = bitcast float %171 to i32
>  %173 = icmp ne i32 %172, 0
>  %temp28.0 = select i1 %173, float %166, float %165
>  %temp29.0 = select i1 %173, float %168, float %166
>  %174 = fmul float %., 2.000000e+00
>  %175 = fadd float %174, -1.000000e+00
>  %176 = fmul float %.41, 2.000000e+00
>  %177 = fadd float %176, -1.000000e+00
>  %178 = fmul float %temp24.0, 2.000000e+00
>  %179 = fadd float %178, -1.000000e+00
>  %180 = fmul float %temp25.0, 2.000000e+00
>  %181 = fadd float %180, -1.000000e+00
>  %182 = fsub float -0.000000e+00, %175
>  %183 = fsub float -0.000000e+00, %177
>  %184 = fsub float -0.000000e+00, %179
>  %185 = fsub float -0.000000e+00, %181
>  %186 = fmul float %.42, 2.000000e+00
>  %187 = fadd float %186, -1.000000e+00
>  %188 = fmul float %.43, 2.000000e+00
>  %189 = fadd float %188, -1.000000e+00
>  %190 = fmul float %temp28.0, 2.000000e+00
>  %191 = fadd float %190, -1.000000e+00
>  %192 = fmul float %temp29.0, 2.000000e+00
>  %193 = fadd float %192, -1.000000e+00
>  %194 = fsub float -0.000000e+00, %187
>  %195 = fsub float -0.000000e+00, %189
>  %196 = fsub float -0.000000e+00, %191
>  %197 = fsub float -0.000000e+00, %193
>  %198 = fmul float %182, %26
>  %199 = fmul float %183, %26
>  %200 = fmul float %184, %27
>  %201 = fmul float %185, %27
>  %202 = fmul float %194, %28
>  %203 = fmul float %195, %28
>  %204 = fmul float %196, %29
>  %205 = fmul float %197, %29
>  %206 = fadd float %198, %202
>  %207 = fadd float %199, %203
>  %208 = fadd float %200, %204
>  %209 = fadd float %201, %205
>  %210 = fadd float %206, %208
>  %211 = fadd float %207, %209
>  %212 = fmul float %210, %113
>  %213 = fmul float %211, %113
>  %214 = fmul float %212, %212
>  %215 = fmul float %213, %213
>  %216 = fadd float %214, %215
>  %217 = fsub float -0.000000e+00, %216
>  %218 = fadd float 0x3FF00068E0000000, %217
>  %219 = call float @llvm.AMDIL.clamp.(float %218, float 0.000000e+00, float 1.000000e+00)
>  %220 = call float @llvm.AMDGPU.rsq(float %219)
>  %221 = fmul float %220, %219
>  %222 = fsub float -0.000000e+00, %219
>  %223 = call float @llvm.AMDGPU.cndlt(float %222, float %221, float 0.000000e+00)
>  %224 = fmul float %212, %212
>  %225 = fmul float %213, %213
>  %226 = fadd float %225, %224
>  %227 = fmul float %223, %223
>  %228 = fadd float %226, %227
>  %229 = call float @llvm.AMDGPU.rsq(float %228)
>  %230 = fmul float %212, %229
>  %231 = fmul float %213, %229
>  %232 = fmul float %223, %229
>  %233 = fsub float -0.000000e+00, %81
>  %234 = fadd float %50, %233
>  %235 = fsub float -0.000000e+00, %82
>  %236 = fadd float %51, %235
>  %237 = fsub float -0.000000e+00, %83
>  %238 = fadd float %52, %237
>  %239 = fmul float %97, %230
>  %240 = fmul float %98, %230
>  %241 = fmul float %99, %230
>  %242 = fmul float %100, %231
>  %243 = fadd float %242, %239
>  %244 = fmul float %101, %231
>  %245 = fadd float %244, %240
>  %246 = fmul float %102, %231
>  %247 = fadd float %246, %241
>  %248 = fmul float %103, %232
>  %249 = fadd float %248, %243
>  %250 = fmul float %104, %232
>  %251 = fadd float %250, %245
>  %252 = fmul float %105, %232
>  %253 = fadd float %252, %247
>  %254 = fadd float %116, %212
>  %255 = fadd float %117, %213
>  %256 = bitcast float %254 to i32
>  %257 = bitcast float %255 to i32
>  %258 = bitcast float %31 to i32
>  %259 = insertelement <4 x i32> undef, i32 %256, i32 0
>  %260 = insertelement <4 x i32> %259, i32 %257, i32 1
>  %261 = insertelement <4 x i32> %260, i32 %258, i32 2
>  %262 = insertelement <4 x i32> %261, i32 undef, i32 3
>  %263 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %262, <32 x i8> %54, <16 x i8> %56, i32 2)
>  %264 = extractelement <4 x float> %263, i32 0
>  %265 = extractelement <4 x float> %263, i32 1
>  %266 = extractelement <4 x float> %263, i32 2
>  %267 = extractelement <4 x float> %263, i32 3
>  %268 = fmul float %267, 3.200000e+01
>  %269 = fadd float %268, -1.600000e+01
>  %270 = call float @llvm.AMDIL.exp.(float %269)
>  %271 = fmul float %264, %270
>  %272 = fmul float %265, %270
>  %273 = fmul float %266, %270
>  %274 = fmul float %22, %271
>  %275 = fmul float %23, %272
>  %276 = fmul float %24, %273
>  %277 = fmul float %25, %114
>  %278 = fmul float %234, %234
>  %279 = fmul float %236, %236
>  %280 = fadd float %279, %278
>  %281 = fmul float %238, %238
>  %282 = fadd float %280, %281
>  %283 = call float @llvm.AMDGPU.rsq(float %282)
>  %284 = fmul float %234, %283
>  %285 = fmul float %236, %283
>  %286 = fmul float %238, %283
>  %287 = fmul float %249, %249
>  %288 = fmul float %251, %251
>  %289 = fadd float %288, %287
>  %290 = fmul float %253, %253
>  %291 = fadd float %289, %290
>  %292 = call float @llvm.AMDGPU.rsq(float %291)
>  %293 = fmul float %249, %292
>  %294 = fmul float %251, %292
>  %295 = fmul float %253, %292
>  %296 = fmul float %284, %293
>  %297 = fmul float %285, %294
>  %298 = fadd float %297, %296
>  %299 = fmul float %286, %295
>  %300 = fadd float %298, %299
>  %301 = call float @llvm.AMDIL.clamp.(float %300, float 0.000000e+00, float 1.000000e+00)
>  %302 = fsub float -0.000000e+00, %301
>  %303 = fadd float 1.000000e+00, %302
>  %304 = call float @llvm.pow.f32(float %303, float %30)
>  %305 = fmul float %277, %304
>  %306 = fmul float %79, %79
>  %307 = fmul float %80, %80
>  %308 = fsub float -0.000000e+00, %306
>  %309 = fmul float 2.000000e+00, %79
>  %310 = fadd float %309, %308
>  %311 = fsub float -0.000000e+00, %307
>  %312 = fmul float 2.000000e+00, %80
>  %313 = fadd float %312, %311
>  %314 = fmul float %79, %38
>  %315 = fmul float %310, %39
>  %316 = fmul float %80, %40
>  %317 = fmul float %313, %41
>  %318 = fsub float -0.000000e+00, %305
>  %319 = fadd float 1.000000e+00, %318
>  %320 = fmul float %34, %319
>  %321 = fmul float %34, %319
>  %322 = fmul float %34, %319
>  %323 = fmul float %35, %319
>  %324 = call float @llvm.AMDGPU.lrp(float %320, float %32, float %274)
>  %325 = call float @llvm.AMDGPU.lrp(float %321, float %32, float %275)
>  %326 = call float @llvm.AMDGPU.lrp(float %322, float %32, float %276)
>  %327 = call float @llvm.AMDGPU.lrp(float %323, float %33, float 1.000000e+00)
>  %328 = call float @llvm.AMDGPU.lrp(float %316, float %46, float %324)
>  %329 = call float @llvm.AMDGPU.lrp(float %316, float %47, float %325)
>  %330 = call float @llvm.AMDGPU.lrp(float %316, float %48, float %326)
>  %331 = call float @llvm.AMDGPU.lrp(float %317, float %49, float %327)
>  %332 = call float @llvm.AMDGPU.lrp(float %314, float %42, float %328)
>  %333 = call float @llvm.AMDGPU.lrp(float %314, float %43, float %329)
>  %334 = call float @llvm.AMDGPU.lrp(float %314, float %44, float %330)
>  %335 = call float @llvm.AMDGPU.lrp(float %315, float %45, float %331)
>  %336 = fcmp uge float %332, 6.550400e+04
>  %337 = select i1 %336, float 6.550400e+04, float %332
>  %338 = fcmp uge float %333, 6.550400e+04
>  %339 = select i1 %338, float 6.550400e+04, float %333
>  %340 = fcmp uge float %334, 6.550400e+04
>  %341 = select i1 %340, float 6.550400e+04, float %334
>  %342 = fcmp uge float %337, 0x3E6FFFFE60000000
>  %343 = select i1 %342, float %337, float 0x3E6FFFFE60000000
>  %344 = fcmp uge float %339, 0x3E6FFFFE60000000
>  %345 = select i1 %344, float %339, float 0x3E6FFFFE60000000
>  %346 = fcmp uge float %341, 0x3E6FFFFE60000000
>  %347 = select i1 %346, float %341, float 0x3E6FFFFE60000000
>  %348 = fmul float %335, %36
>  %349 = fadd float %348, %37
>  %350 = call float @llvm.AMDIL.clamp.(float %349, float 0.000000e+00, float 1.000000e+00)
>  %351 = call i32 @llvm.SI.packf16(float %343, float %345)
>  %352 = bitcast i32 %351 to float
>  %353 = call i32 @llvm.SI.packf16(float %347, float %350)
>  %354 = bitcast i32 %353 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %352, float %354, float %352, float %354)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #2
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.lrp(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
>	%EXEC<def> = S_WQM_B64 %EXEC
>	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
>	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
>	%M0<def> = S_MOV_B32 %SGPR6
>	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
>	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 3, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 20; mem:LD16[%88](align=8)(tbaa=!"const")
>	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 40; mem:LD32[%85](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR8_SGPR9<def> = V_CMP_GT_F32_e64 %VGPR4, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR3, %SGPR8_SGPR9, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_ADD_F32_e32 %VGPR6<kill>, %VGPR6, %EXEC<imp-use>
>	%VGPR6<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR6<kill>, %EXEC<imp-use>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MUL_F32_e32 %SGPR0, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
>	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
>	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
>	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
>	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 12; mem:LD16[%76](align=8)(tbaa=!"const")
>	%SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 24; mem:LD32[%73](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR7_VGPR8_VGPR9_VGPR10<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8<kill>, %SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27<kill>, %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR10_SGPR11<def> = V_CMP_GT_F32_e64 %VGPR9, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_CNDMASK_B32_e64 %VGPR7, %VGPR8, %SGPR10_SGPR11, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_ADD_F32_e32 %VGPR11<kill>, %VGPR11, %EXEC<imp-use>
>	%VGPR11<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR11<def> = V_MUL_F32_e32 %SGPR1, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR11_VGPR12<imp-def>
>	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<tied0>, %VGPR1, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR11_VGPR12<imp-use,kill>, %VGPR11_VGPR12<imp-def>
>	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR11_VGPR12<imp-use,kill>, %VGPR11_VGPR12<imp-def>
>	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<tied0>, %VGPR1, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR11_VGPR12<imp-use,kill>, %VGPR11_VGPR12<imp-def>
>	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 16; mem:LD16[%82](align=8)(tbaa=!"const")
>	%SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 32; mem:LD32[%79](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR11_VGPR12_VGPR13_VGPR14<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR11_VGPR12<kill>, %SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27<kill>, %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR16_SGPR17<def> = V_CMP_GT_F32_e64 %VGPR13, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_CNDMASK_B32_e64 %VGPR11, %VGPR12, %SGPR16_SGPR17, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_ADD_F32_e32 %VGPR15<kill>, %VGPR15, %EXEC<imp-use>
>	%VGPR15<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR15<kill>, %EXEC<imp-use>
>	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR15<def> = V_MUL_F32_e32 %SGPR7, %VGPR15<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-def>
>	%VGPR17<def,tied1> = V_INTERP_P2_F32 %VGPR17<tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-use,kill>, %VGPR16_VGPR17<imp-def>
>	%VGPR16<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-use,kill>, %VGPR16_VGPR17<imp-def>
>	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-use,kill>, %VGPR16_VGPR17<imp-def>
>	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%70](align=8)(tbaa=!"const")
>	%SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%67](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR16_VGPR17_VGPR18_VGPR19<def> = IMAGE_SAMPLE_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR16_VGPR17<kill>, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31<kill>, %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%SGPR18_SGPR19<def> = V_CMP_GT_F32_e64 %VGPR18, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR20<def> = V_CNDMASK_B32_e64 %VGPR16, %VGPR17, %SGPR18_SGPR19, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR20<def> = V_ADD_F32_e32 %VGPR20<kill>, %VGPR20, %EXEC<imp-use>
>	%VGPR20<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR20<kill>, %EXEC<imp-use>
>	%VGPR20<def> = V_ADD_F32_e64 %VGPR20<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR20<def> = V_MUL_F32_e32 %SGPR20, %VGPR20<kill>, %EXEC<imp-use>
>	%VGPR15<def> = V_SUB_F32_e32 %VGPR20<kill>, %VGPR15<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_ADD_F32_e32 %VGPR15<kill>, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR21<def> = V_INTERP_P1_F32 %VGPR0, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-def>
>	%VGPR21<def,tied1> = V_INTERP_P2_F32 %VGPR21<tied0>, %VGPR1, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
>	%VGPR20<def> = V_INTERP_P1_F32 %VGPR0, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
>	%VGPR20<def,tied1> = V_INTERP_P2_F32 %VGPR20<tied0>, %VGPR1, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
>	%SGPR24_SGPR25_SGPR26_SGPR27<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%64](align=8)(tbaa=!"const")
>	%SGPR28_SGPR29_SGPR30_SGPR31_SGPR32_SGPR33_SGPR34_SGPR35<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%61](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR20_VGPR21<def> = IMAGE_SAMPLE_V2 9, 0, 0, 0, 0, 0, 0, 0, %VGPR20_VGPR21<kill>, %SGPR28_SGPR29_SGPR30_SGPR31_SGPR32_SGPR33_SGPR34_SGPR35<kill>, %SGPR24_SGPR25_SGPR26_SGPR27<kill>, %EXEC<imp-use>
>	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
>	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR15<def> = V_MUL_F32_e32 %VGPR21, %VGPR15<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR15, %EXEC<imp-use>
>	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR3, %VGPR5, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
>	%VGPR2<def> = V_ADD_F32_e32 %VGPR2<kill>, %VGPR2, %EXEC<imp-use>
>	%VGPR2<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR8, %VGPR10, %SGPR10_SGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9_VGPR10<imp-use,kill>
>	%VGPR3<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR12, %VGPR14, %SGPR16_SGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR11_VGPR12_VGPR13_VGPR14<imp-use,kill>
>	%VGPR3<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR17, %VGPR19, %SGPR18_SGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR16_VGPR17_VGPR18_VGPR19<imp-use,kill>
>	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR4, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e32 %SGPR20<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR15<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %VGPR2, %VGPR2, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR6, %VGPR6, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_SUB_F32_e32 1.000100e+00, %VGPR3, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_RSQ_LEGACY_F32_e32 %VGPR4, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR4, %EXEC<imp-use>
>	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GT_F32_e64 0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR5<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR4, %VGPR4, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_RSQ_LEGACY_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR6, %VGPR3, %EXEC<imp-use>
>	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 5, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 5, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR7, %EXEC<imp-use>
>	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 6, %M0<kill>, %EXEC<imp-use>
>	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 6, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR9<kill>, %VGPR5, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 3, 6, %M0<kill>, %EXEC<imp-use>
>	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 3, 6, %M0<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR4<kill>, %VGPR3, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 0, 5, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 0, 5, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR7, %EXEC<imp-use>
>	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 3, 5, %M0<kill>, %EXEC<imp-use>
>	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 3, 5, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR9<kill>, %VGPR5, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 2, 6, %M0<kill>, %EXEC<imp-use>
>	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 2, 6, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR9<kill>, %VGPR3, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e32 %VGPR8, %VGPR8, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR4, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 2, 5, %M0<kill>, %EXEC<imp-use>
>	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 2, 5, %M0<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR7<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 1, 6, %M0<kill>, %EXEC<imp-use>
>	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 1, 6, %M0<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR10<kill>, %VGPR5<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 0, 7, %M0<kill>, %EXEC<imp-use>
>	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 0, 7, %M0<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR7<kill>, %VGPR3<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR3, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_RSQ_LEGACY_F32_e32 %VGPR5<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR5, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR5, %EXEC<imp-use>
>	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 49; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 48; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_MUL_F32_e32 %VGPR9, %VGPR9, %EXEC<imp-use>
>	%VGPR10<def> = V_MAD_F32 %VGPR8, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 2, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 2, 1, %M0<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 50; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR11<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR11<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_RSQ_LEGACY_F32_e32 %VGPR10<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR10, %EXEC<imp-use>
>	%VGPR7<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR7<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR10, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR8<kill>, %VGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR5<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR10<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %VGPR5<kill>, %VGPR3<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_LOG_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR3<def> = V_MUL_LEGACY_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_EXP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 3, 4, %M0<kill>, %EXEC<imp-use>
>	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 3, 4, %M0<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MUL_F32_e32 %VGPR20, %VGPR4<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
>	%VGPR5<def> = V_SUB_F32_e32 1.000000e+00, %VGPR4, %EXEC<imp-use>
>	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_RCP_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_MAD_F32 %VGPR7<kill>, %VGPR8, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
>	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR2<kill>, %VGPR8<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR11<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%58](align=8)(tbaa=!"const")
>	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%55](tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR6_VGPR7_VGPR8_VGPR9<def> = IMAGE_SAMPLE_L_V4 15, 0, 0, 0, 0, 0, 0, 0, %VGPR9_VGPR10_VGPR11_VGPR12<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MOV_B32_e32 -1.600000e+01, %EXEC<imp-use>
>	%VGPR10<def> = V_MOV_B32_e32 3.200000e+01, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR2<def> = V_MAD_F32 %VGPR9, %VGPR10<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_EXP_F32_e32 %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_MUL_F32_e32 %VGPR7, %VGPR2, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR10<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_MUL_F32_e32 %VGPR5, %VGPR10<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR10<def> = V_MAD_F32 %VGPR4, %SGPR0, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR12<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR11, %EXEC<imp-use>
>	%VGPR13<def> = V_SUB_F32_e32 1.000000e+00, %VGPR12, %EXEC<imp-use>
>	%VGPR10<def> = V_MUL_F32_e32 %VGPR13, %VGPR10<kill>, %EXEC<imp-use>
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR10<def> = V_MAD_F32 %VGPR12, %SGPR1<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
>	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR1<def> = V_SUB_F32_e32 1.000000e+00, %VGPR0, %EXEC<imp-use>
>	%VGPR10<def> = V_MUL_F32_e32 %VGPR1, %VGPR10<kill>, %EXEC<imp-use>
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR10<def> = V_MAD_F32 %VGPR0, %SGPR1<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_MOV_B32_e32 6.550400e+04, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR10, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_CNDMASK_B32_e64 %VGPR10<kill>, %VGPR15, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR16<def> = V_MOV_B32_e32 5.960460e-08, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR10, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_CNDMASK_B32_e64 %VGPR16, %VGPR10<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_MUL_F32_e32 %VGPR6, %VGPR2, %EXEC<imp-use>
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR17<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR17<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_MUL_F32_e32 %VGPR5, %VGPR17<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_MAD_F32 %VGPR4, %SGPR0, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_MUL_F32_e32 %VGPR13, %VGPR17<kill>, %EXEC<imp-use>
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR17<def> = V_MAD_F32 %VGPR12, %SGPR1<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_MUL_F32_e32 %VGPR1, %VGPR17<kill>, %EXEC<imp-use>
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR17<def> = V_MAD_F32 %VGPR0, %SGPR1<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR17, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_CNDMASK_B32_e64 %VGPR17<kill>, %VGPR15, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR17, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_CNDMASK_B32_e64 %VGPR16, %VGPR17<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR17<kill>, %VGPR10<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR8, %VGPR2<kill>, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MAD_F32 %VGPR12<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR15<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR16<kill>, %VGPR0<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_SUB_F32_e32 1.000000e+00, %VGPR1, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR11, %VGPR11, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e32 %VGPR11<kill>, %VGPR11, %EXEC<imp-use>
>	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR2, %EXEC<imp-use>
>	%VGPR1<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR1<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR14, %VGPR14, %EXEC<imp-use>
>	%VGPR3<def> = V_ADD_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>
>	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR2, %EXEC<imp-use>
>	%VGPR1<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR1<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16; mem:LD4[<unknown>]
>	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 17; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR2<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR1<def> = V_ADD_F32_e64 %VGPR1<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	EXP 15, 0, 1, 1, 1, %VGPR10<kill>, %VGPR0<kill>, %VGPR10, %VGPR0, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>befe0a7e
>befc0306
>c80c0f00
>c80d0f01
>c8080e00
>c8090e01
>c0840314
>c0c60528
>bf8c007f
>f0800f00
>00430202
>bf8c0770
>d0080008
>02010104
>d2000006
>00220702
>060c0d06
>060c0cf3
>c0860100
>bf8c007f
>c2000d07
>bf8c007f
>100c0c00
>c8200b00
>c8210b01
>c81c0a00
>c81d0a01
>c088030c
>c0ca0518
>bf8c007f
>f0800f00
>00850707
>bf8c0770
>d008000a
>02010109
>d200000b
>002a1107
>0616170b
>061616f3
>d206000b
>2201010b
>c2008d05
>bf8c007f
>10161601
>080c0d0b
>c8300d00
>c8310d01
>c82c0c00
>c82d0c01
>c0880310
>c0ca0520
>bf8c007f
>f0800f00
>00850b0b
>bf8c0770
>d0080010
>0201010d
>d200000f
>0042190b
>061e1f0f
>061e1ef3
>c2038d06
>bf8c007f
>101e1e07
>c8440900
>c8450901
>c8400800
>c8410801
>c08a0308
>c0cc0510
>bf8c007f
>f0800f00
>00a61010
>bf8c0770
>d0080012
>02010112
>d2000014
>004a2310
>06282914
>062828f3
>d2060014
>22010114
>c20a0d04
>bf8c007f
>10282814
>081e1f14
>060c0d0f
>c8541100
>c8551101
>c8501000
>c8511001
>c08c0304
>c0ce0508
>bf8c007f
>f0800900
>00c71414
>c83c1200
>c83d1201
>bf8c0770
>101e1f15
>100c1f06
>d2000002
>00220b03
>06040502
>060404f3
>10040400
>d2000003
>002a1508
>06060703
>060606f3
>d2060003
>22010103
>10060601
>08040503
>d2000003
>00421d0c
>06060703
>060606f3
>10060607
>d2000004
>004a2711
>06080904
>060808f3
>d2060004
>22010104
>10080814
>08060704
>06040503
>10041f02
>10060502
>d2820003
>040e0d06
>080806ff
>3f800347
>d2060804
>02010104
>7e0a5b04
>100a0905
>d2060004
>22010104
>d0080000
>02020880
>d2000004
>00020a80
>d2820003
>040e0904
>7e065b03
>100a0702
>100e0706
>c8201500
>c8211501
>10100f08
>c8241800
>c8251801
>d2820008
>04220b09
>10060704
>c8101b00
>c8111b01
>d2820004
>04220704
>c8201400
>c8211401
>10100f08
>c8241700
>c8251701
>d2820008
>04220b09
>c8241a00
>c8251a01
>d2820008
>04220709
>10121108
>d2820009
>04260904
>c8281600
>c8291601
>100e0f0a
>c8281900
>c8291901
>d2820005
>041e0b0a
>c81c1c00
>c81d1c01
>d2820003
>04160707
>d2820005
>04260703
>7e0a5b05
>10080b04
>100e0b08
>c8200500
>c8210501
>c2000d31
>bf8c007f
>08101000
>c8240400
>c8250401
>c2000d30
>bf8c007f
>08121200
>10141309
>d282000a
>042a1108
>c82c0600
>c82d0601
>c2000d32
>bf8c007f
>08161600
>d282000a
>042a170b
>7e145b0a
>10121509
>100e0f09
>10101508
>d2820004
>041e0908
>10060b03
>100a150b
>d2820003
>04120705
>d2060803
>02010103
>080606f2
>7e064f03
>c2000d08
>bf8c007f
>0e060600
>7e064b03
>c8101300
>c8111301
>10080914
>c2000d03
>bf8c007f
>10080800
>10060704
>080606f2
>c2000d0e
>bf8c007f
>10080600
>080a08f2
>c81c0100
>c81d0101
>c8200700
>c8210701
>7e105508
>d282000a
>040a1107
>c8080000
>c8090001
>d2820009
>041a1102
>c2000d0a
>bf8c007f
>7e160200
>c0800300
>c0c80500
>bf8c007f
>f0900f00
>00040609
>7e0402ff
>c1800000
>7e1402ff
>42000000
>bf8c0770
>d2820002
>040a1509
>7e044b02
>10140507
>c2000d01
>bf8c007f
>10141400
>10141505
>c2000d0c
>bf8c007f
>d282000a
>04280104
>c82c0300
>c82d0301
>c2008d16
>bf8c007f
>10181601
>081a18f2
>1014150d
>c2008d1d
>bf8c007f
>d282000a
>0428030c
>c8380200
>c8390201
>c2008d14
>bf8c007f
>10001c01
>080200f2
>10141501
>c2008d19
>bf8c007f
>d282000a
>04280300
>7e1e02ff
>477fe000
>d00c0002
>02021f0a
>d200000a
>000a1f0a
>7e2002ff
>337ffff3
>d00c0002
>0202210a
>d200000a
>000a1510
>10220506
>c2008d00
>bf8c007f
>10222201
>10222305
>d2820011
>04440104
>1022230d
>c2008d1c
>bf8c007f
>d2820011
>0444030c
>10222301
>c2008d18
>bf8c007f
>d2820011
>04440300
>d00c0002
>02021f11
>d2000011
>000a1f11
>d00c0002
>02022111
>d2000011
>000a2310
>5e141511
>10040508
>c2008d02
>bf8c007f
>10040401
>10040505
>d2820002
>04080104
>1004050d
>c2000d1e
>bf8c007f
>d2820002
>0408010c
>10020501
>c2000d1a
>bf8c007f
>d2820000
>04040100
>d00c0000
>02021f00
>d2000000
>00021f00
>d00c0000
>02022100
>d2000000
>00020110
>c2000d0f
>bf8c007f
>10020600
>080402f2
>c2000d0d
>bf8c007f
>d2820001
>04080101
>1004170b
>0606170b
>08040503
>c2000d17
>bf8c007f
>10040400
>080604f2
>10020303
>c2000d1f
>bf8c007f
>d2820001
>04040102
>10041d0e
>06061d0e
>08040503
>c2000d15
>bf8c007f
>10040400
>080604f2
>10020303
>c2000d1b
>bf8c007f
>d2820001
>04040102
>c2000d10
>c2008d11
>bf8c007f
>7e040201
>d2820001
>04080101
>d2060801
>02010101
>5e000300
>f8001c0f
>000a000a
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL IN[6]
>DCL IN[7]
>DCL IN[8]
>DCL OUT[0], POSITION
>DCL OUT[1], CLIPVERTEX
>DCL OUT[2], GENERIC[19]
>DCL OUT[3], GENERIC[20]
>DCL OUT[4], GENERIC[21]
>DCL OUT[5], GENERIC[22]
>DCL OUT[6], GENERIC[23]
>DCL OUT[7], GENERIC[24]
>DCL OUT[8], GENERIC[25]
>DCL OUT[9], GENERIC[26]
>DCL CONST[0..22]
>DCL TEMP[0..15], LOCAL
>IMM[0] FLT32 {    0.5000,     0.0010,     0.0000,     1.0000}
>IMM[1] FLT32 {    0.0001,     1.4427,     0.0000,     0.0000}
>  0: DP4 TEMP[0].x, IN[0], CONST[0]
>  1: DP4 TEMP[1].x, IN[0], CONST[1]
>  2: MOV TEMP[0].y, TEMP[1].xxxx
>  3: DP4 TEMP[1].x, IN[0], CONST[2]
>  4: MOV TEMP[0].z, TEMP[1].xxxx
>  5: DP4 TEMP[1].x, IN[0], CONST[3]
>  6: MOV TEMP[0].w, TEMP[1].xxxx
>  7: MUL TEMP[2].xy, TEMP[0].xyyy, IMM[0].xxxx
>  8: MAD TEMP[2].xy, TEMP[1].xxxx, IMM[0].xxxx, TEMP[2].xyyy
>  9: DP4 TEMP[3].x, IN[0], CONST[4]
> 10: DP4 TEMP[4].x, IN[0], CONST[5]
> 11: MOV TEMP[3].y, TEMP[4].xxxx
> 12: DP4 TEMP[4].x, IN[0], CONST[6]
> 13: MOV TEMP[3].z, TEMP[4].xxxx
> 14: MOV TEMP[4].xyz, TEMP[3].xyzx
> 15: MOV TEMP[4].w, TEMP[1].xxxx
> 16: DP4 TEMP[1].x, IN[4], CONST[14]
> 17: DP4 TEMP[5].x, IN[4], CONST[15]
> 18: MOV TEMP[1].y, TEMP[5].xxxx
> 19: MOV TEMP[1].xy, TEMP[1].xyxx
> 20: DP4 TEMP[5].x, IN[5], CONST[16]
> 21: DP4 TEMP[6].x, IN[5], CONST[17]
> 22: MOV TEMP[5].y, TEMP[6].xxxx
> 23: MOV TEMP[1].zw, TEMP[5].yyxy
> 24: DP4 TEMP[5].x, IN[6], CONST[18]
> 25: DP4 TEMP[6].x, IN[6], CONST[19]
> 26: MOV TEMP[5].y, TEMP[6].xxxx
> 27: MOV TEMP[5].xy, TEMP[5].xyxx
> 28: DP4 TEMP[6].x, IN[7], CONST[20]
> 29: DP4 TEMP[7].x, IN[7], CONST[21]
> 30: MOV TEMP[6].y, TEMP[7].xxxx
> 31: MOV TEMP[5].zw, TEMP[6].yyxy
> 32: MAD TEMP[6].xy, IN[3].xyyy, CONST[7].xxxx, CONST[7].yyyy
> 33: MOV TEMP[6].zw, TEMP[6].yyxy
> 34: MOV TEMP[6].xy, IN[8].xyxx
> 35: MAD TEMP[7].xyz, IN[1].xyzz, CONST[22].xxxx, CONST[22].yyyy
> 36: MOV TEMP[8].xz, TEMP[7].xxzx
> 37: ADD TEMP[9].x, TEMP[7].yyyy, IMM[0].yyyy
> 38: MOV TEMP[8].y, TEMP[9].xxxx
> 39: MAD TEMP[10], IN[2], CONST[22].zzzz, CONST[22].wwww
> 40: MOV TEMP[11].yz, TEMP[10].zyzw
> 41: ADD TEMP[11].x, TEMP[10].xxxx, IMM[0].yyyy
> 42: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[10].wwww
> 43: MUL TEMP[12].xyz, TEMP[8].zxyy, TEMP[11].yzxx
> 44: MAD TEMP[8].xyz, TEMP[8].yzxx, TEMP[11].zxyy, -TEMP[12].xyzz
> 45: MOV TEMP[12].x, CONST[4].xxxx
> 46: MOV TEMP[13].x, CONST[4].yyyy
> 47: MOV TEMP[14].x, CONST[4].zzzz
> 48: MOV TEMP[12].y, CONST[5].xxxx
> 49: MOV TEMP[13].y, CONST[5].yyyy
> 50: MOV TEMP[14].y, CONST[5].zzzz
> 51: MOV TEMP[12].z, CONST[6].xxxx
> 52: MOV TEMP[13].z, CONST[6].yyyy
> 53: MOV TEMP[14].z, CONST[6].zzzz
> 54: DP3 TEMP[15].x, TEMP[12].xyzz, TEMP[12].xyzz
> 55: RCP TEMP[15].x, TEMP[15].xxxx
> 56: MUL TEMP[12].xyz, TEMP[12].xyzz, TEMP[15].xxxx
> 57: DP3 TEMP[15].x, TEMP[13].xyzz, TEMP[13].xyzz
> 58: RCP TEMP[15].x, TEMP[15].xxxx
> 59: MUL TEMP[13].xyz, TEMP[13].xyzz, TEMP[15].xxxx
> 60: DP3 TEMP[15].x, TEMP[14].xyzz, TEMP[14].xyzz
> 61: RCP TEMP[15].x, TEMP[15].xxxx
> 62: MUL TEMP[14].xyz, TEMP[14].xyzz, TEMP[15].xxxx
> 63: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[11].xxxx
> 64: MAD TEMP[11].xyz, TEMP[13].xyzz, TEMP[10].yyyy, TEMP[11].xyzz
> 65: MAD TEMP[10].xyz, TEMP[14].xyzz, TEMP[10].zzzz, TEMP[11].xyzz
> 66: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[8].xxxx
> 67: MAD TEMP[11].xyz, TEMP[13].xyzz, TEMP[8].yyyy, TEMP[11].xyzz
> 68: MAD TEMP[8].xyz, TEMP[14].xyzz, TEMP[8].zzzz, TEMP[11].xyzz
> 69: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[7].xxxx
> 70: MAD TEMP[9].xyz, TEMP[13].xyzz, TEMP[9].xxxx, TEMP[11].xyzz
> 71: MAD TEMP[7].xyz, TEMP[14].xyzz, TEMP[7].zzzz, TEMP[9].xyzz
> 72: DP3 TEMP[9].x, TEMP[10].xyzz, TEMP[10].xyzz
> 73: RSQ TEMP[9].x, TEMP[9].xxxx
> 74: MUL TEMP[9].xyz, TEMP[10].xyzz, TEMP[9].xxxx
> 75: DP3 TEMP[10].x, TEMP[8].xyzz, TEMP[8].xyzz
> 76: RSQ TEMP[10].x, TEMP[10].xxxx
> 77: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[10].xxxx
> 78: DP3 TEMP[10].x, TEMP[7].xyzz, TEMP[7].xyzz
> 79: RSQ TEMP[10].x, TEMP[10].xxxx
> 80: MUL TEMP[7].xyz, TEMP[7].xyzz, TEMP[10].xxxx
> 81: ADD TEMP[10].xyz, TEMP[3].xyzz, -CONST[8].xyzz
> 82: DP3 TEMP[11].x, TEMP[10].xyzz, TEMP[10].xyzz
> 83: RSQ TEMP[12].x, TEMP[11].xxxx
> 84: MUL TEMP[12].x, TEMP[12].xxxx, TEMP[11].xxxx
> 85: CMP TEMP[11].x, -TEMP[11].xxxx, TEMP[12].xxxx, IMM[0].zzzz
> 86: MOV TEMP[12].w, IMM[0].wwww
> 87: MOV TEMP[12].xyz, TEMP[3].xyzx
> 88: MOV TEMP[3].x, IMM[0].zzzz
> 89: FSLT TEMP[13].x, IMM[0].zzzz, CONST[10].xxxx
> 90: UIF TEMP[13].xxxx :0
> 91:   DP4 TEMP[12].x, TEMP[12], CONST[12]
> 92:   MOV TEMP[13].x, TEMP[12].xxxx
> 93:   DP4 TEMP[14].x, CONST[8], CONST[12]
> 94:   MOV TEMP[13].y, TEMP[14].xxxx
> 95:   ADD TEMP[12].x, TEMP[12].xxxx, -TEMP[14].xxxx
> 96:   FSGE TEMP[14].x, TEMP[12].xxxx, IMM[0].zzzz
> 97:   UIF TEMP[14].xxxx :0
> 98:     MOV TEMP[14].xy, TEMP[13].yxyy
> 99:   ELSE :0
>100:     MOV TEMP[14].xy, TEMP[13].xyxx
>101:   ENDIF
>102:   ADD TEMP[13].xy, TEMP[14].xyyy, -CONST[11].xxxx
>103:   ADD TEMP[14].xy, CONST[11].zwww, -TEMP[13].xxxx
>104:   ABS TEMP[12].x, TEMP[12].xxxx
>105:   ADD TEMP[12].x, TEMP[12].xxxx, IMM[0].yyyy
>106:   RCP TEMP[12].x, TEMP[12].xxxx
>107:   MUL_SAT TEMP[12].xy, TEMP[14].xyyy, TEMP[12].xxxx
>108:   MUL TEMP[13].xy, TEMP[13].xyyy, CONST[10].yyyy
>109:   ADD_SAT TEMP[13].xy, IMM[0].wwww, -TEMP[13].xyyy
>110:   MUL TEMP[14].x, TEMP[11].xxxx, CONST[10].xxxx
>111:   ADD_SAT TEMP[12].x, TEMP[12].xxxx, -TEMP[12].yyyy
>112:   ADD TEMP[13].x, TEMP[13].xxxx, TEMP[13].yyyy
>113:   MUL_SAT TEMP[13].x, TEMP[13].xxxx, CONST[11].yyyy
>114:   MUL TEMP[12].x, TEMP[12].xxxx, TEMP[13].xxxx
>115:   MUL_SAT TEMP[12].x, TEMP[14].xxxx, TEMP[12].xxxx
>116:   MOV TEMP[3].x, TEMP[12].xxxx
>117: ENDIF
>118: MOV TEMP[2].z, TEMP[3].xxxx
>119: MOV TEMP[3].x, TEMP[10].yyyy
>120: MOV TEMP[12].x, IMM[0].zzzz
>121: FSLT TEMP[13].x, IMM[0].zzzz, CONST[13].xxxx
>122: UIF TEMP[13].xxxx :0
>123:   MUL_SAT TEMP[13].x, TEMP[11].xxxx, IMM[1].xxxx
>124:   MUL TEMP[13].x, CONST[13].wwww, TEMP[13].xxxx
>125:   ADD TEMP[13].x, IMM[0].wwww, -TEMP[13].xxxx
>126:   MUL TEMP[3].x, TEMP[10].yyyy, TEMP[13].xxxx
>127:   MUL TEMP[3].x, TEMP[3].xxxx, CONST[13].yyyy
>128:   ADD_SAT TEMP[3].x, IMM[0].wwww, -TEMP[3].xxxx
>129:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx
>130:   ADD TEMP[10].x, TEMP[11].xxxx, -CONST[13].zzzz
>131:   MUL TEMP[10].x, -CONST[13].xxxx, TEMP[10].xxxx
>132:   MUL TEMP[10].x, TEMP[10].xxxx, IMM[1].yyyy
>133:   EX2 TEMP[10].x, TEMP[10].xxxx
>134:   ADD_SAT TEMP[10].x, IMM[0].wwww, -TEMP[10].xxxx
>135:   MUL TEMP[12].x, TEMP[10].xxxx, TEMP[3].xxxx
>136: ENDIF
>137: MOV TEMP[2].w, TEMP[12].xxxx
>138: MOV TEMP[3].xyz, TEMP[9].xyzx
>139: MOV TEMP[3].w, TEMP[8].xxxx
>140: MOV TEMP[8].xy, TEMP[8].yzyy
>141: MOV TEMP[8].zw, TEMP[7].yyxy
>142: MOV TEMP[7].x, TEMP[7].zzzz
>143: MOV OUT[6], TEMP[6]
>144: MOV OUT[5], TEMP[5]
>145: MOV OUT[9], TEMP[7]
>146: MOV OUT[3], TEMP[4]
>147: MOV OUT[2], TEMP[2]
>148: MOV OUT[8], TEMP[8]
>149: MOV OUT[7], TEMP[3]
>150: MOV OUT[0], TEMP[0]
>151: MOV OUT[4], TEMP[1]
>152: MOV OUT[1], TEMP[0]
>153: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 252)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 268)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 284)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 300)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %95 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %96 = load <16 x i8> addrspace(2)* %95, !tbaa !0
>  %97 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %96, i32 0, i32 %5)
>  %98 = extractelement <4 x float> %97, i32 0
>  %99 = extractelement <4 x float> %97, i32 1
>  %100 = extractelement <4 x float> %97, i32 2
>  %101 = extractelement <4 x float> %97, i32 3
>  %102 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %103 = load <16 x i8> addrspace(2)* %102, !tbaa !0
>  %104 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %103, i32 0, i32 %5)
>  %105 = extractelement <4 x float> %104, i32 0
>  %106 = extractelement <4 x float> %104, i32 1
>  %107 = extractelement <4 x float> %104, i32 2
>  %108 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %109 = load <16 x i8> addrspace(2)* %108, !tbaa !0
>  %110 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %109, i32 0, i32 %5)
>  %111 = extractelement <4 x float> %110, i32 0
>  %112 = extractelement <4 x float> %110, i32 1
>  %113 = extractelement <4 x float> %110, i32 2
>  %114 = extractelement <4 x float> %110, i32 3
>  %115 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %116 = load <16 x i8> addrspace(2)* %115, !tbaa !0
>  %117 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %116, i32 0, i32 %5)
>  %118 = extractelement <4 x float> %117, i32 0
>  %119 = extractelement <4 x float> %117, i32 1
>  %120 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
>  %122 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %121, i32 0, i32 %5)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = extractelement <4 x float> %122, i32 1
>  %125 = extractelement <4 x float> %122, i32 2
>  %126 = extractelement <4 x float> %122, i32 3
>  %127 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %128 = load <16 x i8> addrspace(2)* %127, !tbaa !0
>  %129 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %128, i32 0, i32 %5)
>  %130 = extractelement <4 x float> %129, i32 0
>  %131 = extractelement <4 x float> %129, i32 1
>  %132 = extractelement <4 x float> %129, i32 2
>  %133 = extractelement <4 x float> %129, i32 3
>  %134 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
>  %135 = load <16 x i8> addrspace(2)* %134, !tbaa !0
>  %136 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %135, i32 0, i32 %5)
>  %137 = extractelement <4 x float> %136, i32 0
>  %138 = extractelement <4 x float> %136, i32 1
>  %139 = extractelement <4 x float> %136, i32 2
>  %140 = extractelement <4 x float> %136, i32 3
>  %141 = getelementptr <16 x i8> addrspace(2)* %3, i32 7
>  %142 = load <16 x i8> addrspace(2)* %141, !tbaa !0
>  %143 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %142, i32 0, i32 %5)
>  %144 = extractelement <4 x float> %143, i32 0
>  %145 = extractelement <4 x float> %143, i32 1
>  %146 = extractelement <4 x float> %143, i32 2
>  %147 = extractelement <4 x float> %143, i32 3
>  %148 = getelementptr <16 x i8> addrspace(2)* %3, i32 8
>  %149 = load <16 x i8> addrspace(2)* %148, !tbaa !0
>  %150 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %149, i32 0, i32 %5)
>  %151 = extractelement <4 x float> %150, i32 0
>  %152 = extractelement <4 x float> %150, i32 1
>  %153 = fmul float %98, %11
>  %154 = fmul float %99, %12
>  %155 = fadd float %153, %154
>  %156 = fmul float %100, %13
>  %157 = fadd float %155, %156
>  %158 = fmul float %101, %14
>  %159 = fadd float %157, %158
>  %160 = fmul float %98, %15
>  %161 = fmul float %99, %16
>  %162 = fadd float %160, %161
>  %163 = fmul float %100, %17
>  %164 = fadd float %162, %163
>  %165 = fmul float %101, %18
>  %166 = fadd float %164, %165
>  %167 = fmul float %98, %19
>  %168 = fmul float %99, %20
>  %169 = fadd float %167, %168
>  %170 = fmul float %100, %21
>  %171 = fadd float %169, %170
>  %172 = fmul float %101, %22
>  %173 = fadd float %171, %172
>  %174 = fmul float %98, %23
>  %175 = fmul float %99, %24
>  %176 = fadd float %174, %175
>  %177 = fmul float %100, %25
>  %178 = fadd float %176, %177
>  %179 = fmul float %101, %26
>  %180 = fadd float %178, %179
>  %181 = fmul float %159, 5.000000e-01
>  %182 = fmul float %166, 5.000000e-01
>  %183 = fmul float %180, 5.000000e-01
>  %184 = fadd float %183, %181
>  %185 = fmul float %180, 5.000000e-01
>  %186 = fadd float %185, %182
>  %187 = fmul float %98, %27
>  %188 = fmul float %99, %28
>  %189 = fadd float %187, %188
>  %190 = fmul float %100, %29
>  %191 = fadd float %189, %190
>  %192 = fmul float %101, %30
>  %193 = fadd float %191, %192
>  %194 = fmul float %98, %31
>  %195 = fmul float %99, %32
>  %196 = fadd float %194, %195
>  %197 = fmul float %100, %33
>  %198 = fadd float %196, %197
>  %199 = fmul float %101, %34
>  %200 = fadd float %198, %199
>  %201 = fmul float %98, %35
>  %202 = fmul float %99, %36
>  %203 = fadd float %201, %202
>  %204 = fmul float %100, %37
>  %205 = fadd float %203, %204
>  %206 = fmul float %101, %38
>  %207 = fadd float %205, %206
>  %208 = fmul float %123, %59
>  %209 = fmul float %124, %60
>  %210 = fadd float %208, %209
>  %211 = fmul float %125, %61
>  %212 = fadd float %210, %211
>  %213 = fmul float %126, %62
>  %214 = fadd float %212, %213
>  %215 = fmul float %123, %63
>  %216 = fmul float %124, %64
>  %217 = fadd float %215, %216
>  %218 = fmul float %125, %65
>  %219 = fadd float %217, %218
>  %220 = fmul float %126, %66
>  %221 = fadd float %219, %220
>  %222 = fmul float %130, %67
>  %223 = fmul float %131, %68
>  %224 = fadd float %222, %223
>  %225 = fmul float %132, %69
>  %226 = fadd float %224, %225
>  %227 = fmul float %133, %70
>  %228 = fadd float %226, %227
>  %229 = fmul float %130, %71
>  %230 = fmul float %131, %72
>  %231 = fadd float %229, %230
>  %232 = fmul float %132, %73
>  %233 = fadd float %231, %232
>  %234 = fmul float %133, %74
>  %235 = fadd float %233, %234
>  %236 = fmul float %137, %75
>  %237 = fmul float %138, %76
>  %238 = fadd float %236, %237
>  %239 = fmul float %139, %77
>  %240 = fadd float %238, %239
>  %241 = fmul float %140, %78
>  %242 = fadd float %240, %241
>  %243 = fmul float %137, %79
>  %244 = fmul float %138, %80
>  %245 = fadd float %243, %244
>  %246 = fmul float %139, %81
>  %247 = fadd float %245, %246
>  %248 = fmul float %140, %82
>  %249 = fadd float %247, %248
>  %250 = fmul float %144, %83
>  %251 = fmul float %145, %84
>  %252 = fadd float %250, %251
>  %253 = fmul float %146, %85
>  %254 = fadd float %252, %253
>  %255 = fmul float %147, %86
>  %256 = fadd float %254, %255
>  %257 = fmul float %144, %87
>  %258 = fmul float %145, %88
>  %259 = fadd float %257, %258
>  %260 = fmul float %146, %89
>  %261 = fadd float %259, %260
>  %262 = fmul float %147, %90
>  %263 = fadd float %261, %262
>  %264 = fmul float %118, %39
>  %265 = fadd float %264, %40
>  %266 = fmul float %119, %39
>  %267 = fadd float %266, %40
>  %268 = fmul float %105, %91
>  %269 = fadd float %268, %92
>  %270 = fmul float %106, %91
>  %271 = fadd float %270, %92
>  %272 = fmul float %107, %91
>  %273 = fadd float %272, %92
>  %274 = fadd float %271, 0x3F50624DE0000000
>  %275 = fmul float %111, %93
>  %276 = fadd float %275, %94
>  %277 = fmul float %112, %93
>  %278 = fadd float %277, %94
>  %279 = fmul float %113, %93
>  %280 = fadd float %279, %94
>  %281 = fmul float %114, %93
>  %282 = fadd float %281, %94
>  %283 = fadd float %276, 0x3F50624DE0000000
>  %284 = fmul float %269, %282
>  %285 = fmul float %274, %282
>  %286 = fmul float %273, %282
>  %287 = fmul float %286, %278
>  %288 = fmul float %284, %280
>  %289 = fmul float %285, %283
>  %290 = fsub float -0.000000e+00, %287
>  %291 = fmul float %285, %280
>  %292 = fadd float %291, %290
>  %293 = fsub float -0.000000e+00, %288
>  %294 = fmul float %286, %283
>  %295 = fadd float %294, %293
>  %296 = fsub float -0.000000e+00, %289
>  %297 = fmul float %284, %278
>  %298 = fadd float %297, %296
>  %299 = fmul float %27, %27
>  %300 = fmul float %31, %31
>  %301 = fadd float %300, %299
>  %302 = fmul float %35, %35
>  %303 = fadd float %301, %302
>  %304 = fdiv float 1.000000e+00, %303
>  %305 = fmul float %27, %304
>  %306 = fmul float %31, %304
>  %307 = fmul float %35, %304
>  %308 = fmul float %28, %28
>  %309 = fmul float %32, %32
>  %310 = fadd float %309, %308
>  %311 = fmul float %36, %36
>  %312 = fadd float %310, %311
>  %313 = fdiv float 1.000000e+00, %312
>  %314 = fmul float %28, %313
>  %315 = fmul float %32, %313
>  %316 = fmul float %36, %313
>  %317 = fmul float %29, %29
>  %318 = fmul float %33, %33
>  %319 = fadd float %318, %317
>  %320 = fmul float %37, %37
>  %321 = fadd float %319, %320
>  %322 = fdiv float 1.000000e+00, %321
>  %323 = fmul float %29, %322
>  %324 = fmul float %33, %322
>  %325 = fmul float %37, %322
>  %326 = fmul float %305, %283
>  %327 = fmul float %306, %283
>  %328 = fmul float %307, %283
>  %329 = fmul float %314, %278
>  %330 = fadd float %329, %326
>  %331 = fmul float %315, %278
>  %332 = fadd float %331, %327
>  %333 = fmul float %316, %278
>  %334 = fadd float %333, %328
>  %335 = fmul float %323, %280
>  %336 = fadd float %335, %330
>  %337 = fmul float %324, %280
>  %338 = fadd float %337, %332
>  %339 = fmul float %325, %280
>  %340 = fadd float %339, %334
>  %341 = fmul float %305, %292
>  %342 = fmul float %306, %292
>  %343 = fmul float %307, %292
>  %344 = fmul float %314, %295
>  %345 = fadd float %344, %341
>  %346 = fmul float %315, %295
>  %347 = fadd float %346, %342
>  %348 = fmul float %316, %295
>  %349 = fadd float %348, %343
>  %350 = fmul float %323, %298
>  %351 = fadd float %350, %345
>  %352 = fmul float %324, %298
>  %353 = fadd float %352, %347
>  %354 = fmul float %325, %298
>  %355 = fadd float %354, %349
>  %356 = fmul float %305, %269
>  %357 = fmul float %306, %269
>  %358 = fmul float %307, %269
>  %359 = fmul float %314, %274
>  %360 = fadd float %359, %356
>  %361 = fmul float %315, %274
>  %362 = fadd float %361, %357
>  %363 = fmul float %316, %274
>  %364 = fadd float %363, %358
>  %365 = fmul float %323, %273
>  %366 = fadd float %365, %360
>  %367 = fmul float %324, %273
>  %368 = fadd float %367, %362
>  %369 = fmul float %325, %273
>  %370 = fadd float %369, %364
>  %371 = fmul float %336, %336
>  %372 = fmul float %338, %338
>  %373 = fadd float %372, %371
>  %374 = fmul float %340, %340
>  %375 = fadd float %373, %374
>  %376 = call float @llvm.AMDGPU.rsq(float %375)
>  %377 = fmul float %336, %376
>  %378 = fmul float %338, %376
>  %379 = fmul float %340, %376
>  %380 = fmul float %351, %351
>  %381 = fmul float %353, %353
>  %382 = fadd float %381, %380
>  %383 = fmul float %355, %355
>  %384 = fadd float %382, %383
>  %385 = call float @llvm.AMDGPU.rsq(float %384)
>  %386 = fmul float %351, %385
>  %387 = fmul float %353, %385
>  %388 = fmul float %355, %385
>  %389 = fmul float %366, %366
>  %390 = fmul float %368, %368
>  %391 = fadd float %390, %389
>  %392 = fmul float %370, %370
>  %393 = fadd float %391, %392
>  %394 = call float @llvm.AMDGPU.rsq(float %393)
>  %395 = fmul float %366, %394
>  %396 = fmul float %368, %394
>  %397 = fmul float %370, %394
>  %398 = fsub float -0.000000e+00, %41
>  %399 = fadd float %193, %398
>  %400 = fsub float -0.000000e+00, %42
>  %401 = fadd float %200, %400
>  %402 = fsub float -0.000000e+00, %43
>  %403 = fadd float %207, %402
>  %404 = fmul float %399, %399
>  %405 = fmul float %401, %401
>  %406 = fadd float %405, %404
>  %407 = fmul float %403, %403
>  %408 = fadd float %406, %407
>  %409 = call float @llvm.AMDGPU.rsq(float %408)
>  %410 = fmul float %409, %408
>  %411 = fsub float -0.000000e+00, %408
>  %412 = call float @llvm.AMDGPU.cndlt(float %411, float %410, float 0.000000e+00)
>  %413 = fcmp olt float 0.000000e+00, %45
>  %414 = sext i1 %413 to i32
>  %415 = bitcast i32 %414 to float
>  %416 = bitcast float %415 to i32
>  %417 = icmp ne i32 %416, 0
>  br i1 %417, label %IF, label %ENDIF
>
>IF:                                               ; preds = %main_body
>  %418 = fmul float %193, %51
>  %419 = fmul float %200, %52
>  %420 = fadd float %418, %419
>  %421 = fmul float %207, %53
>  %422 = fadd float %420, %421
>  %423 = fmul float 1.000000e+00, %54
>  %424 = fadd float %422, %423
>  %425 = fmul float %41, %51
>  %426 = fmul float %42, %52
>  %427 = fadd float %425, %426
>  %428 = fmul float %43, %53
>  %429 = fadd float %427, %428
>  %430 = fmul float %44, %54
>  %431 = fadd float %429, %430
>  %432 = fsub float -0.000000e+00, %431
>  %433 = fadd float %424, %432
>  %434 = fcmp oge float %433, 0.000000e+00
>  %435 = sext i1 %434 to i32
>  %436 = bitcast i32 %435 to float
>  %437 = bitcast float %436 to i32
>  %438 = icmp ne i32 %437, 0
>  %. = select i1 %438, float %431, float %424
>  %.70 = select i1 %438, float %424, float %431
>  %439 = fsub float -0.000000e+00, %47
>  %440 = fadd float %., %439
>  %441 = fsub float -0.000000e+00, %47
>  %442 = fadd float %.70, %441
>  %443 = fsub float -0.000000e+00, %440
>  %444 = fadd float %49, %443
>  %445 = fsub float -0.000000e+00, %440
>  %446 = fadd float %50, %445
>  %447 = call float @fabs(float %433)
>  %448 = fadd float %447, 0x3F50624DE0000000
>  %449 = fdiv float 1.000000e+00, %448
>  %450 = fmul float %444, %449
>  %451 = fmul float %446, %449
>  %452 = call float @llvm.AMDIL.clamp.(float %450, float 0.000000e+00, float 1.000000e+00)
>  %453 = call float @llvm.AMDIL.clamp.(float %451, float 0.000000e+00, float 1.000000e+00)
>  %454 = fmul float %440, %46
>  %455 = fmul float %442, %46
>  %456 = fsub float -0.000000e+00, %454
>  %457 = fadd float 1.000000e+00, %456
>  %458 = fsub float -0.000000e+00, %455
>  %459 = fadd float 1.000000e+00, %458
>  %460 = call float @llvm.AMDIL.clamp.(float %457, float 0.000000e+00, float 1.000000e+00)
>  %461 = call float @llvm.AMDIL.clamp.(float %459, float 0.000000e+00, float 1.000000e+00)
>  %462 = fmul float %412, %45
>  %463 = fsub float -0.000000e+00, %453
>  %464 = fadd float %452, %463
>  %465 = call float @llvm.AMDIL.clamp.(float %464, float 0.000000e+00, float 1.000000e+00)
>  %466 = fadd float %460, %461
>  %467 = fmul float %466, %48
>  %468 = call float @llvm.AMDIL.clamp.(float %467, float 0.000000e+00, float 1.000000e+00)
>  %469 = fmul float %465, %468
>  %470 = fmul float %462, %469
>  %471 = call float @llvm.AMDIL.clamp.(float %470, float 0.000000e+00, float 1.000000e+00)
>  br label %ENDIF
>
>ENDIF:                                            ; preds = %main_body, %IF
>  %temp12.0 = phi float [ %471, %IF ], [ 0.000000e+00, %main_body ]
>  %472 = fcmp olt float 0.000000e+00, %55
>  %473 = sext i1 %472 to i32
>  %474 = bitcast i32 %473 to float
>  %475 = bitcast float %474 to i32
>  %476 = icmp ne i32 %475, 0
>  br i1 %476, label %IF68, label %ENDIF67
>
>IF68:                                             ; preds = %ENDIF
>  %477 = fmul float %412, 0x3F1D745260000000
>  %478 = call float @llvm.AMDIL.clamp.(float %477, float 0.000000e+00, float 1.000000e+00)
>  %479 = fmul float %58, %478
>  %480 = fsub float -0.000000e+00, %479
>  %481 = fadd float 1.000000e+00, %480
>  %482 = fmul float %401, %481
>  %483 = fmul float %482, %56
>  %484 = fsub float -0.000000e+00, %483
>  %485 = fadd float 1.000000e+00, %484
>  %486 = call float @llvm.AMDIL.clamp.(float %485, float 0.000000e+00, float 1.000000e+00)
>  %487 = fmul float %486, %486
>  %488 = fsub float -0.000000e+00, %57
>  %489 = fadd float %412, %488
>  %490 = fsub float -0.000000e+00, %55
>  %491 = fmul float %490, %489
>  %492 = fmul float %491, 0x3FF7154760000000
>  %493 = call float @llvm.AMDIL.exp.(float %492)
>  %494 = fsub float -0.000000e+00, %493
>  %495 = fadd float 1.000000e+00, %494
>  %496 = call float @llvm.AMDIL.clamp.(float %495, float 0.000000e+00, float 1.000000e+00)
>  %497 = fmul float %496, %487
>  br label %ENDIF67
>
>ENDIF67:                                          ; preds = %ENDIF, %IF68
>  %temp48.0 = phi float [ %497, %IF68 ], [ 0.000000e+00, %ENDIF ]
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %184, float %186, float %temp12.0, float %temp48.0)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %193, float %200, float %207, float %180)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %214, float %221, float %228, float %235)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %242, float %249, float %256, float %263)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %151, float %152, float %265, float %267)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %377, float %378, float %379, float %386)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %387, float %388, float %395, float %396)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %397, float %396, float %397, float 0.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %159, float %166, float %173, float %180)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
># Machine code for function main: Post SSA, not tracking liveness
>Function Live Ins: %SGPR0_SGPR1 in %vreg56, %SGPR6_SGPR7 in %vreg59, %VGPR0 in %vreg61
>
>BB#0: derived from LLVM BB %main_body
>    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%115](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%10](align=8)(tbaa=!"const")
>	S_WAITCNT 112
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 91; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 90; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR4, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%107](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 89; mem:LD4[<unknown>]
>	S_WAITCNT 112
>	%VGPR12<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 88; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR13<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_MAD_F32 %VGPR8, %VGPR13, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_MUL_F32_e32 %VGPR14, %VGPR7, %EXEC<imp-use>
>	%VGPR17<def> = V_MAD_F32 %VGPR3, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR16<def> = V_MUL_F32_e32 %VGPR15, %VGPR17, %EXEC<imp-use>
>	%VGPR18<def> = V_MAD_F32 %VGPR10, %VGPR13, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR19<def> = V_MUL_F32_e32 %VGPR18, %VGPR7, %EXEC<imp-use>
>	%VGPR20<def> = V_MAD_F32 %VGPR1, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR20<def> = V_ADD_F32_e32 1.000000e-03, %VGPR20<kill>, %EXEC<imp-use>
>	%VGPR21<def> = V_MUL_F32_e32 %VGPR19, %VGPR20, %EXEC<imp-use>
>	%VGPR16<def> = V_SUB_F32_e32 %VGPR21<kill>, %VGPR16<kill>, %EXEC<imp-use>
>	%VGPR21<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
>	%VGPR1<def> = V_MUL_F32_e32 %VGPR19<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR2<def> = V_MAD_F32 %VGPR9, %VGPR13<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
>	%VGPR19<def> = V_ADD_F32_e32 1.000000e-03, %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR19, %VGPR7<kill>, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %VGPR2, %VGPR17, %EXEC<imp-use>
>	%VGPR1<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR5<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e64 %SGPR4, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR4<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %SGPR5, %VGPR4, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR7<def> = V_MOV_B32_e32 %SGPR8, %EXEC<imp-use>
>	%VGPR3<def> = V_MAD_F32 %SGPR8, %VGPR7, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_RCP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR3, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR22, %VGPR1, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e64 %SGPR5, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR10<def> = V_MOV_B32_e32 %SGPR9, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %SGPR9, %VGPR10, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR11<def> = V_MOV_B32_e32 %SGPR10, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %SGPR10, %VGPR11, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_RCP_F32_e32 %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MUL_F32_e32 %SGPR9<kill>, %VGPR9, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR23, %VGPR16, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR21, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR20, %EXEC<imp-use>
>	%VGPR2<def> = V_SUB_F32_e32 %VGPR12<kill>, %VGPR2<kill>, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR12<def> = V_MOV_B32_e32 %SGPR9, %EXEC<imp-use>
>	%VGPR13<def> = V_MUL_F32_e64 %SGPR9, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR11<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR15<def> = V_MOV_B32_e32 %SGPR11, %EXEC<imp-use>
>	%VGPR13<def> = V_MAD_F32 %SGPR11, %VGPR15, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR24<def> = V_MOV_B32_e32 %SGPR12, %EXEC<imp-use>
>	%VGPR13<def> = V_MAD_F32 %SGPR12, %VGPR24, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_RCP_F32_e32 %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MUL_F32_e32 %SGPR11<kill>, %VGPR13, %EXEC<imp-use>
>	%VGPR6<def> = V_MAD_F32 %VGPR25, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR3, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e32 %VGPR26, %VGPR1, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR9, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR28, %VGPR16, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e32 %SGPR9<kill>, %VGPR13, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR29, %VGPR2, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_MUL_F32_e32 %VGPR27, %VGPR27, %EXEC<imp-use>
>	%VGPR30<def> = V_MAD_F32 %VGPR6, %VGPR6, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_MUL_F32_e32 %VGPR31, %VGPR1<kill>, %EXEC<imp-use>
>	%VGPR32<def> = V_MUL_F32_e32 %SGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR32, %VGPR16<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR33<def> = V_MUL_F32_e32 %SGPR12<kill>, %VGPR13<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_MAD_F32 %VGPR33, %VGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR2<def> = V_MAD_F32 %VGPR1, %VGPR1, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR3<def> = V_RSQ_LEGACY_F32_e32 %VGPR2<kill>, %EXEC<imp-use>
>	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3, %EXEC<imp-use>
>	%VGPR2<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR3, %EXEC<imp-use>
>	%VGPR3<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%98](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR34_VGPR35_VGPR36_VGPR37<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
>	S_WAITCNT 1904
>	%VGPR6<def> = V_MUL_F32_e64 %VGPR35, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR34, %VGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR36, %VGPR15<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
>	%VGPR4<def> = V_MAD_F32 %VGPR37, %VGPR6<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 33; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR6<def> = V_SUBREV_F32_e32 %SGPR4, %VGPR4, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e64 %VGPR35, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR34, %VGPR5<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR36, %VGPR12<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
>	%VGPR5<def> = V_MAD_F32 %VGPR37, %VGPR8<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 32; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_SUBREV_F32_e32 %SGPR5, %VGPR5, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR8, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR6, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e64 %VGPR35, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR34, %VGPR7<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR36, %VGPR24<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR8<kill>, %EXEC<imp-use>
>	%VGPR7<def> = V_MAD_F32 %VGPR37, %VGPR9<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 34; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_SUBREV_F32_e32 %SGPR8, %VGPR7, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR9<kill>, %VGPR9, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR9<def> = V_RSQ_LEGACY_F32_e32 %VGPR8, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR8, %EXEC<imp-use>
>	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
>	%SGPR10_SGPR11<def> = V_CMP_GT_F32_e64 0, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR9<kill>, %SGPR10_SGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR8<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MUL_F32_e64 %VGPR35, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR34, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR36, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR8<def> = V_MAD_F32 %VGPR37, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR9<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_MUL_F32_e64 %VGPR35, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR11<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR34, %VGPR11<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR11<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR36, %VGPR11<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR11<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR9<def> = V_MAD_F32 %VGPR37, %VGPR11<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR11<def> = V_MUL_F32_e32 5.000000e-01, %VGPR9, %EXEC<imp-use>
>	%VGPR11<def> = V_MAD_F32 %VGPR8, 5.000000e-01, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR12<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MUL_F32_e64 %VGPR35, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR13<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR34, %VGPR13<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR13<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR36, %VGPR13<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR13<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR12<def> = V_MAD_F32 %VGPR37, %VGPR13<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR13<def> = V_MUL_F32_e32 5.000000e-01, %VGPR12, %EXEC<imp-use>
>	%VGPR13<def> = V_MAD_F32 %VGPR8, 5.000000e-01, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_MUL_F32_e32 %VGPR22, %VGPR14, %EXEC<imp-use>
>	%VGPR15<def> = V_MAD_F32 %VGPR23, %VGPR19, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR15<def> = V_MAD_F32 %VGPR25, %VGPR18, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR16<def> = V_MUL_F32_e32 %VGPR26, %VGPR14, %EXEC<imp-use>
>	%VGPR16<def> = V_MAD_F32 %VGPR28, %VGPR19, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR16<def> = V_MAD_F32 %VGPR29, %VGPR18, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR24<def> = V_MUL_F32_e32 %VGPR16, %VGPR16, %EXEC<imp-use>
>	%VGPR24<def> = V_MAD_F32 %VGPR15, %VGPR15, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR14<def> = V_MUL_F32_e32 %VGPR31, %VGPR14<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_MAD_F32 %VGPR32, %VGPR19<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR14<def> = V_MAD_F32 %VGPR33, %VGPR18<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR18<def> = V_MAD_F32 %VGPR14, %VGPR14, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR18<def> = V_RSQ_LEGACY_F32_e32 %VGPR18<kill>, %EXEC<imp-use>
>	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR18, %EXEC<imp-use>
>	%VGPR15<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR18, %EXEC<imp-use>
>	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR18<kill>, %EXEC<imp-use>
>	%VGPR18<def> = V_MUL_F32_e32 %VGPR22<kill>, %VGPR20, %EXEC<imp-use>
>	%VGPR18<def> = V_MAD_F32 %VGPR23<kill>, %VGPR21, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR18<def> = V_MAD_F32 %VGPR25<kill>, %VGPR17, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR19<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR20, %EXEC<imp-use>
>	%VGPR19<def> = V_MAD_F32 %VGPR28<kill>, %VGPR21, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR19<def> = V_MAD_F32 %VGPR29<kill>, %VGPR17, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR22<def> = V_MUL_F32_e32 %VGPR19, %VGPR19, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR18, %VGPR18, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR20<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR20<kill>, %EXEC<imp-use>
>	%VGPR20<def> = V_MAD_F32 %VGPR32<kill>, %VGPR21<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR17<def> = V_MAD_F32 %VGPR33<kill>, %VGPR17<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR20<def> = V_MAD_F32 %VGPR17, %VGPR17, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR20<def> = V_RSQ_LEGACY_F32_e32 %VGPR20<kill>, %EXEC<imp-use>
>	%VGPR17<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR20, %EXEC<imp-use>
>	%VGPR18<def> = V_MUL_F32_e32 %VGPR18<kill>, %VGPR20, %EXEC<imp-use>
>	%VGPR19<def> = V_MUL_F32_e32 %VGPR19<kill>, %VGPR20<kill>, %EXEC<imp-use>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 28; mem:LD16[%158](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR21_VGPR22_VGPR23_VGPR24<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 85; mem:LD4[<unknown>]
>	S_WAITCNT 112
>	%VGPR20<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR20<def> = V_MUL_F32_e64 %VGPR22, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 84; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR25<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR20<def> = V_MAD_F32 %VGPR21, %VGPR25<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 86; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR25<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR20<def> = V_MAD_F32 %VGPR23, %VGPR25<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 87; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR25<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR20<def> = V_MAD_F32 %VGPR24, %VGPR25<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 81; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR25<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MUL_F32_e64 %VGPR22, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 80; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR26<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MAD_F32 %VGPR21, %VGPR26<kill>, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 82; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR26<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MAD_F32 %VGPR23, %VGPR26<kill>, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 83; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR26<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR21<def> = V_MAD_F32 %VGPR24, %VGPR26<kill>, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23_VGPR24<imp-use,kill>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 24; mem:LD16[%149](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR23_VGPR24_VGPR25_VGPR26<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 77; mem:LD4[<unknown>]
>	S_WAITCNT 112
>	%VGPR22<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MUL_F32_e64 %VGPR24, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 76; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR27<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR23, %VGPR27<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 78; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR27<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR25, %VGPR27<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 79; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR27<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR22<def> = V_MAD_F32 %VGPR26, %VGPR27<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 73; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR27<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MUL_F32_e64 %VGPR24, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 72; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR28<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR23, %VGPR28<kill>, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 74; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR28<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR25, %VGPR28<kill>, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 75; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR28<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR23<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR23_VGPR24_VGPR25_VGPR26<imp-use,kill>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%140](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR25_VGPR26_VGPR27_VGPR28<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 69; mem:LD4[<unknown>]
>	S_WAITCNT 112
>	%VGPR24<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_MUL_F32_e64 %VGPR26, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 68; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR29<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_MAD_F32 %VGPR25, %VGPR29<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 70; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR29<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_MAD_F32 %VGPR27, %VGPR29<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 71; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR29<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR24<def> = V_MAD_F32 %VGPR28, %VGPR29<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 65; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR29<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MUL_F32_e64 %VGPR26, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 64; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR30<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR25, %VGPR30<kill>, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 66; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR30<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR27, %VGPR30<kill>, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 67; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR30<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR25<def> = V_MAD_F32 %VGPR28, %VGPR30<kill>, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-use,kill>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 16; mem:LD16[%131](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR27_VGPR28_VGPR29_VGPR30<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 61; mem:LD4[<unknown>]
>	S_WAITCNT 112
>	%VGPR26<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MUL_F32_e64 %VGPR28, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 60; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR31<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR27, %VGPR31<kill>, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 62; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR31<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR29, %VGPR31<kill>, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 63; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR31<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR26<def> = V_MAD_F32 %VGPR30, %VGPR31<kill>, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 57; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR31<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MUL_F32_e64 %VGPR28, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 56; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR32<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR27, %VGPR32<kill>, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 58; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR32<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR31<def> = V_MAD_F32 %VGPR29, %VGPR32<kill>, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 59; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR32<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR27<def> = V_MAD_F32 %VGPR30, %VGPR32<kill>, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR27_VGPR28_VGPR29_VGPR30<imp-use,kill>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR28<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MUL_F32_e64 %VGPR35, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR29<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR34, %VGPR29<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR29<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR36, %VGPR29<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR29<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR28<def> = V_MAD_F32 %VGPR37, %VGPR29<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR34_VGPR35_VGPR36_VGPR37<imp-use,kill>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%124](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR30_VGPR31_VGPR32_VGPR33<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29; mem:LD4[<unknown>]
>	S_WAITCNT 112
>	%VGPR34<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR35<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR29<def> = V_MAD_F32 %VGPR31, %VGPR35, %VGPR34, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR30<def> = V_MAD_F32 %VGPR30, %VGPR35<kill>, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR30_VGPR31_VGPR32_VGPR33<imp-use,kill>
>	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 32; mem:LD16[%167](align=8)(tbaa=!"const")
>	S_WAITCNT 127
>	%VGPR31_VGPR32_VGPR33_VGPR34<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
>	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 52; mem:LD4[<unknown>]
>	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 40; mem:LD4[<unknown>]
>	S_WAITCNT 112
>	%SGPR10_SGPR11<def> = V_CMP_GT_F32_e64 %SGPR7, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
>	%SGPR10_SGPR11<def> = S_AND_SAVEEXEC_B64 %SGPR10_SGPR11, %EXEC<imp-def>, %EXEC<imp-use>
>	%SGPR10_SGPR11<def> = S_XOR_B64 %EXEC, %SGPR10_SGPR11
>	S_CBRANCH_EXECZ <BB#2>, %EXEC
>    Successors according to CFG: BB#1(16) BB#2(16)
>
>BB#1: derived from LLVM BB %IF
>    Live Ins: %SGPR6 %VGPR12 %VGPR9 %VGPR28 %VGPR8 %VGPR13 %VGPR11 %VGPR5 %VGPR4 %VGPR7 %VGPR27 %VGPR26 %VGPR25 %VGPR24 %VGPR23 %VGPR22 %VGPR21 %VGPR20 %VGPR30 %VGPR29 %VGPR19 %VGPR18 %VGPR17 %VGPR3 %VGPR2 %VGPR1 %VGPR16 %VGPR15 %VGPR14 %VGPR10 %SGPR0_SGPR1_SGPR2_SGPR3 %SGPR4 %VGPR6 %SGPR5 %SGPR8 %VGPR31_VGPR32_VGPR33_VGPR34 %SGPR7 %SGPR10_SGPR11
>    Predecessors according to CFG: BB#0
>	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 51; mem:LD4[<unknown>]
>	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 50; mem:LD4[<unknown>]
>	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 49; mem:LD4[<unknown>]
>	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 48; mem:LD4[<unknown>]
>	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 47; mem:LD4[<unknown>]
>	%SGPR16<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 46; mem:LD4[<unknown>]
>	%SGPR17<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 45; mem:LD4[<unknown>]
>	%SGPR18<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 44; mem:LD4[<unknown>]
>	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 41; mem:LD4[<unknown>]
>	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 35; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR0<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
>	%VGPR35<def> = V_MOV_B32_e32 %SGPR7<kill>, %EXEC<imp-use>
>	%VGPR36<def> = V_MOV_B32_e32 %SGPR13<kill>, %EXEC<imp-use>
>	%VGPR37<def> = V_MUL_F32_e64 %SGPR4<kill>, %VGPR36, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR38<def> = V_MOV_B32_e32 %SGPR14<kill>, %EXEC<imp-use>
>	%VGPR37<def> = V_MAD_F32 %SGPR5<kill>, %VGPR38, %VGPR37<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR39<def> = V_MOV_B32_e32 %SGPR12<kill>, %EXEC<imp-use>
>	%VGPR37<def> = V_MAD_F32 %SGPR8<kill>, %VGPR39, %VGPR37<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR37<def> = V_MAD_F32 %SGPR20<kill>, %VGPR0, %VGPR37<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR36<def> = V_MUL_F32_e64 %VGPR4, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR36<def> = V_MAD_F32 %VGPR5, %VGPR38<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR36<def> = V_MAD_F32 %VGPR7, %VGPR39<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e32 %VGPR0<kill>, %VGPR36<kill>, %EXEC<imp-use>
>	%VGPR36<def> = V_SUB_F32_e32 %VGPR0, %VGPR37, %EXEC<imp-use>
>	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR36, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR38<def> = V_CNDMASK_B32_e64 %VGPR0, %VGPR37, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR38<def> = V_SUBREV_F32_e32 %SGPR18, %VGPR38<kill>, %EXEC<imp-use>
>	%VGPR39<def> = V_SUB_F32_e32 %SGPR15<kill>, %VGPR38, %EXEC<imp-use>
>	%VGPR36<def> = V_ADD_F32_e64 %VGPR36<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
>	%VGPR36<def> = V_ADD_F32_e32 1.000000e-03, %VGPR36<kill>, %EXEC<imp-use>
>	%VGPR36<def> = V_RCP_F32_e32 %VGPR36<kill>, %EXEC<imp-use>
>	%VGPR39<def> = V_MUL_F32_e32 %VGPR39<kill>, %VGPR36, %EXEC<imp-use>
>	%VGPR39<def> = V_ADD_F32_e64 %VGPR39<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR40<def> = V_SUB_F32_e32 %SGPR16<kill>, %VGPR38, %EXEC<imp-use>
>	%VGPR36<def> = V_MUL_F32_e32 %VGPR40<kill>, %VGPR36<kill>, %EXEC<imp-use>
>	%VGPR36<def> = V_ADD_F32_e64 %VGPR36<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR36<def> = V_SUB_F32_e32 %VGPR36<kill>, %VGPR39<kill>, %EXEC<imp-use>
>	%VGPR36<def> = V_ADD_F32_e64 %VGPR36<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR37<kill>, %VGPR0<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR18<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MUL_F32_e32 %SGPR19, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_SUB_F32_e32 1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR37<def> = V_MUL_F32_e32 %SGPR19<kill>, %VGPR38<kill>, %EXEC<imp-use>
>	%VGPR37<def> = V_SUB_F32_e32 1.000000e+00, %VGPR37<kill>, %EXEC<imp-use>
>	%VGPR37<def> = V_ADD_F32_e64 %VGPR37<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e32 %VGPR37<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_MUL_F32_e32 %VGPR36<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR35<def> = V_MUL_F32_e64 %VGPR10, %VGPR35<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR0<def> = V_MUL_F32_e32 %VGPR35<kill>, %VGPR0<kill>, %EXEC<imp-use>
>	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use,kill>
>    Successors according to CFG: BB#2
>
>BB#2: derived from LLVM BB %ENDIF
>    Live Ins: %SGPR6 %VGPR12 %VGPR9 %VGPR28 %VGPR8 %VGPR13 %VGPR11 %VGPR5 %VGPR4 %VGPR7 %VGPR27 %VGPR26 %VGPR25 %VGPR24 %VGPR23 %VGPR22 %VGPR21 %VGPR20 %VGPR30 %VGPR29 %VGPR19 %VGPR18 %VGPR17 %VGPR3 %VGPR2 %VGPR1 %VGPR16 %VGPR15 %VGPR14 %VGPR10 %SGPR0_SGPR1_SGPR2_SGPR3 %VGPR6 %VGPR31_VGPR32_VGPR33_VGPR34 %SGPR10_SGPR11 %VGPR0
>    Predecessors according to CFG: BB#0 BB#1
>	%EXEC<def> = S_OR_B64 %EXEC, %SGPR10_SGPR11
>	%SGPR4_SGPR5<def> = V_CMP_GT_F32_e64 %SGPR6, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR35<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
>	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
>	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
>	S_CBRANCH_EXECZ <BB#4>, %EXEC
>    Successors according to CFG: BB#3(16) BB#4(16)
>
>BB#3: derived from LLVM BB %IF68
>    Live Ins: %SGPR6 %VGPR12 %VGPR9 %VGPR28 %VGPR8 %VGPR13 %VGPR11 %VGPR5 %VGPR4 %VGPR7 %VGPR27 %VGPR26 %VGPR25 %VGPR24 %VGPR23 %VGPR22 %VGPR21 %VGPR20 %VGPR30 %VGPR29 %VGPR19 %VGPR18 %VGPR17 %VGPR3 %VGPR2 %VGPR1 %VGPR16 %VGPR15 %VGPR14 %VGPR10 %SGPR0_SGPR1_SGPR2_SGPR3 %VGPR6 %VGPR31_VGPR32_VGPR33_VGPR34 %SGPR4_SGPR5 %VGPR0
>    Predecessors according to CFG: BB#2
>	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 54; mem:LD4[<unknown>]
>	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 55; mem:LD4[<unknown>]
>	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 53; mem:LD4[<unknown>]
>	S_WAITCNT 127
>	%VGPR35<def> = V_MOV_B32_e32 %SGPR7<kill>, %EXEC<imp-use>
>	%VGPR35<def> = V_SUB_F32_e64 %VGPR10, %VGPR35<kill>, 0, 0, 0, 0, %EXEC<imp-use>
>	%VGPR35<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR35<kill>, %EXEC<imp-use>
>	%VGPR35<def> = V_MUL_F32_e32 -1.442695e+00, %VGPR35<kill>, %EXEC<imp-use>
>	%VGPR35<def> = V_EXP_F32_e32 %VGPR35<kill>, %EXEC<imp-use>
>	%VGPR35<def> = V_SUB_F32_e32 1.000000e+00, %VGPR35<kill>, %EXEC<imp-use>
>	%VGPR35<def> = V_ADD_F32_e64 %VGPR35<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR36<def> = V_MOV_B32_e32 1.123596e-04, %EXEC<imp-use>
>	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR36<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_ADD_F32_e64 %VGPR10<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR10<kill>, %EXEC<imp-use>
>	%VGPR10<def> = V_SUB_F32_e32 1.000000e+00, %VGPR10<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR10<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_SUB_F32_e32 1.000000e+00, %VGPR6<kill>, %EXEC<imp-use>
>	%VGPR6<def> = V_ADD_F32_e64 %VGPR6<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
>	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR6, %EXEC<imp-use>
>	%VGPR35<def> = V_MUL_F32_e32 %VGPR35<kill>, %VGPR6<kill>, %EXEC<imp-use,kill>
>    Successors according to CFG: BB#4
>
>BB#4: derived from LLVM BB %ENDIF67
>    Live Ins: %VGPR12 %VGPR9 %VGPR28 %VGPR8 %VGPR13 %VGPR11 %VGPR5 %VGPR4 %VGPR7 %VGPR27 %VGPR26 %VGPR25 %VGPR24 %VGPR23 %VGPR22 %VGPR21 %VGPR20 %VGPR30 %VGPR29 %VGPR19 %VGPR18 %VGPR17 %VGPR3 %VGPR2 %VGPR1 %VGPR16 %VGPR15 %VGPR14 %VGPR31_VGPR32_VGPR33_VGPR34 %SGPR4_SGPR5 %VGPR0 %VGPR35
>    Predecessors according to CFG: BB#2 BB#3
>	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
>	EXP 15, 32, 0, 0, 0, %VGPR13<kill>, %VGPR11<kill>, %VGPR0<kill>, %VGPR35<kill>, %EXEC<imp-use>
>	EXP 15, 33, 0, 0, 0, %VGPR5<kill>, %VGPR4<kill>, %VGPR7<kill>, %VGPR8, %EXEC<imp-use>
>	EXP 15, 34, 0, 0, 0, %VGPR27<kill>, %VGPR26<kill>, %VGPR25<kill>, %VGPR24<kill>, %EXEC<imp-use>
>	EXP 15, 35, 0, 0, 0, %VGPR23<kill>, %VGPR22<kill>, %VGPR21<kill>, %VGPR20<kill>, %EXEC<imp-use>
>	EXP 15, 36, 0, 0, 0, %VGPR31, %VGPR32, %VGPR30<kill>, %VGPR29<kill>, %EXEC<imp-use>, %VGPR31_VGPR32_VGPR33_VGPR34<imp-use,kill>
>	EXP 15, 37, 0, 0, 0, %VGPR19<kill>, %VGPR18<kill>, %VGPR17<kill>, %VGPR3<kill>, %EXEC<imp-use>
>	EXP 15, 38, 0, 0, 0, %VGPR2<kill>, %VGPR1<kill>, %VGPR16<kill>, %VGPR15, %EXEC<imp-use>
>	S_WAITCNT 1807
>	%VGPR0<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
>	EXP 15, 39, 0, 0, 0, %VGPR14<kill>, %VGPR15<kill>, %VGPR14, %VGPR0<kill>, %EXEC<imp-use>
>	EXP 15, 12, 0, 1, 0, %VGPR12<kill>, %VGPR9<kill>, %VGPR28<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
>	S_ENDPGM
>
># End machine code for function main.
>
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c202015b
>bf8c007f
>7e0a0204
>c202015a
>bf8c007f
>7e0c0204
>d2820007
>04160d04
>c0840704
>bf8c007f
>e00c2000
>80020800
>c2020159
>bf8c0070
>7e180204
>c2020158
>bf8c007f
>7e1a0204
>d282000e
>04321b08
>101e0f0e
>d2820011
>04160d03
>1020230f
>d2820012
>04321b0a
>10260f12
>d2820014
>04160d01
>062828ff
>3a83126f
>102a2913
>08202115
>d2820015
>04160d02
>10022b13
>d2820002
>04321b09
>062604ff
>3a83126f
>10040f13
>10062302
>08020303
>c2020110
>bf8c007f
>7e0a0204
>d2100003
>02020a04
>c2028114
>bf8c007f
>7e080205
>d2820003
>040e0805
>c2040118
>bf8c007f
>7e0e0208
>d2820003
>040e0e08
>7e065503
>102c0605
>100c0316
>c2028111
>bf8c007f
>7e100205
>d2100009
>02021005
>c2048115
>bf8c007f
>7e140209
>d2820009
>04261409
>c2050119
>bf8c007f
>7e16020a
>d2820009
>0426160a
>7e125509
>102e1209
>d2820006
>041a2117
>10182b0f
>10042902
>0804050c
>c2048112
>bf8c007f
>7e180209
>d210000d
>02021809
>c2058116
>bf8c007f
>7e1e020b
>d282000d
>04361e0b
>c206011a
>bf8c007f
>7e30020c
>d282000d
>0436300c
>7e1a550d
>10321a0b
>d2820006
>041a0519
>10340604
>1036031a
>10381205
>d282001b
>046e211c
>103a1a09
>d282001b
>046e051d
>103c371b
>d282001e
>047a0d06
>103e0608
>1002031f
>1040120a
>d2820001
>04062120
>10421a0c
>d2820001
>04060521
>d2820002
>047a0301
>7e065b02
>10020701
>10040706
>1006071b
>c0840700
>bf8c007f
>e00c2000
>80022200
>bf8c0770
>d2100006
>02021523
>d2820004
>041a0922
>d2820004
>04121f24
>c2020117
>bf8c007f
>7e0c0204
>d2820004
>04120d25
>c2020121
>bf8c007f
>0a0c0804
>d2100008
>02021123
>d2820005
>04220b22
>d2820005
>04161924
>c2028113
>bf8c007f
>7e100205
>d2820005
>04161125
>c2028120
>bf8c007f
>0a100a05
>10101108
>d2820008
>04220d06
>d2100009
>02021723
>d2820007
>04260f22
>d2820007
>041e3124
>c204011b
>bf8c007f
>7e120208
>d2820007
>041e1325
>c2040122
>bf8c007f
>0a120e08
>d2820008
>04221309
>7e125b08
>10121109
>d2060008
>22010108
>d008000a
>02021080
>d200000a
>002a1280
>c204810d
>bf8c007f
>7e100209
>d2100008
>02021123
>c204810c
>bf8c007f
>7e120209
>d2820008
>04221322
>c204810e
>bf8c007f
>7e120209
>d2820008
>04221324
>c204810f
>bf8c007f
>7e120209
>d2820008
>04221325
>c2048105
>bf8c007f
>7e120209
>d2100009
>02021323
>c2048104
>bf8c007f
>7e160209
>d2820009
>04261722
>c2048106
>bf8c007f
>7e160209
>d2820009
>04261724
>c2048107
>bf8c007f
>7e160209
>d2820009
>04261725
>101612f0
>d282000b
>042de108
>c2048101
>bf8c007f
>7e180209
>d210000c
>02021923
>c2048100
>bf8c007f
>7e1a0209
>d282000c
>04321b22
>c2048102
>bf8c007f
>7e1a0209
>d282000c
>04321b24
>c2048103
>bf8c007f
>7e1a0209
>d282000c
>04321b25
>101a18f0
>d282000d
>0435e108
>101e1d16
>d282000f
>043e2717
>d282000f
>043e2519
>10201d1a
>d2820010
>0442271c
>d2820010
>0442251d
>10302110
>d2820018
>04621f0f
>101c1d1f
>d282000e
>043a2720
>d282000e
>043a2521
>d2820012
>04621d0e
>7e245b12
>101c250e
>101e250f
>10202510
>10242916
>d2820012
>044a2b17
>d2820012
>044a2319
>1026291a
>d2820013
>044e2b1c
>d2820013
>044e231d
>102c2713
>d2820016
>045a2512
>1028291f
>d2820014
>04522b20
>d2820011
>04522321
>d2820014
>045a2311
>7e285b14
>10222911
>10242912
>10262913
>c086071c
>bf8c007f
>e00c2000
>80031500
>c2048155
>bf8c0070
>7e280209
>d2100014
>02022916
>c2048154
>bf8c007f
>7e320209
>d2820014
>04523315
>c2048156
>bf8c007f
>7e320209
>d2820014
>04523317
>c2048157
>bf8c007f
>7e320209
>d2820014
>04523318
>c2048151
>bf8c007f
>7e320209
>d2100019
>02023316
>c2048150
>bf8c007f
>7e340209
>d2820019
>04663515
>c2048152
>bf8c007f
>7e340209
>d2820019
>04663517
>c2048153
>bf8c007f
>7e340209
>d2820015
>04663518
>c0860718
>bf8c007f
>e00c2000
>80031700
>c204814d
>bf8c0070
>7e2c0209
>d2100016
>02022d18
>c204814c
>bf8c007f
>7e360209
>d2820016
>045a3717
>c204814e
>bf8c007f
>7e360209
>d2820016
>045a3719
>c204814f
>bf8c007f
>7e360209
>d2820016
>045a371a
>c2048149
>bf8c007f
>7e360209
>d210001b
>02023718
>c2048148
>bf8c007f
>7e380209
>d282001b
>046e3917
>c204814a
>bf8c007f
>7e380209
>d282001b
>046e3919
>c204814b
>bf8c007f
>7e380209
>d2820017
>046e391a
>c0860714
>bf8c007f
>e00c2000
>80031900
>c2048145
>bf8c0070
>7e300209
>d2100018
>0202311a
>c2048144
>bf8c007f
>7e3a0209
>d2820018
>04623b19
>c2048146
>bf8c007f
>7e3a0209
>d2820018
>04623b1b
>c2048147
>bf8c007f
>7e3a0209
>d2820018
>04623b1c
>c2048141
>bf8c007f
>7e3a0209
>d210001d
>02023b1a
>c2048140
>bf8c007f
>7e3c0209
>d282001d
>04763d19
>c2048142
>bf8c007f
>7e3c0209
>d282001d
>04763d1b
>c2048143
>bf8c007f
>7e3c0209
>d2820019
>04763d1c
>c0860710
>bf8c007f
>e00c2000
>80031b00
>c204813d
>bf8c0070
>7e340209
>d210001a
>0202351c
>c204813c
>bf8c007f
>7e3e0209
>d282001a
>046a3f1b
>c204813e
>bf8c007f
>7e3e0209
>d282001a
>046a3f1d
>c204813f
>bf8c007f
>7e3e0209
>d282001a
>046a3f1e
>c2048139
>bf8c007f
>7e3e0209
>d210001f
>02023f1c
>c2048138
>bf8c007f
>7e400209
>d282001f
>047e411b
>c204813a
>bf8c007f
>7e400209
>d282001f
>047e411d
>c204813b
>bf8c007f
>7e400209
>d282001b
>047e411e
>c2048109
>bf8c007f
>7e380209
>d210001c
>02023923
>c2048108
>bf8c007f
>7e3a0209
>d282001c
>04723b22
>c204810a
>bf8c007f
>7e3a0209
>d282001c
>04723b24
>c204810b
>bf8c007f
>7e3a0209
>d282001c
>04723b25
>c086070c
>bf8c007f
>e00c2000
>80031e00
>c204811d
>bf8c0070
>7e440209
>c204811c
>bf8c007f
>7e460209
>d282001d
>048a471f
>d282001e
>048a471e
>c0860720
>bf8c007f
>e00c2000
>80031f00
>c2030134
>c2038128
>bf8c0070
>d008000a
>02010007
>7e000280
>be8a240a
>898a0a7e
>bf88004a
>c2048133
>c2060132
>c2068131
>c2070130
>c207812f
>c208012e
>c208812d
>c209012c
>c2098129
>c20a0123
>bf8c007f
>7e000209
>7e460207
>7e48020d
>d2100025
>02024804
>7e4c020e
>d2820025
>04964c05
>7e4e020c
>d2820025
>04964e08
>d2820025
>04960014
>d2100024
>02024904
>d2820024
>04924d05
>d2820024
>04924f07
>06004900
>08484b00
>d00c0004
>02010124
>d2000026
>00124b00
>0a4c4c12
>084e4c0f
>d2060124
>02010124
>064848ff
>3a83126f
>7e485524
>104e4927
>d2060827
>02010127
>08504c10
>10484928
>d2060824
>02010124
>08484f24
>d2060824
>02010124
>d2000000
>00120125
>0a000012
>10000013
>080000f2
>d2060800
>02010100
>104a4c13
>084a4af2
>d2060825
>02010125
>06000125
>10000011
>d2060800
>02010100
>10000124
>d2100023
>0202470a
>10000123
>d2060800
>02010100
>88fe0a7e
>d0080004
>02010006
>7e460280
>be842404
>8984047e
>bf88001c
>c2038136
>c2040137
>c2000135
>bf8c007f
>7e460207
>d2080023
>0202470a
>10464606
>104646ff
>bfb8aa3b
>7e464b23
>084646f2
>d2060823
>02010123
>7e4802ff
>38eba293
>1014490a
>d206080a
>0201010a
>10141408
>081414f2
>100c1506
>100c0c00
>080c0cf2
>d2060806
>02010106
>100c0d06
>10460d23
>88fe047e
>f800020f
>23000b0d
>f800021f
>08070405
>f800022f
>18191a1b
>f800023f
>14151617
>f800024f
>1d1e201f
>f800025f
>03111213
>f800026f
>0f100102
>bf8c070f
>7e000280
>f800027f
>000e0f0e
>f80008cf
>081c090c
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], POSITION, LINEAR
>DCL IN[1], FACE, CONSTANT
>DCL IN[2], GENERIC[19], PERSPECTIVE
>DCL IN[3], GENERIC[20], PERSPECTIVE
>DCL IN[4], GENERIC[21], PERSPECTIVE
>DCL IN[5], GENERIC[22], PERSPECTIVE
>DCL IN[6], GENERIC[23], PERSPECTIVE
>DCL IN[7], GENERIC[24], PERSPECTIVE
>DCL IN[8], GENERIC[25], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL SAMP[4]
>DCL SAMP[5]
>DCL SAMP[6]
>DCL SAMP[7]
>DCL SAMP[8]
>DCL CONST[54]
>DCL CONST[0..44]
>DCL TEMP[0..1]
>DCL TEMP[2..22], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,    -1.0000,     4.5948}
>IMM[1] FLT32 {   32.0000,   -16.0000,     0.5000,     4.0000}
>IMM[2] FLT32 {    2.0000,    -0.0010,     0.0000,     0.0000}
>IMM[3] FLT32 {    0.0000,     0.0100,     0.2500,     3.0000}
>IMM[4] FLT32 {65504.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0], IN[0]
>  1: MAD TEMP[0].y, IN[0], CONST[54].xxxx, CONST[54].yyyy
>  2: MOV_SAT TEMP[1], IN[1]
>  3: MOV TEMP[2].x, IN[7].wwww
>  4: MOV TEMP[2].yz, IN[8].yxyy
>  5: UIF TEMP[1].xxxx :3
>  6:   MOV TEMP[3].x, IMM[0].zzzz
>  7: ELSE :3
>  8:   MOV TEMP[3].x, IMM[0].yyyy
>  9: ENDIF
> 10: ADD TEMP[4].xyz, CONST[11].xyzz, -IN[2].xyzz
> 11: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz
> 12: RSQ TEMP[5].x, TEMP[5].xxxx
> 13: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xxxx
> 14: MUL TEMP[5].x, TEMP[3].xxxx, CONST[14].wwww
> 15: MUL TEMP[6].xy, TEMP[0].xyyy, CONST[12].xyyy
> 16: MOV TEMP[7].xy, IN[4].zwww
> 17: TEX TEMP[7], TEMP[7], SAMP[2], 2D
> 18: MOV TEMP[8].w, TEMP[7].wwww
> 19: MUL TEMP[8].xyz, TEMP[7].xyzz, IMM[0].wwww
> 20: LRP TEMP[8].xyz, CONST[1].wwww, TEMP[8].xyzz, IMM[0].yyyy
> 21: MOV TEMP[9].xy, IN[5].xyyy
> 22: TEX TEMP[9], TEMP[9], SAMP[4], 2D
> 23: MOV TEMP[10].xyz, TEMP[9]
> 24: MOV TEMP[11].xy, IN[3].xyyy
> 25: TEX TEMP[11], TEMP[11], SAMP[3], 2D
> 26: MUL TEMP[12], TEMP[11], CONST[0]
> 27: MUL TEMP[12], TEMP[12], IN[6]
> 28: MOV TEMP[13].w, TEMP[12].wwww
> 29: ADD TEMP[14].x, IMM[0].yyyy, -TEMP[11].wwww
> 30: MUL TEMP[14].x, TEMP[14].xxxx, CONST[12].zzzz
> 31: LRP TEMP[13].xyz, TEMP[14].xxxx, TEMP[11].xyzz, TEMP[12].xyzz
> 32: MOV TEMP[11].xy, IN[3].zwww
> 33: TEX TEMP[11].xyw, TEMP[11], SAMP[5], 2D
> 34: MUL TEMP[12].xy, CONST[14].xyyy, TEMP[11].wxxx
> 35: ADD TEMP[12].xy, IMM[0].yyyy, -TEMP[12].xyyy
> 36: MUL TEMP[13], TEMP[13], TEMP[8]
> 37: DP3 TEMP[8].x, IN[7].xyzz, IN[7].xyzz
> 38: RSQ TEMP[8].x, TEMP[8].xxxx
> 39: MUL TEMP[8].xyz, IN[7].xyzz, TEMP[8].xxxx
> 40: FSLT TEMP[5].x, IMM[0].xxxx, TEMP[5].xxxx
> 41: UIF TEMP[5].xxxx :3
> 42:   MOV TEMP[5].xyz, -TEMP[8].xyzx
> 43: ELSE :3
> 44:   MOV TEMP[5].xyz, TEMP[8].xyzx
> 45: ENDIF
> 46: MOV TEMP[8].w, TEMP[13].wwww
> 47: MOV TEMP[6].xy, TEMP[6].xyyy
> 48: TEX TEMP[6], TEMP[6], SAMP[8], 2D
> 49: MAD TEMP[3], TEMP[6], CONST[10].xxxz, CONST[10].yyyw
> 50: MOV TEMP[6].xy, IN[4].xyyy
> 51: TEX TEMP[6], TEMP[6], SAMP[6], 2D
> 52: MAD TEMP[14].x, TEMP[6].wwww, IMM[1].xxxx, IMM[1].yyyy
> 53: EX2 TEMP[14].x, TEMP[14].xxxx
> 54: MUL TEMP[6].xyz, TEMP[6].xyzz, TEMP[14].xxxx
> 55: MAD TEMP[2].xyz, CONST[3].xyzz, TEMP[6].xyzz, TEMP[2].xyzz
> 56: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].wwww
> 57: MAD TEMP[6].x, TEMP[3].wwww, IMM[1].zzzz, IMM[1].zzzz
> 58: DP3_SAT TEMP[14].x, TEMP[5].xyzz, TEMP[4].xyzz
> 59: ADD TEMP[14].x, IMM[0].yyyy, -TEMP[14].xxxx
> 60: POW TEMP[14].x, TEMP[14].xxxx, IMM[1].wwww
> 61: MUL TEMP[14].x, TEMP[14].xxxx, CONST[3].wwww
> 62: MUL TEMP[15].xy, TEMP[12].xyyy, TEMP[14].xxxx
> 63: ADD TEMP[15].y, TEMP[12].xyyy, -TEMP[15].xyyy
> 64: DP3 TEMP[16].x, TEMP[5].xyzz, TEMP[4].xyzz
> 65: MUL TEMP[16].xyz, TEMP[16].xxxx, TEMP[5].xyzz
> 66: MUL TEMP[16].xyz, IMM[2].xxxx, TEMP[16].xyzz
> 67: ADD TEMP[16].xyz, TEMP[4].xyzz, -TEMP[16].xyzz
> 68: LRP TEMP[17].xyz, TEMP[15].yyyy, -TEMP[5].xyzz, TEMP[16].xyzz
> 69: ABS TEMP[18].xyz, TEMP[17].xyzz
> 70: MAX TEMP[19].x, TEMP[18].yyyy, TEMP[18].zzzz
> 71: MAX TEMP[19].x, TEMP[18].xxxx, TEMP[19].xxxx
> 72: ADD TEMP[20].x, TEMP[19].xxxx, IMM[2].yyyy
> 73: FSGE TEMP[21].x, TEMP[20].xxxx, TEMP[18].xxxx
> 74: AND TEMP[21].x, TEMP[21].xxxx, IMM[0].yyyy
> 75: FSGE TEMP[22].x, TEMP[20].xxxx, TEMP[18].yyyy
> 76: AND TEMP[22].x, TEMP[22].xxxx, IMM[0].yyyy
> 77: MOV TEMP[21].y, TEMP[22].xxxx
> 78: FSGE TEMP[18].x, TEMP[20].xxxx, TEMP[18].zzzz
> 79: AND TEMP[18].x, TEMP[18].xxxx, IMM[0].yyyy
> 80: MOV TEMP[21].z, TEMP[18].xxxx
> 81: RCP TEMP[18].x, TEMP[19].xxxx
> 82: MUL TEMP[18].xyz, IMM[0].zzyy, TEMP[18].xxxx
> 83: MUL TEMP[16].xyz, TEMP[17].xyzz, TEMP[18].xyzz
> 84: ADD TEMP[17].x, CONST[14].zzzz, IMM[0].zzzz
> 85: MUL TEMP[17].x, TEMP[15].yyyy, TEMP[17].xxxx
> 86: MUL TEMP[18].xyz, TEMP[16].xyzz, TEMP[21].xyzz
> 87: FLR TEMP[19].x, TEMP[17].xxxx
> 88: ADD TEMP[19].x, CONST[14].zzzz, -TEMP[19].xxxx
> 89: EX2 TEMP[19].x, TEMP[19].xxxx
> 90: RCP TEMP[19].x, TEMP[19].xxxx
> 91: MUL TEMP[18].xyz, TEMP[18].xyzz, TEMP[19].xxxx
> 92: ADD TEMP[16].xyz, TEMP[16].xyzz, -TEMP[18].xyzz
> 93: MOV TEMP[16].xyz, TEMP[16].xyzz
> 94: MOV TEMP[16].w, TEMP[17].xxxx
> 95: TXL TEMP[16], TEMP[16], SAMP[7], CUBE
> 96: MAD TEMP[17].x, TEMP[16].wwww, IMM[1].xxxx, IMM[1].yyyy
> 97: EX2 TEMP[17].x, TEMP[17].xxxx
> 98: MUL TEMP[16].xyz, TEMP[16].xyzz, TEMP[17].xxxx
> 99: MUL TEMP[17].xyz, CONST[1].xyzz, TEMP[11].yyyy
>100: MUL TEMP[17].xyz, TEMP[17].xyzz, TEMP[11].yyyy
>101: MAD_SAT TEMP[15].x, TEMP[15].yyyy, IMM[2].xxxx, IMM[0].zzzz
>102: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[6].xxxx
>103: MUL TEMP[16].xyz, TEMP[16].xyzz, CONST[2].xyzz
>104: MUL TEMP[16].xyz, TEMP[17].xyzz, TEMP[16].xyzz
>105: LRP TEMP[15].xyz, TEMP[15].xxxx, TEMP[17].xyzz, TEMP[16].xyzz
>106: LRP TEMP[14].xyz, TEMP[14].xxxx, IMM[0].yyyy, TEMP[17].xyzz
>107: LRP TEMP[14].xyz, TEMP[14].xyzz, TEMP[15].xyzz, TEMP[13].xyzz
>108: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[14].xyzz
>109: MAD TEMP[2].xyz, TEMP[3].xyzz, TEMP[13].xyzz, TEMP[2].xyzz
>110: ADD TEMP[3].xyz, IN[2].xyzz, -CONST[30].xyzz
>111: DP3 TEMP[14].x, TEMP[3].xyzz, TEMP[3].xyzz
>112: RSQ TEMP[14].x, TEMP[14].xxxx
>113: MUL TEMP[15].x, CONST[31].wwww, TEMP[14].xxxx
>114: RCP TEMP[15].x, TEMP[15].xxxx
>115: MOV_SAT TEMP[15].x, TEMP[15].xxxx
>116: ADD TEMP[15].x, IMM[0].yyyy, -TEMP[15].xxxx
>117: MUL TEMP[15].x, TEMP[15].xxxx, TEMP[14].xxxx
>118: MUL TEMP[3].xyz, -TEMP[3].xyzz, TEMP[14].xxxx
>119: DP3 TEMP[14].x, TEMP[3].xyzz, -CONST[31].xyzz
>120: MUL TEMP[14].x, TEMP[14].xxxx, CONST[29].wwww
>121: ADD_SAT TEMP[14].x, CONST[30].wwww, -TEMP[14].xxxx
>122: MUL TEMP[15].x, TEMP[15].xxxx, TEMP[14].xxxx
>123: DP3_SAT TEMP[14].x, TEMP[5].xyzz, TEMP[3].xyzz
>124: ADD TEMP[3].xyz, TEMP[4].xyzz, TEMP[3].xyzz
>125: DP3 TEMP[16].x, TEMP[3].xyzz, TEMP[3].xyzz
>126: RSQ TEMP[16].x, TEMP[16].xxxx
>127: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[16].xxxx
>128: DP3 TEMP[16].x, TEMP[3].xyzz, TEMP[5].xyzz
>129: DDX TEMP[17].x, TEMP[16].xxxx
>130: ABS TEMP[17].x, TEMP[17].xxxx
>131: MUL TEMP[19], CONST[54].xxxx, TEMP[16].xxxx
>132: DDY TEMP[18].x, TEMP[19]
>133: ABS TEMP[18].x, TEMP[18].xxxx
>134: ADD TEMP[17].x, TEMP[17].xxxx, TEMP[18].xxxx
>135: MAD TEMP[17].x, TEMP[17].xxxx, IMM[1].zzzz, IMM[2].zzzz
>136: MAD_SAT TEMP[16].xy, TEMP[17].xxxx, IMM[0].zyyy, TEMP[16].xxxx
>137: DP3_SAT TEMP[3].x, TEMP[3].xyzz, TEMP[4].xyzz
>138: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[3].xxxx
>139: POW TEMP[3].x, TEMP[3].xxxx, IMM[1].wwww
>140: MUL TEMP[3].x, TEMP[3].xxxx, CONST[3].wwww
>141: MUL TEMP[3].xy, TEMP[12].xyyy, TEMP[3].xxxx
>142: ADD TEMP[3].xy, TEMP[12].xyyy, -TEMP[3].xyyy
>143: POW TEMP[12].x, TEMP[3].xxxx, IMM[1].wwww
>144: POW TEMP[12].y, TEMP[3].yyyy, IMM[1].wwww
>145: ADD_SAT TEMP[3].xy, TEMP[12].xyyy, IMM[2].wwww
>146: MUL TEMP[12], TEMP[16].xyxy, TEMP[3].xxyy
>147: ADD TEMP[17], TEMP[3].xxyy, IMM[0].zzzz
>148: MAD TEMP[17], TEMP[16].xyxy, TEMP[17], IMM[0].yyyy
>149: RCP TEMP[18].x, TEMP[17].xxxx
>150: RCP TEMP[18].y, TEMP[17].yyyy
>151: RCP TEMP[18].z, TEMP[17].zzzz
>152: RCP TEMP[18].w, TEMP[17].wwww
>153: MUL_SAT TEMP[12], TEMP[12], TEMP[18]
>154: ADD TEMP[12].xy, TEMP[12].ywww, -TEMP[12].xzzz
>155: ADD TEMP[16].x, TEMP[16].yyyy, -TEMP[16].xxxx
>156: ADD TEMP[16].x, TEMP[16].xxxx, IMM[3].xxxx
>157: DP3_SAT TEMP[17].x, TEMP[5].xyzz, TEMP[4].xyzz
>158: MUL TEMP[17].x, TEMP[17].xxxx, TEMP[14].xxxx
>159: MAX TEMP[17].x, TEMP[17].xxxx, IMM[3].yyyy
>160: RSQ TEMP[18].x, TEMP[17].xxxx
>161: MUL TEMP[18].x, TEMP[18].xxxx, TEMP[17].xxxx
>162: CMP TEMP[18].x, -TEMP[17].xxxx, TEMP[18].xxxx, IMM[0].xxxx
>163: LRP TEMP[3].xy, TEMP[3].xyyy, IMM[0].yyyy, TEMP[18].xxxx
>164: MUL TEMP[3].xy, TEMP[16].xxxx, TEMP[3].xyyy
>165: RCP TEMP[16].x, TEMP[3].xxxx
>166: RCP TEMP[16].y, TEMP[3].yyyy
>167: MUL TEMP[3].y, TEMP[12].xyyy, TEMP[16].xyyy
>168: MUL TEMP[12].xyz, CONST[1].xyzz, TEMP[11].yyyy
>169: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[11].yyyy
>170: LRP TEMP[3].xyz, TEMP[11].xyzz, TEMP[3].yyyy, TEMP[13].xyzz
>171: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[14].xxxx
>172: MUL TEMP[3].xyz, TEMP[3].xyzz, CONST[29].xyzz
>173: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[15].xxxx
>174: DP4 TEMP[11].x, IN[2], CONST[35]
>175: DP4 TEMP[12].x, IN[2], CONST[36]
>176: MOV TEMP[11].y, TEMP[12].xxxx
>177: DP4 TEMP[12].x, IN[2], CONST[37]
>178: DP4 TEMP[13].x, IN[2], CONST[38]
>179: RCP TEMP[13].x, TEMP[13].xxxx
>180: MUL TEMP[11].xy, TEMP[11].xyyy, TEMP[13].xxxx
>181: MAD TEMP[11].xy, TEMP[11].xyyy, IMM[1].zzzz, IMM[1].zzzz
>182: MAD TEMP[13].xy, TEMP[11].xyyy, CONST[34].xyyy, CONST[34].zwww
>183: MOV TEMP[13].xy, TEMP[13].xyyy
>184: TEX TEMP[13].xyz, TEMP[13], SAMP[1], 2D
>185: MOV TEMP[11].xy, TEMP[11].xyyy
>186: MOV TEMP[11].w, IMM[0].xxxx
>187: TXL TEMP[11].xy, TEMP[11], SAMP[0], 2D
>188: ADD TEMP[14].x, IMM[0].yyyy, -TEMP[11].yyyy
>189: MUL TEMP[14].x, TEMP[14].xxxx, IMM[3].zzzz
>190: ADD TEMP[14].x, TEMP[11].xxxx, -TEMP[14].xxxx
>191: ADD TEMP[12].x, TEMP[11].xxxx, -TEMP[12].xxxx
>192: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[11].xxxx
>193: ADD TEMP[11].x, TEMP[14].xxxx, -TEMP[11].xxxx
>194: MAX TEMP[11].x, TEMP[11].xxxx, CONST[32].xxxx
>195: MAD TEMP[14].x, TEMP[12].xxxx, TEMP[12].xxxx, TEMP[11].xxxx
>196: RCP TEMP[14].x, TEMP[14].xxxx
>197: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[14].xxxx
>198: POW TEMP[11].x, TEMP[11].xxxx, CONST[32].yyyy
>199: MAD_SAT TEMP[11].x, TEMP[11].xxxx, CONST[33].zzzz, CONST[33].wwww
>200: MUL TEMP[14].x, TEMP[11].xxxx, TEMP[11].xxxx
>201: MUL TEMP[11].x, IMM[2].xxxx, TEMP[11].xxxx
>202: ADD TEMP[11].x, IMM[3].wwww, -TEMP[11].xxxx
>203: MUL TEMP[11].x, TEMP[14].xxxx, TEMP[11].xxxx
>204: FSGE TEMP[12].x, TEMP[12].xxxx, IMM[0].xxxx
>205: UIF TEMP[12].xxxx :3
>206:   MOV TEMP[12].x, IMM[0].yyyy
>207: ELSE :3
>208:   MOV TEMP[12].x, TEMP[11].xxxx
>209: ENDIF
>210: MUL TEMP[11].xyz, TEMP[13].xyzz, TEMP[12].xxxx
>211: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[11].xyzz
>212: MAD TEMP[8].xyz, TEMP[3].xyzz, TEMP[6].xxxx, TEMP[2].xyzz
>213: LRP TEMP[2].x, TEMP[7].wwww, TEMP[9].wwww, IMM[0].yyyy
>214: MOV TEMP[10].w, TEMP[2].xxxx
>215: LRP TEMP[2], CONST[9].xxxy, TEMP[10], IMM[0].yyyy
>216: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[2].wwww
>217: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[2].xyzz
>218: DP3 TEMP[2].x, TEMP[5].xyzz, TEMP[4].xyzz
>219: ABS TEMP[2].x, TEMP[2].xxxx
>220: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
>221: MAD_SAT TEMP[2].x, TEMP[2].xxxx, CONST[13].xxxx, CONST[13].yyyy
>222: ADD TEMP[2].x, IMM[0].yyyy, -TEMP[2].xxxx
>223: MUL TEMP[2], CONST[4].zzzw, TEMP[2].xxxx
>224: LRP TEMP[2], TEMP[2], CONST[4].xxxy, TEMP[8]
>225: MIN TEMP[3].xyz, TEMP[2].xyzz, IMM[4].xxxx
>226: MAX TEMP[8].xyz, TEMP[3].xyzz, IMM[4].yyyy
>227: MAD_SAT TEMP[2].x, TEMP[2].wwww, CONST[13].zzzz, CONST[13].wwww
>228: MOV TEMP[8].w, TEMP[2].xxxx
>229: MOV OUT[0], TEMP[8]
>230: END
>; ModuleID = 'tgsi'
>
>@ddxy_lds = external addrspace(3) global [64 x i32]
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 28)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %21, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %21, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %21, i32 160)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %21, i32 168)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %21, i32 172)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %21, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %21, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %21, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %21, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %21, i32 220)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %21, i32 224)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %21, i32 228)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %21, i32 232)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %21, i32 236)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %21, i32 484)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %21, i32 488)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %21, i32 492)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %21, i32 496)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %21, i32 500)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %21, i32 504)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %21, i32 508)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %21, i32 512)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %21, i32 516)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %21, i32 536)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %21, i32 540)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %21, i32 544)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %21, i32 548)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %21, i32 552)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %21, i32 556)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %21, i32 560)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %21, i32 564)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %21, i32 568)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %21, i32 572)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %21, i32 576)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %21, i32 580)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %21, i32 584)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %21, i32 588)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %21, i32 592)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %21, i32 596)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %21, i32 600)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %21, i32 604)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %21, i32 608)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %21, i32 612)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %21, i32 616)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %21, i32 620)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %21, i32 864)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %21, i32 868)
>  %99 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %100 = load <32 x i8> addrspace(2)* %99, !tbaa !0
>  %101 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %102 = load <16 x i8> addrspace(2)* %101, !tbaa !0
>  %103 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %104 = load <32 x i8> addrspace(2)* %103, !tbaa !0
>  %105 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %106 = load <16 x i8> addrspace(2)* %105, !tbaa !0
>  %107 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %108 = load <32 x i8> addrspace(2)* %107, !tbaa !0
>  %109 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %110 = load <16 x i8> addrspace(2)* %109, !tbaa !0
>  %111 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
>  %112 = load <32 x i8> addrspace(2)* %111, !tbaa !0
>  %113 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
>  %114 = load <16 x i8> addrspace(2)* %113, !tbaa !0
>  %115 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
>  %116 = load <32 x i8> addrspace(2)* %115, !tbaa !0
>  %117 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
>  %118 = load <16 x i8> addrspace(2)* %117, !tbaa !0
>  %119 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
>  %120 = load <32 x i8> addrspace(2)* %119, !tbaa !0
>  %121 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
>  %122 = load <16 x i8> addrspace(2)* %121, !tbaa !0
>  %123 = getelementptr <32 x i8> addrspace(2)* %2, i32 6
>  %124 = load <32 x i8> addrspace(2)* %123, !tbaa !0
>  %125 = getelementptr <16 x i8> addrspace(2)* %1, i32 6
>  %126 = load <16 x i8> addrspace(2)* %125, !tbaa !0
>  %127 = getelementptr <32 x i8> addrspace(2)* %2, i32 7
>  %128 = load <32 x i8> addrspace(2)* %127, !tbaa !0
>  %129 = getelementptr <16 x i8> addrspace(2)* %1, i32 7
>  %130 = load <16 x i8> addrspace(2)* %129, !tbaa !0
>  %131 = getelementptr <32 x i8> addrspace(2)* %2, i32 8
>  %132 = load <32 x i8> addrspace(2)* %131, !tbaa !0
>  %133 = getelementptr <16 x i8> addrspace(2)* %1, i32 8
>  %134 = load <16 x i8> addrspace(2)* %133, !tbaa !0
>  %135 = fcmp ugt float %16, 0.000000e+00
>  %136 = select i1 %135, float 1.000000e+00, float 0.000000e+00
>  %137 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %138 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %139 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %140 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %141 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %142 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %143 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
>  %144 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %145 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %146 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %147 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
>  %148 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %149 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %150 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %151 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %152 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %153 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
>  %154 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %155 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
>  %156 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
>  %157 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
>  %158 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %3, <2 x i32> %5)
>  %159 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %5)
>  %160 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %5)
>  %161 = fmul float %13, %97
>  %162 = fadd float %161, %98
>  %163 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
>  %164 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %165 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %166 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %167 = bitcast float %163 to i32
>  %168 = icmp ne i32 %167, 0
>  %. = select i1 %168, float -1.000000e+00, float 1.000000e+00
>  %169 = fsub float -0.000000e+00, %137
>  %170 = fadd float %47, %169
>  %171 = fsub float -0.000000e+00, %138
>  %172 = fadd float %48, %171
>  %173 = fsub float -0.000000e+00, %139
>  %174 = fadd float %49, %173
>  %175 = fmul float %170, %170
>  %176 = fmul float %172, %172
>  %177 = fadd float %176, %175
>  %178 = fmul float %174, %174
>  %179 = fadd float %177, %178
>  %180 = call float @llvm.AMDGPU.rsq(float %179)
>  %181 = fmul float %170, %180
>  %182 = fmul float %172, %180
>  %183 = fmul float %174, %180
>  %184 = fmul float %., %60
>  %185 = fmul float %12, %50
>  %186 = fmul float %162, %51
>  %187 = bitcast float %147 to i32
>  %188 = bitcast float %148 to i32
>  %189 = insertelement <2 x i32> undef, i32 %187, i32 0
>  %190 = insertelement <2 x i32> %189, i32 %188, i32 1
>  %191 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %190, <32 x i8> %108, <16 x i8> %110, i32 2)
>  %192 = extractelement <4 x float> %191, i32 0
>  %193 = extractelement <4 x float> %191, i32 1
>  %194 = extractelement <4 x float> %191, i32 2
>  %195 = extractelement <4 x float> %191, i32 3
>  %196 = fmul float %192, 0x4012611180000000
>  %197 = fmul float %193, 0x4012611180000000
>  %198 = fmul float %194, 0x4012611180000000
>  %199 = call float @llvm.AMDGPU.lrp(float %29, float %196, float 1.000000e+00)
>  %200 = call float @llvm.AMDGPU.lrp(float %29, float %197, float 1.000000e+00)
>  %201 = call float @llvm.AMDGPU.lrp(float %29, float %198, float 1.000000e+00)
>  %202 = bitcast float %149 to i32
>  %203 = bitcast float %150 to i32
>  %204 = insertelement <2 x i32> undef, i32 %202, i32 0
>  %205 = insertelement <2 x i32> %204, i32 %203, i32 1
>  %206 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %205, <32 x i8> %116, <16 x i8> %118, i32 2)
>  %207 = extractelement <4 x float> %206, i32 0
>  %208 = extractelement <4 x float> %206, i32 1
>  %209 = extractelement <4 x float> %206, i32 2
>  %210 = extractelement <4 x float> %206, i32 3
>  %211 = bitcast float %141 to i32
>  %212 = bitcast float %142 to i32
>  %213 = insertelement <2 x i32> undef, i32 %211, i32 0
>  %214 = insertelement <2 x i32> %213, i32 %212, i32 1
>  %215 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %214, <32 x i8> %112, <16 x i8> %114, i32 2)
>  %216 = extractelement <4 x float> %215, i32 0
>  %217 = extractelement <4 x float> %215, i32 1
>  %218 = extractelement <4 x float> %215, i32 2
>  %219 = extractelement <4 x float> %215, i32 3
>  %220 = fmul float %216, %22
>  %221 = fmul float %217, %23
>  %222 = fmul float %218, %24
>  %223 = fmul float %219, %25
>  %224 = fmul float %220, %151
>  %225 = fmul float %221, %152
>  %226 = fmul float %222, %153
>  %227 = fmul float %223, %154
>  %228 = fsub float -0.000000e+00, %219
>  %229 = fadd float 1.000000e+00, %228
>  %230 = fmul float %229, %52
>  %231 = call float @llvm.AMDGPU.lrp(float %230, float %216, float %224)
>  %232 = call float @llvm.AMDGPU.lrp(float %230, float %217, float %225)
>  %233 = call float @llvm.AMDGPU.lrp(float %230, float %218, float %226)
>  %234 = bitcast float %143 to i32
>  %235 = bitcast float %144 to i32
>  %236 = insertelement <2 x i32> undef, i32 %234, i32 0
>  %237 = insertelement <2 x i32> %236, i32 %235, i32 1
>  %238 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %237, <32 x i8> %120, <16 x i8> %122, i32 2)
>  %239 = extractelement <4 x float> %238, i32 0
>  %240 = extractelement <4 x float> %238, i32 1
>  %241 = extractelement <4 x float> %238, i32 3
>  %242 = fmul float %57, %241
>  %243 = fmul float %58, %239
>  %244 = fsub float -0.000000e+00, %242
>  %245 = fadd float 1.000000e+00, %244
>  %246 = fsub float -0.000000e+00, %243
>  %247 = fadd float 1.000000e+00, %246
>  %248 = fmul float %231, %199
>  %249 = fmul float %232, %200
>  %250 = fmul float %233, %201
>  %251 = fmul float %227, %195
>  %252 = fmul float %155, %155
>  %253 = fmul float %156, %156
>  %254 = fadd float %253, %252
>  %255 = fmul float %157, %157
>  %256 = fadd float %254, %255
>  %257 = call float @llvm.AMDGPU.rsq(float %256)
>  %258 = fmul float %155, %257
>  %259 = fmul float %156, %257
>  %260 = fmul float %157, %257
>  %261 = fcmp olt float 0.000000e+00, %184
>  %262 = sext i1 %261 to i32
>  %263 = bitcast i32 %262 to float
>  %264 = bitcast float %263 to i32
>  %265 = icmp ne i32 %264, 0
>  br i1 %265, label %IF93, label %ENDIF92
>
>IF93:                                             ; preds = %main_body
>  %266 = fsub float -0.000000e+00, %258
>  %267 = fsub float -0.000000e+00, %259
>  %268 = fsub float -0.000000e+00, %260
>  br label %ENDIF92
>
>ENDIF92:                                          ; preds = %main_body, %IF93
>  %temp20.0 = phi float [ %266, %IF93 ], [ %258, %main_body ]
>  %temp21.0 = phi float [ %267, %IF93 ], [ %259, %main_body ]
>  %temp22.0 = phi float [ %268, %IF93 ], [ %260, %main_body ]
>  %269 = bitcast float %185 to i32
>  %270 = bitcast float %186 to i32
>  %271 = insertelement <2 x i32> undef, i32 %269, i32 0
>  %272 = insertelement <2 x i32> %271, i32 %270, i32 1
>  %273 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %272, <32 x i8> %132, <16 x i8> %134, i32 2)
>  %274 = extractelement <4 x float> %273, i32 0
>  %275 = extractelement <4 x float> %273, i32 1
>  %276 = extractelement <4 x float> %273, i32 2
>  %277 = extractelement <4 x float> %273, i32 3
>  %278 = fmul float %274, %43
>  %279 = fadd float %278, %44
>  %280 = fmul float %275, %43
>  %281 = fadd float %280, %44
>  %282 = fmul float %276, %43
>  %283 = fadd float %282, %44
>  %284 = fmul float %277, %45
>  %285 = fadd float %284, %46
>  %286 = bitcast float %145 to i32
>  %287 = bitcast float %146 to i32
>  %288 = insertelement <2 x i32> undef, i32 %286, i32 0
>  %289 = insertelement <2 x i32> %288, i32 %287, i32 1
>  %290 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %289, <32 x i8> %124, <16 x i8> %126, i32 2)
>  %291 = extractelement <4 x float> %290, i32 0
>  %292 = extractelement <4 x float> %290, i32 1
>  %293 = extractelement <4 x float> %290, i32 2
>  %294 = extractelement <4 x float> %290, i32 3
>  %295 = fmul float %294, 3.200000e+01
>  %296 = fadd float %295, -1.600000e+01
>  %297 = call float @llvm.AMDIL.exp.(float %296)
>  %298 = fmul float %291, %297
>  %299 = fmul float %292, %297
>  %300 = fmul float %293, %297
>  %301 = fmul float %33, %298
>  %302 = fadd float %301, %158
>  %303 = fmul float %34, %299
>  %304 = fadd float %303, %159
>  %305 = fmul float %35, %300
>  %306 = fadd float %305, %160
>  %307 = fmul float %302, %285
>  %308 = fmul float %304, %285
>  %309 = fmul float %306, %285
>  %310 = fmul float %285, 5.000000e-01
>  %311 = fadd float %310, 5.000000e-01
>  %312 = fmul float %temp20.0, %181
>  %313 = fmul float %temp21.0, %182
>  %314 = fadd float %313, %312
>  %315 = fmul float %temp22.0, %183
>  %316 = fadd float %314, %315
>  %317 = call float @llvm.AMDIL.clamp.(float %316, float 0.000000e+00, float 1.000000e+00)
>  %318 = fsub float -0.000000e+00, %317
>  %319 = fadd float 1.000000e+00, %318
>  %320 = call float @llvm.pow.f32(float %319, float 4.000000e+00)
>  %321 = fmul float %320, %36
>  %322 = fmul float %247, %321
>  %323 = fsub float -0.000000e+00, %322
>  %324 = fadd float %247, %323
>  %325 = fmul float %temp20.0, %181
>  %326 = fmul float %temp21.0, %182
>  %327 = fadd float %326, %325
>  %328 = fmul float %temp22.0, %183
>  %329 = fadd float %327, %328
>  %330 = fmul float %329, %temp20.0
>  %331 = fmul float %329, %temp21.0
>  %332 = fmul float %329, %temp22.0
>  %333 = fmul float 2.000000e+00, %330
>  %334 = fmul float 2.000000e+00, %331
>  %335 = fmul float 2.000000e+00, %332
>  %336 = fsub float -0.000000e+00, %333
>  %337 = fadd float %181, %336
>  %338 = fsub float -0.000000e+00, %334
>  %339 = fadd float %182, %338
>  %340 = fsub float -0.000000e+00, %335
>  %341 = fadd float %183, %340
>  %342 = fsub float -0.000000e+00, %temp20.0
>  %343 = call float @llvm.AMDGPU.lrp(float %324, float %342, float %337)
>  %344 = fsub float -0.000000e+00, %temp21.0
>  %345 = call float @llvm.AMDGPU.lrp(float %324, float %344, float %339)
>  %346 = fsub float -0.000000e+00, %temp22.0
>  %347 = call float @llvm.AMDGPU.lrp(float %324, float %346, float %341)
>  %348 = call float @fabs(float %343)
>  %349 = call float @fabs(float %345)
>  %350 = call float @fabs(float %347)
>  %351 = fcmp uge float %349, %350
>  %352 = select i1 %351, float %349, float %350
>  %353 = fcmp uge float %348, %352
>  %354 = select i1 %353, float %348, float %352
>  %355 = fadd float %354, 0xBF50624DE0000000
>  %356 = fcmp oge float %355, %348
>  %357 = sext i1 %356 to i32
>  %358 = bitcast i32 %357 to float
>  %359 = bitcast float %358 to i32
>  %360 = and i32 %359, 1065353216
>  %361 = bitcast i32 %360 to float
>  %362 = fcmp oge float %355, %349
>  %363 = sext i1 %362 to i32
>  %364 = bitcast i32 %363 to float
>  %365 = bitcast float %364 to i32
>  %366 = and i32 %365, 1065353216
>  %367 = bitcast i32 %366 to float
>  %368 = fcmp oge float %355, %350
>  %369 = sext i1 %368 to i32
>  %370 = bitcast i32 %369 to float
>  %371 = bitcast float %370 to i32
>  %372 = and i32 %371, 1065353216
>  %373 = bitcast i32 %372 to float
>  %374 = fdiv float 1.000000e+00, %354
>  %375 = fmul float -1.000000e+00, %374
>  %376 = fmul float -1.000000e+00, %374
>  %377 = fmul float 1.000000e+00, %374
>  %378 = fmul float %343, %375
>  %379 = fmul float %345, %376
>  %380 = fmul float %347, %377
>  %381 = fadd float %59, -1.000000e+00
>  %382 = fmul float %324, %381
>  %383 = fmul float %378, %361
>  %384 = fmul float %379, %367
>  %385 = fmul float %380, %373
>  %386 = call float @floor(float %382)
>  %387 = fsub float -0.000000e+00, %386
>  %388 = fadd float %59, %387
>  %389 = call float @llvm.AMDIL.exp.(float %388)
>  %390 = fdiv float 1.000000e+00, %389
>  %391 = fmul float %383, %390
>  %392 = fmul float %384, %390
>  %393 = fmul float %385, %390
>  %394 = fsub float -0.000000e+00, %391
>  %395 = fadd float %378, %394
>  %396 = fsub float -0.000000e+00, %392
>  %397 = fadd float %379, %396
>  %398 = fsub float -0.000000e+00, %393
>  %399 = fadd float %380, %398
>  %400 = insertelement <4 x float> undef, float %395, i32 0
>  %401 = insertelement <4 x float> %400, float %397, i32 1
>  %402 = insertelement <4 x float> %401, float %399, i32 2
>  %403 = insertelement <4 x float> %402, float %382, i32 3
>  %404 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %403)
>  %405 = extractelement <4 x float> %404, i32 0
>  %406 = extractelement <4 x float> %404, i32 1
>  %407 = extractelement <4 x float> %404, i32 2
>  %408 = extractelement <4 x float> %404, i32 3
>  %409 = call float @fabs(float %407)
>  %410 = fdiv float 1.000000e+00, %409
>  %411 = fmul float %405, %410
>  %412 = fadd float %411, 1.500000e+00
>  %413 = fmul float %406, %410
>  %414 = fadd float %413, 1.500000e+00
>  %415 = bitcast float %414 to i32
>  %416 = bitcast float %412 to i32
>  %417 = bitcast float %408 to i32
>  %418 = bitcast float %382 to i32
>  %419 = insertelement <4 x i32> undef, i32 %415, i32 0
>  %420 = insertelement <4 x i32> %419, i32 %416, i32 1
>  %421 = insertelement <4 x i32> %420, i32 %417, i32 2
>  %422 = insertelement <4 x i32> %421, i32 %418, i32 3
>  %423 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %422, <32 x i8> %128, <16 x i8> %130, i32 4)
>  %424 = extractelement <4 x float> %423, i32 0
>  %425 = extractelement <4 x float> %423, i32 1
>  %426 = extractelement <4 x float> %423, i32 2
>  %427 = extractelement <4 x float> %423, i32 3
>  %428 = fmul float %427, 3.200000e+01
>  %429 = fadd float %428, -1.600000e+01
>  %430 = call float @llvm.AMDIL.exp.(float %429)
>  %431 = fmul float %424, %430
>  %432 = fmul float %425, %430
>  %433 = fmul float %426, %430
>  %434 = fmul float %26, %240
>  %435 = fmul float %27, %240
>  %436 = fmul float %28, %240
>  %437 = fmul float %434, %240
>  %438 = fmul float %435, %240
>  %439 = fmul float %436, %240
>  %440 = fmul float %324, 2.000000e+00
>  %441 = fadd float %440, -1.000000e+00
>  %442 = call float @llvm.AMDIL.clamp.(float %441, float 0.000000e+00, float 1.000000e+00)
>  %443 = fmul float %279, %311
>  %444 = fmul float %281, %311
>  %445 = fmul float %283, %311
>  %446 = fmul float %431, %30
>  %447 = fmul float %432, %31
>  %448 = fmul float %433, %32
>  %449 = fmul float %437, %446
>  %450 = fmul float %438, %447
>  %451 = fmul float %439, %448
>  %452 = call float @llvm.AMDGPU.lrp(float %442, float %437, float %449)
>  %453 = call float @llvm.AMDGPU.lrp(float %442, float %438, float %450)
>  %454 = call float @llvm.AMDGPU.lrp(float %442, float %439, float %451)
>  %455 = call float @llvm.AMDGPU.lrp(float %321, float 1.000000e+00, float %437)
>  %456 = call float @llvm.AMDGPU.lrp(float %321, float 1.000000e+00, float %438)
>  %457 = call float @llvm.AMDGPU.lrp(float %321, float 1.000000e+00, float %439)
>  %458 = call float @llvm.AMDGPU.lrp(float %455, float %452, float %248)
>  %459 = call float @llvm.AMDGPU.lrp(float %456, float %453, float %249)
>  %460 = call float @llvm.AMDGPU.lrp(float %457, float %454, float %250)
>  %461 = fmul float %307, %458
>  %462 = fmul float %308, %459
>  %463 = fmul float %309, %460
>  %464 = fmul float %443, %248
>  %465 = fadd float %464, %461
>  %466 = fmul float %444, %249
>  %467 = fadd float %466, %462
>  %468 = fmul float %445, %250
>  %469 = fadd float %468, %463
>  %470 = fsub float -0.000000e+00, %65
>  %471 = fadd float %137, %470
>  %472 = fsub float -0.000000e+00, %66
>  %473 = fadd float %138, %472
>  %474 = fsub float -0.000000e+00, %67
>  %475 = fadd float %139, %474
>  %476 = fmul float %471, %471
>  %477 = fmul float %473, %473
>  %478 = fadd float %477, %476
>  %479 = fmul float %475, %475
>  %480 = fadd float %478, %479
>  %481 = call float @llvm.AMDGPU.rsq(float %480)
>  %482 = fmul float %72, %481
>  %483 = fdiv float 1.000000e+00, %482
>  %484 = call float @llvm.AMDIL.clamp.(float %483, float 0.000000e+00, float 1.000000e+00)
>  %485 = fsub float -0.000000e+00, %484
>  %486 = fadd float 1.000000e+00, %485
>  %487 = fmul float %486, %481
>  %488 = fsub float -0.000000e+00, %471
>  %489 = fmul float %488, %481
>  %490 = fsub float -0.000000e+00, %473
>  %491 = fmul float %490, %481
>  %492 = fsub float -0.000000e+00, %475
>  %493 = fmul float %492, %481
>  %494 = fsub float -0.000000e+00, %69
>  %495 = fsub float -0.000000e+00, %70
>  %496 = fsub float -0.000000e+00, %71
>  %497 = fmul float %489, %494
>  %498 = fmul float %491, %495
>  %499 = fadd float %498, %497
>  %500 = fmul float %493, %496
>  %501 = fadd float %499, %500
>  %502 = fmul float %501, %64
>  %503 = fsub float -0.000000e+00, %502
>  %504 = fadd float %68, %503
>  %505 = call float @llvm.AMDIL.clamp.(float %504, float 0.000000e+00, float 1.000000e+00)
>  %506 = fmul float %487, %505
>  %507 = fmul float %temp20.0, %489
>  %508 = fmul float %temp21.0, %491
>  %509 = fadd float %508, %507
>  %510 = fmul float %temp22.0, %493
>  %511 = fadd float %509, %510
>  %512 = call float @llvm.AMDIL.clamp.(float %511, float 0.000000e+00, float 1.000000e+00)
>  %513 = fadd float %181, %489
>  %514 = fadd float %182, %491
>  %515 = fadd float %183, %493
>  %516 = fmul float %513, %513
>  %517 = fmul float %514, %514
>  %518 = fadd float %517, %516
>  %519 = fmul float %515, %515
>  %520 = fadd float %518, %519
>  %521 = call float @llvm.AMDGPU.rsq(float %520)
>  %522 = fmul float %513, %521
>  %523 = fmul float %514, %521
>  %524 = fmul float %515, %521
>  %525 = fmul float %522, %temp20.0
>  %526 = fmul float %523, %temp21.0
>  %527 = fadd float %526, %525
>  %528 = fmul float %524, %temp22.0
>  %529 = fadd float %527, %528
>  %530 = call i32 @llvm.SI.tid()
>  %531 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %530
>  %532 = and i32 %530, -4
>  %533 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %532
>  %534 = add i32 %532, 1
>  %535 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %534
>  %536 = bitcast float %529 to i32
>  store i32 %536, i32 addrspace(3)* %531
>  %537 = load i32 addrspace(3)* %533
>  %538 = bitcast i32 %537 to float
>  %539 = load i32 addrspace(3)* %535
>  %540 = bitcast i32 %539 to float
>  %541 = fsub float %540, %538
>  %542 = insertelement <4 x float> undef, float %541, i32 0
>  %543 = insertelement <4 x float> %542, float %541, i32 1
>  %544 = insertelement <4 x float> %543, float %541, i32 2
>  %545 = insertelement <4 x float> %544, float %541, i32 3
>  %546 = extractelement <4 x float> %545, i32 0
>  %547 = call float @fabs(float %546)
>  %548 = fmul float %97, %529
>  %549 = fmul float %97, %529
>  %550 = fmul float %97, %529
>  %551 = fmul float %97, %529
>  %552 = call i32 @llvm.SI.tid()
>  %553 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %552
>  %554 = and i32 %552, -4
>  %555 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %554
>  %556 = add i32 %554, 2
>  %557 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %556
>  %558 = bitcast float %548 to i32
>  store i32 %558, i32 addrspace(3)* %553
>  %559 = load i32 addrspace(3)* %555
>  %560 = bitcast i32 %559 to float
>  %561 = load i32 addrspace(3)* %557
>  %562 = bitcast i32 %561 to float
>  %563 = fsub float %562, %560
>  %564 = bitcast float %549 to i32
>  store i32 %564, i32 addrspace(3)* %553
>  %565 = load i32 addrspace(3)* %555
>  %566 = bitcast i32 %565 to float
>  %567 = load i32 addrspace(3)* %557
>  %568 = bitcast i32 %567 to float
>  %569 = fsub float %568, %566
>  %570 = bitcast float %550 to i32
>  store i32 %570, i32 addrspace(3)* %553
>  %571 = load i32 addrspace(3)* %555
>  %572 = bitcast i32 %571 to float
>  %573 = load i32 addrspace(3)* %557
>  %574 = bitcast i32 %573 to float
>  %575 = fsub float %574, %572
>  %576 = bitcast float %551 to i32
>  store i32 %576, i32 addrspace(3)* %553
>  %577 = load i32 addrspace(3)* %555
>  %578 = bitcast i32 %577 to float
>  %579 = load i32 addrspace(3)* %557
>  %580 = bitcast i32 %579 to float
>  %581 = fsub float %580, %578
>  %582 = insertelement <4 x float> undef, float %563, i32 0
>  %583 = insertelement <4 x float> %582, float %569, i32 1
>  %584 = insertelement <4 x float> %583, float %575, i32 2
>  %585 = insertelement <4 x float> %584, float %581, i32 3
>  %586 = extractelement <4 x float> %585, i32 0
>  %587 = call float @fabs(float %586)
>  %588 = fadd float %547, %587
>  %589 = fmul float %588, 5.000000e-01
>  %590 = fadd float %589, 0x3EE4F8B580000000
>  %591 = fmul float %590, -1.000000e+00
>  %592 = fadd float %591, %529
>  %593 = fmul float %590, 1.000000e+00
>  %594 = fadd float %593, %529
>  %595 = call float @llvm.AMDIL.clamp.(float %592, float 0.000000e+00, float 1.000000e+00)
>  %596 = call float @llvm.AMDIL.clamp.(float %594, float 0.000000e+00, float 1.000000e+00)
>  %597 = fmul float %522, %181
>  %598 = fmul float %523, %182
>  %599 = fadd float %598, %597
>  %600 = fmul float %524, %183
>  %601 = fadd float %599, %600
>  %602 = call float @llvm.AMDIL.clamp.(float %601, float 0.000000e+00, float 1.000000e+00)
>  %603 = fsub float -0.000000e+00, %602
>  %604 = fadd float 1.000000e+00, %603
>  %605 = call float @llvm.pow.f32(float %604, float 4.000000e+00)
>  %606 = fmul float %605, %36
>  %607 = fmul float %245, %606
>  %608 = fmul float %247, %606
>  %609 = fsub float -0.000000e+00, %607
>  %610 = fadd float %245, %609
>  %611 = fsub float -0.000000e+00, %608
>  %612 = fadd float %247, %611
>  %613 = call float @llvm.pow.f32(float %610, float 4.000000e+00)
>  %614 = call float @llvm.pow.f32(float %612, float 4.000000e+00)
>  %615 = fadd float %613, 0x3E7AD7F2A0000000
>  %616 = fadd float %614, 0x3E7AD7F2A0000000
>  %617 = call float @llvm.AMDIL.clamp.(float %615, float 0.000000e+00, float 1.000000e+00)
>  %618 = call float @llvm.AMDIL.clamp.(float %616, float 0.000000e+00, float 1.000000e+00)
>  %619 = fmul float %595, %617
>  %620 = fmul float %596, %617
>  %621 = fmul float %595, %618
>  %622 = fmul float %596, %618
>  %623 = fadd float %617, -1.000000e+00
>  %624 = fadd float %617, -1.000000e+00
>  %625 = fadd float %618, -1.000000e+00
>  %626 = fadd float %618, -1.000000e+00
>  %627 = fmul float %595, %623
>  %628 = fadd float %627, 1.000000e+00
>  %629 = fmul float %596, %624
>  %630 = fadd float %629, 1.000000e+00
>  %631 = fmul float %595, %625
>  %632 = fadd float %631, 1.000000e+00
>  %633 = fmul float %596, %626
>  %634 = fadd float %633, 1.000000e+00
>  %635 = fdiv float 1.000000e+00, %628
>  %636 = fdiv float 1.000000e+00, %630
>  %637 = fdiv float 1.000000e+00, %632
>  %638 = fdiv float 1.000000e+00, %634
>  %639 = fmul float %619, %635
>  %640 = fmul float %620, %636
>  %641 = fmul float %621, %637
>  %642 = fmul float %622, %638
>  %643 = call float @llvm.AMDIL.clamp.(float %639, float 0.000000e+00, float 1.000000e+00)
>  %644 = call float @llvm.AMDIL.clamp.(float %640, float 0.000000e+00, float 1.000000e+00)
>  %645 = call float @llvm.AMDIL.clamp.(float %641, float 0.000000e+00, float 1.000000e+00)
>  %646 = call float @llvm.AMDIL.clamp.(float %642, float 0.000000e+00, float 1.000000e+00)
>  %647 = fsub float -0.000000e+00, %645
>  %648 = fadd float %646, %647
>  %649 = fsub float -0.000000e+00, %595
>  %650 = fadd float %596, %649
>  %651 = fadd float %650, 0x3EB0C6F7A0000000
>  %652 = fmul float %temp20.0, %181
>  %653 = fmul float %temp21.0, %182
>  %654 = fadd float %653, %652
>  %655 = fmul float %temp22.0, %183
>  %656 = fadd float %654, %655
>  %657 = call float @llvm.AMDIL.clamp.(float %656, float 0.000000e+00, float 1.000000e+00)
>  %658 = fmul float %657, %512
>  %659 = fcmp uge float %658, 0x3F847AE140000000
>  %660 = select i1 %659, float %658, float 0x3F847AE140000000
>  %661 = call float @llvm.AMDGPU.rsq(float %660)
>  %662 = fmul float %661, %660
>  %663 = fsub float -0.000000e+00, %660
>  %664 = call float @llvm.AMDGPU.cndlt(float %663, float %662, float 0.000000e+00)
>  %665 = call float @llvm.AMDGPU.lrp(float %617, float 1.000000e+00, float %664)
>  %666 = call float @llvm.AMDGPU.lrp(float %618, float 1.000000e+00, float %664)
>  %667 = fmul float %651, %666
>  %668 = fdiv float 1.000000e+00, %667
>  %669 = fmul float %648, %668
>  %670 = fmul float %26, %240
>  %671 = fmul float %27, %240
>  %672 = fmul float %28, %240
>  %673 = fmul float %670, %240
>  %674 = fmul float %671, %240
>  %675 = fmul float %672, %240
>  %676 = call float @llvm.AMDGPU.lrp(float %673, float %669, float %248)
>  %677 = call float @llvm.AMDGPU.lrp(float %674, float %669, float %249)
>  %678 = call float @llvm.AMDGPU.lrp(float %675, float %669, float %250)
>  %679 = fmul float %676, %512
>  %680 = fmul float %677, %512
>  %681 = fmul float %678, %512
>  %682 = fmul float %679, %61
>  %683 = fmul float %680, %62
>  %684 = fmul float %681, %63
>  %685 = fmul float %682, %506
>  %686 = fmul float %683, %506
>  %687 = fmul float %684, %506
>  %688 = fmul float %137, %81
>  %689 = fmul float %138, %82
>  %690 = fadd float %688, %689
>  %691 = fmul float %139, %83
>  %692 = fadd float %690, %691
>  %693 = fmul float %140, %84
>  %694 = fadd float %692, %693
>  %695 = fmul float %137, %85
>  %696 = fmul float %138, %86
>  %697 = fadd float %695, %696
>  %698 = fmul float %139, %87
>  %699 = fadd float %697, %698
>  %700 = fmul float %140, %88
>  %701 = fadd float %699, %700
>  %702 = fmul float %137, %89
>  %703 = fmul float %138, %90
>  %704 = fadd float %702, %703
>  %705 = fmul float %139, %91
>  %706 = fadd float %704, %705
>  %707 = fmul float %140, %92
>  %708 = fadd float %706, %707
>  %709 = fmul float %137, %93
>  %710 = fmul float %138, %94
>  %711 = fadd float %709, %710
>  %712 = fmul float %139, %95
>  %713 = fadd float %711, %712
>  %714 = fmul float %140, %96
>  %715 = fadd float %713, %714
>  %716 = fdiv float 1.000000e+00, %715
>  %717 = fmul float %694, %716
>  %718 = fmul float %701, %716
>  %719 = fmul float %717, 5.000000e-01
>  %720 = fadd float %719, 5.000000e-01
>  %721 = fmul float %718, 5.000000e-01
>  %722 = fadd float %721, 5.000000e-01
>  %723 = fmul float %720, %77
>  %724 = fadd float %723, %79
>  %725 = fmul float %722, %78
>  %726 = fadd float %725, %80
>  %727 = bitcast float %724 to i32
>  %728 = bitcast float %726 to i32
>  %729 = insertelement <2 x i32> undef, i32 %727, i32 0
>  %730 = insertelement <2 x i32> %729, i32 %728, i32 1
>  %731 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %730, <32 x i8> %104, <16 x i8> %106, i32 2)
>  %732 = extractelement <4 x float> %731, i32 0
>  %733 = extractelement <4 x float> %731, i32 1
>  %734 = extractelement <4 x float> %731, i32 2
>  %735 = bitcast float %720 to i32
>  %736 = bitcast float %722 to i32
>  %737 = bitcast float 0.000000e+00 to i32
>  %738 = insertelement <4 x i32> undef, i32 %735, i32 0
>  %739 = insertelement <4 x i32> %738, i32 %736, i32 1
>  %740 = insertelement <4 x i32> %739, i32 %737, i32 2
>  %741 = insertelement <4 x i32> %740, i32 undef, i32 3
>  %742 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %741, <32 x i8> %100, <16 x i8> %102, i32 2)
>  %743 = extractelement <4 x float> %742, i32 0
>  %744 = extractelement <4 x float> %742, i32 1
>  %745 = fsub float -0.000000e+00, %744
>  %746 = fadd float 1.000000e+00, %745
>  %747 = fmul float %746, 2.500000e-01
>  %748 = fsub float -0.000000e+00, %747
>  %749 = fadd float %743, %748
>  %750 = fsub float -0.000000e+00, %708
>  %751 = fadd float %743, %750
>  %752 = fmul float %743, %743
>  %753 = fsub float -0.000000e+00, %752
>  %754 = fadd float %749, %753
>  %755 = fcmp uge float %754, %73
>  %756 = select i1 %755, float %754, float %73
>  %757 = fmul float %751, %751
>  %758 = fadd float %757, %756
>  %759 = fdiv float 1.000000e+00, %758
>  %760 = fmul float %756, %759
>  %761 = call float @llvm.pow.f32(float %760, float %74)
>  %762 = fmul float %761, %75
>  %763 = fadd float %762, %76
>  %764 = call float @llvm.AMDIL.clamp.(float %763, float 0.000000e+00, float 1.000000e+00)
>  %765 = fmul float %764, %764
>  %766 = fmul float 2.000000e+00, %764
>  %767 = fsub float -0.000000e+00, %766
>  %768 = fadd float 3.000000e+00, %767
>  %769 = fmul float %765, %768
>  %770 = fcmp oge float %751, 0.000000e+00
>  %771 = sext i1 %770 to i32
>  %772 = bitcast i32 %771 to float
>  %773 = bitcast float %772 to i32
>  %774 = icmp ne i32 %773, 0
>  %.98 = select i1 %774, float 1.000000e+00, float %769
>  %775 = fmul float %732, %.98
>  %776 = fmul float %733, %.98
>  %777 = fmul float %734, %.98
>  %778 = fmul float %685, %775
>  %779 = fmul float %686, %776
>  %780 = fmul float %687, %777
>  %781 = fmul float %778, %311
>  %782 = fadd float %781, %465
>  %783 = fmul float %779, %311
>  %784 = fadd float %783, %467
>  %785 = fmul float %780, %311
>  %786 = fadd float %785, %469
>  %787 = call float @llvm.AMDGPU.lrp(float %195, float %210, float 1.000000e+00)
>  %788 = call float @llvm.AMDGPU.lrp(float %41, float %207, float 1.000000e+00)
>  %789 = call float @llvm.AMDGPU.lrp(float %41, float %208, float 1.000000e+00)
>  %790 = call float @llvm.AMDGPU.lrp(float %41, float %209, float 1.000000e+00)
>  %791 = call float @llvm.AMDGPU.lrp(float %42, float %787, float 1.000000e+00)
>  %792 = fmul float %788, %791
>  %793 = fmul float %789, %791
>  %794 = fmul float %790, %791
>  %795 = fmul float %782, %792
>  %796 = fmul float %784, %793
>  %797 = fmul float %786, %794
>  %798 = fmul float %temp20.0, %181
>  %799 = fmul float %temp21.0, %182
>  %800 = fadd float %799, %798
>  %801 = fmul float %temp22.0, %183
>  %802 = fadd float %800, %801
>  %803 = call float @fabs(float %802)
>  %804 = fmul float %803, %803
>  %805 = fmul float %804, %53
>  %806 = fadd float %805, %54
>  %807 = call float @llvm.AMDIL.clamp.(float %806, float 0.000000e+00, float 1.000000e+00)
>  %808 = fsub float -0.000000e+00, %807
>  %809 = fadd float 1.000000e+00, %808
>  %810 = fmul float %39, %809
>  %811 = fmul float %39, %809
>  %812 = fmul float %39, %809
>  %813 = fmul float %40, %809
>  %814 = call float @llvm.AMDGPU.lrp(float %810, float %37, float %795)
>  %815 = call float @llvm.AMDGPU.lrp(float %811, float %37, float %796)
>  %816 = call float @llvm.AMDGPU.lrp(float %812, float %37, float %797)
>  %817 = call float @llvm.AMDGPU.lrp(float %813, float %38, float %251)
>  %818 = fcmp uge float %814, 6.550400e+04
>  %819 = select i1 %818, float 6.550400e+04, float %814
>  %820 = fcmp uge float %815, 6.550400e+04
>  %821 = select i1 %820, float 6.550400e+04, float %815
>  %822 = fcmp uge float %816, 6.550400e+04
>  %823 = select i1 %822, float 6.550400e+04, float %816
>  %824 = fcmp uge float %819, 0x3E6FFFFE60000000
>  %825 = select i1 %824, float %819, float 0x3E6FFFFE60000000
>  %826 = fcmp uge float %821, 0x3E6FFFFE60000000
>  %827 = select i1 %826, float %821, float 0x3E6FFFFE60000000
>  %828 = fcmp uge float %823, 0x3E6FFFFE60000000
>  %829 = select i1 %828, float %823, float 0x3E6FFFFE60000000
>  %830 = fmul float %817, %55
>  %831 = fadd float %830, %56
>  %832 = call float @llvm.AMDIL.clamp.(float %831, float 0.000000e+00, float 1.000000e+00)
>  %833 = call i32 @llvm.SI.packf16(float %825, float %827)
>  %834 = bitcast i32 %833 to float
>  %835 = call i32 @llvm.SI.packf16(float %829, float %832)
>  %836 = bitcast i32 %835 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %834, float %836, float %834, float %836)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.lrp(float, float, float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #2
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #3
>
>; Function Attrs: readonly
>declare float @fabs(float) #4
>
>; Function Attrs: readonly
>declare float @floor(float) #4
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare i32 @llvm.SI.tid() #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { nounwind readonly }
>attributes #4 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>Sam3.orig: AMDGPUInstrInfo.cpp:109: virtual void llvm::AMDGPUInstrInfo::storeRegToStackSlot(llvm::MachineBasicBlock&, llvm::MachineBasicBlock::iterator, unsigned int, bool, int, const llvm::TargetRegisterClass*, const llvm::TargetRegisterInfo*) const: Assertion `!"Not Implemented"' failed.
>Stack dump:
>0.	Running pass 'Function Pass Manager' on module 'tgsi'.
>1.	Running pass 'Greedy Register Allocator' on function '@main'

Actions: View

Attachments on bug 68224: 84175 | 84473 | 84475 | 84543 | 84544 | 84551 | 84880 | 85372 | 89616 | 89631 | 89640 | 89659 | 89671 | 89680 | 89719 | 89806 | 89825 | 89853 | 89854 | 89954

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.