Attachment 84653 Details for Bug 68251 – Track pfit enabling separately.

[patch] Track pfit enabling separately.

0001-drm-i915-Track-pfit-enable-state-separately-from-siz.patch (text/plain), 6.31 KB, created by Chris Wilson on 2013-08-26 15:00:07 UTC

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Creator: Chris Wilson

Created: 2013-08-26 15:00:07 UTC

Size: 6.31 KB

patch

obsolete

>From f057964233fe4a26f3dba4cfb4f5d06ca33cdcd5 Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Mon, 26 Aug 2013 15:56:50 +0100
>Subject: [PATCH] drm/i915: Track pfit enable state separately from size
>
>Detangle the additional state of whether or not the hw has the pfit
>enabled from whether it has zero size. This allows us to cleanly
>distinguish in the code when we expect the pfit to be enabled (for
>Haswell pc8), and when the BIOS is confused and needs sanitizing.
>
>Reported-by: shui yanwei <yangweix.shui@intel.com>
>References: https://bugs.freedesktop.org/show_bug.cgi?id=68251&list_id=337713
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>---
> drivers/gpu/drm/i915/intel_ddi.c     |    2 +-
> drivers/gpu/drm/i915/intel_display.c |   21 +++++++++++++--------
> drivers/gpu/drm/i915/intel_drv.h     |    1 +
> drivers/gpu/drm/i915/intel_panel.c   |    1 +
> drivers/gpu/drm/i915/intel_pm.c      |    6 +++---
> 5 files changed, 19 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>index 63aca49..63de270 100644
>--- a/drivers/gpu/drm/i915/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/intel_ddi.c
>@@ -778,7 +778,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
> 			/* Can only use the always-on power well for eDP when
> 			 * not using the panel fitter, and when not using motion
> 			  * blur mitigation (which we don't support). */
>-			if (intel_crtc->config.pch_pfit.size)
>+			if (intel_crtc->config.pch_pfit.enabled)
> 				temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
> 			else
> 				temp |= TRANS_DDI_EDP_INPUT_A_ON;
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 2d81ac7..ca4129a 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -2249,7 +2249,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
> 		I915_WRITE(PIPESRC(intel_crtc->pipe),
> 			   ((crtc->mode.hdisplay - 1) << 16) |
> 			   (crtc->mode.vdisplay - 1));
>-		if (!intel_crtc->config.pch_pfit.size &&
>+		if (!intel_crtc->config.pch_pfit.enabled &&
> 		    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
> 		     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
> 			I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
>@@ -3203,7 +3203,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 	int pipe = crtc->pipe;
> 
>-	if (crtc->config.pch_pfit.size) {
>+	if (crtc->config.pch_pfit.enabled) {
> 		/* Force use of hard-coded filter coefficients
> 		 * as some pre-programmed values are broken,
> 		 * e.g. x201.
>@@ -3428,7 +3428,7 @@ static void ironlake_pfit_disable(struct intel_crtc *crtc)
> 
> 	/* To avoid upsetting the power well on haswell only disable the pfit if
> 	 * it's in use. The hw state code will make sure we get this right. */
>-	if (crtc->config.pch_pfit.size) {
>+	if (crtc->config.pch_pfit.enabled) {
> 		I915_WRITE(PF_CTL(pipe), 0);
> 		I915_WRITE(PF_WIN_POS(pipe), 0);
> 		I915_WRITE(PF_WIN_SZ(pipe), 0);
>@@ -5859,6 +5859,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
> 	tmp = I915_READ(PF_CTL(crtc->pipe));
> 
> 	if (tmp & PF_ENABLE) {
>+		pipe_config->pch_pfit.enabled = true;
> 		pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
> 		pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
> 
>@@ -6236,7 +6237,7 @@ static void haswell_modeset_global_resources(struct drm_device *dev)
> 		if (!crtc->base.enabled)
> 			continue;
> 
>-		if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
>+		if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
> 		    crtc->config.cpu_transcoder != TRANSCODER_EDP)
> 			enable = true;
> 	}
>@@ -8205,9 +8206,10 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> 		      pipe_config->gmch_pfit.control,
> 		      pipe_config->gmch_pfit.pgm_ratios,
> 		      pipe_config->gmch_pfit.lvds_border_bits);
>-	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
>+	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
> 		      pipe_config->pch_pfit.pos,
>-		      pipe_config->pch_pfit.size);
>+		      pipe_config->pch_pfit.size,
>+		      pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
> 	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
> }
> 
>@@ -8603,8 +8605,11 @@ intel_pipe_config_compare(struct drm_device *dev,
> 	if (INTEL_INFO(dev)->gen < 4)
> 		PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
> 	PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
>-	PIPE_CONF_CHECK_I(pch_pfit.pos);
>-	PIPE_CONF_CHECK_I(pch_pfit.size);
>+	PIPE_CONF_CHECK_I(pch_pfit.enabled);
>+	if (current_config->pch_pfit.enabled) {
>+		PIPE_CONF_CHECK_I(pch_pfit.pos);
>+		PIPE_CONF_CHECK_I(pch_pfit.size);
>+	}
> 
> 	PIPE_CONF_CHECK_I(ips_enabled);
> 
>diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index e7949cb..a79ac33 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -280,6 +280,7 @@ struct intel_crtc_config {
> 	struct {
> 		u32 pos;
> 		u32 size;
>+		bool enabled;
> 	} pch_pfit;
> 
> 	/* FDI configuration, only valid if has_pch_encoder is set. */
>diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
>index a43c33b..28f7373 100644
>--- a/drivers/gpu/drm/i915/intel_panel.c
>+++ b/drivers/gpu/drm/i915/intel_panel.c
>@@ -120,6 +120,7 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
> done:
> 	pipe_config->pch_pfit.pos = (x << 16) | y;
> 	pipe_config->pch_pfit.size = (width << 16) | height;
>+	pipe_config->pch_pfit.enabled = true;
> }
> 
> static void
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index f995dda..9d91d37 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -2096,16 +2096,16 @@ static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
> 				    struct drm_crtc *crtc)
> {
> 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>-	uint32_t pixel_rate, pfit_size;
>+	uint32_t pixel_rate;
> 
> 	pixel_rate = intel_crtc->config.adjusted_mode.clock;
> 
> 	/* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
> 	 * adjust the pixel_rate here. */
> 
>-	pfit_size = intel_crtc->config.pch_pfit.size;
>-	if (pfit_size) {
>+	if (intel_crtc->config.pch_pfit.enabled) {
> 		uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
>+		uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
> 
> 		pipe_w = intel_crtc->config.requested_mode.hdisplay;
> 		pipe_h = intel_crtc->config.requested_mode.vdisplay;
>-- 
>1.7.9.5
>

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Attachments on bug 68251: 84218 | 84233 | 84653 | 84673

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