Attachment 84747 Details for Bug 52952 – possible fix

[patch] possible fix

0001-drm-radeon-fix-resume-on-some-rs4xx-boards-v2.patch (text/plain), 1.66 KB, created by Alex Deucher on 2013-08-27 19:10:07 UTC

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Creator: Alex Deucher

Created: 2013-08-27 19:10:07 UTC

Size: 1.66 KB

patch

obsolete

>From c37ef645e80068222e359e0c2aa5c47f8c8a55cb Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexander.deucher@amd.com>
>Date: Mon, 26 Aug 2013 17:52:12 -0400
>Subject: [PATCH] drm/radeon: fix resume on some rs4xx boards (v2)
>
>Setting MC_MISC_CNTL.GART_INDEX_REG_EN causes hangs on
>some boards on resume.  The systems seem to work fine
>without touching this bit so leave it as is.
>
>v2: read-modify-write the GART_INDEX_REG_EN bit.
>I suspect the problem is that we are losing the other
>settings in the register.
>
>Reported-by: Ondrej Zary <linux@rainbow-software.org>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>Cc: stable@vger.kernel.org
>---
> drivers/gpu/drm/radeon/rs400.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
>index 233a9b9..b8074a8 100644
>--- a/drivers/gpu/drm/radeon/rs400.c
>+++ b/drivers/gpu/drm/radeon/rs400.c
>@@ -174,10 +174,13 @@ int rs400_gart_enable(struct radeon_device *rdev)
> 	/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
> 	 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
> 	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
>-		WREG32_MC(RS480_MC_MISC_CNTL,
>-			  (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
>+		tmp = RREG32_MC(RS480_MC_MISC_CNTL);
>+		tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
>+		WREG32_MC(RS480_MC_MISC_CNTL, tmp);
> 	} else {
>-		WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
>+		tmp = RREG32_MC(RS480_MC_MISC_CNTL);
>+		tmp |= RS480_GART_INDEX_REG_EN;
>+		WREG32_MC(RS480_MC_MISC_CNTL, tmp);
> 	}
> 	/* Enable gart */
> 	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
>-- 
>1.8.3.1
>

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