Attachment 8541 Details for Bug 9807 – Xorg.0.log

Xorg.0.log

Xorg.0.log (text/plain), 93.85 KB, created by Wei Tang on 2007-01-29 19:13:09 UTC

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Creator: Wei Tang

Created: 2007-01-29 19:13:09 UTC

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obsolete

>
>This is a pre-release version of the X server from The X.Org Foundation.
>It is not supported in any way.
>Bugs may be filed in the bugzilla at http://bugs.freedesktop.org/.
>Select the "xorg" product for bugs you find in this release.
>Before reporting bugs in pre-release versions please check the
>latest version in the X.Org Foundation git repository.
>See http://wiki.x.org/wiki/GitPage for git access instructions.
>
>X Window System Version 7.1.99.903 (7.2.0 RC 3)
>Release Date: 1 December 2006
>X Protocol Version 11, Revision 0, Release 7.1.99.903
>Build Operating System: Linux 2.6.15-1.2054_FC5smp i686 
>Current Operating System: Linux x-855gm.sh.intel.com 2.6.19 #1 SMP Fri Jan 26 11:45:48 CST 2007 i686
>Build Date: 05 January 2007
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Module Loader present
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/opt/X11R7/var/log/Xorg.0.log", Time: Mon Jan 29 13:22:12 2007
>(==) Using config file: "/etc/X11/xorg.conf"
>(==) ServerLayout "Default Layout"
>(**) |-->Screen "Screen0" (0)
>(**) |   |-->Monitor "Monitor0"
>(**) |   |-->Device "Videocard0"
>(**) |-->Input Device "Mouse0"
>(**) |-->Input Device "Keyboard0"
>(**) FontPath set to:
>	unix/:7100
>(==) RgbPath set to "/opt/X11R7/share/X11/rgb"
>(==) ModulePath set to "/opt/X11R7/lib/xorg/modules"
>(WW) Open ACPI failed (/var/run/acpid.socket) (No such file or directory)
>(II) No APM support in BIOS or kernel
>(II) Loader magic: 0x81cabe0
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.3
>	X.Org Video Driver: 1.0
>	X.Org XInput driver : 0.6
>	X.Org Server Extension : 0.3
>	X.Org Font Renderer : 0.5
>(II) Loader running on linux
>(II) LoadModule: "pcidata"
>(II) Loading /opt/X11R7/lib/xorg/modules//libpcidata.so
>(II) Module pcidata: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.0
>(--) using VT number 7
>
>(II) PCI: PCI scan (all values are in hex)
>(II) PCI: 00:00:0: chip 8086,3580 card 0000,0000 rev 02 class 06,00,00 hdr 80
>(II) PCI: 00:00:1: chip 8086,3584 card 1179,ff10 rev 02 class 08,80,00 hdr 00
>(II) PCI: 00:00:3: chip 8086,3585 card 1179,ff10 rev 02 class 08,80,00 hdr 80
>(II) PCI: 00:02:0: chip 8086,3582 card 1179,ff10 rev 02 class 03,00,00 hdr 80
>(II) PCI: 00:02:1: chip 8086,3582 card 1179,ff10 rev 02 class 03,80,00 hdr 80
>(II) PCI: 00:1d:0: chip 8086,24c2 card 1179,ff10 rev 03 class 0c,03,00 hdr 80
>(II) PCI: 00:1d:2: chip 8086,24c7 card 1179,ff10 rev 03 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:7: chip 8086,24cd card 1179,ff10 rev 03 class 0c,03,20 hdr 00
>(II) PCI: 00:1e:0: chip 8086,2448 card 0000,0000 rev 83 class 06,04,00 hdr 01
>(II) PCI: 00:1f:0: chip 8086,24cc card 0000,0000 rev 03 class 06,01,00 hdr 80
>(II) PCI: 00:1f:1: chip 8086,24ca card 1179,ff10 rev 03 class 01,01,8a hdr 00
>(II) PCI: 00:1f:3: chip 8086,24c3 card 1179,ff10 rev 03 class 0c,05,00 hdr 00
>(II) PCI: 00:1f:5: chip 8086,24c5 card 1179,ff10 rev 03 class 04,01,00 hdr 00
>(II) PCI: 00:1f:6: chip 8086,24c6 card 1179,0001 rev 03 class 07,03,00 hdr 00
>(II) PCI: 01:04:0: chip 8086,1043 card 8086,2581 rev 04 class 02,80,00 hdr 00
>(II) PCI: 01:06:0: chip 104c,ac55 card c400,0000 rev 01 class 06,07,00 hdr 82
>(II) PCI: 01:06:1: chip 104c,ac55 card cc00,0000 rev 01 class 06,07,00 hdr 82
>(II) PCI: 01:08:0: chip 8086,103a card 0000,0000 rev 83 class 02,00,00 hdr 00
>(II) PCI: End of PCI scan
>(II) Intel Bridge workaround enabled
>(II) Host-to-PCI bridge:
>(II) Bus 0: bridge is at (0:0:0), (0,0,6), BCTRL: 0x0008 (VGA_EN is set)
>(II) Bus 0 I/O range:
>	[0] -1	0	0x00000000 - 0x0000ffff (0x10000) IX[B]
>(II) Bus 0 non-prefetchable memory range:
>	[0] -1	0	0x00000000 - 0xffffffff (0x0) MX[B]
>(II) Bus 0 prefetchable memory range:
>	[0] -1	0	0x00000000 - 0xffffffff (0x0) MX[B]
>(II) Subtractive PCI-to-PCI bridge:
>(II) Bus 1: bridge is at (0:30:0), (0,1,1), BCTRL: 0x0002 (VGA_EN is cleared)
>(II) Bus 1 I/O range:
>	[0] -1	0	0x0000c000 - 0x0000dfff (0x2000) IX[B]
>(II) Bus 1 non-prefetchable memory range:
>	[0] -1	0	0xe0000000 - 0xefffffff (0x10000000) MX[B]
>(II) Bus 1 prefetchable memory range:
>	[0] -1	0	0xa0000000 - 0xafffffff (0x10000000) MX[B]
>(II) PCI-to-ISA bridge:
>(II) Bus -1: bridge is at (0:31:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set)
>(II) PCI-to-CardBus bridge:
>(II) Bus 2: bridge is at (1:6:0), (1,2,5), BCTRL: 0x03c0 (VGA_EN is cleared)
>(II) Bus 2 I/O range:
>	[0] -1	0	0x0000c400 - 0x0000c4ff (0x100) IX[B]
>	[1] -1	0	0x0000c800 - 0x0000c8ff (0x100) IX[B]
>(II) Bus 2 prefetchable memory range:
>	[0] -1	0	0xa0000000 - 0xa1ffffff (0x2000000) MX[B]
>(II) PCI-to-CardBus bridge:
>(II) Bus 6: bridge is at (1:6:1), (1,6,9), BCTRL: 0x03c0 (VGA_EN is cleared)
>(II) Bus 6 I/O range:
>	[0] -1	0	0x0000cc00 - 0x0000ccff (0x100) IX[B]
>	[1] -1	0	0x0000d000 - 0x0000d0ff (0x100) IX[B]
>(II) Bus 6 prefetchable memory range:
>	[0] -1	0	0xa2000000 - 0xa3ffffff (0x2000000) MX[B]
>(--) PCI:*(0:2:0) Intel Corporation 82852/855GM Integrated Graphics Device rev 2, Mem @ 0xb0000000/27, 0xf0000000/19, I/O @ 0xe000/3
>(--) PCI: (0:2:1) Intel Corporation 82852/855GM Integrated Graphics Device rev 2, Mem @ 0x10000000/27, 0x18000000/19
>(II) Addressable bus resource ranges are
>	[0] -1	0	0x00000000 - 0xffffffff (0x0) MX[B]
>	[1] -1	0	0x00000000 - 0x0000ffff (0x10000) IX[B]
>(II) OS-reported resource ranges:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>(II) Active PCI resource ranges:
>	[0] -1	0	0xe0000000 - 0xe0000fff (0x1000) MX[B]
>	[1] -1	0	0xe0001000 - 0xe0001fff (0x1000) MX[B]
>	[2] -1	0	0xf0080600 - 0xf00806ff (0x100) MX[B]
>	[3] -1	0	0xf0080400 - 0xf00805ff (0x200) MX[B]
>	[4] -1	0	0x18080000 - 0x180803ff (0x400) MX[B]
>	[5] -1	0	0xf4000000 - 0xf40003ff (0x400) MX[B]
>	[6] -1	0	0xf0000000 - 0xf007ffff (0x80000) MX[B](B)
>	[7] -1	0	0xb0000000 - 0xb7ffffff (0x8000000) MX[B](B)
>	[8] -1	0	0x0000c000 - 0x0000c03f (0x40) IX[B]
>	[9] -1	0	0x0000e400 - 0x0000e47f (0x80) IX[B]
>	[10] -1	0	0x0000e300 - 0x0000e3ff (0x100) IX[B]
>	[11] -1	0	0x0000e200 - 0x0000e23f (0x40) IX[B]
>	[12] -1	0	0x0000e100 - 0x0000e1ff (0x100) IX[B]
>	[13] -1	0	0x00001400 - 0x0000141f (0x20) IX[B]
>	[14] -1	0	0x00001100 - 0x0000110f (0x10) IX[B]
>	[15] -1	0	0x00001700 - 0x0000171f (0x20) IX[B]
>	[16] -1	0	0x00001200 - 0x0000121f (0x20) IX[B]
>	[17] -1	0	0x0000e000 - 0x0000e007 (0x8) IX[B](B)
>(II) Inactive PCI resource ranges:
>	[0] -1	0	0x18000000 - 0x1807ffff (0x80000) MX[B](B)
>	[1] -1	0	0x10000000 - 0x17ffffff (0x8000000) MX[B](B)
>(II) Active PCI resource ranges after removing overlaps:
>	[0] -1	0	0xe0000000 - 0xe0000fff (0x1000) MX[B]
>	[1] -1	0	0xe0001000 - 0xe0001fff (0x1000) MX[B]
>	[2] -1	0	0xf0080600 - 0xf00806ff (0x100) MX[B]
>	[3] -1	0	0xf0080400 - 0xf00805ff (0x200) MX[B]
>	[4] -1	0	0x18080000 - 0x180803ff (0x400) MX[B]
>	[5] -1	0	0xf4000000 - 0xf40003ff (0x400) MX[B]
>	[6] -1	0	0xf0000000 - 0xf007ffff (0x80000) MX[B](B)
>	[7] -1	0	0xb0000000 - 0xb7ffffff (0x8000000) MX[B](B)
>	[8] -1	0	0x0000c000 - 0x0000c03f (0x40) IX[B]
>	[9] -1	0	0x0000e400 - 0x0000e47f (0x80) IX[B]
>	[10] -1	0	0x0000e300 - 0x0000e3ff (0x100) IX[B]
>	[11] -1	0	0x0000e200 - 0x0000e23f (0x40) IX[B]
>	[12] -1	0	0x0000e100 - 0x0000e1ff (0x100) IX[B]
>	[13] -1	0	0x00001400 - 0x0000141f (0x20) IX[B]
>	[14] -1	0	0x00001100 - 0x0000110f (0x10) IX[B]
>	[15] -1	0	0x00001700 - 0x0000171f (0x20) IX[B]
>	[16] -1	0	0x00001200 - 0x0000121f (0x20) IX[B]
>	[17] -1	0	0x0000e000 - 0x0000e007 (0x8) IX[B](B)
>(II) Inactive PCI resource ranges after removing overlaps:
>	[0] -1	0	0x18000000 - 0x1807ffff (0x80000) MX[B](B)
>	[1] -1	0	0x10000000 - 0x17ffffff (0x8000000) MX[B](B)
>(II) OS-reported resource ranges after removing overlaps with PCI:
>	[0] -1	0	0x00100000 - 0x17ffffff (0x17f00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>(II) All system resource ranges:
>	[0] -1	0	0x00100000 - 0x17ffffff (0x17f00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xe0000000 - 0xe0000fff (0x1000) MX[B]
>	[5] -1	0	0xe0001000 - 0xe0001fff (0x1000) MX[B]
>	[6] -1	0	0xf0080600 - 0xf00806ff (0x100) MX[B]
>	[7] -1	0	0xf0080400 - 0xf00805ff (0x200) MX[B]
>	[8] -1	0	0x18080000 - 0x180803ff (0x400) MX[B]
>	[9] -1	0	0xf4000000 - 0xf40003ff (0x400) MX[B]
>	[10] -1	0	0xf0000000 - 0xf007ffff (0x80000) MX[B](B)
>	[11] -1	0	0xb0000000 - 0xb7ffffff (0x8000000) MX[B](B)
>	[12] -1	0	0x18000000 - 0x1807ffff (0x80000) MX[B](B)
>	[13] -1	0	0x10000000 - 0x17ffffff (0x8000000) MX[B](B)
>	[14] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[15] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[16] -1	0	0x0000c000 - 0x0000c03f (0x40) IX[B]
>	[17] -1	0	0x0000e400 - 0x0000e47f (0x80) IX[B]
>	[18] -1	0	0x0000e300 - 0x0000e3ff (0x100) IX[B]
>	[19] -1	0	0x0000e200 - 0x0000e23f (0x40) IX[B]
>	[20] -1	0	0x0000e100 - 0x0000e1ff (0x100) IX[B]
>	[21] -1	0	0x00001400 - 0x0000141f (0x20) IX[B]
>	[22] -1	0	0x00001100 - 0x0000110f (0x10) IX[B]
>	[23] -1	0	0x00001700 - 0x0000171f (0x20) IX[B]
>	[24] -1	0	0x00001200 - 0x0000121f (0x20) IX[B]
>	[25] -1	0	0x0000e000 - 0x0000e007 (0x8) IX[B](B)
>(II) LoadModule: "dbe"
>(II) Loading /opt/X11R7/lib/xorg/modules/extensions//libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "extmod"
>(II) Loading /opt/X11R7/lib/xorg/modules/extensions//libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension SHAPE
>(II) Loading extension MIT-SUNDRY-NONSTANDARD
>(II) Loading extension BIG-REQUESTS
>(II) Loading extension SYNC
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XC-MISC
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-Misc
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension TOG-CUP
>(II) Loading extension Extended-Visual-Information
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "fbdevhw"
>(II) Loading /opt/X11R7/lib/xorg/modules/linux//libfbdevhw.so
>(II) Module fbdevhw: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 0.0.2
>	ABI class: X.Org Video Driver, version 1.0
>(II) LoadModule: "glx"
>(II) Loading /opt/X11R7/lib/xorg/modules/extensions//libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(==) AIGLX enabled
>(II) Loading extension GLX
>(II) LoadModule: "record"
>(II) Loading /opt/X11R7/lib/xorg/modules/extensions//librecord.so
>(II) Module record: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.13.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension RECORD
>(II) LoadModule: "freetype"
>(II) Loading /opt/X11R7/lib/xorg/modules/fonts//libfreetype.so
>(II) Module freetype: vendor="X.Org Foundation & the After X-TT Project"
>	compiled for 7.1.99.903, module version = 2.1.0
>	Module class: X.Org Font Renderer
>	ABI class: X.Org Font Renderer, version 0.5
>(II) Loading font FreeType
>(II) LoadModule: "type1"
>(II) Loading /opt/X11R7/lib/xorg/modules/fonts//libtype1.so
>(II) Module type1: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.0.2
>	Module class: X.Org Font Renderer
>	ABI class: X.Org Font Renderer, version 0.5
>(II) Loading font Type1
>(II) LoadModule: "dri"
>(II) Loading /opt/X11R7/lib/xorg/modules/extensions//libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "i810"
>(II) Loading /opt/X11R7/lib/xorg/modules/drivers//i810_drv.so
>(II) Module i810: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.7.2
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 1.0
>(II) LoadModule: "mouse"
>(II) Loading /opt/X11R7/lib/xorg/modules/input//mouse_drv.so
>(II) Module mouse: vendor="X.Org Foundation"
>	compiled for 7.1.99.2, module version = 1.1.1
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 0.6
>(II) LoadModule: "kbd"
>(II) Loading /opt/X11R7/lib/xorg/modules/input//kbd_drv.so
>(II) Module kbd: vendor="X.Org Foundation"
>	compiled for 7.1.99.2, module version = 1.1.0
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 0.6
>(II) I810: Driver for Intel Integrated Graphics Chipsets: i810, i810-dc100,
>	i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G, E7221 (i915),
>	915GM, 945G, 945GM, 965G, 965G, 965Q, 946GZ
>(II) Primary Device is: PCI 00:02:0
>(--) Assigning device section with no busID to primary device
>(--) Chipset 852GM/855GM found
>(II) resource ranges after xf86ClaimFixedResources() call:
>	[0] -1	0	0x00100000 - 0x17ffffff (0x17f00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xe0000000 - 0xe0000fff (0x1000) MX[B]
>	[5] -1	0	0xe0001000 - 0xe0001fff (0x1000) MX[B]
>	[6] -1	0	0xf0080600 - 0xf00806ff (0x100) MX[B]
>	[7] -1	0	0xf0080400 - 0xf00805ff (0x200) MX[B]
>	[8] -1	0	0x18080000 - 0x180803ff (0x400) MX[B]
>	[9] -1	0	0xf4000000 - 0xf40003ff (0x400) MX[B]
>	[10] -1	0	0xf0000000 - 0xf007ffff (0x80000) MX[B](B)
>	[11] -1	0	0xb0000000 - 0xb7ffffff (0x8000000) MX[B](B)
>	[12] -1	0	0x18000000 - 0x1807ffff (0x80000) MX[B](B)
>	[13] -1	0	0x10000000 - 0x17ffffff (0x8000000) MX[B](B)
>	[14] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[15] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[16] -1	0	0x0000c000 - 0x0000c03f (0x40) IX[B]
>	[17] -1	0	0x0000e400 - 0x0000e47f (0x80) IX[B]
>	[18] -1	0	0x0000e300 - 0x0000e3ff (0x100) IX[B]
>	[19] -1	0	0x0000e200 - 0x0000e23f (0x40) IX[B]
>	[20] -1	0	0x0000e100 - 0x0000e1ff (0x100) IX[B]
>	[21] -1	0	0x00001400 - 0x0000141f (0x20) IX[B]
>	[22] -1	0	0x00001100 - 0x0000110f (0x10) IX[B]
>	[23] -1	0	0x00001700 - 0x0000171f (0x20) IX[B]
>	[24] -1	0	0x00001200 - 0x0000121f (0x20) IX[B]
>	[25] -1	0	0x0000e000 - 0x0000e007 (0x8) IX[B](B)
>(II) resource ranges after probing:
>	[0] -1	0	0x00100000 - 0x17ffffff (0x17f00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xe0000000 - 0xe0000fff (0x1000) MX[B]
>	[5] -1	0	0xe0001000 - 0xe0001fff (0x1000) MX[B]
>	[6] -1	0	0xf0080600 - 0xf00806ff (0x100) MX[B]
>	[7] -1	0	0xf0080400 - 0xf00805ff (0x200) MX[B]
>	[8] -1	0	0x18080000 - 0x180803ff (0x400) MX[B]
>	[9] -1	0	0xf4000000 - 0xf40003ff (0x400) MX[B]
>	[10] -1	0	0xf0000000 - 0xf007ffff (0x80000) MX[B](B)
>	[11] -1	0	0xb0000000 - 0xb7ffffff (0x8000000) MX[B](B)
>	[12] -1	0	0x18000000 - 0x1807ffff (0x80000) MX[B](B)
>	[13] -1	0	0x10000000 - 0x17ffffff (0x8000000) MX[B](B)
>	[14] 1	0	0x000a0000 - 0x000affff (0x10000) MS[B]
>	[15] 1	0	0x000b0000 - 0x000b7fff (0x8000) MS[B]
>	[16] 1	0	0x000b8000 - 0x000bffff (0x8000) MS[B]
>	[17] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[18] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[19] -1	0	0x0000c000 - 0x0000c03f (0x40) IX[B]
>	[20] -1	0	0x0000e400 - 0x0000e47f (0x80) IX[B]
>	[21] -1	0	0x0000e300 - 0x0000e3ff (0x100) IX[B]
>	[22] -1	0	0x0000e200 - 0x0000e23f (0x40) IX[B]
>	[23] -1	0	0x0000e100 - 0x0000e1ff (0x100) IX[B]
>	[24] -1	0	0x00001400 - 0x0000141f (0x20) IX[B]
>	[25] -1	0	0x00001100 - 0x0000110f (0x10) IX[B]
>	[26] -1	0	0x00001700 - 0x0000171f (0x20) IX[B]
>	[27] -1	0	0x00001200 - 0x0000121f (0x20) IX[B]
>	[28] -1	0	0x0000e000 - 0x0000e007 (0x8) IX[B](B)
>	[29] 1	0	0x000003b0 - 0x000003bb (0xc) IS[B]
>	[30] 1	0	0x000003c0 - 0x000003df (0x20) IS[B]
>(II) Setting vga for screen 0.
>(II) Loading sub module "int10"
>(II) LoadModule: "int10"
>(II) Loading /opt/X11R7/lib/xorg/modules//libint10.so
>(II) Module int10: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) Loading sub module "vbe"
>(II) LoadModule: "vbe"
>(II) Loading /opt/X11R7/lib/xorg/modules//libvbe.so
>(II) Module vbe: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.1.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>(II) Loading /opt/X11R7/lib/xorg/modules//libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 1.0
>(**) I810(0): Depth 24, (--) framebuffer bpp 32
>(==) I810(0): RGB weight 888
>(==) I810(0): Default visual is TrueColor
>(**) I810(0): Option "Legacy3D" "TRUE"
>(II) I810(0): Integrated Graphics Chipset: Intel(R) 855GM
>(--) I810(0): Chipset: "852GM/855GM"
>(--) I810(0): Linear framebuffer at 0xB0000000
>(--) I810(0): IO registers at addr 0xF0000000
>(II) I810(0): Hardware state on X startup:
>(II) I810(0): DumpRegsBegin
>(II) I810(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) I810(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) I810(0):        VCLK_POST_DIV: 0x0000888b
>(II) I810(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) I810(0):              D_STATE: 0x0000030f
>(II) I810(0):        DSPCLK_GATE_D: 0x00000000
>(II) I810(0):       RENCLK_GATE_D1: 0x00000000
>(II) I810(0):       RENCLK_GATE_D2: 0x00000000
>(II) I810(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) I810(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) I810(0):              SDVOUDI: 0x00000000
>(II) I810(0):               DSPARB: 0x00015455
>(II) I810(0):               DSPFW1: 0x00000000
>(II) I810(0):               DSPFW2: 0x00000000
>(II) I810(0):               DSPFW3: 0x00000000
>(II) I810(0):                 ADPA: 0x00001c18
>(II) I810(0):                 LVDS: 0xc0000300 (enabled, pipe B)
>(II) I810(0):                 DVOA: 0x00000000
>(II) I810(0):                 DVOB: 0x00000000
>(II) I810(0):                 DVOC: 0x00000000
>(II) I810(0):          DVOA_SRCDIM: 0x00000000
>(II) I810(0):          DVOB_SRCDIM: 0x00000000
>(II) I810(0):          DVOC_SRCDIM: 0x00000000
>(II) I810(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) I810(0):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II) I810(0):         PFIT_CONTROL: 0x80000668
>(II) I810(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) I810(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) I810(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) I810(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) I810(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) I810(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) I810(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) I810(0):             DSPABASE: 0x00000000
>(II) I810(0):             DSPASURF: 0x00000000
>(II) I810(0):          DSPATILEOFF: 0x00000000
>(II) I810(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) I810(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) I810(0):                 FPA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):               DPLL_A: 0x808b0000 (enabled, non-dvo, VGA, unknown mode, default clock, p1 = 1, p2 = 0)
>(II) I810(0):            DPLL_A_MD: 0x00000000
>(II) I810(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) I810(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) I810(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) I810(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) I810(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) I810(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) I810(0):            BCLRPAT_A: 0x00000000
>(II) I810(0):         VSYNCSHIFT_A: 0x00000000
>(II) I810(0):             DSPBCNTR: 0x49000000 (disabled, pipe B)
>(II) I810(0):           DSPBSTRIDE: 0x00000280 (640 bytes)
>(II) I810(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) I810(0):             DSPBSIZE: 0x01df027f (640, 480)
>(II) I810(0):             DSPBBASE: 0x00000000
>(II) I810(0):             DSPBSURF: 0x00000000
>(II) I810(0):          DSPBTILEOFF: 0x00000000
>(II) I810(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) I810(0):             PIPEBSRC: 0x027f018f (640, 400)
>(II) I810(0):                 FPB0: 0x0004120c (n = 4, m1 = 18, m2 = 12)
>(II) I810(0):                 FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):               DPLL_B: 0x90010000 (enabled, non-dvo, unknown mode, default clock, p1 = 1, p2 = 0)
>(II) I810(0):            DPLL_B_MD: 0x00000000
>(II) I810(0):             HTOTAL_B: 0x053f03ff (1024 active, 1344 total)
>(II) I810(0):             HBLANK_B: 0x053f03ff (1024 start, 1344 end)
>(II) I810(0):              HSYNC_B: 0x049f0417 (1048 start, 1184 end)
>(II) I810(0):             VTOTAL_B: 0x032502ff (768 active, 806 total)
>(II) I810(0):             VBLANK_B: 0x032502ff (768 start, 806 end)
>(II) I810(0):              VSYNC_B: 0x03080302 (771 start, 777 end)
>(II) I810(0):            BCLRPAT_B: 0x00000000
>(II) I810(0):         VSYNCSHIFT_B: 0x00000000
>(II) I810(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) I810(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) I810(0):        VCLK_POST_DIV: 0x0000888b
>(II) I810(0):             VGACNTRL: 0x2204008e (enabled)
>(II) I810(0):               TV_CTL: 0x00000000
>(II) I810(0):               TV_DAC: 0x00000000
>(II) I810(0):             TV_CSC_Y: 0x00000000
>(II) I810(0):            TV_CSC_Y2: 0x00000000
>(II) I810(0):             TV_CSC_U: 0x00000000
>(II) I810(0):            TV_CSC_U2: 0x00000000
>(II) I810(0):             TV_CSC_V: 0x00000000
>(II) I810(0):            TV_CSC_V2: 0x00000000
>(II) I810(0):         TV_CLR_KNOBS: 0x00000000
>(II) I810(0):         TV_CLR_LEVEL: 0x00000000
>(II) I810(0):           TV_H_CTL_1: 0x00000000
>(II) I810(0):           TV_H_CTL_2: 0x00000000
>(II) I810(0):           TV_H_CTL_3: 0x00000000
>(II) I810(0):           TV_V_CTL_1: 0x00000000
>(II) I810(0):           TV_V_CTL_2: 0x00000000
>(II) I810(0):           TV_V_CTL_3: 0x00000000
>(II) I810(0):           TV_V_CTL_4: 0x00000000
>(II) I810(0):           TV_V_CTL_5: 0x00000000
>(II) I810(0):           TV_V_CTL_6: 0x00000000
>(II) I810(0):           TV_V_CTL_7: 0x00000000
>(II) I810(0):          TV_SC_CTL_1: 0x00000000
>(II) I810(0):          TV_SC_CTL_2: 0x00000000
>(II) I810(0):          TV_SC_CTL_3: 0x00000000
>(II) I810(0):           TV_WIN_POS: 0x00000000
>(II) I810(0):          TV_WIN_SIZE: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_1: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_2: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_3: 0x00000000
>(II) I810(0):        TV_CC_CONTROL: 0x00000000
>(II) I810(0):           TV_CC_DATA: 0x00000000
>(II) I810(0):          TV_H_LUMA_0: 0x00000000
>(II) I810(0):         TV_H_LUMA_59: 0x00000000
>(II) I810(0):        TV_H_CHROMA_0: 0x00000000
>(II) I810(0):       TV_H_CHROMA_59: 0x00000000
>(II) I810(0):                 SR00: 0x03
>(II) I810(0):                 SR01: 0x00
>(II) I810(0):                 SR02: 0x03
>(II) I810(0):                 SR03: 0x04
>(II) I810(0):                 SR04: 0x02
>(II) I810(0):                 SR05: 0x00
>(II) I810(0):                 SR06: 0x00
>(II) I810(0):                 SR07: 0x00
>(II) I810(0):                  MSR: 0x67
>(II) I810(0):                 CR00: 0x5f
>(II) I810(0):                 CR01: 0x4f
>(II) I810(0):                 CR02: 0x50
>(II) I810(0):                 CR03: 0x82
>(II) I810(0):                 CR04: 0x55
>(II) I810(0):                 CR05: 0x81
>(II) I810(0):                 CR06: 0xbf
>(II) I810(0):                 CR07: 0x1f
>(II) I810(0):                 CR08: 0x00
>(II) I810(0):                 CR09: 0x4f
>(II) I810(0):                 CR0a: 0x1f
>(II) I810(0):                 CR0b: 0x1e
>(II) I810(0):                 CR0c: 0x00
>(II) I810(0):                 CR0d: 0x00
>(II) I810(0):                 CR0e: 0x00
>(II) I810(0):                 CR0f: 0x00
>(II) I810(0):                 CR10: 0x9c
>(II) I810(0):                 CR11: 0x8e
>(II) I810(0):                 CR12: 0x8f
>(II) I810(0):                 CR13: 0x28
>(II) I810(0):                 CR14: 0x1f
>(II) I810(0):                 CR15: 0x96
>(II) I810(0):                 CR16: 0xb9
>(II) I810(0):                 CR17: 0xa3
>(II) I810(0):                 CR18: 0xff
>(II) I810(0):                 CR19: 0x00
>(II) I810(0):                 CR1a: 0x00
>(II) I810(0):                 CR1b: 0x00
>(II) I810(0):                 CR1c: 0x00
>(II) I810(0):                 CR1d: 0x00
>(II) I810(0):                 CR1e: 0x00
>(II) I810(0):                 CR1f: 0x00
>(II) I810(0):                 CR20: 0x00
>(II) I810(0):                 CR21: 0x00
>(II) I810(0):                 CR22: 0x20
>(II) I810(0):                 CR23: 0x00
>(II) I810(0):                 CR24: 0x00
>(EE) I810(0): p1 out of range
>(II) I810(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) I810(0): pipe A dot 261600 n 2 m1 18 m2 7 p1 1 p2 10
>(II) I810(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) I810(0): pipe B dot 182400 n 4 m1 18 m2 12 p1 1 p2 10
>(II) I810(0): DumpRegsEnd
>(II) I810(0): 2 display pipes available.
>(II) I810(0): detected 128 kB GTT.
>(II) I810(0): detected 32636 kB stolen memory.
>(II) I810(0): Kernel reported 45056 total, 1 used
>(II) I810(0): I830CheckAvailableMemory: 180220 kB available
>(==) I810(0): Using XAA for acceleration
>(**) I810(0): Will try to allocate texture pool for old Mesa 3D driver.
>(II) I810(0): Will try to reserve 32768 kiB of AGP aperture space
>	for the DRM memory manager.
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"
>(II) Loading /opt/X11R7/lib/xorg/modules//libddc.so
>(II) Module ddc: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"
>(II) Loading /opt/X11R7/lib/xorg/modules//libi2c.so
>(II) Module i2c: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.2.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) I810(0): I2C bus "CRTDDC_A" initialized.
>(II) Loading sub module "int10"
>(II) LoadModule: "int10"
>(II) Reloading /opt/X11R7/lib/xorg/modules//libint10.so
>(II) I810(0): initializing int10
>(II) I810(0): Primary V_BIOS segment is: 0xc000
>(II) I810(0): VESA BIOS detected
>(II) I810(0): VESA VBE Version 3.0
>(II) I810(0): VESA VBE Total Mem: 32576 kB
>(II) I810(0): VESA VBE OEM: Intel(r)852MG/852MGE/855MG/855MGE Graphics Chip Accelerated VGA BIOS
>(II) I810(0): VESA VBE OEM Software Rev: 1.0
>(II) I810(0): VESA VBE OEM Vendor: Intel Corporation
>(II) I810(0): VESA VBE OEM Product: Intel(r)852MG/852MGE/855MG/855MGE Graphics Controller
>(II) I810(0): VESA VBE OEM Product Rev: Hardware Version 0.0
>(II) I810(0): Found BDB block type 254
>(II) I810(0): Found BDB block type 1
>(II) I810(0): Found BDB block type 254
>(II) I810(0): Found BDB block type 2
>(II) I810(0): Found BDB block type 3
>(II) I810(0): Found BDB block type 4
>(II) I810(0): Found BDB block type 254
>(II) I810(0): Found BDB block type 5
>(II) I810(0): Found BDB block type 6
>(II) I810(0): Found BDB block type 7
>(II) I810(0): Found BDB block type 8
>(II) I810(0): Found BDB block type 10
>(II) I810(0): Found BDB block type 11
>(II) I810(0): Found BDB block type 12
>(II) I810(0): Found BDB block type 13
>(II) I810(0): Found BDB block type 14
>(II) I810(0): Found BDB block type 15
>(II) I810(0): Found BDB block type 16
>(II) I810(0): Found BDB block type 17
>(II) I810(0): Found BDB block type 18
>(II) I810(0): Found BDB block type 19
>(II) I810(0): Found BDB block type 20
>(II) I810(0): Found BDB block type 40
>(II) I810(0): Found BDB block type 41
>(II) I810(0): Found panel mode in BIOS VBT tables:
>(II) I810(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 (48.4 kHz)
>(II) I810(0): Found BDB block type 42
>(II) I810(0): I2C bus "LVDSDDC_C" initialized.
>(II) I810(0): I2C bus "DVODDC_D" initialized.
>(II) Loading sub module "sil164"
>(II) LoadModule: "sil164"
>(II) Loading /opt/X11R7/lib/xorg/modules/drivers//sil164.so
>(II) Module sil164: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) I810(0): I2C bus "DVOI2C_E" initialized.
>(EE) I810(0): detecting sil164
>(EE) I810(0): Unable to read from DVOI2C_E Slave 112.
>(II) Loading sub module "ch7xxx"
>(II) LoadModule: "ch7xxx"
>(II) Loading /opt/X11R7/lib/xorg/modules/drivers//ch7xxx.so
>(II) Module ch7xxx: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) I810(0): I2C bus "DVOI2C_E" removed.
>(II) I810(0): I2C bus "DVOI2C_E" initialized.
>(II) I810(0): Detected CH7009A chipset, vendor/device ID 0x84/0x17
>(II) I810(0): I2C device "DVOI2C_E:CH7xxx TMDS Controller" registered at address 0xEC.
>chosen: dotclock 31500 vco 1008000 ((m 126, m1 20, m2 14), n 4, (p 32, p1 6, p2 1))
>clock regs: 0x90860000, 0x0004140e
>(II) I810(0): Disabling unused functions
>(II) I810(0): Disabling output VGA
>(II) I810(0): Disabling output LVDS
>(II) I810(0): Disabling output TMDS
>(II) I810(0): Disabling CRTC B
>chosen: dotclock 31500 vco 1008000 ((m 126, m1 20, m2 14), n 4, (p 32, p1 6, p2 1))
>clock regs: 0x90860000, 0x0004140e
>(II) I810(0): Disabling unused functions
>(II) I810(0): Disabling output VGA
>(II) I810(0): Disabling output LVDS
>(II) I810(0): Disabling output TMDS
>(II) I810(0): Disabling CRTC B
>(II) I810(0): I2C device "CRTDDC_A:ddc2" registered at address 0xA0.
>(II) I810(0): I2C device "CRTDDC_A:ddc2" removed.
>(II) I810(0): EDID for output VGA
>(II) I810(0): Not using default mode "640x350" (vrefresh out of range)
>(II) I810(0): Not using default mode "640x400" (vrefresh out of range)
>(II) I810(0): Not using default mode "720x400" (vrefresh out of range)
>(II) I810(0): Not using default mode "640x480" (vrefresh out of range)
>(II) I810(0): Not using default mode "640x480" (vrefresh out of range)
>(II) I810(0): Not using default mode "640x480" (vrefresh out of range)
>(II) I810(0): Not using default mode "800x600" (vrefresh out of range)
>(II) I810(0): Not using default mode "800x600" (vrefresh out of range)
>(II) I810(0): Not using default mode "800x600" (vrefresh out of range)
>(II) I810(0): Not using default mode "800x600" (vrefresh out of range)
>(II) I810(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) I810(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) I810(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) I810(0): Not using default mode "1152x864" (vrefresh out of range)
>(II) I810(0): Not using default mode "1280x960" (hsync out of range)
>(II) I810(0): Not using default mode "1280x960" (vrefresh out of range)
>(II) I810(0): Not using default mode "1280x1024" (hsync out of range)
>(II) I810(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) I810(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) I810(0): Not using default mode "1600x1200" (hsync out of range)
>(II) I810(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) I810(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) I810(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) I810(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) I810(0): Not using default mode "1792x1344" (hsync out of range)
>(II) I810(0): Not using default mode "1792x1344" (vrefresh out of range)
>(II) I810(0): Not using default mode "1856x1392" (hsync out of range)
>(II) I810(0): Not using default mode "1856x1392" (vrefresh out of range)
>(II) I810(0): Not using default mode "1920x1440" (hsync out of range)
>(II) I810(0): Not using default mode "1920x1440" (vrefresh out of range)
>(II) I810(0): Not using default mode "832x624" (vrefresh out of range)
>(II) I810(0): Not using default mode "1152x768" (vrefresh out of range)
>(II) I810(0): Not using default mode "1400x1050" (hsync out of range)
>(II) I810(0): Not using default mode "1400x1050" (vrefresh out of range)
>(II) I810(0): Not using default mode "1600x1024" (hsync out of range)
>(II) I810(0): Not using default mode "1920x1440" (vrefresh out of range)
>(II) I810(0): Not using default mode "2048x1536" (hsync out of range)
>(II) I810(0): Not using default mode "2048x1536" (vrefresh out of range)
>(II) I810(0): Not using default mode "2048x1536" (vrefresh out of range)
>(II) I810(0): Printing probed modes for output VGA
>(II) I810(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) I810(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) I810(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) I810(0): I2C device "LVDSDDC_C:ddc2" registered at address 0xA0.
>(II) I810(0): I2C device "LVDSDDC_C:ddc2" removed.
>(II) I810(0): EDID for output LVDS
>(II) I810(0): Not using default mode "1152x864" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1280x960" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1280x960" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1280x1024" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1280x1024" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1280x1024" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1600x1200" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1600x1200" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1600x1200" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1600x1200" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1600x1200" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1792x1344" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1792x1344" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1856x1392" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1856x1392" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1920x1440" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1920x1440" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1152x768" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1400x1050" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1400x1050" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1600x1024" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "1920x1440" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "2048x1536" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "2048x1536" (exceeds panel dimensions)
>(II) I810(0): Not using default mode "2048x1536" (exceeds panel dimensions)
>(II) I810(0): Printing probed modes for output LVDS
>(II) I810(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 (48.4 kHz)
>(II) I810(0): Modeline "1024x768"x85.0   94.50  1024 1072 1168 1376  768 769 772 808 +hsync +vsync (68.7 kHz)
>(II) I810(0): Modeline "1024x768"x75.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz)
>(II) I810(0): Modeline "1024x768"x70.1   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz)
>(II) I810(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) I810(0): Modeline "832x624"x74.6   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz)
>(II) I810(0): Modeline "800x600"x85.1   56.30  800 832 896 1048  600 601 604 631 +hsync +vsync (53.7 kHz)
>(II) I810(0): Modeline "800x600"x72.2   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz)
>(II) I810(0): Modeline "800x600"x75.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz)
>(II) I810(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) I810(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz)
>(II) I810(0): Modeline "640x480"x85.0   36.00  640 696 752 832  480 481 484 509 -hsync -vsync (43.3 kHz)
>(II) I810(0): Modeline "640x480"x72.8   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz)
>(II) I810(0): Modeline "640x480"x75.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz)
>(II) I810(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) I810(0): Modeline "720x400"x85.0   35.50  720 756 828 936  400 401 404 446 -hsync +vsync (37.9 kHz)
>(II) I810(0): Modeline "640x400"x85.1   31.50  640 672 736 832  400 401 404 445 -hsync +vsync (37.9 kHz)
>(II) I810(0): Modeline "640x350"x85.1   31.50  640 672 736 832  350 382 385 445 +hsync -vsync (37.9 kHz)
>(II) I810(0): Monitoring connected displays enabled
>(--) I810(0): Pre-allocated VideoRam: 32636 kByte
>(==) I810(0): Potential VideoRam: 131072 kByte
>(==) I810(0): video overlay key set to 0x101fe
>(**) I810(0): page flipping disabled
>(==) I810(0): Using gamma correction (1.0, 1.0, 1.0)
>(II) I810(0): move blank start from 1024 to 1024
>(II) I810(0): move blank start from 1024 to 1024
>(II) I810(0): move blank start from 1024 to 1024
>(II) I810(0): move blank start from 1024 to 1024
>(II) I810(0): move blank start from 1024 to 1024
>(II) I810(0): move blank start from 832 to 832
>(II) I810(0): move blank start from 800 to 800
>(II) I810(0): move blank start from 800 to 800
>(II) I810(0): move blank start from 800 to 800
>(II) I810(0): move blank start from 800 to 800
>(II) I810(0): move blank start from 800 to 800
>(II) I810(0): move blank start from 640 to 640
>(II) I810(0): move blank start from 640 to 640
>(II) I810(0): move blank start from 640 to 640
>(II) I810(0): move blank start from 640 to 640
>(II) I810(0): move blank start from 720 to 720
>(II) I810(0): move blank start from 640 to 640
>(II) I810(0): move blank start from 640 to 640
>(WW) I810(0): DRM memory manager will be disabled
>	to make room for video memory
>(==) I810(0): VideoRam: 72704 KB
>(==) I810(0): DPI set to (75, 75)
>(II) Loading sub module "fb"
>(II) LoadModule: "fb"
>(II) Loading /opt/X11R7/lib/xorg/modules//libfb.so
>(II) Module fb: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.0.0
>	ABI class: X.Org ANSI C Emulation, version 0.3
>(II) Loading sub module "xaa"
>(II) LoadModule: "xaa"
>(II) Loading /opt/X11R7/lib/xorg/modules//libxaa.so
>(II) Module xaa: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.2.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) Loading sub module "ramdac"
>(II) LoadModule: "ramdac"
>(II) Loading /opt/X11R7/lib/xorg/modules//libramdac.so
>(II) Module ramdac: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) I810(0): Comparing regs from server start up to After PreInit
>(II) Loading sub module "shadow"
>(II) LoadModule: "shadow"
>(II) Loading /opt/X11R7/lib/xorg/modules//libshadow.so
>(II) Module shadow: vendor="X.Org Foundation"
>	compiled for 7.1.99.903, module version = 1.1.0
>	ABI class: X.Org ANSI C Emulation, version 0.3
>(==) Depth 24 pixmap format is 32 bpp
>(II) do I need RAC?  No, I don't.
>(II) resource ranges after preInit:
>	[0] 1	0	0xf0000000 - 0xf007ffff (0x80000) MS[B]
>	[1] 1	0	0xb0000000 - 0xb7ffffff (0x8000000) MS[B]
>	[2] -1	0	0x00100000 - 0x17ffffff (0x17f00000) MX[B]E(B)
>	[3] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[4] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[5] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[6] -1	0	0xe0000000 - 0xe0000fff (0x1000) MX[B]
>	[7] -1	0	0xe0001000 - 0xe0001fff (0x1000) MX[B]
>	[8] -1	0	0xf0080600 - 0xf00806ff (0x100) MX[B]
>	[9] -1	0	0xf0080400 - 0xf00805ff (0x200) MX[B]
>	[10] -1	0	0x18080000 - 0x180803ff (0x400) MX[B]
>	[11] -1	0	0xf4000000 - 0xf40003ff (0x400) MX[B]
>	[12] -1	0	0xf0000000 - 0xf007ffff (0x80000) MX[B](B)
>	[13] -1	0	0xb0000000 - 0xb7ffffff (0x8000000) MX[B](B)
>	[14] -1	0	0x18000000 - 0x1807ffff (0x80000) MX[B](B)
>	[15] -1	0	0x10000000 - 0x17ffffff (0x8000000) MX[B](B)
>	[16] 1	0	0x000a0000 - 0x000affff (0x10000) MS[B](OprD)
>	[17] 1	0	0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD)
>	[18] 1	0	0x000b8000 - 0x000bffff (0x8000) MS[B](OprD)
>	[19] 1	0	0x0000e000 - 0x0000e007 (0x8) IS[B]
>	[20] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[21] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[22] -1	0	0x0000c000 - 0x0000c03f (0x40) IX[B]
>	[23] -1	0	0x0000e400 - 0x0000e47f (0x80) IX[B]
>	[24] -1	0	0x0000e300 - 0x0000e3ff (0x100) IX[B]
>	[25] -1	0	0x0000e200 - 0x0000e23f (0x40) IX[B]
>	[26] -1	0	0x0000e100 - 0x0000e1ff (0x100) IX[B]
>	[27] -1	0	0x00001400 - 0x0000141f (0x20) IX[B]
>	[28] -1	0	0x00001100 - 0x0000110f (0x10) IX[B]
>	[29] -1	0	0x00001700 - 0x0000171f (0x20) IX[B]
>	[30] -1	0	0x00001200 - 0x0000121f (0x20) IX[B]
>	[31] -1	0	0x0000e000 - 0x0000e007 (0x8) IX[B](B)
>	[32] 1	0	0x000003b0 - 0x000003bb (0xc) IS[B](OprU)
>	[33] 1	0	0x000003c0 - 0x000003df (0x20) IS[B](OprU)
>(II) I810(0): Allocated 128 kB for the ring buffer at 0x0
>(II) I810(0): Allocating at least 4344 scanlines for pixmap cache
>(II) I810(0): Initial framebuffer allocation size: 21472 kByte
>(II) I810(0): Allocated 4 kB for HW cursor at 0x7fff000 (0x09bd1000)
>(II) I810(0): Allocated 16 kB for HW (ARGB) cursor at 0x7ffb000 (0x094a8000)
>(II) I810(0): Allocated 4 kB for Overlay registers at 0x7ffa000 (0x0949d000).
>(II) I810(0): Allocated 64 kB for the scratch buffer at 0x7fea000
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is -1, (No such device or address)
>drmOpenDevice: open result is -1, (No such device or address)
>drmOpenDevice: Open failed
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is -1, (No such device or address)
>drmOpenDevice: open result is -1, (No such device or address)
>drmOpenDevice: Open failed
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 9, (OK)
>drmOpenByBusid: drmOpenMinor returns 9
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(II) I810(0): [drm] loaded kernel module for "i915" driver
>(II) I810(0): [drm] DRM interface version 1.3
>(II) I810(0): [drm] created "i915" driver at busid "pci:0000:00:02.0"
>(II) I810(0): [drm] added 8192 byte SAREA at 0xce99b000
>(II) I810(0): [drm] mapped SAREA 0xce99b000 to 0xb7d37000
>(II) I810(0): [drm] framebuffer handle = 0xb0020000
>(II) I810(0): [drm] added 1 reserved context for kernel
>(II) I810(0): Not enabling the DRM memory manager.
>(II) I810(0): Allocated 32 kB for the logical context at 0x7fe2000.
>(II) I810(0): Allocated 3072 kB for the back buffer at 0x7800000.
>(II) I810(0): Allocated 3072 kB for the depth buffer at 0x7400000.
>(II) I810(0): Allocated 44800 kB for textures at 0x1518000
>(II) I810(0): 0x81f4a10: Memory at offset 0x00020000, size 21472 kBytes
>(II) I810(0): 0x81ffef8: Memory at offset 0x07fff000, size 4 kBytes
>(II) I810(0): 0x8200450: Memory at offset 0x07ffb000, size 16 kBytes
>(II) I810(0): 0x81f677c: Memory at offset 0x00000000, size 128 kBytes
>(II) I810(0): 0x81f4a50: Memory at offset 0x07fea000, size 64 kBytes
>(II) I810(0): 0x8200478: Memory at offset 0x07ffa000, size 4 kBytes
>(II) I810(0): 0x81f4b8c: Memory at offset 0x07fe2000, size 32 kBytes
>(II) I810(0): 0x81f4bac: Memory at offset 0x07800000, size 3072 kBytes
>(II) I810(0): 0x81f4bcc: Memory at offset 0x07400000, size 3072 kBytes
>(II) I810(0): 0x81f4bec: Memory at offset 0x01518000, size 44800 kBytes
>(II) I810(0): Activating tiled memory for the back buffer.
>(II) I810(0): Activating tiled memory for the depth buffer.
>(II) I810(0): [drm] Registers = 0xf0000000
>(II) I810(0): [drm] ring buffer = 0xb0000000
>(II) I810(0): [drm] init sarea width,height = 1024 x 768 (pitch 1024)
>(II) I810(0): [drm] Mapping front buffer
>(II) I810(0): [drm] Front Buffer = 0x26004000
>(II) I810(0): [drm] Back Buffer = 0xb7800000
>(II) I810(0): [drm] Depth Buffer = 0xb7400000
>(II) I810(0): [drm] textures = 0xb1518000
>(II) I810(0): [drm] Initialized kernel agp heap manager, 45875200
>(II) I810(0): [dri] visual configs initialized
>(==) I810(0): Write-combining range (0xb0000000,0x8000000)
>(II) I810(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000
>(II) I810(0): xf86BindGARTMemory: bind key 7 at 0x01fdf000 (pgoffset 8159)
>(II) I810(0): xf86BindGARTMemory: bind key 0 at 0x07fff000 (pgoffset 32767)
>(II) I810(0): xf86BindGARTMemory: bind key 1 at 0x07ffb000 (pgoffset 32763)
>(II) I810(0): xf86BindGARTMemory: bind key 3 at 0x07fea000 (pgoffset 32746)
>(II) I810(0): xf86BindGARTMemory: bind key 2 at 0x07ffa000 (pgoffset 32762)
>(II) I810(0): xf86BindGARTMemory: bind key 4 at 0x07fe2000 (pgoffset 32738)
>(II) I810(0): xf86BindGARTMemory: bind key 5 at 0x07800000 (pgoffset 30720)
>(II) I810(0): xf86BindGARTMemory: bind key 6 at 0x07400000 (pgoffset 29696)
>(II) I810(0): Disabling unused functions
>(II) I810(0): Disabling output TMDS
>chosen: dotclock 65000 vco 1040000 ((m 130, m1 21, m2 13), n 4, (p 16, p1 2, p2 1))
>clock regs: 0x90820000, 0x0004150d
>chosen: dotclock 65000 vco 1040000 ((m 130, m1 21, m2 13), n 4, (p 16, p1 2, p2 1))
>clock regs: 0x90820000, 0x0004150d
>(II) I810(0): DumpRegsBegin
>(II) I810(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) I810(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) I810(0):        VCLK_POST_DIV: 0x0000888b
>(II) I810(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) I810(0):              D_STATE: 0x0000030f
>(II) I810(0):        DSPCLK_GATE_D: 0x00000000
>(II) I810(0):       RENCLK_GATE_D1: 0x00000000
>(II) I810(0):       RENCLK_GATE_D2: 0x00000000
>(II) I810(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) I810(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) I810(0):              SDVOUDI: 0x00000000
>(II) I810(0):               DSPARB: 0x00015455
>(II) I810(0):               DSPFW1: 0x00000000
>(II) I810(0):               DSPFW2: 0x00000000
>(II) I810(0):               DSPFW3: 0x00000000
>(II) I810(0):                 ADPA: 0x80000000
>(II) I810(0):                 LVDS: 0xc0000300 (enabled, pipe B)
>(II) I810(0):                 DVOA: 0x00000000
>(II) I810(0):                 DVOB: 0x00000000
>(II) I810(0):                 DVOC: 0x00000000
>(II) I810(0):          DVOA_SRCDIM: 0x00000000
>(II) I810(0):          DVOB_SRCDIM: 0x00000000
>(II) I810(0):          DVOC_SRCDIM: 0x00000000
>(II) I810(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) I810(0):            PP_STATUS: 0xd000000a (on, ready, sequencing on)
>(II) I810(0):         PFIT_CONTROL: 0x80000668
>(II) I810(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) I810(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) I810(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) I810(0):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II) I810(0):           DSPASTRIDE: 0x00001000 (4096 bytes)
>(II) I810(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) I810(0):             DSPASIZE: 0x02ff03ff (1024, 768)
>(II) I810(0):             DSPABASE: 0x00020000
>(II) I810(0):             DSPASURF: 0x00000000
>(II) I810(0):          DSPATILEOFF: 0x00000000
>(II) I810(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) I810(0):             PIPEASRC: 0x03ff02ff (1024, 768)
>(II) I810(0):                 FPA0: 0x0004150d (n = 4, m1 = 21, m2 = 13)
>(II) I810(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):               DPLL_A: 0x90820000 (enabled, non-dvo, unknown mode, default clock, p1 = 2, p2 = 0)
>(II) I810(0):            DPLL_A_MD: 0x00000000
>(II) I810(0):             HTOTAL_A: 0x053f03ff (1024 active, 1344 total)
>(II) I810(0):             HBLANK_A: 0x053f03ff (1024 start, 1344 end)
>(II) I810(0):              HSYNC_A: 0x049f0417 (1048 start, 1184 end)
>(II) I810(0):             VTOTAL_A: 0x032502ff (768 active, 806 total)
>(II) I810(0):             VBLANK_A: 0x032502ff (768 start, 806 end)
>(II) I810(0):              VSYNC_A: 0x03080302 (771 start, 777 end)
>(II) I810(0):            BCLRPAT_A: 0x00000000
>(II) I810(0):         VSYNCSHIFT_A: 0x00000000
>(II) I810(0):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II) I810(0):           DSPBSTRIDE: 0x00001000 (4096 bytes)
>(II) I810(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) I810(0):             DSPBSIZE: 0x02ff03ff (1024, 768)
>(II) I810(0):             DSPBBASE: 0x00020000
>(II) I810(0):             DSPBSURF: 0x00000000
>(II) I810(0):          DSPBTILEOFF: 0x00000000
>(II) I810(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) I810(0):             PIPEBSRC: 0x03ff02ff (1024, 768)
>(II) I810(0):                 FPB0: 0x0004150d (n = 4, m1 = 21, m2 = 13)
>(II) I810(0):                 FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):               DPLL_B: 0x90820000 (enabled, non-dvo, unknown mode, default clock, p1 = 2, p2 = 0)
>(II) I810(0):            DPLL_B_MD: 0x00000000
>(II) I810(0):             HTOTAL_B: 0x053f03ff (1024 active, 1344 total)
>(II) I810(0):             HBLANK_B: 0x053f03ff (1024 start, 1344 end)
>(II) I810(0):              HSYNC_B: 0x049f0417 (1048 start, 1184 end)
>(II) I810(0):             VTOTAL_B: 0x032502ff (768 active, 806 total)
>(II) I810(0):             VBLANK_B: 0x032502ff (768 start, 806 end)
>(II) I810(0):              VSYNC_B: 0x03080302 (771 start, 777 end)
>(II) I810(0):            BCLRPAT_B: 0x00000000
>(II) I810(0):         VSYNCSHIFT_B: 0x00000000
>(II) I810(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) I810(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) I810(0):        VCLK_POST_DIV: 0x0000888b
>(II) I810(0):             VGACNTRL: 0x80000000 (disabled)
>(II) I810(0):               TV_CTL: 0x00000000
>(II) I810(0):               TV_DAC: 0x00000000
>(II) I810(0):             TV_CSC_Y: 0x00000000
>(II) I810(0):            TV_CSC_Y2: 0x00000000
>(II) I810(0):             TV_CSC_U: 0x00000000
>(II) I810(0):            TV_CSC_U2: 0x00000000
>(II) I810(0):             TV_CSC_V: 0x00000000
>(II) I810(0):            TV_CSC_V2: 0x00000000
>(II) I810(0):         TV_CLR_KNOBS: 0x00000000
>(II) I810(0):         TV_CLR_LEVEL: 0x00000000
>(II) I810(0):           TV_H_CTL_1: 0x00000000
>(II) I810(0):           TV_H_CTL_2: 0x00000000
>(II) I810(0):           TV_H_CTL_3: 0x00000000
>(II) I810(0):           TV_V_CTL_1: 0x00000000
>(II) I810(0):           TV_V_CTL_2: 0x00000000
>(II) I810(0):           TV_V_CTL_3: 0x00000000
>(II) I810(0):           TV_V_CTL_4: 0x00000000
>(II) I810(0):           TV_V_CTL_5: 0x00000000
>(II) I810(0):           TV_V_CTL_6: 0x00000000
>(II) I810(0):           TV_V_CTL_7: 0x00000000
>(II) I810(0):          TV_SC_CTL_1: 0x00000000
>(II) I810(0):          TV_SC_CTL_2: 0x00000000
>(II) I810(0):          TV_SC_CTL_3: 0x00000000
>(II) I810(0):           TV_WIN_POS: 0x00000000
>(II) I810(0):          TV_WIN_SIZE: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_1: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_2: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_3: 0x00000000
>(II) I810(0):        TV_CC_CONTROL: 0x00000000
>(II) I810(0):           TV_CC_DATA: 0x00000000
>(II) I810(0):          TV_H_LUMA_0: 0x00000000
>(II) I810(0):         TV_H_LUMA_59: 0x00000000
>(II) I810(0):        TV_H_CHROMA_0: 0x00000000
>(II) I810(0):       TV_H_CHROMA_59: 0x00000000
>(II) I810(0):                 SR00: 0x03
>(II) I810(0):                 SR01: 0x00
>(II) I810(0):                 SR02: 0x03
>(II) I810(0):                 SR03: 0x04
>(II) I810(0):                 SR04: 0x02
>(II) I810(0):                 SR05: 0x00
>(II) I810(0):                 SR06: 0x00
>(II) I810(0):                 SR07: 0x00
>(II) I810(0):                  MSR: 0x67
>(II) I810(0):                 CR00: 0x5f
>(II) I810(0):                 CR01: 0x4f
>(II) I810(0):                 CR02: 0x50
>(II) I810(0):                 CR03: 0x82
>(II) I810(0):                 CR04: 0x55
>(II) I810(0):                 CR05: 0x81
>(II) I810(0):                 CR06: 0xbf
>(II) I810(0):                 CR07: 0x1f
>(II) I810(0):                 CR08: 0x00
>(II) I810(0):                 CR09: 0x4f
>(II) I810(0):                 CR0a: 0x1f
>(II) I810(0):                 CR0b: 0x1e
>(II) I810(0):                 CR0c: 0x00
>(II) I810(0):                 CR0d: 0x00
>(II) I810(0):                 CR0e: 0x00
>(II) I810(0):                 CR0f: 0x00
>(II) I810(0):                 CR10: 0x9c
>(II) I810(0):                 CR11: 0x0e
>(II) I810(0):                 CR12: 0x8f
>(II) I810(0):                 CR13: 0x28
>(II) I810(0):                 CR14: 0x1f
>(II) I810(0):                 CR15: 0x96
>(II) I810(0):                 CR16: 0xb9
>(II) I810(0):                 CR17: 0xa3
>(II) I810(0):                 CR18: 0xff
>(II) I810(0):                 CR19: 0x00
>(II) I810(0):                 CR1a: 0x00
>(II) I810(0):                 CR1b: 0x00
>(II) I810(0):                 CR1c: 0x00
>(II) I810(0):                 CR1d: 0x00
>(II) I810(0):                 CR1e: 0x00
>(II) I810(0):                 CR1f: 0x00
>(II) I810(0):                 CR20: 0x00
>(II) I810(0):                 CR21: 0x00
>(II) I810(0):                 CR22: 0x00
>(II) I810(0):                 CR23: 0x00
>(II) I810(0):                 CR24: 0x00
>(EE) I810(0): p1 out of range
>(II) I810(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) I810(0): pipe A dot 208000 n 4 m1 21 m2 13 p1 1 p2 10
>(EE) I810(0): p1 out of range
>(II) I810(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) I810(0): pipe B dot 208000 n 4 m1 21 m2 13 p1 1 p2 10
>(II) I810(0): DumpRegsEnd
>(II) I810(0): Output configuration:
>(II) I810(0):   Pipe A is on
>(II) I810(0):   Display plane A is now enabled and connected to pipe A.
>(II) I810(0):   Pipe B is on
>(II) I810(0):   Display plane B is now enabled and connected to pipe B.
>(II) I810(0):   Output VGA is connected to pipe A
>(II) I810(0):   Output LVDS is connected to pipe B
>(II) I810(0):   Output TMDS is connected to pipe none
>(II) I810(0): Using XFree86 Acceleration Architecture (XAA)
>	Screen to screen bit blits
>	Solid filled rectangles
>	8x8 mono pattern filled rectangles
>	Indirect CPU to Screen color expansion
>	Solid Horizontal and Vertical Lines
>	Offscreen Pixmaps
>	Setting up tile and stipple cache:
>		32 128x128 slots
>		26 256x256 slots
>		8 512x512 slots
>(==) I810(0): Backing store disabled
>(==) I810(0): Silken mouse enabled
>(II) I810(0): Initializing HW Cursor
>(**) Option "dpms"
>(**) I810(0): DPMS enabled
>(II) I810(0): Set up overlay video
>(II) I810(0): X context handle = 0x1
>(II) I810(0): [drm] installed DRM signal handler
>(II) I810(0): [DRI] installation complete
>(II) I810(0): [drm] dma control initialized, using IRQ 10
>(II) I810(0): direct rendering: Enabled
>(II) I810(0): RandR enabled, ignore the following RandR disabled message.
>(II) I810(0): Rotating to 0 degrees
>(--) RandR disabled
>(II) Initializing built-in extension MIT-SHM
>(II) Initializing built-in extension XInputExtension
>(II) Initializing built-in extension XTEST
>(II) Initializing built-in extension XKEYBOARD
>(II) Initializing built-in extension XC-APPGROUP
>(II) Initializing built-in extension XAccessControlExtension
>(II) Initializing built-in extension SECURITY
>(II) Initializing built-in extension XINERAMA
>(II) Initializing built-in extension XFIXES
>(II) Initializing built-in extension XFree86-Bigfont
>(II) Initializing built-in extension RENDER
>(II) Initializing built-in extension RANDR
>(II) Initializing built-in extension COMPOSITE
>(II) Initializing built-in extension DAMAGE
>(II) Initializing built-in extension XEVIE
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 10, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 10, (OK)
>drmOpenByBusid: drmOpenMinor returns 10
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(WW) AIGLX: 3D driver claims to not support visual 0x23
>(WW) AIGLX: 3D driver claims to not support visual 0x24
>(WW) AIGLX: 3D driver claims to not support visual 0x25
>(WW) AIGLX: 3D driver claims to not support visual 0x26
>(WW) AIGLX: 3D driver claims to not support visual 0x27
>(WW) AIGLX: 3D driver claims to not support visual 0x28
>(WW) AIGLX: 3D driver claims to not support visual 0x29
>(WW) AIGLX: 3D driver claims to not support visual 0x2a
>(WW) AIGLX: 3D driver claims to not support visual 0x2b
>(WW) AIGLX: 3D driver claims to not support visual 0x2c
>(WW) AIGLX: 3D driver claims to not support visual 0x2d
>(WW) AIGLX: 3D driver claims to not support visual 0x2e
>(WW) AIGLX: 3D driver claims to not support visual 0x2f
>(WW) AIGLX: 3D driver claims to not support visual 0x30
>(WW) AIGLX: 3D driver claims to not support visual 0x31
>(WW) AIGLX: 3D driver claims to not support visual 0x32
>(II) AIGLX: Loaded and initialized /opt/X11R7/lib/dri/i915_dri.so
>(II) GLX: Initialized DRI GL provider for screen 0
>(II) I810(0): Setting screen physical size to 347 x 260
>(**) Option "Protocol" "IMPS/2"
>(**) Mouse0: Device: "/dev/input/mice"
>(**) Mouse0: Protocol: "IMPS/2"
>(**) Option "CorePointer"
>(**) Mouse0: Core Pointer
>(**) Option "Device" "/dev/input/mice"
>(**) Option "Emulate3Buttons" "yes"
>(**) Mouse0: Emulate3Buttons, Emulate3Timeout: 50
>(**) Option "ZAxisMapping" "4 5"
>(**) Mouse0: ZAxisMapping: buttons 4 and 5
>(**) Mouse0: Buttons: 9
>(**) Option "CoreKeyboard"
>(**) Keyboard0: Core Keyboard
>(**) Option "Protocol" "standard"
>(**) Keyboard0: Protocol: standard
>(**) Option "AutoRepeat" "500 30"
>(**) Option "XkbRules" "xorg"
>(**) Keyboard0: XkbRules: "xorg"
>(**) Option "XkbModel" "pc105"
>(**) Keyboard0: XkbModel: "pc105"
>(**) Option "XkbLayout" "us"
>(**) Keyboard0: XkbLayout: "us"
>(**) Option "CustomKeycodes" "off"
>(**) Keyboard0: CustomKeycodes disabled
>(II) XINPUT: Adding extended input device "Keyboard0" (type: KEYBOARD)
>(II) XINPUT: Adding extended input device "Mouse0" (type: MOUSE)
>(II) Mouse0: ps2EnableDataReporting: succeeded
>(II) AIGLX: Suspending AIGLX clients for VT switch
>(II) I810(0): Comparing regs from server start up to After LeaveVT
>(WW) I810(0): Register 0x61200 (PP_STATUS) changed from 0xc0000008 to 0xd0000009
>(WW) I810(0): PP_STATUS before: on, ready, sequencing idle
>(WW) I810(0): PP_STATUS after: on, ready, sequencing on
>(II) I810(0): DumpRegsBegin
>(II) I810(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) I810(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) I810(0):        VCLK_POST_DIV: 0x0000888b
>(II) I810(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) I810(0):              D_STATE: 0x0000030f
>(II) I810(0):        DSPCLK_GATE_D: 0x00000000
>(II) I810(0):       RENCLK_GATE_D1: 0x00000000
>(II) I810(0):       RENCLK_GATE_D2: 0x00000000
>(II) I810(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) I810(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) I810(0):              SDVOUDI: 0x00000000
>(II) I810(0):               DSPARB: 0x00015455
>(II) I810(0):               DSPFW1: 0x00000000
>(II) I810(0):               DSPFW2: 0x00000000
>(II) I810(0):               DSPFW3: 0x00000000
>(II) I810(0):                 ADPA: 0x00001c18
>(II) I810(0):                 LVDS: 0xc0000300 (enabled, pipe B)
>(II) I810(0):                 DVOA: 0x00000000
>(II) I810(0):                 DVOB: 0x00000000
>(II) I810(0):                 DVOC: 0x00000000
>(II) I810(0):          DVOA_SRCDIM: 0x00000000
>(II) I810(0):          DVOB_SRCDIM: 0x00000000
>(II) I810(0):          DVOC_SRCDIM: 0x00000000
>(II) I810(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) I810(0):            PP_STATUS: 0xd0000009 (on, ready, sequencing on)
>(II) I810(0):         PFIT_CONTROL: 0x80000668
>(II) I810(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) I810(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) I810(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) I810(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) I810(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) I810(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) I810(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) I810(0):             DSPABASE: 0x00000000
>(II) I810(0):             DSPASURF: 0x00000000
>(II) I810(0):          DSPATILEOFF: 0x00000000
>(II) I810(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) I810(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) I810(0):                 FPA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):               DPLL_A: 0x808b0000 (enabled, non-dvo, VGA, unknown mode, default clock, p1 = 1, p2 = 0)
>(II) I810(0):            DPLL_A_MD: 0x00000000
>(II) I810(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) I810(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) I810(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) I810(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) I810(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) I810(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) I810(0):            BCLRPAT_A: 0x00000000
>(II) I810(0):         VSYNCSHIFT_A: 0x00000000
>(II) I810(0):             DSPBCNTR: 0x49000000 (disabled, pipe B)
>(II) I810(0):           DSPBSTRIDE: 0x00000280 (640 bytes)
>(II) I810(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) I810(0):             DSPBSIZE: 0x01df027f (640, 480)
>(II) I810(0):             DSPBBASE: 0x00000000
>(II) I810(0):             DSPBSURF: 0x00000000
>(II) I810(0):          DSPBTILEOFF: 0x00000000
>(II) I810(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) I810(0):             PIPEBSRC: 0x027f018f (640, 400)
>(II) I810(0):                 FPB0: 0x0004120c (n = 4, m1 = 18, m2 = 12)
>(II) I810(0):                 FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):               DPLL_B: 0x90010000 (enabled, non-dvo, unknown mode, default clock, p1 = 1, p2 = 0)
>(II) I810(0):            DPLL_B_MD: 0x00000000
>(II) I810(0):             HTOTAL_B: 0x053f03ff (1024 active, 1344 total)
>(II) I810(0):             HBLANK_B: 0x053f03ff (1024 start, 1344 end)
>(II) I810(0):              HSYNC_B: 0x049f0417 (1048 start, 1184 end)
>(II) I810(0):             VTOTAL_B: 0x032502ff (768 active, 806 total)
>(II) I810(0):             VBLANK_B: 0x032502ff (768 start, 806 end)
>(II) I810(0):              VSYNC_B: 0x03080302 (771 start, 777 end)
>(II) I810(0):            BCLRPAT_B: 0x00000000
>(II) I810(0):         VSYNCSHIFT_B: 0x00000000
>(II) I810(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) I810(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) I810(0):        VCLK_POST_DIV: 0x0000888b
>(II) I810(0):             VGACNTRL: 0x2204008e (enabled)
>(II) I810(0):               TV_CTL: 0x00000000
>(II) I810(0):               TV_DAC: 0x00000000
>(II) I810(0):             TV_CSC_Y: 0x00000000
>(II) I810(0):            TV_CSC_Y2: 0x00000000
>(II) I810(0):             TV_CSC_U: 0x00000000
>(II) I810(0):            TV_CSC_U2: 0x00000000
>(II) I810(0):             TV_CSC_V: 0x00000000
>(II) I810(0):            TV_CSC_V2: 0x00000000
>(II) I810(0):         TV_CLR_KNOBS: 0x00000000
>(II) I810(0):         TV_CLR_LEVEL: 0x00000000
>(II) I810(0):           TV_H_CTL_1: 0x00000000
>(II) I810(0):           TV_H_CTL_2: 0x00000000
>(II) I810(0):           TV_H_CTL_3: 0x00000000
>(II) I810(0):           TV_V_CTL_1: 0x00000000
>(II) I810(0):           TV_V_CTL_2: 0x00000000
>(II) I810(0):           TV_V_CTL_3: 0x00000000
>(II) I810(0):           TV_V_CTL_4: 0x00000000
>(II) I810(0):           TV_V_CTL_5: 0x00000000
>(II) I810(0):           TV_V_CTL_6: 0x00000000
>(II) I810(0):           TV_V_CTL_7: 0x00000000
>(II) I810(0):          TV_SC_CTL_1: 0x00000000
>(II) I810(0):          TV_SC_CTL_2: 0x00000000
>(II) I810(0):          TV_SC_CTL_3: 0x00000000
>(II) I810(0):           TV_WIN_POS: 0x00000000
>(II) I810(0):          TV_WIN_SIZE: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_1: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_2: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_3: 0x00000000
>(II) I810(0):        TV_CC_CONTROL: 0x00000000
>(II) I810(0):           TV_CC_DATA: 0x00000000
>(II) I810(0):          TV_H_LUMA_0: 0x00000000
>(II) I810(0):         TV_H_LUMA_59: 0x00000000
>(II) I810(0):        TV_H_CHROMA_0: 0x00000000
>(II) I810(0):       TV_H_CHROMA_59: 0x00000000
>(II) I810(0):                 SR00: 0x03
>(II) I810(0):                 SR01: 0x00
>(II) I810(0):                 SR02: 0x03
>(II) I810(0):                 SR03: 0x04
>(II) I810(0):                 SR04: 0x02
>(II) I810(0):                 SR05: 0x00
>(II) I810(0):                 SR06: 0x00
>(II) I810(0):                 SR07: 0x00
>(II) I810(0):                  MSR: 0x67
>(II) I810(0):                 CR00: 0x5f
>(II) I810(0):                 CR01: 0x4f
>(II) I810(0):                 CR02: 0x50
>(II) I810(0):                 CR03: 0x82
>(II) I810(0):                 CR04: 0x55
>(II) I810(0):                 CR05: 0x81
>(II) I810(0):                 CR06: 0xbf
>(II) I810(0):                 CR07: 0x1f
>(II) I810(0):                 CR08: 0x00
>(II) I810(0):                 CR09: 0x4f
>(II) I810(0):                 CR0a: 0x1f
>(II) I810(0):                 CR0b: 0x1e
>(II) I810(0):                 CR0c: 0x00
>(II) I810(0):                 CR0d: 0x00
>(II) I810(0):                 CR0e: 0x98
>(II) I810(0):                 CR0f: 0x00
>(II) I810(0):                 CR10: 0x9c
>(II) I810(0):                 CR11: 0x8e
>(II) I810(0):                 CR12: 0x8f
>(II) I810(0):                 CR13: 0x28
>(II) I810(0):                 CR14: 0x1f
>(II) I810(0):                 CR15: 0x96
>(II) I810(0):                 CR16: 0xb9
>(II) I810(0):                 CR17: 0xa3
>(II) I810(0):                 CR18: 0xff
>(II) I810(0):                 CR19: 0x00
>(II) I810(0):                 CR1a: 0x00
>(II) I810(0):                 CR1b: 0x00
>(II) I810(0):                 CR1c: 0x00
>(II) I810(0):                 CR1d: 0x00
>(II) I810(0):                 CR1e: 0x00
>(II) I810(0):                 CR1f: 0x00
>(II) I810(0):                 CR20: 0x00
>(II) I810(0):                 CR21: 0x00
>(II) I810(0):                 CR22: 0x00
>(II) I810(0):                 CR23: 0x00
>(II) I810(0):                 CR24: 0x00
>(EE) I810(0): p1 out of range
>(II) I810(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) I810(0): pipe A dot 261600 n 2 m1 18 m2 7 p1 1 p2 10
>(II) I810(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) I810(0): pipe B dot 182400 n 4 m1 18 m2 12 p1 1 p2 10
>(II) I810(0): DumpRegsEnd
>(II) I810(0): xf86UnbindGARTMemory: unbind key 7
>(II) I810(0): xf86UnbindGARTMemory: unbind key 0
>(II) I810(0): xf86UnbindGARTMemory: unbind key 1
>(II) I810(0): xf86UnbindGARTMemory: unbind key 3
>(II) I810(0): xf86UnbindGARTMemory: unbind key 2
>(II) I810(0): xf86UnbindGARTMemory: unbind key 4
>(II) I810(0): xf86UnbindGARTMemory: unbind key 5
>(II) I810(0): xf86UnbindGARTMemory: unbind key 6
>(WW) Open ACPI failed (/var/run/acpid.socket) (No such file or directory)
>(II) No APM support in BIOS or kernel
>(II) AIGLX: Resuming AIGLX clients after VT switch
>(II) I810(0): xf86BindGARTMemory: bind key 7 at 0x01fdf000 (pgoffset 8159)
>(II) I810(0): xf86BindGARTMemory: bind key 0 at 0x07fff000 (pgoffset 32767)
>(II) I810(0): xf86BindGARTMemory: bind key 1 at 0x07ffb000 (pgoffset 32763)
>(II) I810(0): xf86BindGARTMemory: bind key 3 at 0x07fea000 (pgoffset 32746)
>(II) I810(0): xf86BindGARTMemory: bind key 2 at 0x07ffa000 (pgoffset 32762)
>(II) I810(0): xf86BindGARTMemory: bind key 4 at 0x07fe2000 (pgoffset 32738)
>(II) I810(0): xf86BindGARTMemory: bind key 5 at 0x07800000 (pgoffset 30720)
>(II) I810(0): xf86BindGARTMemory: bind key 6 at 0x07400000 (pgoffset 29696)
>(II) I810(0): Disabling unused functions
>(II) I810(0): Disabling output TMDS
>chosen: dotclock 65000 vco 1040000 ((m 130, m1 21, m2 13), n 4, (p 16, p1 2, p2 1))
>clock regs: 0x90820000, 0x0004150d
>chosen: dotclock 65000 vco 1040000 ((m 130, m1 21, m2 13), n 4, (p 16, p1 2, p2 1))
>clock regs: 0x90820000, 0x0004150d
>(II) I810(0): DumpRegsBegin
>(II) I810(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) I810(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) I810(0):        VCLK_POST_DIV: 0x0000888b
>(II) I810(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) I810(0):              D_STATE: 0x0000030f
>(II) I810(0):        DSPCLK_GATE_D: 0x00000000
>(II) I810(0):       RENCLK_GATE_D1: 0x00000000
>(II) I810(0):       RENCLK_GATE_D2: 0x00000000
>(II) I810(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) I810(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) I810(0):              SDVOUDI: 0x00000000
>(II) I810(0):               DSPARB: 0x00015455
>(II) I810(0):               DSPFW1: 0x00000000
>(II) I810(0):               DSPFW2: 0x00000000
>(II) I810(0):               DSPFW3: 0x00000000
>(II) I810(0):                 ADPA: 0x80000000
>(II) I810(0):                 LVDS: 0xc0000300 (enabled, pipe B)
>(II) I810(0):                 DVOA: 0x00000000
>(II) I810(0):                 DVOB: 0x00000000
>(II) I810(0):                 DVOC: 0x00000000
>(II) I810(0):          DVOA_SRCDIM: 0x00000000
>(II) I810(0):          DVOB_SRCDIM: 0x00000000
>(II) I810(0):          DVOC_SRCDIM: 0x00000000
>(II) I810(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) I810(0):            PP_STATUS: 0xd000000a (on, ready, sequencing on)
>(II) I810(0):         PFIT_CONTROL: 0x80000668
>(II) I810(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) I810(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) I810(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) I810(0):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II) I810(0):           DSPASTRIDE: 0x00001000 (4096 bytes)
>(II) I810(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) I810(0):             DSPASIZE: 0x02ff03ff (1024, 768)
>(II) I810(0):             DSPABASE: 0x00020000
>(II) I810(0):             DSPASURF: 0x00000000
>(II) I810(0):          DSPATILEOFF: 0x00000000
>(II) I810(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) I810(0):             PIPEASRC: 0x03ff02ff (1024, 768)
>(II) I810(0):                 FPA0: 0x0004150d (n = 4, m1 = 21, m2 = 13)
>(II) I810(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):               DPLL_A: 0x90820000 (enabled, non-dvo, unknown mode, default clock, p1 = 2, p2 = 0)
>(II) I810(0):            DPLL_A_MD: 0x00000000
>(II) I810(0):             HTOTAL_A: 0x053f03ff (1024 active, 1344 total)
>(II) I810(0):             HBLANK_A: 0x053f03ff (1024 start, 1344 end)
>(II) I810(0):              HSYNC_A: 0x049f0417 (1048 start, 1184 end)
>(II) I810(0):             VTOTAL_A: 0x032502ff (768 active, 806 total)
>(II) I810(0):             VBLANK_A: 0x032502ff (768 start, 806 end)
>(II) I810(0):              VSYNC_A: 0x03080302 (771 start, 777 end)
>(II) I810(0):            BCLRPAT_A: 0x00000000
>(II) I810(0):         VSYNCSHIFT_A: 0x00000000
>(II) I810(0):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II) I810(0):           DSPBSTRIDE: 0x00001000 (4096 bytes)
>(II) I810(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) I810(0):             DSPBSIZE: 0x02ff03ff (1024, 768)
>(II) I810(0):             DSPBBASE: 0x00020000
>(II) I810(0):             DSPBSURF: 0x00000000
>(II) I810(0):          DSPBTILEOFF: 0x00000000
>(II) I810(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) I810(0):             PIPEBSRC: 0x03ff02ff (1024, 768)
>(II) I810(0):                 FPB0: 0x0004150d (n = 4, m1 = 21, m2 = 13)
>(II) I810(0):                 FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):               DPLL_B: 0x90820000 (enabled, non-dvo, unknown mode, default clock, p1 = 2, p2 = 0)
>(II) I810(0):            DPLL_B_MD: 0x00000000
>(II) I810(0):             HTOTAL_B: 0x053f03ff (1024 active, 1344 total)
>(II) I810(0):             HBLANK_B: 0x053f03ff (1024 start, 1344 end)
>(II) I810(0):              HSYNC_B: 0x049f0417 (1048 start, 1184 end)
>(II) I810(0):             VTOTAL_B: 0x032502ff (768 active, 806 total)
>(II) I810(0):             VBLANK_B: 0x032502ff (768 start, 806 end)
>(II) I810(0):              VSYNC_B: 0x03080302 (771 start, 777 end)
>(II) I810(0):            BCLRPAT_B: 0x00000000
>(II) I810(0):         VSYNCSHIFT_B: 0x00000000
>(II) I810(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) I810(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) I810(0):        VCLK_POST_DIV: 0x0000888b
>(II) I810(0):             VGACNTRL: 0x80000000 (disabled)
>(II) I810(0):               TV_CTL: 0x00000000
>(II) I810(0):               TV_DAC: 0x00000000
>(II) I810(0):             TV_CSC_Y: 0x00000000
>(II) I810(0):            TV_CSC_Y2: 0x00000000
>(II) I810(0):             TV_CSC_U: 0x00000000
>(II) I810(0):            TV_CSC_U2: 0x00000000
>(II) I810(0):             TV_CSC_V: 0x00000000
>(II) I810(0):            TV_CSC_V2: 0x00000000
>(II) I810(0):         TV_CLR_KNOBS: 0x00000000
>(II) I810(0):         TV_CLR_LEVEL: 0x00000000
>(II) I810(0):           TV_H_CTL_1: 0x00000000
>(II) I810(0):           TV_H_CTL_2: 0x00000000
>(II) I810(0):           TV_H_CTL_3: 0x00000000
>(II) I810(0):           TV_V_CTL_1: 0x00000000
>(II) I810(0):           TV_V_CTL_2: 0x00000000
>(II) I810(0):           TV_V_CTL_3: 0x00000000
>(II) I810(0):           TV_V_CTL_4: 0x00000000
>(II) I810(0):           TV_V_CTL_5: 0x00000000
>(II) I810(0):           TV_V_CTL_6: 0x00000000
>(II) I810(0):           TV_V_CTL_7: 0x00000000
>(II) I810(0):          TV_SC_CTL_1: 0x00000000
>(II) I810(0):          TV_SC_CTL_2: 0x00000000
>(II) I810(0):          TV_SC_CTL_3: 0x00000000
>(II) I810(0):           TV_WIN_POS: 0x00000000
>(II) I810(0):          TV_WIN_SIZE: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_1: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_2: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_3: 0x00000000
>(II) I810(0):        TV_CC_CONTROL: 0x00000000
>(II) I810(0):           TV_CC_DATA: 0x00000000
>(II) I810(0):          TV_H_LUMA_0: 0x00000000
>(II) I810(0):         TV_H_LUMA_59: 0x00000000
>(II) I810(0):        TV_H_CHROMA_0: 0x00000000
>(II) I810(0):       TV_H_CHROMA_59: 0x00000000
>(II) I810(0):                 SR00: 0x03
>(II) I810(0):                 SR01: 0x00
>(II) I810(0):                 SR02: 0x03
>(II) I810(0):                 SR03: 0x04
>(II) I810(0):                 SR04: 0x02
>(II) I810(0):                 SR05: 0x00
>(II) I810(0):                 SR06: 0x00
>(II) I810(0):                 SR07: 0x00
>(II) I810(0):                  MSR: 0x67
>(II) I810(0):                 CR00: 0x5f
>(II) I810(0):                 CR01: 0x4f
>(II) I810(0):                 CR02: 0x50
>(II) I810(0):                 CR03: 0x82
>(II) I810(0):                 CR04: 0x55
>(II) I810(0):                 CR05: 0x81
>(II) I810(0):                 CR06: 0xbf
>(II) I810(0):                 CR07: 0x1f
>(II) I810(0):                 CR08: 0x00
>(II) I810(0):                 CR09: 0x4f
>(II) I810(0):                 CR0a: 0x1f
>(II) I810(0):                 CR0b: 0x1e
>(II) I810(0):                 CR0c: 0x00
>(II) I810(0):                 CR0d: 0x00
>(II) I810(0):                 CR0e: 0x00
>(II) I810(0):                 CR0f: 0x00
>(II) I810(0):                 CR10: 0x9c
>(II) I810(0):                 CR11: 0x8e
>(II) I810(0):                 CR12: 0x8f
>(II) I810(0):                 CR13: 0x28
>(II) I810(0):                 CR14: 0x1f
>(II) I810(0):                 CR15: 0x96
>(II) I810(0):                 CR16: 0xb9
>(II) I810(0):                 CR17: 0xa3
>(II) I810(0):                 CR18: 0xff
>(II) I810(0):                 CR19: 0x00
>(II) I810(0):                 CR1a: 0x00
>(II) I810(0):                 CR1b: 0x00
>(II) I810(0):                 CR1c: 0x00
>(II) I810(0):                 CR1d: 0x00
>(II) I810(0):                 CR1e: 0x00
>(II) I810(0):                 CR1f: 0x00
>(II) I810(0):                 CR20: 0x00
>(II) I810(0):                 CR21: 0x00
>(II) I810(0):                 CR22: 0x20
>(II) I810(0):                 CR23: 0x00
>(II) I810(0):                 CR24: 0x00
>(EE) I810(0): p1 out of range
>(II) I810(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) I810(0): pipe A dot 208000 n 4 m1 21 m2 13 p1 1 p2 10
>(EE) I810(0): p1 out of range
>(II) I810(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) I810(0): pipe B dot 208000 n 4 m1 21 m2 13 p1 1 p2 10
>(II) I810(0): DumpRegsEnd
>(II) I810(0): Output configuration:
>(II) I810(0):   Pipe A is on
>(II) I810(0):   Display plane A is now enabled and connected to pipe A.
>(II) I810(0):   Pipe B is on
>(II) I810(0):   Display plane B is now enabled and connected to pipe B.
>(II) I810(0):   Output VGA is connected to pipe A
>(II) I810(0):   Output LVDS is connected to pipe B
>(II) I810(0):   Output TMDS is connected to pipe none
>(II) I810(0): [drm] dma control initialized, using IRQ 10
>(II) Mouse0: ps2EnableDataReporting: succeeded
>(II) AIGLX: Suspending AIGLX clients for VT switch
>(II) I810(0): Comparing regs from server start up to After LeaveVT
>(WW) I810(0): Register 0x61200 (PP_STATUS) changed from 0xc0000008 to 0xd0000009
>(WW) I810(0): PP_STATUS before: on, ready, sequencing idle
>(WW) I810(0): PP_STATUS after: on, ready, sequencing on
>(II) I810(0): DumpRegsBegin
>(II) I810(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) I810(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) I810(0):        VCLK_POST_DIV: 0x0000888b
>(II) I810(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) I810(0):              D_STATE: 0x0000030f
>(II) I810(0):        DSPCLK_GATE_D: 0x00000000
>(II) I810(0):       RENCLK_GATE_D1: 0x00000000
>(II) I810(0):       RENCLK_GATE_D2: 0x00000000
>(II) I810(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) I810(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) I810(0):              SDVOUDI: 0x00000000
>(II) I810(0):               DSPARB: 0x00015455
>(II) I810(0):               DSPFW1: 0x00000000
>(II) I810(0):               DSPFW2: 0x00000000
>(II) I810(0):               DSPFW3: 0x00000000
>(II) I810(0):                 ADPA: 0x00001c18
>(II) I810(0):                 LVDS: 0xc0000300 (enabled, pipe B)
>(II) I810(0):                 DVOA: 0x00000000
>(II) I810(0):                 DVOB: 0x00000000
>(II) I810(0):                 DVOC: 0x00000000
>(II) I810(0):          DVOA_SRCDIM: 0x00000000
>(II) I810(0):          DVOB_SRCDIM: 0x00000000
>(II) I810(0):          DVOC_SRCDIM: 0x00000000
>(II) I810(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) I810(0):            PP_STATUS: 0xd0000009 (on, ready, sequencing on)
>(II) I810(0):         PFIT_CONTROL: 0x80000668
>(II) I810(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) I810(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) I810(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) I810(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) I810(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) I810(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) I810(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) I810(0):             DSPABASE: 0x00000000
>(II) I810(0):             DSPASURF: 0x00000000
>(II) I810(0):          DSPATILEOFF: 0x00000000
>(II) I810(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) I810(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) I810(0):                 FPA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):               DPLL_A: 0x808b0000 (enabled, non-dvo, VGA, unknown mode, default clock, p1 = 1, p2 = 0)
>(II) I810(0):            DPLL_A_MD: 0x00000000
>(II) I810(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) I810(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) I810(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) I810(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) I810(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) I810(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) I810(0):            BCLRPAT_A: 0x00000000
>(II) I810(0):         VSYNCSHIFT_A: 0x00000000
>(II) I810(0):             DSPBCNTR: 0x49000000 (disabled, pipe B)
>(II) I810(0):           DSPBSTRIDE: 0x00000280 (640 bytes)
>(II) I810(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) I810(0):             DSPBSIZE: 0x01df027f (640, 480)
>(II) I810(0):             DSPBBASE: 0x00000000
>(II) I810(0):             DSPBSURF: 0x00000000
>(II) I810(0):          DSPBTILEOFF: 0x00000000
>(II) I810(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) I810(0):             PIPEBSRC: 0x027f018f (640, 400)
>(II) I810(0):                 FPB0: 0x0004120c (n = 4, m1 = 18, m2 = 12)
>(II) I810(0):                 FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):               DPLL_B: 0x90010000 (enabled, non-dvo, unknown mode, default clock, p1 = 1, p2 = 0)
>(II) I810(0):            DPLL_B_MD: 0x00000000
>(II) I810(0):             HTOTAL_B: 0x053f03ff (1024 active, 1344 total)
>(II) I810(0):             HBLANK_B: 0x053f03ff (1024 start, 1344 end)
>(II) I810(0):              HSYNC_B: 0x049f0417 (1048 start, 1184 end)
>(II) I810(0):             VTOTAL_B: 0x032502ff (768 active, 806 total)
>(II) I810(0):             VBLANK_B: 0x032502ff (768 start, 806 end)
>(II) I810(0):              VSYNC_B: 0x03080302 (771 start, 777 end)
>(II) I810(0):            BCLRPAT_B: 0x00000000
>(II) I810(0):         VSYNCSHIFT_B: 0x00000000
>(II) I810(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) I810(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) I810(0):        VCLK_POST_DIV: 0x0000888b
>(II) I810(0):             VGACNTRL: 0x2204008e (enabled)
>(II) I810(0):               TV_CTL: 0x00000000
>(II) I810(0):               TV_DAC: 0x00000000
>(II) I810(0):             TV_CSC_Y: 0x00000000
>(II) I810(0):            TV_CSC_Y2: 0x00000000
>(II) I810(0):             TV_CSC_U: 0x00000000
>(II) I810(0):            TV_CSC_U2: 0x00000000
>(II) I810(0):             TV_CSC_V: 0x00000000
>(II) I810(0):            TV_CSC_V2: 0x00000000
>(II) I810(0):         TV_CLR_KNOBS: 0x00000000
>(II) I810(0):         TV_CLR_LEVEL: 0x00000000
>(II) I810(0):           TV_H_CTL_1: 0x00000000
>(II) I810(0):           TV_H_CTL_2: 0x00000000
>(II) I810(0):           TV_H_CTL_3: 0x00000000
>(II) I810(0):           TV_V_CTL_1: 0x00000000
>(II) I810(0):           TV_V_CTL_2: 0x00000000
>(II) I810(0):           TV_V_CTL_3: 0x00000000
>(II) I810(0):           TV_V_CTL_4: 0x00000000
>(II) I810(0):           TV_V_CTL_5: 0x00000000
>(II) I810(0):           TV_V_CTL_6: 0x00000000
>(II) I810(0):           TV_V_CTL_7: 0x00000000
>(II) I810(0):          TV_SC_CTL_1: 0x00000000
>(II) I810(0):          TV_SC_CTL_2: 0x00000000
>(II) I810(0):          TV_SC_CTL_3: 0x00000000
>(II) I810(0):           TV_WIN_POS: 0x00000000
>(II) I810(0):          TV_WIN_SIZE: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_1: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_2: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_3: 0x00000000
>(II) I810(0):        TV_CC_CONTROL: 0x00000000
>(II) I810(0):           TV_CC_DATA: 0x00000000
>(II) I810(0):          TV_H_LUMA_0: 0x00000000
>(II) I810(0):         TV_H_LUMA_59: 0x00000000
>(II) I810(0):        TV_H_CHROMA_0: 0x00000000
>(II) I810(0):       TV_H_CHROMA_59: 0x00000000
>(II) I810(0):                 SR00: 0x03
>(II) I810(0):                 SR01: 0x00
>(II) I810(0):                 SR02: 0x03
>(II) I810(0):                 SR03: 0x04
>(II) I810(0):                 SR04: 0x02
>(II) I810(0):                 SR05: 0x00
>(II) I810(0):                 SR06: 0x00
>(II) I810(0):                 SR07: 0x00
>(II) I810(0):                  MSR: 0x67
>(II) I810(0):                 CR00: 0x5f
>(II) I810(0):                 CR01: 0x4f
>(II) I810(0):                 CR02: 0x50
>(II) I810(0):                 CR03: 0x82
>(II) I810(0):                 CR04: 0x55
>(II) I810(0):                 CR05: 0x81
>(II) I810(0):                 CR06: 0xbf
>(II) I810(0):                 CR07: 0x1f
>(II) I810(0):                 CR08: 0x00
>(II) I810(0):                 CR09: 0x4f
>(II) I810(0):                 CR0a: 0x1f
>(II) I810(0):                 CR0b: 0x1e
>(II) I810(0):                 CR0c: 0x00
>(II) I810(0):                 CR0d: 0x00
>(II) I810(0):                 CR0e: 0x98
>(II) I810(0):                 CR0f: 0x00
>(II) I810(0):                 CR10: 0x9c
>(II) I810(0):                 CR11: 0x8e
>(II) I810(0):                 CR12: 0x8f
>(II) I810(0):                 CR13: 0x28
>(II) I810(0):                 CR14: 0x1f
>(II) I810(0):                 CR15: 0x96
>(II) I810(0):                 CR16: 0xb9
>(II) I810(0):                 CR17: 0xa3
>(II) I810(0):                 CR18: 0xff
>(II) I810(0):                 CR19: 0x00
>(II) I810(0):                 CR1a: 0x00
>(II) I810(0):                 CR1b: 0x00
>(II) I810(0):                 CR1c: 0x00
>(II) I810(0):                 CR1d: 0x00
>(II) I810(0):                 CR1e: 0x00
>(II) I810(0):                 CR1f: 0x00
>(II) I810(0):                 CR20: 0x00
>(II) I810(0):                 CR21: 0x00
>(II) I810(0):                 CR22: 0x20
>(II) I810(0):                 CR23: 0x00
>(II) I810(0):                 CR24: 0x00
>(EE) I810(0): p1 out of range
>(II) I810(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) I810(0): pipe A dot 261600 n 2 m1 18 m2 7 p1 1 p2 10
>(II) I810(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) I810(0): pipe B dot 182400 n 4 m1 18 m2 12 p1 1 p2 10
>(II) I810(0): DumpRegsEnd
>(II) I810(0): xf86UnbindGARTMemory: unbind key 7
>(II) I810(0): xf86UnbindGARTMemory: unbind key 0
>(II) I810(0): xf86UnbindGARTMemory: unbind key 1
>(II) I810(0): xf86UnbindGARTMemory: unbind key 3
>(II) I810(0): xf86UnbindGARTMemory: unbind key 2
>(II) I810(0): xf86UnbindGARTMemory: unbind key 4
>(II) I810(0): xf86UnbindGARTMemory: unbind key 5
>(II) I810(0): xf86UnbindGARTMemory: unbind key 6
>(WW) Open ACPI failed (/var/run/acpid.socket) (No such file or directory)
>(II) No APM support in BIOS or kernel
>(II) AIGLX: Resuming AIGLX clients after VT switch
>(II) I810(0): xf86BindGARTMemory: bind key 7 at 0x01fdf000 (pgoffset 8159)
>(II) I810(0): xf86BindGARTMemory: bind key 0 at 0x07fff000 (pgoffset 32767)
>(II) I810(0): xf86BindGARTMemory: bind key 1 at 0x07ffb000 (pgoffset 32763)
>(II) I810(0): xf86BindGARTMemory: bind key 3 at 0x07fea000 (pgoffset 32746)
>(II) I810(0): xf86BindGARTMemory: bind key 2 at 0x07ffa000 (pgoffset 32762)
>(II) I810(0): xf86BindGARTMemory: bind key 4 at 0x07fe2000 (pgoffset 32738)
>(II) I810(0): xf86BindGARTMemory: bind key 5 at 0x07800000 (pgoffset 30720)
>(II) I810(0): xf86BindGARTMemory: bind key 6 at 0x07400000 (pgoffset 29696)
>(II) I810(0): Disabling unused functions
>(II) I810(0): Disabling output TMDS
>chosen: dotclock 65000 vco 1040000 ((m 130, m1 21, m2 13), n 4, (p 16, p1 2, p2 1))
>clock regs: 0x90820000, 0x0004150d
>chosen: dotclock 65000 vco 1040000 ((m 130, m1 21, m2 13), n 4, (p 16, p1 2, p2 1))
>clock regs: 0x90820000, 0x0004150d
>(II) I810(0): DumpRegsBegin
>(II) I810(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) I810(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) I810(0):        VCLK_POST_DIV: 0x0000888b
>(II) I810(0):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II) I810(0):              D_STATE: 0x0000030f
>(II) I810(0):        DSPCLK_GATE_D: 0x00000000
>(II) I810(0):       RENCLK_GATE_D1: 0x00000000
>(II) I810(0):       RENCLK_GATE_D2: 0x00000000
>(II) I810(0):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) I810(0):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II) I810(0):              SDVOUDI: 0x00000000
>(II) I810(0):               DSPARB: 0x00015455
>(II) I810(0):               DSPFW1: 0x00000000
>(II) I810(0):               DSPFW2: 0x00000000
>(II) I810(0):               DSPFW3: 0x00000000
>(II) I810(0):                 ADPA: 0x80000000
>(II) I810(0):                 LVDS: 0xc0000300 (enabled, pipe B)
>(II) I810(0):                 DVOA: 0x00000000
>(II) I810(0):                 DVOB: 0x00000000
>(II) I810(0):                 DVOC: 0x00000000
>(II) I810(0):          DVOA_SRCDIM: 0x00000000
>(II) I810(0):          DVOB_SRCDIM: 0x00000000
>(II) I810(0):          DVOC_SRCDIM: 0x00000000
>(II) I810(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) I810(0):            PP_STATUS: 0xd000000a (on, ready, sequencing on)
>(II) I810(0):         PFIT_CONTROL: 0x80000668
>(II) I810(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) I810(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) I810(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) I810(0):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II) I810(0):           DSPASTRIDE: 0x00001000 (4096 bytes)
>(II) I810(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) I810(0):             DSPASIZE: 0x02ff03ff (1024, 768)
>(II) I810(0):             DSPABASE: 0x00020000
>(II) I810(0):             DSPASURF: 0x00000000
>(II) I810(0):          DSPATILEOFF: 0x00000000
>(II) I810(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) I810(0):             PIPEASRC: 0x03ff02ff (1024, 768)
>(II) I810(0):                 FPA0: 0x0004150d (n = 4, m1 = 21, m2 = 13)
>(II) I810(0):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):               DPLL_A: 0x90820000 (enabled, non-dvo, unknown mode, default clock, p1 = 2, p2 = 0)
>(II) I810(0):            DPLL_A_MD: 0x00000000
>(II) I810(0):             HTOTAL_A: 0x053f03ff (1024 active, 1344 total)
>(II) I810(0):             HBLANK_A: 0x053f03ff (1024 start, 1344 end)
>(II) I810(0):              HSYNC_A: 0x049f0417 (1048 start, 1184 end)
>(II) I810(0):             VTOTAL_A: 0x032502ff (768 active, 806 total)
>(II) I810(0):             VBLANK_A: 0x032502ff (768 start, 806 end)
>(II) I810(0):              VSYNC_A: 0x03080302 (771 start, 777 end)
>(II) I810(0):            BCLRPAT_A: 0x00000000
>(II) I810(0):         VSYNCSHIFT_A: 0x00000000
>(II) I810(0):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II) I810(0):           DSPBSTRIDE: 0x00001000 (4096 bytes)
>(II) I810(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) I810(0):             DSPBSIZE: 0x02ff03ff (1024, 768)
>(II) I810(0):             DSPBBASE: 0x00020000
>(II) I810(0):             DSPBSURF: 0x00000000
>(II) I810(0):          DSPBTILEOFF: 0x00000000
>(II) I810(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) I810(0):             PIPEBSRC: 0x03ff02ff (1024, 768)
>(II) I810(0):                 FPB0: 0x0004150d (n = 4, m1 = 21, m2 = 13)
>(II) I810(0):                 FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II) I810(0):               DPLL_B: 0x90820000 (enabled, non-dvo, unknown mode, default clock, p1 = 2, p2 = 0)
>(II) I810(0):            DPLL_B_MD: 0x00000000
>(II) I810(0):             HTOTAL_B: 0x053f03ff (1024 active, 1344 total)
>(II) I810(0):             HBLANK_B: 0x053f03ff (1024 start, 1344 end)
>(II) I810(0):              HSYNC_B: 0x049f0417 (1048 start, 1184 end)
>(II) I810(0):             VTOTAL_B: 0x032502ff (768 active, 806 total)
>(II) I810(0):             VBLANK_B: 0x032502ff (768 start, 806 end)
>(II) I810(0):              VSYNC_B: 0x03080302 (771 start, 777 end)
>(II) I810(0):            BCLRPAT_B: 0x00000000
>(II) I810(0):         VSYNCSHIFT_B: 0x00000000
>(II) I810(0):    VCLK_DIVISOR_VGA0: 0x00021207
>(II) I810(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) I810(0):        VCLK_POST_DIV: 0x0000888b
>(II) I810(0):             VGACNTRL: 0x80000000 (disabled)
>(II) I810(0):               TV_CTL: 0x00000000
>(II) I810(0):               TV_DAC: 0x00000000
>(II) I810(0):             TV_CSC_Y: 0x00000000
>(II) I810(0):            TV_CSC_Y2: 0x00000000
>(II) I810(0):             TV_CSC_U: 0x00000000
>(II) I810(0):            TV_CSC_U2: 0x00000000
>(II) I810(0):             TV_CSC_V: 0x00000000
>(II) I810(0):            TV_CSC_V2: 0x00000000
>(II) I810(0):         TV_CLR_KNOBS: 0x00000000
>(II) I810(0):         TV_CLR_LEVEL: 0x00000000
>(II) I810(0):           TV_H_CTL_1: 0x00000000
>(II) I810(0):           TV_H_CTL_2: 0x00000000
>(II) I810(0):           TV_H_CTL_3: 0x00000000
>(II) I810(0):           TV_V_CTL_1: 0x00000000
>(II) I810(0):           TV_V_CTL_2: 0x00000000
>(II) I810(0):           TV_V_CTL_3: 0x00000000
>(II) I810(0):           TV_V_CTL_4: 0x00000000
>(II) I810(0):           TV_V_CTL_5: 0x00000000
>(II) I810(0):           TV_V_CTL_6: 0x00000000
>(II) I810(0):           TV_V_CTL_7: 0x00000000
>(II) I810(0):          TV_SC_CTL_1: 0x00000000
>(II) I810(0):          TV_SC_CTL_2: 0x00000000
>(II) I810(0):          TV_SC_CTL_3: 0x00000000
>(II) I810(0):           TV_WIN_POS: 0x00000000
>(II) I810(0):          TV_WIN_SIZE: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_1: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_2: 0x00000000
>(II) I810(0):      TV_FILTER_CTL_3: 0x00000000
>(II) I810(0):        TV_CC_CONTROL: 0x00000000
>(II) I810(0):           TV_CC_DATA: 0x00000000
>(II) I810(0):          TV_H_LUMA_0: 0x00000000
>(II) I810(0):         TV_H_LUMA_59: 0x00000000
>(II) I810(0):        TV_H_CHROMA_0: 0x00000000
>(II) I810(0):       TV_H_CHROMA_59: 0x00000000
>(II) I810(0):                 SR00: 0x03
>(II) I810(0):                 SR01: 0x00
>(II) I810(0):                 SR02: 0x03
>(II) I810(0):                 SR03: 0x04
>(II) I810(0):                 SR04: 0x02
>(II) I810(0):                 SR05: 0x00
>(II) I810(0):                 SR06: 0x00
>(II) I810(0):                 SR07: 0x00
>(II) I810(0):                  MSR: 0x67
>(II) I810(0):                 CR00: 0x5f
>(II) I810(0):                 CR01: 0x4f
>(II) I810(0):                 CR02: 0x50
>(II) I810(0):                 CR03: 0x82
>(II) I810(0):                 CR04: 0x55
>(II) I810(0):                 CR05: 0x81
>(II) I810(0):                 CR06: 0xbf
>(II) I810(0):                 CR07: 0x1f
>(II) I810(0):                 CR08: 0x00
>(II) I810(0):                 CR09: 0x4f
>(II) I810(0):                 CR0a: 0x1f
>(II) I810(0):                 CR0b: 0x1e
>(II) I810(0):                 CR0c: 0x00
>(II) I810(0):                 CR0d: 0x00
>(II) I810(0):                 CR0e: 0x00
>(II) I810(0):                 CR0f: 0x00
>(II) I810(0):                 CR10: 0x9c
>(II) I810(0):                 CR11: 0x8e
>(II) I810(0):                 CR12: 0x8f
>(II) I810(0):                 CR13: 0x28
>(II) I810(0):                 CR14: 0x1f
>(II) I810(0):                 CR15: 0x96
>(II) I810(0):                 CR16: 0xb9
>(II) I810(0):                 CR17: 0xa3
>(II) I810(0):                 CR18: 0xff
>(II) I810(0):                 CR19: 0x00
>(II) I810(0):                 CR1a: 0x00
>(II) I810(0):                 CR1b: 0x00
>(II) I810(0):                 CR1c: 0x00
>(II) I810(0):                 CR1d: 0x00
>(II) I810(0):                 CR1e: 0x00
>(II) I810(0):                 CR1f: 0x00
>(II) I810(0):                 CR20: 0x00
>(II) I810(0):                 CR21: 0x00
>(II) I810(0):                 CR22: 0x20
>(II) I810(0):                 CR23: 0x00
>(II) I810(0):                 CR24: 0x00
>(EE) I810(0): p1 out of range
>(II) I810(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) I810(0): pipe A dot 208000 n 4 m1 21 m2 13 p1 1 p2 10
>(EE) I810(0): p1 out of range
>(II) I810(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) I810(0): pipe B dot 208000 n 4 m1 21 m2 13 p1 1 p2 10
>(II) I810(0): DumpRegsEnd
>(II) I810(0): Output configuration:
>(II) I810(0):   Pipe A is on
>(II) I810(0):   Display plane A is now enabled and connected to pipe A.
>(II) I810(0):   Pipe B is on
>(II) I810(0):   Display plane B is now enabled and connected to pipe B.
>(II) I810(0):   Output VGA is connected to pipe A
>(II) I810(0):   Output LVDS is connected to pipe B
>(II) I810(0):   Output TMDS is connected to pipe none
>(II) I810(0): [drm] dma control initialized, using IRQ 10
>(II) Mouse0: ps2EnableDataReporting: succeeded

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Attachments on bug 9807: 8540 | 8541 | 9493

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