Attachment 85414 Details for Bug 69081 – KF shaders dump

KF shaders dump

KFshaders.txt (text/plain), 2.33 MB, created by José Suárez on 2013-09-08 02:08:15 UTC

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Creator: José Suárez

Created: 2013-09-08 02:08:15 UTC

Size: 2.33 MB

patch

obsolete

>Running Steam on ubuntu 13.04 64-bit
>STEAM_RUNTIME is enabled automatically
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>[2013-09-08 03:57:27] Startup - updater built Sep  6 2013 12:04:22
>[2013-09-08 03:57:27] Opted in to client beta 'publicbeta' via beta file
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>unlinked 0 orphaned pipes
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>[0908/035727:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation
>[2013-09-08 03:57:27] Verificando instalaciÃ³n...
>[2013-09-08 03:57:27] Verification complete
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %21 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %22 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %23 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8080300
>c8090301
>c80c0200
>c80d0201
>c8100100
>c8110101
>c8140000
>c8150001
>f800180f
>02030405
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  %69 = call float @llvm.AMDIL.clamp.(float %37, float 0,000000e+00, float 0x3FF0000000000000)
>  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0,000000e+00, float 0x3FF0000000000000)
>  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0,000000e+00, float 0x3FF0000000000000)
>  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0,000000e+00, float 0x3FF0000000000000)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %69, float %70, float %71, float %72)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
>  %25 = bitcast i32 %24 to float
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>5e000101
>c8060102
>c80a0002
>5e020302
>f8001c0f
>00010001
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
>  %36 = bitcast i32 %35 to float
>  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
>  %38 = bitcast i32 %37 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
>  %36 = bitcast i32 %35 to float
>  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
>  %38 = bitcast i32 %37 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], CONST[4]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
>  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %33 = fdiv float %30, %32
>  %34 = fdiv float %31, %32
>  %35 = bitcast float %33 to i32
>  %36 = bitcast float %34 to i32
>  %37 = insertelement <2 x i32> undef, i32 %35, i32 0
>  %38 = insertelement <2 x i32> %37, i32 %36, i32 1
>  %39 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %38, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %40 = extractelement <4 x float> %39, i32 0
>  %41 = extractelement <4 x float> %39, i32 1
>  %42 = extractelement <4 x float> %39, i32 2
>  %43 = extractelement <4 x float> %39, i32 3
>  %44 = fmul float %40, %22
>  %45 = fmul float %41, %23
>  %46 = fmul float %42, %24
>  %47 = fmul float %43, %25
>  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %49 = bitcast i32 %48 to float
>  %50 = call i32 @llvm.SI.packf16(float %46, float %47)
>  %51 = bitcast i32 %50 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %49, float %51, float %49, float %51)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0300
>c80d0301
>7e085503
>10060902
>c8140000
>c8150001
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430002
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>10080604
>c2020112
>bf8c007f
>100a0404
>5e080905
>c2020111
>bf8c007f
>100a0204
>c2000110
>bf8c007f
>10000000
>5e000b00
>f8001c0f
>04000400
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>Generating new string page texture 2: 48x256, total string texture memory is 49,15 KB
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %31 = fdiv float %28, %30
>  %32 = fdiv float %29, %30
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, %24
>  %43 = fmul float %39, %25
>  %44 = fmul float %40, %26
>  %45 = fmul float %41, %27
>  %46 = call i32 @llvm.SI.packf16(float %42, float %43)
>  %47 = bitcast i32 %46 to float
>  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %49 = bitcast i32 %48 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>c81c0200
>c81d0201
>100e0f04
>5e0c0d07
>c81c0100
>c81d0101
>100e0f03
>c8200000
>c8210001
>10001102
>5e000f00
>f8001c0f
>06000600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0,000000e+00, float 0x3FF0000000000000)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0,000000e+00, float 0x3FF0000000000000)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0,000000e+00, float 0x3FF0000000000000)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0,000000e+00, float 0x3FF0000000000000)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>Generating new string page texture 3: 384x256, total string texture memory is 442,37 KB
>
>(steam:4381): Gtk-WARNING **: Imposible encontrar el motor de temas en la ruta al _modulo: Â«oxygen-gtkÂ»,
>
>(steam:4381): Gtk-WARNING **: Imposible encontrar el motor de temas en la ruta al _modulo: Â«oxygen-gtkÂ»,
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>`menu_proxy_module_load': /home/jose/.local/share/Steam/ubuntu12_32/steam: undefined symbol: menu_proxy_module_load
>
>(steam:4381): Gtk-WARNING **: Failed to load type module: (null)
>
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Translation has an invalid value 'I-->D' for default text direction.  Defaulting to left-to-right.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>** (steam:4381): WARNING **: replace_settings: error updating connection /org/freedesktop/NetworkManager/Settings/1 settings: (1) type
>roaming config store loaded successfully - 9188 bytes.
>migrating temporary roaming config store
>Adding license for package 0
>Adding license for package 63
>Adding license for package 113
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>Adding license for package 16640
>Adding license for package 16767
>Adding license for package 16805
>Adding license for package 17344
>Adding license for package 17347
>Adding license for package 17433
>Adding license for package 17483
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>Adding license for package 17485
>Adding license for package 17486
>Adding license for package 17487
>Adding license for package 17593
>Adding license for package 17607
>Adding license for package 17642
>Adding license for package 17711
>Adding license for package 17804
>Adding license for package 17840
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>Adding license for package 17915
>Adding license for package 17938
>Adding license for package 17968
>Adding license for package 18017
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>Adding license for package 18344
>Adding license for package 18358
>Adding license for package 18444
>Adding license for package 18531
>Adding license for package 18555
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>Adding license for package 18559
>Adding license for package 18604
>Adding license for package 18616
>Adding license for package 18629
>Adding license for package 18769
>Adding license for package 18876
>Adding license for package 18877
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>Adding license for package 19007
>Adding license for package 19296
>Adding license for package 25597
>Adding license for package 25643
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>Adding license for package 25922
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>Adding license for package 26390
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>Adding license for package 27322
>Adding license for package 27397
>Adding license for package 27535
>Adding license for package 27988
>Adding license for package 27989
>Adding license for package 27990
>Adding license for package 27991
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>Adding license for package 28373
>Adding license for package 28515
>Adding license for package 28770
>Adding license for package 28771
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>Adding license for package 29532
>Adding license for package 29789
>Adding license for package 30170
>Adding license for package 30274
>ExecCommandLine: "/home/jose/.local/share/Steam/ubuntu12_32/steam"
>System startup time: 9,11 seconds
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>Running Steam on ubuntu 13.04 64-bit
>STEAM_RUNTIME has been set by the user to: /home/jose/.local/share/Steam/ubuntu12_32/steam-runtime
>Generating new string page texture 74: 1024x256, total string texture memory is 1,49 MB
>Generating new string page texture 75: 256x256, total string texture memory is 262,14 KB
>Generating new string page texture 76: 256x256, total string texture memory is 1,75 MB
>Generating new string page texture 77: 128x256, total string texture memory is 1,88 MB
>Generating new string page texture 78: 32x256, total string texture memory is 1,92 MB
>Generating new string page texture 79: 64x256, total string texture memory is 1,98 MB
>Generating new string page texture 80: 24x256, total string texture memory is 2,01 MB
>ExecCommandLine: "/home/jose/.steam/root/ubuntu12_32/steam steam://open/driverhelperready"
>ExecSteamURL: "steam://open/driverhelperready"
>Generating new string page texture 88: 256x256, total string texture memory is 2,27 MB
>Generating new string page texture 89: 128x256, total string texture memory is 2,40 MB
>Generating new string page texture 91: 256x256, total string texture memory is 2,66 MB
>CAPIJobRequestUserStats - Server response failed 2
>Generating new string page texture 97: 256x256, total string texture memory is 2,92 MB
>Generating new string page texture 98: 64x256, total string texture memory is 2,99 MB
>Generating new string page texture 99: 128x256, total string texture memory is 3,12 MB
>Generating new string page texture 111: 128x256, total string texture memory is 3,25 MB
>Generating new string page texture 115: 256x256, total string texture memory is 3,51 MB
>Installing breakpad exception handler for appid(steam)/version(1378500910_client)
>Game update: AppID 1250 "Killing Floor", ProcID 4485, IP 0.0.0.0:0
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:4381): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>Setting breakpad minidump AppID = 1250
>Steam_SetMinidumpSteamID:  Caching Steam ID:  76561198042971456 [API loaded no]
>[0908/035754:ERROR:nss_ocsp.cc(588)] No URLRequestContext for OCSP handler.
>[0908/035754:ERROR:nss_ocsp.cc(588)] No URLRequestContext for OCSP handler.
>[0908/035754:ERROR:nss_ocsp.cc(588)] No URLRequestContext for OCSP handler.
>[0908/035754:ERROR:nss_ocsp.cc(588)] No URLRequestContext for OCSP handler.
>[0908/035756:ERROR:nss_ocsp.cc(588)] No URLRequestContext for OCSP handler.
>[0908/035756:ERROR:nss_ocsp.cc(588)] No URLRequestContext for OCSP handler.
>[0908/035756:ERROR:nss_ocsp.cc(588)] No URLRequestContext for OCSP handler.
>[0908/035756:ERROR:nss_ocsp.cc(588)] No URLRequestContext for OCSP handler.
>[0908/035756:ERROR:nss_ocsp.cc(588)] No URLRequestContext for OCSP handler.
>[0908/035756:ERROR:nss_ocsp.cc(588)] No URLRequestContext for OCSP handler.
>[0908/035756:ERROR:nss_ocsp.cc(588)] No URLRequestContext for OCSP handler.
>[0908/035756:ERROR:nss_ocsp.cc(588)] No URLRequestContext for OCSP handler.
>AL lib: sdl.c:228: No OpenAL capture support in the SDL backend at this time.
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %21 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %22 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %23 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8080300
>c8090301
>c80c0200
>c80d0201
>c8100100
>c8110101
>c8140000
>c8150001
>f800180f
>02030405
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  %69 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %69, float %70, float %71, float %72)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
>  %25 = bitcast i32 %24 to float
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>5e000101
>c8060102
>c80a0002
>5e020302
>f8001c0f
>00010001
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
>  %36 = bitcast i32 %35 to float
>  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
>  %38 = bitcast i32 %37 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
>  %36 = bitcast i32 %35 to float
>  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
>  %38 = bitcast i32 %37 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %31 = fdiv float %28, %30
>  %32 = fdiv float %29, %30
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, %24
>  %43 = fmul float %39, %25
>  %44 = fmul float %40, %26
>  %45 = fmul float %41, %27
>  %46 = call i32 @llvm.SI.packf16(float %42, float %43)
>  %47 = bitcast i32 %46 to float
>  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %49 = bitcast i32 %48 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>c81c0200
>c81d0201
>100e0f04
>5e0c0d07
>c81c0100
>c81d0101
>100e0f03
>c8200000
>c8210001
>10001102
>5e000f00
>f8001c0f
>06000600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>Installing breakpad exception handler for appid(gameoverlayui)/version(20130906120449_client)
>Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
>Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  %69 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %69, float %70, float %71, float %72)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MOV OUT[0], TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %27 = fdiv float %24, %26
>  %28 = fdiv float %25, %26
>  %29 = bitcast float %27 to i32
>  %30 = bitcast float %28 to i32
>  %31 = insertelement <2 x i32> undef, i32 %29, i32 0
>  %32 = insertelement <2 x i32> %31, i32 %30, i32 1
>  %33 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %32, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = call i32 @llvm.SI.packf16(float %34, float %35)
>  %39 = bitcast i32 %38 to float
>  %40 = call i32 @llvm.SI.packf16(float %36, float %37)
>  %41 = bitcast i32 %40 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %39, float %41, float %39, float %41)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0300
>c80d0301
>7e085503
>10060902
>c8140000
>c8150001
>10040905
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %31 = fdiv float %28, %30
>  %32 = fdiv float %29, %30
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, %24
>  %43 = fmul float %39, %25
>  %44 = fmul float %40, %26
>  %45 = fmul float %41, %27
>  %46 = call i32 @llvm.SI.packf16(float %42, float %43)
>  %47 = bitcast i32 %46 to float
>  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %49 = bitcast i32 %48 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>c81c0200
>c81d0201
>100e0f04
>5e0c0d07
>c81c0100
>c81d0101
>100e0f03
>c8200000
>c8210001
>10001102
>5e000f00
>f8001c0f
>06000600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>[0908/035759:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>f800180f
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MOV OUT[0], TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %27 = fdiv float %24, %26
>  %28 = fdiv float %25, %26
>  %29 = bitcast float %27 to i32
>  %30 = bitcast float %28 to i32
>  %31 = insertelement <2 x i32> undef, i32 %29, i32 0
>  %32 = insertelement <2 x i32> %31, i32 %30, i32 1
>  %33 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %32, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = fcmp ugt float %37, 0.000000e+00
>  %39 = sext i1 %38 to i32
>  %40 = trunc i32 %39 to i1
>  %41 = select i1 %40, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %41)
>  %42 = call i32 @llvm.SI.packf16(float %34, float %35)
>  %43 = bitcast i32 %42 to float
>  %44 = call i32 @llvm.SI.packf16(float %36, float %37)
>  %45 = bitcast i32 %44 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %43, float %45, float %43, float %45)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0300
>c80d0301
>7e085503
>10060902
>c8140000
>c8150001
>10040905
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>d0080000
>02010103
>d2000004
>0001e4f3
>7c260880
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], CONST[4]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
>  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %33 = fdiv float %30, %32
>  %34 = fdiv float %31, %32
>  %35 = bitcast float %33 to i32
>  %36 = bitcast float %34 to i32
>  %37 = insertelement <2 x i32> undef, i32 %35, i32 0
>  %38 = insertelement <2 x i32> %37, i32 %36, i32 1
>  %39 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %38, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %40 = extractelement <4 x float> %39, i32 0
>  %41 = extractelement <4 x float> %39, i32 1
>  %42 = extractelement <4 x float> %39, i32 2
>  %43 = extractelement <4 x float> %39, i32 3
>  %44 = fmul float %40, %22
>  %45 = fmul float %41, %23
>  %46 = fmul float %42, %24
>  %47 = fmul float %43, %25
>  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %49 = bitcast i32 %48 to float
>  %50 = call i32 @llvm.SI.packf16(float %46, float %47)
>  %51 = bitcast i32 %50 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %49, float %51, float %49, float %51)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0300
>c80d0301
>7e085503
>10060902
>c8140000
>c8150001
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430002
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>10080604
>c2020112
>bf8c007f
>100a0404
>5e080905
>c2020111
>bf8c007f
>100a0204
>c2000110
>bf8c007f
>10000000
>5e000b00
>f8001c0f
>04000400
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MUL TEMP[0], IN[1].xxxx, CONST[4]
>  5: MAD TEMP[0], IN[1].yyyy, CONST[5], TEMP[0]
>  6: MAD TEMP[0], IN[1].zzzz, CONST[6], TEMP[0]
>  7: MAD OUT[1], IN[1].wwww, CONST[7], TEMP[0]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = fmul float %46, %11
>  %58 = fmul float %46, %12
>  %59 = fmul float %46, %13
>  %60 = fmul float %46, %14
>  %61 = fmul float %47, %15
>  %62 = fadd float %61, %57
>  %63 = fmul float %47, %16
>  %64 = fadd float %63, %58
>  %65 = fmul float %47, %17
>  %66 = fadd float %65, %59
>  %67 = fmul float %47, %18
>  %68 = fadd float %67, %60
>  %69 = fmul float %48, %19
>  %70 = fadd float %69, %62
>  %71 = fmul float %48, %20
>  %72 = fadd float %71, %64
>  %73 = fmul float %48, %21
>  %74 = fadd float %73, %66
>  %75 = fmul float %48, %22
>  %76 = fadd float %75, %68
>  %77 = fmul float %49, %23
>  %78 = fadd float %77, %70
>  %79 = fmul float %49, %24
>  %80 = fadd float %79, %72
>  %81 = fmul float %49, %25
>  %82 = fadd float %81, %74
>  %83 = fmul float %49, %26
>  %84 = fadd float %83, %76
>  %85 = fmul float %53, %27
>  %86 = fmul float %53, %28
>  %87 = fmul float %53, %29
>  %88 = fmul float %53, %30
>  %89 = fmul float %54, %31
>  %90 = fadd float %89, %85
>  %91 = fmul float %54, %32
>  %92 = fadd float %91, %86
>  %93 = fmul float %54, %33
>  %94 = fadd float %93, %87
>  %95 = fmul float %54, %34
>  %96 = fadd float %95, %88
>  %97 = fmul float %55, %35
>  %98 = fadd float %97, %90
>  %99 = fmul float %55, %36
>  %100 = fadd float %99, %92
>  %101 = fmul float %55, %37
>  %102 = fadd float %101, %94
>  %103 = fmul float %55, %38
>  %104 = fadd float %103, %96
>  %105 = fmul float %56, %39
>  %106 = fadd float %105, %98
>  %107 = fmul float %56, %40
>  %108 = fadd float %107, %100
>  %109 = fmul float %56, %41
>  %110 = fadd float %109, %102
>  %111 = fmul float %56, %42
>  %112 = fadd float %111, %104
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %106, float %108, float %110, float %112)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %78, float %80, float %82, float %84)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800020f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
>  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
>  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
>  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = extractelement <4 x float> %59, i32 3
>  %64 = fmul float %46, %11
>  %65 = fmul float %46, %12
>  %66 = fmul float %46, %13
>  %67 = fmul float %46, %14
>  %68 = fmul float %47, %15
>  %69 = fadd float %68, %64
>  %70 = fmul float %47, %16
>  %71 = fadd float %70, %65
>  %72 = fmul float %47, %17
>  %73 = fadd float %72, %66
>  %74 = fmul float %47, %18
>  %75 = fadd float %74, %67
>  %76 = fmul float %48, %19
>  %77 = fadd float %76, %69
>  %78 = fmul float %48, %20
>  %79 = fadd float %78, %71
>  %80 = fmul float %48, %21
>  %81 = fadd float %80, %73
>  %82 = fmul float %48, %22
>  %83 = fadd float %82, %75
>  %84 = fmul float %49, %23
>  %85 = fadd float %84, %77
>  %86 = fmul float %49, %24
>  %87 = fadd float %86, %79
>  %88 = fmul float %49, %25
>  %89 = fadd float %88, %81
>  %90 = fmul float %49, %26
>  %91 = fadd float %90, %83
>  %92 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
>  %93 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %94 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
>  %96 = fmul float %60, %27
>  %97 = fmul float %60, %28
>  %98 = fmul float %60, %29
>  %99 = fmul float %60, %30
>  %100 = fmul float %61, %31
>  %101 = fadd float %100, %96
>  %102 = fmul float %61, %32
>  %103 = fadd float %102, %97
>  %104 = fmul float %61, %33
>  %105 = fadd float %104, %98
>  %106 = fmul float %61, %34
>  %107 = fadd float %106, %99
>  %108 = fmul float %62, %35
>  %109 = fadd float %108, %101
>  %110 = fmul float %62, %36
>  %111 = fadd float %110, %103
>  %112 = fmul float %62, %37
>  %113 = fadd float %112, %105
>  %114 = fmul float %62, %38
>  %115 = fadd float %114, %107
>  %116 = fmul float %63, %39
>  %117 = fadd float %116, %109
>  %118 = fmul float %63, %40
>  %119 = fadd float %118, %111
>  %120 = fmul float %63, %41
>  %121 = fadd float %120, %113
>  %122 = fmul float %63, %42
>  %123 = fadd float %122, %115
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %92, float %93, float %94, float %95)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %117, float %119, float %121, float %123)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %85, float %87, float %89, float %91)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800021f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MOV OUT[0], TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %27 = fdiv float %24, %26
>  %28 = fdiv float %25, %26
>  %29 = bitcast float %27 to i32
>  %30 = bitcast float %28 to i32
>  %31 = insertelement <2 x i32> undef, i32 %29, i32 0
>  %32 = insertelement <2 x i32> %31, i32 %30, i32 1
>  %33 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %32, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = call i32 @llvm.SI.packf16(float %34, float %35)
>  %39 = bitcast i32 %38 to float
>  %40 = call i32 @llvm.SI.packf16(float %36, float %37)
>  %41 = bitcast i32 %40 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %39, float %41, float %39, float %41)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0300
>c80d0301
>7e085503
>10060902
>c8140000
>c8150001
>10040905
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], FOG, PERSPECTIVE
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..3]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MOV TEMP[1].w, TEMP[0].wwww
>  4: MAD_SAT TEMP[2].x, IN[0].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  5: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].xxxx
>  6: MUL TEMP[3].xyz, CONST[2].xyzz, TEMP[3].xxxx
>  7: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
>  8: MOV OUT[0], TEMP[1]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %35 = fdiv float %32, %34
>  %36 = fdiv float %33, %34
>  %37 = bitcast float %35 to i32
>  %38 = bitcast float %36 to i32
>  %39 = insertelement <2 x i32> undef, i32 %37, i32 0
>  %40 = insertelement <2 x i32> %39, i32 %38, i32 1
>  %41 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %42 = extractelement <4 x float> %41, i32 0
>  %43 = extractelement <4 x float> %41, i32 1
>  %44 = extractelement <4 x float> %41, i32 2
>  %45 = extractelement <4 x float> %41, i32 3
>  %46 = fmul float %31, %22
>  %47 = fadd float %46, %23
>  %48 = call float @llvm.AMDIL.clamp.(float %47, float 0.000000e+00, float 1.000000e+00)
>  %49 = fsub float -0.000000e+00, %48
>  %50 = fadd float 1.000000e+00, %49
>  %51 = fmul float %24, %50
>  %52 = fmul float %25, %50
>  %53 = fmul float %26, %50
>  %54 = fmul float %42, %48
>  %55 = fadd float %54, %51
>  %56 = fmul float %43, %48
>  %57 = fadd float %56, %52
>  %58 = fmul float %44, %48
>  %59 = fadd float %58, %53
>  %60 = call i32 @llvm.SI.packf16(float %55, float %57)
>  %61 = bitcast i32 %60 to float
>  %62 = call i32 @llvm.SI.packf16(float %59, float %45)
>  %63 = bitcast i32 %62 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %61, float %63, float %61, float %63)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c8180000
>c8190001
>c0800100
>bf8c0070
>c2020104
>c2028105
>bf8c007f
>7e000205
>d2820000
>04000906
>d2060800
>02010100
>080200f2
>c202010a
>bf8c007f
>100c0204
>d2820006
>041a0104
>5e0c0b06
>c2020109
>bf8c007f
>100e0204
>d2820007
>041e0103
>c2000108
>bf8c007f
>10020200
>d2820000
>04060102
>5e000f00
>f8001c0f
>06000600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], FOG
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP4 TEMP[0], IN[0], CONST[6]
>  5: ABS OUT[1].x, TEMP[0]
>  6: MOV OUT[1].yzw, IMM[0].xxxy
>  7: MOV OUT[2], IN[1]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = fmul float %34, %11
>  %46 = fmul float %34, %12
>  %47 = fmul float %34, %13
>  %48 = fmul float %34, %14
>  %49 = fmul float %35, %15
>  %50 = fadd float %49, %45
>  %51 = fmul float %35, %16
>  %52 = fadd float %51, %46
>  %53 = fmul float %35, %17
>  %54 = fadd float %53, %47
>  %55 = fmul float %35, %18
>  %56 = fadd float %55, %48
>  %57 = fmul float %36, %19
>  %58 = fadd float %57, %50
>  %59 = fmul float %36, %20
>  %60 = fadd float %59, %52
>  %61 = fmul float %36, %21
>  %62 = fadd float %61, %54
>  %63 = fmul float %36, %22
>  %64 = fadd float %63, %56
>  %65 = fmul float %37, %23
>  %66 = fadd float %65, %58
>  %67 = fmul float %37, %24
>  %68 = fadd float %67, %60
>  %69 = fmul float %37, %25
>  %70 = fadd float %69, %62
>  %71 = fmul float %37, %26
>  %72 = fadd float %71, %64
>  %73 = fmul float %34, %27
>  %74 = fmul float %35, %28
>  %75 = fadd float %73, %74
>  %76 = fmul float %36, %29
>  %77 = fadd float %75, %76
>  %78 = fmul float %37, %30
>  %79 = fadd float %77, %78
>  %80 = call float @fabs(float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %80, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %41, float %42, float %43, float %44)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %66, float %68, float %70, float %72)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800020f
>06070705
>c0820704
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..3]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: ADD TEMP[1].x, IMM[0].xxxx, -CONST[3].wwww
>  5: MOV TEMP[2].xy, IN[2].xyyy
>  6: MOV TEMP[2].w, IN[2].wwww
>  7: TXP TEMP[2], TEMP[2], SAMP[0], 2D
>  8: MUL TEMP[2], TEMP[2], CONST[3].wwww
>  9: MAD TEMP[0].xyz, TEMP[0], TEMP[1].xxxx, TEMP[2]
> 10: MOV TEMP[0].xyz, TEMP[0].xyzx
> 11: MOV TEMP[0].w, CONST[3].wwww
> 12: MOV OUT[0], TEMP[0]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
>  %23 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %24 = load <32 x i8> addrspace(2)* %23, !tbaa !0
>  %25 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %26 = load <16 x i8> addrspace(2)* %25, !tbaa !0
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %40 = fdiv float %34, %36
>  %41 = fdiv float %35, %36
>  %42 = bitcast float %40 to i32
>  %43 = bitcast float %41 to i32
>  %44 = insertelement <2 x i32> undef, i32 %42, i32 0
>  %45 = insertelement <2 x i32> %44, i32 %43, i32 1
>  %46 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %45, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %47 = extractelement <4 x float> %46, i32 0
>  %48 = extractelement <4 x float> %46, i32 1
>  %49 = extractelement <4 x float> %46, i32 2
>  %50 = fmul float %47, %31
>  %51 = fmul float %48, %32
>  %52 = fmul float %49, %33
>  %53 = fsub float -0.000000e+00, %22
>  %54 = fadd float 1.000000e+00, %53
>  %55 = fdiv float %37, %39
>  %56 = fdiv float %38, %39
>  %57 = bitcast float %55 to i32
>  %58 = bitcast float %56 to i32
>  %59 = insertelement <2 x i32> undef, i32 %57, i32 0
>  %60 = insertelement <2 x i32> %59, i32 %58, i32 1
>  %61 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %60, <32 x i8> %24, <16 x i8> %26, i32 2)
>  %62 = extractelement <4 x float> %61, i32 0
>  %63 = extractelement <4 x float> %61, i32 1
>  %64 = extractelement <4 x float> %61, i32 2
>  %65 = fmul float %62, %22
>  %66 = fmul float %63, %22
>  %67 = fmul float %64, %22
>  %68 = fmul float %50, %54
>  %69 = fadd float %68, %65
>  %70 = fmul float %51, %54
>  %71 = fadd float %70, %66
>  %72 = fmul float %52, %54
>  %73 = fadd float %72, %67
>  %74 = call i32 @llvm.SI.packf16(float %69, float %71)
>  %75 = bitcast i32 %74 to float
>  %76 = call i32 @llvm.SI.packf16(float %73, float %22)
>  %77 = bitcast i32 %76 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %75, float %77, float %75, float %77)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430202
>c0840100
>bf8c0070
>c200090f
>bf8c007f
>100a0600
>c8180500
>c8190501
>c81c0700
>c81d0701
>7e105507
>100e1106
>c8240400
>c8250401
>100c1109
>c0840304
>c0c60508
>bf8c007f
>f0800700
>00430606
>c8240100
>c8250101
>bf8c0770
>10141307
>d2080009
>020000f2
>d2820005
>0416130a
>10140400
>c82c0000
>c82d0001
>10161706
>d282000a
>042a130b
>5e0a0b0a
>10040800
>c80c0200
>c80d0201
>10000708
>d2820000
>040a1300
>d25e0000
>02000100
>f8001c0f
>00050005
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: MOV OUT[3], IN[3]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %5)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = extractelement <4 x float> %50, i32 3
>  %55 = fmul float %30, %11
>  %56 = fmul float %30, %12
>  %57 = fmul float %30, %13
>  %58 = fmul float %30, %14
>  %59 = fmul float %31, %15
>  %60 = fadd float %59, %55
>  %61 = fmul float %31, %16
>  %62 = fadd float %61, %56
>  %63 = fmul float %31, %17
>  %64 = fadd float %63, %57
>  %65 = fmul float %31, %18
>  %66 = fadd float %65, %58
>  %67 = fmul float %32, %19
>  %68 = fadd float %67, %60
>  %69 = fmul float %32, %20
>  %70 = fadd float %69, %62
>  %71 = fmul float %32, %21
>  %72 = fadd float %71, %64
>  %73 = fmul float %32, %22
>  %74 = fadd float %73, %66
>  %75 = fmul float %33, %23
>  %76 = fadd float %75, %68
>  %77 = fmul float %33, %24
>  %78 = fadd float %77, %70
>  %79 = fmul float %33, %25
>  %80 = fadd float %79, %72
>  %81 = fmul float %33, %26
>  %82 = fadd float %81, %74
>  %83 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %84 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %85 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %86 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %83, float %84, float %85, float %86)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %51, float %52, float %53, float %54)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %76, float %78, float %80, float %82)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800022f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %31 = fdiv float %28, %30
>  %32 = fdiv float %29, %30
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, %24
>  %43 = fmul float %39, %25
>  %44 = fmul float %40, %26
>  %45 = fmul float %41, %27
>  %46 = fcmp ugt float %45, 0x3FDFDFDFE0000000
>  %47 = sext i1 %46 to i32
>  %48 = trunc i32 %47 to i1
>  %49 = select i1 %48, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %49)
>  %50 = call i32 @llvm.SI.packf16(float %42, float %43)
>  %51 = bitcast i32 %50 to float
>  %52 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %53 = bitcast i32 %52 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %51, float %53, float %51, float %53)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>7e0e02ff
>3efefeff
>d0080000
>02020f06
>d2000007
>0001e4f3
>7c260e80
>c81c0200
>c81d0201
>100e0f04
>5e0c0d07
>c81c0100
>c81d0101
>100e0f03
>c8200000
>c8210001
>10001102
>5e000f00
>f8001c0f
>06000600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..1], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV TEMP[1].xy, IN[2].xyyy
>  5: MOV TEMP[1].w, IN[2].wwww
>  6: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  7: MUL TEMP[1].xyz, TEMP[1], TEMP[0]
>  8: MOV TEMP[1].xyz, TEMP[1].xyzx
>  9: MOV TEMP[1].w, TEMP[0].wwww
> 10: MOV OUT[0], TEMP[1]
> 11: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %38 = fdiv float %32, %34
>  %39 = fdiv float %33, %34
>  %40 = bitcast float %38 to i32
>  %41 = bitcast float %39 to i32
>  %42 = insertelement <2 x i32> undef, i32 %40, i32 0
>  %43 = insertelement <2 x i32> %42, i32 %41, i32 1
>  %44 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %43, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = extractelement <4 x float> %44, i32 1
>  %47 = extractelement <4 x float> %44, i32 2
>  %48 = extractelement <4 x float> %44, i32 3
>  %49 = fmul float %45, %28
>  %50 = fmul float %46, %29
>  %51 = fmul float %47, %30
>  %52 = fmul float %48, %31
>  %53 = fdiv float %35, %37
>  %54 = fdiv float %36, %37
>  %55 = bitcast float %53 to i32
>  %56 = bitcast float %54 to i32
>  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
>  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
>  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = fmul float %60, %49
>  %64 = fmul float %61, %50
>  %65 = fmul float %62, %51
>  %66 = call i32 @llvm.SI.packf16(float %63, float %64)
>  %67 = bitcast i32 %66 to float
>  %68 = call i32 @llvm.SI.packf16(float %65, float %52)
>  %69 = bitcast i32 %68 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %67, float %69, float %67, float %69)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180100
>c8190101
>bf8c0770
>100c0d03
>c81c0900
>c81d0901
>c8200b00
>c8210b01
>7e125508
>10101307
>c8280800
>c8290801
>100e130a
>c0800300
>c0c40500
>bf8c007f
>f0800700
>00020707
>bf8c0770
>100c0d08
>c8280000
>c8290001
>10141502
>10141507
>5e0c0d0a
>c8280200
>c8290201
>10141504
>100e1509
>c8200300
>c8210301
>10001105
>5e000107
>f8001c0f
>00060006
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..11]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
>  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
>  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
>  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
>  9: MUL TEMP[0], IN[3].xxxx, CONST[8]
> 10: MAD TEMP[0], IN[3].yyyy, CONST[9], TEMP[0]
> 11: MAD TEMP[0], IN[3].zzzz, CONST[10], TEMP[0]
> 12: MAD OUT[3], IN[3].wwww, CONST[11], TEMP[0]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %59 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
>  %61 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %60, i32 0, i32 %5)
>  %62 = extractelement <4 x float> %61, i32 0
>  %63 = extractelement <4 x float> %61, i32 1
>  %64 = extractelement <4 x float> %61, i32 2
>  %65 = extractelement <4 x float> %61, i32 3
>  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
>  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
>  %69 = extractelement <4 x float> %68, i32 0
>  %70 = extractelement <4 x float> %68, i32 1
>  %71 = extractelement <4 x float> %68, i32 2
>  %72 = extractelement <4 x float> %68, i32 3
>  %73 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %74 = load <16 x i8> addrspace(2)* %73, !tbaa !0
>  %75 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %74, i32 0, i32 %5)
>  %76 = extractelement <4 x float> %75, i32 0
>  %77 = extractelement <4 x float> %75, i32 1
>  %78 = extractelement <4 x float> %75, i32 2
>  %79 = extractelement <4 x float> %75, i32 3
>  %80 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %81 = load <16 x i8> addrspace(2)* %80, !tbaa !0
>  %82 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %81, i32 0, i32 %5)
>  %83 = extractelement <4 x float> %82, i32 0
>  %84 = extractelement <4 x float> %82, i32 1
>  %85 = extractelement <4 x float> %82, i32 2
>  %86 = extractelement <4 x float> %82, i32 3
>  %87 = fmul float %62, %11
>  %88 = fmul float %62, %12
>  %89 = fmul float %62, %13
>  %90 = fmul float %62, %14
>  %91 = fmul float %63, %15
>  %92 = fadd float %91, %87
>  %93 = fmul float %63, %16
>  %94 = fadd float %93, %88
>  %95 = fmul float %63, %17
>  %96 = fadd float %95, %89
>  %97 = fmul float %63, %18
>  %98 = fadd float %97, %90
>  %99 = fmul float %64, %19
>  %100 = fadd float %99, %92
>  %101 = fmul float %64, %20
>  %102 = fadd float %101, %94
>  %103 = fmul float %64, %21
>  %104 = fadd float %103, %96
>  %105 = fmul float %64, %22
>  %106 = fadd float %105, %98
>  %107 = fmul float %65, %23
>  %108 = fadd float %107, %100
>  %109 = fmul float %65, %24
>  %110 = fadd float %109, %102
>  %111 = fmul float %65, %25
>  %112 = fadd float %111, %104
>  %113 = fmul float %65, %26
>  %114 = fadd float %113, %106
>  %115 = call float @llvm.AMDIL.clamp.(float %69, float 0.000000e+00, float 1.000000e+00)
>  %116 = call float @llvm.AMDIL.clamp.(float %70, float 0.000000e+00, float 1.000000e+00)
>  %117 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %118 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
>  %119 = fmul float %76, %27
>  %120 = fmul float %76, %28
>  %121 = fmul float %76, %29
>  %122 = fmul float %76, %30
>  %123 = fmul float %77, %31
>  %124 = fadd float %123, %119
>  %125 = fmul float %77, %32
>  %126 = fadd float %125, %120
>  %127 = fmul float %77, %33
>  %128 = fadd float %127, %121
>  %129 = fmul float %77, %34
>  %130 = fadd float %129, %122
>  %131 = fmul float %78, %35
>  %132 = fadd float %131, %124
>  %133 = fmul float %78, %36
>  %134 = fadd float %133, %126
>  %135 = fmul float %78, %37
>  %136 = fadd float %135, %128
>  %137 = fmul float %78, %38
>  %138 = fadd float %137, %130
>  %139 = fmul float %79, %39
>  %140 = fadd float %139, %132
>  %141 = fmul float %79, %40
>  %142 = fadd float %141, %134
>  %143 = fmul float %79, %41
>  %144 = fadd float %143, %136
>  %145 = fmul float %79, %42
>  %146 = fadd float %145, %138
>  %147 = fmul float %83, %43
>  %148 = fmul float %83, %44
>  %149 = fmul float %83, %45
>  %150 = fmul float %83, %46
>  %151 = fmul float %84, %47
>  %152 = fadd float %151, %147
>  %153 = fmul float %84, %48
>  %154 = fadd float %153, %148
>  %155 = fmul float %84, %49
>  %156 = fadd float %155, %149
>  %157 = fmul float %84, %50
>  %158 = fadd float %157, %150
>  %159 = fmul float %85, %51
>  %160 = fadd float %159, %152
>  %161 = fmul float %85, %52
>  %162 = fadd float %161, %154
>  %163 = fmul float %85, %53
>  %164 = fadd float %163, %156
>  %165 = fmul float %85, %54
>  %166 = fadd float %165, %158
>  %167 = fmul float %86, %55
>  %168 = fadd float %167, %160
>  %169 = fmul float %86, %56
>  %170 = fadd float %169, %162
>  %171 = fmul float %86, %57
>  %172 = fadd float %171, %164
>  %173 = fmul float %86, %58
>  %174 = fadd float %173, %166
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %115, float %116, float %117, float %118)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %140, float %142, float %144, float %146)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %168, float %170, float %172, float %174)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %108, float %110, float %112, float %114)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800021f
>05060701
>c084070c
>bf8c000f
>e00c2000
>80020100
>c2020123
>bf8c0070
>100a0204
>c2020127
>bf8c007f
>d2820005
>04140902
>c202012b
>bf8c007f
>d2820005
>04140903
>c202012f
>bf8c007f
>d2820005
>04140904
>c2020122
>bf8c007f
>100c0204
>c2020126
>bf8c007f
>d2820006
>04180902
>c202012a
>bf8c007f
>d2820006
>04180903
>c202012e
>bf8c007f
>d2820006
>04180904
>c2020121
>bf8c007f
>100e0204
>c2020125
>bf8c007f
>d2820007
>041c0902
>c2020129
>bf8c007f
>d2820007
>041c0903
>c202012d
>bf8c007f
>d2820007
>041c0904
>c2020120
>bf8c007f
>10100204
>c2020124
>bf8c007f
>d2820008
>04200902
>c2020128
>bf8c007f
>d2820008
>04200903
>c202012c
>bf8c007f
>d2820001
>04200904
>f800022f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %31 = fdiv float %28, %30
>  %32 = fdiv float %29, %30
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, %24
>  %43 = fmul float %39, %25
>  %44 = fmul float %40, %26
>  %45 = fmul float %41, %27
>  %46 = fcmp ugt float %45, 0.000000e+00
>  %47 = sext i1 %46 to i32
>  %48 = trunc i32 %47 to i1
>  %49 = select i1 %48, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %49)
>  %50 = call i32 @llvm.SI.packf16(float %42, float %43)
>  %51 = bitcast i32 %50 to float
>  %52 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %53 = bitcast i32 %52 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %51, float %53, float %51, float %53)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>d0080000
>02010106
>d2000007
>0001e4f3
>7c260e80
>c81c0200
>c81d0201
>100e0f04
>5e0c0d07
>c81c0100
>c81d0101
>100e0f03
>c8200000
>c8210001
>10001102
>5e000f00
>f8001c0f
>06000600
>bf810000
>Installing breakpad exception handler for appid(killingfloor-bin)/version(1.0_client)
>Installing breakpad exception handler for appid(killingfloor-bin)/version(1.0_client)
>Installing breakpad exception handler for appid(killingfloor-bin)/version(1.0_client)
>Defaulting to false
>Defaulting to false
>Installing breakpad exception handler for appid(killingfloor-bin)/version(1.0_client)
>Game update: AppID 1250 "Killing Floor", ProcID 4486, IP 79.156.97.242:7707
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  %69 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %69, float %70, float %71, float %72)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  5: MOV OUT[0], TEMP[0]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %31 = fdiv float %28, %30
>  %32 = fdiv float %29, %30
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, %24
>  %43 = fmul float %39, %25
>  %44 = fmul float %40, %26
>  %45 = fmul float %41, %27
>  %46 = fmul float %42, 2.000000e+00
>  %47 = fmul float %43, 2.000000e+00
>  %48 = fmul float %44, 2.000000e+00
>  %49 = fmul float %45, 1.000000e+00
>  %50 = call float @llvm.AMDIL.clamp.(float %46, float 0.000000e+00, float 1.000000e+00)
>  %51 = call float @llvm.AMDIL.clamp.(float %47, float 0.000000e+00, float 1.000000e+00)
>  %52 = call float @llvm.AMDIL.clamp.(float %48, float 0.000000e+00, float 1.000000e+00)
>  %53 = call float @llvm.AMDIL.clamp.(float %49, float 0.000000e+00, float 1.000000e+00)
>  %54 = call i32 @llvm.SI.packf16(float %50, float %51)
>  %55 = bitcast i32 %54 to float
>  %56 = call i32 @llvm.SI.packf16(float %52, float %53)
>  %57 = bitcast i32 %56 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %55, float %57, float %55, float %57)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020202
>c8180100
>c8190101
>bf8c0770
>100e0d03
>d2820006
>041e0d03
>d2060806
>02010106
>c81c0000
>c81d0001
>10100f02
>d2820007
>04220f02
>d2060807
>02010107
>5e0c0d07
>c81c0200
>c81d0201
>10100f04
>d2820007
>04220f04
>d2060807
>02010107
>c8200300
>c8210301
>10001105
>d2060800
>02010100
>5e000107
>f8001c0f
>00060006
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..10]
>DCL TEMP[0..3]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MOV OUT[2], IN[3]
> 15: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %57 = load <16 x i8> addrspace(2)* %56, !tbaa !0
>  %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %57, i32 0, i32 %5)
>  %59 = extractelement <4 x float> %58, i32 0
>  %60 = extractelement <4 x float> %58, i32 1
>  %61 = extractelement <4 x float> %58, i32 2
>  %62 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %63 = load <16 x i8> addrspace(2)* %62, !tbaa !0
>  %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %63, i32 0, i32 %5)
>  %65 = extractelement <4 x float> %64, i32 0
>  %66 = extractelement <4 x float> %64, i32 1
>  %67 = extractelement <4 x float> %64, i32 2
>  %68 = extractelement <4 x float> %64, i32 3
>  %69 = fmul float %46, %11
>  %70 = fmul float %46, %12
>  %71 = fmul float %46, %13
>  %72 = fmul float %46, %14
>  %73 = fmul float %47, %15
>  %74 = fadd float %73, %69
>  %75 = fmul float %47, %16
>  %76 = fadd float %75, %70
>  %77 = fmul float %47, %17
>  %78 = fadd float %77, %71
>  %79 = fmul float %47, %18
>  %80 = fadd float %79, %72
>  %81 = fmul float %48, %19
>  %82 = fadd float %81, %74
>  %83 = fmul float %48, %20
>  %84 = fadd float %83, %76
>  %85 = fmul float %48, %21
>  %86 = fadd float %85, %78
>  %87 = fmul float %48, %22
>  %88 = fadd float %87, %80
>  %89 = fmul float %49, %23
>  %90 = fadd float %89, %82
>  %91 = fmul float %49, %24
>  %92 = fadd float %91, %84
>  %93 = fmul float %49, %25
>  %94 = fadd float %93, %86
>  %95 = fmul float %49, %26
>  %96 = fadd float %95, %88
>  %97 = fmul float %53, %27
>  %98 = fmul float %54, %28
>  %99 = fadd float %98, %97
>  %100 = fmul float %55, %29
>  %101 = fadd float %99, %100
>  %102 = fmul float %53, %30
>  %103 = fmul float %54, %31
>  %104 = fadd float %103, %102
>  %105 = fmul float %55, %32
>  %106 = fadd float %104, %105
>  %107 = fmul float %53, %33
>  %108 = fmul float %54, %34
>  %109 = fadd float %108, %107
>  %110 = fmul float %55, %35
>  %111 = fadd float %109, %110
>  %112 = fmul float %101, %101
>  %113 = fmul float %106, %106
>  %114 = fadd float %113, %112
>  %115 = fmul float %111, %111
>  %116 = fadd float %114, %115
>  %117 = call float @fabs(float %116)
>  %118 = call float @llvm.AMDGPU.rsq(float %117)
>  %119 = fmul float %36, %39
>  %120 = fadd float %119, %59
>  %121 = fmul float %37, %40
>  %122 = fadd float %121, %60
>  %123 = fmul float %38, %41
>  %124 = fadd float %123, %61
>  %125 = call float @llvm.AMDIL.clamp.(float %120, float 0.000000e+00, float 1.000000e+00)
>  %126 = call float @llvm.AMDIL.clamp.(float %122, float 0.000000e+00, float 1.000000e+00)
>  %127 = call float @llvm.AMDIL.clamp.(float %124, float 0.000000e+00, float 1.000000e+00)
>  %128 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %125, float %126, float %127, float %128)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %65, float %66, float %67, float %68)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %90, float %92, float %94, float %96)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..19]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: MOV OUT[2], IN[3]
> 41: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = extractelement <4 x float> %73, i32 3
>  %78 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %79 = load <16 x i8> addrspace(2)* %78, !tbaa !0
>  %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %79, i32 0, i32 %5)
>  %81 = extractelement <4 x float> %80, i32 0
>  %82 = extractelement <4 x float> %80, i32 1
>  %83 = extractelement <4 x float> %80, i32 2
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = extractelement <4 x float> %92, i32 3
>  %97 = fmul float %74, %11
>  %98 = fmul float %74, %12
>  %99 = fmul float %74, %13
>  %100 = fmul float %74, %14
>  %101 = fmul float %75, %15
>  %102 = fadd float %101, %97
>  %103 = fmul float %75, %16
>  %104 = fadd float %103, %98
>  %105 = fmul float %75, %17
>  %106 = fadd float %105, %99
>  %107 = fmul float %75, %18
>  %108 = fadd float %107, %100
>  %109 = fmul float %76, %19
>  %110 = fadd float %109, %102
>  %111 = fmul float %76, %20
>  %112 = fadd float %111, %104
>  %113 = fmul float %76, %21
>  %114 = fadd float %113, %106
>  %115 = fmul float %76, %22
>  %116 = fadd float %115, %108
>  %117 = fmul float %77, %23
>  %118 = fadd float %117, %110
>  %119 = fmul float %77, %24
>  %120 = fadd float %119, %112
>  %121 = fmul float %77, %25
>  %122 = fadd float %121, %114
>  %123 = fmul float %77, %26
>  %124 = fadd float %123, %116
>  %125 = fmul float %81, %27
>  %126 = fmul float %82, %28
>  %127 = fadd float %126, %125
>  %128 = fmul float %83, %29
>  %129 = fadd float %127, %128
>  %130 = fmul float %81, %30
>  %131 = fmul float %82, %31
>  %132 = fadd float %131, %130
>  %133 = fmul float %83, %32
>  %134 = fadd float %132, %133
>  %135 = fmul float %81, %33
>  %136 = fmul float %82, %34
>  %137 = fadd float %136, %135
>  %138 = fmul float %83, %35
>  %139 = fadd float %137, %138
>  %140 = fmul float %129, %129
>  %141 = fmul float %134, %134
>  %142 = fadd float %141, %140
>  %143 = fmul float %139, %139
>  %144 = fadd float %142, %143
>  %145 = call float @fabs(float %144)
>  %146 = call float @llvm.AMDGPU.rsq(float %145)
>  %147 = fmul float %129, %146
>  %148 = fmul float %134, %146
>  %149 = fmul float %139, %146
>  %150 = fmul float %37, %40
>  %151 = fadd float %150, %87
>  %152 = fmul float %38, %41
>  %153 = fadd float %152, %88
>  %154 = fmul float %39, %42
>  %155 = fadd float %154, %89
>  %156 = call float @llvm.AMDIL.clamp.(float %151, float 0.000000e+00, float 1.000000e+00)
>  %157 = call float @llvm.AMDIL.clamp.(float %153, float 0.000000e+00, float 1.000000e+00)
>  %158 = call float @llvm.AMDIL.clamp.(float %155, float 0.000000e+00, float 1.000000e+00)
>  %159 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %160 = fmul float %74, %47
>  %161 = fmul float %74, %48
>  %162 = fmul float %74, %49
>  %163 = fmul float %75, %50
>  %164 = fadd float %163, %160
>  %165 = fmul float %75, %51
>  %166 = fadd float %165, %161
>  %167 = fmul float %75, %52
>  %168 = fadd float %167, %162
>  %169 = fmul float %76, %53
>  %170 = fadd float %169, %164
>  %171 = fmul float %76, %54
>  %172 = fadd float %171, %166
>  %173 = fmul float %76, %55
>  %174 = fadd float %173, %168
>  %175 = fmul float %77, %56
>  %176 = fadd float %175, %170
>  %177 = fmul float %77, %57
>  %178 = fadd float %177, %172
>  %179 = fmul float %77, %58
>  %180 = fadd float %179, %174
>  %181 = fsub float %44, %176
>  %182 = fsub float %45, %178
>  %183 = fsub float %46, %180
>  %184 = fmul float %181, %181
>  %185 = fmul float %182, %182
>  %186 = fadd float %185, %184
>  %187 = fmul float %183, %183
>  %188 = fadd float %186, %187
>  %189 = call float @fabs(float %188)
>  %190 = call float @llvm.AMDGPU.rsq(float %189)
>  %191 = fmul float %181, %190
>  %192 = fmul float %182, %190
>  %193 = fmul float %183, %190
>  %194 = fdiv float 1.000000e+00, %190
>  %195 = fmul float %190, %194
>  %196 = fmul float %194, %194
>  %197 = fmul float %59, %195
>  %198 = fmul float %60, %194
>  %199 = fadd float %198, %197
>  %200 = fmul float %61, %196
>  %201 = fadd float %199, %200
>  %202 = fdiv float 1.000000e+00, %201
>  %203 = fmul float %176, %176
>  %204 = fmul float %178, %178
>  %205 = fadd float %204, %203
>  %206 = fmul float %180, %180
>  %207 = fadd float %205, %206
>  %208 = call float @fabs(float %207)
>  %209 = call float @llvm.AMDGPU.rsq(float %208)
>  %210 = fmul float %176, %209
>  %211 = fmul float %178, %209
>  %212 = fmul float %180, %209
>  %213 = fsub float %191, %210
>  %214 = fsub float %192, %211
>  %215 = fsub float %193, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fmul float %147, %191
>  %227 = fmul float %148, %192
>  %228 = fadd float %227, %226
>  %229 = fmul float %149, %193
>  %230 = fadd float %228, %229
>  %231 = fmul float %147, %223
>  %232 = fmul float %148, %224
>  %233 = fadd float %232, %231
>  %234 = fmul float %149, %225
>  %235 = fadd float %233, %234
>  %236 = fcmp uge float %230, 0.000000e+00
>  %237 = select i1 %236, float %230, float 0.000000e+00
>  %238 = fcmp uge float %235, 0.000000e+00
>  %239 = select i1 %238, float %235, float 0.000000e+00
>  %240 = call float @llvm.pow.f32(float %239, float %36)
>  %241 = call float @llvm.AMDGPU.cndlt(float %230, float 0.000000e+00, float %240)
>  %242 = fmul float 1.000000e+00, %202
>  %243 = fmul float %237, %202
>  %244 = fmul float %241, %202
>  %245 = fmul float %242, %62
>  %246 = fadd float %245, %151
>  %247 = fmul float %242, %63
>  %248 = fadd float %247, %153
>  %249 = fmul float %242, %64
>  %250 = fadd float %249, %155
>  %251 = fmul float %243, %65
>  %252 = fadd float %251, %246
>  %253 = fmul float %243, %66
>  %254 = fadd float %253, %248
>  %255 = fmul float %243, %67
>  %256 = fadd float %255, %250
>  %257 = fmul float %244, %68
>  %258 = fadd float %257, %252
>  %259 = fmul float %244, %69
>  %260 = fadd float %259, %254
>  %261 = fmul float %244, %70
>  %262 = fadd float %261, %256
>  %263 = call float @llvm.AMDIL.clamp.(float %258, float 0.000000e+00, float 1.000000e+00)
>  %264 = call float @llvm.AMDIL.clamp.(float %260, float 0.000000e+00, float 1.000000e+00)
>  %265 = call float @llvm.AMDIL.clamp.(float %262, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %263, float %264, float %265, float %159)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %93, float %94, float %95, float %96)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %118, float %120, float %122, float %124)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820005
>04140904
>c2020130
>bf8c007f
>100c0204
>c2020134
>bf8c007f
>d2820006
>04180902
>c2020138
>bf8c007f
>d2820006
>04180903
>c202013c
>bf8c007f
>d2820007
>04180904
>100c0f07
>d2820006
>041a0b05
>c2020132
>bf8c007f
>10100204
>c2020136
>bf8c007f
>d2820008
>04200902
>c202013a
>bf8c007f
>d2820008
>04200903
>c202013e
>bf8c007f
>d2820008
>04200904
>d2820006
>041a1108
>d2060106
>02010106
>7e125b06
>10141305
>c202012d
>bf8c007f
>080c0a04
>c202012c
>bf8c007f
>081a0e04
>100a1b0d
>d2820005
>04160d06
>c202012e
>bf8c007f
>08161004
>d2820005
>0416170b
>d2060105
>02010105
>7e0a5b05
>100c0b06
>08181506
>10141307
>100e0b0d
>081a1507
>10141b0d
>d282000a
>042a190c
>10121308
>10100b0b
>08121308
>d282000a
>042a1309
>d206010a
>0201010a
>7e145b0a
>1016150c
>1018150d
>c0840704
>bf8c007f
>e00c2000
>80020d00
>c2020114
>bf8c0070
>10221a04
>c2020115
>bf8c007f
>d2820011
>0444090e
>c2020116
>bf8c007f
>d2820011
>0444090f
>c2020110
>bf8c007f
>10241a04
>c2020111
>bf8c007f
>d2820012
>0448090e
>c2020112
>bf8c007f
>d2820012
>0448090f
>10262512
>d2820013
>044e2311
>c2020118
>bf8c007f
>10281a04
>c2020119
>bf8c007f
>d2820014
>0450090e
>c202011a
>bf8c007f
>d282000e
>0450090f
>d282000d
>044e1d0e
>d206010d
>0201010d
>7e1e5b0d
>101a1f12
>1020190d
>10181f11
>d282000b
>0442170c
>10141509
>10121f0e
>d282000a
>042e1509
>d00c0004
>0201010a
>d200000a
>00121480
>7e144f0a
>c202011c
>bf8c007f
>0e141404
>7e144b0a
>100e0f0d
>d2820006
>041e0d0c
>d2820007
>041a1109
>d0080004
>02020e80
>d2000008
>0011010a
>7e0c5505
>100a0d05
>c2020140
>bf8c007f
>100a0a04
>c2020141
>bf8c007f
>d2820005
>04160c04
>100c0d06
>c2020142
>bf8c007f
>d2820005
>04160c04
>7e0c5505
>100a0d08
>d00c0004
>02010107
>d2000007
>00120e80
>100e0d07
>c0840708
>bf8c007f
>e00c2000
>80020800
>c2020122
>c2028126
>bf8c0070
>7e180205
>d282000c
>042a1804
>c2020146
>bf8c007f
>d282000c
>04300906
>c202014a
>bf8c007f
>d282000c
>04300907
>c202014e
>bf8c007f
>d282000c
>04300905
>d206080c
>0201010c
>c2020121
>c2028125
>bf8c007f
>7e1a0205
>d282000d
>04261a04
>c2020145
>bf8c007f
>d282000d
>04340906
>c2020149
>bf8c007f
>d282000d
>04340907
>c202014d
>bf8c007f
>d282000d
>04340905
>d206080d
>0201010d
>c2020120
>c2028124
>bf8c007f
>7e1c0205
>d2820008
>04221c04
>c2020144
>bf8c007f
>d2820006
>04200906
>c2020148
>bf8c007f
>d2820006
>04180907
>c202014c
>bf8c007f
>d2820005
>04180905
>d2060805
>02010105
>c202012b
>bf8c007f
>d2060806
>02010004
>f800020f
>060c0d05
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL IN[1], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MOV TEMP[1].xy, IN[1].xyyy
>  4: MOV TEMP[1].w, IN[1].wwww
>  5: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  6: MUL TEMP[1].xyz, TEMP[1], TEMP[0]
>  7: MOV TEMP[1].xyz, TEMP[1].xyzx
>  8: MOV TEMP[1].w, TEMP[0].wwww
>  9: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
> 10: MOV OUT[0], TEMP[0]
> 11: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %34 = fdiv float %28, %30
>  %35 = fdiv float %29, %30
>  %36 = bitcast float %34 to i32
>  %37 = bitcast float %35 to i32
>  %38 = insertelement <2 x i32> undef, i32 %36, i32 0
>  %39 = insertelement <2 x i32> %38, i32 %37, i32 1
>  %40 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %39, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = fdiv float %31, %33
>  %46 = fdiv float %32, %33
>  %47 = bitcast float %45 to i32
>  %48 = bitcast float %46 to i32
>  %49 = insertelement <2 x i32> undef, i32 %47, i32 0
>  %50 = insertelement <2 x i32> %49, i32 %48, i32 1
>  %51 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %50, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %52 = extractelement <4 x float> %51, i32 0
>  %53 = extractelement <4 x float> %51, i32 1
>  %54 = extractelement <4 x float> %51, i32 2
>  %55 = fmul float %52, %41
>  %56 = fmul float %53, %42
>  %57 = fmul float %54, %43
>  %58 = fmul float %55, 2.000000e+00
>  %59 = fmul float %56, 2.000000e+00
>  %60 = fmul float %57, 2.000000e+00
>  %61 = fmul float %44, 1.000000e+00
>  %62 = call float @llvm.AMDIL.clamp.(float %58, float 0.000000e+00, float 1.000000e+00)
>  %63 = call float @llvm.AMDIL.clamp.(float %59, float 0.000000e+00, float 1.000000e+00)
>  %64 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %65 = call float @llvm.AMDIL.clamp.(float %61, float 0.000000e+00, float 1.000000e+00)
>  %66 = call i32 @llvm.SI.packf16(float %62, float %63)
>  %67 = bitcast i32 %66 to float
>  %68 = call i32 @llvm.SI.packf16(float %64, float %65)
>  %69 = bitcast i32 %68 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %67, float %69, float %67, float %69)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0300
>c80d0301
>7e085503
>10060902
>c8140000
>c8150001
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180500
>c8190501
>c81c0700
>c81d0701
>7e105507
>100e1106
>c8240400
>c8250401
>100c1109
>c0800300
>c0c20500
>bf8c0070
>f0800700
>00010606
>bf8c0770
>10000707
>d2820000
>04020707
>d2060800
>02010100
>10020506
>d2820001
>04060506
>d2060801
>02010101
>5e000101
>10020908
>d2820001
>04060908
>d2060801
>02010101
>d2060802
>02010105
>5e020501
>f8001c0f
>01000100
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL OUT[2], GENERIC[1]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV TEMP[1].xy, IN[2].xyyy
>  5: MOV TEMP[1].w, IN[2].wwww
>  6: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  7: MUL_SAT TEMP[2], TEMP[0], IMM[0].xxxy
>  8: MUL TEMP[1].xyz, TEMP[1], TEMP[2]
>  9: MOV TEMP[1].xyz, TEMP[1].xyzx
> 10: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
> 11: MOV TEMP[1].w, TEMP[0].wwww
> 12: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
> 13: MOV OUT[0], TEMP[0]
> 14: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %38 = fdiv float %32, %34
>  %39 = fdiv float %33, %34
>  %40 = bitcast float %38 to i32
>  %41 = bitcast float %39 to i32
>  %42 = insertelement <2 x i32> undef, i32 %40, i32 0
>  %43 = insertelement <2 x i32> %42, i32 %41, i32 1
>  %44 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %43, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = extractelement <4 x float> %44, i32 1
>  %47 = extractelement <4 x float> %44, i32 2
>  %48 = extractelement <4 x float> %44, i32 3
>  %49 = fmul float %45, %28
>  %50 = fmul float %46, %29
>  %51 = fmul float %47, %30
>  %52 = fmul float %48, %31
>  %53 = fdiv float %35, %37
>  %54 = fdiv float %36, %37
>  %55 = bitcast float %53 to i32
>  %56 = bitcast float %54 to i32
>  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
>  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
>  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = fmul float %49, 2.000000e+00
>  %64 = fmul float %50, 2.000000e+00
>  %65 = fmul float %51, 2.000000e+00
>  %66 = fmul float %52, 1.000000e+00
>  %67 = call float @llvm.AMDIL.clamp.(float %63, float 0.000000e+00, float 1.000000e+00)
>  %68 = call float @llvm.AMDIL.clamp.(float %64, float 0.000000e+00, float 1.000000e+00)
>  %69 = call float @llvm.AMDIL.clamp.(float %65, float 0.000000e+00, float 1.000000e+00)
>  %70 = call float @llvm.AMDIL.clamp.(float %66, float 0.000000e+00, float 1.000000e+00)
>  %71 = fmul float %60, %67
>  %72 = fmul float %61, %68
>  %73 = fmul float %62, %69
>  %74 = fmul float %49, 2.000000e+00
>  %75 = fmul float %50, 2.000000e+00
>  %76 = fmul float %51, 2.000000e+00
>  %77 = fmul float %52, 1.000000e+00
>  %78 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %75, float 0.000000e+00, float 1.000000e+00)
>  %80 = call float @llvm.AMDIL.clamp.(float %76, float 0.000000e+00, float 1.000000e+00)
>  %81 = call float @llvm.AMDIL.clamp.(float %77, float 0.000000e+00, float 1.000000e+00)
>  %82 = fmul float %71, 2.000000e+00
>  %83 = fmul float %72, 2.000000e+00
>  %84 = fmul float %73, 2.000000e+00
>  %85 = fmul float %81, 1.000000e+00
>  %86 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %87 = call float @llvm.AMDIL.clamp.(float %83, float 0.000000e+00, float 1.000000e+00)
>  %88 = call float @llvm.AMDIL.clamp.(float %84, float 0.000000e+00, float 1.000000e+00)
>  %89 = call float @llvm.AMDIL.clamp.(float %85, float 0.000000e+00, float 1.000000e+00)
>  %90 = call i32 @llvm.SI.packf16(float %86, float %87)
>  %91 = bitcast i32 %90 to float
>  %92 = call i32 @llvm.SI.packf16(float %88, float %89)
>  %93 = bitcast i32 %92 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %91, float %93, float %91, float %93)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180100
>c8190101
>bf8c0770
>100e0d03
>d2820006
>041e0d03
>d2060809
>02010106
>c8180900
>c8190901
>c81c0b00
>c81d0b01
>7e105507
>100e1106
>c8280800
>c8290801
>100c110a
>c0800300
>c0c40500
>bf8c007f
>f0800700
>00020606
>bf8c0770
>10141307
>d2820009
>042a1307
>d2060809
>02010109
>c8280000
>c8290001
>10161502
>d282000a
>042e1502
>d206080a
>0201010a
>10161506
>d282000a
>042e1506
>d206080a
>0201010a
>5e12130a
>c8280200
>c8290201
>10161504
>d282000a
>042e1504
>d206080a
>0201010a
>10161508
>d2820006
>042e1508
>d2060806
>02010106
>c81c0300
>c81d0301
>10000f05
>d2060800
>02010100
>d2060800
>02010100
>5e000106
>f8001c0f
>00090009
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..33]
>DCL TEMP[0..10]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD TEMP[3], TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: SUB TEMP[5], CONST[28], TEMP[4]
> 78: DP3 TEMP[7], TEMP[5], TEMP[5]
> 79: RSQ TEMP[7], |TEMP[7]|
> 80: MUL TEMP[5], TEMP[5], TEMP[7]
> 81: DP3 TEMP[8], -TEMP[5], CONST[30]
> 82: SLT TEMP[9], CONST[30].wwww, TEMP[8]
> 83: POW TEMP[8], TEMP[8], CONST[29].wwww
> 84: MUL TEMP[10], TEMP[9], TEMP[8]
> 85: RCP TEMP[7].yz, TEMP[7]
> 86: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 87: DP3 TEMP[7], CONST[29], TEMP[7]
> 88: RCP TEMP[7], TEMP[7]
> 89: MUL TEMP[10], TEMP[7], TEMP[10]
> 90: SUB TEMP[7], TEMP[5], TEMP[6]
> 91: DP3 TEMP[8].x, TEMP[7], TEMP[7]
> 92: RSQ TEMP[8].x, |TEMP[8]|
> 93: MUL TEMP[7], TEMP[7], TEMP[8].xxxx
> 94: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 95: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 96: LIT TEMP[1], TEMP[2]
> 97: MUL TEMP[1], TEMP[1], TEMP[10]
> 98: MAD TEMP[3], TEMP[1].xxxx, CONST[31], TEMP[3]
> 99: MAD TEMP[3], TEMP[1].yyyy, CONST[32], TEMP[3]
>100: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[33], TEMP[3]
>101: MOV OUT[2], IN[2]
>102: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 476)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 492)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %113 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %115 = call float @llvm.SI.load.const(<16 x i8> %10, i32 528)
>  %116 = call float @llvm.SI.load.const(<16 x i8> %10, i32 532)
>  %117 = call float @llvm.SI.load.const(<16 x i8> %10, i32 536)
>  %118 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %119 = load <16 x i8> addrspace(2)* %118, !tbaa !0
>  %120 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %119, i32 0, i32 %5)
>  %121 = extractelement <4 x float> %120, i32 0
>  %122 = extractelement <4 x float> %120, i32 1
>  %123 = extractelement <4 x float> %120, i32 2
>  %124 = extractelement <4 x float> %120, i32 3
>  %125 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %126 = load <16 x i8> addrspace(2)* %125, !tbaa !0
>  %127 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %126, i32 0, i32 %5)
>  %128 = extractelement <4 x float> %127, i32 0
>  %129 = extractelement <4 x float> %127, i32 1
>  %130 = extractelement <4 x float> %127, i32 2
>  %131 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %132 = load <16 x i8> addrspace(2)* %131, !tbaa !0
>  %133 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %132, i32 0, i32 %5)
>  %134 = extractelement <4 x float> %133, i32 0
>  %135 = extractelement <4 x float> %133, i32 1
>  %136 = extractelement <4 x float> %133, i32 2
>  %137 = extractelement <4 x float> %133, i32 3
>  %138 = fmul float %121, %11
>  %139 = fmul float %121, %12
>  %140 = fmul float %121, %13
>  %141 = fmul float %121, %14
>  %142 = fmul float %122, %15
>  %143 = fadd float %142, %138
>  %144 = fmul float %122, %16
>  %145 = fadd float %144, %139
>  %146 = fmul float %122, %17
>  %147 = fadd float %146, %140
>  %148 = fmul float %122, %18
>  %149 = fadd float %148, %141
>  %150 = fmul float %123, %19
>  %151 = fadd float %150, %143
>  %152 = fmul float %123, %20
>  %153 = fadd float %152, %145
>  %154 = fmul float %123, %21
>  %155 = fadd float %154, %147
>  %156 = fmul float %123, %22
>  %157 = fadd float %156, %149
>  %158 = fmul float %124, %23
>  %159 = fadd float %158, %151
>  %160 = fmul float %124, %24
>  %161 = fadd float %160, %153
>  %162 = fmul float %124, %25
>  %163 = fadd float %162, %155
>  %164 = fmul float %124, %26
>  %165 = fadd float %164, %157
>  %166 = fmul float %128, %27
>  %167 = fmul float %129, %28
>  %168 = fadd float %167, %166
>  %169 = fmul float %130, %29
>  %170 = fadd float %168, %169
>  %171 = fmul float %128, %30
>  %172 = fmul float %129, %31
>  %173 = fadd float %172, %171
>  %174 = fmul float %130, %32
>  %175 = fadd float %173, %174
>  %176 = fmul float %128, %33
>  %177 = fmul float %129, %34
>  %178 = fadd float %177, %176
>  %179 = fmul float %130, %35
>  %180 = fadd float %178, %179
>  %181 = fmul float %170, %170
>  %182 = fmul float %175, %175
>  %183 = fadd float %182, %181
>  %184 = fmul float %180, %180
>  %185 = fadd float %183, %184
>  %186 = call float @fabs(float %185)
>  %187 = call float @llvm.AMDGPU.rsq(float %186)
>  %188 = fmul float %170, %187
>  %189 = fmul float %175, %187
>  %190 = fmul float %180, %187
>  %191 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %192 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %193 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %194 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %195 = fmul float %121, %44
>  %196 = fmul float %121, %45
>  %197 = fmul float %121, %46
>  %198 = fmul float %122, %47
>  %199 = fadd float %198, %195
>  %200 = fmul float %122, %48
>  %201 = fadd float %200, %196
>  %202 = fmul float %122, %49
>  %203 = fadd float %202, %197
>  %204 = fmul float %123, %50
>  %205 = fadd float %204, %199
>  %206 = fmul float %123, %51
>  %207 = fadd float %206, %201
>  %208 = fmul float %123, %52
>  %209 = fadd float %208, %203
>  %210 = fmul float %124, %53
>  %211 = fadd float %210, %205
>  %212 = fmul float %124, %54
>  %213 = fadd float %212, %207
>  %214 = fmul float %124, %55
>  %215 = fadd float %214, %209
>  %216 = fsub float %41, %211
>  %217 = fsub float %42, %213
>  %218 = fsub float %43, %215
>  %219 = fmul float %216, %216
>  %220 = fmul float %217, %217
>  %221 = fadd float %220, %219
>  %222 = fmul float %218, %218
>  %223 = fadd float %221, %222
>  %224 = call float @fabs(float %223)
>  %225 = call float @llvm.AMDGPU.rsq(float %224)
>  %226 = fmul float %216, %225
>  %227 = fmul float %217, %225
>  %228 = fmul float %218, %225
>  %229 = fdiv float 1.000000e+00, %225
>  %230 = fmul float %225, %229
>  %231 = fmul float %229, %229
>  %232 = fmul float %56, %230
>  %233 = fmul float %57, %229
>  %234 = fadd float %233, %232
>  %235 = fmul float %58, %231
>  %236 = fadd float %234, %235
>  %237 = fdiv float 1.000000e+00, %236
>  %238 = fmul float %211, %211
>  %239 = fmul float %213, %213
>  %240 = fadd float %239, %238
>  %241 = fmul float %215, %215
>  %242 = fadd float %240, %241
>  %243 = call float @fabs(float %242)
>  %244 = call float @llvm.AMDGPU.rsq(float %243)
>  %245 = fmul float %211, %244
>  %246 = fmul float %213, %244
>  %247 = fmul float %215, %244
>  %248 = fsub float %226, %245
>  %249 = fsub float %227, %246
>  %250 = fsub float %228, %247
>  %251 = fmul float %248, %248
>  %252 = fmul float %249, %249
>  %253 = fadd float %252, %251
>  %254 = fmul float %250, %250
>  %255 = fadd float %253, %254
>  %256 = call float @fabs(float %255)
>  %257 = call float @llvm.AMDGPU.rsq(float %256)
>  %258 = fmul float %248, %257
>  %259 = fmul float %249, %257
>  %260 = fmul float %250, %257
>  %261 = fmul float %188, %226
>  %262 = fmul float %189, %227
>  %263 = fadd float %262, %261
>  %264 = fmul float %190, %228
>  %265 = fadd float %263, %264
>  %266 = fmul float %188, %258
>  %267 = fmul float %189, %259
>  %268 = fadd float %267, %266
>  %269 = fmul float %190, %260
>  %270 = fadd float %268, %269
>  %271 = fcmp uge float %265, 0.000000e+00
>  %272 = select i1 %271, float %265, float 0.000000e+00
>  %273 = fcmp uge float %270, 0.000000e+00
>  %274 = select i1 %273, float %270, float 0.000000e+00
>  %275 = call float @llvm.pow.f32(float %274, float %36)
>  %276 = call float @llvm.AMDGPU.cndlt(float %265, float 0.000000e+00, float %275)
>  %277 = fmul float 1.000000e+00, %237
>  %278 = fmul float %272, %237
>  %279 = fmul float %276, %237
>  %280 = fmul float %277, %59
>  %281 = fadd float %280, %37
>  %282 = fmul float %277, %60
>  %283 = fadd float %282, %38
>  %284 = fmul float %277, %61
>  %285 = fadd float %284, %39
>  %286 = fmul float %278, %62
>  %287 = fadd float %286, %281
>  %288 = fmul float %278, %63
>  %289 = fadd float %288, %283
>  %290 = fmul float %278, %64
>  %291 = fadd float %290, %285
>  %292 = fmul float %279, %65
>  %293 = fadd float %292, %287
>  %294 = fmul float %279, %66
>  %295 = fadd float %294, %289
>  %296 = fmul float %279, %67
>  %297 = fadd float %296, %291
>  %298 = fsub float %68, %211
>  %299 = fsub float %69, %213
>  %300 = fsub float %70, %215
>  %301 = fmul float %298, %298
>  %302 = fmul float %299, %299
>  %303 = fadd float %302, %301
>  %304 = fmul float %300, %300
>  %305 = fadd float %303, %304
>  %306 = call float @fabs(float %305)
>  %307 = call float @llvm.AMDGPU.rsq(float %306)
>  %308 = fmul float %298, %307
>  %309 = fmul float %299, %307
>  %310 = fmul float %300, %307
>  %311 = fdiv float 1.000000e+00, %307
>  %312 = fmul float %307, %311
>  %313 = fmul float %311, %311
>  %314 = fmul float %71, %312
>  %315 = fmul float %72, %311
>  %316 = fadd float %315, %314
>  %317 = fmul float %73, %313
>  %318 = fadd float %316, %317
>  %319 = fdiv float 1.000000e+00, %318
>  %320 = fsub float %308, %245
>  %321 = fsub float %309, %246
>  %322 = fsub float %310, %247
>  %323 = fmul float %320, %320
>  %324 = fmul float %321, %321
>  %325 = fadd float %324, %323
>  %326 = fmul float %322, %322
>  %327 = fadd float %325, %326
>  %328 = call float @fabs(float %327)
>  %329 = call float @llvm.AMDGPU.rsq(float %328)
>  %330 = fmul float %320, %329
>  %331 = fmul float %321, %329
>  %332 = fmul float %322, %329
>  %333 = fmul float %188, %308
>  %334 = fmul float %189, %309
>  %335 = fadd float %334, %333
>  %336 = fmul float %190, %310
>  %337 = fadd float %335, %336
>  %338 = fmul float %188, %330
>  %339 = fmul float %189, %331
>  %340 = fadd float %339, %338
>  %341 = fmul float %190, %332
>  %342 = fadd float %340, %341
>  %343 = fcmp uge float %337, 0.000000e+00
>  %344 = select i1 %343, float %337, float 0.000000e+00
>  %345 = fcmp uge float %342, 0.000000e+00
>  %346 = select i1 %345, float %342, float 0.000000e+00
>  %347 = call float @llvm.pow.f32(float %346, float %36)
>  %348 = call float @llvm.AMDGPU.cndlt(float %337, float 0.000000e+00, float %347)
>  %349 = fmul float 1.000000e+00, %319
>  %350 = fmul float %344, %319
>  %351 = fmul float %348, %319
>  %352 = fmul float %349, %74
>  %353 = fadd float %352, %293
>  %354 = fmul float %349, %75
>  %355 = fadd float %354, %295
>  %356 = fmul float %349, %76
>  %357 = fadd float %356, %297
>  %358 = fmul float %350, %77
>  %359 = fadd float %358, %353
>  %360 = fmul float %350, %78
>  %361 = fadd float %360, %355
>  %362 = fmul float %350, %79
>  %363 = fadd float %362, %357
>  %364 = fmul float %351, %80
>  %365 = fadd float %364, %359
>  %366 = fmul float %351, %81
>  %367 = fadd float %366, %361
>  %368 = fmul float %351, %82
>  %369 = fadd float %368, %363
>  %370 = fsub float %83, %211
>  %371 = fsub float %84, %213
>  %372 = fsub float %85, %215
>  %373 = fmul float %370, %370
>  %374 = fmul float %371, %371
>  %375 = fadd float %374, %373
>  %376 = fmul float %372, %372
>  %377 = fadd float %375, %376
>  %378 = call float @fabs(float %377)
>  %379 = call float @llvm.AMDGPU.rsq(float %378)
>  %380 = fmul float %370, %379
>  %381 = fmul float %371, %379
>  %382 = fmul float %372, %379
>  %383 = fdiv float 1.000000e+00, %379
>  %384 = fmul float %379, %383
>  %385 = fmul float %383, %383
>  %386 = fmul float %86, %384
>  %387 = fmul float %87, %383
>  %388 = fadd float %387, %386
>  %389 = fmul float %88, %385
>  %390 = fadd float %388, %389
>  %391 = fdiv float 1.000000e+00, %390
>  %392 = fsub float %380, %245
>  %393 = fsub float %381, %246
>  %394 = fsub float %382, %247
>  %395 = fmul float %392, %392
>  %396 = fmul float %393, %393
>  %397 = fadd float %396, %395
>  %398 = fmul float %394, %394
>  %399 = fadd float %397, %398
>  %400 = call float @fabs(float %399)
>  %401 = call float @llvm.AMDGPU.rsq(float %400)
>  %402 = fmul float %392, %401
>  %403 = fmul float %393, %401
>  %404 = fmul float %394, %401
>  %405 = fmul float %188, %380
>  %406 = fmul float %189, %381
>  %407 = fadd float %406, %405
>  %408 = fmul float %190, %382
>  %409 = fadd float %407, %408
>  %410 = fmul float %188, %402
>  %411 = fmul float %189, %403
>  %412 = fadd float %411, %410
>  %413 = fmul float %190, %404
>  %414 = fadd float %412, %413
>  %415 = fcmp uge float %409, 0.000000e+00
>  %416 = select i1 %415, float %409, float 0.000000e+00
>  %417 = fcmp uge float %414, 0.000000e+00
>  %418 = select i1 %417, float %414, float 0.000000e+00
>  %419 = call float @llvm.pow.f32(float %418, float %36)
>  %420 = call float @llvm.AMDGPU.cndlt(float %409, float 0.000000e+00, float %419)
>  %421 = fmul float 1.000000e+00, %391
>  %422 = fmul float %416, %391
>  %423 = fmul float %420, %391
>  %424 = fmul float %421, %89
>  %425 = fadd float %424, %365
>  %426 = fmul float %421, %90
>  %427 = fadd float %426, %367
>  %428 = fmul float %421, %91
>  %429 = fadd float %428, %369
>  %430 = fmul float %422, %92
>  %431 = fadd float %430, %425
>  %432 = fmul float %422, %93
>  %433 = fadd float %432, %427
>  %434 = fmul float %422, %94
>  %435 = fadd float %434, %429
>  %436 = fmul float %423, %95
>  %437 = fadd float %436, %431
>  %438 = fmul float %423, %96
>  %439 = fadd float %438, %433
>  %440 = fmul float %423, %97
>  %441 = fadd float %440, %435
>  %442 = fsub float %98, %211
>  %443 = fsub float %99, %213
>  %444 = fsub float %100, %215
>  %445 = fmul float %442, %442
>  %446 = fmul float %443, %443
>  %447 = fadd float %446, %445
>  %448 = fmul float %444, %444
>  %449 = fadd float %447, %448
>  %450 = call float @fabs(float %449)
>  %451 = call float @llvm.AMDGPU.rsq(float %450)
>  %452 = fmul float %442, %451
>  %453 = fmul float %443, %451
>  %454 = fmul float %444, %451
>  %455 = fsub float -0.000000e+00, %452
>  %456 = fsub float -0.000000e+00, %453
>  %457 = fsub float -0.000000e+00, %454
>  %458 = fmul float %455, %105
>  %459 = fmul float %456, %106
>  %460 = fadd float %459, %458
>  %461 = fmul float %457, %107
>  %462 = fadd float %460, %461
>  %463 = fcmp olt float %108, %462
>  %464 = select i1 %463, float 1.000000e+00, float 0.000000e+00
>  %465 = fcmp olt float %108, %462
>  %466 = select i1 %465, float 1.000000e+00, float 0.000000e+00
>  %467 = fcmp olt float %108, %462
>  %468 = select i1 %467, float 1.000000e+00, float 0.000000e+00
>  %469 = call float @llvm.pow.f32(float %462, float %104)
>  %470 = fmul float %464, %469
>  %471 = fmul float %466, %469
>  %472 = fmul float %468, %469
>  %473 = fdiv float 1.000000e+00, %451
>  %474 = fmul float %451, %473
>  %475 = fmul float %473, %473
>  %476 = fmul float %101, %474
>  %477 = fmul float %102, %473
>  %478 = fadd float %477, %476
>  %479 = fmul float %103, %475
>  %480 = fadd float %478, %479
>  %481 = fdiv float 1.000000e+00, %480
>  %482 = fmul float %481, %470
>  %483 = fmul float %481, %471
>  %484 = fmul float %481, %472
>  %485 = fsub float %452, %245
>  %486 = fsub float %453, %246
>  %487 = fsub float %454, %247
>  %488 = fmul float %485, %485
>  %489 = fmul float %486, %486
>  %490 = fadd float %489, %488
>  %491 = fmul float %487, %487
>  %492 = fadd float %490, %491
>  %493 = call float @fabs(float %492)
>  %494 = call float @llvm.AMDGPU.rsq(float %493)
>  %495 = fmul float %485, %494
>  %496 = fmul float %486, %494
>  %497 = fmul float %487, %494
>  %498 = fmul float %188, %452
>  %499 = fmul float %189, %453
>  %500 = fadd float %499, %498
>  %501 = fmul float %190, %454
>  %502 = fadd float %500, %501
>  %503 = fmul float %188, %495
>  %504 = fmul float %189, %496
>  %505 = fadd float %504, %503
>  %506 = fmul float %190, %497
>  %507 = fadd float %505, %506
>  %508 = fcmp uge float %502, 0.000000e+00
>  %509 = select i1 %508, float %502, float 0.000000e+00
>  %510 = fcmp uge float %507, 0.000000e+00
>  %511 = select i1 %510, float %507, float 0.000000e+00
>  %512 = call float @llvm.pow.f32(float %511, float %36)
>  %513 = call float @llvm.AMDGPU.cndlt(float %502, float 0.000000e+00, float %512)
>  %514 = fmul float 1.000000e+00, %482
>  %515 = fmul float %509, %483
>  %516 = fmul float %513, %484
>  %517 = fmul float %514, %109
>  %518 = fadd float %517, %437
>  %519 = fmul float %514, %110
>  %520 = fadd float %519, %439
>  %521 = fmul float %514, %111
>  %522 = fadd float %521, %441
>  %523 = fmul float %515, %112
>  %524 = fadd float %523, %518
>  %525 = fmul float %515, %113
>  %526 = fadd float %525, %520
>  %527 = fmul float %515, %114
>  %528 = fadd float %527, %522
>  %529 = fmul float %516, %115
>  %530 = fadd float %529, %524
>  %531 = fmul float %516, %116
>  %532 = fadd float %531, %526
>  %533 = fmul float %516, %117
>  %534 = fadd float %533, %528
>  %535 = call float @llvm.AMDIL.clamp.(float %530, float 0.000000e+00, float 1.000000e+00)
>  %536 = call float @llvm.AMDIL.clamp.(float %532, float 0.000000e+00, float 1.000000e+00)
>  %537 = call float @llvm.AMDIL.clamp.(float %534, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %535, float %536, float %537, float %194)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %134, float %135, float %136, float %137)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %159, float %161, float %163, float %165)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>c2020155
>bf8c007f
>d2820007
>041c0912
>c2020159
>bf8c007f
>d2820007
>041c0913
>c2020165
>bf8c007f
>d2820007
>041c0914
>c2020169
>bf8c007f
>d2820007
>041c0915
>c202016d
>bf8c007f
>d2820007
>041c0916
>c202017d
>bf8c007f
>d2820007
>041c090a
>c2020181
>bf8c007f
>d2820007
>041c090c
>c2020185
>bf8c007f
>d2820007
>041c0906
>d2060807
>02010107
>c202013c
>c2028120
>bf8c007f
>7e1a0205
>d2820009
>04340909
>c2020140
>bf8c007f
>d2820009
>0424090b
>c2020144
>bf8c007f
>d2820008
>04240908
>c2020150
>bf8c007f
>d2820008
>04200911
>c2020154
>bf8c007f
>d2820008
>04200912
>c2020158
>bf8c007f
>d2820008
>04200913
>c2020164
>bf8c007f
>d2820008
>04200914
>c2020168
>bf8c007f
>d2820008
>04200915
>c202016c
>bf8c007f
>d2820008
>04200916
>c202017c
>bf8c007f
>d2820008
>0420090a
>c2020180
>bf8c007f
>d2820008
>0420090c
>c2020184
>bf8c007f
>d2820006
>04200906
>d2060806
>02010106
>c2020123
>bf8c007f
>d2060808
>02010004
>f800020f
>08050706
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..32]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD TEMP[3], TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: SUB TEMP[5], CONST[28], TEMP[4]
> 78: DP3 TEMP[7], TEMP[5], TEMP[5]
> 79: RSQ TEMP[7], |TEMP[7]|
> 80: MUL TEMP[5], TEMP[5], TEMP[7]
> 81: RCP TEMP[7].yz, TEMP[7]
> 82: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 83: DP3 TEMP[7], CONST[29], TEMP[7]
> 84: RCP TEMP[8], TEMP[7]
> 85: SUB TEMP[7], TEMP[5], TEMP[6]
> 86: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 87: RSQ TEMP[9].x, |TEMP[9]|
> 88: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 89: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 90: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 91: LIT TEMP[1], TEMP[2]
> 92: MUL TEMP[1], TEMP[1], TEMP[8]
> 93: MAD TEMP[3], TEMP[1].xxxx, CONST[30], TEMP[3]
> 94: MAD TEMP[3], TEMP[1].yyyy, CONST[31], TEMP[3]
> 95: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[32], TEMP[3]
> 96: MOV OUT[2], IN[2]
> 97: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %113 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %114 = load <16 x i8> addrspace(2)* %113, !tbaa !0
>  %115 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %114, i32 0, i32 %5)
>  %116 = extractelement <4 x float> %115, i32 0
>  %117 = extractelement <4 x float> %115, i32 1
>  %118 = extractelement <4 x float> %115, i32 2
>  %119 = extractelement <4 x float> %115, i32 3
>  %120 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
>  %122 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %121, i32 0, i32 %5)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = extractelement <4 x float> %122, i32 1
>  %125 = extractelement <4 x float> %122, i32 2
>  %126 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %127 = load <16 x i8> addrspace(2)* %126, !tbaa !0
>  %128 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %127, i32 0, i32 %5)
>  %129 = extractelement <4 x float> %128, i32 0
>  %130 = extractelement <4 x float> %128, i32 1
>  %131 = extractelement <4 x float> %128, i32 2
>  %132 = extractelement <4 x float> %128, i32 3
>  %133 = fmul float %116, %11
>  %134 = fmul float %116, %12
>  %135 = fmul float %116, %13
>  %136 = fmul float %116, %14
>  %137 = fmul float %117, %15
>  %138 = fadd float %137, %133
>  %139 = fmul float %117, %16
>  %140 = fadd float %139, %134
>  %141 = fmul float %117, %17
>  %142 = fadd float %141, %135
>  %143 = fmul float %117, %18
>  %144 = fadd float %143, %136
>  %145 = fmul float %118, %19
>  %146 = fadd float %145, %138
>  %147 = fmul float %118, %20
>  %148 = fadd float %147, %140
>  %149 = fmul float %118, %21
>  %150 = fadd float %149, %142
>  %151 = fmul float %118, %22
>  %152 = fadd float %151, %144
>  %153 = fmul float %119, %23
>  %154 = fadd float %153, %146
>  %155 = fmul float %119, %24
>  %156 = fadd float %155, %148
>  %157 = fmul float %119, %25
>  %158 = fadd float %157, %150
>  %159 = fmul float %119, %26
>  %160 = fadd float %159, %152
>  %161 = fmul float %123, %27
>  %162 = fmul float %124, %28
>  %163 = fadd float %162, %161
>  %164 = fmul float %125, %29
>  %165 = fadd float %163, %164
>  %166 = fmul float %123, %30
>  %167 = fmul float %124, %31
>  %168 = fadd float %167, %166
>  %169 = fmul float %125, %32
>  %170 = fadd float %168, %169
>  %171 = fmul float %123, %33
>  %172 = fmul float %124, %34
>  %173 = fadd float %172, %171
>  %174 = fmul float %125, %35
>  %175 = fadd float %173, %174
>  %176 = fmul float %165, %165
>  %177 = fmul float %170, %170
>  %178 = fadd float %177, %176
>  %179 = fmul float %175, %175
>  %180 = fadd float %178, %179
>  %181 = call float @fabs(float %180)
>  %182 = call float @llvm.AMDGPU.rsq(float %181)
>  %183 = fmul float %165, %182
>  %184 = fmul float %170, %182
>  %185 = fmul float %175, %182
>  %186 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %187 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %188 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %189 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %190 = fmul float %116, %44
>  %191 = fmul float %116, %45
>  %192 = fmul float %116, %46
>  %193 = fmul float %117, %47
>  %194 = fadd float %193, %190
>  %195 = fmul float %117, %48
>  %196 = fadd float %195, %191
>  %197 = fmul float %117, %49
>  %198 = fadd float %197, %192
>  %199 = fmul float %118, %50
>  %200 = fadd float %199, %194
>  %201 = fmul float %118, %51
>  %202 = fadd float %201, %196
>  %203 = fmul float %118, %52
>  %204 = fadd float %203, %198
>  %205 = fmul float %119, %53
>  %206 = fadd float %205, %200
>  %207 = fmul float %119, %54
>  %208 = fadd float %207, %202
>  %209 = fmul float %119, %55
>  %210 = fadd float %209, %204
>  %211 = fsub float %41, %206
>  %212 = fsub float %42, %208
>  %213 = fsub float %43, %210
>  %214 = fmul float %211, %211
>  %215 = fmul float %212, %212
>  %216 = fadd float %215, %214
>  %217 = fmul float %213, %213
>  %218 = fadd float %216, %217
>  %219 = call float @fabs(float %218)
>  %220 = call float @llvm.AMDGPU.rsq(float %219)
>  %221 = fmul float %211, %220
>  %222 = fmul float %212, %220
>  %223 = fmul float %213, %220
>  %224 = fdiv float 1.000000e+00, %220
>  %225 = fmul float %220, %224
>  %226 = fmul float %224, %224
>  %227 = fmul float %56, %225
>  %228 = fmul float %57, %224
>  %229 = fadd float %228, %227
>  %230 = fmul float %58, %226
>  %231 = fadd float %229, %230
>  %232 = fdiv float 1.000000e+00, %231
>  %233 = fmul float %206, %206
>  %234 = fmul float %208, %208
>  %235 = fadd float %234, %233
>  %236 = fmul float %210, %210
>  %237 = fadd float %235, %236
>  %238 = call float @fabs(float %237)
>  %239 = call float @llvm.AMDGPU.rsq(float %238)
>  %240 = fmul float %206, %239
>  %241 = fmul float %208, %239
>  %242 = fmul float %210, %239
>  %243 = fsub float %221, %240
>  %244 = fsub float %222, %241
>  %245 = fsub float %223, %242
>  %246 = fmul float %243, %243
>  %247 = fmul float %244, %244
>  %248 = fadd float %247, %246
>  %249 = fmul float %245, %245
>  %250 = fadd float %248, %249
>  %251 = call float @fabs(float %250)
>  %252 = call float @llvm.AMDGPU.rsq(float %251)
>  %253 = fmul float %243, %252
>  %254 = fmul float %244, %252
>  %255 = fmul float %245, %252
>  %256 = fmul float %183, %221
>  %257 = fmul float %184, %222
>  %258 = fadd float %257, %256
>  %259 = fmul float %185, %223
>  %260 = fadd float %258, %259
>  %261 = fmul float %183, %253
>  %262 = fmul float %184, %254
>  %263 = fadd float %262, %261
>  %264 = fmul float %185, %255
>  %265 = fadd float %263, %264
>  %266 = fcmp uge float %260, 0.000000e+00
>  %267 = select i1 %266, float %260, float 0.000000e+00
>  %268 = fcmp uge float %265, 0.000000e+00
>  %269 = select i1 %268, float %265, float 0.000000e+00
>  %270 = call float @llvm.pow.f32(float %269, float %36)
>  %271 = call float @llvm.AMDGPU.cndlt(float %260, float 0.000000e+00, float %270)
>  %272 = fmul float 1.000000e+00, %232
>  %273 = fmul float %267, %232
>  %274 = fmul float %271, %232
>  %275 = fmul float %272, %59
>  %276 = fadd float %275, %37
>  %277 = fmul float %272, %60
>  %278 = fadd float %277, %38
>  %279 = fmul float %272, %61
>  %280 = fadd float %279, %39
>  %281 = fmul float %273, %62
>  %282 = fadd float %281, %276
>  %283 = fmul float %273, %63
>  %284 = fadd float %283, %278
>  %285 = fmul float %273, %64
>  %286 = fadd float %285, %280
>  %287 = fmul float %274, %65
>  %288 = fadd float %287, %282
>  %289 = fmul float %274, %66
>  %290 = fadd float %289, %284
>  %291 = fmul float %274, %67
>  %292 = fadd float %291, %286
>  %293 = fsub float %68, %206
>  %294 = fsub float %69, %208
>  %295 = fsub float %70, %210
>  %296 = fmul float %293, %293
>  %297 = fmul float %294, %294
>  %298 = fadd float %297, %296
>  %299 = fmul float %295, %295
>  %300 = fadd float %298, %299
>  %301 = call float @fabs(float %300)
>  %302 = call float @llvm.AMDGPU.rsq(float %301)
>  %303 = fmul float %293, %302
>  %304 = fmul float %294, %302
>  %305 = fmul float %295, %302
>  %306 = fdiv float 1.000000e+00, %302
>  %307 = fmul float %302, %306
>  %308 = fmul float %306, %306
>  %309 = fmul float %71, %307
>  %310 = fmul float %72, %306
>  %311 = fadd float %310, %309
>  %312 = fmul float %73, %308
>  %313 = fadd float %311, %312
>  %314 = fdiv float 1.000000e+00, %313
>  %315 = fsub float %303, %240
>  %316 = fsub float %304, %241
>  %317 = fsub float %305, %242
>  %318 = fmul float %315, %315
>  %319 = fmul float %316, %316
>  %320 = fadd float %319, %318
>  %321 = fmul float %317, %317
>  %322 = fadd float %320, %321
>  %323 = call float @fabs(float %322)
>  %324 = call float @llvm.AMDGPU.rsq(float %323)
>  %325 = fmul float %315, %324
>  %326 = fmul float %316, %324
>  %327 = fmul float %317, %324
>  %328 = fmul float %183, %303
>  %329 = fmul float %184, %304
>  %330 = fadd float %329, %328
>  %331 = fmul float %185, %305
>  %332 = fadd float %330, %331
>  %333 = fmul float %183, %325
>  %334 = fmul float %184, %326
>  %335 = fadd float %334, %333
>  %336 = fmul float %185, %327
>  %337 = fadd float %335, %336
>  %338 = fcmp uge float %332, 0.000000e+00
>  %339 = select i1 %338, float %332, float 0.000000e+00
>  %340 = fcmp uge float %337, 0.000000e+00
>  %341 = select i1 %340, float %337, float 0.000000e+00
>  %342 = call float @llvm.pow.f32(float %341, float %36)
>  %343 = call float @llvm.AMDGPU.cndlt(float %332, float 0.000000e+00, float %342)
>  %344 = fmul float 1.000000e+00, %314
>  %345 = fmul float %339, %314
>  %346 = fmul float %343, %314
>  %347 = fmul float %344, %74
>  %348 = fadd float %347, %288
>  %349 = fmul float %344, %75
>  %350 = fadd float %349, %290
>  %351 = fmul float %344, %76
>  %352 = fadd float %351, %292
>  %353 = fmul float %345, %77
>  %354 = fadd float %353, %348
>  %355 = fmul float %345, %78
>  %356 = fadd float %355, %350
>  %357 = fmul float %345, %79
>  %358 = fadd float %357, %352
>  %359 = fmul float %346, %80
>  %360 = fadd float %359, %354
>  %361 = fmul float %346, %81
>  %362 = fadd float %361, %356
>  %363 = fmul float %346, %82
>  %364 = fadd float %363, %358
>  %365 = fsub float %83, %206
>  %366 = fsub float %84, %208
>  %367 = fsub float %85, %210
>  %368 = fmul float %365, %365
>  %369 = fmul float %366, %366
>  %370 = fadd float %369, %368
>  %371 = fmul float %367, %367
>  %372 = fadd float %370, %371
>  %373 = call float @fabs(float %372)
>  %374 = call float @llvm.AMDGPU.rsq(float %373)
>  %375 = fmul float %365, %374
>  %376 = fmul float %366, %374
>  %377 = fmul float %367, %374
>  %378 = fdiv float 1.000000e+00, %374
>  %379 = fmul float %374, %378
>  %380 = fmul float %378, %378
>  %381 = fmul float %86, %379
>  %382 = fmul float %87, %378
>  %383 = fadd float %382, %381
>  %384 = fmul float %88, %380
>  %385 = fadd float %383, %384
>  %386 = fdiv float 1.000000e+00, %385
>  %387 = fsub float %375, %240
>  %388 = fsub float %376, %241
>  %389 = fsub float %377, %242
>  %390 = fmul float %387, %387
>  %391 = fmul float %388, %388
>  %392 = fadd float %391, %390
>  %393 = fmul float %389, %389
>  %394 = fadd float %392, %393
>  %395 = call float @fabs(float %394)
>  %396 = call float @llvm.AMDGPU.rsq(float %395)
>  %397 = fmul float %387, %396
>  %398 = fmul float %388, %396
>  %399 = fmul float %389, %396
>  %400 = fmul float %183, %375
>  %401 = fmul float %184, %376
>  %402 = fadd float %401, %400
>  %403 = fmul float %185, %377
>  %404 = fadd float %402, %403
>  %405 = fmul float %183, %397
>  %406 = fmul float %184, %398
>  %407 = fadd float %406, %405
>  %408 = fmul float %185, %399
>  %409 = fadd float %407, %408
>  %410 = fcmp uge float %404, 0.000000e+00
>  %411 = select i1 %410, float %404, float 0.000000e+00
>  %412 = fcmp uge float %409, 0.000000e+00
>  %413 = select i1 %412, float %409, float 0.000000e+00
>  %414 = call float @llvm.pow.f32(float %413, float %36)
>  %415 = call float @llvm.AMDGPU.cndlt(float %404, float 0.000000e+00, float %414)
>  %416 = fmul float 1.000000e+00, %386
>  %417 = fmul float %411, %386
>  %418 = fmul float %415, %386
>  %419 = fmul float %416, %89
>  %420 = fadd float %419, %360
>  %421 = fmul float %416, %90
>  %422 = fadd float %421, %362
>  %423 = fmul float %416, %91
>  %424 = fadd float %423, %364
>  %425 = fmul float %417, %92
>  %426 = fadd float %425, %420
>  %427 = fmul float %417, %93
>  %428 = fadd float %427, %422
>  %429 = fmul float %417, %94
>  %430 = fadd float %429, %424
>  %431 = fmul float %418, %95
>  %432 = fadd float %431, %426
>  %433 = fmul float %418, %96
>  %434 = fadd float %433, %428
>  %435 = fmul float %418, %97
>  %436 = fadd float %435, %430
>  %437 = fsub float %98, %206
>  %438 = fsub float %99, %208
>  %439 = fsub float %100, %210
>  %440 = fmul float %437, %437
>  %441 = fmul float %438, %438
>  %442 = fadd float %441, %440
>  %443 = fmul float %439, %439
>  %444 = fadd float %442, %443
>  %445 = call float @fabs(float %444)
>  %446 = call float @llvm.AMDGPU.rsq(float %445)
>  %447 = fmul float %437, %446
>  %448 = fmul float %438, %446
>  %449 = fmul float %439, %446
>  %450 = fdiv float 1.000000e+00, %446
>  %451 = fmul float %446, %450
>  %452 = fmul float %450, %450
>  %453 = fmul float %101, %451
>  %454 = fmul float %102, %450
>  %455 = fadd float %454, %453
>  %456 = fmul float %103, %452
>  %457 = fadd float %455, %456
>  %458 = fdiv float 1.000000e+00, %457
>  %459 = fsub float %447, %240
>  %460 = fsub float %448, %241
>  %461 = fsub float %449, %242
>  %462 = fmul float %459, %459
>  %463 = fmul float %460, %460
>  %464 = fadd float %463, %462
>  %465 = fmul float %461, %461
>  %466 = fadd float %464, %465
>  %467 = call float @fabs(float %466)
>  %468 = call float @llvm.AMDGPU.rsq(float %467)
>  %469 = fmul float %459, %468
>  %470 = fmul float %460, %468
>  %471 = fmul float %461, %468
>  %472 = fmul float %183, %447
>  %473 = fmul float %184, %448
>  %474 = fadd float %473, %472
>  %475 = fmul float %185, %449
>  %476 = fadd float %474, %475
>  %477 = fmul float %183, %469
>  %478 = fmul float %184, %470
>  %479 = fadd float %478, %477
>  %480 = fmul float %185, %471
>  %481 = fadd float %479, %480
>  %482 = fcmp uge float %476, 0.000000e+00
>  %483 = select i1 %482, float %476, float 0.000000e+00
>  %484 = fcmp uge float %481, 0.000000e+00
>  %485 = select i1 %484, float %481, float 0.000000e+00
>  %486 = call float @llvm.pow.f32(float %485, float %36)
>  %487 = call float @llvm.AMDGPU.cndlt(float %476, float 0.000000e+00, float %486)
>  %488 = fmul float 1.000000e+00, %458
>  %489 = fmul float %483, %458
>  %490 = fmul float %487, %458
>  %491 = fmul float %488, %104
>  %492 = fadd float %491, %432
>  %493 = fmul float %488, %105
>  %494 = fadd float %493, %434
>  %495 = fmul float %488, %106
>  %496 = fadd float %495, %436
>  %497 = fmul float %489, %107
>  %498 = fadd float %497, %492
>  %499 = fmul float %489, %108
>  %500 = fadd float %499, %494
>  %501 = fmul float %489, %109
>  %502 = fadd float %501, %496
>  %503 = fmul float %490, %110
>  %504 = fadd float %503, %498
>  %505 = fmul float %490, %111
>  %506 = fadd float %505, %500
>  %507 = fmul float %490, %112
>  %508 = fadd float %507, %502
>  %509 = call float @llvm.AMDIL.clamp.(float %504, float 0.000000e+00, float 1.000000e+00)
>  %510 = call float @llvm.AMDIL.clamp.(float %506, float 0.000000e+00, float 1.000000e+00)
>  %511 = call float @llvm.AMDIL.clamp.(float %508, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %509, float %510, float %511, float %189)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %129, float %130, float %131, float %132)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %154, float %156, float %158, float %160)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
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>d282001b
>04580b14
>10343317
>102c350e
>10383315
>d2820015
>045a390f
>10303318
>d2820016
>04563110
>d00c0008
>02010116
>d2000015
>00222c80
>102a2915
>c202816a
>bf8c007f
>d2820017
>046c0b15
>08320b1c
>08340f1a
>1036351a
>d282001b
>046e3319
>08301118
>d282001b
>046e3118
>d206011b
>0201011b
>7e365b1b
>10323719
>1034371a
>1034350e
>d2820019
>046a330f
>10303718
>d2820018
>04663110
>d00c0008
>02010118
>d2000018
>00223080
>7e304f18
>0e303004
>7e304b18
>d0080008
>02022c80
>d2000016
>00210118
>102c2916
>c202816e
>bf8c007f
>d2820018
>045c0b16
>c2028171
>bf8c007f
>082e0c05
>c2028170
>bf8c007f
>08121205
>100c1309
>d2820006
>041a2f17
>c2028172
>bf8c007f
>08141405
>d2820006
>041a150a
>d2060106
>02010106
>7e325b06
>7e0c5519
>10340d19
>c2028174
>bf8c007f
>10343405
>c2028175
>bf8c007f
>d282001a
>046a0c05
>100c0d06
>c2028176
>bf8c007f
>d2820006
>046a0c05
>7e0c5506
>c202817a
>bf8c007f
>d282001a
>04600b06
>10303309
>1012310e
>10363317
>d2820009
>0426370f
>1032330a
>d282000a
>04263310
>d00c0008
>0201010a
>d2000009
>00221480
>10120d09
>c202817e
>bf8c007f
>d2820017
>04680b09
>080a0b1b
>080e0f18
>10300f07
>d2820018
>04620b05
>08101119
>d2820018
>04621108
>d2060118
>02010118
>7e305b18
>100a3105
>100e3107
>100e0f0e
>d2820005
>041e0b0f
>100e3108
>d2820005
>04160f10
>d00c0008
>02010105
>d2000005
>00220a80
>7e0a4f05
>0e0a0a04
>7e0a4b05
>d0080004
>02021480
>d2000005
>00110105
>100e0d05
>c2020182
>bf8c007f
>d2820005
>045c0907
>d2060805
>02010105
>c202013d
>c2028121
>bf8c007f
>7e100205
>d2820008
>0420090c
>c2020141
>bf8c007f
>d2820008
>0420090d
>c2020145
>bf8c007f
>d2820008
>0420090b
>c2020151
>bf8c007f
>d2820008
>04200911
>c2020155
>bf8c007f
>d2820008
>04200912
>c2020159
>bf8c007f
>d2820008
>04200913
>c2020165
>bf8c007f
>d2820008
>04200914
>c2020169
>bf8c007f
>d2820008
>04200915
>c202016d
>bf8c007f
>d2820008
>04200916
>c2020179
>bf8c007f
>d2820008
>04200906
>c202017d
>bf8c007f
>d2820008
>04200909
>c2020181
>bf8c007f
>d2820008
>04200907
>d2060808
>02010108
>c202013c
>c2028120
>bf8c007f
>7e140205
>d282000a
>0428090c
>c2020140
>bf8c007f
>d282000a
>0428090d
>c2020144
>bf8c007f
>d282000a
>0428090b
>c2020150
>bf8c007f
>d282000a
>04280911
>c2020154
>bf8c007f
>d282000a
>04280912
>c2020158
>bf8c007f
>d282000a
>04280913
>c2020164
>bf8c007f
>d282000a
>04280914
>c2020168
>bf8c007f
>d282000a
>04280915
>c202016c
>bf8c007f
>d282000a
>04280916
>c2020178
>bf8c007f
>d2820006
>04280906
>c202017c
>bf8c007f
>d2820006
>04180909
>c2020180
>bf8c007f
>d2820006
>04180907
>d2060806
>02010106
>c2020123
>bf8c007f
>d2060807
>02010004
>f800020f
>07050806
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..22]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: MOV OUT[2], IN[2]
> 59: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %84 = load <16 x i8> addrspace(2)* %83, !tbaa !0
>  %85 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %84, i32 0, i32 %5)
>  %86 = extractelement <4 x float> %85, i32 0
>  %87 = extractelement <4 x float> %85, i32 1
>  %88 = extractelement <4 x float> %85, i32 2
>  %89 = extractelement <4 x float> %85, i32 3
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %97 = load <16 x i8> addrspace(2)* %96, !tbaa !0
>  %98 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %97, i32 0, i32 %5)
>  %99 = extractelement <4 x float> %98, i32 0
>  %100 = extractelement <4 x float> %98, i32 1
>  %101 = extractelement <4 x float> %98, i32 2
>  %102 = extractelement <4 x float> %98, i32 3
>  %103 = fmul float %86, %11
>  %104 = fmul float %86, %12
>  %105 = fmul float %86, %13
>  %106 = fmul float %86, %14
>  %107 = fmul float %87, %15
>  %108 = fadd float %107, %103
>  %109 = fmul float %87, %16
>  %110 = fadd float %109, %104
>  %111 = fmul float %87, %17
>  %112 = fadd float %111, %105
>  %113 = fmul float %87, %18
>  %114 = fadd float %113, %106
>  %115 = fmul float %88, %19
>  %116 = fadd float %115, %108
>  %117 = fmul float %88, %20
>  %118 = fadd float %117, %110
>  %119 = fmul float %88, %21
>  %120 = fadd float %119, %112
>  %121 = fmul float %88, %22
>  %122 = fadd float %121, %114
>  %123 = fmul float %89, %23
>  %124 = fadd float %123, %116
>  %125 = fmul float %89, %24
>  %126 = fadd float %125, %118
>  %127 = fmul float %89, %25
>  %128 = fadd float %127, %120
>  %129 = fmul float %89, %26
>  %130 = fadd float %129, %122
>  %131 = fmul float %93, %27
>  %132 = fmul float %94, %28
>  %133 = fadd float %132, %131
>  %134 = fmul float %95, %29
>  %135 = fadd float %133, %134
>  %136 = fmul float %93, %30
>  %137 = fmul float %94, %31
>  %138 = fadd float %137, %136
>  %139 = fmul float %95, %32
>  %140 = fadd float %138, %139
>  %141 = fmul float %93, %33
>  %142 = fmul float %94, %34
>  %143 = fadd float %142, %141
>  %144 = fmul float %95, %35
>  %145 = fadd float %143, %144
>  %146 = fmul float %135, %135
>  %147 = fmul float %140, %140
>  %148 = fadd float %147, %146
>  %149 = fmul float %145, %145
>  %150 = fadd float %148, %149
>  %151 = call float @fabs(float %150)
>  %152 = call float @llvm.AMDGPU.rsq(float %151)
>  %153 = fmul float %135, %152
>  %154 = fmul float %140, %152
>  %155 = fmul float %145, %152
>  %156 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %157 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %158 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %159 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %160 = fmul float %86, %44
>  %161 = fmul float %86, %45
>  %162 = fmul float %86, %46
>  %163 = fmul float %87, %47
>  %164 = fadd float %163, %160
>  %165 = fmul float %87, %48
>  %166 = fadd float %165, %161
>  %167 = fmul float %87, %49
>  %168 = fadd float %167, %162
>  %169 = fmul float %88, %50
>  %170 = fadd float %169, %164
>  %171 = fmul float %88, %51
>  %172 = fadd float %171, %166
>  %173 = fmul float %88, %52
>  %174 = fadd float %173, %168
>  %175 = fmul float %89, %53
>  %176 = fadd float %175, %170
>  %177 = fmul float %89, %54
>  %178 = fadd float %177, %172
>  %179 = fmul float %89, %55
>  %180 = fadd float %179, %174
>  %181 = fsub float %41, %176
>  %182 = fsub float %42, %178
>  %183 = fsub float %43, %180
>  %184 = fmul float %181, %181
>  %185 = fmul float %182, %182
>  %186 = fadd float %185, %184
>  %187 = fmul float %183, %183
>  %188 = fadd float %186, %187
>  %189 = call float @fabs(float %188)
>  %190 = call float @llvm.AMDGPU.rsq(float %189)
>  %191 = fmul float %181, %190
>  %192 = fmul float %182, %190
>  %193 = fmul float %183, %190
>  %194 = fdiv float 1.000000e+00, %190
>  %195 = fmul float %190, %194
>  %196 = fmul float %194, %194
>  %197 = fmul float %56, %195
>  %198 = fmul float %57, %194
>  %199 = fadd float %198, %197
>  %200 = fmul float %58, %196
>  %201 = fadd float %199, %200
>  %202 = fdiv float 1.000000e+00, %201
>  %203 = fmul float %176, %176
>  %204 = fmul float %178, %178
>  %205 = fadd float %204, %203
>  %206 = fmul float %180, %180
>  %207 = fadd float %205, %206
>  %208 = call float @fabs(float %207)
>  %209 = call float @llvm.AMDGPU.rsq(float %208)
>  %210 = fmul float %176, %209
>  %211 = fmul float %178, %209
>  %212 = fmul float %180, %209
>  %213 = fsub float %191, %210
>  %214 = fsub float %192, %211
>  %215 = fsub float %193, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fmul float %153, %191
>  %227 = fmul float %154, %192
>  %228 = fadd float %227, %226
>  %229 = fmul float %155, %193
>  %230 = fadd float %228, %229
>  %231 = fmul float %153, %223
>  %232 = fmul float %154, %224
>  %233 = fadd float %232, %231
>  %234 = fmul float %155, %225
>  %235 = fadd float %233, %234
>  %236 = fcmp uge float %230, 0.000000e+00
>  %237 = select i1 %236, float %230, float 0.000000e+00
>  %238 = fcmp uge float %235, 0.000000e+00
>  %239 = select i1 %238, float %235, float 0.000000e+00
>  %240 = call float @llvm.pow.f32(float %239, float %36)
>  %241 = call float @llvm.AMDGPU.cndlt(float %230, float 0.000000e+00, float %240)
>  %242 = fmul float 1.000000e+00, %202
>  %243 = fmul float %237, %202
>  %244 = fmul float %241, %202
>  %245 = fmul float %242, %59
>  %246 = fadd float %245, %37
>  %247 = fmul float %242, %60
>  %248 = fadd float %247, %38
>  %249 = fmul float %242, %61
>  %250 = fadd float %249, %39
>  %251 = fmul float %243, %62
>  %252 = fadd float %251, %246
>  %253 = fmul float %243, %63
>  %254 = fadd float %253, %248
>  %255 = fmul float %243, %64
>  %256 = fadd float %255, %250
>  %257 = fmul float %244, %65
>  %258 = fadd float %257, %252
>  %259 = fmul float %244, %66
>  %260 = fadd float %259, %254
>  %261 = fmul float %244, %67
>  %262 = fadd float %261, %256
>  %263 = fsub float %68, %176
>  %264 = fsub float %69, %178
>  %265 = fsub float %70, %180
>  %266 = fmul float %263, %263
>  %267 = fmul float %264, %264
>  %268 = fadd float %267, %266
>  %269 = fmul float %265, %265
>  %270 = fadd float %268, %269
>  %271 = call float @fabs(float %270)
>  %272 = call float @llvm.AMDGPU.rsq(float %271)
>  %273 = fmul float %263, %272
>  %274 = fmul float %264, %272
>  %275 = fmul float %265, %272
>  %276 = fdiv float 1.000000e+00, %272
>  %277 = fmul float %272, %276
>  %278 = fmul float %276, %276
>  %279 = fmul float %71, %277
>  %280 = fmul float %72, %276
>  %281 = fadd float %280, %279
>  %282 = fmul float %73, %278
>  %283 = fadd float %281, %282
>  %284 = fdiv float 1.000000e+00, %283
>  %285 = fsub float %273, %210
>  %286 = fsub float %274, %211
>  %287 = fsub float %275, %212
>  %288 = fmul float %285, %285
>  %289 = fmul float %286, %286
>  %290 = fadd float %289, %288
>  %291 = fmul float %287, %287
>  %292 = fadd float %290, %291
>  %293 = call float @fabs(float %292)
>  %294 = call float @llvm.AMDGPU.rsq(float %293)
>  %295 = fmul float %285, %294
>  %296 = fmul float %286, %294
>  %297 = fmul float %287, %294
>  %298 = fmul float %153, %273
>  %299 = fmul float %154, %274
>  %300 = fadd float %299, %298
>  %301 = fmul float %155, %275
>  %302 = fadd float %300, %301
>  %303 = fmul float %153, %295
>  %304 = fmul float %154, %296
>  %305 = fadd float %304, %303
>  %306 = fmul float %155, %297
>  %307 = fadd float %305, %306
>  %308 = fcmp uge float %302, 0.000000e+00
>  %309 = select i1 %308, float %302, float 0.000000e+00
>  %310 = fcmp uge float %307, 0.000000e+00
>  %311 = select i1 %310, float %307, float 0.000000e+00
>  %312 = call float @llvm.pow.f32(float %311, float %36)
>  %313 = call float @llvm.AMDGPU.cndlt(float %302, float 0.000000e+00, float %312)
>  %314 = fmul float 1.000000e+00, %284
>  %315 = fmul float %309, %284
>  %316 = fmul float %313, %284
>  %317 = fmul float %314, %74
>  %318 = fadd float %317, %258
>  %319 = fmul float %314, %75
>  %320 = fadd float %319, %260
>  %321 = fmul float %314, %76
>  %322 = fadd float %321, %262
>  %323 = fmul float %315, %77
>  %324 = fadd float %323, %318
>  %325 = fmul float %315, %78
>  %326 = fadd float %325, %320
>  %327 = fmul float %315, %79
>  %328 = fadd float %327, %322
>  %329 = fmul float %316, %80
>  %330 = fadd float %329, %324
>  %331 = fmul float %316, %81
>  %332 = fadd float %331, %326
>  %333 = fmul float %316, %82
>  %334 = fadd float %333, %328
>  %335 = call float @llvm.AMDIL.clamp.(float %330, float 0.000000e+00, float 1.000000e+00)
>  %336 = call float @llvm.AMDIL.clamp.(float %332, float 0.000000e+00, float 1.000000e+00)
>  %337 = call float @llvm.AMDIL.clamp.(float %334, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %335, float %336, float %337, float %159)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %99, float %100, float %101, float %102)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %124, float %126, float %128, float %130)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020129
>bf8c007f
>100a0204
>c202012d
>bf8c007f
>d2820005
>04140902
>c2020131
>bf8c007f
>d2820005
>04140903
>c2020135
>bf8c007f
>d2820006
>04140904
>c2020128
>bf8c007f
>100a0204
>c202012c
>bf8c007f
>d2820005
>04140902
>c2020130
>bf8c007f
>d2820005
>04140903
>c2020134
>bf8c007f
>d2820009
>04140904
>100a1309
>d2820005
>04160d06
>c202012a
>bf8c007f
>100e0204
>c202012e
>bf8c007f
>d2820007
>041c0902
>c2020132
>bf8c007f
>d2820007
>041c0903
>c2020136
>bf8c007f
>d282000a
>041c0904
>d2820005
>0416150a
>d2060105
>02010105
>7e105b05
>100a1106
>c2020125
>bf8c007f
>080e0c04
>c2020124
>bf8c007f
>081a1204
>10161b0d
>d282000b
>042e0f07
>c2020126
>bf8c007f
>081c1404
>d282000b
>042e1d0e
>d206010b
>0201010b
>7e165b0b
>10181707
>081e0b0c
>100e1109
>101a170d
>08280f0d
>10202914
>d2820012
>04421f0f
>1010110a
>1022170e
>08201111
>d282000e
>044a2110
>d206010e
>0201010e
>7e245b0e
>1026250f
>101e2514
>c0840704
>bf8c007f
>e00c2000
>80021400
>c2020114
>bf8c0070
>101c2804
>c2020115
>bf8c007f
>d282000e
>04380915
>c2020116
>bf8c007f
>d2820018
>04380916
>c2020110
>bf8c007f
>101c2804
>c2020111
>bf8c007f
>d282000e
>04380915
>c2020112
>bf8c007f
>d282000e
>04380916
>10321d0e
>d2820019
>04663118
>c2020118
>bf8c007f
>10342804
>c2020119
>bf8c007f
>d282001a
>04680915
>c202011a
>bf8c007f
>d2820014
>04680916
>d2820015
>04662914
>d2060115
>02010115
>7e2a5b15
>101c2b0e
>102c1f0e
>101e2b18
>d2820013
>045a270f
>10242510
>10202b14
>d2820012
>044e2510
>d00c0004
>02010112
>d2000012
>00122480
>7e244f12
>c202011c
>bf8c007f
>0e242404
>7e244b12
>101a1b0e
>d282000c
>0436190f
>d282000d
>04322310
>d0080008
>02021a80
>d2000011
>00210112
>7e18550b
>1016190b
>c2028138
>bf8c007f
>10161605
>c2028139
>bf8c007f
>d282000b
>042e1805
>1018190c
>c202813a
>bf8c007f
>d282000b
>042e1805
>7e18550b
>10161911
>d00c0008
>0201010d
>d200000d
>00221a80
>101a190d
>c202813e
>c2040122
>bf8c007f
>7e220208
>d2820011
>04440b0c
>c2028142
>bf8c007f
>d2820011
>04440b0d
>c2028146
>bf8c007f
>d2820012
>04440b0b
>c2028149
>bf8c007f
>08220c05
>c2028148
>bf8c007f
>08121205
>100c1309
>d2820006
>041a2311
>c202814a
>bf8c007f
>08141405
>d2820006
>041a150a
>d2060106
>02010106
>7e265b06
>7e0c5513
>10280d13
>c202814c
>bf8c007f
>10282805
>c202814d
>bf8c007f
>d2820014
>04520c05
>100c0d06
>c202814e
>bf8c007f
>d2820006
>04520c05
>7e0c5506
>c2028152
>bf8c007f
>d2820014
>04480b06
>10242709
>1012250e
>102a2711
>d2820009
>04262b0f
>1026270a
>d282000a
>04262710
>d00c0008
>0201010a
>d2000009
>00221480
>10120d09
>c2028156
>bf8c007f
>d2820011
>04500b09
>080a0b15
>080e0f12
>10240f07
>d2820012
>044a0b05
>08101113
>d2820012
>044a1108
>d2060112
>02010112
>7e245b12
>100a2505
>100e2507
>100e0f0e
>d2820005
>041e0b0f
>100e2508
>d2820005
>04160f10
>d00c0008
>02010105
>d2000005
>00220a80
>7e0a4f05
>0e0a0a04
>7e0a4b05
>d0080004
>02021480
>d2000005
>00110105
>100e0d05
>c202015a
>bf8c007f
>d2820005
>04440907
>d2060805
>02010105
>c202013d
>c2028121
>bf8c007f
>7e100205
>d2820008
>0420090c
>c2020141
>bf8c007f
>d2820008
>0420090d
>c2020145
>bf8c007f
>d2820008
>0420090b
>c2020151
>bf8c007f
>d2820008
>04200906
>c2020155
>bf8c007f
>d2820008
>04200909
>c2020159
>bf8c007f
>d2820008
>04200907
>d2060808
>02010108
>c202013c
>c2028120
>bf8c007f
>7e140205
>d282000a
>0428090c
>c2020140
>bf8c007f
>d282000a
>0428090d
>c2020144
>bf8c007f
>d282000a
>0428090b
>c2020150
>bf8c007f
>d2820006
>04280906
>c2020154
>bf8c007f
>d2820006
>04180909
>c2020158
>bf8c007f
>d2820006
>04180907
>d2060806
>02010106
>c2020123
>bf8c007f
>d2060807
>02010004
>f800020f
>07050806
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[1].xyz, TEMP[0], IN[0]
>  4: MOV TEMP[1].xyz, TEMP[1].xyzx
>  5: MOV TEMP[1].w, TEMP[0].wwww
>  6: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
>  7: MOV TEMP[0].xyz, TEMP[0].xyzx
>  8: MOV TEMP[1].xy, IN[2].xyyy
>  9: MOV TEMP[1].w, IN[2].wwww
> 10: TXP TEMP[1].w, TEMP[1], SAMP[0], 2D
> 11: MOV TEMP[0].w, TEMP[1].wwww
> 12: MOV OUT[0], TEMP[0]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %37 = fdiv float %31, %33
>  %38 = fdiv float %32, %33
>  %39 = bitcast float %37 to i32
>  %40 = bitcast float %38 to i32
>  %41 = insertelement <2 x i32> undef, i32 %39, i32 0
>  %42 = insertelement <2 x i32> %41, i32 %40, i32 1
>  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %42, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %44, %28
>  %49 = fmul float %45, %29
>  %50 = fmul float %46, %30
>  %51 = fmul float %48, 2.000000e+00
>  %52 = fmul float %49, 2.000000e+00
>  %53 = fmul float %50, 2.000000e+00
>  %54 = fmul float %47, 1.000000e+00
>  %55 = call float @llvm.AMDIL.clamp.(float %51, float 0.000000e+00, float 1.000000e+00)
>  %56 = call float @llvm.AMDIL.clamp.(float %52, float 0.000000e+00, float 1.000000e+00)
>  %57 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
>  %58 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %59 = fdiv float %34, %36
>  %60 = fdiv float %35, %36
>  %61 = bitcast float %59 to i32
>  %62 = bitcast float %60 to i32
>  %63 = insertelement <2 x i32> undef, i32 %61, i32 0
>  %64 = insertelement <2 x i32> %63, i32 %62, i32 1
>  %65 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %64, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %66 = extractelement <4 x float> %65, i32 3
>  %67 = call i32 @llvm.SI.packf16(float %55, float %56)
>  %68 = bitcast i32 %67 to float
>  %69 = call i32 @llvm.SI.packf16(float %57, float %66)
>  %70 = bitcast i32 %69 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %68, float %70, float %68, float %70)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800700
>00430302
>c8080100
>c8090101
>bf8c0770
>100c0504
>d2820002
>041a0504
>d2060802
>02010102
>c8180000
>c8190001
>100e0d03
>d2820006
>041e0d03
>d2060806
>02010106
>5e040506
>c8180200
>c8190201
>100e0d05
>d2820003
>041e0d05
>d2060803
>02010103
>c8100900
>c8110901
>c8140b00
>c8150b01
>7e0c5505
>100a0d04
>c81c0800
>c81d0801
>10080d07
>c0800300
>c0c20500
>bf8c007f
>f0800800
>00010004
>bf8c0770
>5e000103
>f8001c0f
>00020002
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..17]
>DCL TEMP[0..3]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: DP4 TEMP[1].x, IN[0], CONST[11]
> 15: DP4 TEMP[1].y, IN[0], CONST[12]
> 16: DP4 TEMP[1].z, IN[0], CONST[13]
> 17: MOV TEMP[1].w, IN[3]
> 18: MUL TEMP[2], TEMP[1].xxxx, CONST[14]
> 19: MAD TEMP[2], TEMP[1].yyyy, CONST[15], TEMP[2]
> 20: MAD TEMP[2], TEMP[1].zzzz, CONST[16], TEMP[2]
> 21: MAD OUT[2], TEMP[1].wwww, CONST[17], TEMP[2]
> 22: MOV OUT[3], IN[4]
> 23: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 252)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 268)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 284)
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = extractelement <4 x float> %73, i32 3
>  %78 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %79 = load <16 x i8> addrspace(2)* %78, !tbaa !0
>  %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %79, i32 0, i32 %5)
>  %81 = extractelement <4 x float> %80, i32 0
>  %82 = extractelement <4 x float> %80, i32 1
>  %83 = extractelement <4 x float> %80, i32 2
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 3
>  %94 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %95 = load <16 x i8> addrspace(2)* %94, !tbaa !0
>  %96 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %95, i32 0, i32 %5)
>  %97 = extractelement <4 x float> %96, i32 0
>  %98 = extractelement <4 x float> %96, i32 1
>  %99 = extractelement <4 x float> %96, i32 2
>  %100 = extractelement <4 x float> %96, i32 3
>  %101 = fmul float %74, %11
>  %102 = fmul float %74, %12
>  %103 = fmul float %74, %13
>  %104 = fmul float %74, %14
>  %105 = fmul float %75, %15
>  %106 = fadd float %105, %101
>  %107 = fmul float %75, %16
>  %108 = fadd float %107, %102
>  %109 = fmul float %75, %17
>  %110 = fadd float %109, %103
>  %111 = fmul float %75, %18
>  %112 = fadd float %111, %104
>  %113 = fmul float %76, %19
>  %114 = fadd float %113, %106
>  %115 = fmul float %76, %20
>  %116 = fadd float %115, %108
>  %117 = fmul float %76, %21
>  %118 = fadd float %117, %110
>  %119 = fmul float %76, %22
>  %120 = fadd float %119, %112
>  %121 = fmul float %77, %23
>  %122 = fadd float %121, %114
>  %123 = fmul float %77, %24
>  %124 = fadd float %123, %116
>  %125 = fmul float %77, %25
>  %126 = fadd float %125, %118
>  %127 = fmul float %77, %26
>  %128 = fadd float %127, %120
>  %129 = fmul float %81, %27
>  %130 = fmul float %82, %28
>  %131 = fadd float %130, %129
>  %132 = fmul float %83, %29
>  %133 = fadd float %131, %132
>  %134 = fmul float %81, %30
>  %135 = fmul float %82, %31
>  %136 = fadd float %135, %134
>  %137 = fmul float %83, %32
>  %138 = fadd float %136, %137
>  %139 = fmul float %81, %33
>  %140 = fmul float %82, %34
>  %141 = fadd float %140, %139
>  %142 = fmul float %83, %35
>  %143 = fadd float %141, %142
>  %144 = fmul float %133, %133
>  %145 = fmul float %138, %138
>  %146 = fadd float %145, %144
>  %147 = fmul float %143, %143
>  %148 = fadd float %146, %147
>  %149 = call float @fabs(float %148)
>  %150 = call float @llvm.AMDGPU.rsq(float %149)
>  %151 = fmul float %36, %39
>  %152 = fadd float %151, %87
>  %153 = fmul float %37, %40
>  %154 = fadd float %153, %88
>  %155 = fmul float %38, %41
>  %156 = fadd float %155, %89
>  %157 = call float @llvm.AMDIL.clamp.(float %152, float 0.000000e+00, float 1.000000e+00)
>  %158 = call float @llvm.AMDIL.clamp.(float %154, float 0.000000e+00, float 1.000000e+00)
>  %159 = call float @llvm.AMDIL.clamp.(float %156, float 0.000000e+00, float 1.000000e+00)
>  %160 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %161 = fmul float %74, %43
>  %162 = fmul float %75, %44
>  %163 = fadd float %161, %162
>  %164 = fmul float %76, %45
>  %165 = fadd float %163, %164
>  %166 = fmul float %77, %46
>  %167 = fadd float %165, %166
>  %168 = fmul float %74, %47
>  %169 = fmul float %75, %48
>  %170 = fadd float %168, %169
>  %171 = fmul float %76, %49
>  %172 = fadd float %170, %171
>  %173 = fmul float %77, %50
>  %174 = fadd float %172, %173
>  %175 = fmul float %74, %51
>  %176 = fmul float %75, %52
>  %177 = fadd float %175, %176
>  %178 = fmul float %76, %53
>  %179 = fadd float %177, %178
>  %180 = fmul float %77, %54
>  %181 = fadd float %179, %180
>  %182 = fmul float %167, %55
>  %183 = fmul float %167, %56
>  %184 = fmul float %167, %57
>  %185 = fmul float %167, %58
>  %186 = fmul float %174, %59
>  %187 = fadd float %186, %182
>  %188 = fmul float %174, %60
>  %189 = fadd float %188, %183
>  %190 = fmul float %174, %61
>  %191 = fadd float %190, %184
>  %192 = fmul float %174, %62
>  %193 = fadd float %192, %185
>  %194 = fmul float %181, %63
>  %195 = fadd float %194, %187
>  %196 = fmul float %181, %64
>  %197 = fadd float %196, %189
>  %198 = fmul float %181, %65
>  %199 = fadd float %198, %191
>  %200 = fmul float %181, %66
>  %201 = fadd float %200, %193
>  %202 = fmul float %93, %67
>  %203 = fadd float %202, %195
>  %204 = fmul float %93, %68
>  %205 = fadd float %204, %197
>  %206 = fmul float %93, %69
>  %207 = fadd float %206, %199
>  %208 = fmul float %93, %70
>  %209 = fadd float %208, %201
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %157, float %158, float %159, float %160)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %203, float %205, float %207, float %209)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %97, float %98, float %99, float %100)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %122, float %124, float %126, float %128)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c0840700
>bf8c000f
>e00c2000
>80020100
>c2020131
>bf8c0070
>100a0404
>c2020130
>bf8c007f
>d2820005
>04140901
>c2020132
>bf8c007f
>d2820005
>04140903
>c2020133
>bf8c007f
>d2820005
>04140904
>c202012d
>bf8c007f
>100c0404
>c202012c
>bf8c007f
>d2820006
>04180901
>c202012e
>bf8c007f
>d2820006
>04180903
>c202012f
>bf8c007f
>d2820006
>04180904
>c202013b
>bf8c007f
>100e0c04
>c202013f
>bf8c007f
>d2820008
>041c0905
>c2020135
>bf8c007f
>100e0404
>c2020134
>bf8c007f
>d2820007
>041c0901
>c2020136
>bf8c007f
>d2820007
>041c0903
>c2020137
>bf8c007f
>d2820007
>041c0904
>c2020143
>bf8c007f
>d282000c
>04200907
>c084070c
>bf8c007f
>e00c2000
>80020800
>c2020147
>bf8c0070
>d282000c
>0430090b
>c202013a
>bf8c007f
>101a0c04
>c202013e
>bf8c007f
>d282000d
>04340905
>c2020142
>bf8c007f
>d282000d
>04340907
>c2020146
>bf8c007f
>d282000d
>0434090b
>c2020139
>bf8c007f
>101c0c04
>c202013d
>bf8c007f
>d282000e
>04380905
>c2020141
>bf8c007f
>d282000e
>04380907
>c2020145
>bf8c007f
>d282000e
>0438090b
>c2020138
>bf8c007f
>100c0c04
>c202013c
>bf8c007f
>d2820005
>04180905
>c2020140
>bf8c007f
>d2820005
>04140907
>c2020144
>bf8c007f
>d2820005
>0414090b
>f800021f
>0c0d0e05
>c0820710
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..26]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: DP4 TEMP[1].x, IN[0], CONST[20]
> 41: DP4 TEMP[1].y, IN[0], CONST[21]
> 42: DP4 TEMP[1].z, IN[0], CONST[22]
> 43: MOV TEMP[1].w, IN[3]
> 44: MUL TEMP[2], TEMP[1].xxxx, CONST[23]
> 45: MAD TEMP[2], TEMP[1].yyyy, CONST[24], TEMP[2]
> 46: MAD TEMP[2], TEMP[1].zzzz, CONST[25], TEMP[2]
> 47: MAD OUT[2], TEMP[1].wwww, CONST[26], TEMP[2]
> 48: MOV OUT[3], IN[4]
> 49: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
>  %99 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %100 = load <16 x i8> addrspace(2)* %99, !tbaa !0
>  %101 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %100, i32 0, i32 %5)
>  %102 = extractelement <4 x float> %101, i32 0
>  %103 = extractelement <4 x float> %101, i32 1
>  %104 = extractelement <4 x float> %101, i32 2
>  %105 = extractelement <4 x float> %101, i32 3
>  %106 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %107 = load <16 x i8> addrspace(2)* %106, !tbaa !0
>  %108 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %107, i32 0, i32 %5)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = extractelement <4 x float> %108, i32 1
>  %111 = extractelement <4 x float> %108, i32 2
>  %112 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %113 = load <16 x i8> addrspace(2)* %112, !tbaa !0
>  %114 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %113, i32 0, i32 %5)
>  %115 = extractelement <4 x float> %114, i32 0
>  %116 = extractelement <4 x float> %114, i32 1
>  %117 = extractelement <4 x float> %114, i32 2
>  %118 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %119 = load <16 x i8> addrspace(2)* %118, !tbaa !0
>  %120 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %119, i32 0, i32 %5)
>  %121 = extractelement <4 x float> %120, i32 3
>  %122 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
>  %124 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %123, i32 0, i32 %5)
>  %125 = extractelement <4 x float> %124, i32 0
>  %126 = extractelement <4 x float> %124, i32 1
>  %127 = extractelement <4 x float> %124, i32 2
>  %128 = extractelement <4 x float> %124, i32 3
>  %129 = fmul float %102, %11
>  %130 = fmul float %102, %12
>  %131 = fmul float %102, %13
>  %132 = fmul float %102, %14
>  %133 = fmul float %103, %15
>  %134 = fadd float %133, %129
>  %135 = fmul float %103, %16
>  %136 = fadd float %135, %130
>  %137 = fmul float %103, %17
>  %138 = fadd float %137, %131
>  %139 = fmul float %103, %18
>  %140 = fadd float %139, %132
>  %141 = fmul float %104, %19
>  %142 = fadd float %141, %134
>  %143 = fmul float %104, %20
>  %144 = fadd float %143, %136
>  %145 = fmul float %104, %21
>  %146 = fadd float %145, %138
>  %147 = fmul float %104, %22
>  %148 = fadd float %147, %140
>  %149 = fmul float %105, %23
>  %150 = fadd float %149, %142
>  %151 = fmul float %105, %24
>  %152 = fadd float %151, %144
>  %153 = fmul float %105, %25
>  %154 = fadd float %153, %146
>  %155 = fmul float %105, %26
>  %156 = fadd float %155, %148
>  %157 = fmul float %109, %27
>  %158 = fmul float %110, %28
>  %159 = fadd float %158, %157
>  %160 = fmul float %111, %29
>  %161 = fadd float %159, %160
>  %162 = fmul float %109, %30
>  %163 = fmul float %110, %31
>  %164 = fadd float %163, %162
>  %165 = fmul float %111, %32
>  %166 = fadd float %164, %165
>  %167 = fmul float %109, %33
>  %168 = fmul float %110, %34
>  %169 = fadd float %168, %167
>  %170 = fmul float %111, %35
>  %171 = fadd float %169, %170
>  %172 = fmul float %161, %161
>  %173 = fmul float %166, %166
>  %174 = fadd float %173, %172
>  %175 = fmul float %171, %171
>  %176 = fadd float %174, %175
>  %177 = call float @fabs(float %176)
>  %178 = call float @llvm.AMDGPU.rsq(float %177)
>  %179 = fmul float %161, %178
>  %180 = fmul float %166, %178
>  %181 = fmul float %171, %178
>  %182 = fmul float %37, %40
>  %183 = fadd float %182, %115
>  %184 = fmul float %38, %41
>  %185 = fadd float %184, %116
>  %186 = fmul float %39, %42
>  %187 = fadd float %186, %117
>  %188 = call float @llvm.AMDIL.clamp.(float %183, float 0.000000e+00, float 1.000000e+00)
>  %189 = call float @llvm.AMDIL.clamp.(float %185, float 0.000000e+00, float 1.000000e+00)
>  %190 = call float @llvm.AMDIL.clamp.(float %187, float 0.000000e+00, float 1.000000e+00)
>  %191 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %192 = fmul float %102, %47
>  %193 = fmul float %102, %48
>  %194 = fmul float %102, %49
>  %195 = fmul float %103, %50
>  %196 = fadd float %195, %192
>  %197 = fmul float %103, %51
>  %198 = fadd float %197, %193
>  %199 = fmul float %103, %52
>  %200 = fadd float %199, %194
>  %201 = fmul float %104, %53
>  %202 = fadd float %201, %196
>  %203 = fmul float %104, %54
>  %204 = fadd float %203, %198
>  %205 = fmul float %104, %55
>  %206 = fadd float %205, %200
>  %207 = fmul float %105, %56
>  %208 = fadd float %207, %202
>  %209 = fmul float %105, %57
>  %210 = fadd float %209, %204
>  %211 = fmul float %105, %58
>  %212 = fadd float %211, %206
>  %213 = fsub float %44, %208
>  %214 = fsub float %45, %210
>  %215 = fsub float %46, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fdiv float 1.000000e+00, %222
>  %227 = fmul float %222, %226
>  %228 = fmul float %226, %226
>  %229 = fmul float %59, %227
>  %230 = fmul float %60, %226
>  %231 = fadd float %230, %229
>  %232 = fmul float %61, %228
>  %233 = fadd float %231, %232
>  %234 = fdiv float 1.000000e+00, %233
>  %235 = fmul float %208, %208
>  %236 = fmul float %210, %210
>  %237 = fadd float %236, %235
>  %238 = fmul float %212, %212
>  %239 = fadd float %237, %238
>  %240 = call float @fabs(float %239)
>  %241 = call float @llvm.AMDGPU.rsq(float %240)
>  %242 = fmul float %208, %241
>  %243 = fmul float %210, %241
>  %244 = fmul float %212, %241
>  %245 = fsub float %223, %242
>  %246 = fsub float %224, %243
>  %247 = fsub float %225, %244
>  %248 = fmul float %245, %245
>  %249 = fmul float %246, %246
>  %250 = fadd float %249, %248
>  %251 = fmul float %247, %247
>  %252 = fadd float %250, %251
>  %253 = call float @fabs(float %252)
>  %254 = call float @llvm.AMDGPU.rsq(float %253)
>  %255 = fmul float %245, %254
>  %256 = fmul float %246, %254
>  %257 = fmul float %247, %254
>  %258 = fmul float %179, %223
>  %259 = fmul float %180, %224
>  %260 = fadd float %259, %258
>  %261 = fmul float %181, %225
>  %262 = fadd float %260, %261
>  %263 = fmul float %179, %255
>  %264 = fmul float %180, %256
>  %265 = fadd float %264, %263
>  %266 = fmul float %181, %257
>  %267 = fadd float %265, %266
>  %268 = fcmp uge float %262, 0.000000e+00
>  %269 = select i1 %268, float %262, float 0.000000e+00
>  %270 = fcmp uge float %267, 0.000000e+00
>  %271 = select i1 %270, float %267, float 0.000000e+00
>  %272 = call float @llvm.pow.f32(float %271, float %36)
>  %273 = call float @llvm.AMDGPU.cndlt(float %262, float 0.000000e+00, float %272)
>  %274 = fmul float 1.000000e+00, %234
>  %275 = fmul float %269, %234
>  %276 = fmul float %273, %234
>  %277 = fmul float %274, %62
>  %278 = fadd float %277, %183
>  %279 = fmul float %274, %63
>  %280 = fadd float %279, %185
>  %281 = fmul float %274, %64
>  %282 = fadd float %281, %187
>  %283 = fmul float %275, %65
>  %284 = fadd float %283, %278
>  %285 = fmul float %275, %66
>  %286 = fadd float %285, %280
>  %287 = fmul float %275, %67
>  %288 = fadd float %287, %282
>  %289 = fmul float %276, %68
>  %290 = fadd float %289, %284
>  %291 = fmul float %276, %69
>  %292 = fadd float %291, %286
>  %293 = fmul float %276, %70
>  %294 = fadd float %293, %288
>  %295 = call float @llvm.AMDIL.clamp.(float %290, float 0.000000e+00, float 1.000000e+00)
>  %296 = call float @llvm.AMDIL.clamp.(float %292, float 0.000000e+00, float 1.000000e+00)
>  %297 = call float @llvm.AMDIL.clamp.(float %294, float 0.000000e+00, float 1.000000e+00)
>  %298 = fmul float %102, %71
>  %299 = fmul float %103, %72
>  %300 = fadd float %298, %299
>  %301 = fmul float %104, %73
>  %302 = fadd float %300, %301
>  %303 = fmul float %105, %74
>  %304 = fadd float %302, %303
>  %305 = fmul float %102, %75
>  %306 = fmul float %103, %76
>  %307 = fadd float %305, %306
>  %308 = fmul float %104, %77
>  %309 = fadd float %307, %308
>  %310 = fmul float %105, %78
>  %311 = fadd float %309, %310
>  %312 = fmul float %102, %79
>  %313 = fmul float %103, %80
>  %314 = fadd float %312, %313
>  %315 = fmul float %104, %81
>  %316 = fadd float %314, %315
>  %317 = fmul float %105, %82
>  %318 = fadd float %316, %317
>  %319 = fmul float %304, %83
>  %320 = fmul float %304, %84
>  %321 = fmul float %304, %85
>  %322 = fmul float %304, %86
>  %323 = fmul float %311, %87
>  %324 = fadd float %323, %319
>  %325 = fmul float %311, %88
>  %326 = fadd float %325, %320
>  %327 = fmul float %311, %89
>  %328 = fadd float %327, %321
>  %329 = fmul float %311, %90
>  %330 = fadd float %329, %322
>  %331 = fmul float %318, %91
>  %332 = fadd float %331, %324
>  %333 = fmul float %318, %92
>  %334 = fadd float %333, %326
>  %335 = fmul float %318, %93
>  %336 = fadd float %335, %328
>  %337 = fmul float %318, %94
>  %338 = fadd float %337, %330
>  %339 = fmul float %121, %95
>  %340 = fadd float %339, %332
>  %341 = fmul float %121, %96
>  %342 = fadd float %341, %334
>  %343 = fmul float %121, %97
>  %344 = fadd float %343, %336
>  %345 = fmul float %121, %98
>  %346 = fadd float %345, %338
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %295, float %296, float %297, float %191)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %340, float %342, float %344, float %346)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %125, float %126, float %127, float %128)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %150, float %152, float %154, float %156)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820005
>04140904
>c2020130
>bf8c007f
>100c0204
>c2020134
>bf8c007f
>d2820006
>04180902
>c2020138
>bf8c007f
>d2820006
>04180903
>c202013c
>bf8c007f
>d2820007
>04180904
>100c0f07
>d2820006
>041a0b05
>c2020132
>bf8c007f
>10100204
>c2020136
>bf8c007f
>d2820008
>04200902
>c202013a
>bf8c007f
>d2820008
>04200903
>c202013e
>bf8c007f
>d2820008
>04200904
>d2820006
>041a1108
>d2060106
>02010106
>7e125b06
>10141305
>c202012d
>bf8c007f
>080c0a04
>c202012c
>bf8c007f
>081a0e04
>100a1b0d
>d2820005
>04160d06
>c202012e
>bf8c007f
>08161004
>d2820005
>0416170b
>d2060105
>02010105
>7e0a5b05
>100c0b06
>08181506
>10141307
>100e0b0d
>081a1507
>10141b0d
>d282000a
>042a190c
>10121308
>10100b0b
>08121308
>d282000a
>042a1309
>d206010a
>0201010a
>7e145b0a
>1016150c
>1018150d
>c0840704
>bf8c007f
>e00c2000
>80020d00
>c2020114
>bf8c0070
>10221a04
>c2020115
>bf8c007f
>d2820011
>0444090e
>c2020116
>bf8c007f
>d2820011
>0444090f
>c2020110
>bf8c007f
>10241a04
>c2020111
>bf8c007f
>d2820012
>0448090e
>c2020112
>bf8c007f
>d2820012
>0448090f
>10262512
>d2820013
>044e2311
>c2020118
>bf8c007f
>10281a04
>c2020119
>bf8c007f
>d2820014
>0450090e
>c202011a
>bf8c007f
>d282000e
>0450090f
>d282000d
>044e1d0e
>d206010d
>0201010d
>7e1e5b0d
>101a1f12
>1020190d
>10181f11
>d282000b
>0442170c
>10141509
>10121f0e
>d282000a
>042e1509
>d00c0004
>0201010a
>d200000a
>00121480
>7e144f0a
>c202011c
>bf8c007f
>0e141404
>7e144b0a
>100e0f0d
>d2820006
>041e0d0c
>d2820007
>041a1109
>d0080004
>02020e80
>d2000008
>0011010a
>7e0c5505
>100a0d05
>c2020140
>bf8c007f
>100a0a04
>c2020141
>bf8c007f
>d2820005
>04160c04
>100c0d06
>c2020142
>bf8c007f
>d2820005
>04160c04
>7e0c5505
>100a0d08
>d00c0004
>02010107
>d2000007
>00120e80
>100e0d07
>c0840708
>bf8c007f
>e00c2000
>80020800
>c2020122
>c2028126
>bf8c0070
>7e180205
>d282000c
>042a1804
>c2020146
>bf8c007f
>d282000c
>04300906
>c202014a
>bf8c007f
>d282000c
>04300907
>c202014e
>bf8c007f
>d282000c
>04300905
>d206080c
>0201010c
>c2020121
>c2028125
>bf8c007f
>7e1a0205
>d282000d
>04261a04
>c2020145
>bf8c007f
>d282000d
>04340906
>c2020149
>bf8c007f
>d282000d
>04340907
>c202014d
>bf8c007f
>d282000d
>04340905
>d206080d
>0201010d
>c2020120
>c2028124
>bf8c007f
>7e1c0205
>d2820008
>04221c04
>c2020144
>bf8c007f
>d2820006
>04200906
>c2020148
>bf8c007f
>d2820006
>04180907
>c202014c
>bf8c007f
>d2820005
>04180905
>d2060805
>02010105
>c202012b
>bf8c007f
>d2060806
>02010004
>f800020f
>060c0d05
>c2020155
>bf8c000f
>100a0404
>c2020154
>bf8c007f
>d2820005
>04140901
>c2020156
>bf8c007f
>d2820005
>04140903
>c2020157
>bf8c007f
>d2820005
>04140904
>c2020151
>bf8c007f
>100c0404
>c2020150
>bf8c007f
>d2820006
>04180901
>c2020152
>bf8c007f
>d2820006
>04180903
>c2020153
>bf8c007f
>d2820006
>04180904
>c202015f
>bf8c007f
>100e0c04
>c2020163
>bf8c007f
>d2820008
>041c0905
>c2020159
>bf8c007f
>100e0404
>c2020158
>bf8c007f
>d2820007
>041c0901
>c202015a
>bf8c007f
>d2820007
>041c0903
>c202015b
>bf8c007f
>d2820007
>041c0904
>c2020167
>bf8c007f
>d282000c
>04200907
>c084070c
>bf8c007f
>e00c2000
>80020800
>c202016b
>bf8c0070
>d282000c
>0430090b
>c202015e
>bf8c007f
>101a0c04
>c2020162
>bf8c007f
>d282000d
>04340905
>c2020166
>bf8c007f
>d282000d
>04340907
>c202016a
>bf8c007f
>d282000d
>0434090b
>c202015d
>bf8c007f
>101c0c04
>c2020161
>bf8c007f
>d282000e
>04380905
>c2020165
>bf8c007f
>d282000e
>04380907
>c2020169
>bf8c007f
>d282000e
>0438090b
>c202015c
>bf8c007f
>100c0c04
>c2020160
>bf8c007f
>d2820005
>04180905
>c2020164
>bf8c007f
>d2820005
>04140907
>c2020168
>bf8c007f
>d2820005
>0414090b
>f800021f
>0c0d0e05
>c0820710
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[1].xyz, TEMP[0], IN[0]
>  4: MOV TEMP[1].xyz, TEMP[1].xyzx
>  5: MOV TEMP[1].w, TEMP[0].wwww
>  6: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
>  7: MOV TEMP[0].xyz, TEMP[0].xyzx
>  8: MOV TEMP[1].xy, IN[2].xyyy
>  9: MOV TEMP[1].w, IN[2].wwww
> 10: TXP TEMP[1].w, TEMP[1], SAMP[0], 2D
> 11: MOV TEMP[0].w, TEMP[1].wwww
> 12: MOV OUT[0], TEMP[0]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %37 = fdiv float %31, %33
>  %38 = fdiv float %32, %33
>  %39 = bitcast float %37 to i32
>  %40 = bitcast float %38 to i32
>  %41 = insertelement <2 x i32> undef, i32 %39, i32 0
>  %42 = insertelement <2 x i32> %41, i32 %40, i32 1
>  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %42, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %44, %28
>  %49 = fmul float %45, %29
>  %50 = fmul float %46, %30
>  %51 = fmul float %48, 2.000000e+00
>  %52 = fmul float %49, 2.000000e+00
>  %53 = fmul float %50, 2.000000e+00
>  %54 = fmul float %47, 1.000000e+00
>  %55 = call float @llvm.AMDIL.clamp.(float %51, float 0.000000e+00, float 1.000000e+00)
>  %56 = call float @llvm.AMDIL.clamp.(float %52, float 0.000000e+00, float 1.000000e+00)
>  %57 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
>  %58 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %59 = fdiv float %34, %36
>  %60 = fdiv float %35, %36
>  %61 = bitcast float %59 to i32
>  %62 = bitcast float %60 to i32
>  %63 = insertelement <2 x i32> undef, i32 %61, i32 0
>  %64 = insertelement <2 x i32> %63, i32 %62, i32 1
>  %65 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %64, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %66 = extractelement <4 x float> %65, i32 3
>  %67 = fcmp ugt float %66, 0.000000e+00
>  %68 = sext i1 %67 to i32
>  %69 = trunc i32 %68 to i1
>  %70 = select i1 %69, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %70)
>  %71 = call i32 @llvm.SI.packf16(float %55, float %56)
>  %72 = bitcast i32 %71 to float
>  %73 = call i32 @llvm.SI.packf16(float %57, float %66)
>  %74 = bitcast i32 %73 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %72, float %74, float %72, float %74)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800800
>00430202
>bf8c0770
>d0080000
>02010102
>d2000003
>0001e4f3
>7c260680
>c80c0500
>c80d0501
>c8100700
>c8110701
>7e0a5504
>10080b03
>c8180400
>c8190401
>10060b06
>c0800304
>c0c40508
>bf8c007f
>f0800700
>00020303
>c8180100
>c8190101
>bf8c0770
>100e0d04
>d2820006
>041e0d04
>d2060806
>02010106
>c81c0000
>c81d0001
>10100f03
>d2820007
>04220f03
>d2060807
>02010107
>5e0c0d07
>c81c0200
>c81d0201
>10000f05
>d2820000
>04020f05
>d2060800
>02010100
>5e000500
>f8001c0f
>00060006
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL IN[3], GENERIC[2], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[2], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV TEMP[1].xy, IN[2].xyyy
>  5: MOV TEMP[1].w, IN[2].wwww
>  6: TXP TEMP[1], TEMP[1], SAMP[1], 2D
>  7: MUL_SAT TEMP[2], TEMP[0], IMM[0].xxxy
>  8: MUL TEMP[1].xyz, TEMP[1], TEMP[2]
>  9: MOV TEMP[1].xyz, TEMP[1].xyzx
> 10: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
> 11: MOV TEMP[1].w, TEMP[0].wwww
> 12: TXP TEMP[0], IN[3], SAMP[0], CUBE
> 13: MUL_SAT TEMP[2], TEMP[1], IMM[0].xxxy
> 14: MUL_SAT TEMP[3], TEMP[1], IMM[0].xxxy
> 15: MAD TEMP[0].xyz, TEMP[0], TEMP[2].wwww, TEMP[3]
> 16: MOV_SAT TEMP[0].xyz, TEMP[0].xyzz
> 17: MUL_SAT TEMP[1], TEMP[1], IMM[0].xxxy
> 18: MOV TEMP[0].w, TEMP[1].wwww
> 19: MOV OUT[0], TEMP[0]
> 20: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %46 = fdiv float %36, %38
>  %47 = fdiv float %37, %38
>  %48 = bitcast float %46 to i32
>  %49 = bitcast float %47 to i32
>  %50 = insertelement <2 x i32> undef, i32 %48, i32 0
>  %51 = insertelement <2 x i32> %50, i32 %49, i32 1
>  %52 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %51, <32 x i8> %29, <16 x i8> %31, i32 2)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = fmul float %53, %32
>  %58 = fmul float %54, %33
>  %59 = fmul float %55, %34
>  %60 = fmul float %56, %35
>  %61 = fdiv float %39, %41
>  %62 = fdiv float %40, %41
>  %63 = bitcast float %61 to i32
>  %64 = bitcast float %62 to i32
>  %65 = insertelement <2 x i32> undef, i32 %63, i32 0
>  %66 = insertelement <2 x i32> %65, i32 %64, i32 1
>  %67 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %66, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %68 = extractelement <4 x float> %67, i32 0
>  %69 = extractelement <4 x float> %67, i32 1
>  %70 = extractelement <4 x float> %67, i32 2
>  %71 = fmul float %57, 2.000000e+00
>  %72 = fmul float %58, 2.000000e+00
>  %73 = fmul float %59, 2.000000e+00
>  %74 = fmul float %60, 1.000000e+00
>  %75 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %76 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %73, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00)
>  %79 = fmul float %68, %75
>  %80 = fmul float %69, %76
>  %81 = fmul float %70, %77
>  %82 = fmul float %57, 2.000000e+00
>  %83 = fmul float %58, 2.000000e+00
>  %84 = fmul float %59, 2.000000e+00
>  %85 = fmul float %60, 1.000000e+00
>  %86 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %87 = call float @llvm.AMDIL.clamp.(float %83, float 0.000000e+00, float 1.000000e+00)
>  %88 = call float @llvm.AMDIL.clamp.(float %84, float 0.000000e+00, float 1.000000e+00)
>  %89 = call float @llvm.AMDIL.clamp.(float %85, float 0.000000e+00, float 1.000000e+00)
>  %90 = fdiv float %42, %45
>  %91 = fdiv float %43, %45
>  %92 = fdiv float %44, %45
>  %93 = insertelement <4 x float> undef, float %90, i32 0
>  %94 = insertelement <4 x float> %93, float %91, i32 1
>  %95 = insertelement <4 x float> %94, float %92, i32 2
>  %96 = insertelement <4 x float> %95, float 1.000000e+00, i32 3
>  %97 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %96)
>  %98 = extractelement <4 x float> %97, i32 0
>  %99 = extractelement <4 x float> %97, i32 1
>  %100 = extractelement <4 x float> %97, i32 2
>  %101 = extractelement <4 x float> %97, i32 3
>  %102 = call float @fabs(float %100)
>  %103 = fdiv float 1.000000e+00, %102
>  %104 = fmul float %98, %103
>  %105 = fadd float %104, 1.500000e+00
>  %106 = fmul float %99, %103
>  %107 = fadd float %106, 1.500000e+00
>  %108 = bitcast float %107 to i32
>  %109 = bitcast float %105 to i32
>  %110 = bitcast float %101 to i32
>  %111 = insertelement <4 x i32> undef, i32 %108, i32 0
>  %112 = insertelement <4 x i32> %111, i32 %109, i32 1
>  %113 = insertelement <4 x i32> %112, i32 %110, i32 2
>  %114 = insertelement <4 x i32> %113, i32 undef, i32 3
>  %115 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %114, <32 x i8> %21, <16 x i8> %23, i32 4)
>  %116 = extractelement <4 x float> %115, i32 0
>  %117 = extractelement <4 x float> %115, i32 1
>  %118 = extractelement <4 x float> %115, i32 2
>  %119 = fmul float %79, 2.000000e+00
>  %120 = fmul float %80, 2.000000e+00
>  %121 = fmul float %81, 2.000000e+00
>  %122 = fmul float %89, 1.000000e+00
>  %123 = call float @llvm.AMDIL.clamp.(float %119, float 0.000000e+00, float 1.000000e+00)
>  %124 = call float @llvm.AMDIL.clamp.(float %120, float 0.000000e+00, float 1.000000e+00)
>  %125 = call float @llvm.AMDIL.clamp.(float %121, float 0.000000e+00, float 1.000000e+00)
>  %126 = call float @llvm.AMDIL.clamp.(float %122, float 0.000000e+00, float 1.000000e+00)
>  %127 = fmul float %79, 2.000000e+00
>  %128 = fmul float %80, 2.000000e+00
>  %129 = fmul float %81, 2.000000e+00
>  %130 = fmul float %89, 1.000000e+00
>  %131 = call float @llvm.AMDIL.clamp.(float %127, float 0.000000e+00, float 1.000000e+00)
>  %132 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
>  %133 = call float @llvm.AMDIL.clamp.(float %129, float 0.000000e+00, float 1.000000e+00)
>  %134 = call float @llvm.AMDIL.clamp.(float %130, float 0.000000e+00, float 1.000000e+00)
>  %135 = fmul float %116, %126
>  %136 = fadd float %135, %131
>  %137 = fmul float %117, %126
>  %138 = fadd float %137, %132
>  %139 = fmul float %118, %126
>  %140 = fadd float %139, %133
>  %141 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
>  %142 = call float @llvm.AMDIL.clamp.(float %138, float 0.000000e+00, float 1.000000e+00)
>  %143 = call float @llvm.AMDIL.clamp.(float %140, float 0.000000e+00, float 1.000000e+00)
>  %144 = fmul float %79, 2.000000e+00
>  %145 = fmul float %80, 2.000000e+00
>  %146 = fmul float %81, 2.000000e+00
>  %147 = fmul float %89, 1.000000e+00
>  %148 = call float @llvm.AMDIL.clamp.(float %144, float 0.000000e+00, float 1.000000e+00)
>  %149 = call float @llvm.AMDIL.clamp.(float %145, float 0.000000e+00, float 1.000000e+00)
>  %150 = call float @llvm.AMDIL.clamp.(float %146, float 0.000000e+00, float 1.000000e+00)
>  %151 = call float @llvm.AMDIL.clamp.(float %147, float 0.000000e+00, float 1.000000e+00)
>  %152 = call i32 @llvm.SI.packf16(float %141, float %142)
>  %153 = bitcast i32 %152 to float
>  %154 = call i32 @llvm.SI.packf16(float %143, float %151)
>  %155 = bitcast i32 %154 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %153, float %155, float %153, float %155)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080d00
>c8090d01
>c80c0f00
>c80d0f01
>7e0c5503
>10060d02
>c81c0c00
>c81d0c01
>10040d07
>c81c0e00
>c81d0e01
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430207
>c8140500
>c8150501
>c8180700
>c8190701
>7e0e5506
>100c0f05
>c8200400
>c8210401
>100a0f08
>c0840308
>c0c60510
>bf8c0070
>f0800f00
>00430505
>c8240100
>c8250101
>bf8c0770
>10141306
>d2820009
>042a1306
>d206080c
>02010109
>c8240900
>c8250901
>c8280b00
>c8290b01
>7e16550a
>10141709
>c8340800
>c8350801
>1012170d
>c0800304
>c0c40508
>bf8c007f
>f0800700
>00020909
>bf8c0770
>101a190a
>d282000c
>0436190a
>d206080d
>0201010c
>c8300300
>c8310301
>10181908
>d206080c
>0201010c
>d206080c
>0201010c
>d282000d
>04361903
>d206080d
>0201010d
>c8380000
>c8390001
>101e1d05
>d282000e
>043e1d05
>d206080e
>0201010e
>101e1d09
>d282000e
>043e1d09
>d206080e
>0201010e
>d282000e
>043a1902
>d206080e
>0201010e
>5e1a1b0e
>c8380200
>c8390201
>10001d07
>d2820000
>04021d07
>d2060800
>02010100
>1002010b
>d2820000
>0406010b
>d2060800
>02010100
>d2820000
>04021904
>d2060800
>02010100
>5e001900
>f8001c0f
>000d000d
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..22]
>DCL TEMP[0..4]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MOV OUT[2], IN[3]
> 15: MUL TEMP[1], IN[4].xxxx, CONST[11]
> 16: MAD TEMP[1], IN[4].yyyy, CONST[12], TEMP[1]
> 17: MAD TEMP[1], IN[4].zzzz, CONST[13], TEMP[1]
> 18: MAD OUT[3], IN[4].wwww, CONST[14], TEMP[1]
> 19: MUL TEMP[2], IN[0].xxxx, CONST[15]
> 20: MAD TEMP[2], IN[0].yyyy, CONST[16], TEMP[2]
> 21: MAD TEMP[2], IN[0].zzzz, CONST[17], TEMP[2]
> 22: MAD TEMP[2], IN[0].wwww, CONST[18], TEMP[2]
> 23: DP3 TEMP[4].x, TEMP[2], TEMP[2]
> 24: RSQ TEMP[4].x, |TEMP[4]|
> 25: MUL TEMP[3], TEMP[2], TEMP[4].xxxx
> 26: DP3 TEMP[4], TEMP[0], TEMP[3]
> 27: ADD TEMP[4], TEMP[4], TEMP[4]
> 28: MAD TEMP[1].xyz, -TEMP[4], TEMP[0], TEMP[3]
> 29: MOV TEMP[1].w, IN[5]
> 30: MUL TEMP[4], TEMP[1].xxxx, CONST[19]
> 31: MAD TEMP[4], TEMP[1].yyyy, CONST[20], TEMP[4]
> 32: MAD TEMP[4], TEMP[1].zzzz, CONST[21], TEMP[4]
> 33: MAD OUT[4], TEMP[1].wwww, CONST[22], TEMP[4]
> 34: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %87 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
>  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %5)
>  %90 = extractelement <4 x float> %89, i32 0
>  %91 = extractelement <4 x float> %89, i32 1
>  %92 = extractelement <4 x float> %89, i32 2
>  %93 = extractelement <4 x float> %89, i32 3
>  %94 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %95 = load <16 x i8> addrspace(2)* %94, !tbaa !0
>  %96 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %95, i32 0, i32 %5)
>  %97 = extractelement <4 x float> %96, i32 0
>  %98 = extractelement <4 x float> %96, i32 1
>  %99 = extractelement <4 x float> %96, i32 2
>  %100 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %101 = load <16 x i8> addrspace(2)* %100, !tbaa !0
>  %102 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %101, i32 0, i32 %5)
>  %103 = extractelement <4 x float> %102, i32 0
>  %104 = extractelement <4 x float> %102, i32 1
>  %105 = extractelement <4 x float> %102, i32 2
>  %106 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %107 = load <16 x i8> addrspace(2)* %106, !tbaa !0
>  %108 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %107, i32 0, i32 %5)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = extractelement <4 x float> %108, i32 1
>  %111 = extractelement <4 x float> %108, i32 2
>  %112 = extractelement <4 x float> %108, i32 3
>  %113 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %114 = load <16 x i8> addrspace(2)* %113, !tbaa !0
>  %115 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %114, i32 0, i32 %5)
>  %116 = extractelement <4 x float> %115, i32 0
>  %117 = extractelement <4 x float> %115, i32 1
>  %118 = extractelement <4 x float> %115, i32 2
>  %119 = extractelement <4 x float> %115, i32 3
>  %120 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
>  %122 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %121, i32 0, i32 %5)
>  %123 = extractelement <4 x float> %122, i32 3
>  %124 = fmul float %90, %11
>  %125 = fmul float %90, %12
>  %126 = fmul float %90, %13
>  %127 = fmul float %90, %14
>  %128 = fmul float %91, %15
>  %129 = fadd float %128, %124
>  %130 = fmul float %91, %16
>  %131 = fadd float %130, %125
>  %132 = fmul float %91, %17
>  %133 = fadd float %132, %126
>  %134 = fmul float %91, %18
>  %135 = fadd float %134, %127
>  %136 = fmul float %92, %19
>  %137 = fadd float %136, %129
>  %138 = fmul float %92, %20
>  %139 = fadd float %138, %131
>  %140 = fmul float %92, %21
>  %141 = fadd float %140, %133
>  %142 = fmul float %92, %22
>  %143 = fadd float %142, %135
>  %144 = fmul float %93, %23
>  %145 = fadd float %144, %137
>  %146 = fmul float %93, %24
>  %147 = fadd float %146, %139
>  %148 = fmul float %93, %25
>  %149 = fadd float %148, %141
>  %150 = fmul float %93, %26
>  %151 = fadd float %150, %143
>  %152 = fmul float %97, %27
>  %153 = fmul float %98, %28
>  %154 = fadd float %153, %152
>  %155 = fmul float %99, %29
>  %156 = fadd float %154, %155
>  %157 = fmul float %97, %30
>  %158 = fmul float %98, %31
>  %159 = fadd float %158, %157
>  %160 = fmul float %99, %32
>  %161 = fadd float %159, %160
>  %162 = fmul float %97, %33
>  %163 = fmul float %98, %34
>  %164 = fadd float %163, %162
>  %165 = fmul float %99, %35
>  %166 = fadd float %164, %165
>  %167 = fmul float %156, %156
>  %168 = fmul float %161, %161
>  %169 = fadd float %168, %167
>  %170 = fmul float %166, %166
>  %171 = fadd float %169, %170
>  %172 = call float @fabs(float %171)
>  %173 = call float @llvm.AMDGPU.rsq(float %172)
>  %174 = fmul float %156, %173
>  %175 = fmul float %161, %173
>  %176 = fmul float %166, %173
>  %177 = fmul float %36, %39
>  %178 = fadd float %177, %103
>  %179 = fmul float %37, %40
>  %180 = fadd float %179, %104
>  %181 = fmul float %38, %41
>  %182 = fadd float %181, %105
>  %183 = call float @llvm.AMDIL.clamp.(float %178, float 0.000000e+00, float 1.000000e+00)
>  %184 = call float @llvm.AMDIL.clamp.(float %180, float 0.000000e+00, float 1.000000e+00)
>  %185 = call float @llvm.AMDIL.clamp.(float %182, float 0.000000e+00, float 1.000000e+00)
>  %186 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %187 = fmul float %116, %43
>  %188 = fmul float %116, %44
>  %189 = fmul float %116, %45
>  %190 = fmul float %116, %46
>  %191 = fmul float %117, %47
>  %192 = fadd float %191, %187
>  %193 = fmul float %117, %48
>  %194 = fadd float %193, %188
>  %195 = fmul float %117, %49
>  %196 = fadd float %195, %189
>  %197 = fmul float %117, %50
>  %198 = fadd float %197, %190
>  %199 = fmul float %118, %51
>  %200 = fadd float %199, %192
>  %201 = fmul float %118, %52
>  %202 = fadd float %201, %194
>  %203 = fmul float %118, %53
>  %204 = fadd float %203, %196
>  %205 = fmul float %118, %54
>  %206 = fadd float %205, %198
>  %207 = fmul float %119, %55
>  %208 = fadd float %207, %200
>  %209 = fmul float %119, %56
>  %210 = fadd float %209, %202
>  %211 = fmul float %119, %57
>  %212 = fadd float %211, %204
>  %213 = fmul float %119, %58
>  %214 = fadd float %213, %206
>  %215 = fmul float %90, %59
>  %216 = fmul float %90, %60
>  %217 = fmul float %90, %61
>  %218 = fmul float %91, %62
>  %219 = fadd float %218, %215
>  %220 = fmul float %91, %63
>  %221 = fadd float %220, %216
>  %222 = fmul float %91, %64
>  %223 = fadd float %222, %217
>  %224 = fmul float %92, %65
>  %225 = fadd float %224, %219
>  %226 = fmul float %92, %66
>  %227 = fadd float %226, %221
>  %228 = fmul float %92, %67
>  %229 = fadd float %228, %223
>  %230 = fmul float %93, %68
>  %231 = fadd float %230, %225
>  %232 = fmul float %93, %69
>  %233 = fadd float %232, %227
>  %234 = fmul float %93, %70
>  %235 = fadd float %234, %229
>  %236 = fmul float %231, %231
>  %237 = fmul float %233, %233
>  %238 = fadd float %237, %236
>  %239 = fmul float %235, %235
>  %240 = fadd float %238, %239
>  %241 = call float @fabs(float %240)
>  %242 = call float @llvm.AMDGPU.rsq(float %241)
>  %243 = fmul float %231, %242
>  %244 = fmul float %233, %242
>  %245 = fmul float %235, %242
>  %246 = fmul float %174, %243
>  %247 = fmul float %175, %244
>  %248 = fadd float %247, %246
>  %249 = fmul float %176, %245
>  %250 = fadd float %248, %249
>  %251 = fadd float %250, %250
>  %252 = fadd float %250, %250
>  %253 = fadd float %250, %250
>  %254 = fsub float -0.000000e+00, %251
>  %255 = fmul float %254, %174
>  %256 = fadd float %255, %243
>  %257 = fsub float -0.000000e+00, %252
>  %258 = fmul float %257, %175
>  %259 = fadd float %258, %244
>  %260 = fsub float -0.000000e+00, %253
>  %261 = fmul float %260, %176
>  %262 = fadd float %261, %245
>  %263 = fmul float %256, %71
>  %264 = fmul float %256, %72
>  %265 = fmul float %256, %73
>  %266 = fmul float %256, %74
>  %267 = fmul float %259, %75
>  %268 = fadd float %267, %263
>  %269 = fmul float %259, %76
>  %270 = fadd float %269, %264
>  %271 = fmul float %259, %77
>  %272 = fadd float %271, %265
>  %273 = fmul float %259, %78
>  %274 = fadd float %273, %266
>  %275 = fmul float %262, %79
>  %276 = fadd float %275, %268
>  %277 = fmul float %262, %80
>  %278 = fadd float %277, %270
>  %279 = fmul float %262, %81
>  %280 = fadd float %279, %272
>  %281 = fmul float %262, %82
>  %282 = fadd float %281, %274
>  %283 = fmul float %123, %83
>  %284 = fadd float %283, %276
>  %285 = fmul float %123, %84
>  %286 = fadd float %285, %278
>  %287 = fmul float %123, %85
>  %288 = fadd float %287, %280
>  %289 = fmul float %123, %86
>  %290 = fadd float %289, %282
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %183, float %184, float %185, float %186)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %109, float %110, float %111, float %112)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %208, float %210, float %212, float %214)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %284, float %286, float %288, float %290)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %145, float %147, float %149, float %151)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0840710
>bf8c000f
>e00c2000
>80020100
>c202012f
>bf8c0070
>100a0204
>c2020133
>bf8c007f
>d2820005
>04140902
>c2020137
>bf8c007f
>d2820005
>04140903
>c202013b
>bf8c007f
>d2820005
>04140904
>c202012e
>bf8c007f
>100c0204
>c2020132
>bf8c007f
>d2820006
>04180902
>c2020136
>bf8c007f
>d2820006
>04180903
>c202013a
>bf8c007f
>d2820006
>04180904
>c202012d
>bf8c007f
>100e0204
>c2020131
>bf8c007f
>d2820007
>041c0902
>c2020135
>bf8c007f
>d2820007
>041c0903
>c2020139
>bf8c007f
>d2820007
>041c0904
>c202012c
>bf8c007f
>10100204
>c2020130
>bf8c007f
>d2820008
>04200902
>c2020134
>bf8c007f
>d2820008
>04200903
>c2020138
>bf8c007f
>d2820001
>04200904
>f800022f
>05060701
>c0840704
>bf8c000f
>e00c2000
>80020100
>c2020114
>bf8c0070
>100a0204
>c2020115
>bf8c007f
>d2820005
>04140902
>c2020116
>bf8c007f
>d2820005
>04140903
>c2020110
>bf8c007f
>100c0204
>c2020111
>bf8c007f
>d2820006
>04180902
>c2020112
>bf8c007f
>d2820006
>04180903
>100e0d06
>d2820008
>041e0b05
>c2020118
>bf8c007f
>100e0204
>c2020119
>bf8c007f
>d2820007
>041c0902
>c202011a
>bf8c007f
>d2820007
>041c0903
>d2820001
>04220f07
>d2060101
>02010101
>7e105b01
>100c1106
>c0840700
>bf8c007f
>e00c2000
>80020100
>c202013d
>bf8c0070
>10120204
>c2020141
>bf8c007f
>d2820009
>04240902
>c2020145
>bf8c007f
>d2820009
>04240903
>c2020149
>bf8c007f
>d2820009
>04240904
>c202013c
>bf8c007f
>10140204
>c2020140
>bf8c007f
>d282000a
>04280902
>c2020144
>bf8c007f
>d282000a
>04280903
>c2020148
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c202013e
>bf8c007f
>10160204
>c2020142
>bf8c007f
>d282000b
>042c0902
>c2020146
>bf8c007f
>d282000b
>042c0903
>c202014a
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101c1506
>100a1105
>101a1909
>d2820009
>043a1b05
>100e1107
>1010190b
>d2820009
>04261107
>06121309
>100a0b09
>080a0b0d
>100c0d09
>080c0d0a
>c202014f
>bf8c007f
>10140c04
>c2020153
>bf8c007f
>d282000a
>04280905
>100e0f09
>080e0f08
>c2020157
>bf8c007f
>d282000c
>04280907
>c0820714
>bf8c007f
>e00c2000
>80010800
>c202015b
>bf8c0070
>d2820000
>0430090b
>c202014e
>bf8c007f
>10180c04
>c2020152
>bf8c007f
>d282000c
>04300905
>c2020156
>bf8c007f
>d282000c
>04300907
>c202015a
>bf8c007f
>d282000c
>0430090b
>c202014d
>bf8c007f
>101a0c04
>c2020151
>bf8c007f
>d282000d
>04340905
>c2020155
>bf8c007f
>d282000d
>04340907
>c2020159
>bf8c007f
>d282000d
>0434090b
>c202014c
>bf8c007f
>100c0c04
>c2020150
>bf8c007f
>d2820005
>04180905
>c2020154
>bf8c007f
>d2820005
>04140907
>c2020158
>bf8c007f
>d2820005
>0414090b
>f800023f
>000c0d05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..10]
>DCL TEMP[0..3]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MOV OUT[2], IN[3]
> 15: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %57 = load <16 x i8> addrspace(2)* %56, !tbaa !0
>  %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %57, i32 0, i32 %5)
>  %59 = extractelement <4 x float> %58, i32 0
>  %60 = extractelement <4 x float> %58, i32 1
>  %61 = extractelement <4 x float> %58, i32 2
>  %62 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %63 = load <16 x i8> addrspace(2)* %62, !tbaa !0
>  %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %63, i32 0, i32 %5)
>  %65 = extractelement <4 x float> %64, i32 0
>  %66 = extractelement <4 x float> %64, i32 1
>  %67 = extractelement <4 x float> %64, i32 2
>  %68 = extractelement <4 x float> %64, i32 3
>  %69 = fmul float %46, %11
>  %70 = fmul float %46, %12
>  %71 = fmul float %46, %13
>  %72 = fmul float %46, %14
>  %73 = fmul float %47, %15
>  %74 = fadd float %73, %69
>  %75 = fmul float %47, %16
>  %76 = fadd float %75, %70
>  %77 = fmul float %47, %17
>  %78 = fadd float %77, %71
>  %79 = fmul float %47, %18
>  %80 = fadd float %79, %72
>  %81 = fmul float %48, %19
>  %82 = fadd float %81, %74
>  %83 = fmul float %48, %20
>  %84 = fadd float %83, %76
>  %85 = fmul float %48, %21
>  %86 = fadd float %85, %78
>  %87 = fmul float %48, %22
>  %88 = fadd float %87, %80
>  %89 = fmul float %49, %23
>  %90 = fadd float %89, %82
>  %91 = fmul float %49, %24
>  %92 = fadd float %91, %84
>  %93 = fmul float %49, %25
>  %94 = fadd float %93, %86
>  %95 = fmul float %49, %26
>  %96 = fadd float %95, %88
>  %97 = fmul float %53, %27
>  %98 = fmul float %54, %28
>  %99 = fadd float %98, %97
>  %100 = fmul float %55, %29
>  %101 = fadd float %99, %100
>  %102 = fmul float %53, %30
>  %103 = fmul float %54, %31
>  %104 = fadd float %103, %102
>  %105 = fmul float %55, %32
>  %106 = fadd float %104, %105
>  %107 = fmul float %53, %33
>  %108 = fmul float %54, %34
>  %109 = fadd float %108, %107
>  %110 = fmul float %55, %35
>  %111 = fadd float %109, %110
>  %112 = fmul float %101, %101
>  %113 = fmul float %106, %106
>  %114 = fadd float %113, %112
>  %115 = fmul float %111, %111
>  %116 = fadd float %114, %115
>  %117 = call float @fabs(float %116)
>  %118 = call float @llvm.AMDGPU.rsq(float %117)
>  %119 = fmul float %36, %39
>  %120 = fadd float %119, %59
>  %121 = fmul float %37, %40
>  %122 = fadd float %121, %60
>  %123 = fmul float %38, %41
>  %124 = fadd float %123, %61
>  %125 = call float @llvm.AMDIL.clamp.(float %120, float 0.000000e+00, float 1.000000e+00)
>  %126 = call float @llvm.AMDIL.clamp.(float %122, float 0.000000e+00, float 1.000000e+00)
>  %127 = call float @llvm.AMDIL.clamp.(float %124, float 0.000000e+00, float 1.000000e+00)
>  %128 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %125, float %126, float %127, float %128)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %65, float %66, float %67, float %68)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %90, float %92, float %94, float %96)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV TEMP[1].xy, IN[2].xyyy
>  5: MOV TEMP[1].w, IN[2].wwww
>  6: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  7: MUL_SAT TEMP[2], TEMP[0], IMM[0].xxxy
>  8: MUL_SAT TEMP[3], TEMP[0], IMM[0].xxxy
>  9: MAD TEMP[1].xyz, TEMP[1], TEMP[2].wwww, TEMP[3]
> 10: MOV_SAT TEMP[1].xyz, TEMP[1].xyzz
> 11: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
> 12: MOV TEMP[1].w, TEMP[0].wwww
> 13: MOV OUT[0], TEMP[1]
> 14: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %38 = fdiv float %32, %34
>  %39 = fdiv float %33, %34
>  %40 = bitcast float %38 to i32
>  %41 = bitcast float %39 to i32
>  %42 = insertelement <2 x i32> undef, i32 %40, i32 0
>  %43 = insertelement <2 x i32> %42, i32 %41, i32 1
>  %44 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %43, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = extractelement <4 x float> %44, i32 1
>  %47 = extractelement <4 x float> %44, i32 2
>  %48 = extractelement <4 x float> %44, i32 3
>  %49 = fmul float %45, %28
>  %50 = fmul float %46, %29
>  %51 = fmul float %47, %30
>  %52 = fmul float %48, %31
>  %53 = fdiv float %35, %37
>  %54 = fdiv float %36, %37
>  %55 = bitcast float %53 to i32
>  %56 = bitcast float %54 to i32
>  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
>  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
>  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = fmul float %49, 2.000000e+00
>  %64 = fmul float %50, 2.000000e+00
>  %65 = fmul float %51, 2.000000e+00
>  %66 = fmul float %52, 1.000000e+00
>  %67 = call float @llvm.AMDIL.clamp.(float %63, float 0.000000e+00, float 1.000000e+00)
>  %68 = call float @llvm.AMDIL.clamp.(float %64, float 0.000000e+00, float 1.000000e+00)
>  %69 = call float @llvm.AMDIL.clamp.(float %65, float 0.000000e+00, float 1.000000e+00)
>  %70 = call float @llvm.AMDIL.clamp.(float %66, float 0.000000e+00, float 1.000000e+00)
>  %71 = fmul float %49, 2.000000e+00
>  %72 = fmul float %50, 2.000000e+00
>  %73 = fmul float %51, 2.000000e+00
>  %74 = fmul float %52, 1.000000e+00
>  %75 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %76 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %73, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00)
>  %79 = fmul float %60, %70
>  %80 = fadd float %79, %75
>  %81 = fmul float %61, %70
>  %82 = fadd float %81, %76
>  %83 = fmul float %62, %70
>  %84 = fadd float %83, %77
>  %85 = call float @llvm.AMDIL.clamp.(float %80, float 0.000000e+00, float 1.000000e+00)
>  %86 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %87 = call float @llvm.AMDIL.clamp.(float %84, float 0.000000e+00, float 1.000000e+00)
>  %88 = fmul float %49, 2.000000e+00
>  %89 = fmul float %50, 2.000000e+00
>  %90 = fmul float %51, 2.000000e+00
>  %91 = fmul float %52, 1.000000e+00
>  %92 = call float @llvm.AMDIL.clamp.(float %88, float 0.000000e+00, float 1.000000e+00)
>  %93 = call float @llvm.AMDIL.clamp.(float %89, float 0.000000e+00, float 1.000000e+00)
>  %94 = call float @llvm.AMDIL.clamp.(float %90, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %91, float 0.000000e+00, float 1.000000e+00)
>  %96 = call i32 @llvm.SI.packf16(float %85, float %86)
>  %97 = bitcast i32 %96 to float
>  %98 = call i32 @llvm.SI.packf16(float %87, float %95)
>  %99 = bitcast i32 %98 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %97, float %99, float %97, float %99)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180100
>c8190101
>bf8c0770
>100e0d03
>d2820006
>041e0d03
>d2060809
>02010106
>c8180900
>c8190901
>c81c0b00
>c81d0b01
>7e105507
>100e1106
>c8280800
>c8290801
>100c110a
>c0800300
>c0c40500
>bf8c007f
>f0800700
>00020606
>c8280300
>c8290301
>10141505
>d206080a
>0201010a
>bf8c0770
>d2820009
>04261507
>d2060809
>02010109
>c82c0000
>c82d0001
>10181702
>d282000b
>04321702
>d206080b
>0201010b
>d282000b
>042e1506
>d206080b
>0201010b
>5e12130b
>c82c0200
>c82d0201
>10001704
>d2820000
>04021704
>d2060800
>02010100
>d2820000
>04021508
>d2060800
>02010100
>5e001500
>f8001c0f
>00090009
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..33]
>DCL TEMP[0..10]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD TEMP[3], TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: SUB TEMP[5], CONST[28], TEMP[4]
> 78: DP3 TEMP[7], TEMP[5], TEMP[5]
> 79: RSQ TEMP[7], |TEMP[7]|
> 80: MUL TEMP[5], TEMP[5], TEMP[7]
> 81: DP3 TEMP[8], -TEMP[5], CONST[30]
> 82: SLT TEMP[9], CONST[30].wwww, TEMP[8]
> 83: POW TEMP[8], TEMP[8], CONST[29].wwww
> 84: MUL TEMP[10], TEMP[9], TEMP[8]
> 85: RCP TEMP[7].yz, TEMP[7]
> 86: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 87: DP3 TEMP[7], CONST[29], TEMP[7]
> 88: RCP TEMP[7], TEMP[7]
> 89: MUL TEMP[10], TEMP[7], TEMP[10]
> 90: SUB TEMP[7], TEMP[5], TEMP[6]
> 91: DP3 TEMP[8].x, TEMP[7], TEMP[7]
> 92: RSQ TEMP[8].x, |TEMP[8]|
> 93: MUL TEMP[7], TEMP[7], TEMP[8].xxxx
> 94: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 95: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 96: LIT TEMP[1], TEMP[2]
> 97: MUL TEMP[1], TEMP[1], TEMP[10]
> 98: MAD TEMP[3], TEMP[1].xxxx, CONST[31], TEMP[3]
> 99: MAD TEMP[3], TEMP[1].yyyy, CONST[32], TEMP[3]
>100: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[33], TEMP[3]
>101: MOV OUT[2], IN[2]
>102: MOV OUT[3], IN[3]
>103: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 476)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 492)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %113 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %115 = call float @llvm.SI.load.const(<16 x i8> %10, i32 528)
>  %116 = call float @llvm.SI.load.const(<16 x i8> %10, i32 532)
>  %117 = call float @llvm.SI.load.const(<16 x i8> %10, i32 536)
>  %118 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %119 = load <16 x i8> addrspace(2)* %118, !tbaa !0
>  %120 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %119, i32 0, i32 %5)
>  %121 = extractelement <4 x float> %120, i32 0
>  %122 = extractelement <4 x float> %120, i32 1
>  %123 = extractelement <4 x float> %120, i32 2
>  %124 = extractelement <4 x float> %120, i32 3
>  %125 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %126 = load <16 x i8> addrspace(2)* %125, !tbaa !0
>  %127 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %126, i32 0, i32 %5)
>  %128 = extractelement <4 x float> %127, i32 0
>  %129 = extractelement <4 x float> %127, i32 1
>  %130 = extractelement <4 x float> %127, i32 2
>  %131 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %132 = load <16 x i8> addrspace(2)* %131, !tbaa !0
>  %133 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %132, i32 0, i32 %5)
>  %134 = extractelement <4 x float> %133, i32 0
>  %135 = extractelement <4 x float> %133, i32 1
>  %136 = extractelement <4 x float> %133, i32 2
>  %137 = extractelement <4 x float> %133, i32 3
>  %138 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %139 = load <16 x i8> addrspace(2)* %138, !tbaa !0
>  %140 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %139, i32 0, i32 %5)
>  %141 = extractelement <4 x float> %140, i32 0
>  %142 = extractelement <4 x float> %140, i32 1
>  %143 = extractelement <4 x float> %140, i32 2
>  %144 = extractelement <4 x float> %140, i32 3
>  %145 = fmul float %121, %11
>  %146 = fmul float %121, %12
>  %147 = fmul float %121, %13
>  %148 = fmul float %121, %14
>  %149 = fmul float %122, %15
>  %150 = fadd float %149, %145
>  %151 = fmul float %122, %16
>  %152 = fadd float %151, %146
>  %153 = fmul float %122, %17
>  %154 = fadd float %153, %147
>  %155 = fmul float %122, %18
>  %156 = fadd float %155, %148
>  %157 = fmul float %123, %19
>  %158 = fadd float %157, %150
>  %159 = fmul float %123, %20
>  %160 = fadd float %159, %152
>  %161 = fmul float %123, %21
>  %162 = fadd float %161, %154
>  %163 = fmul float %123, %22
>  %164 = fadd float %163, %156
>  %165 = fmul float %124, %23
>  %166 = fadd float %165, %158
>  %167 = fmul float %124, %24
>  %168 = fadd float %167, %160
>  %169 = fmul float %124, %25
>  %170 = fadd float %169, %162
>  %171 = fmul float %124, %26
>  %172 = fadd float %171, %164
>  %173 = fmul float %128, %27
>  %174 = fmul float %129, %28
>  %175 = fadd float %174, %173
>  %176 = fmul float %130, %29
>  %177 = fadd float %175, %176
>  %178 = fmul float %128, %30
>  %179 = fmul float %129, %31
>  %180 = fadd float %179, %178
>  %181 = fmul float %130, %32
>  %182 = fadd float %180, %181
>  %183 = fmul float %128, %33
>  %184 = fmul float %129, %34
>  %185 = fadd float %184, %183
>  %186 = fmul float %130, %35
>  %187 = fadd float %185, %186
>  %188 = fmul float %177, %177
>  %189 = fmul float %182, %182
>  %190 = fadd float %189, %188
>  %191 = fmul float %187, %187
>  %192 = fadd float %190, %191
>  %193 = call float @fabs(float %192)
>  %194 = call float @llvm.AMDGPU.rsq(float %193)
>  %195 = fmul float %177, %194
>  %196 = fmul float %182, %194
>  %197 = fmul float %187, %194
>  %198 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %199 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %200 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %201 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %202 = fmul float %121, %44
>  %203 = fmul float %121, %45
>  %204 = fmul float %121, %46
>  %205 = fmul float %122, %47
>  %206 = fadd float %205, %202
>  %207 = fmul float %122, %48
>  %208 = fadd float %207, %203
>  %209 = fmul float %122, %49
>  %210 = fadd float %209, %204
>  %211 = fmul float %123, %50
>  %212 = fadd float %211, %206
>  %213 = fmul float %123, %51
>  %214 = fadd float %213, %208
>  %215 = fmul float %123, %52
>  %216 = fadd float %215, %210
>  %217 = fmul float %124, %53
>  %218 = fadd float %217, %212
>  %219 = fmul float %124, %54
>  %220 = fadd float %219, %214
>  %221 = fmul float %124, %55
>  %222 = fadd float %221, %216
>  %223 = fsub float %41, %218
>  %224 = fsub float %42, %220
>  %225 = fsub float %43, %222
>  %226 = fmul float %223, %223
>  %227 = fmul float %224, %224
>  %228 = fadd float %227, %226
>  %229 = fmul float %225, %225
>  %230 = fadd float %228, %229
>  %231 = call float @fabs(float %230)
>  %232 = call float @llvm.AMDGPU.rsq(float %231)
>  %233 = fmul float %223, %232
>  %234 = fmul float %224, %232
>  %235 = fmul float %225, %232
>  %236 = fdiv float 1.000000e+00, %232
>  %237 = fmul float %232, %236
>  %238 = fmul float %236, %236
>  %239 = fmul float %56, %237
>  %240 = fmul float %57, %236
>  %241 = fadd float %240, %239
>  %242 = fmul float %58, %238
>  %243 = fadd float %241, %242
>  %244 = fdiv float 1.000000e+00, %243
>  %245 = fmul float %218, %218
>  %246 = fmul float %220, %220
>  %247 = fadd float %246, %245
>  %248 = fmul float %222, %222
>  %249 = fadd float %247, %248
>  %250 = call float @fabs(float %249)
>  %251 = call float @llvm.AMDGPU.rsq(float %250)
>  %252 = fmul float %218, %251
>  %253 = fmul float %220, %251
>  %254 = fmul float %222, %251
>  %255 = fsub float %233, %252
>  %256 = fsub float %234, %253
>  %257 = fsub float %235, %254
>  %258 = fmul float %255, %255
>  %259 = fmul float %256, %256
>  %260 = fadd float %259, %258
>  %261 = fmul float %257, %257
>  %262 = fadd float %260, %261
>  %263 = call float @fabs(float %262)
>  %264 = call float @llvm.AMDGPU.rsq(float %263)
>  %265 = fmul float %255, %264
>  %266 = fmul float %256, %264
>  %267 = fmul float %257, %264
>  %268 = fmul float %195, %233
>  %269 = fmul float %196, %234
>  %270 = fadd float %269, %268
>  %271 = fmul float %197, %235
>  %272 = fadd float %270, %271
>  %273 = fmul float %195, %265
>  %274 = fmul float %196, %266
>  %275 = fadd float %274, %273
>  %276 = fmul float %197, %267
>  %277 = fadd float %275, %276
>  %278 = fcmp uge float %272, 0.000000e+00
>  %279 = select i1 %278, float %272, float 0.000000e+00
>  %280 = fcmp uge float %277, 0.000000e+00
>  %281 = select i1 %280, float %277, float 0.000000e+00
>  %282 = call float @llvm.pow.f32(float %281, float %36)
>  %283 = call float @llvm.AMDGPU.cndlt(float %272, float 0.000000e+00, float %282)
>  %284 = fmul float 1.000000e+00, %244
>  %285 = fmul float %279, %244
>  %286 = fmul float %283, %244
>  %287 = fmul float %284, %59
>  %288 = fadd float %287, %37
>  %289 = fmul float %284, %60
>  %290 = fadd float %289, %38
>  %291 = fmul float %284, %61
>  %292 = fadd float %291, %39
>  %293 = fmul float %285, %62
>  %294 = fadd float %293, %288
>  %295 = fmul float %285, %63
>  %296 = fadd float %295, %290
>  %297 = fmul float %285, %64
>  %298 = fadd float %297, %292
>  %299 = fmul float %286, %65
>  %300 = fadd float %299, %294
>  %301 = fmul float %286, %66
>  %302 = fadd float %301, %296
>  %303 = fmul float %286, %67
>  %304 = fadd float %303, %298
>  %305 = fsub float %68, %218
>  %306 = fsub float %69, %220
>  %307 = fsub float %70, %222
>  %308 = fmul float %305, %305
>  %309 = fmul float %306, %306
>  %310 = fadd float %309, %308
>  %311 = fmul float %307, %307
>  %312 = fadd float %310, %311
>  %313 = call float @fabs(float %312)
>  %314 = call float @llvm.AMDGPU.rsq(float %313)
>  %315 = fmul float %305, %314
>  %316 = fmul float %306, %314
>  %317 = fmul float %307, %314
>  %318 = fdiv float 1.000000e+00, %314
>  %319 = fmul float %314, %318
>  %320 = fmul float %318, %318
>  %321 = fmul float %71, %319
>  %322 = fmul float %72, %318
>  %323 = fadd float %322, %321
>  %324 = fmul float %73, %320
>  %325 = fadd float %323, %324
>  %326 = fdiv float 1.000000e+00, %325
>  %327 = fsub float %315, %252
>  %328 = fsub float %316, %253
>  %329 = fsub float %317, %254
>  %330 = fmul float %327, %327
>  %331 = fmul float %328, %328
>  %332 = fadd float %331, %330
>  %333 = fmul float %329, %329
>  %334 = fadd float %332, %333
>  %335 = call float @fabs(float %334)
>  %336 = call float @llvm.AMDGPU.rsq(float %335)
>  %337 = fmul float %327, %336
>  %338 = fmul float %328, %336
>  %339 = fmul float %329, %336
>  %340 = fmul float %195, %315
>  %341 = fmul float %196, %316
>  %342 = fadd float %341, %340
>  %343 = fmul float %197, %317
>  %344 = fadd float %342, %343
>  %345 = fmul float %195, %337
>  %346 = fmul float %196, %338
>  %347 = fadd float %346, %345
>  %348 = fmul float %197, %339
>  %349 = fadd float %347, %348
>  %350 = fcmp uge float %344, 0.000000e+00
>  %351 = select i1 %350, float %344, float 0.000000e+00
>  %352 = fcmp uge float %349, 0.000000e+00
>  %353 = select i1 %352, float %349, float 0.000000e+00
>  %354 = call float @llvm.pow.f32(float %353, float %36)
>  %355 = call float @llvm.AMDGPU.cndlt(float %344, float 0.000000e+00, float %354)
>  %356 = fmul float 1.000000e+00, %326
>  %357 = fmul float %351, %326
>  %358 = fmul float %355, %326
>  %359 = fmul float %356, %74
>  %360 = fadd float %359, %300
>  %361 = fmul float %356, %75
>  %362 = fadd float %361, %302
>  %363 = fmul float %356, %76
>  %364 = fadd float %363, %304
>  %365 = fmul float %357, %77
>  %366 = fadd float %365, %360
>  %367 = fmul float %357, %78
>  %368 = fadd float %367, %362
>  %369 = fmul float %357, %79
>  %370 = fadd float %369, %364
>  %371 = fmul float %358, %80
>  %372 = fadd float %371, %366
>  %373 = fmul float %358, %81
>  %374 = fadd float %373, %368
>  %375 = fmul float %358, %82
>  %376 = fadd float %375, %370
>  %377 = fsub float %83, %218
>  %378 = fsub float %84, %220
>  %379 = fsub float %85, %222
>  %380 = fmul float %377, %377
>  %381 = fmul float %378, %378
>  %382 = fadd float %381, %380
>  %383 = fmul float %379, %379
>  %384 = fadd float %382, %383
>  %385 = call float @fabs(float %384)
>  %386 = call float @llvm.AMDGPU.rsq(float %385)
>  %387 = fmul float %377, %386
>  %388 = fmul float %378, %386
>  %389 = fmul float %379, %386
>  %390 = fdiv float 1.000000e+00, %386
>  %391 = fmul float %386, %390
>  %392 = fmul float %390, %390
>  %393 = fmul float %86, %391
>  %394 = fmul float %87, %390
>  %395 = fadd float %394, %393
>  %396 = fmul float %88, %392
>  %397 = fadd float %395, %396
>  %398 = fdiv float 1.000000e+00, %397
>  %399 = fsub float %387, %252
>  %400 = fsub float %388, %253
>  %401 = fsub float %389, %254
>  %402 = fmul float %399, %399
>  %403 = fmul float %400, %400
>  %404 = fadd float %403, %402
>  %405 = fmul float %401, %401
>  %406 = fadd float %404, %405
>  %407 = call float @fabs(float %406)
>  %408 = call float @llvm.AMDGPU.rsq(float %407)
>  %409 = fmul float %399, %408
>  %410 = fmul float %400, %408
>  %411 = fmul float %401, %408
>  %412 = fmul float %195, %387
>  %413 = fmul float %196, %388
>  %414 = fadd float %413, %412
>  %415 = fmul float %197, %389
>  %416 = fadd float %414, %415
>  %417 = fmul float %195, %409
>  %418 = fmul float %196, %410
>  %419 = fadd float %418, %417
>  %420 = fmul float %197, %411
>  %421 = fadd float %419, %420
>  %422 = fcmp uge float %416, 0.000000e+00
>  %423 = select i1 %422, float %416, float 0.000000e+00
>  %424 = fcmp uge float %421, 0.000000e+00
>  %425 = select i1 %424, float %421, float 0.000000e+00
>  %426 = call float @llvm.pow.f32(float %425, float %36)
>  %427 = call float @llvm.AMDGPU.cndlt(float %416, float 0.000000e+00, float %426)
>  %428 = fmul float 1.000000e+00, %398
>  %429 = fmul float %423, %398
>  %430 = fmul float %427, %398
>  %431 = fmul float %428, %89
>  %432 = fadd float %431, %372
>  %433 = fmul float %428, %90
>  %434 = fadd float %433, %374
>  %435 = fmul float %428, %91
>  %436 = fadd float %435, %376
>  %437 = fmul float %429, %92
>  %438 = fadd float %437, %432
>  %439 = fmul float %429, %93
>  %440 = fadd float %439, %434
>  %441 = fmul float %429, %94
>  %442 = fadd float %441, %436
>  %443 = fmul float %430, %95
>  %444 = fadd float %443, %438
>  %445 = fmul float %430, %96
>  %446 = fadd float %445, %440
>  %447 = fmul float %430, %97
>  %448 = fadd float %447, %442
>  %449 = fsub float %98, %218
>  %450 = fsub float %99, %220
>  %451 = fsub float %100, %222
>  %452 = fmul float %449, %449
>  %453 = fmul float %450, %450
>  %454 = fadd float %453, %452
>  %455 = fmul float %451, %451
>  %456 = fadd float %454, %455
>  %457 = call float @fabs(float %456)
>  %458 = call float @llvm.AMDGPU.rsq(float %457)
>  %459 = fmul float %449, %458
>  %460 = fmul float %450, %458
>  %461 = fmul float %451, %458
>  %462 = fsub float -0.000000e+00, %459
>  %463 = fsub float -0.000000e+00, %460
>  %464 = fsub float -0.000000e+00, %461
>  %465 = fmul float %462, %105
>  %466 = fmul float %463, %106
>  %467 = fadd float %466, %465
>  %468 = fmul float %464, %107
>  %469 = fadd float %467, %468
>  %470 = fcmp olt float %108, %469
>  %471 = select i1 %470, float 1.000000e+00, float 0.000000e+00
>  %472 = fcmp olt float %108, %469
>  %473 = select i1 %472, float 1.000000e+00, float 0.000000e+00
>  %474 = fcmp olt float %108, %469
>  %475 = select i1 %474, float 1.000000e+00, float 0.000000e+00
>  %476 = call float @llvm.pow.f32(float %469, float %104)
>  %477 = fmul float %471, %476
>  %478 = fmul float %473, %476
>  %479 = fmul float %475, %476
>  %480 = fdiv float 1.000000e+00, %458
>  %481 = fmul float %458, %480
>  %482 = fmul float %480, %480
>  %483 = fmul float %101, %481
>  %484 = fmul float %102, %480
>  %485 = fadd float %484, %483
>  %486 = fmul float %103, %482
>  %487 = fadd float %485, %486
>  %488 = fdiv float 1.000000e+00, %487
>  %489 = fmul float %488, %477
>  %490 = fmul float %488, %478
>  %491 = fmul float %488, %479
>  %492 = fsub float %459, %252
>  %493 = fsub float %460, %253
>  %494 = fsub float %461, %254
>  %495 = fmul float %492, %492
>  %496 = fmul float %493, %493
>  %497 = fadd float %496, %495
>  %498 = fmul float %494, %494
>  %499 = fadd float %497, %498
>  %500 = call float @fabs(float %499)
>  %501 = call float @llvm.AMDGPU.rsq(float %500)
>  %502 = fmul float %492, %501
>  %503 = fmul float %493, %501
>  %504 = fmul float %494, %501
>  %505 = fmul float %195, %459
>  %506 = fmul float %196, %460
>  %507 = fadd float %506, %505
>  %508 = fmul float %197, %461
>  %509 = fadd float %507, %508
>  %510 = fmul float %195, %502
>  %511 = fmul float %196, %503
>  %512 = fadd float %511, %510
>  %513 = fmul float %197, %504
>  %514 = fadd float %512, %513
>  %515 = fcmp uge float %509, 0.000000e+00
>  %516 = select i1 %515, float %509, float 0.000000e+00
>  %517 = fcmp uge float %514, 0.000000e+00
>  %518 = select i1 %517, float %514, float 0.000000e+00
>  %519 = call float @llvm.pow.f32(float %518, float %36)
>  %520 = call float @llvm.AMDGPU.cndlt(float %509, float 0.000000e+00, float %519)
>  %521 = fmul float 1.000000e+00, %489
>  %522 = fmul float %516, %490
>  %523 = fmul float %520, %491
>  %524 = fmul float %521, %109
>  %525 = fadd float %524, %444
>  %526 = fmul float %521, %110
>  %527 = fadd float %526, %446
>  %528 = fmul float %521, %111
>  %529 = fadd float %528, %448
>  %530 = fmul float %522, %112
>  %531 = fadd float %530, %525
>  %532 = fmul float %522, %113
>  %533 = fadd float %532, %527
>  %534 = fmul float %522, %114
>  %535 = fadd float %534, %529
>  %536 = fmul float %523, %115
>  %537 = fadd float %536, %531
>  %538 = fmul float %523, %116
>  %539 = fadd float %538, %533
>  %540 = fmul float %523, %117
>  %541 = fadd float %540, %535
>  %542 = call float @llvm.AMDIL.clamp.(float %537, float 0.000000e+00, float 1.000000e+00)
>  %543 = call float @llvm.AMDIL.clamp.(float %539, float 0.000000e+00, float 1.000000e+00)
>  %544 = call float @llvm.AMDIL.clamp.(float %541, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %542, float %543, float %544, float %201)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %134, float %135, float %136, float %137)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %141, float %142, float %143, float %144)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %166, float %168, float %170, float %172)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>c202814e
>bf8c007f
>d2820011
>045e2205
>7e225511
>c2028152
>bf8c007f
>d2820018
>044c0b11
>102e2d14
>10262f0e
>10322d12
>d2820012
>044e330f
>102a2d15
>d2820013
>044a2b10
>d00c0008
>02010113
>d2000012
>00222680
>10242312
>c2028156
>bf8c007f
>d2820014
>04600b12
>082c0b19
>082e0d17
>10302f17
>d2820018
>04622d16
>082a0f15
>d2820018
>04622b15
>d2060118
>02010118
>7e305b18
>102c3116
>102e3117
>102e2f0e
>d2820016
>045e2d0f
>102a3115
>d2820015
>045a2b10
>d00c0008
>02010115
>d2000015
>00222a80
>7e2a4f15
>0e2a2a04
>7e2a4b15
>d0080008
>02022680
>d2000013
>00210115
>10262313
>c202815a
>bf8c007f
>d2820016
>04500b13
>c202815d
>bf8c007f
>082a1405
>c202815c
>bf8c007f
>082e1805
>10282f17
>d2820014
>04522b15
>c202815e
>bf8c007f
>08301a05
>d2820014
>04523118
>d2060114
>02010114
>7e325b14
>7e285519
>10342919
>c2028160
>bf8c007f
>10343405
>c2028161
>bf8c007f
>d282001a
>046a2805
>10282914
>c2028162
>bf8c007f
>d2820014
>046a2805
>7e285514
>c2028166
>bf8c007f
>d282001b
>04580b14
>10343317
>102c350e
>10383315
>d2820015
>045a390f
>10303318
>d2820016
>04563110
>d00c0008
>02010116
>d2000015
>00222c80
>102a2915
>c202816a
>bf8c007f
>d2820017
>046c0b15
>08320b1c
>08340d1a
>1036351a
>d282001b
>046e3319
>08300f18
>d282001b
>046e3118
>d206011b
>0201011b
>7e365b1b
>10323719
>1034371a
>1034350e
>d2820019
>046a330f
>10303718
>d2820018
>04663110
>d00c0008
>02010118
>d2000018
>00223080
>7e304f18
>0e303004
>7e304b18
>d0080008
>02022c80
>d2000016
>00210118
>102c2916
>c202816e
>bf8c007f
>d2820017
>045c0b16
>c2028171
>bf8c007f
>08301405
>c2028170
>bf8c007f
>08321805
>10143319
>d282000a
>042a3118
>c2028172
>bf8c007f
>08181a05
>d282000a
>042a190c
>d206010a
>0201010a
>7e145b0a
>101a1519
>c2028178
>bf8c007f
>10321a05
>10301518
>d206001a
>22010118
>c2028179
>bf8c007f
>10343405
>0834331a
>1032150c
>c202817a
>bf8c007f
>10183205
>0834191a
>c202817b
>bf8c007f
>d0020008
>02023405
>d200000c
>0021e480
>7e344f1a
>c2028177
>bf8c007f
>0e343405
>7e344b1a
>1018350c
>7e34550a
>1014350a
>c2028174
>bf8c007f
>10141405
>c2028175
>bf8c007f
>d282000a
>042a3405
>1034351a
>c2028176
>bf8c007f
>d282000a
>042a3405
>7e14550a
>1014190a
>c202817e
>bf8c007f
>d282001a
>045c0b0a
>10181b0e
>d282000c
>0432310f
>d2820017
>04323310
>d00c0008
>02010117
>d200000c
>00222e80
>1018150c
>c2028182
>bf8c007f
>d282001a
>04680b0c
>080a0b18
>080c0d0d
>101a0d06
>d282000d
>04360b05
>080e0f19
>d282000d
>04360f07
>d206010d
>0201010d
>7e1a5b0d
>100a1b05
>100c1b06
>100c0d0e
>d2820005
>041a0b0f
>100c1b07
>d2820005
>04160d10
>d00c0008
>02010105
>d2000005
>00220a80
>7e0a4f05
>0e0a0a04
>7e0a4b05
>d0080004
>02022e80
>d2000005
>00110105
>100c1505
>c2020186
>bf8c007f
>d2820005
>04680906
>d2060805
>02010105
>c202013d
>c2028121
>bf8c007f
>7e0e0205
>d2820007
>041c0909
>c2020141
>bf8c007f
>d2820007
>041c090b
>c2020145
>bf8c007f
>d2820007
>041c0908
>c2020151
>bf8c007f
>d2820007
>041c0911
>c2020155
>bf8c007f
>d2820007
>041c0912
>c2020159
>bf8c007f
>d2820007
>041c0913
>c2020165
>bf8c007f
>d2820007
>041c0914
>c2020169
>bf8c007f
>d2820007
>041c0915
>c202016d
>bf8c007f
>d2820007
>041c0916
>c202017d
>bf8c007f
>d2820007
>041c090a
>c2020181
>bf8c007f
>d2820007
>041c090c
>c2020185
>bf8c007f
>d2820007
>041c0906
>d2060807
>02010107
>c202013c
>c2028120
>bf8c007f
>7e1a0205
>d2820009
>04340909
>c2020140
>bf8c007f
>d2820009
>0424090b
>c2020144
>bf8c007f
>d2820008
>04240908
>c2020150
>bf8c007f
>d2820008
>04200911
>c2020154
>bf8c007f
>d2820008
>04200912
>c2020158
>bf8c007f
>d2820008
>04200913
>c2020164
>bf8c007f
>d2820008
>04200914
>c2020168
>bf8c007f
>d2820008
>04200915
>c202016c
>bf8c007f
>d2820008
>04200916
>c202017c
>bf8c007f
>d2820008
>0420090a
>c2020180
>bf8c007f
>d2820008
>0420090c
>c2020184
>bf8c007f
>d2820006
>04200906
>d2060806
>02010106
>c2020123
>bf8c007f
>d2060808
>02010004
>f800020f
>08050706
>c0840708
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800021f
>08070605
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..32]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD TEMP[3], TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: SUB TEMP[5], CONST[28], TEMP[4]
> 78: DP3 TEMP[7], TEMP[5], TEMP[5]
> 79: RSQ TEMP[7], |TEMP[7]|
> 80: MUL TEMP[5], TEMP[5], TEMP[7]
> 81: RCP TEMP[7].yz, TEMP[7]
> 82: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 83: DP3 TEMP[7], CONST[29], TEMP[7]
> 84: RCP TEMP[8], TEMP[7]
> 85: SUB TEMP[7], TEMP[5], TEMP[6]
> 86: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 87: RSQ TEMP[9].x, |TEMP[9]|
> 88: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 89: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 90: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 91: LIT TEMP[1], TEMP[2]
> 92: MUL TEMP[1], TEMP[1], TEMP[8]
> 93: MAD TEMP[3], TEMP[1].xxxx, CONST[30], TEMP[3]
> 94: MAD TEMP[3], TEMP[1].yyyy, CONST[31], TEMP[3]
> 95: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[32], TEMP[3]
> 96: MOV OUT[2], IN[2]
> 97: MOV OUT[3], IN[3]
> 98: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %113 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %114 = load <16 x i8> addrspace(2)* %113, !tbaa !0
>  %115 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %114, i32 0, i32 %5)
>  %116 = extractelement <4 x float> %115, i32 0
>  %117 = extractelement <4 x float> %115, i32 1
>  %118 = extractelement <4 x float> %115, i32 2
>  %119 = extractelement <4 x float> %115, i32 3
>  %120 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
>  %122 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %121, i32 0, i32 %5)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = extractelement <4 x float> %122, i32 1
>  %125 = extractelement <4 x float> %122, i32 2
>  %126 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %127 = load <16 x i8> addrspace(2)* %126, !tbaa !0
>  %128 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %127, i32 0, i32 %5)
>  %129 = extractelement <4 x float> %128, i32 0
>  %130 = extractelement <4 x float> %128, i32 1
>  %131 = extractelement <4 x float> %128, i32 2
>  %132 = extractelement <4 x float> %128, i32 3
>  %133 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %134 = load <16 x i8> addrspace(2)* %133, !tbaa !0
>  %135 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %134, i32 0, i32 %5)
>  %136 = extractelement <4 x float> %135, i32 0
>  %137 = extractelement <4 x float> %135, i32 1
>  %138 = extractelement <4 x float> %135, i32 2
>  %139 = extractelement <4 x float> %135, i32 3
>  %140 = fmul float %116, %11
>  %141 = fmul float %116, %12
>  %142 = fmul float %116, %13
>  %143 = fmul float %116, %14
>  %144 = fmul float %117, %15
>  %145 = fadd float %144, %140
>  %146 = fmul float %117, %16
>  %147 = fadd float %146, %141
>  %148 = fmul float %117, %17
>  %149 = fadd float %148, %142
>  %150 = fmul float %117, %18
>  %151 = fadd float %150, %143
>  %152 = fmul float %118, %19
>  %153 = fadd float %152, %145
>  %154 = fmul float %118, %20
>  %155 = fadd float %154, %147
>  %156 = fmul float %118, %21
>  %157 = fadd float %156, %149
>  %158 = fmul float %118, %22
>  %159 = fadd float %158, %151
>  %160 = fmul float %119, %23
>  %161 = fadd float %160, %153
>  %162 = fmul float %119, %24
>  %163 = fadd float %162, %155
>  %164 = fmul float %119, %25
>  %165 = fadd float %164, %157
>  %166 = fmul float %119, %26
>  %167 = fadd float %166, %159
>  %168 = fmul float %123, %27
>  %169 = fmul float %124, %28
>  %170 = fadd float %169, %168
>  %171 = fmul float %125, %29
>  %172 = fadd float %170, %171
>  %173 = fmul float %123, %30
>  %174 = fmul float %124, %31
>  %175 = fadd float %174, %173
>  %176 = fmul float %125, %32
>  %177 = fadd float %175, %176
>  %178 = fmul float %123, %33
>  %179 = fmul float %124, %34
>  %180 = fadd float %179, %178
>  %181 = fmul float %125, %35
>  %182 = fadd float %180, %181
>  %183 = fmul float %172, %172
>  %184 = fmul float %177, %177
>  %185 = fadd float %184, %183
>  %186 = fmul float %182, %182
>  %187 = fadd float %185, %186
>  %188 = call float @fabs(float %187)
>  %189 = call float @llvm.AMDGPU.rsq(float %188)
>  %190 = fmul float %172, %189
>  %191 = fmul float %177, %189
>  %192 = fmul float %182, %189
>  %193 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %194 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %195 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %196 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %197 = fmul float %116, %44
>  %198 = fmul float %116, %45
>  %199 = fmul float %116, %46
>  %200 = fmul float %117, %47
>  %201 = fadd float %200, %197
>  %202 = fmul float %117, %48
>  %203 = fadd float %202, %198
>  %204 = fmul float %117, %49
>  %205 = fadd float %204, %199
>  %206 = fmul float %118, %50
>  %207 = fadd float %206, %201
>  %208 = fmul float %118, %51
>  %209 = fadd float %208, %203
>  %210 = fmul float %118, %52
>  %211 = fadd float %210, %205
>  %212 = fmul float %119, %53
>  %213 = fadd float %212, %207
>  %214 = fmul float %119, %54
>  %215 = fadd float %214, %209
>  %216 = fmul float %119, %55
>  %217 = fadd float %216, %211
>  %218 = fsub float %41, %213
>  %219 = fsub float %42, %215
>  %220 = fsub float %43, %217
>  %221 = fmul float %218, %218
>  %222 = fmul float %219, %219
>  %223 = fadd float %222, %221
>  %224 = fmul float %220, %220
>  %225 = fadd float %223, %224
>  %226 = call float @fabs(float %225)
>  %227 = call float @llvm.AMDGPU.rsq(float %226)
>  %228 = fmul float %218, %227
>  %229 = fmul float %219, %227
>  %230 = fmul float %220, %227
>  %231 = fdiv float 1.000000e+00, %227
>  %232 = fmul float %227, %231
>  %233 = fmul float %231, %231
>  %234 = fmul float %56, %232
>  %235 = fmul float %57, %231
>  %236 = fadd float %235, %234
>  %237 = fmul float %58, %233
>  %238 = fadd float %236, %237
>  %239 = fdiv float 1.000000e+00, %238
>  %240 = fmul float %213, %213
>  %241 = fmul float %215, %215
>  %242 = fadd float %241, %240
>  %243 = fmul float %217, %217
>  %244 = fadd float %242, %243
>  %245 = call float @fabs(float %244)
>  %246 = call float @llvm.AMDGPU.rsq(float %245)
>  %247 = fmul float %213, %246
>  %248 = fmul float %215, %246
>  %249 = fmul float %217, %246
>  %250 = fsub float %228, %247
>  %251 = fsub float %229, %248
>  %252 = fsub float %230, %249
>  %253 = fmul float %250, %250
>  %254 = fmul float %251, %251
>  %255 = fadd float %254, %253
>  %256 = fmul float %252, %252
>  %257 = fadd float %255, %256
>  %258 = call float @fabs(float %257)
>  %259 = call float @llvm.AMDGPU.rsq(float %258)
>  %260 = fmul float %250, %259
>  %261 = fmul float %251, %259
>  %262 = fmul float %252, %259
>  %263 = fmul float %190, %228
>  %264 = fmul float %191, %229
>  %265 = fadd float %264, %263
>  %266 = fmul float %192, %230
>  %267 = fadd float %265, %266
>  %268 = fmul float %190, %260
>  %269 = fmul float %191, %261
>  %270 = fadd float %269, %268
>  %271 = fmul float %192, %262
>  %272 = fadd float %270, %271
>  %273 = fcmp uge float %267, 0.000000e+00
>  %274 = select i1 %273, float %267, float 0.000000e+00
>  %275 = fcmp uge float %272, 0.000000e+00
>  %276 = select i1 %275, float %272, float 0.000000e+00
>  %277 = call float @llvm.pow.f32(float %276, float %36)
>  %278 = call float @llvm.AMDGPU.cndlt(float %267, float 0.000000e+00, float %277)
>  %279 = fmul float 1.000000e+00, %239
>  %280 = fmul float %274, %239
>  %281 = fmul float %278, %239
>  %282 = fmul float %279, %59
>  %283 = fadd float %282, %37
>  %284 = fmul float %279, %60
>  %285 = fadd float %284, %38
>  %286 = fmul float %279, %61
>  %287 = fadd float %286, %39
>  %288 = fmul float %280, %62
>  %289 = fadd float %288, %283
>  %290 = fmul float %280, %63
>  %291 = fadd float %290, %285
>  %292 = fmul float %280, %64
>  %293 = fadd float %292, %287
>  %294 = fmul float %281, %65
>  %295 = fadd float %294, %289
>  %296 = fmul float %281, %66
>  %297 = fadd float %296, %291
>  %298 = fmul float %281, %67
>  %299 = fadd float %298, %293
>  %300 = fsub float %68, %213
>  %301 = fsub float %69, %215
>  %302 = fsub float %70, %217
>  %303 = fmul float %300, %300
>  %304 = fmul float %301, %301
>  %305 = fadd float %304, %303
>  %306 = fmul float %302, %302
>  %307 = fadd float %305, %306
>  %308 = call float @fabs(float %307)
>  %309 = call float @llvm.AMDGPU.rsq(float %308)
>  %310 = fmul float %300, %309
>  %311 = fmul float %301, %309
>  %312 = fmul float %302, %309
>  %313 = fdiv float 1.000000e+00, %309
>  %314 = fmul float %309, %313
>  %315 = fmul float %313, %313
>  %316 = fmul float %71, %314
>  %317 = fmul float %72, %313
>  %318 = fadd float %317, %316
>  %319 = fmul float %73, %315
>  %320 = fadd float %318, %319
>  %321 = fdiv float 1.000000e+00, %320
>  %322 = fsub float %310, %247
>  %323 = fsub float %311, %248
>  %324 = fsub float %312, %249
>  %325 = fmul float %322, %322
>  %326 = fmul float %323, %323
>  %327 = fadd float %326, %325
>  %328 = fmul float %324, %324
>  %329 = fadd float %327, %328
>  %330 = call float @fabs(float %329)
>  %331 = call float @llvm.AMDGPU.rsq(float %330)
>  %332 = fmul float %322, %331
>  %333 = fmul float %323, %331
>  %334 = fmul float %324, %331
>  %335 = fmul float %190, %310
>  %336 = fmul float %191, %311
>  %337 = fadd float %336, %335
>  %338 = fmul float %192, %312
>  %339 = fadd float %337, %338
>  %340 = fmul float %190, %332
>  %341 = fmul float %191, %333
>  %342 = fadd float %341, %340
>  %343 = fmul float %192, %334
>  %344 = fadd float %342, %343
>  %345 = fcmp uge float %339, 0.000000e+00
>  %346 = select i1 %345, float %339, float 0.000000e+00
>  %347 = fcmp uge float %344, 0.000000e+00
>  %348 = select i1 %347, float %344, float 0.000000e+00
>  %349 = call float @llvm.pow.f32(float %348, float %36)
>  %350 = call float @llvm.AMDGPU.cndlt(float %339, float 0.000000e+00, float %349)
>  %351 = fmul float 1.000000e+00, %321
>  %352 = fmul float %346, %321
>  %353 = fmul float %350, %321
>  %354 = fmul float %351, %74
>  %355 = fadd float %354, %295
>  %356 = fmul float %351, %75
>  %357 = fadd float %356, %297
>  %358 = fmul float %351, %76
>  %359 = fadd float %358, %299
>  %360 = fmul float %352, %77
>  %361 = fadd float %360, %355
>  %362 = fmul float %352, %78
>  %363 = fadd float %362, %357
>  %364 = fmul float %352, %79
>  %365 = fadd float %364, %359
>  %366 = fmul float %353, %80
>  %367 = fadd float %366, %361
>  %368 = fmul float %353, %81
>  %369 = fadd float %368, %363
>  %370 = fmul float %353, %82
>  %371 = fadd float %370, %365
>  %372 = fsub float %83, %213
>  %373 = fsub float %84, %215
>  %374 = fsub float %85, %217
>  %375 = fmul float %372, %372
>  %376 = fmul float %373, %373
>  %377 = fadd float %376, %375
>  %378 = fmul float %374, %374
>  %379 = fadd float %377, %378
>  %380 = call float @fabs(float %379)
>  %381 = call float @llvm.AMDGPU.rsq(float %380)
>  %382 = fmul float %372, %381
>  %383 = fmul float %373, %381
>  %384 = fmul float %374, %381
>  %385 = fdiv float 1.000000e+00, %381
>  %386 = fmul float %381, %385
>  %387 = fmul float %385, %385
>  %388 = fmul float %86, %386
>  %389 = fmul float %87, %385
>  %390 = fadd float %389, %388
>  %391 = fmul float %88, %387
>  %392 = fadd float %390, %391
>  %393 = fdiv float 1.000000e+00, %392
>  %394 = fsub float %382, %247
>  %395 = fsub float %383, %248
>  %396 = fsub float %384, %249
>  %397 = fmul float %394, %394
>  %398 = fmul float %395, %395
>  %399 = fadd float %398, %397
>  %400 = fmul float %396, %396
>  %401 = fadd float %399, %400
>  %402 = call float @fabs(float %401)
>  %403 = call float @llvm.AMDGPU.rsq(float %402)
>  %404 = fmul float %394, %403
>  %405 = fmul float %395, %403
>  %406 = fmul float %396, %403
>  %407 = fmul float %190, %382
>  %408 = fmul float %191, %383
>  %409 = fadd float %408, %407
>  %410 = fmul float %192, %384
>  %411 = fadd float %409, %410
>  %412 = fmul float %190, %404
>  %413 = fmul float %191, %405
>  %414 = fadd float %413, %412
>  %415 = fmul float %192, %406
>  %416 = fadd float %414, %415
>  %417 = fcmp uge float %411, 0.000000e+00
>  %418 = select i1 %417, float %411, float 0.000000e+00
>  %419 = fcmp uge float %416, 0.000000e+00
>  %420 = select i1 %419, float %416, float 0.000000e+00
>  %421 = call float @llvm.pow.f32(float %420, float %36)
>  %422 = call float @llvm.AMDGPU.cndlt(float %411, float 0.000000e+00, float %421)
>  %423 = fmul float 1.000000e+00, %393
>  %424 = fmul float %418, %393
>  %425 = fmul float %422, %393
>  %426 = fmul float %423, %89
>  %427 = fadd float %426, %367
>  %428 = fmul float %423, %90
>  %429 = fadd float %428, %369
>  %430 = fmul float %423, %91
>  %431 = fadd float %430, %371
>  %432 = fmul float %424, %92
>  %433 = fadd float %432, %427
>  %434 = fmul float %424, %93
>  %435 = fadd float %434, %429
>  %436 = fmul float %424, %94
>  %437 = fadd float %436, %431
>  %438 = fmul float %425, %95
>  %439 = fadd float %438, %433
>  %440 = fmul float %425, %96
>  %441 = fadd float %440, %435
>  %442 = fmul float %425, %97
>  %443 = fadd float %442, %437
>  %444 = fsub float %98, %213
>  %445 = fsub float %99, %215
>  %446 = fsub float %100, %217
>  %447 = fmul float %444, %444
>  %448 = fmul float %445, %445
>  %449 = fadd float %448, %447
>  %450 = fmul float %446, %446
>  %451 = fadd float %449, %450
>  %452 = call float @fabs(float %451)
>  %453 = call float @llvm.AMDGPU.rsq(float %452)
>  %454 = fmul float %444, %453
>  %455 = fmul float %445, %453
>  %456 = fmul float %446, %453
>  %457 = fdiv float 1.000000e+00, %453
>  %458 = fmul float %453, %457
>  %459 = fmul float %457, %457
>  %460 = fmul float %101, %458
>  %461 = fmul float %102, %457
>  %462 = fadd float %461, %460
>  %463 = fmul float %103, %459
>  %464 = fadd float %462, %463
>  %465 = fdiv float 1.000000e+00, %464
>  %466 = fsub float %454, %247
>  %467 = fsub float %455, %248
>  %468 = fsub float %456, %249
>  %469 = fmul float %466, %466
>  %470 = fmul float %467, %467
>  %471 = fadd float %470, %469
>  %472 = fmul float %468, %468
>  %473 = fadd float %471, %472
>  %474 = call float @fabs(float %473)
>  %475 = call float @llvm.AMDGPU.rsq(float %474)
>  %476 = fmul float %466, %475
>  %477 = fmul float %467, %475
>  %478 = fmul float %468, %475
>  %479 = fmul float %190, %454
>  %480 = fmul float %191, %455
>  %481 = fadd float %480, %479
>  %482 = fmul float %192, %456
>  %483 = fadd float %481, %482
>  %484 = fmul float %190, %476
>  %485 = fmul float %191, %477
>  %486 = fadd float %485, %484
>  %487 = fmul float %192, %478
>  %488 = fadd float %486, %487
>  %489 = fcmp uge float %483, 0.000000e+00
>  %490 = select i1 %489, float %483, float 0.000000e+00
>  %491 = fcmp uge float %488, 0.000000e+00
>  %492 = select i1 %491, float %488, float 0.000000e+00
>  %493 = call float @llvm.pow.f32(float %492, float %36)
>  %494 = call float @llvm.AMDGPU.cndlt(float %483, float 0.000000e+00, float %493)
>  %495 = fmul float 1.000000e+00, %465
>  %496 = fmul float %490, %465
>  %497 = fmul float %494, %465
>  %498 = fmul float %495, %104
>  %499 = fadd float %498, %439
>  %500 = fmul float %495, %105
>  %501 = fadd float %500, %441
>  %502 = fmul float %495, %106
>  %503 = fadd float %502, %443
>  %504 = fmul float %496, %107
>  %505 = fadd float %504, %499
>  %506 = fmul float %496, %108
>  %507 = fadd float %506, %501
>  %508 = fmul float %496, %109
>  %509 = fadd float %508, %503
>  %510 = fmul float %497, %110
>  %511 = fadd float %510, %505
>  %512 = fmul float %497, %111
>  %513 = fadd float %512, %507
>  %514 = fmul float %497, %112
>  %515 = fadd float %514, %509
>  %516 = call float @llvm.AMDIL.clamp.(float %511, float 0.000000e+00, float 1.000000e+00)
>  %517 = call float @llvm.AMDIL.clamp.(float %513, float 0.000000e+00, float 1.000000e+00)
>  %518 = call float @llvm.AMDIL.clamp.(float %515, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %516, float %517, float %518, float %196)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %129, float %130, float %131, float %132)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %136, float %137, float %138, float %139)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %161, float %163, float %165, float %167)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020129
>bf8c007f
>100a0204
>c202012d
>bf8c007f
>d2820005
>04140902
>c2020131
>bf8c007f
>d2820005
>04140903
>c2020135
>bf8c007f
>d2820006
>04140904
>c2020128
>bf8c007f
>100a0204
>c202012c
>bf8c007f
>d2820005
>04140902
>c2020130
>bf8c007f
>d2820005
>04140903
>c2020134
>bf8c007f
>d2820009
>04140904
>100a1309
>d2820005
>04160d06
>c202012a
>bf8c007f
>100e0204
>c202012e
>bf8c007f
>d2820007
>041c0902
>c2020132
>bf8c007f
>d2820007
>041c0903
>c2020136
>bf8c007f
>d282000a
>041c0904
>d2820005
>0416150a
>d2060105
>02010105
>7e105b05
>100a1106
>c2020125
>bf8c007f
>080e0c04
>c2020124
>bf8c007f
>081a1204
>10161b0d
>d282000b
>042e0f07
>c2020126
>bf8c007f
>081c1404
>d282000b
>042e1d0e
>d206010b
>0201010b
>7e165b0b
>10181707
>081e0b0c
>100e1109
>101a170d
>08280f0d
>10202914
>d2820012
>04421f0f
>1010110a
>1022170e
>08201111
>d282000e
>044a2110
>d206010e
>0201010e
>7e245b0e
>1026250f
>101e2514
>c0840704
>bf8c007f
>e00c2000
>80021400
>c2020114
>bf8c0070
>101c2804
>c2020115
>bf8c007f
>d282000e
>04380915
>c2020116
>bf8c007f
>d2820018
>04380916
>c2020110
>bf8c007f
>101c2804
>c2020111
>bf8c007f
>d282000e
>04380915
>c2020112
>bf8c007f
>d282000e
>04380916
>10321d0e
>d2820019
>04663118
>c2020118
>bf8c007f
>10342804
>c2020119
>bf8c007f
>d282001a
>04680915
>c202011a
>bf8c007f
>d2820014
>04680916
>d2820015
>04662914
>d2060115
>02010115
>7e2a5b15
>101c2b0e
>102c1f0e
>101e2b18
>d2820013
>045a270f
>10242510
>10202b14
>d2820012
>044e2510
>d00c0004
>02010112
>d2000012
>00122480
>7e244f12
>c202011c
>bf8c007f
>0e242404
>7e244b12
>101a1b0e
>d282000c
>0436190f
>d282000d
>04322310
>d0080008
>02021a80
>d2000011
>00210112
>7e18550b
>1016190b
>c2028138
>bf8c007f
>10161605
>c2028139
>bf8c007f
>d282000b
>042e1805
>1018190c
>c202813a
>bf8c007f
>d282000b
>042e1805
>7e18550b
>10161911
>d00c0008
>0201010d
>d200000d
>00221a80
>101a190d
>c202813e
>c2040122
>bf8c007f
>7e220208
>d2820011
>04440b0c
>c2028142
>bf8c007f
>d2820011
>04440b0d
>c2028146
>bf8c007f
>d2820013
>04440b0b
>c2028149
>bf8c007f
>08240c05
>c2028148
>bf8c007f
>08281205
>10222914
>d2820011
>04462512
>c202814a
>bf8c007f
>082a1405
>d2820011
>04462b15
>d2060111
>02010111
>7e2c5b11
>7e225516
>102e2316
>c202814c
>bf8c007f
>102e2e05
>c202814d
>bf8c007f
>d2820017
>045e2205
>10222311
>c202814e
>bf8c007f
>d2820011
>045e2205
>7e225511
>c2028152
>bf8c007f
>d2820018
>044c0b11
>102e2d14
>10262f0e
>10322d12
>d2820012
>044e330f
>102a2d15
>d2820013
>044a2b10
>d00c0008
>02010113
>d2000012
>00222680
>10242312
>c2028156
>bf8c007f
>d2820014
>04600b12
>082c0b19
>082e0f17
>10302f17
>d2820018
>04622d16
>082a1115
>d2820018
>04622b15
>d2060118
>02010118
>7e305b18
>102c3116
>102e3117
>102e2f0e
>d2820016
>045e2d0f
>102a3115
>d2820015
>045a2b10
>d00c0008
>02010115
>d2000015
>00222a80
>7e2a4f15
>0e2a2a04
>7e2a4b15
>d0080008
>02022680
>d2000013
>00210115
>10262313
>c202815a
>bf8c007f
>d2820016
>04500b13
>c202815d
>bf8c007f
>082a0c05
>c202815c
>bf8c007f
>082e1205
>10282f17
>d2820014
>04522b15
>c202815e
>bf8c007f
>08301405
>d2820014
>04523118
>d2060114
>02010114
>7e325b14
>7e285519
>10342919
>c2028160
>bf8c007f
>10343405
>c2028161
>bf8c007f
>d282001a
>046a2805
>10282914
>c2028162
>bf8c007f
>d2820014
>046a2805
>7e285514
>c2028166
>bf8c007f
>d282001b
>04580b14
>10343317
>102c350e
>10383315
>d2820015
>045a390f
>10303318
>d2820016
>04563110
>d00c0008
>02010116
>d2000015
>00222c80
>102a2915
>c202816a
>bf8c007f
>d2820017
>046c0b15
>08320b1c
>08340f1a
>1036351a
>d282001b
>046e3319
>08301118
>d282001b
>046e3118
>d206011b
>0201011b
>7e365b1b
>10323719
>1034371a
>1034350e
>d2820019
>046a330f
>10303718
>d2820018
>04663110
>d00c0008
>02010118
>d2000018
>00223080
>7e304f18
>0e303004
>7e304b18
>d0080008
>02022c80
>d2000016
>00210118
>102c2916
>c202816e
>bf8c007f
>d2820018
>045c0b16
>c2028171
>bf8c007f
>082e0c05
>c2028170
>bf8c007f
>08121205
>100c1309
>d2820006
>041a2f17
>c2028172
>bf8c007f
>08141405
>d2820006
>041a150a
>d2060106
>02010106
>7e325b06
>7e0c5519
>10340d19
>c2028174
>bf8c007f
>10343405
>c2028175
>bf8c007f
>d282001a
>046a0c05
>100c0d06
>c2028176
>bf8c007f
>d2820006
>046a0c05
>7e0c5506
>c202817a
>bf8c007f
>d282001a
>04600b06
>10303309
>1012310e
>10363317
>d2820009
>0426370f
>1032330a
>d282000a
>04263310
>d00c0008
>0201010a
>d2000009
>00221480
>10120d09
>c202817e
>bf8c007f
>d2820017
>04680b09
>080a0b1b
>080e0f18
>10300f07
>d2820018
>04620b05
>08101119
>d2820018
>04621108
>d2060118
>02010118
>7e305b18
>100a3105
>100e3107
>100e0f0e
>d2820005
>041e0b0f
>100e3108
>d2820005
>04160f10
>d00c0008
>02010105
>d2000005
>00220a80
>7e0a4f05
>0e0a0a04
>7e0a4b05
>d0080004
>02021480
>d2000005
>00110105
>100e0d05
>c2020182
>bf8c007f
>d2820005
>045c0907
>d2060805
>02010105
>c202013d
>c2028121
>bf8c007f
>7e100205
>d2820008
>0420090c
>c2020141
>bf8c007f
>d2820008
>0420090d
>c2020145
>bf8c007f
>d2820008
>0420090b
>c2020151
>bf8c007f
>d2820008
>04200911
>c2020155
>bf8c007f
>d2820008
>04200912
>c2020159
>bf8c007f
>d2820008
>04200913
>c2020165
>bf8c007f
>d2820008
>04200914
>c2020169
>bf8c007f
>d2820008
>04200915
>c202016d
>bf8c007f
>d2820008
>04200916
>c2020179
>bf8c007f
>d2820008
>04200906
>c202017d
>bf8c007f
>d2820008
>04200909
>c2020181
>bf8c007f
>d2820008
>04200907
>d2060808
>02010108
>c202013c
>c2028120
>bf8c007f
>7e140205
>d282000a
>0428090c
>c2020140
>bf8c007f
>d282000a
>0428090d
>c2020144
>bf8c007f
>d282000a
>0428090b
>c2020150
>bf8c007f
>d282000a
>04280911
>c2020154
>bf8c007f
>d282000a
>04280912
>c2020158
>bf8c007f
>d282000a
>04280913
>c2020164
>bf8c007f
>d282000a
>04280914
>c2020168
>bf8c007f
>d282000a
>04280915
>c202016c
>bf8c007f
>d282000a
>04280916
>c2020178
>bf8c007f
>d2820006
>04280906
>c202017c
>bf8c007f
>d2820006
>04180909
>c2020180
>bf8c007f
>d2820006
>04180907
>d2060806
>02010106
>c2020123
>bf8c007f
>d2060807
>02010004
>f800020f
>07050806
>c0840708
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800021f
>08070605
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..27]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: MOV OUT[2], IN[3]
> 41: MUL TEMP[1], IN[4].xxxx, CONST[20]
> 42: MAD TEMP[1], IN[4].yyyy, CONST[21], TEMP[1]
> 43: MAD TEMP[1], IN[4].zzzz, CONST[22], TEMP[1]
> 44: MAD OUT[3], IN[4].wwww, CONST[23], TEMP[1]
> 45: DP3 TEMP[2], TEMP[0], TEMP[6]
> 46: ADD TEMP[2], TEMP[2], TEMP[2]
> 47: MAD TEMP[1].xyz, -TEMP[2], TEMP[0], TEMP[6]
> 48: MOV TEMP[1].w, IN[5]
> 49: MUL TEMP[2], TEMP[1].xxxx, CONST[24]
> 50: MAD TEMP[2], TEMP[1].yyyy, CONST[25], TEMP[2]
> 51: MAD TEMP[2], TEMP[1].zzzz, CONST[26], TEMP[2]
> 52: MAD OUT[4], TEMP[1].wwww, CONST[27], TEMP[2]
> 53: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 444)
>  %103 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %104 = load <16 x i8> addrspace(2)* %103, !tbaa !0
>  %105 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %104, i32 0, i32 %5)
>  %106 = extractelement <4 x float> %105, i32 0
>  %107 = extractelement <4 x float> %105, i32 1
>  %108 = extractelement <4 x float> %105, i32 2
>  %109 = extractelement <4 x float> %105, i32 3
>  %110 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %111 = load <16 x i8> addrspace(2)* %110, !tbaa !0
>  %112 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %111, i32 0, i32 %5)
>  %113 = extractelement <4 x float> %112, i32 0
>  %114 = extractelement <4 x float> %112, i32 1
>  %115 = extractelement <4 x float> %112, i32 2
>  %116 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %117 = load <16 x i8> addrspace(2)* %116, !tbaa !0
>  %118 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %117, i32 0, i32 %5)
>  %119 = extractelement <4 x float> %118, i32 0
>  %120 = extractelement <4 x float> %118, i32 1
>  %121 = extractelement <4 x float> %118, i32 2
>  %122 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
>  %124 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %123, i32 0, i32 %5)
>  %125 = extractelement <4 x float> %124, i32 0
>  %126 = extractelement <4 x float> %124, i32 1
>  %127 = extractelement <4 x float> %124, i32 2
>  %128 = extractelement <4 x float> %124, i32 3
>  %129 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %130 = load <16 x i8> addrspace(2)* %129, !tbaa !0
>  %131 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %130, i32 0, i32 %5)
>  %132 = extractelement <4 x float> %131, i32 0
>  %133 = extractelement <4 x float> %131, i32 1
>  %134 = extractelement <4 x float> %131, i32 2
>  %135 = extractelement <4 x float> %131, i32 3
>  %136 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %137 = load <16 x i8> addrspace(2)* %136, !tbaa !0
>  %138 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %137, i32 0, i32 %5)
>  %139 = extractelement <4 x float> %138, i32 3
>  %140 = fmul float %106, %11
>  %141 = fmul float %106, %12
>  %142 = fmul float %106, %13
>  %143 = fmul float %106, %14
>  %144 = fmul float %107, %15
>  %145 = fadd float %144, %140
>  %146 = fmul float %107, %16
>  %147 = fadd float %146, %141
>  %148 = fmul float %107, %17
>  %149 = fadd float %148, %142
>  %150 = fmul float %107, %18
>  %151 = fadd float %150, %143
>  %152 = fmul float %108, %19
>  %153 = fadd float %152, %145
>  %154 = fmul float %108, %20
>  %155 = fadd float %154, %147
>  %156 = fmul float %108, %21
>  %157 = fadd float %156, %149
>  %158 = fmul float %108, %22
>  %159 = fadd float %158, %151
>  %160 = fmul float %109, %23
>  %161 = fadd float %160, %153
>  %162 = fmul float %109, %24
>  %163 = fadd float %162, %155
>  %164 = fmul float %109, %25
>  %165 = fadd float %164, %157
>  %166 = fmul float %109, %26
>  %167 = fadd float %166, %159
>  %168 = fmul float %113, %27
>  %169 = fmul float %114, %28
>  %170 = fadd float %169, %168
>  %171 = fmul float %115, %29
>  %172 = fadd float %170, %171
>  %173 = fmul float %113, %30
>  %174 = fmul float %114, %31
>  %175 = fadd float %174, %173
>  %176 = fmul float %115, %32
>  %177 = fadd float %175, %176
>  %178 = fmul float %113, %33
>  %179 = fmul float %114, %34
>  %180 = fadd float %179, %178
>  %181 = fmul float %115, %35
>  %182 = fadd float %180, %181
>  %183 = fmul float %172, %172
>  %184 = fmul float %177, %177
>  %185 = fadd float %184, %183
>  %186 = fmul float %182, %182
>  %187 = fadd float %185, %186
>  %188 = call float @fabs(float %187)
>  %189 = call float @llvm.AMDGPU.rsq(float %188)
>  %190 = fmul float %172, %189
>  %191 = fmul float %177, %189
>  %192 = fmul float %182, %189
>  %193 = fmul float %37, %40
>  %194 = fadd float %193, %119
>  %195 = fmul float %38, %41
>  %196 = fadd float %195, %120
>  %197 = fmul float %39, %42
>  %198 = fadd float %197, %121
>  %199 = call float @llvm.AMDIL.clamp.(float %194, float 0.000000e+00, float 1.000000e+00)
>  %200 = call float @llvm.AMDIL.clamp.(float %196, float 0.000000e+00, float 1.000000e+00)
>  %201 = call float @llvm.AMDIL.clamp.(float %198, float 0.000000e+00, float 1.000000e+00)
>  %202 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %203 = fmul float %106, %47
>  %204 = fmul float %106, %48
>  %205 = fmul float %106, %49
>  %206 = fmul float %107, %50
>  %207 = fadd float %206, %203
>  %208 = fmul float %107, %51
>  %209 = fadd float %208, %204
>  %210 = fmul float %107, %52
>  %211 = fadd float %210, %205
>  %212 = fmul float %108, %53
>  %213 = fadd float %212, %207
>  %214 = fmul float %108, %54
>  %215 = fadd float %214, %209
>  %216 = fmul float %108, %55
>  %217 = fadd float %216, %211
>  %218 = fmul float %109, %56
>  %219 = fadd float %218, %213
>  %220 = fmul float %109, %57
>  %221 = fadd float %220, %215
>  %222 = fmul float %109, %58
>  %223 = fadd float %222, %217
>  %224 = fsub float %44, %219
>  %225 = fsub float %45, %221
>  %226 = fsub float %46, %223
>  %227 = fmul float %224, %224
>  %228 = fmul float %225, %225
>  %229 = fadd float %228, %227
>  %230 = fmul float %226, %226
>  %231 = fadd float %229, %230
>  %232 = call float @fabs(float %231)
>  %233 = call float @llvm.AMDGPU.rsq(float %232)
>  %234 = fmul float %224, %233
>  %235 = fmul float %225, %233
>  %236 = fmul float %226, %233
>  %237 = fdiv float 1.000000e+00, %233
>  %238 = fmul float %233, %237
>  %239 = fmul float %237, %237
>  %240 = fmul float %59, %238
>  %241 = fmul float %60, %237
>  %242 = fadd float %241, %240
>  %243 = fmul float %61, %239
>  %244 = fadd float %242, %243
>  %245 = fdiv float 1.000000e+00, %244
>  %246 = fmul float %219, %219
>  %247 = fmul float %221, %221
>  %248 = fadd float %247, %246
>  %249 = fmul float %223, %223
>  %250 = fadd float %248, %249
>  %251 = call float @fabs(float %250)
>  %252 = call float @llvm.AMDGPU.rsq(float %251)
>  %253 = fmul float %219, %252
>  %254 = fmul float %221, %252
>  %255 = fmul float %223, %252
>  %256 = fsub float %234, %253
>  %257 = fsub float %235, %254
>  %258 = fsub float %236, %255
>  %259 = fmul float %256, %256
>  %260 = fmul float %257, %257
>  %261 = fadd float %260, %259
>  %262 = fmul float %258, %258
>  %263 = fadd float %261, %262
>  %264 = call float @fabs(float %263)
>  %265 = call float @llvm.AMDGPU.rsq(float %264)
>  %266 = fmul float %256, %265
>  %267 = fmul float %257, %265
>  %268 = fmul float %258, %265
>  %269 = fmul float %190, %234
>  %270 = fmul float %191, %235
>  %271 = fadd float %270, %269
>  %272 = fmul float %192, %236
>  %273 = fadd float %271, %272
>  %274 = fmul float %190, %266
>  %275 = fmul float %191, %267
>  %276 = fadd float %275, %274
>  %277 = fmul float %192, %268
>  %278 = fadd float %276, %277
>  %279 = fcmp uge float %273, 0.000000e+00
>  %280 = select i1 %279, float %273, float 0.000000e+00
>  %281 = fcmp uge float %278, 0.000000e+00
>  %282 = select i1 %281, float %278, float 0.000000e+00
>  %283 = call float @llvm.pow.f32(float %282, float %36)
>  %284 = call float @llvm.AMDGPU.cndlt(float %273, float 0.000000e+00, float %283)
>  %285 = fmul float 1.000000e+00, %245
>  %286 = fmul float %280, %245
>  %287 = fmul float %284, %245
>  %288 = fmul float %285, %62
>  %289 = fadd float %288, %194
>  %290 = fmul float %285, %63
>  %291 = fadd float %290, %196
>  %292 = fmul float %285, %64
>  %293 = fadd float %292, %198
>  %294 = fmul float %286, %65
>  %295 = fadd float %294, %289
>  %296 = fmul float %286, %66
>  %297 = fadd float %296, %291
>  %298 = fmul float %286, %67
>  %299 = fadd float %298, %293
>  %300 = fmul float %287, %68
>  %301 = fadd float %300, %295
>  %302 = fmul float %287, %69
>  %303 = fadd float %302, %297
>  %304 = fmul float %287, %70
>  %305 = fadd float %304, %299
>  %306 = call float @llvm.AMDIL.clamp.(float %301, float 0.000000e+00, float 1.000000e+00)
>  %307 = call float @llvm.AMDIL.clamp.(float %303, float 0.000000e+00, float 1.000000e+00)
>  %308 = call float @llvm.AMDIL.clamp.(float %305, float 0.000000e+00, float 1.000000e+00)
>  %309 = fmul float %132, %71
>  %310 = fmul float %132, %72
>  %311 = fmul float %132, %73
>  %312 = fmul float %132, %74
>  %313 = fmul float %133, %75
>  %314 = fadd float %313, %309
>  %315 = fmul float %133, %76
>  %316 = fadd float %315, %310
>  %317 = fmul float %133, %77
>  %318 = fadd float %317, %311
>  %319 = fmul float %133, %78
>  %320 = fadd float %319, %312
>  %321 = fmul float %134, %79
>  %322 = fadd float %321, %314
>  %323 = fmul float %134, %80
>  %324 = fadd float %323, %316
>  %325 = fmul float %134, %81
>  %326 = fadd float %325, %318
>  %327 = fmul float %134, %82
>  %328 = fadd float %327, %320
>  %329 = fmul float %135, %83
>  %330 = fadd float %329, %322
>  %331 = fmul float %135, %84
>  %332 = fadd float %331, %324
>  %333 = fmul float %135, %85
>  %334 = fadd float %333, %326
>  %335 = fmul float %135, %86
>  %336 = fadd float %335, %328
>  %337 = fmul float %190, %253
>  %338 = fmul float %191, %254
>  %339 = fadd float %338, %337
>  %340 = fmul float %192, %255
>  %341 = fadd float %339, %340
>  %342 = fadd float %341, %341
>  %343 = fadd float %341, %341
>  %344 = fadd float %341, %341
>  %345 = fsub float -0.000000e+00, %342
>  %346 = fmul float %345, %190
>  %347 = fadd float %346, %253
>  %348 = fsub float -0.000000e+00, %343
>  %349 = fmul float %348, %191
>  %350 = fadd float %349, %254
>  %351 = fsub float -0.000000e+00, %344
>  %352 = fmul float %351, %192
>  %353 = fadd float %352, %255
>  %354 = fmul float %347, %87
>  %355 = fmul float %347, %88
>  %356 = fmul float %347, %89
>  %357 = fmul float %347, %90
>  %358 = fmul float %350, %91
>  %359 = fadd float %358, %354
>  %360 = fmul float %350, %92
>  %361 = fadd float %360, %355
>  %362 = fmul float %350, %93
>  %363 = fadd float %362, %356
>  %364 = fmul float %350, %94
>  %365 = fadd float %364, %357
>  %366 = fmul float %353, %95
>  %367 = fadd float %366, %359
>  %368 = fmul float %353, %96
>  %369 = fadd float %368, %361
>  %370 = fmul float %353, %97
>  %371 = fadd float %370, %363
>  %372 = fmul float %353, %98
>  %373 = fadd float %372, %365
>  %374 = fmul float %139, %99
>  %375 = fadd float %374, %367
>  %376 = fmul float %139, %100
>  %377 = fadd float %376, %369
>  %378 = fmul float %139, %101
>  %379 = fadd float %378, %371
>  %380 = fmul float %139, %102
>  %381 = fadd float %380, %373
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %306, float %307, float %308, float %202)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %125, float %126, float %127, float %128)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %330, float %332, float %334, float %336)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %375, float %377, float %379, float %381)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %161, float %163, float %165, float %167)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820007
>04140904
>c2020130
>bf8c007f
>100a0204
>c2020134
>bf8c007f
>d2820005
>04140902
>c2020138
>bf8c007f
>d2820005
>04140903
>c202013c
>bf8c007f
>d2820006
>04140904
>100a0d06
>d2820005
>04160f07
>c2020132
>bf8c007f
>10100204
>c2020136
>bf8c007f
>d2820008
>04200902
>c202013a
>bf8c007f
>d2820008
>04200903
>c202013e
>bf8c007f
>d2820008
>04200904
>d2820005
>04161108
>d2060105
>02010105
>7e125b05
>100a1307
>c202012d
>bf8c007f
>080e0e04
>c202012c
>bf8c007f
>081a0c04
>10141b0d
>d282000b
>042a0f07
>c202012e
>bf8c007f
>08141004
>d282000b
>042e150a
>d206010b
>0201010b
>7e165b0b
>10181707
>08200b0c
>100e1306
>101a170d
>08220f0d
>100c2311
>d282000f
>041a2110
>100c1308
>101c170a
>08100d0e
>d2820009
>043e1108
>d2060109
>02010109
>7e1e5b09
>10201f10
>10141f11
>c0840704
>bf8c007f
>e00c2000
>80021100
>c2020114
>bf8c0070
>10122204
>c2020115
>bf8c007f
>d2820009
>04240912
>c2020116
>bf8c007f
>d2820015
>04240913
>c2020110
>bf8c007f
>10122204
>c2020111
>bf8c007f
>d2820009
>04240912
>c2020112
>bf8c007f
>d2820009
>04240913
>102c1309
>d2820016
>045a2b15
>c2020118
>bf8c007f
>102e2204
>c2020119
>bf8c007f
>d2820017
>045c0912
>c202011a
>bf8c007f
>d2820011
>045c0913
>d2820012
>045a2311
>d2060112
>02010112
>7e245b12
>10122509
>10261509
>10142515
>d2820010
>044e210a
>101e1f08
>10102511
>d282000f
>04421f08
>d00c0004
>0201010f
>d200000f
>00121e80
>7e1e4f0f
>c202011c
>bf8c007f
>0e1e1e04
>7e1e4b0f
>101a1b09
>d282000c
>0436190a
>d282000d
>04321d08
>d0080004
>02021a80
>d200000e
>0011010f
>7e18550b
>1016190b
>c2020140
>bf8c007f
>10161604
>c2020141
>bf8c007f
>d282000b
>042e1804
>1018190c
>c2020142
>bf8c007f
>d282000b
>042e1804
>7e18550b
>1016190e
>d00c0004
>0201010d
>d200000d
>00121a80
>101a190d
>c0840708
>bf8c007f
>e00c2000
>80020e00
>c2020122
>c2028126
>bf8c0070
>7e240205
>d2820012
>04422404
>c2020146
>bf8c007f
>d2820012
>0448090c
>c202014a
>bf8c007f
>d2820012
>0448090d
>c202014e
>bf8c007f
>d2820012
>0448090b
>d2060812
>02010112
>c2020121
>c2028125
>bf8c007f
>7e260205
>d2820013
>043e2604
>c2020145
>bf8c007f
>d2820013
>044c090c
>c2020149
>bf8c007f
>d2820013
>044c090d
>c202014d
>bf8c007f
>d2820013
>044c090b
>d2060813
>02010113
>c2020120
>c2028124
>bf8c007f
>7e280205
>d282000e
>043a2804
>c2020144
>bf8c007f
>d282000c
>0438090c
>c2020148
>bf8c007f
>d282000c
>0430090d
>c202014c
>bf8c007f
>d282000b
>0430090b
>d206080b
>0201010b
>c202012b
>bf8c007f
>d206080c
>02010004
>f800020f
>0c12130b
>c084070c
>bf8c000f
>e00c2000
>80020b00
>bf8c0770
>f800021f
>0e0d0c0b
>c0840710
>bf8c000f
>e00c2000
>80020b00
>c2020153
>bf8c0070
>101e1604
>c2020157
>bf8c007f
>d282000f
>043c090c
>c202015b
>bf8c007f
>d282000f
>043c090d
>c202015f
>bf8c007f
>d282000f
>043c090e
>c2020152
>bf8c007f
>10201604
>c2020156
>bf8c007f
>d2820010
>0440090c
>c202015a
>bf8c007f
>d2820010
>0440090d
>c202015e
>bf8c007f
>d2820010
>0440090e
>c2020151
>bf8c007f
>10221604
>c2020155
>bf8c007f
>d2820011
>0444090c
>c2020159
>bf8c007f
>d2820011
>0444090d
>c202015d
>bf8c007f
>d2820011
>0444090e
>c2020150
>bf8c007f
>10241604
>c2020154
>bf8c007f
>d2820012
>0448090c
>c2020158
>bf8c007f
>d2820012
>0448090d
>c202015c
>bf8c007f
>d282000b
>0448090e
>f800022f
>0f10110b
>bf8c070f
>10160f09
>d282000b
>042e0b0a
>d282000b
>042e0d08
>0616170b
>1014150b
>080a1505
>1012130b
>080e1307
>c2020163
>bf8c007f
>10120e04
>c2020167
>bf8c007f
>d2820009
>04240905
>1010110b
>080c1106
>c202016b
>bf8c007f
>d282000c
>04240906
>c0820714
>bf8c007f
>e00c2000
>80010800
>c202016f
>bf8c0070
>d2820000
>0430090b
>c2020162
>bf8c007f
>10180e04
>c2020166
>bf8c007f
>d282000c
>04300905
>c202016a
>bf8c007f
>d282000c
>04300906
>c202016e
>bf8c007f
>d282000c
>0430090b
>c2020161
>bf8c007f
>101a0e04
>c2020165
>bf8c007f
>d282000d
>04340905
>c2020169
>bf8c007f
>d282000d
>04340906
>c202016d
>bf8c007f
>d282000d
>0434090b
>c2020160
>bf8c007f
>100e0e04
>c2020164
>bf8c007f
>d2820005
>041c0905
>c2020168
>bf8c007f
>d2820005
>04140906
>c202016c
>bf8c007f
>d2820005
>0414090b
>f800023f
>000c0d05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..22]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: MOV OUT[2], IN[2]
> 59: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %84 = load <16 x i8> addrspace(2)* %83, !tbaa !0
>  %85 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %84, i32 0, i32 %5)
>  %86 = extractelement <4 x float> %85, i32 0
>  %87 = extractelement <4 x float> %85, i32 1
>  %88 = extractelement <4 x float> %85, i32 2
>  %89 = extractelement <4 x float> %85, i32 3
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %97 = load <16 x i8> addrspace(2)* %96, !tbaa !0
>  %98 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %97, i32 0, i32 %5)
>  %99 = extractelement <4 x float> %98, i32 0
>  %100 = extractelement <4 x float> %98, i32 1
>  %101 = extractelement <4 x float> %98, i32 2
>  %102 = extractelement <4 x float> %98, i32 3
>  %103 = fmul float %86, %11
>  %104 = fmul float %86, %12
>  %105 = fmul float %86, %13
>  %106 = fmul float %86, %14
>  %107 = fmul float %87, %15
>  %108 = fadd float %107, %103
>  %109 = fmul float %87, %16
>  %110 = fadd float %109, %104
>  %111 = fmul float %87, %17
>  %112 = fadd float %111, %105
>  %113 = fmul float %87, %18
>  %114 = fadd float %113, %106
>  %115 = fmul float %88, %19
>  %116 = fadd float %115, %108
>  %117 = fmul float %88, %20
>  %118 = fadd float %117, %110
>  %119 = fmul float %88, %21
>  %120 = fadd float %119, %112
>  %121 = fmul float %88, %22
>  %122 = fadd float %121, %114
>  %123 = fmul float %89, %23
>  %124 = fadd float %123, %116
>  %125 = fmul float %89, %24
>  %126 = fadd float %125, %118
>  %127 = fmul float %89, %25
>  %128 = fadd float %127, %120
>  %129 = fmul float %89, %26
>  %130 = fadd float %129, %122
>  %131 = fmul float %93, %27
>  %132 = fmul float %94, %28
>  %133 = fadd float %132, %131
>  %134 = fmul float %95, %29
>  %135 = fadd float %133, %134
>  %136 = fmul float %93, %30
>  %137 = fmul float %94, %31
>  %138 = fadd float %137, %136
>  %139 = fmul float %95, %32
>  %140 = fadd float %138, %139
>  %141 = fmul float %93, %33
>  %142 = fmul float %94, %34
>  %143 = fadd float %142, %141
>  %144 = fmul float %95, %35
>  %145 = fadd float %143, %144
>  %146 = fmul float %135, %135
>  %147 = fmul float %140, %140
>  %148 = fadd float %147, %146
>  %149 = fmul float %145, %145
>  %150 = fadd float %148, %149
>  %151 = call float @fabs(float %150)
>  %152 = call float @llvm.AMDGPU.rsq(float %151)
>  %153 = fmul float %135, %152
>  %154 = fmul float %140, %152
>  %155 = fmul float %145, %152
>  %156 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %157 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %158 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %159 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %160 = fmul float %86, %44
>  %161 = fmul float %86, %45
>  %162 = fmul float %86, %46
>  %163 = fmul float %87, %47
>  %164 = fadd float %163, %160
>  %165 = fmul float %87, %48
>  %166 = fadd float %165, %161
>  %167 = fmul float %87, %49
>  %168 = fadd float %167, %162
>  %169 = fmul float %88, %50
>  %170 = fadd float %169, %164
>  %171 = fmul float %88, %51
>  %172 = fadd float %171, %166
>  %173 = fmul float %88, %52
>  %174 = fadd float %173, %168
>  %175 = fmul float %89, %53
>  %176 = fadd float %175, %170
>  %177 = fmul float %89, %54
>  %178 = fadd float %177, %172
>  %179 = fmul float %89, %55
>  %180 = fadd float %179, %174
>  %181 = fsub float %41, %176
>  %182 = fsub float %42, %178
>  %183 = fsub float %43, %180
>  %184 = fmul float %181, %181
>  %185 = fmul float %182, %182
>  %186 = fadd float %185, %184
>  %187 = fmul float %183, %183
>  %188 = fadd float %186, %187
>  %189 = call float @fabs(float %188)
>  %190 = call float @llvm.AMDGPU.rsq(float %189)
>  %191 = fmul float %181, %190
>  %192 = fmul float %182, %190
>  %193 = fmul float %183, %190
>  %194 = fdiv float 1.000000e+00, %190
>  %195 = fmul float %190, %194
>  %196 = fmul float %194, %194
>  %197 = fmul float %56, %195
>  %198 = fmul float %57, %194
>  %199 = fadd float %198, %197
>  %200 = fmul float %58, %196
>  %201 = fadd float %199, %200
>  %202 = fdiv float 1.000000e+00, %201
>  %203 = fmul float %176, %176
>  %204 = fmul float %178, %178
>  %205 = fadd float %204, %203
>  %206 = fmul float %180, %180
>  %207 = fadd float %205, %206
>  %208 = call float @fabs(float %207)
>  %209 = call float @llvm.AMDGPU.rsq(float %208)
>  %210 = fmul float %176, %209
>  %211 = fmul float %178, %209
>  %212 = fmul float %180, %209
>  %213 = fsub float %191, %210
>  %214 = fsub float %192, %211
>  %215 = fsub float %193, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fmul float %153, %191
>  %227 = fmul float %154, %192
>  %228 = fadd float %227, %226
>  %229 = fmul float %155, %193
>  %230 = fadd float %228, %229
>  %231 = fmul float %153, %223
>  %232 = fmul float %154, %224
>  %233 = fadd float %232, %231
>  %234 = fmul float %155, %225
>  %235 = fadd float %233, %234
>  %236 = fcmp uge float %230, 0.000000e+00
>  %237 = select i1 %236, float %230, float 0.000000e+00
>  %238 = fcmp uge float %235, 0.000000e+00
>  %239 = select i1 %238, float %235, float 0.000000e+00
>  %240 = call float @llvm.pow.f32(float %239, float %36)
>  %241 = call float @llvm.AMDGPU.cndlt(float %230, float 0.000000e+00, float %240)
>  %242 = fmul float 1.000000e+00, %202
>  %243 = fmul float %237, %202
>  %244 = fmul float %241, %202
>  %245 = fmul float %242, %59
>  %246 = fadd float %245, %37
>  %247 = fmul float %242, %60
>  %248 = fadd float %247, %38
>  %249 = fmul float %242, %61
>  %250 = fadd float %249, %39
>  %251 = fmul float %243, %62
>  %252 = fadd float %251, %246
>  %253 = fmul float %243, %63
>  %254 = fadd float %253, %248
>  %255 = fmul float %243, %64
>  %256 = fadd float %255, %250
>  %257 = fmul float %244, %65
>  %258 = fadd float %257, %252
>  %259 = fmul float %244, %66
>  %260 = fadd float %259, %254
>  %261 = fmul float %244, %67
>  %262 = fadd float %261, %256
>  %263 = fsub float %68, %176
>  %264 = fsub float %69, %178
>  %265 = fsub float %70, %180
>  %266 = fmul float %263, %263
>  %267 = fmul float %264, %264
>  %268 = fadd float %267, %266
>  %269 = fmul float %265, %265
>  %270 = fadd float %268, %269
>  %271 = call float @fabs(float %270)
>  %272 = call float @llvm.AMDGPU.rsq(float %271)
>  %273 = fmul float %263, %272
>  %274 = fmul float %264, %272
>  %275 = fmul float %265, %272
>  %276 = fdiv float 1.000000e+00, %272
>  %277 = fmul float %272, %276
>  %278 = fmul float %276, %276
>  %279 = fmul float %71, %277
>  %280 = fmul float %72, %276
>  %281 = fadd float %280, %279
>  %282 = fmul float %73, %278
>  %283 = fadd float %281, %282
>  %284 = fdiv float 1.000000e+00, %283
>  %285 = fsub float %273, %210
>  %286 = fsub float %274, %211
>  %287 = fsub float %275, %212
>  %288 = fmul float %285, %285
>  %289 = fmul float %286, %286
>  %290 = fadd float %289, %288
>  %291 = fmul float %287, %287
>  %292 = fadd float %290, %291
>  %293 = call float @fabs(float %292)
>  %294 = call float @llvm.AMDGPU.rsq(float %293)
>  %295 = fmul float %285, %294
>  %296 = fmul float %286, %294
>  %297 = fmul float %287, %294
>  %298 = fmul float %153, %273
>  %299 = fmul float %154, %274
>  %300 = fadd float %299, %298
>  %301 = fmul float %155, %275
>  %302 = fadd float %300, %301
>  %303 = fmul float %153, %295
>  %304 = fmul float %154, %296
>  %305 = fadd float %304, %303
>  %306 = fmul float %155, %297
>  %307 = fadd float %305, %306
>  %308 = fcmp uge float %302, 0.000000e+00
>  %309 = select i1 %308, float %302, float 0.000000e+00
>  %310 = fcmp uge float %307, 0.000000e+00
>  %311 = select i1 %310, float %307, float 0.000000e+00
>  %312 = call float @llvm.pow.f32(float %311, float %36)
>  %313 = call float @llvm.AMDGPU.cndlt(float %302, float 0.000000e+00, float %312)
>  %314 = fmul float 1.000000e+00, %284
>  %315 = fmul float %309, %284
>  %316 = fmul float %313, %284
>  %317 = fmul float %314, %74
>  %318 = fadd float %317, %258
>  %319 = fmul float %314, %75
>  %320 = fadd float %319, %260
>  %321 = fmul float %314, %76
>  %322 = fadd float %321, %262
>  %323 = fmul float %315, %77
>  %324 = fadd float %323, %318
>  %325 = fmul float %315, %78
>  %326 = fadd float %325, %320
>  %327 = fmul float %315, %79
>  %328 = fadd float %327, %322
>  %329 = fmul float %316, %80
>  %330 = fadd float %329, %324
>  %331 = fmul float %316, %81
>  %332 = fadd float %331, %326
>  %333 = fmul float %316, %82
>  %334 = fadd float %333, %328
>  %335 = call float @llvm.AMDIL.clamp.(float %330, float 0.000000e+00, float 1.000000e+00)
>  %336 = call float @llvm.AMDIL.clamp.(float %332, float 0.000000e+00, float 1.000000e+00)
>  %337 = call float @llvm.AMDIL.clamp.(float %334, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %335, float %336, float %337, float %159)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %99, float %100, float %101, float %102)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %124, float %126, float %128, float %130)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
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>c2020129
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>0416150a
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>c2020110
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>bf8c007f
>d282000e
>04380915
>c2020112
>bf8c007f
>d282000e
>04380916
>10321d0e
>d2820019
>04663118
>c2020118
>bf8c007f
>10342804
>c2020119
>bf8c007f
>d282001a
>04680915
>c202011a
>bf8c007f
>d2820014
>04680916
>d2820015
>04662914
>d2060115
>02010115
>7e2a5b15
>101c2b0e
>102c1f0e
>101e2b18
>d2820013
>045a270f
>10242510
>10202b14
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>d2000012
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>04322310
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>d2000011
>00210112
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>1016190b
>c2028138
>bf8c007f
>10161605
>c2028139
>bf8c007f
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>042e1805
>1018190c
>c202813a
>bf8c007f
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>042e1805
>7e18550b
>10161911
>d00c0008
>0201010d
>d200000d
>00221a80
>101a190d
>c202813e
>c2040122
>bf8c007f
>7e220208
>d2820011
>04440b0c
>c2028142
>bf8c007f
>d2820011
>04440b0d
>c2028146
>bf8c007f
>d2820012
>04440b0b
>c2028149
>bf8c007f
>08220c05
>c2028148
>bf8c007f
>08121205
>100c1309
>d2820006
>041a2311
>c202814a
>bf8c007f
>08141405
>d2820006
>041a150a
>d2060106
>02010106
>7e265b06
>7e0c5513
>10280d13
>c202814c
>bf8c007f
>10282805
>c202814d
>bf8c007f
>d2820014
>04520c05
>100c0d06
>c202814e
>bf8c007f
>d2820006
>04520c05
>7e0c5506
>c2028152
>bf8c007f
>d2820014
>04480b06
>10242709
>1012250e
>102a2711
>d2820009
>04262b0f
>1026270a
>d282000a
>04262710
>d00c0008
>0201010a
>d2000009
>00221480
>10120d09
>c2028156
>bf8c007f
>d2820011
>04500b09
>080a0b15
>080e0f12
>10240f07
>d2820012
>044a0b05
>08101113
>d2820012
>044a1108
>d2060112
>02010112
>7e245b12
>100a2505
>100e2507
>100e0f0e
>d2820005
>041e0b0f
>100e2508
>d2820005
>04160f10
>d00c0008
>02010105
>d2000005
>00220a80
>7e0a4f05
>0e0a0a04
>7e0a4b05
>d0080004
>02021480
>d2000005
>00110105
>100e0d05
>c202015a
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>d2820005
>04440907
>d2060805
>02010105
>c202013d
>c2028121
>bf8c007f
>7e100205
>d2820008
>0420090c
>c2020141
>bf8c007f
>d2820008
>0420090d
>c2020145
>bf8c007f
>d2820008
>0420090b
>c2020151
>bf8c007f
>d2820008
>04200906
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>04200909
>c2020159
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>d2820008
>04200907
>d2060808
>02010108
>c202013c
>c2028120
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>0428090c
>c2020140
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>04180909
>c2020158
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>04180907
>d2060806
>02010106
>c2020123
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>d2060807
>02010004
>f800020f
>07050806
>c0820708
>bf8c000f
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>08070605
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>10000204
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>d2820000
>04000902
>c202010b
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>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  5: MOV OUT[0], TEMP[0]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %31 = fdiv float %28, %30
>  %32 = fdiv float %29, %30
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, %24
>  %43 = fmul float %39, %25
>  %44 = fmul float %40, %26
>  %45 = fmul float %41, %27
>  %46 = fmul float %42, 2.000000e+00
>  %47 = fmul float %43, 2.000000e+00
>  %48 = fmul float %44, 2.000000e+00
>  %49 = fmul float %45, 1.000000e+00
>  %50 = call float @llvm.AMDIL.clamp.(float %46, float 0.000000e+00, float 1.000000e+00)
>  %51 = call float @llvm.AMDIL.clamp.(float %47, float 0.000000e+00, float 1.000000e+00)
>  %52 = call float @llvm.AMDIL.clamp.(float %48, float 0.000000e+00, float 1.000000e+00)
>  %53 = call float @llvm.AMDIL.clamp.(float %49, float 0.000000e+00, float 1.000000e+00)
>  %54 = fcmp ugt float %53, 0x3FDFDFDFE0000000
>  %55 = sext i1 %54 to i32
>  %56 = trunc i32 %55 to i1
>  %57 = select i1 %56, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %57)
>  %58 = call i32 @llvm.SI.packf16(float %50, float %51)
>  %59 = bitcast i32 %58 to float
>  %60 = call i32 @llvm.SI.packf16(float %52, float %53)
>  %61 = bitcast i32 %60 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %59, float %61, float %59, float %61)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>d2060806
>02010106
>7e0e02ff
>3efefeff
>d0080000
>02020f06
>d2000007
>0001e4f3
>7c260e80
>c81c0100
>c81d0101
>10100f03
>d2820007
>04220f03
>d2060807
>02010107
>c8200000
>c8210001
>10121102
>d2820008
>04261102
>d2060808
>02010108
>5e0e0f08
>c8200200
>c8210201
>10001104
>d2820000
>04021104
>d2060800
>02010100
>5e000d00
>f8001c0f
>00070007
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..19]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: MOV OUT[2], IN[3]
> 41: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = extractelement <4 x float> %73, i32 3
>  %78 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %79 = load <16 x i8> addrspace(2)* %78, !tbaa !0
>  %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %79, i32 0, i32 %5)
>  %81 = extractelement <4 x float> %80, i32 0
>  %82 = extractelement <4 x float> %80, i32 1
>  %83 = extractelement <4 x float> %80, i32 2
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = extractelement <4 x float> %92, i32 3
>  %97 = fmul float %74, %11
>  %98 = fmul float %74, %12
>  %99 = fmul float %74, %13
>  %100 = fmul float %74, %14
>  %101 = fmul float %75, %15
>  %102 = fadd float %101, %97
>  %103 = fmul float %75, %16
>  %104 = fadd float %103, %98
>  %105 = fmul float %75, %17
>  %106 = fadd float %105, %99
>  %107 = fmul float %75, %18
>  %108 = fadd float %107, %100
>  %109 = fmul float %76, %19
>  %110 = fadd float %109, %102
>  %111 = fmul float %76, %20
>  %112 = fadd float %111, %104
>  %113 = fmul float %76, %21
>  %114 = fadd float %113, %106
>  %115 = fmul float %76, %22
>  %116 = fadd float %115, %108
>  %117 = fmul float %77, %23
>  %118 = fadd float %117, %110
>  %119 = fmul float %77, %24
>  %120 = fadd float %119, %112
>  %121 = fmul float %77, %25
>  %122 = fadd float %121, %114
>  %123 = fmul float %77, %26
>  %124 = fadd float %123, %116
>  %125 = fmul float %81, %27
>  %126 = fmul float %82, %28
>  %127 = fadd float %126, %125
>  %128 = fmul float %83, %29
>  %129 = fadd float %127, %128
>  %130 = fmul float %81, %30
>  %131 = fmul float %82, %31
>  %132 = fadd float %131, %130
>  %133 = fmul float %83, %32
>  %134 = fadd float %132, %133
>  %135 = fmul float %81, %33
>  %136 = fmul float %82, %34
>  %137 = fadd float %136, %135
>  %138 = fmul float %83, %35
>  %139 = fadd float %137, %138
>  %140 = fmul float %129, %129
>  %141 = fmul float %134, %134
>  %142 = fadd float %141, %140
>  %143 = fmul float %139, %139
>  %144 = fadd float %142, %143
>  %145 = call float @fabs(float %144)
>  %146 = call float @llvm.AMDGPU.rsq(float %145)
>  %147 = fmul float %129, %146
>  %148 = fmul float %134, %146
>  %149 = fmul float %139, %146
>  %150 = fmul float %37, %40
>  %151 = fadd float %150, %87
>  %152 = fmul float %38, %41
>  %153 = fadd float %152, %88
>  %154 = fmul float %39, %42
>  %155 = fadd float %154, %89
>  %156 = call float @llvm.AMDIL.clamp.(float %151, float 0.000000e+00, float 1.000000e+00)
>  %157 = call float @llvm.AMDIL.clamp.(float %153, float 0.000000e+00, float 1.000000e+00)
>  %158 = call float @llvm.AMDIL.clamp.(float %155, float 0.000000e+00, float 1.000000e+00)
>  %159 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %160 = fmul float %74, %47
>  %161 = fmul float %74, %48
>  %162 = fmul float %74, %49
>  %163 = fmul float %75, %50
>  %164 = fadd float %163, %160
>  %165 = fmul float %75, %51
>  %166 = fadd float %165, %161
>  %167 = fmul float %75, %52
>  %168 = fadd float %167, %162
>  %169 = fmul float %76, %53
>  %170 = fadd float %169, %164
>  %171 = fmul float %76, %54
>  %172 = fadd float %171, %166
>  %173 = fmul float %76, %55
>  %174 = fadd float %173, %168
>  %175 = fmul float %77, %56
>  %176 = fadd float %175, %170
>  %177 = fmul float %77, %57
>  %178 = fadd float %177, %172
>  %179 = fmul float %77, %58
>  %180 = fadd float %179, %174
>  %181 = fsub float %44, %176
>  %182 = fsub float %45, %178
>  %183 = fsub float %46, %180
>  %184 = fmul float %181, %181
>  %185 = fmul float %182, %182
>  %186 = fadd float %185, %184
>  %187 = fmul float %183, %183
>  %188 = fadd float %186, %187
>  %189 = call float @fabs(float %188)
>  %190 = call float @llvm.AMDGPU.rsq(float %189)
>  %191 = fmul float %181, %190
>  %192 = fmul float %182, %190
>  %193 = fmul float %183, %190
>  %194 = fdiv float 1.000000e+00, %190
>  %195 = fmul float %190, %194
>  %196 = fmul float %194, %194
>  %197 = fmul float %59, %195
>  %198 = fmul float %60, %194
>  %199 = fadd float %198, %197
>  %200 = fmul float %61, %196
>  %201 = fadd float %199, %200
>  %202 = fdiv float 1.000000e+00, %201
>  %203 = fmul float %176, %176
>  %204 = fmul float %178, %178
>  %205 = fadd float %204, %203
>  %206 = fmul float %180, %180
>  %207 = fadd float %205, %206
>  %208 = call float @fabs(float %207)
>  %209 = call float @llvm.AMDGPU.rsq(float %208)
>  %210 = fmul float %176, %209
>  %211 = fmul float %178, %209
>  %212 = fmul float %180, %209
>  %213 = fsub float %191, %210
>  %214 = fsub float %192, %211
>  %215 = fsub float %193, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fmul float %147, %191
>  %227 = fmul float %148, %192
>  %228 = fadd float %227, %226
>  %229 = fmul float %149, %193
>  %230 = fadd float %228, %229
>  %231 = fmul float %147, %223
>  %232 = fmul float %148, %224
>  %233 = fadd float %232, %231
>  %234 = fmul float %149, %225
>  %235 = fadd float %233, %234
>  %236 = fcmp uge float %230, 0.000000e+00
>  %237 = select i1 %236, float %230, float 0.000000e+00
>  %238 = fcmp uge float %235, 0.000000e+00
>  %239 = select i1 %238, float %235, float 0.000000e+00
>  %240 = call float @llvm.pow.f32(float %239, float %36)
>  %241 = call float @llvm.AMDGPU.cndlt(float %230, float 0.000000e+00, float %240)
>  %242 = fmul float 1.000000e+00, %202
>  %243 = fmul float %237, %202
>  %244 = fmul float %241, %202
>  %245 = fmul float %242, %62
>  %246 = fadd float %245, %151
>  %247 = fmul float %242, %63
>  %248 = fadd float %247, %153
>  %249 = fmul float %242, %64
>  %250 = fadd float %249, %155
>  %251 = fmul float %243, %65
>  %252 = fadd float %251, %246
>  %253 = fmul float %243, %66
>  %254 = fadd float %253, %248
>  %255 = fmul float %243, %67
>  %256 = fadd float %255, %250
>  %257 = fmul float %244, %68
>  %258 = fadd float %257, %252
>  %259 = fmul float %244, %69
>  %260 = fadd float %259, %254
>  %261 = fmul float %244, %70
>  %262 = fadd float %261, %256
>  %263 = call float @llvm.AMDIL.clamp.(float %258, float 0.000000e+00, float 1.000000e+00)
>  %264 = call float @llvm.AMDIL.clamp.(float %260, float 0.000000e+00, float 1.000000e+00)
>  %265 = call float @llvm.AMDIL.clamp.(float %262, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %263, float %264, float %265, float %159)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %93, float %94, float %95, float %96)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %118, float %120, float %122, float %124)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820005
>04140904
>c2020130
>bf8c007f
>100c0204
>c2020134
>bf8c007f
>d2820006
>04180902
>c2020138
>bf8c007f
>d2820006
>04180903
>c202013c
>bf8c007f
>d2820007
>04180904
>100c0f07
>d2820006
>041a0b05
>c2020132
>bf8c007f
>10100204
>c2020136
>bf8c007f
>d2820008
>04200902
>c202013a
>bf8c007f
>d2820008
>04200903
>c202013e
>bf8c007f
>d2820008
>04200904
>d2820006
>041a1108
>d2060106
>02010106
>7e125b06
>10141305
>c202012d
>bf8c007f
>080c0a04
>c202012c
>bf8c007f
>081a0e04
>100a1b0d
>d2820005
>04160d06
>c202012e
>bf8c007f
>08161004
>d2820005
>0416170b
>d2060105
>02010105
>7e0a5b05
>100c0b06
>08181506
>10141307
>100e0b0d
>081a1507
>10141b0d
>d282000a
>042a190c
>10121308
>10100b0b
>08121308
>d282000a
>042a1309
>d206010a
>0201010a
>7e145b0a
>1016150c
>1018150d
>c0840704
>bf8c007f
>e00c2000
>80020d00
>c2020114
>bf8c0070
>10221a04
>c2020115
>bf8c007f
>d2820011
>0444090e
>c2020116
>bf8c007f
>d2820011
>0444090f
>c2020110
>bf8c007f
>10241a04
>c2020111
>bf8c007f
>d2820012
>0448090e
>c2020112
>bf8c007f
>d2820012
>0448090f
>10262512
>d2820013
>044e2311
>c2020118
>bf8c007f
>10281a04
>c2020119
>bf8c007f
>d2820014
>0450090e
>c202011a
>bf8c007f
>d282000e
>0450090f
>d282000d
>044e1d0e
>d206010d
>0201010d
>7e1e5b0d
>101a1f12
>1020190d
>10181f11
>d282000b
>0442170c
>10141509
>10121f0e
>d282000a
>042e1509
>d00c0004
>0201010a
>d200000a
>00121480
>7e144f0a
>c202011c
>bf8c007f
>0e141404
>7e144b0a
>100e0f0d
>d2820006
>041e0d0c
>d2820007
>041a1109
>d0080004
>02020e80
>d2000008
>0011010a
>7e0c5505
>100a0d05
>c2020140
>bf8c007f
>100a0a04
>c2020141
>bf8c007f
>d2820005
>04160c04
>100c0d06
>c2020142
>bf8c007f
>d2820005
>04160c04
>7e0c5505
>100a0d08
>d00c0004
>02010107
>d2000007
>00120e80
>100e0d07
>c0840708
>bf8c007f
>e00c2000
>80020800
>c2020122
>c2028126
>bf8c0070
>7e180205
>d282000c
>042a1804
>c2020146
>bf8c007f
>d282000c
>04300906
>c202014a
>bf8c007f
>d282000c
>04300907
>c202014e
>bf8c007f
>d282000c
>04300905
>d206080c
>0201010c
>c2020121
>c2028125
>bf8c007f
>7e1a0205
>d282000d
>04261a04
>c2020145
>bf8c007f
>d282000d
>04340906
>c2020149
>bf8c007f
>d282000d
>04340907
>c202014d
>bf8c007f
>d282000d
>04340905
>d206080d
>0201010d
>c2020120
>c2028124
>bf8c007f
>7e1c0205
>d2820008
>04221c04
>c2020144
>bf8c007f
>d2820006
>04200906
>c2020148
>bf8c007f
>d2820006
>04180907
>c202014c
>bf8c007f
>d2820005
>04180905
>d2060805
>02010105
>c202012b
>bf8c007f
>d2060806
>02010004
>f800020f
>060c0d05
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL IN[3], GENERIC[2], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    1.0000,     2.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[2], 2D
>  3: TXP TEMP[1], IN[2], SAMP[1], CUBE
>  4: MOV TEMP[2].xy, IN[3].xyyy
>  5: MOV TEMP[2].w, IN[3].wwww
>  6: TXP TEMP[2], TEMP[2], SAMP[0], 2D
>  7: MAD TEMP[1].xyz, TEMP[0], TEMP[1].wwww, TEMP[1]
>  8: MOV_SAT TEMP[1].xyz, TEMP[1].xyzz
>  9: MOV TEMP[1].w, TEMP[0].wwww
> 10: ADD TEMP[0].x, IMM[0].xxxx, -TEMP[2].wwww
> 11: MUL TEMP[1], TEMP[1], TEMP[2].wwww
> 12: MAD TEMP[0].xyz, TEMP[2], TEMP[0].xxxx, TEMP[1]
> 13: MOV TEMP[0].xyz, TEMP[0].xyzx
> 14: MOV TEMP[0].w, TEMP[2].wwww
> 15: MUL TEMP[0].xyz, IN[0], TEMP[0]
> 16: MOV TEMP[0].xyz, TEMP[0].xyzx
> 17: MOV TEMP[0].w, TEMP[2].wwww
> 18: MUL_SAT TEMP[0], TEMP[0], IMM[0].yyyx
> 19: MOV OUT[0], TEMP[0]
> 20: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %45 = fdiv float %35, %37
>  %46 = fdiv float %36, %37
>  %47 = bitcast float %45 to i32
>  %48 = bitcast float %46 to i32
>  %49 = insertelement <2 x i32> undef, i32 %47, i32 0
>  %50 = insertelement <2 x i32> %49, i32 %48, i32 1
>  %51 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %50, <32 x i8> %29, <16 x i8> %31, i32 2)
>  %52 = extractelement <4 x float> %51, i32 0
>  %53 = extractelement <4 x float> %51, i32 1
>  %54 = extractelement <4 x float> %51, i32 2
>  %55 = fdiv float %38, %41
>  %56 = fdiv float %39, %41
>  %57 = fdiv float %40, %41
>  %58 = insertelement <4 x float> undef, float %55, i32 0
>  %59 = insertelement <4 x float> %58, float %56, i32 1
>  %60 = insertelement <4 x float> %59, float %57, i32 2
>  %61 = insertelement <4 x float> %60, float 1.000000e+00, i32 3
>  %62 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %61)
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = extractelement <4 x float> %62, i32 1
>  %65 = extractelement <4 x float> %62, i32 2
>  %66 = extractelement <4 x float> %62, i32 3
>  %67 = call float @fabs(float %65)
>  %68 = fdiv float 1.000000e+00, %67
>  %69 = fmul float %63, %68
>  %70 = fadd float %69, 1.500000e+00
>  %71 = fmul float %64, %68
>  %72 = fadd float %71, 1.500000e+00
>  %73 = bitcast float %72 to i32
>  %74 = bitcast float %70 to i32
>  %75 = bitcast float %66 to i32
>  %76 = insertelement <4 x i32> undef, i32 %73, i32 0
>  %77 = insertelement <4 x i32> %76, i32 %74, i32 1
>  %78 = insertelement <4 x i32> %77, i32 %75, i32 2
>  %79 = insertelement <4 x i32> %78, i32 undef, i32 3
>  %80 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %79, <32 x i8> %25, <16 x i8> %27, i32 4)
>  %81 = extractelement <4 x float> %80, i32 0
>  %82 = extractelement <4 x float> %80, i32 1
>  %83 = extractelement <4 x float> %80, i32 2
>  %84 = extractelement <4 x float> %80, i32 3
>  %85 = fdiv float %42, %44
>  %86 = fdiv float %43, %44
>  %87 = bitcast float %85 to i32
>  %88 = bitcast float %86 to i32
>  %89 = insertelement <2 x i32> undef, i32 %87, i32 0
>  %90 = insertelement <2 x i32> %89, i32 %88, i32 1
>  %91 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %90, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %92 = extractelement <4 x float> %91, i32 0
>  %93 = extractelement <4 x float> %91, i32 1
>  %94 = extractelement <4 x float> %91, i32 2
>  %95 = extractelement <4 x float> %91, i32 3
>  %96 = fmul float %52, %84
>  %97 = fadd float %96, %81
>  %98 = fmul float %53, %84
>  %99 = fadd float %98, %82
>  %100 = fmul float %54, %84
>  %101 = fadd float %100, %83
>  %102 = call float @llvm.AMDIL.clamp.(float %97, float 0.000000e+00, float 1.000000e+00)
>  %103 = call float @llvm.AMDIL.clamp.(float %99, float 0.000000e+00, float 1.000000e+00)
>  %104 = call float @llvm.AMDIL.clamp.(float %101, float 0.000000e+00, float 1.000000e+00)
>  %105 = fsub float -0.000000e+00, %95
>  %106 = fadd float 1.000000e+00, %105
>  %107 = fmul float %102, %95
>  %108 = fmul float %103, %95
>  %109 = fmul float %104, %95
>  %110 = fmul float %92, %106
>  %111 = fadd float %110, %107
>  %112 = fmul float %93, %106
>  %113 = fadd float %112, %108
>  %114 = fmul float %94, %106
>  %115 = fadd float %114, %109
>  %116 = fmul float %32, %111
>  %117 = fmul float %33, %113
>  %118 = fmul float %34, %115
>  %119 = fmul float %116, 2.000000e+00
>  %120 = fmul float %117, 2.000000e+00
>  %121 = fmul float %118, 2.000000e+00
>  %122 = fmul float %95, 1.000000e+00
>  %123 = call float @llvm.AMDIL.clamp.(float %119, float 0.000000e+00, float 1.000000e+00)
>  %124 = call float @llvm.AMDIL.clamp.(float %120, float 0.000000e+00, float 1.000000e+00)
>  %125 = call float @llvm.AMDIL.clamp.(float %121, float 0.000000e+00, float 1.000000e+00)
>  %126 = call float @llvm.AMDIL.clamp.(float %122, float 0.000000e+00, float 1.000000e+00)
>  %127 = call i32 @llvm.SI.packf16(float %123, float %124)
>  %128 = bitcast i32 %127 to float
>  %129 = call i32 @llvm.SI.packf16(float %125, float %126)
>  %130 = bitcast i32 %129 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %128, float %130, float %128, float %130)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e0c5503
>10060d02
>c81c0800
>c81d0801
>10040d07
>c81c0a00
>c81d0a01
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430207
>c8180500
>c8190501
>c81c0700
>c81d0701
>7e105507
>100e1106
>c8240400
>c8250401
>100c1109
>c0840308
>c0c60510
>bf8c0070
>f0800700
>00430606
>bf8c0770
>d2820009
>040e0b07
>d206080d
>02010109
>c8240d00
>c8250d01
>c8280f00
>c8290f01
>7e16550a
>10141709
>c8300c00
>c8310c01
>1012170c
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020909
>bf8c0770
>101c190d
>081a18f2
>d282000e
>043a1b0a
>c83c0100
>c83d0101
>10201d0f
>d282000e
>04421d0f
>d206080e
>0201010e
>d282000f
>040a0b06
>d206080f
>0201010f
>101e190f
>d282000f
>043e1b09
>c8400000
>c8410001
>10221f10
>d282000f
>04461f10
>d206080f
>0201010f
>5e1c1d0f
>d2820002
>04120b08
>d2060802
>02010102
>10041902
>d2820002
>040a1b0b
>c80c0200
>c80d0201
>10000503
>d2820000
>04020503
>d2060800
>02010100
>d2060801
>0201010c
>5e000300
>f8001c0f
>000e000e
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..14]
>DCL TEMP[0..3]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MOV OUT[2], IN[3]
> 15: MUL TEMP[1], IN[0].xxxx, CONST[11]
> 16: MAD TEMP[1], IN[0].yyyy, CONST[12], TEMP[1]
> 17: MAD TEMP[1], IN[0].zzzz, CONST[13], TEMP[1]
> 18: MAD TEMP[1], IN[0].wwww, CONST[14], TEMP[1]
> 19: DP3 TEMP[3].x, TEMP[1], TEMP[1]
> 20: RSQ TEMP[3].x, |TEMP[3]|
> 21: MUL TEMP[2], TEMP[1], TEMP[3].xxxx
> 22: DP3 TEMP[3], TEMP[0], TEMP[2]
> 23: ADD TEMP[3], TEMP[3], TEMP[3]
> 24: MAD OUT[3].xyz, -TEMP[3], TEMP[0], TEMP[2]
> 25: MOV OUT[3].w, IN[4]
> 26: MOV OUT[4], IN[5]
> 27: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
>  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
>  %58 = extractelement <4 x float> %57, i32 0
>  %59 = extractelement <4 x float> %57, i32 1
>  %60 = extractelement <4 x float> %57, i32 2
>  %61 = extractelement <4 x float> %57, i32 3
>  %62 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %63 = load <16 x i8> addrspace(2)* %62, !tbaa !0
>  %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %63, i32 0, i32 %5)
>  %65 = extractelement <4 x float> %64, i32 0
>  %66 = extractelement <4 x float> %64, i32 1
>  %67 = extractelement <4 x float> %64, i32 2
>  %68 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
>  %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %69, i32 0, i32 %5)
>  %71 = extractelement <4 x float> %70, i32 0
>  %72 = extractelement <4 x float> %70, i32 1
>  %73 = extractelement <4 x float> %70, i32 2
>  %74 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %75 = load <16 x i8> addrspace(2)* %74, !tbaa !0
>  %76 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %75, i32 0, i32 %5)
>  %77 = extractelement <4 x float> %76, i32 0
>  %78 = extractelement <4 x float> %76, i32 1
>  %79 = extractelement <4 x float> %76, i32 2
>  %80 = extractelement <4 x float> %76, i32 3
>  %81 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %82 = load <16 x i8> addrspace(2)* %81, !tbaa !0
>  %83 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %82, i32 0, i32 %5)
>  %84 = extractelement <4 x float> %83, i32 3
>  %85 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %86 = load <16 x i8> addrspace(2)* %85, !tbaa !0
>  %87 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %86, i32 0, i32 %5)
>  %88 = extractelement <4 x float> %87, i32 0
>  %89 = extractelement <4 x float> %87, i32 1
>  %90 = extractelement <4 x float> %87, i32 2
>  %91 = extractelement <4 x float> %87, i32 3
>  %92 = fmul float %58, %11
>  %93 = fmul float %58, %12
>  %94 = fmul float %58, %13
>  %95 = fmul float %58, %14
>  %96 = fmul float %59, %15
>  %97 = fadd float %96, %92
>  %98 = fmul float %59, %16
>  %99 = fadd float %98, %93
>  %100 = fmul float %59, %17
>  %101 = fadd float %100, %94
>  %102 = fmul float %59, %18
>  %103 = fadd float %102, %95
>  %104 = fmul float %60, %19
>  %105 = fadd float %104, %97
>  %106 = fmul float %60, %20
>  %107 = fadd float %106, %99
>  %108 = fmul float %60, %21
>  %109 = fadd float %108, %101
>  %110 = fmul float %60, %22
>  %111 = fadd float %110, %103
>  %112 = fmul float %61, %23
>  %113 = fadd float %112, %105
>  %114 = fmul float %61, %24
>  %115 = fadd float %114, %107
>  %116 = fmul float %61, %25
>  %117 = fadd float %116, %109
>  %118 = fmul float %61, %26
>  %119 = fadd float %118, %111
>  %120 = fmul float %65, %27
>  %121 = fmul float %66, %28
>  %122 = fadd float %121, %120
>  %123 = fmul float %67, %29
>  %124 = fadd float %122, %123
>  %125 = fmul float %65, %30
>  %126 = fmul float %66, %31
>  %127 = fadd float %126, %125
>  %128 = fmul float %67, %32
>  %129 = fadd float %127, %128
>  %130 = fmul float %65, %33
>  %131 = fmul float %66, %34
>  %132 = fadd float %131, %130
>  %133 = fmul float %67, %35
>  %134 = fadd float %132, %133
>  %135 = fmul float %124, %124
>  %136 = fmul float %129, %129
>  %137 = fadd float %136, %135
>  %138 = fmul float %134, %134
>  %139 = fadd float %137, %138
>  %140 = call float @fabs(float %139)
>  %141 = call float @llvm.AMDGPU.rsq(float %140)
>  %142 = fmul float %124, %141
>  %143 = fmul float %129, %141
>  %144 = fmul float %134, %141
>  %145 = fmul float %36, %39
>  %146 = fadd float %145, %71
>  %147 = fmul float %37, %40
>  %148 = fadd float %147, %72
>  %149 = fmul float %38, %41
>  %150 = fadd float %149, %73
>  %151 = call float @llvm.AMDIL.clamp.(float %146, float 0.000000e+00, float 1.000000e+00)
>  %152 = call float @llvm.AMDIL.clamp.(float %148, float 0.000000e+00, float 1.000000e+00)
>  %153 = call float @llvm.AMDIL.clamp.(float %150, float 0.000000e+00, float 1.000000e+00)
>  %154 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %155 = fmul float %58, %43
>  %156 = fmul float %58, %44
>  %157 = fmul float %58, %45
>  %158 = fmul float %59, %46
>  %159 = fadd float %158, %155
>  %160 = fmul float %59, %47
>  %161 = fadd float %160, %156
>  %162 = fmul float %59, %48
>  %163 = fadd float %162, %157
>  %164 = fmul float %60, %49
>  %165 = fadd float %164, %159
>  %166 = fmul float %60, %50
>  %167 = fadd float %166, %161
>  %168 = fmul float %60, %51
>  %169 = fadd float %168, %163
>  %170 = fmul float %61, %52
>  %171 = fadd float %170, %165
>  %172 = fmul float %61, %53
>  %173 = fadd float %172, %167
>  %174 = fmul float %61, %54
>  %175 = fadd float %174, %169
>  %176 = fmul float %171, %171
>  %177 = fmul float %173, %173
>  %178 = fadd float %177, %176
>  %179 = fmul float %175, %175
>  %180 = fadd float %178, %179
>  %181 = call float @fabs(float %180)
>  %182 = call float @llvm.AMDGPU.rsq(float %181)
>  %183 = fmul float %171, %182
>  %184 = fmul float %173, %182
>  %185 = fmul float %175, %182
>  %186 = fmul float %142, %183
>  %187 = fmul float %143, %184
>  %188 = fadd float %187, %186
>  %189 = fmul float %144, %185
>  %190 = fadd float %188, %189
>  %191 = fadd float %190, %190
>  %192 = fadd float %190, %190
>  %193 = fadd float %190, %190
>  %194 = fsub float -0.000000e+00, %191
>  %195 = fmul float %194, %142
>  %196 = fadd float %195, %183
>  %197 = fsub float -0.000000e+00, %192
>  %198 = fmul float %197, %143
>  %199 = fadd float %198, %184
>  %200 = fsub float -0.000000e+00, %193
>  %201 = fmul float %200, %144
>  %202 = fadd float %201, %185
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %151, float %152, float %153, float %154)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %77, float %78, float %79, float %80)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %196, float %199, float %202, float %84)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %88, float %89, float %90, float %91)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %113, float %115, float %117, float %119)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0840704
>bf8c000f
>e00c2000
>80020100
>c2020114
>bf8c0070
>100a0204
>c2020115
>bf8c007f
>d2820005
>04140902
>c2020116
>bf8c007f
>d2820005
>04140903
>c2020110
>bf8c007f
>100c0204
>c2020111
>bf8c007f
>d2820006
>04180902
>c2020112
>bf8c007f
>d2820006
>04180903
>100e0d06
>d2820008
>041e0b05
>c2020118
>bf8c007f
>100e0204
>c2020119
>bf8c007f
>d2820007
>041c0902
>c202011a
>bf8c007f
>d2820007
>041c0903
>d2820001
>04220f07
>d2060101
>02010101
>7e105b01
>100c1106
>c0840700
>bf8c007f
>e00c2000
>80020100
>c202012d
>bf8c0070
>10120204
>c2020131
>bf8c007f
>d2820009
>04240902
>c2020135
>bf8c007f
>d2820009
>04240903
>c2020139
>bf8c007f
>d2820009
>04240904
>c202012c
>bf8c007f
>10140204
>c2020130
>bf8c007f
>d282000a
>04280902
>c2020134
>bf8c007f
>d282000a
>04280903
>c2020138
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c202012e
>bf8c007f
>10160204
>c2020132
>bf8c007f
>d282000b
>042c0902
>c2020136
>bf8c007f
>d282000b
>042c0903
>c202013a
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101a1506
>100a1105
>10121909
>d282000d
>04361305
>100e1107
>1016190b
>d2820008
>04361707
>06101108
>100e0f08
>080e0f0b
>100a0b08
>080a0b09
>100c0d08
>080c0d0a
>c0840710
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800022f
>0b070506
>c0820714
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..10]
>DCL TEMP[0..3]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MOV OUT[2], IN[3]
> 15: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %57 = load <16 x i8> addrspace(2)* %56, !tbaa !0
>  %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %57, i32 0, i32 %5)
>  %59 = extractelement <4 x float> %58, i32 0
>  %60 = extractelement <4 x float> %58, i32 1
>  %61 = extractelement <4 x float> %58, i32 2
>  %62 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %63 = load <16 x i8> addrspace(2)* %62, !tbaa !0
>  %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %63, i32 0, i32 %5)
>  %65 = extractelement <4 x float> %64, i32 0
>  %66 = extractelement <4 x float> %64, i32 1
>  %67 = extractelement <4 x float> %64, i32 2
>  %68 = extractelement <4 x float> %64, i32 3
>  %69 = fmul float %46, %11
>  %70 = fmul float %46, %12
>  %71 = fmul float %46, %13
>  %72 = fmul float %46, %14
>  %73 = fmul float %47, %15
>  %74 = fadd float %73, %69
>  %75 = fmul float %47, %16
>  %76 = fadd float %75, %70
>  %77 = fmul float %47, %17
>  %78 = fadd float %77, %71
>  %79 = fmul float %47, %18
>  %80 = fadd float %79, %72
>  %81 = fmul float %48, %19
>  %82 = fadd float %81, %74
>  %83 = fmul float %48, %20
>  %84 = fadd float %83, %76
>  %85 = fmul float %48, %21
>  %86 = fadd float %85, %78
>  %87 = fmul float %48, %22
>  %88 = fadd float %87, %80
>  %89 = fmul float %49, %23
>  %90 = fadd float %89, %82
>  %91 = fmul float %49, %24
>  %92 = fadd float %91, %84
>  %93 = fmul float %49, %25
>  %94 = fadd float %93, %86
>  %95 = fmul float %49, %26
>  %96 = fadd float %95, %88
>  %97 = fmul float %53, %27
>  %98 = fmul float %54, %28
>  %99 = fadd float %98, %97
>  %100 = fmul float %55, %29
>  %101 = fadd float %99, %100
>  %102 = fmul float %53, %30
>  %103 = fmul float %54, %31
>  %104 = fadd float %103, %102
>  %105 = fmul float %55, %32
>  %106 = fadd float %104, %105
>  %107 = fmul float %53, %33
>  %108 = fmul float %54, %34
>  %109 = fadd float %108, %107
>  %110 = fmul float %55, %35
>  %111 = fadd float %109, %110
>  %112 = fmul float %101, %101
>  %113 = fmul float %106, %106
>  %114 = fadd float %113, %112
>  %115 = fmul float %111, %111
>  %116 = fadd float %114, %115
>  %117 = call float @fabs(float %116)
>  %118 = call float @llvm.AMDGPU.rsq(float %117)
>  %119 = fmul float %36, %39
>  %120 = fadd float %119, %59
>  %121 = fmul float %37, %40
>  %122 = fadd float %121, %60
>  %123 = fmul float %38, %41
>  %124 = fadd float %123, %61
>  %125 = call float @llvm.AMDIL.clamp.(float %120, float 0.000000e+00, float 1.000000e+00)
>  %126 = call float @llvm.AMDIL.clamp.(float %122, float 0.000000e+00, float 1.000000e+00)
>  %127 = call float @llvm.AMDIL.clamp.(float %124, float 0.000000e+00, float 1.000000e+00)
>  %128 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %125, float %126, float %127, float %128)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %65, float %66, float %67, float %68)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %90, float %92, float %94, float %96)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL IN[3], GENERIC[2], PERSPECTIVE
>DCL IN[4], GENERIC[4], PERSPECTIVE
>DCL IN[5], GENERIC[5], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL SAMP[4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     2.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[4], 2D
>  3: TXP TEMP[1], IN[2], SAMP[3], CUBE
>  4: MOV TEMP[2].xy, IN[3].xyyy
>  5: MOV TEMP[2].w, IN[3].wwww
>  6: TXP TEMP[2], TEMP[2], SAMP[2], 2D
>  7: MAD TEMP[1].xyz, TEMP[0], TEMP[1].wwww, TEMP[1]
>  8: MOV_SAT TEMP[1].xyz, TEMP[1].xyzz
>  9: MOV TEMP[1].w, TEMP[0].wwww
> 10: ADD TEMP[0].x, IMM[0].xxxx, -TEMP[2].wwww
> 11: MUL TEMP[1], TEMP[1], TEMP[2].wwww
> 12: MAD TEMP[0].xyz, TEMP[2], TEMP[0].xxxx, TEMP[1]
> 13: MOV TEMP[0].xyz, TEMP[0].xyzx
> 14: MOV TEMP[0].w, TEMP[2].wwww
> 15: MUL TEMP[0].xyz, IN[0], TEMP[0]
> 16: MOV TEMP[0].xyz, TEMP[0].xyzx
> 17: MOV TEMP[0].w, TEMP[2].wwww
> 18: MUL_SAT TEMP[0], TEMP[0], IMM[0].yyyx
> 19: MOV TEMP[0].xyz, TEMP[0].xyzx
> 20: MOV TEMP[1].xy, IN[4].xyyy
> 21: MOV TEMP[1].w, IN[4].wwww
> 22: TXP TEMP[1].w, TEMP[1], SAMP[1], 2D
> 23: MOV TEMP[0].w, TEMP[1].wwww
> 24: ADD TEMP[2].x, IMM[0].xxxx, -TEMP[1].wwww
> 25: MOV TEMP[3].xy, IN[5].xyyy
> 26: MOV TEMP[3].w, IN[5].wwww
> 27: TXP TEMP[3], TEMP[3], SAMP[0], 2D
> 28: MUL TEMP[3], TEMP[3], TEMP[1].wwww
> 29: MAD TEMP[0].xyz, TEMP[0], TEMP[2].xxxx, TEMP[3]
> 30: MOV TEMP[0].xyz, TEMP[0].xyzx
> 31: MOV TEMP[0].w, TEMP[1].wwww
> 32: MOV OUT[0], TEMP[0]
> 33: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
>  %33 = load <32 x i8> addrspace(2)* %32, !tbaa !0
>  %34 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
>  %37 = load <32 x i8> addrspace(2)* %36, !tbaa !0
>  %38 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %46 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %47 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %48 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
>  %49 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %50 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %51 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %52 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %53 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %54 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %55 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %56 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
>  %57 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
>  %58 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %3, <2 x i32> %5)
>  %59 = fdiv float %43, %45
>  %60 = fdiv float %44, %45
>  %61 = bitcast float %59 to i32
>  %62 = bitcast float %60 to i32
>  %63 = insertelement <2 x i32> undef, i32 %61, i32 0
>  %64 = insertelement <2 x i32> %63, i32 %62, i32 1
>  %65 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %64, <32 x i8> %37, <16 x i8> %39, i32 2)
>  %66 = extractelement <4 x float> %65, i32 0
>  %67 = extractelement <4 x float> %65, i32 1
>  %68 = extractelement <4 x float> %65, i32 2
>  %69 = fdiv float %46, %49
>  %70 = fdiv float %47, %49
>  %71 = fdiv float %48, %49
>  %72 = insertelement <4 x float> undef, float %69, i32 0
>  %73 = insertelement <4 x float> %72, float %70, i32 1
>  %74 = insertelement <4 x float> %73, float %71, i32 2
>  %75 = insertelement <4 x float> %74, float 1.000000e+00, i32 3
>  %76 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %75)
>  %77 = extractelement <4 x float> %76, i32 0
>  %78 = extractelement <4 x float> %76, i32 1
>  %79 = extractelement <4 x float> %76, i32 2
>  %80 = extractelement <4 x float> %76, i32 3
>  %81 = call float @fabs(float %79)
>  %82 = fdiv float 1.000000e+00, %81
>  %83 = fmul float %77, %82
>  %84 = fadd float %83, 1.500000e+00
>  %85 = fmul float %78, %82
>  %86 = fadd float %85, 1.500000e+00
>  %87 = bitcast float %86 to i32
>  %88 = bitcast float %84 to i32
>  %89 = bitcast float %80 to i32
>  %90 = insertelement <4 x i32> undef, i32 %87, i32 0
>  %91 = insertelement <4 x i32> %90, i32 %88, i32 1
>  %92 = insertelement <4 x i32> %91, i32 %89, i32 2
>  %93 = insertelement <4 x i32> %92, i32 undef, i32 3
>  %94 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %93, <32 x i8> %33, <16 x i8> %35, i32 4)
>  %95 = extractelement <4 x float> %94, i32 0
>  %96 = extractelement <4 x float> %94, i32 1
>  %97 = extractelement <4 x float> %94, i32 2
>  %98 = extractelement <4 x float> %94, i32 3
>  %99 = fdiv float %50, %52
>  %100 = fdiv float %51, %52
>  %101 = bitcast float %99 to i32
>  %102 = bitcast float %100 to i32
>  %103 = insertelement <2 x i32> undef, i32 %101, i32 0
>  %104 = insertelement <2 x i32> %103, i32 %102, i32 1
>  %105 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %104, <32 x i8> %29, <16 x i8> %31, i32 2)
>  %106 = extractelement <4 x float> %105, i32 0
>  %107 = extractelement <4 x float> %105, i32 1
>  %108 = extractelement <4 x float> %105, i32 2
>  %109 = extractelement <4 x float> %105, i32 3
>  %110 = fmul float %66, %98
>  %111 = fadd float %110, %95
>  %112 = fmul float %67, %98
>  %113 = fadd float %112, %96
>  %114 = fmul float %68, %98
>  %115 = fadd float %114, %97
>  %116 = call float @llvm.AMDIL.clamp.(float %111, float 0.000000e+00, float 1.000000e+00)
>  %117 = call float @llvm.AMDIL.clamp.(float %113, float 0.000000e+00, float 1.000000e+00)
>  %118 = call float @llvm.AMDIL.clamp.(float %115, float 0.000000e+00, float 1.000000e+00)
>  %119 = fsub float -0.000000e+00, %109
>  %120 = fadd float 1.000000e+00, %119
>  %121 = fmul float %116, %109
>  %122 = fmul float %117, %109
>  %123 = fmul float %118, %109
>  %124 = fmul float %106, %120
>  %125 = fadd float %124, %121
>  %126 = fmul float %107, %120
>  %127 = fadd float %126, %122
>  %128 = fmul float %108, %120
>  %129 = fadd float %128, %123
>  %130 = fmul float %40, %125
>  %131 = fmul float %41, %127
>  %132 = fmul float %42, %129
>  %133 = fmul float %130, 2.000000e+00
>  %134 = fmul float %131, 2.000000e+00
>  %135 = fmul float %132, 2.000000e+00
>  %136 = fmul float %109, 1.000000e+00
>  %137 = call float @llvm.AMDIL.clamp.(float %133, float 0.000000e+00, float 1.000000e+00)
>  %138 = call float @llvm.AMDIL.clamp.(float %134, float 0.000000e+00, float 1.000000e+00)
>  %139 = call float @llvm.AMDIL.clamp.(float %135, float 0.000000e+00, float 1.000000e+00)
>  %140 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
>  %141 = fdiv float %53, %55
>  %142 = fdiv float %54, %55
>  %143 = bitcast float %141 to i32
>  %144 = bitcast float %142 to i32
>  %145 = insertelement <2 x i32> undef, i32 %143, i32 0
>  %146 = insertelement <2 x i32> %145, i32 %144, i32 1
>  %147 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %146, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %148 = extractelement <4 x float> %147, i32 3
>  %149 = fsub float -0.000000e+00, %148
>  %150 = fadd float 1.000000e+00, %149
>  %151 = fdiv float %56, %58
>  %152 = fdiv float %57, %58
>  %153 = bitcast float %151 to i32
>  %154 = bitcast float %152 to i32
>  %155 = insertelement <2 x i32> undef, i32 %153, i32 0
>  %156 = insertelement <2 x i32> %155, i32 %154, i32 1
>  %157 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %156, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %158 = extractelement <4 x float> %157, i32 0
>  %159 = extractelement <4 x float> %157, i32 1
>  %160 = extractelement <4 x float> %157, i32 2
>  %161 = fmul float %158, %148
>  %162 = fmul float %159, %148
>  %163 = fmul float %160, %148
>  %164 = fmul float %137, %150
>  %165 = fadd float %164, %161
>  %166 = fmul float %138, %150
>  %167 = fadd float %166, %162
>  %168 = fmul float %139, %150
>  %169 = fadd float %168, %163
>  %170 = call i32 @llvm.SI.packf16(float %165, float %167)
>  %171 = bitcast i32 %170 to float
>  %172 = call i32 @llvm.SI.packf16(float %169, float %148)
>  %173 = bitcast i32 %172 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %171, float %173, float %171, float %173)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e0c5503
>10060d02
>c81c0800
>c81d0801
>10040d07
>c81c0a00
>c81d0a01
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c084030c
>c0c60518
>bf8c007f
>f0800f00
>00430207
>c8180500
>c8190501
>c81c0700
>c81d0701
>7e105507
>100e1106
>c8240400
>c8250401
>100c1109
>c0840310
>c0c60520
>bf8c0070
>f0800700
>00430606
>bf8c0770
>d2820009
>040e0b07
>d206080d
>02010109
>c8240d00
>c8250d01
>c8280f00
>c8290f01
>7e16550a
>10141709
>c8300c00
>c8310c01
>1012170c
>c0840308
>c0c60510
>bf8c007f
>f0800f00
>00430909
>bf8c0770
>101c190d
>081a18f2
>d282000e
>043a1b0a
>c83c0100
>c83d0101
>10201d0f
>d282000e
>04421d0f
>d206080f
>0201010e
>c8381100
>c8391101
>c8401300
>c8411301
>7e245510
>1022250e
>c8381000
>c8391001
>1020250e
>c0840304
>c0c60508
>bf8c007f
>f0800800
>00430e10
>c8401500
>c8411501
>c8441700
>c8451701
>7e245511
>10222510
>c84c1400
>c84d1401
>10202513
>c0800300
>c0c40500
>bf8c0070
>f0800700
>00021010
>bf8c0770
>10281d11
>08261cf2
>d282000f
>0452270f
>d2820014
>040a0b06
>d2060814
>02010114
>10281914
>d2820014
>04521b09
>c8540000
>c8550001
>102c2915
>d2820014
>045a2915
>d2060814
>02010114
>102a1d10
>d2820014
>04562714
>5e1e1f14
>d2820002
>04120b08
>d2060802
>02010102
>10041902
>d2820002
>040a1b0b
>c80c0200
>c80d0201
>10000503
>d2820000
>04020503
>d2060800
>02010100
>10021d12
>d2820000
>04062700
>5e001d00
>f8001c0f
>000f000f
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL IN[6]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL OUT[5], GENERIC[4]
>DCL OUT[6], GENERIC[5]
>DCL CONST[0..32]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD TEMP[3], TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: SUB TEMP[5], CONST[28], TEMP[4]
> 78: DP3 TEMP[7], TEMP[5], TEMP[5]
> 79: RSQ TEMP[7], |TEMP[7]|
> 80: MUL TEMP[5], TEMP[5], TEMP[7]
> 81: RCP TEMP[7].yz, TEMP[7]
> 82: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 83: DP3 TEMP[7], CONST[29], TEMP[7]
> 84: RCP TEMP[8], TEMP[7]
> 85: SUB TEMP[7], TEMP[5], TEMP[6]
> 86: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 87: RSQ TEMP[9].x, |TEMP[9]|
> 88: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 89: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 90: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 91: LIT TEMP[1], TEMP[2]
> 92: MUL TEMP[1], TEMP[1], TEMP[8]
> 93: MAD TEMP[3], TEMP[1].xxxx, CONST[30], TEMP[3]
> 94: MAD TEMP[3], TEMP[1].yyyy, CONST[31], TEMP[3]
> 95: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[32], TEMP[3]
> 96: MOV OUT[2], IN[2]
> 97: DP3 TEMP[1], TEMP[0], TEMP[6]
> 98: ADD TEMP[1], TEMP[1], TEMP[1]
> 99: MAD OUT[3].xyz, -TEMP[1], TEMP[0], TEMP[6]
>100: MOV OUT[3].w, IN[3]
>101: MOV OUT[4], IN[4]
>102: MOV OUT[5], IN[5]
>103: MOV OUT[6], IN[6]
>104: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %113 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %114 = load <16 x i8> addrspace(2)* %113, !tbaa !0
>  %115 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %114, i32 0, i32 %5)
>  %116 = extractelement <4 x float> %115, i32 0
>  %117 = extractelement <4 x float> %115, i32 1
>  %118 = extractelement <4 x float> %115, i32 2
>  %119 = extractelement <4 x float> %115, i32 3
>  %120 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
>  %122 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %121, i32 0, i32 %5)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = extractelement <4 x float> %122, i32 1
>  %125 = extractelement <4 x float> %122, i32 2
>  %126 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %127 = load <16 x i8> addrspace(2)* %126, !tbaa !0
>  %128 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %127, i32 0, i32 %5)
>  %129 = extractelement <4 x float> %128, i32 0
>  %130 = extractelement <4 x float> %128, i32 1
>  %131 = extractelement <4 x float> %128, i32 2
>  %132 = extractelement <4 x float> %128, i32 3
>  %133 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %134 = load <16 x i8> addrspace(2)* %133, !tbaa !0
>  %135 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %134, i32 0, i32 %5)
>  %136 = extractelement <4 x float> %135, i32 3
>  %137 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %138 = load <16 x i8> addrspace(2)* %137, !tbaa !0
>  %139 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %138, i32 0, i32 %5)
>  %140 = extractelement <4 x float> %139, i32 0
>  %141 = extractelement <4 x float> %139, i32 1
>  %142 = extractelement <4 x float> %139, i32 2
>  %143 = extractelement <4 x float> %139, i32 3
>  %144 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %145 = load <16 x i8> addrspace(2)* %144, !tbaa !0
>  %146 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %145, i32 0, i32 %5)
>  %147 = extractelement <4 x float> %146, i32 0
>  %148 = extractelement <4 x float> %146, i32 1
>  %149 = extractelement <4 x float> %146, i32 2
>  %150 = extractelement <4 x float> %146, i32 3
>  %151 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
>  %152 = load <16 x i8> addrspace(2)* %151, !tbaa !0
>  %153 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %152, i32 0, i32 %5)
>  %154 = extractelement <4 x float> %153, i32 0
>  %155 = extractelement <4 x float> %153, i32 1
>  %156 = extractelement <4 x float> %153, i32 2
>  %157 = extractelement <4 x float> %153, i32 3
>  %158 = fmul float %116, %11
>  %159 = fmul float %116, %12
>  %160 = fmul float %116, %13
>  %161 = fmul float %116, %14
>  %162 = fmul float %117, %15
>  %163 = fadd float %162, %158
>  %164 = fmul float %117, %16
>  %165 = fadd float %164, %159
>  %166 = fmul float %117, %17
>  %167 = fadd float %166, %160
>  %168 = fmul float %117, %18
>  %169 = fadd float %168, %161
>  %170 = fmul float %118, %19
>  %171 = fadd float %170, %163
>  %172 = fmul float %118, %20
>  %173 = fadd float %172, %165
>  %174 = fmul float %118, %21
>  %175 = fadd float %174, %167
>  %176 = fmul float %118, %22
>  %177 = fadd float %176, %169
>  %178 = fmul float %119, %23
>  %179 = fadd float %178, %171
>  %180 = fmul float %119, %24
>  %181 = fadd float %180, %173
>  %182 = fmul float %119, %25
>  %183 = fadd float %182, %175
>  %184 = fmul float %119, %26
>  %185 = fadd float %184, %177
>  %186 = fmul float %123, %27
>  %187 = fmul float %124, %28
>  %188 = fadd float %187, %186
>  %189 = fmul float %125, %29
>  %190 = fadd float %188, %189
>  %191 = fmul float %123, %30
>  %192 = fmul float %124, %31
>  %193 = fadd float %192, %191
>  %194 = fmul float %125, %32
>  %195 = fadd float %193, %194
>  %196 = fmul float %123, %33
>  %197 = fmul float %124, %34
>  %198 = fadd float %197, %196
>  %199 = fmul float %125, %35
>  %200 = fadd float %198, %199
>  %201 = fmul float %190, %190
>  %202 = fmul float %195, %195
>  %203 = fadd float %202, %201
>  %204 = fmul float %200, %200
>  %205 = fadd float %203, %204
>  %206 = call float @fabs(float %205)
>  %207 = call float @llvm.AMDGPU.rsq(float %206)
>  %208 = fmul float %190, %207
>  %209 = fmul float %195, %207
>  %210 = fmul float %200, %207
>  %211 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %212 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %213 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %214 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %215 = fmul float %116, %44
>  %216 = fmul float %116, %45
>  %217 = fmul float %116, %46
>  %218 = fmul float %117, %47
>  %219 = fadd float %218, %215
>  %220 = fmul float %117, %48
>  %221 = fadd float %220, %216
>  %222 = fmul float %117, %49
>  %223 = fadd float %222, %217
>  %224 = fmul float %118, %50
>  %225 = fadd float %224, %219
>  %226 = fmul float %118, %51
>  %227 = fadd float %226, %221
>  %228 = fmul float %118, %52
>  %229 = fadd float %228, %223
>  %230 = fmul float %119, %53
>  %231 = fadd float %230, %225
>  %232 = fmul float %119, %54
>  %233 = fadd float %232, %227
>  %234 = fmul float %119, %55
>  %235 = fadd float %234, %229
>  %236 = fsub float %41, %231
>  %237 = fsub float %42, %233
>  %238 = fsub float %43, %235
>  %239 = fmul float %236, %236
>  %240 = fmul float %237, %237
>  %241 = fadd float %240, %239
>  %242 = fmul float %238, %238
>  %243 = fadd float %241, %242
>  %244 = call float @fabs(float %243)
>  %245 = call float @llvm.AMDGPU.rsq(float %244)
>  %246 = fmul float %236, %245
>  %247 = fmul float %237, %245
>  %248 = fmul float %238, %245
>  %249 = fdiv float 1.000000e+00, %245
>  %250 = fmul float %245, %249
>  %251 = fmul float %249, %249
>  %252 = fmul float %56, %250
>  %253 = fmul float %57, %249
>  %254 = fadd float %253, %252
>  %255 = fmul float %58, %251
>  %256 = fadd float %254, %255
>  %257 = fdiv float 1.000000e+00, %256
>  %258 = fmul float %231, %231
>  %259 = fmul float %233, %233
>  %260 = fadd float %259, %258
>  %261 = fmul float %235, %235
>  %262 = fadd float %260, %261
>  %263 = call float @fabs(float %262)
>  %264 = call float @llvm.AMDGPU.rsq(float %263)
>  %265 = fmul float %231, %264
>  %266 = fmul float %233, %264
>  %267 = fmul float %235, %264
>  %268 = fsub float %246, %265
>  %269 = fsub float %247, %266
>  %270 = fsub float %248, %267
>  %271 = fmul float %268, %268
>  %272 = fmul float %269, %269
>  %273 = fadd float %272, %271
>  %274 = fmul float %270, %270
>  %275 = fadd float %273, %274
>  %276 = call float @fabs(float %275)
>  %277 = call float @llvm.AMDGPU.rsq(float %276)
>  %278 = fmul float %268, %277
>  %279 = fmul float %269, %277
>  %280 = fmul float %270, %277
>  %281 = fmul float %208, %246
>  %282 = fmul float %209, %247
>  %283 = fadd float %282, %281
>  %284 = fmul float %210, %248
>  %285 = fadd float %283, %284
>  %286 = fmul float %208, %278
>  %287 = fmul float %209, %279
>  %288 = fadd float %287, %286
>  %289 = fmul float %210, %280
>  %290 = fadd float %288, %289
>  %291 = fcmp uge float %285, 0.000000e+00
>  %292 = select i1 %291, float %285, float 0.000000e+00
>  %293 = fcmp uge float %290, 0.000000e+00
>  %294 = select i1 %293, float %290, float 0.000000e+00
>  %295 = call float @llvm.pow.f32(float %294, float %36)
>  %296 = call float @llvm.AMDGPU.cndlt(float %285, float 0.000000e+00, float %295)
>  %297 = fmul float 1.000000e+00, %257
>  %298 = fmul float %292, %257
>  %299 = fmul float %296, %257
>  %300 = fmul float %297, %59
>  %301 = fadd float %300, %37
>  %302 = fmul float %297, %60
>  %303 = fadd float %302, %38
>  %304 = fmul float %297, %61
>  %305 = fadd float %304, %39
>  %306 = fmul float %298, %62
>  %307 = fadd float %306, %301
>  %308 = fmul float %298, %63
>  %309 = fadd float %308, %303
>  %310 = fmul float %298, %64
>  %311 = fadd float %310, %305
>  %312 = fmul float %299, %65
>  %313 = fadd float %312, %307
>  %314 = fmul float %299, %66
>  %315 = fadd float %314, %309
>  %316 = fmul float %299, %67
>  %317 = fadd float %316, %311
>  %318 = fsub float %68, %231
>  %319 = fsub float %69, %233
>  %320 = fsub float %70, %235
>  %321 = fmul float %318, %318
>  %322 = fmul float %319, %319
>  %323 = fadd float %322, %321
>  %324 = fmul float %320, %320
>  %325 = fadd float %323, %324
>  %326 = call float @fabs(float %325)
>  %327 = call float @llvm.AMDGPU.rsq(float %326)
>  %328 = fmul float %318, %327
>  %329 = fmul float %319, %327
>  %330 = fmul float %320, %327
>  %331 = fdiv float 1.000000e+00, %327
>  %332 = fmul float %327, %331
>  %333 = fmul float %331, %331
>  %334 = fmul float %71, %332
>  %335 = fmul float %72, %331
>  %336 = fadd float %335, %334
>  %337 = fmul float %73, %333
>  %338 = fadd float %336, %337
>  %339 = fdiv float 1.000000e+00, %338
>  %340 = fsub float %328, %265
>  %341 = fsub float %329, %266
>  %342 = fsub float %330, %267
>  %343 = fmul float %340, %340
>  %344 = fmul float %341, %341
>  %345 = fadd float %344, %343
>  %346 = fmul float %342, %342
>  %347 = fadd float %345, %346
>  %348 = call float @fabs(float %347)
>  %349 = call float @llvm.AMDGPU.rsq(float %348)
>  %350 = fmul float %340, %349
>  %351 = fmul float %341, %349
>  %352 = fmul float %342, %349
>  %353 = fmul float %208, %328
>  %354 = fmul float %209, %329
>  %355 = fadd float %354, %353
>  %356 = fmul float %210, %330
>  %357 = fadd float %355, %356
>  %358 = fmul float %208, %350
>  %359 = fmul float %209, %351
>  %360 = fadd float %359, %358
>  %361 = fmul float %210, %352
>  %362 = fadd float %360, %361
>  %363 = fcmp uge float %357, 0.000000e+00
>  %364 = select i1 %363, float %357, float 0.000000e+00
>  %365 = fcmp uge float %362, 0.000000e+00
>  %366 = select i1 %365, float %362, float 0.000000e+00
>  %367 = call float @llvm.pow.f32(float %366, float %36)
>  %368 = call float @llvm.AMDGPU.cndlt(float %357, float 0.000000e+00, float %367)
>  %369 = fmul float 1.000000e+00, %339
>  %370 = fmul float %364, %339
>  %371 = fmul float %368, %339
>  %372 = fmul float %369, %74
>  %373 = fadd float %372, %313
>  %374 = fmul float %369, %75
>  %375 = fadd float %374, %315
>  %376 = fmul float %369, %76
>  %377 = fadd float %376, %317
>  %378 = fmul float %370, %77
>  %379 = fadd float %378, %373
>  %380 = fmul float %370, %78
>  %381 = fadd float %380, %375
>  %382 = fmul float %370, %79
>  %383 = fadd float %382, %377
>  %384 = fmul float %371, %80
>  %385 = fadd float %384, %379
>  %386 = fmul float %371, %81
>  %387 = fadd float %386, %381
>  %388 = fmul float %371, %82
>  %389 = fadd float %388, %383
>  %390 = fsub float %83, %231
>  %391 = fsub float %84, %233
>  %392 = fsub float %85, %235
>  %393 = fmul float %390, %390
>  %394 = fmul float %391, %391
>  %395 = fadd float %394, %393
>  %396 = fmul float %392, %392
>  %397 = fadd float %395, %396
>  %398 = call float @fabs(float %397)
>  %399 = call float @llvm.AMDGPU.rsq(float %398)
>  %400 = fmul float %390, %399
>  %401 = fmul float %391, %399
>  %402 = fmul float %392, %399
>  %403 = fdiv float 1.000000e+00, %399
>  %404 = fmul float %399, %403
>  %405 = fmul float %403, %403
>  %406 = fmul float %86, %404
>  %407 = fmul float %87, %403
>  %408 = fadd float %407, %406
>  %409 = fmul float %88, %405
>  %410 = fadd float %408, %409
>  %411 = fdiv float 1.000000e+00, %410
>  %412 = fsub float %400, %265
>  %413 = fsub float %401, %266
>  %414 = fsub float %402, %267
>  %415 = fmul float %412, %412
>  %416 = fmul float %413, %413
>  %417 = fadd float %416, %415
>  %418 = fmul float %414, %414
>  %419 = fadd float %417, %418
>  %420 = call float @fabs(float %419)
>  %421 = call float @llvm.AMDGPU.rsq(float %420)
>  %422 = fmul float %412, %421
>  %423 = fmul float %413, %421
>  %424 = fmul float %414, %421
>  %425 = fmul float %208, %400
>  %426 = fmul float %209, %401
>  %427 = fadd float %426, %425
>  %428 = fmul float %210, %402
>  %429 = fadd float %427, %428
>  %430 = fmul float %208, %422
>  %431 = fmul float %209, %423
>  %432 = fadd float %431, %430
>  %433 = fmul float %210, %424
>  %434 = fadd float %432, %433
>  %435 = fcmp uge float %429, 0.000000e+00
>  %436 = select i1 %435, float %429, float 0.000000e+00
>  %437 = fcmp uge float %434, 0.000000e+00
>  %438 = select i1 %437, float %434, float 0.000000e+00
>  %439 = call float @llvm.pow.f32(float %438, float %36)
>  %440 = call float @llvm.AMDGPU.cndlt(float %429, float 0.000000e+00, float %439)
>  %441 = fmul float 1.000000e+00, %411
>  %442 = fmul float %436, %411
>  %443 = fmul float %440, %411
>  %444 = fmul float %441, %89
>  %445 = fadd float %444, %385
>  %446 = fmul float %441, %90
>  %447 = fadd float %446, %387
>  %448 = fmul float %441, %91
>  %449 = fadd float %448, %389
>  %450 = fmul float %442, %92
>  %451 = fadd float %450, %445
>  %452 = fmul float %442, %93
>  %453 = fadd float %452, %447
>  %454 = fmul float %442, %94
>  %455 = fadd float %454, %449
>  %456 = fmul float %443, %95
>  %457 = fadd float %456, %451
>  %458 = fmul float %443, %96
>  %459 = fadd float %458, %453
>  %460 = fmul float %443, %97
>  %461 = fadd float %460, %455
>  %462 = fsub float %98, %231
>  %463 = fsub float %99, %233
>  %464 = fsub float %100, %235
>  %465 = fmul float %462, %462
>  %466 = fmul float %463, %463
>  %467 = fadd float %466, %465
>  %468 = fmul float %464, %464
>  %469 = fadd float %467, %468
>  %470 = call float @fabs(float %469)
>  %471 = call float @llvm.AMDGPU.rsq(float %470)
>  %472 = fmul float %462, %471
>  %473 = fmul float %463, %471
>  %474 = fmul float %464, %471
>  %475 = fdiv float 1.000000e+00, %471
>  %476 = fmul float %471, %475
>  %477 = fmul float %475, %475
>  %478 = fmul float %101, %476
>  %479 = fmul float %102, %475
>  %480 = fadd float %479, %478
>  %481 = fmul float %103, %477
>  %482 = fadd float %480, %481
>  %483 = fdiv float 1.000000e+00, %482
>  %484 = fsub float %472, %265
>  %485 = fsub float %473, %266
>  %486 = fsub float %474, %267
>  %487 = fmul float %484, %484
>  %488 = fmul float %485, %485
>  %489 = fadd float %488, %487
>  %490 = fmul float %486, %486
>  %491 = fadd float %489, %490
>  %492 = call float @fabs(float %491)
>  %493 = call float @llvm.AMDGPU.rsq(float %492)
>  %494 = fmul float %484, %493
>  %495 = fmul float %485, %493
>  %496 = fmul float %486, %493
>  %497 = fmul float %208, %472
>  %498 = fmul float %209, %473
>  %499 = fadd float %498, %497
>  %500 = fmul float %210, %474
>  %501 = fadd float %499, %500
>  %502 = fmul float %208, %494
>  %503 = fmul float %209, %495
>  %504 = fadd float %503, %502
>  %505 = fmul float %210, %496
>  %506 = fadd float %504, %505
>  %507 = fcmp uge float %501, 0.000000e+00
>  %508 = select i1 %507, float %501, float 0.000000e+00
>  %509 = fcmp uge float %506, 0.000000e+00
>  %510 = select i1 %509, float %506, float 0.000000e+00
>  %511 = call float @llvm.pow.f32(float %510, float %36)
>  %512 = call float @llvm.AMDGPU.cndlt(float %501, float 0.000000e+00, float %511)
>  %513 = fmul float 1.000000e+00, %483
>  %514 = fmul float %508, %483
>  %515 = fmul float %512, %483
>  %516 = fmul float %513, %104
>  %517 = fadd float %516, %457
>  %518 = fmul float %513, %105
>  %519 = fadd float %518, %459
>  %520 = fmul float %513, %106
>  %521 = fadd float %520, %461
>  %522 = fmul float %514, %107
>  %523 = fadd float %522, %517
>  %524 = fmul float %514, %108
>  %525 = fadd float %524, %519
>  %526 = fmul float %514, %109
>  %527 = fadd float %526, %521
>  %528 = fmul float %515, %110
>  %529 = fadd float %528, %523
>  %530 = fmul float %515, %111
>  %531 = fadd float %530, %525
>  %532 = fmul float %515, %112
>  %533 = fadd float %532, %527
>  %534 = call float @llvm.AMDIL.clamp.(float %529, float 0.000000e+00, float 1.000000e+00)
>  %535 = call float @llvm.AMDIL.clamp.(float %531, float 0.000000e+00, float 1.000000e+00)
>  %536 = call float @llvm.AMDIL.clamp.(float %533, float 0.000000e+00, float 1.000000e+00)
>  %537 = fmul float %208, %265
>  %538 = fmul float %209, %266
>  %539 = fadd float %538, %537
>  %540 = fmul float %210, %267
>  %541 = fadd float %539, %540
>  %542 = fadd float %541, %541
>  %543 = fadd float %541, %541
>  %544 = fadd float %541, %541
>  %545 = fsub float -0.000000e+00, %542
>  %546 = fmul float %545, %208
>  %547 = fadd float %546, %265
>  %548 = fsub float -0.000000e+00, %543
>  %549 = fmul float %548, %209
>  %550 = fadd float %549, %266
>  %551 = fsub float -0.000000e+00, %544
>  %552 = fmul float %551, %210
>  %553 = fadd float %552, %267
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %534, float %535, float %536, float %214)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %129, float %130, float %131, float %132)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %547, float %550, float %553, float %136)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %140, float %141, float %142, float %143)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %147, float %148, float %149, float %150)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %154, float %155, float %156, float %157)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %179, float %181, float %183, float %185)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>046a1605
>7e16550b
>c202817a
>bf8c007f
>d2820018
>04600b0b
>1034330c
>10183508
>10363317
>d282000c
>04323709
>102e330d
>d282000d
>04322f0a
>d00c0008
>0201010d
>d200000c
>00221a80
>1018170c
>c202817e
>bf8c007f
>d2820018
>04600b0c
>08320b1b
>08340d1a
>1036351a
>d282001b
>046e3319
>082e0f17
>d282001b
>046e2f17
>d206011b
>0201011b
>7e365b1b
>10323719
>1034371a
>10343508
>d2820019
>046a3309
>102e3717
>d2820017
>04662f0a
>d00c0008
>02010117
>d2000017
>00222e80
>7e2e4f17
>0e2e2e04
>7e2e4b17
>d0080004
>02021a80
>d200000d
>00110117
>102e170d
>c2020182
>bf8c007f
>d282000d
>04600917
>d206080d
>0201010d
>c202013d
>c2028121
>bf8c007f
>7e300205
>d2820018
>0460090f
>c2020141
>bf8c007f
>d2820018
>04600910
>c2020145
>bf8c007f
>d2820018
>0460090e
>c2020151
>bf8c007f
>d2820018
>04600911
>c2020155
>bf8c007f
>d2820018
>04600912
>c2020159
>bf8c007f
>d2820018
>04600913
>c2020165
>bf8c007f
>d2820018
>04600914
>c2020169
>bf8c007f
>d2820018
>04600915
>c202016d
>bf8c007f
>d2820018
>04600916
>c2020179
>bf8c007f
>d2820018
>0460090b
>c202017d
>bf8c007f
>d2820018
>0460090c
>c2020181
>bf8c007f
>d2820018
>04600917
>d2060818
>02010118
>c202013c
>c2028120
>bf8c007f
>7e320205
>d282000f
>0464090f
>c2020140
>bf8c007f
>d282000f
>043c0910
>c2020144
>bf8c007f
>d282000e
>043c090e
>c2020150
>bf8c007f
>d282000e
>04380911
>c2020154
>bf8c007f
>d282000e
>04380912
>c2020158
>bf8c007f
>d282000e
>04380913
>c2020164
>bf8c007f
>d282000e
>04380914
>c2020168
>bf8c007f
>d282000e
>04380915
>c202016c
>bf8c007f
>d282000e
>04380916
>c2020178
>bf8c007f
>d282000b
>0438090b
>c202017c
>bf8c007f
>d282000b
>042c090c
>c2020180
>bf8c007f
>d282000b
>042c0917
>d206080b
>0201010b
>c2020123
>bf8c007f
>d206080c
>02010004
>f800020f
>0c0d180b
>c0840708
>bf8c000f
>e00c2000
>80020b00
>bf8c0770
>f800021f
>0e0d0c0b
>bf8c070f
>10160d08
>d282000b
>042e0b09
>d282000b
>042e0f0a
>0616170b
>1014150b
>080e1507
>1012130b
>080a1305
>1010110b
>080c1106
>c084070c
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800022f
>0b070506
>c0840710
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800023f
>08070605
>c0840714
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800024f
>08070605
>c0820718
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800025f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..19]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: MOV OUT[2], IN[3]
> 41: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = extractelement <4 x float> %73, i32 3
>  %78 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %79 = load <16 x i8> addrspace(2)* %78, !tbaa !0
>  %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %79, i32 0, i32 %5)
>  %81 = extractelement <4 x float> %80, i32 0
>  %82 = extractelement <4 x float> %80, i32 1
>  %83 = extractelement <4 x float> %80, i32 2
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = extractelement <4 x float> %92, i32 3
>  %97 = fmul float %74, %11
>  %98 = fmul float %74, %12
>  %99 = fmul float %74, %13
>  %100 = fmul float %74, %14
>  %101 = fmul float %75, %15
>  %102 = fadd float %101, %97
>  %103 = fmul float %75, %16
>  %104 = fadd float %103, %98
>  %105 = fmul float %75, %17
>  %106 = fadd float %105, %99
>  %107 = fmul float %75, %18
>  %108 = fadd float %107, %100
>  %109 = fmul float %76, %19
>  %110 = fadd float %109, %102
>  %111 = fmul float %76, %20
>  %112 = fadd float %111, %104
>  %113 = fmul float %76, %21
>  %114 = fadd float %113, %106
>  %115 = fmul float %76, %22
>  %116 = fadd float %115, %108
>  %117 = fmul float %77, %23
>  %118 = fadd float %117, %110
>  %119 = fmul float %77, %24
>  %120 = fadd float %119, %112
>  %121 = fmul float %77, %25
>  %122 = fadd float %121, %114
>  %123 = fmul float %77, %26
>  %124 = fadd float %123, %116
>  %125 = fmul float %81, %27
>  %126 = fmul float %82, %28
>  %127 = fadd float %126, %125
>  %128 = fmul float %83, %29
>  %129 = fadd float %127, %128
>  %130 = fmul float %81, %30
>  %131 = fmul float %82, %31
>  %132 = fadd float %131, %130
>  %133 = fmul float %83, %32
>  %134 = fadd float %132, %133
>  %135 = fmul float %81, %33
>  %136 = fmul float %82, %34
>  %137 = fadd float %136, %135
>  %138 = fmul float %83, %35
>  %139 = fadd float %137, %138
>  %140 = fmul float %129, %129
>  %141 = fmul float %134, %134
>  %142 = fadd float %141, %140
>  %143 = fmul float %139, %139
>  %144 = fadd float %142, %143
>  %145 = call float @fabs(float %144)
>  %146 = call float @llvm.AMDGPU.rsq(float %145)
>  %147 = fmul float %129, %146
>  %148 = fmul float %134, %146
>  %149 = fmul float %139, %146
>  %150 = fmul float %37, %40
>  %151 = fadd float %150, %87
>  %152 = fmul float %38, %41
>  %153 = fadd float %152, %88
>  %154 = fmul float %39, %42
>  %155 = fadd float %154, %89
>  %156 = call float @llvm.AMDIL.clamp.(float %151, float 0.000000e+00, float 1.000000e+00)
>  %157 = call float @llvm.AMDIL.clamp.(float %153, float 0.000000e+00, float 1.000000e+00)
>  %158 = call float @llvm.AMDIL.clamp.(float %155, float 0.000000e+00, float 1.000000e+00)
>  %159 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %160 = fmul float %74, %47
>  %161 = fmul float %74, %48
>  %162 = fmul float %74, %49
>  %163 = fmul float %75, %50
>  %164 = fadd float %163, %160
>  %165 = fmul float %75, %51
>  %166 = fadd float %165, %161
>  %167 = fmul float %75, %52
>  %168 = fadd float %167, %162
>  %169 = fmul float %76, %53
>  %170 = fadd float %169, %164
>  %171 = fmul float %76, %54
>  %172 = fadd float %171, %166
>  %173 = fmul float %76, %55
>  %174 = fadd float %173, %168
>  %175 = fmul float %77, %56
>  %176 = fadd float %175, %170
>  %177 = fmul float %77, %57
>  %178 = fadd float %177, %172
>  %179 = fmul float %77, %58
>  %180 = fadd float %179, %174
>  %181 = fsub float %44, %176
>  %182 = fsub float %45, %178
>  %183 = fsub float %46, %180
>  %184 = fmul float %181, %181
>  %185 = fmul float %182, %182
>  %186 = fadd float %185, %184
>  %187 = fmul float %183, %183
>  %188 = fadd float %186, %187
>  %189 = call float @fabs(float %188)
>  %190 = call float @llvm.AMDGPU.rsq(float %189)
>  %191 = fmul float %181, %190
>  %192 = fmul float %182, %190
>  %193 = fmul float %183, %190
>  %194 = fdiv float 1.000000e+00, %190
>  %195 = fmul float %190, %194
>  %196 = fmul float %194, %194
>  %197 = fmul float %59, %195
>  %198 = fmul float %60, %194
>  %199 = fadd float %198, %197
>  %200 = fmul float %61, %196
>  %201 = fadd float %199, %200
>  %202 = fdiv float 1.000000e+00, %201
>  %203 = fmul float %176, %176
>  %204 = fmul float %178, %178
>  %205 = fadd float %204, %203
>  %206 = fmul float %180, %180
>  %207 = fadd float %205, %206
>  %208 = call float @fabs(float %207)
>  %209 = call float @llvm.AMDGPU.rsq(float %208)
>  %210 = fmul float %176, %209
>  %211 = fmul float %178, %209
>  %212 = fmul float %180, %209
>  %213 = fsub float %191, %210
>  %214 = fsub float %192, %211
>  %215 = fsub float %193, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fmul float %147, %191
>  %227 = fmul float %148, %192
>  %228 = fadd float %227, %226
>  %229 = fmul float %149, %193
>  %230 = fadd float %228, %229
>  %231 = fmul float %147, %223
>  %232 = fmul float %148, %224
>  %233 = fadd float %232, %231
>  %234 = fmul float %149, %225
>  %235 = fadd float %233, %234
>  %236 = fcmp uge float %230, 0.000000e+00
>  %237 = select i1 %236, float %230, float 0.000000e+00
>  %238 = fcmp uge float %235, 0.000000e+00
>  %239 = select i1 %238, float %235, float 0.000000e+00
>  %240 = call float @llvm.pow.f32(float %239, float %36)
>  %241 = call float @llvm.AMDGPU.cndlt(float %230, float 0.000000e+00, float %240)
>  %242 = fmul float 1.000000e+00, %202
>  %243 = fmul float %237, %202
>  %244 = fmul float %241, %202
>  %245 = fmul float %242, %62
>  %246 = fadd float %245, %151
>  %247 = fmul float %242, %63
>  %248 = fadd float %247, %153
>  %249 = fmul float %242, %64
>  %250 = fadd float %249, %155
>  %251 = fmul float %243, %65
>  %252 = fadd float %251, %246
>  %253 = fmul float %243, %66
>  %254 = fadd float %253, %248
>  %255 = fmul float %243, %67
>  %256 = fadd float %255, %250
>  %257 = fmul float %244, %68
>  %258 = fadd float %257, %252
>  %259 = fmul float %244, %69
>  %260 = fadd float %259, %254
>  %261 = fmul float %244, %70
>  %262 = fadd float %261, %256
>  %263 = call float @llvm.AMDIL.clamp.(float %258, float 0.000000e+00, float 1.000000e+00)
>  %264 = call float @llvm.AMDIL.clamp.(float %260, float 0.000000e+00, float 1.000000e+00)
>  %265 = call float @llvm.AMDIL.clamp.(float %262, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %263, float %264, float %265, float %159)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %93, float %94, float %95, float %96)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %118, float %120, float %122, float %124)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820005
>04140904
>c2020130
>bf8c007f
>100c0204
>c2020134
>bf8c007f
>d2820006
>04180902
>c2020138
>bf8c007f
>d2820006
>04180903
>c202013c
>bf8c007f
>d2820007
>04180904
>100c0f07
>d2820006
>041a0b05
>c2020132
>bf8c007f
>10100204
>c2020136
>bf8c007f
>d2820008
>04200902
>c202013a
>bf8c007f
>d2820008
>04200903
>c202013e
>bf8c007f
>d2820008
>04200904
>d2820006
>041a1108
>d2060106
>02010106
>7e125b06
>10141305
>c202012d
>bf8c007f
>080c0a04
>c202012c
>bf8c007f
>081a0e04
>100a1b0d
>d2820005
>04160d06
>c202012e
>bf8c007f
>08161004
>d2820005
>0416170b
>d2060105
>02010105
>7e0a5b05
>100c0b06
>08181506
>10141307
>100e0b0d
>081a1507
>10141b0d
>d282000a
>042a190c
>10121308
>10100b0b
>08121308
>d282000a
>042a1309
>d206010a
>0201010a
>7e145b0a
>1016150c
>1018150d
>c0840704
>bf8c007f
>e00c2000
>80020d00
>c2020114
>bf8c0070
>10221a04
>c2020115
>bf8c007f
>d2820011
>0444090e
>c2020116
>bf8c007f
>d2820011
>0444090f
>c2020110
>bf8c007f
>10241a04
>c2020111
>bf8c007f
>d2820012
>0448090e
>c2020112
>bf8c007f
>d2820012
>0448090f
>10262512
>d2820013
>044e2311
>c2020118
>bf8c007f
>10281a04
>c2020119
>bf8c007f
>d2820014
>0450090e
>c202011a
>bf8c007f
>d282000e
>0450090f
>d282000d
>044e1d0e
>d206010d
>0201010d
>7e1e5b0d
>101a1f12
>1020190d
>10181f11
>d282000b
>0442170c
>10141509
>10121f0e
>d282000a
>042e1509
>d00c0004
>0201010a
>d200000a
>00121480
>7e144f0a
>c202011c
>bf8c007f
>0e141404
>7e144b0a
>100e0f0d
>d2820006
>041e0d0c
>d2820007
>041a1109
>d0080004
>02020e80
>d2000008
>0011010a
>7e0c5505
>100a0d05
>c2020140
>bf8c007f
>100a0a04
>c2020141
>bf8c007f
>d2820005
>04160c04
>100c0d06
>c2020142
>bf8c007f
>d2820005
>04160c04
>7e0c5505
>100a0d08
>d00c0004
>02010107
>d2000007
>00120e80
>100e0d07
>c0840708
>bf8c007f
>e00c2000
>80020800
>c2020122
>c2028126
>bf8c0070
>7e180205
>d282000c
>042a1804
>c2020146
>bf8c007f
>d282000c
>04300906
>c202014a
>bf8c007f
>d282000c
>04300907
>c202014e
>bf8c007f
>d282000c
>04300905
>d206080c
>0201010c
>c2020121
>c2028125
>bf8c007f
>7e1a0205
>d282000d
>04261a04
>c2020145
>bf8c007f
>d282000d
>04340906
>c2020149
>bf8c007f
>d282000d
>04340907
>c202014d
>bf8c007f
>d282000d
>04340905
>d206080d
>0201010d
>c2020120
>c2028124
>bf8c007f
>7e1c0205
>d2820008
>04221c04
>c2020144
>bf8c007f
>d2820006
>04200906
>c2020148
>bf8c007f
>d2820006
>04180907
>c202014c
>bf8c007f
>d2820005
>04180905
>d2060805
>02010105
>c202012b
>bf8c007f
>d2060806
>02010004
>f800020f
>060c0d05
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL IN[3], GENERIC[2], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[2], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  5: MOV TEMP[0].xyz, TEMP[0].xyzx
>  6: MOV TEMP[1].xy, IN[2].xyyy
>  7: MOV TEMP[1].w, IN[2].wwww
>  8: TXP TEMP[1].w, TEMP[1], SAMP[1], 2D
>  9: MOV TEMP[0].w, TEMP[1].wwww
> 10: ADD TEMP[2].x, IMM[0].yyyy, -TEMP[1].wwww
> 11: MOV TEMP[3].xy, IN[3].xyyy
> 12: MOV TEMP[3].w, IN[3].wwww
> 13: TXP TEMP[3], TEMP[3], SAMP[0], 2D
> 14: MUL TEMP[3], TEMP[3], TEMP[1].wwww
> 15: MAD TEMP[0].xyz, TEMP[0], TEMP[2].xxxx, TEMP[3]
> 16: MOV TEMP[0].xyz, TEMP[0].xyzx
> 17: MOV TEMP[0].w, TEMP[1].wwww
> 18: MOV OUT[0], TEMP[0]
> 19: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %45 = fdiv float %36, %38
>  %46 = fdiv float %37, %38
>  %47 = bitcast float %45 to i32
>  %48 = bitcast float %46 to i32
>  %49 = insertelement <2 x i32> undef, i32 %47, i32 0
>  %50 = insertelement <2 x i32> %49, i32 %48, i32 1
>  %51 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %50, <32 x i8> %29, <16 x i8> %31, i32 2)
>  %52 = extractelement <4 x float> %51, i32 0
>  %53 = extractelement <4 x float> %51, i32 1
>  %54 = extractelement <4 x float> %51, i32 2
>  %55 = extractelement <4 x float> %51, i32 3
>  %56 = fmul float %52, %32
>  %57 = fmul float %53, %33
>  %58 = fmul float %54, %34
>  %59 = fmul float %55, %35
>  %60 = fmul float %56, 2.000000e+00
>  %61 = fmul float %57, 2.000000e+00
>  %62 = fmul float %58, 2.000000e+00
>  %63 = fmul float %59, 1.000000e+00
>  %64 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %65 = call float @llvm.AMDIL.clamp.(float %61, float 0.000000e+00, float 1.000000e+00)
>  %66 = call float @llvm.AMDIL.clamp.(float %62, float 0.000000e+00, float 1.000000e+00)
>  %67 = call float @llvm.AMDIL.clamp.(float %63, float 0.000000e+00, float 1.000000e+00)
>  %68 = fdiv float %39, %41
>  %69 = fdiv float %40, %41
>  %70 = bitcast float %68 to i32
>  %71 = bitcast float %69 to i32
>  %72 = insertelement <2 x i32> undef, i32 %70, i32 0
>  %73 = insertelement <2 x i32> %72, i32 %71, i32 1
>  %74 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %73, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %75 = extractelement <4 x float> %74, i32 3
>  %76 = fsub float -0.000000e+00, %75
>  %77 = fadd float 1.000000e+00, %76
>  %78 = fdiv float %42, %44
>  %79 = fdiv float %43, %44
>  %80 = bitcast float %78 to i32
>  %81 = bitcast float %79 to i32
>  %82 = insertelement <2 x i32> undef, i32 %80, i32 0
>  %83 = insertelement <2 x i32> %82, i32 %81, i32 1
>  %84 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %83, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %85 = extractelement <4 x float> %84, i32 0
>  %86 = extractelement <4 x float> %84, i32 1
>  %87 = extractelement <4 x float> %84, i32 2
>  %88 = fmul float %85, %75
>  %89 = fmul float %86, %75
>  %90 = fmul float %87, %75
>  %91 = fmul float %64, %77
>  %92 = fadd float %91, %88
>  %93 = fmul float %65, %77
>  %94 = fadd float %93, %89
>  %95 = fmul float %66, %77
>  %96 = fadd float %95, %90
>  %97 = call i32 @llvm.SI.packf16(float %92, float %94)
>  %98 = bitcast i32 %97 to float
>  %99 = call i32 @llvm.SI.packf16(float %96, float %75)
>  %100 = bitcast i32 %99 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %98, float %100, float %98, float %100)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800800
>00430202
>c80c0d00
>c80d0d01
>c8100f00
>c8110f01
>7e0a5504
>10080b03
>c8180c00
>c8190c01
>10060b06
>c0840300
>c0c60500
>bf8c0070
>f0800700
>00430303
>bf8c0770
>100c0504
>c81c0500
>c81d0501
>c8200700
>c8210701
>7e125508
>10101307
>c8280400
>c8290401
>100e130a
>c0800308
>c0c40510
>bf8c007f
>f0800700
>00020707
>c8280100
>c8290101
>bf8c0770
>10161508
>d282000a
>042e1508
>d206080b
>0201010a
>081404f2
>d2820006
>041a150b
>10160503
>c8300000
>c8310001
>101a1907
>d282000c
>04361907
>d206080c
>0201010c
>d282000b
>042e150c
>5e0c0d0b
>10060505
>c8100200
>c8110201
>10000909
>d2820000
>04020909
>d2060800
>02010100
>d2820000
>040e1500
>5e000500
>f8001c0f
>00060006
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..19]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: MOV OUT[2], IN[3]
> 41: MOV OUT[3], IN[4]
> 42: MOV OUT[4], IN[5]
> 43: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = extractelement <4 x float> %73, i32 3
>  %78 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %79 = load <16 x i8> addrspace(2)* %78, !tbaa !0
>  %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %79, i32 0, i32 %5)
>  %81 = extractelement <4 x float> %80, i32 0
>  %82 = extractelement <4 x float> %80, i32 1
>  %83 = extractelement <4 x float> %80, i32 2
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = extractelement <4 x float> %92, i32 3
>  %97 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %98 = load <16 x i8> addrspace(2)* %97, !tbaa !0
>  %99 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %98, i32 0, i32 %5)
>  %100 = extractelement <4 x float> %99, i32 0
>  %101 = extractelement <4 x float> %99, i32 1
>  %102 = extractelement <4 x float> %99, i32 2
>  %103 = extractelement <4 x float> %99, i32 3
>  %104 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %105 = load <16 x i8> addrspace(2)* %104, !tbaa !0
>  %106 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %105, i32 0, i32 %5)
>  %107 = extractelement <4 x float> %106, i32 0
>  %108 = extractelement <4 x float> %106, i32 1
>  %109 = extractelement <4 x float> %106, i32 2
>  %110 = extractelement <4 x float> %106, i32 3
>  %111 = fmul float %74, %11
>  %112 = fmul float %74, %12
>  %113 = fmul float %74, %13
>  %114 = fmul float %74, %14
>  %115 = fmul float %75, %15
>  %116 = fadd float %115, %111
>  %117 = fmul float %75, %16
>  %118 = fadd float %117, %112
>  %119 = fmul float %75, %17
>  %120 = fadd float %119, %113
>  %121 = fmul float %75, %18
>  %122 = fadd float %121, %114
>  %123 = fmul float %76, %19
>  %124 = fadd float %123, %116
>  %125 = fmul float %76, %20
>  %126 = fadd float %125, %118
>  %127 = fmul float %76, %21
>  %128 = fadd float %127, %120
>  %129 = fmul float %76, %22
>  %130 = fadd float %129, %122
>  %131 = fmul float %77, %23
>  %132 = fadd float %131, %124
>  %133 = fmul float %77, %24
>  %134 = fadd float %133, %126
>  %135 = fmul float %77, %25
>  %136 = fadd float %135, %128
>  %137 = fmul float %77, %26
>  %138 = fadd float %137, %130
>  %139 = fmul float %81, %27
>  %140 = fmul float %82, %28
>  %141 = fadd float %140, %139
>  %142 = fmul float %83, %29
>  %143 = fadd float %141, %142
>  %144 = fmul float %81, %30
>  %145 = fmul float %82, %31
>  %146 = fadd float %145, %144
>  %147 = fmul float %83, %32
>  %148 = fadd float %146, %147
>  %149 = fmul float %81, %33
>  %150 = fmul float %82, %34
>  %151 = fadd float %150, %149
>  %152 = fmul float %83, %35
>  %153 = fadd float %151, %152
>  %154 = fmul float %143, %143
>  %155 = fmul float %148, %148
>  %156 = fadd float %155, %154
>  %157 = fmul float %153, %153
>  %158 = fadd float %156, %157
>  %159 = call float @fabs(float %158)
>  %160 = call float @llvm.AMDGPU.rsq(float %159)
>  %161 = fmul float %143, %160
>  %162 = fmul float %148, %160
>  %163 = fmul float %153, %160
>  %164 = fmul float %37, %40
>  %165 = fadd float %164, %87
>  %166 = fmul float %38, %41
>  %167 = fadd float %166, %88
>  %168 = fmul float %39, %42
>  %169 = fadd float %168, %89
>  %170 = call float @llvm.AMDIL.clamp.(float %165, float 0.000000e+00, float 1.000000e+00)
>  %171 = call float @llvm.AMDIL.clamp.(float %167, float 0.000000e+00, float 1.000000e+00)
>  %172 = call float @llvm.AMDIL.clamp.(float %169, float 0.000000e+00, float 1.000000e+00)
>  %173 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %174 = fmul float %74, %47
>  %175 = fmul float %74, %48
>  %176 = fmul float %74, %49
>  %177 = fmul float %75, %50
>  %178 = fadd float %177, %174
>  %179 = fmul float %75, %51
>  %180 = fadd float %179, %175
>  %181 = fmul float %75, %52
>  %182 = fadd float %181, %176
>  %183 = fmul float %76, %53
>  %184 = fadd float %183, %178
>  %185 = fmul float %76, %54
>  %186 = fadd float %185, %180
>  %187 = fmul float %76, %55
>  %188 = fadd float %187, %182
>  %189 = fmul float %77, %56
>  %190 = fadd float %189, %184
>  %191 = fmul float %77, %57
>  %192 = fadd float %191, %186
>  %193 = fmul float %77, %58
>  %194 = fadd float %193, %188
>  %195 = fsub float %44, %190
>  %196 = fsub float %45, %192
>  %197 = fsub float %46, %194
>  %198 = fmul float %195, %195
>  %199 = fmul float %196, %196
>  %200 = fadd float %199, %198
>  %201 = fmul float %197, %197
>  %202 = fadd float %200, %201
>  %203 = call float @fabs(float %202)
>  %204 = call float @llvm.AMDGPU.rsq(float %203)
>  %205 = fmul float %195, %204
>  %206 = fmul float %196, %204
>  %207 = fmul float %197, %204
>  %208 = fdiv float 1.000000e+00, %204
>  %209 = fmul float %204, %208
>  %210 = fmul float %208, %208
>  %211 = fmul float %59, %209
>  %212 = fmul float %60, %208
>  %213 = fadd float %212, %211
>  %214 = fmul float %61, %210
>  %215 = fadd float %213, %214
>  %216 = fdiv float 1.000000e+00, %215
>  %217 = fmul float %190, %190
>  %218 = fmul float %192, %192
>  %219 = fadd float %218, %217
>  %220 = fmul float %194, %194
>  %221 = fadd float %219, %220
>  %222 = call float @fabs(float %221)
>  %223 = call float @llvm.AMDGPU.rsq(float %222)
>  %224 = fmul float %190, %223
>  %225 = fmul float %192, %223
>  %226 = fmul float %194, %223
>  %227 = fsub float %205, %224
>  %228 = fsub float %206, %225
>  %229 = fsub float %207, %226
>  %230 = fmul float %227, %227
>  %231 = fmul float %228, %228
>  %232 = fadd float %231, %230
>  %233 = fmul float %229, %229
>  %234 = fadd float %232, %233
>  %235 = call float @fabs(float %234)
>  %236 = call float @llvm.AMDGPU.rsq(float %235)
>  %237 = fmul float %227, %236
>  %238 = fmul float %228, %236
>  %239 = fmul float %229, %236
>  %240 = fmul float %161, %205
>  %241 = fmul float %162, %206
>  %242 = fadd float %241, %240
>  %243 = fmul float %163, %207
>  %244 = fadd float %242, %243
>  %245 = fmul float %161, %237
>  %246 = fmul float %162, %238
>  %247 = fadd float %246, %245
>  %248 = fmul float %163, %239
>  %249 = fadd float %247, %248
>  %250 = fcmp uge float %244, 0.000000e+00
>  %251 = select i1 %250, float %244, float 0.000000e+00
>  %252 = fcmp uge float %249, 0.000000e+00
>  %253 = select i1 %252, float %249, float 0.000000e+00
>  %254 = call float @llvm.pow.f32(float %253, float %36)
>  %255 = call float @llvm.AMDGPU.cndlt(float %244, float 0.000000e+00, float %254)
>  %256 = fmul float 1.000000e+00, %216
>  %257 = fmul float %251, %216
>  %258 = fmul float %255, %216
>  %259 = fmul float %256, %62
>  %260 = fadd float %259, %165
>  %261 = fmul float %256, %63
>  %262 = fadd float %261, %167
>  %263 = fmul float %256, %64
>  %264 = fadd float %263, %169
>  %265 = fmul float %257, %65
>  %266 = fadd float %265, %260
>  %267 = fmul float %257, %66
>  %268 = fadd float %267, %262
>  %269 = fmul float %257, %67
>  %270 = fadd float %269, %264
>  %271 = fmul float %258, %68
>  %272 = fadd float %271, %266
>  %273 = fmul float %258, %69
>  %274 = fadd float %273, %268
>  %275 = fmul float %258, %70
>  %276 = fadd float %275, %270
>  %277 = call float @llvm.AMDIL.clamp.(float %272, float 0.000000e+00, float 1.000000e+00)
>  %278 = call float @llvm.AMDIL.clamp.(float %274, float 0.000000e+00, float 1.000000e+00)
>  %279 = call float @llvm.AMDIL.clamp.(float %276, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %277, float %278, float %279, float %173)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %93, float %94, float %95, float %96)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %100, float %101, float %102, float %103)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %107, float %108, float %109, float %110)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %132, float %134, float %136, float %138)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>d2820006
>04200906
>c2020148
>bf8c007f
>d2820006
>04180907
>c202014c
>bf8c007f
>d2820005
>04180905
>d2060805
>02010105
>c202012b
>bf8c007f
>d2060806
>02010004
>f800020f
>060c0d05
>c084070c
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800021f
>08070605
>c0840710
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800022f
>08070605
>c0820714
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL IN[3], GENERIC[2], PERSPECTIVE
>DCL IN[4], GENERIC[4], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    1.0000,     2.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[3], 2D
>  3: TXP TEMP[1], IN[2], SAMP[2], CUBE
>  4: MOV TEMP[2].xy, IN[3].xyyy
>  5: MOV TEMP[2].w, IN[3].wwww
>  6: TXP TEMP[2], TEMP[2], SAMP[1], 2D
>  7: MAD TEMP[1].xyz, TEMP[0], TEMP[1].wwww, TEMP[1]
>  8: MOV_SAT TEMP[1].xyz, TEMP[1].xyzz
>  9: MOV TEMP[1].w, TEMP[0].wwww
> 10: ADD TEMP[0].x, IMM[0].xxxx, -TEMP[2].wwww
> 11: MUL TEMP[1], TEMP[1], TEMP[2].wwww
> 12: MAD TEMP[0].xyz, TEMP[2], TEMP[0].xxxx, TEMP[1]
> 13: MOV TEMP[0].xyz, TEMP[0].xyzx
> 14: MOV TEMP[0].w, TEMP[2].wwww
> 15: MUL TEMP[0].xyz, IN[0], TEMP[0]
> 16: MOV TEMP[0].xyz, TEMP[0].xyzx
> 17: MOV TEMP[0].w, TEMP[2].wwww
> 18: MUL_SAT TEMP[0], TEMP[0], IMM[0].yyyx
> 19: MOV TEMP[0].xyz, TEMP[0].xyzx
> 20: MOV TEMP[1].xy, IN[4].xyyy
> 21: MOV TEMP[1].w, IN[4].wwww
> 22: TXP TEMP[1].w, TEMP[1], SAMP[0], 2D
> 23: MOV TEMP[0].w, TEMP[1].wwww
> 24: MOV OUT[0], TEMP[0]
> 25: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
>  %33 = load <32 x i8> addrspace(2)* %32, !tbaa !0
>  %34 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %46 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %47 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %48 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %49 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %50 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %51 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %52 = fdiv float %39, %41
>  %53 = fdiv float %40, %41
>  %54 = bitcast float %52 to i32
>  %55 = bitcast float %53 to i32
>  %56 = insertelement <2 x i32> undef, i32 %54, i32 0
>  %57 = insertelement <2 x i32> %56, i32 %55, i32 1
>  %58 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %57, <32 x i8> %33, <16 x i8> %35, i32 2)
>  %59 = extractelement <4 x float> %58, i32 0
>  %60 = extractelement <4 x float> %58, i32 1
>  %61 = extractelement <4 x float> %58, i32 2
>  %62 = fdiv float %42, %45
>  %63 = fdiv float %43, %45
>  %64 = fdiv float %44, %45
>  %65 = insertelement <4 x float> undef, float %62, i32 0
>  %66 = insertelement <4 x float> %65, float %63, i32 1
>  %67 = insertelement <4 x float> %66, float %64, i32 2
>  %68 = insertelement <4 x float> %67, float 1.000000e+00, i32 3
>  %69 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %68)
>  %70 = extractelement <4 x float> %69, i32 0
>  %71 = extractelement <4 x float> %69, i32 1
>  %72 = extractelement <4 x float> %69, i32 2
>  %73 = extractelement <4 x float> %69, i32 3
>  %74 = call float @fabs(float %72)
>  %75 = fdiv float 1.000000e+00, %74
>  %76 = fmul float %70, %75
>  %77 = fadd float %76, 1.500000e+00
>  %78 = fmul float %71, %75
>  %79 = fadd float %78, 1.500000e+00
>  %80 = bitcast float %79 to i32
>  %81 = bitcast float %77 to i32
>  %82 = bitcast float %73 to i32
>  %83 = insertelement <4 x i32> undef, i32 %80, i32 0
>  %84 = insertelement <4 x i32> %83, i32 %81, i32 1
>  %85 = insertelement <4 x i32> %84, i32 %82, i32 2
>  %86 = insertelement <4 x i32> %85, i32 undef, i32 3
>  %87 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %86, <32 x i8> %29, <16 x i8> %31, i32 4)
>  %88 = extractelement <4 x float> %87, i32 0
>  %89 = extractelement <4 x float> %87, i32 1
>  %90 = extractelement <4 x float> %87, i32 2
>  %91 = extractelement <4 x float> %87, i32 3
>  %92 = fdiv float %46, %48
>  %93 = fdiv float %47, %48
>  %94 = bitcast float %92 to i32
>  %95 = bitcast float %93 to i32
>  %96 = insertelement <2 x i32> undef, i32 %94, i32 0
>  %97 = insertelement <2 x i32> %96, i32 %95, i32 1
>  %98 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %97, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %99 = extractelement <4 x float> %98, i32 0
>  %100 = extractelement <4 x float> %98, i32 1
>  %101 = extractelement <4 x float> %98, i32 2
>  %102 = extractelement <4 x float> %98, i32 3
>  %103 = fmul float %59, %91
>  %104 = fadd float %103, %88
>  %105 = fmul float %60, %91
>  %106 = fadd float %105, %89
>  %107 = fmul float %61, %91
>  %108 = fadd float %107, %90
>  %109 = call float @llvm.AMDIL.clamp.(float %104, float 0.000000e+00, float 1.000000e+00)
>  %110 = call float @llvm.AMDIL.clamp.(float %106, float 0.000000e+00, float 1.000000e+00)
>  %111 = call float @llvm.AMDIL.clamp.(float %108, float 0.000000e+00, float 1.000000e+00)
>  %112 = fsub float -0.000000e+00, %102
>  %113 = fadd float 1.000000e+00, %112
>  %114 = fmul float %109, %102
>  %115 = fmul float %110, %102
>  %116 = fmul float %111, %102
>  %117 = fmul float %99, %113
>  %118 = fadd float %117, %114
>  %119 = fmul float %100, %113
>  %120 = fadd float %119, %115
>  %121 = fmul float %101, %113
>  %122 = fadd float %121, %116
>  %123 = fmul float %36, %118
>  %124 = fmul float %37, %120
>  %125 = fmul float %38, %122
>  %126 = fmul float %123, 2.000000e+00
>  %127 = fmul float %124, 2.000000e+00
>  %128 = fmul float %125, 2.000000e+00
>  %129 = fmul float %102, 1.000000e+00
>  %130 = call float @llvm.AMDIL.clamp.(float %126, float 0.000000e+00, float 1.000000e+00)
>  %131 = call float @llvm.AMDIL.clamp.(float %127, float 0.000000e+00, float 1.000000e+00)
>  %132 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
>  %133 = call float @llvm.AMDIL.clamp.(float %129, float 0.000000e+00, float 1.000000e+00)
>  %134 = fdiv float %49, %51
>  %135 = fdiv float %50, %51
>  %136 = bitcast float %134 to i32
>  %137 = bitcast float %135 to i32
>  %138 = insertelement <2 x i32> undef, i32 %136, i32 0
>  %139 = insertelement <2 x i32> %138, i32 %137, i32 1
>  %140 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %139, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %141 = extractelement <4 x float> %140, i32 3
>  %142 = fcmp ugt float %141, 0x3FDFDFDFE0000000
>  %143 = sext i1 %142 to i32
>  %144 = trunc i32 %143 to i1
>  %145 = select i1 %144, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %145)
>  %146 = call i32 @llvm.SI.packf16(float %130, float %131)
>  %147 = bitcast i32 %146 to float
>  %148 = call i32 @llvm.SI.packf16(float %132, float %141)
>  %149 = bitcast i32 %148 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %147, float %149, float %147, float %149)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8081100
>c8091101
>c80c1300
>c80d1301
>7e085503
>10060902
>c8141000
>c8151001
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800800
>00430202
>7e0602ff
>3efefeff
>bf8c0770
>d0080000
>02020702
>d2000003
>0001e4f3
>7c260680
>c80c0900
>c80d0901
>c8100b00
>c8110b01
>7e0e5504
>10080f03
>c8200800
>c8210801
>10060f08
>c8200a00
>c8210a01
>100a0f08
>7e0c02f2
>d28a0008
>04160903
>d28c0007
>04160903
>d28e0009
>04160903
>d288000a
>04160903
>d2060103
>02010109
>7e065503
>7e0802ff
>3fc00000
>d2820009
>04120707
>d2820008
>04120708
>c0840308
>c0c60510
>bf8c007f
>f0800f00
>00430308
>c81c0500
>c81d0501
>c8200700
>c8210701
>7e125508
>10101307
>c8280400
>c8290401
>100e130a
>c084030c
>c0c60518
>bf8c0070
>f0800700
>00430707
>bf8c0770
>d282000a
>04120d08
>d206080e
>0201010a
>c8280d00
>c8290d01
>c82c0f00
>c82d0f01
>7e18550b
>1016190a
>c8340c00
>c8350c01
>1014190d
>c0800304
>c0c40508
>bf8c007f
>f0800f00
>00020a0a
>bf8c0770
>101e1b0e
>081c1af2
>d282000f
>043e1d0b
>c8400100
>c8410101
>10221f10
>d282000f
>04461f10
>d206080f
>0201010f
>d2820010
>040e0d07
>d2060810
>02010110
>10201b10
>d2820010
>04421d0a
>c8440000
>c8450001
>10242111
>d2820010
>044a2111
>d2060810
>02010110
>5e1e1f10
>d2820003
>04160d09
>d2060803
>02010103
>10061b03
>d2820003
>040e1d0c
>c8100200
>c8110201
>10000704
>d2820000
>04020704
>d2060800
>02010100
>5e000500
>f8001c0f
>000f000f
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL IN[6]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL OUT[5], GENERIC[4]
>DCL CONST[0..19]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: MOV OUT[2], IN[3]
> 41: DP3 TEMP[1], TEMP[0], TEMP[6]
> 42: ADD TEMP[1], TEMP[1], TEMP[1]
> 43: MAD OUT[3].xyz, -TEMP[1], TEMP[0], TEMP[6]
> 44: MOV OUT[3].w, IN[4]
> 45: MOV OUT[4], IN[5]
> 46: MOV OUT[5], IN[6]
> 47: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = extractelement <4 x float> %73, i32 3
>  %78 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %79 = load <16 x i8> addrspace(2)* %78, !tbaa !0
>  %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %79, i32 0, i32 %5)
>  %81 = extractelement <4 x float> %80, i32 0
>  %82 = extractelement <4 x float> %80, i32 1
>  %83 = extractelement <4 x float> %80, i32 2
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = extractelement <4 x float> %92, i32 3
>  %97 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %98 = load <16 x i8> addrspace(2)* %97, !tbaa !0
>  %99 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %98, i32 0, i32 %5)
>  %100 = extractelement <4 x float> %99, i32 3
>  %101 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %102 = load <16 x i8> addrspace(2)* %101, !tbaa !0
>  %103 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %102, i32 0, i32 %5)
>  %104 = extractelement <4 x float> %103, i32 0
>  %105 = extractelement <4 x float> %103, i32 1
>  %106 = extractelement <4 x float> %103, i32 2
>  %107 = extractelement <4 x float> %103, i32 3
>  %108 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
>  %109 = load <16 x i8> addrspace(2)* %108, !tbaa !0
>  %110 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %109, i32 0, i32 %5)
>  %111 = extractelement <4 x float> %110, i32 0
>  %112 = extractelement <4 x float> %110, i32 1
>  %113 = extractelement <4 x float> %110, i32 2
>  %114 = extractelement <4 x float> %110, i32 3
>  %115 = fmul float %74, %11
>  %116 = fmul float %74, %12
>  %117 = fmul float %74, %13
>  %118 = fmul float %74, %14
>  %119 = fmul float %75, %15
>  %120 = fadd float %119, %115
>  %121 = fmul float %75, %16
>  %122 = fadd float %121, %116
>  %123 = fmul float %75, %17
>  %124 = fadd float %123, %117
>  %125 = fmul float %75, %18
>  %126 = fadd float %125, %118
>  %127 = fmul float %76, %19
>  %128 = fadd float %127, %120
>  %129 = fmul float %76, %20
>  %130 = fadd float %129, %122
>  %131 = fmul float %76, %21
>  %132 = fadd float %131, %124
>  %133 = fmul float %76, %22
>  %134 = fadd float %133, %126
>  %135 = fmul float %77, %23
>  %136 = fadd float %135, %128
>  %137 = fmul float %77, %24
>  %138 = fadd float %137, %130
>  %139 = fmul float %77, %25
>  %140 = fadd float %139, %132
>  %141 = fmul float %77, %26
>  %142 = fadd float %141, %134
>  %143 = fmul float %81, %27
>  %144 = fmul float %82, %28
>  %145 = fadd float %144, %143
>  %146 = fmul float %83, %29
>  %147 = fadd float %145, %146
>  %148 = fmul float %81, %30
>  %149 = fmul float %82, %31
>  %150 = fadd float %149, %148
>  %151 = fmul float %83, %32
>  %152 = fadd float %150, %151
>  %153 = fmul float %81, %33
>  %154 = fmul float %82, %34
>  %155 = fadd float %154, %153
>  %156 = fmul float %83, %35
>  %157 = fadd float %155, %156
>  %158 = fmul float %147, %147
>  %159 = fmul float %152, %152
>  %160 = fadd float %159, %158
>  %161 = fmul float %157, %157
>  %162 = fadd float %160, %161
>  %163 = call float @fabs(float %162)
>  %164 = call float @llvm.AMDGPU.rsq(float %163)
>  %165 = fmul float %147, %164
>  %166 = fmul float %152, %164
>  %167 = fmul float %157, %164
>  %168 = fmul float %37, %40
>  %169 = fadd float %168, %87
>  %170 = fmul float %38, %41
>  %171 = fadd float %170, %88
>  %172 = fmul float %39, %42
>  %173 = fadd float %172, %89
>  %174 = call float @llvm.AMDIL.clamp.(float %169, float 0.000000e+00, float 1.000000e+00)
>  %175 = call float @llvm.AMDIL.clamp.(float %171, float 0.000000e+00, float 1.000000e+00)
>  %176 = call float @llvm.AMDIL.clamp.(float %173, float 0.000000e+00, float 1.000000e+00)
>  %177 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %178 = fmul float %74, %47
>  %179 = fmul float %74, %48
>  %180 = fmul float %74, %49
>  %181 = fmul float %75, %50
>  %182 = fadd float %181, %178
>  %183 = fmul float %75, %51
>  %184 = fadd float %183, %179
>  %185 = fmul float %75, %52
>  %186 = fadd float %185, %180
>  %187 = fmul float %76, %53
>  %188 = fadd float %187, %182
>  %189 = fmul float %76, %54
>  %190 = fadd float %189, %184
>  %191 = fmul float %76, %55
>  %192 = fadd float %191, %186
>  %193 = fmul float %77, %56
>  %194 = fadd float %193, %188
>  %195 = fmul float %77, %57
>  %196 = fadd float %195, %190
>  %197 = fmul float %77, %58
>  %198 = fadd float %197, %192
>  %199 = fsub float %44, %194
>  %200 = fsub float %45, %196
>  %201 = fsub float %46, %198
>  %202 = fmul float %199, %199
>  %203 = fmul float %200, %200
>  %204 = fadd float %203, %202
>  %205 = fmul float %201, %201
>  %206 = fadd float %204, %205
>  %207 = call float @fabs(float %206)
>  %208 = call float @llvm.AMDGPU.rsq(float %207)
>  %209 = fmul float %199, %208
>  %210 = fmul float %200, %208
>  %211 = fmul float %201, %208
>  %212 = fdiv float 1.000000e+00, %208
>  %213 = fmul float %208, %212
>  %214 = fmul float %212, %212
>  %215 = fmul float %59, %213
>  %216 = fmul float %60, %212
>  %217 = fadd float %216, %215
>  %218 = fmul float %61, %214
>  %219 = fadd float %217, %218
>  %220 = fdiv float 1.000000e+00, %219
>  %221 = fmul float %194, %194
>  %222 = fmul float %196, %196
>  %223 = fadd float %222, %221
>  %224 = fmul float %198, %198
>  %225 = fadd float %223, %224
>  %226 = call float @fabs(float %225)
>  %227 = call float @llvm.AMDGPU.rsq(float %226)
>  %228 = fmul float %194, %227
>  %229 = fmul float %196, %227
>  %230 = fmul float %198, %227
>  %231 = fsub float %209, %228
>  %232 = fsub float %210, %229
>  %233 = fsub float %211, %230
>  %234 = fmul float %231, %231
>  %235 = fmul float %232, %232
>  %236 = fadd float %235, %234
>  %237 = fmul float %233, %233
>  %238 = fadd float %236, %237
>  %239 = call float @fabs(float %238)
>  %240 = call float @llvm.AMDGPU.rsq(float %239)
>  %241 = fmul float %231, %240
>  %242 = fmul float %232, %240
>  %243 = fmul float %233, %240
>  %244 = fmul float %165, %209
>  %245 = fmul float %166, %210
>  %246 = fadd float %245, %244
>  %247 = fmul float %167, %211
>  %248 = fadd float %246, %247
>  %249 = fmul float %165, %241
>  %250 = fmul float %166, %242
>  %251 = fadd float %250, %249
>  %252 = fmul float %167, %243
>  %253 = fadd float %251, %252
>  %254 = fcmp uge float %248, 0.000000e+00
>  %255 = select i1 %254, float %248, float 0.000000e+00
>  %256 = fcmp uge float %253, 0.000000e+00
>  %257 = select i1 %256, float %253, float 0.000000e+00
>  %258 = call float @llvm.pow.f32(float %257, float %36)
>  %259 = call float @llvm.AMDGPU.cndlt(float %248, float 0.000000e+00, float %258)
>  %260 = fmul float 1.000000e+00, %220
>  %261 = fmul float %255, %220
>  %262 = fmul float %259, %220
>  %263 = fmul float %260, %62
>  %264 = fadd float %263, %169
>  %265 = fmul float %260, %63
>  %266 = fadd float %265, %171
>  %267 = fmul float %260, %64
>  %268 = fadd float %267, %173
>  %269 = fmul float %261, %65
>  %270 = fadd float %269, %264
>  %271 = fmul float %261, %66
>  %272 = fadd float %271, %266
>  %273 = fmul float %261, %67
>  %274 = fadd float %273, %268
>  %275 = fmul float %262, %68
>  %276 = fadd float %275, %270
>  %277 = fmul float %262, %69
>  %278 = fadd float %277, %272
>  %279 = fmul float %262, %70
>  %280 = fadd float %279, %274
>  %281 = call float @llvm.AMDIL.clamp.(float %276, float 0.000000e+00, float 1.000000e+00)
>  %282 = call float @llvm.AMDIL.clamp.(float %278, float 0.000000e+00, float 1.000000e+00)
>  %283 = call float @llvm.AMDIL.clamp.(float %280, float 0.000000e+00, float 1.000000e+00)
>  %284 = fmul float %165, %228
>  %285 = fmul float %166, %229
>  %286 = fadd float %285, %284
>  %287 = fmul float %167, %230
>  %288 = fadd float %286, %287
>  %289 = fadd float %288, %288
>  %290 = fadd float %288, %288
>  %291 = fadd float %288, %288
>  %292 = fsub float -0.000000e+00, %289
>  %293 = fmul float %292, %165
>  %294 = fadd float %293, %228
>  %295 = fsub float -0.000000e+00, %290
>  %296 = fmul float %295, %166
>  %297 = fadd float %296, %229
>  %298 = fsub float -0.000000e+00, %291
>  %299 = fmul float %298, %167
>  %300 = fadd float %299, %230
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %281, float %282, float %283, float %177)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %93, float %94, float %95, float %96)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %294, float %297, float %300, float %100)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %104, float %105, float %106, float %107)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %111, float %112, float %113, float %114)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %136, float %138, float %140, float %142)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>c202012b
>bf8c007f
>d206080c
>02010004
>f800020f
>0c12130b
>c084070c
>bf8c000f
>e00c2000
>80020b00
>bf8c0770
>f800021f
>0e0d0c0b
>bf8c070f
>10160d08
>d282000b
>042e0b09
>d282000b
>042e0f0a
>0616170b
>1014150b
>080e1507
>1012130b
>080a1305
>1010110b
>080c1106
>c0840710
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800022f
>0b070506
>c0840714
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800023f
>08070605
>c0820718
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800024f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..23]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: MOV OUT[2], IN[3]
> 41: MUL TEMP[1], IN[4].xxxx, CONST[20]
> 42: MAD TEMP[1], IN[4].yyyy, CONST[21], TEMP[1]
> 43: MAD TEMP[1], IN[4].zzzz, CONST[22], TEMP[1]
> 44: MAD OUT[3], IN[4].wwww, CONST[23], TEMP[1]
> 45: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %87 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
>  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %5)
>  %90 = extractelement <4 x float> %89, i32 0
>  %91 = extractelement <4 x float> %89, i32 1
>  %92 = extractelement <4 x float> %89, i32 2
>  %93 = extractelement <4 x float> %89, i32 3
>  %94 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %95 = load <16 x i8> addrspace(2)* %94, !tbaa !0
>  %96 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %95, i32 0, i32 %5)
>  %97 = extractelement <4 x float> %96, i32 0
>  %98 = extractelement <4 x float> %96, i32 1
>  %99 = extractelement <4 x float> %96, i32 2
>  %100 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %101 = load <16 x i8> addrspace(2)* %100, !tbaa !0
>  %102 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %101, i32 0, i32 %5)
>  %103 = extractelement <4 x float> %102, i32 0
>  %104 = extractelement <4 x float> %102, i32 1
>  %105 = extractelement <4 x float> %102, i32 2
>  %106 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %107 = load <16 x i8> addrspace(2)* %106, !tbaa !0
>  %108 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %107, i32 0, i32 %5)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = extractelement <4 x float> %108, i32 1
>  %111 = extractelement <4 x float> %108, i32 2
>  %112 = extractelement <4 x float> %108, i32 3
>  %113 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %114 = load <16 x i8> addrspace(2)* %113, !tbaa !0
>  %115 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %114, i32 0, i32 %5)
>  %116 = extractelement <4 x float> %115, i32 0
>  %117 = extractelement <4 x float> %115, i32 1
>  %118 = extractelement <4 x float> %115, i32 2
>  %119 = extractelement <4 x float> %115, i32 3
>  %120 = fmul float %90, %11
>  %121 = fmul float %90, %12
>  %122 = fmul float %90, %13
>  %123 = fmul float %90, %14
>  %124 = fmul float %91, %15
>  %125 = fadd float %124, %120
>  %126 = fmul float %91, %16
>  %127 = fadd float %126, %121
>  %128 = fmul float %91, %17
>  %129 = fadd float %128, %122
>  %130 = fmul float %91, %18
>  %131 = fadd float %130, %123
>  %132 = fmul float %92, %19
>  %133 = fadd float %132, %125
>  %134 = fmul float %92, %20
>  %135 = fadd float %134, %127
>  %136 = fmul float %92, %21
>  %137 = fadd float %136, %129
>  %138 = fmul float %92, %22
>  %139 = fadd float %138, %131
>  %140 = fmul float %93, %23
>  %141 = fadd float %140, %133
>  %142 = fmul float %93, %24
>  %143 = fadd float %142, %135
>  %144 = fmul float %93, %25
>  %145 = fadd float %144, %137
>  %146 = fmul float %93, %26
>  %147 = fadd float %146, %139
>  %148 = fmul float %97, %27
>  %149 = fmul float %98, %28
>  %150 = fadd float %149, %148
>  %151 = fmul float %99, %29
>  %152 = fadd float %150, %151
>  %153 = fmul float %97, %30
>  %154 = fmul float %98, %31
>  %155 = fadd float %154, %153
>  %156 = fmul float %99, %32
>  %157 = fadd float %155, %156
>  %158 = fmul float %97, %33
>  %159 = fmul float %98, %34
>  %160 = fadd float %159, %158
>  %161 = fmul float %99, %35
>  %162 = fadd float %160, %161
>  %163 = fmul float %152, %152
>  %164 = fmul float %157, %157
>  %165 = fadd float %164, %163
>  %166 = fmul float %162, %162
>  %167 = fadd float %165, %166
>  %168 = call float @fabs(float %167)
>  %169 = call float @llvm.AMDGPU.rsq(float %168)
>  %170 = fmul float %152, %169
>  %171 = fmul float %157, %169
>  %172 = fmul float %162, %169
>  %173 = fmul float %37, %40
>  %174 = fadd float %173, %103
>  %175 = fmul float %38, %41
>  %176 = fadd float %175, %104
>  %177 = fmul float %39, %42
>  %178 = fadd float %177, %105
>  %179 = call float @llvm.AMDIL.clamp.(float %174, float 0.000000e+00, float 1.000000e+00)
>  %180 = call float @llvm.AMDIL.clamp.(float %176, float 0.000000e+00, float 1.000000e+00)
>  %181 = call float @llvm.AMDIL.clamp.(float %178, float 0.000000e+00, float 1.000000e+00)
>  %182 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %183 = fmul float %90, %47
>  %184 = fmul float %90, %48
>  %185 = fmul float %90, %49
>  %186 = fmul float %91, %50
>  %187 = fadd float %186, %183
>  %188 = fmul float %91, %51
>  %189 = fadd float %188, %184
>  %190 = fmul float %91, %52
>  %191 = fadd float %190, %185
>  %192 = fmul float %92, %53
>  %193 = fadd float %192, %187
>  %194 = fmul float %92, %54
>  %195 = fadd float %194, %189
>  %196 = fmul float %92, %55
>  %197 = fadd float %196, %191
>  %198 = fmul float %93, %56
>  %199 = fadd float %198, %193
>  %200 = fmul float %93, %57
>  %201 = fadd float %200, %195
>  %202 = fmul float %93, %58
>  %203 = fadd float %202, %197
>  %204 = fsub float %44, %199
>  %205 = fsub float %45, %201
>  %206 = fsub float %46, %203
>  %207 = fmul float %204, %204
>  %208 = fmul float %205, %205
>  %209 = fadd float %208, %207
>  %210 = fmul float %206, %206
>  %211 = fadd float %209, %210
>  %212 = call float @fabs(float %211)
>  %213 = call float @llvm.AMDGPU.rsq(float %212)
>  %214 = fmul float %204, %213
>  %215 = fmul float %205, %213
>  %216 = fmul float %206, %213
>  %217 = fdiv float 1.000000e+00, %213
>  %218 = fmul float %213, %217
>  %219 = fmul float %217, %217
>  %220 = fmul float %59, %218
>  %221 = fmul float %60, %217
>  %222 = fadd float %221, %220
>  %223 = fmul float %61, %219
>  %224 = fadd float %222, %223
>  %225 = fdiv float 1.000000e+00, %224
>  %226 = fmul float %199, %199
>  %227 = fmul float %201, %201
>  %228 = fadd float %227, %226
>  %229 = fmul float %203, %203
>  %230 = fadd float %228, %229
>  %231 = call float @fabs(float %230)
>  %232 = call float @llvm.AMDGPU.rsq(float %231)
>  %233 = fmul float %199, %232
>  %234 = fmul float %201, %232
>  %235 = fmul float %203, %232
>  %236 = fsub float %214, %233
>  %237 = fsub float %215, %234
>  %238 = fsub float %216, %235
>  %239 = fmul float %236, %236
>  %240 = fmul float %237, %237
>  %241 = fadd float %240, %239
>  %242 = fmul float %238, %238
>  %243 = fadd float %241, %242
>  %244 = call float @fabs(float %243)
>  %245 = call float @llvm.AMDGPU.rsq(float %244)
>  %246 = fmul float %236, %245
>  %247 = fmul float %237, %245
>  %248 = fmul float %238, %245
>  %249 = fmul float %170, %214
>  %250 = fmul float %171, %215
>  %251 = fadd float %250, %249
>  %252 = fmul float %172, %216
>  %253 = fadd float %251, %252
>  %254 = fmul float %170, %246
>  %255 = fmul float %171, %247
>  %256 = fadd float %255, %254
>  %257 = fmul float %172, %248
>  %258 = fadd float %256, %257
>  %259 = fcmp uge float %253, 0.000000e+00
>  %260 = select i1 %259, float %253, float 0.000000e+00
>  %261 = fcmp uge float %258, 0.000000e+00
>  %262 = select i1 %261, float %258, float 0.000000e+00
>  %263 = call float @llvm.pow.f32(float %262, float %36)
>  %264 = call float @llvm.AMDGPU.cndlt(float %253, float 0.000000e+00, float %263)
>  %265 = fmul float 1.000000e+00, %225
>  %266 = fmul float %260, %225
>  %267 = fmul float %264, %225
>  %268 = fmul float %265, %62
>  %269 = fadd float %268, %174
>  %270 = fmul float %265, %63
>  %271 = fadd float %270, %176
>  %272 = fmul float %265, %64
>  %273 = fadd float %272, %178
>  %274 = fmul float %266, %65
>  %275 = fadd float %274, %269
>  %276 = fmul float %266, %66
>  %277 = fadd float %276, %271
>  %278 = fmul float %266, %67
>  %279 = fadd float %278, %273
>  %280 = fmul float %267, %68
>  %281 = fadd float %280, %275
>  %282 = fmul float %267, %69
>  %283 = fadd float %282, %277
>  %284 = fmul float %267, %70
>  %285 = fadd float %284, %279
>  %286 = call float @llvm.AMDIL.clamp.(float %281, float 0.000000e+00, float 1.000000e+00)
>  %287 = call float @llvm.AMDIL.clamp.(float %283, float 0.000000e+00, float 1.000000e+00)
>  %288 = call float @llvm.AMDIL.clamp.(float %285, float 0.000000e+00, float 1.000000e+00)
>  %289 = fmul float %116, %71
>  %290 = fmul float %116, %72
>  %291 = fmul float %116, %73
>  %292 = fmul float %116, %74
>  %293 = fmul float %117, %75
>  %294 = fadd float %293, %289
>  %295 = fmul float %117, %76
>  %296 = fadd float %295, %290
>  %297 = fmul float %117, %77
>  %298 = fadd float %297, %291
>  %299 = fmul float %117, %78
>  %300 = fadd float %299, %292
>  %301 = fmul float %118, %79
>  %302 = fadd float %301, %294
>  %303 = fmul float %118, %80
>  %304 = fadd float %303, %296
>  %305 = fmul float %118, %81
>  %306 = fadd float %305, %298
>  %307 = fmul float %118, %82
>  %308 = fadd float %307, %300
>  %309 = fmul float %119, %83
>  %310 = fadd float %309, %302
>  %311 = fmul float %119, %84
>  %312 = fadd float %311, %304
>  %313 = fmul float %119, %85
>  %314 = fadd float %313, %306
>  %315 = fmul float %119, %86
>  %316 = fadd float %315, %308
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %286, float %287, float %288, float %182)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %109, float %110, float %111, float %112)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %310, float %312, float %314, float %316)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %141, float %143, float %145, float %147)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820005
>04140904
>c2020130
>bf8c007f
>100c0204
>c2020134
>bf8c007f
>d2820006
>04180902
>c2020138
>bf8c007f
>d2820006
>04180903
>c202013c
>bf8c007f
>d2820007
>04180904
>100c0f07
>d2820006
>041a0b05
>c2020132
>bf8c007f
>10100204
>c2020136
>bf8c007f
>d2820008
>04200902
>c202013a
>bf8c007f
>d2820008
>04200903
>c202013e
>bf8c007f
>d2820008
>04200904
>d2820006
>041a1108
>d2060106
>02010106
>7e125b06
>10141305
>c202012d
>bf8c007f
>080c0a04
>c202012c
>bf8c007f
>081a0e04
>100a1b0d
>d2820005
>04160d06
>c202012e
>bf8c007f
>08161004
>d2820005
>0416170b
>d2060105
>02010105
>7e0a5b05
>100c0b06
>08181506
>10141307
>100e0b0d
>081a1507
>10141b0d
>d282000a
>042a190c
>10121308
>10100b0b
>08121308
>d282000a
>042a1309
>d206010a
>0201010a
>7e145b0a
>1016150c
>1018150d
>c0840704
>bf8c007f
>e00c2000
>80020d00
>c2020114
>bf8c0070
>10221a04
>c2020115
>bf8c007f
>d2820011
>0444090e
>c2020116
>bf8c007f
>d2820011
>0444090f
>c2020110
>bf8c007f
>10241a04
>c2020111
>bf8c007f
>d2820012
>0448090e
>c2020112
>bf8c007f
>d2820012
>0448090f
>10262512
>d2820013
>044e2311
>c2020118
>bf8c007f
>10281a04
>c2020119
>bf8c007f
>d2820014
>0450090e
>c202011a
>bf8c007f
>d282000e
>0450090f
>d282000d
>044e1d0e
>d206010d
>0201010d
>7e1e5b0d
>101a1f12
>1020190d
>10181f11
>d282000b
>0442170c
>10141509
>10121f0e
>d282000a
>042e1509
>d00c0004
>0201010a
>d200000a
>00121480
>7e144f0a
>c202011c
>bf8c007f
>0e141404
>7e144b0a
>100e0f0d
>d2820006
>041e0d0c
>d2820007
>041a1109
>d0080004
>02020e80
>d2000008
>0011010a
>7e0c5505
>100a0d05
>c2020140
>bf8c007f
>100a0a04
>c2020141
>bf8c007f
>d2820005
>04160c04
>100c0d06
>c2020142
>bf8c007f
>d2820005
>04160c04
>7e0c5505
>100a0d08
>d00c0004
>02010107
>d2000007
>00120e80
>100e0d07
>c0840708
>bf8c007f
>e00c2000
>80020800
>c2020122
>c2028126
>bf8c0070
>7e180205
>d282000c
>042a1804
>c2020146
>bf8c007f
>d282000c
>04300906
>c202014a
>bf8c007f
>d282000c
>04300907
>c202014e
>bf8c007f
>d282000c
>04300905
>d206080c
>0201010c
>c2020121
>c2028125
>bf8c007f
>7e1a0205
>d282000d
>04261a04
>c2020145
>bf8c007f
>d282000d
>04340906
>c2020149
>bf8c007f
>d282000d
>04340907
>c202014d
>bf8c007f
>d282000d
>04340905
>d206080d
>0201010d
>c2020120
>c2028124
>bf8c007f
>7e1c0205
>d2820008
>04221c04
>c2020144
>bf8c007f
>d2820006
>04200906
>c2020148
>bf8c007f
>d2820006
>04180907
>c202014c
>bf8c007f
>d2820005
>04180905
>d2060805
>02010105
>c202012b
>bf8c007f
>d2060806
>02010004
>f800020f
>060c0d05
>c084070c
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800021f
>08070605
>c0820710
>bf8c000f
>e00c2000
>80010500
>c2020153
>bf8c0070
>10000a04
>c2020157
>bf8c007f
>d2820000
>04000906
>c202015b
>bf8c007f
>d2820000
>04000907
>c202015f
>bf8c007f
>d2820000
>04000908
>c2020152
>bf8c007f
>10120a04
>c2020156
>bf8c007f
>d2820009
>04240906
>c202015a
>bf8c007f
>d2820009
>04240907
>c202015e
>bf8c007f
>d2820009
>04240908
>c2020151
>bf8c007f
>10140a04
>c2020155
>bf8c007f
>d282000a
>04280906
>c2020159
>bf8c007f
>d282000a
>04280907
>c202015d
>bf8c007f
>d282000a
>04280908
>c2020150
>bf8c007f
>10160a04
>c2020154
>bf8c007f
>d282000b
>042c0906
>c2020158
>bf8c007f
>d282000b
>042c0907
>c202015c
>bf8c007f
>d2820005
>042c0908
>f800022f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL IN[3], GENERIC[2], PERSPECTIVE
>DCL IN[4], GENERIC[3], PERSPECTIVE
>DCL IN[5], GENERIC[4], PERSPECTIVE
>DCL IN[6], GENERIC[6], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL SAMP[4]
>DCL SAMP[5]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     2.0000,     0.0000,     0.0000}
>  0: TXP TEMP[0], IN[1], SAMP[5], CUBE
>  1: MOV TEMP[1].xy, IN[2].xyyy
>  2: MOV TEMP[1].w, IN[2].wwww
>  3: TXP TEMP[1], TEMP[1], SAMP[4], 2D
>  4: MOV TEMP[2].xy, IN[3].xyyy
>  5: MOV TEMP[2].w, IN[3].wwww
>  6: TXP TEMP[2], TEMP[2], SAMP[3], 2D
>  7: MAD TEMP[0].xyz, IN[0], TEMP[0].wwww, TEMP[0]
>  8: MOV_SAT TEMP[0].xyz, TEMP[0].xyzz
>  9: MOV TEMP[0].w, IN[0].wwww
> 10: MUL TEMP[0].xyz, TEMP[1], TEMP[0]
> 11: MOV TEMP[0].xyz, TEMP[0].xyzx
> 12: MOV TEMP[0].w, TEMP[1].wwww
> 13: ADD TEMP[1].x, IMM[0].xxxx, -TEMP[2].wwww
> 14: MUL_SAT TEMP[0], TEMP[0], IMM[0].yyyx
> 15: MUL TEMP[0], TEMP[0], TEMP[2].wwww
> 16: MAD TEMP[0].xyz, TEMP[2], TEMP[1].xxxx, TEMP[0]
> 17: MOV TEMP[0].xyz, TEMP[0].xyzx
> 18: MOV TEMP[1].xy, IN[4].xyyy
> 19: MOV TEMP[1].w, IN[4].wwww
> 20: TXP TEMP[1].w, TEMP[1], SAMP[2], 2D
> 21: MOV TEMP[0].w, TEMP[1].wwww
> 22: ADD TEMP[2].x, IMM[0].xxxx, -TEMP[1].wwww
> 23: TXP TEMP[3], IN[5], SAMP[1], CUBE
> 24: MUL TEMP[3], TEMP[3], TEMP[1].wwww
> 25: MAD TEMP[0].xyz, TEMP[0], TEMP[2].xxxx, TEMP[3]
> 26: MOV TEMP[0].xyz, TEMP[0].xyzx
> 27: MOV TEMP[0].w, TEMP[1].wwww
> 28: MUL TEMP[0].xyz, IN[0], TEMP[0]
> 29: MOV TEMP[0].xyz, TEMP[0].xyzx
> 30: MOV TEMP[0].w, TEMP[1].wwww
> 31: MOV TEMP[1].xy, IN[6].xyyy
> 32: MOV TEMP[1].w, IN[6].wwww
> 33: TXP TEMP[1], TEMP[1], SAMP[0], 2D
> 34: MUL_SAT TEMP[2], TEMP[0], IMM[0].yyyx
> 35: MUL TEMP[1].xyz, TEMP[1], TEMP[2]
> 36: MOV TEMP[1].xyz, TEMP[1].xyzx
> 37: MUL_SAT TEMP[0], TEMP[0], IMM[0].yyyx
> 38: MOV TEMP[1].w, TEMP[0].wwww
> 39: MUL_SAT TEMP[0], TEMP[1], IMM[0].yyyx
> 40: MOV OUT[0], TEMP[0]
> 41: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
>  %33 = load <32 x i8> addrspace(2)* %32, !tbaa !0
>  %34 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
>  %37 = load <32 x i8> addrspace(2)* %36, !tbaa !0
>  %38 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
>  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
>  %42 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
>  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
>  %44 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %46 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %47 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %48 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %49 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
>  %50 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %51 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %52 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %53 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %54 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %55 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %56 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %57 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %58 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %59 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %60 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
>  %61 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
>  %62 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
>  %63 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %3, <2 x i32> %5)
>  %64 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %5)
>  %65 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %5)
>  %66 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %3, <2 x i32> %5)
>  %67 = fdiv float %47, %50
>  %68 = fdiv float %48, %50
>  %69 = fdiv float %49, %50
>  %70 = insertelement <4 x float> undef, float %67, i32 0
>  %71 = insertelement <4 x float> %70, float %68, i32 1
>  %72 = insertelement <4 x float> %71, float %69, i32 2
>  %73 = insertelement <4 x float> %72, float 1.000000e+00, i32 3
>  %74 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %73)
>  %75 = extractelement <4 x float> %74, i32 0
>  %76 = extractelement <4 x float> %74, i32 1
>  %77 = extractelement <4 x float> %74, i32 2
>  %78 = extractelement <4 x float> %74, i32 3
>  %79 = call float @fabs(float %77)
>  %80 = fdiv float 1.000000e+00, %79
>  %81 = fmul float %75, %80
>  %82 = fadd float %81, 1.500000e+00
>  %83 = fmul float %76, %80
>  %84 = fadd float %83, 1.500000e+00
>  %85 = bitcast float %84 to i32
>  %86 = bitcast float %82 to i32
>  %87 = bitcast float %78 to i32
>  %88 = insertelement <4 x i32> undef, i32 %85, i32 0
>  %89 = insertelement <4 x i32> %88, i32 %86, i32 1
>  %90 = insertelement <4 x i32> %89, i32 %87, i32 2
>  %91 = insertelement <4 x i32> %90, i32 undef, i32 3
>  %92 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %91, <32 x i8> %41, <16 x i8> %43, i32 4)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = extractelement <4 x float> %92, i32 3
>  %97 = fdiv float %51, %53
>  %98 = fdiv float %52, %53
>  %99 = bitcast float %97 to i32
>  %100 = bitcast float %98 to i32
>  %101 = insertelement <2 x i32> undef, i32 %99, i32 0
>  %102 = insertelement <2 x i32> %101, i32 %100, i32 1
>  %103 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %102, <32 x i8> %37, <16 x i8> %39, i32 2)
>  %104 = extractelement <4 x float> %103, i32 0
>  %105 = extractelement <4 x float> %103, i32 1
>  %106 = extractelement <4 x float> %103, i32 2
>  %107 = extractelement <4 x float> %103, i32 3
>  %108 = fdiv float %54, %56
>  %109 = fdiv float %55, %56
>  %110 = bitcast float %108 to i32
>  %111 = bitcast float %109 to i32
>  %112 = insertelement <2 x i32> undef, i32 %110, i32 0
>  %113 = insertelement <2 x i32> %112, i32 %111, i32 1
>  %114 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %113, <32 x i8> %33, <16 x i8> %35, i32 2)
>  %115 = extractelement <4 x float> %114, i32 0
>  %116 = extractelement <4 x float> %114, i32 1
>  %117 = extractelement <4 x float> %114, i32 2
>  %118 = extractelement <4 x float> %114, i32 3
>  %119 = fmul float %44, %96
>  %120 = fadd float %119, %93
>  %121 = fmul float %45, %96
>  %122 = fadd float %121, %94
>  %123 = fmul float %46, %96
>  %124 = fadd float %123, %95
>  %125 = call float @llvm.AMDIL.clamp.(float %120, float 0.000000e+00, float 1.000000e+00)
>  %126 = call float @llvm.AMDIL.clamp.(float %122, float 0.000000e+00, float 1.000000e+00)
>  %127 = call float @llvm.AMDIL.clamp.(float %124, float 0.000000e+00, float 1.000000e+00)
>  %128 = fmul float %104, %125
>  %129 = fmul float %105, %126
>  %130 = fmul float %106, %127
>  %131 = fsub float -0.000000e+00, %118
>  %132 = fadd float 1.000000e+00, %131
>  %133 = fmul float %128, 2.000000e+00
>  %134 = fmul float %129, 2.000000e+00
>  %135 = fmul float %130, 2.000000e+00
>  %136 = fmul float %107, 1.000000e+00
>  %137 = call float @llvm.AMDIL.clamp.(float %133, float 0.000000e+00, float 1.000000e+00)
>  %138 = call float @llvm.AMDIL.clamp.(float %134, float 0.000000e+00, float 1.000000e+00)
>  %139 = call float @llvm.AMDIL.clamp.(float %135, float 0.000000e+00, float 1.000000e+00)
>  %140 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
>  %141 = fmul float %137, %118
>  %142 = fmul float %138, %118
>  %143 = fmul float %139, %118
>  %144 = fmul float %115, %132
>  %145 = fadd float %144, %141
>  %146 = fmul float %116, %132
>  %147 = fadd float %146, %142
>  %148 = fmul float %117, %132
>  %149 = fadd float %148, %143
>  %150 = fdiv float %57, %59
>  %151 = fdiv float %58, %59
>  %152 = bitcast float %150 to i32
>  %153 = bitcast float %151 to i32
>  %154 = insertelement <2 x i32> undef, i32 %152, i32 0
>  %155 = insertelement <2 x i32> %154, i32 %153, i32 1
>  %156 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %155, <32 x i8> %29, <16 x i8> %31, i32 2)
>  %157 = extractelement <4 x float> %156, i32 3
>  %158 = fsub float -0.000000e+00, %157
>  %159 = fadd float 1.000000e+00, %158
>  %160 = fdiv float %60, %63
>  %161 = fdiv float %61, %63
>  %162 = fdiv float %62, %63
>  %163 = insertelement <4 x float> undef, float %160, i32 0
>  %164 = insertelement <4 x float> %163, float %161, i32 1
>  %165 = insertelement <4 x float> %164, float %162, i32 2
>  %166 = insertelement <4 x float> %165, float 1.000000e+00, i32 3
>  %167 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %166)
>  %168 = extractelement <4 x float> %167, i32 0
>  %169 = extractelement <4 x float> %167, i32 1
>  %170 = extractelement <4 x float> %167, i32 2
>  %171 = extractelement <4 x float> %167, i32 3
>  %172 = call float @fabs(float %170)
>  %173 = fdiv float 1.000000e+00, %172
>  %174 = fmul float %168, %173
>  %175 = fadd float %174, 1.500000e+00
>  %176 = fmul float %169, %173
>  %177 = fadd float %176, 1.500000e+00
>  %178 = bitcast float %177 to i32
>  %179 = bitcast float %175 to i32
>  %180 = bitcast float %171 to i32
>  %181 = insertelement <4 x i32> undef, i32 %178, i32 0
>  %182 = insertelement <4 x i32> %181, i32 %179, i32 1
>  %183 = insertelement <4 x i32> %182, i32 %180, i32 2
>  %184 = insertelement <4 x i32> %183, i32 undef, i32 3
>  %185 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %184, <32 x i8> %25, <16 x i8> %27, i32 4)
>  %186 = extractelement <4 x float> %185, i32 0
>  %187 = extractelement <4 x float> %185, i32 1
>  %188 = extractelement <4 x float> %185, i32 2
>  %189 = fmul float %186, %157
>  %190 = fmul float %187, %157
>  %191 = fmul float %188, %157
>  %192 = fmul float %145, %159
>  %193 = fadd float %192, %189
>  %194 = fmul float %147, %159
>  %195 = fadd float %194, %190
>  %196 = fmul float %149, %159
>  %197 = fadd float %196, %191
>  %198 = fmul float %44, %193
>  %199 = fmul float %45, %195
>  %200 = fmul float %46, %197
>  %201 = fdiv float %64, %66
>  %202 = fdiv float %65, %66
>  %203 = bitcast float %201 to i32
>  %204 = bitcast float %202 to i32
>  %205 = insertelement <2 x i32> undef, i32 %203, i32 0
>  %206 = insertelement <2 x i32> %205, i32 %204, i32 1
>  %207 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %206, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %208 = extractelement <4 x float> %207, i32 0
>  %209 = extractelement <4 x float> %207, i32 1
>  %210 = extractelement <4 x float> %207, i32 2
>  %211 = fmul float %198, 2.000000e+00
>  %212 = fmul float %199, 2.000000e+00
>  %213 = fmul float %200, 2.000000e+00
>  %214 = fmul float %157, 1.000000e+00
>  %215 = call float @llvm.AMDIL.clamp.(float %211, float 0.000000e+00, float 1.000000e+00)
>  %216 = call float @llvm.AMDIL.clamp.(float %212, float 0.000000e+00, float 1.000000e+00)
>  %217 = call float @llvm.AMDIL.clamp.(float %213, float 0.000000e+00, float 1.000000e+00)
>  %218 = call float @llvm.AMDIL.clamp.(float %214, float 0.000000e+00, float 1.000000e+00)
>  %219 = fmul float %208, %215
>  %220 = fmul float %209, %216
>  %221 = fmul float %210, %217
>  %222 = fmul float %198, 2.000000e+00
>  %223 = fmul float %199, 2.000000e+00
>  %224 = fmul float %200, 2.000000e+00
>  %225 = fmul float %157, 1.000000e+00
>  %226 = call float @llvm.AMDIL.clamp.(float %222, float 0.000000e+00, float 1.000000e+00)
>  %227 = call float @llvm.AMDIL.clamp.(float %223, float 0.000000e+00, float 1.000000e+00)
>  %228 = call float @llvm.AMDIL.clamp.(float %224, float 0.000000e+00, float 1.000000e+00)
>  %229 = call float @llvm.AMDIL.clamp.(float %225, float 0.000000e+00, float 1.000000e+00)
>  %230 = fmul float %219, 2.000000e+00
>  %231 = fmul float %220, 2.000000e+00
>  %232 = fmul float %221, 2.000000e+00
>  %233 = fmul float %229, 1.000000e+00
>  %234 = call float @llvm.AMDIL.clamp.(float %230, float 0.000000e+00, float 1.000000e+00)
>  %235 = call float @llvm.AMDIL.clamp.(float %231, float 0.000000e+00, float 1.000000e+00)
>  %236 = call float @llvm.AMDIL.clamp.(float %232, float 0.000000e+00, float 1.000000e+00)
>  %237 = call float @llvm.AMDIL.clamp.(float %233, float 0.000000e+00, float 1.000000e+00)
>  %238 = call i32 @llvm.SI.packf16(float %234, float %235)
>  %239 = bitcast i32 %238 to float
>  %240 = call i32 @llvm.SI.packf16(float %236, float %237)
>  %241 = bitcast i32 %240 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %239, float %241, float %239, float %241)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0500
>c80d0501
>c8080700
>c8090701
>7e045502
>101e0503
>c80c0400
>c80d0401
>101c0503
>c80c0600
>c80d0601
>10200503
>7e2202f2
>d28a0003
>04421f0e
>d28c0002
>04421f0e
>d28e0004
>04421f0e
>d2880005
>04421f0e
>d206010a
>02010104
>7e14550a
>7e2602ff
>3fc00000
>d2820004
>044e1502
>d2820003
>044e1503
>c0840314
>c0c60528
>bf8c007f
>f0800f00
>00430203
>c8480100
>c8490101
>bf8c0770
>d2820006
>040e0b12
>d2060809
>02010106
>c8180900
>c8190901
>c81c0b00
>c81d0b01
>7e105507
>100e1106
>c8280800
>c8290801
>100c110a
>c0840310
>c0c60520
>bf8c007f
>f0800700
>00430606
>bf8c0770
>10141307
>d2820009
>042a1307
>d206080d
>02010109
>c8240d00
>c8250d01
>c8280f00
>c8290f01
>7e16550a
>10141709
>c8300c00
>c8310c01
>1012170c
>c084030c
>c0c60518
>bf8c007f
>f0800f00
>00430909
>bf8c0770
>1028190d
>081a18f2
>d2820014
>04521b0a
>c8581500
>c8591501
>c8541700
>c8551701
>7e2a5515
>101e2b16
>c8581400
>c8591401
>101c2b16
>c8581600
>c8591601
>10202b16
>d28a0016
>04421f0e
>d28c0015
>04421f0e
>d28e0017
>04421f0e
>d2880018
>04421f0e
>d206010e
>02010117
>7e1c550e
>d2820017
>044e1d15
>d2820016
>044e1d16
>c0840304
>c0c60508
>bf8c007f
>f0800700
>00430e16
>c8441100
>c8451101
>c84c1300
>c84d1301
>7e265513
>102c2711
>c8441000
>c8451001
>102a2711
>c0840308
>c0c60510
>bf8c0070
>f0800800
>00431115
>bf8c0770
>102a230f
>082622f2
>d2820014
>04562714
>102a2912
>d2820012
>04562912
>d2060812
>02010112
>c8501900
>c8511901
>c8541b00
>c8551b01
>7e2c5515
>102a2d14
>c85c1800
>c85d1801
>10282d17
>c0800300
>c0c40500
>bf8c007f
>f0800700
>00021414
>bf8c0770
>102e2515
>d2820012
>045e2515
>d2060812
>02010112
>c85c0000
>c85d0001
>d2820018
>040a0b17
>d2060818
>02010118
>10323106
>d2820018
>04663106
>d2060818
>02010118
>10301918
>d2820018
>04621b09
>1032230e
>d2820018
>04662718
>10323117
>d2820017
>04663117
>d2060817
>02010117
>10302f14
>d2820017
>04622f14
>d2060817
>02010117
>5e242517
>c85c0200
>c85d0201
>d2820000
>04120b17
>d2060800
>02010100
>10020108
>d2820000
>04060108
>d2060800
>02010100
>10001900
>d2820000
>04021b0b
>10022310
>d2820000
>04062700
>10020117
>d2820000
>04060117
>d2060800
>02010100
>10020116
>d2820000
>04060116
>d2060800
>02010100
>d2060801
>02010111
>d2060801
>02010101
>5e000300
>f8001c0f
>00120012
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL IN[6]
>DCL IN[7]
>DCL IN[8]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL OUT[5], GENERIC[3]
>DCL OUT[6], GENERIC[4]
>DCL OUT[7], GENERIC[6]
>DCL CONST[0..35]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: DP3 TEMP[1], TEMP[0], TEMP[6]
> 41: ADD TEMP[1], TEMP[1], TEMP[1]
> 42: MAD OUT[2].xyz, -TEMP[1], TEMP[0], TEMP[6]
> 43: MOV OUT[2].w, IN[3]
> 44: MUL TEMP[1], IN[4].xxxx, CONST[20]
> 45: MAD TEMP[1], IN[4].yyyy, CONST[21], TEMP[1]
> 46: MAD TEMP[1], IN[4].zzzz, CONST[22], TEMP[1]
> 47: MAD OUT[3], IN[4].wwww, CONST[23], TEMP[1]
> 48: MOV OUT[4], IN[5]
> 49: MUL TEMP[1], IN[6].xxxx, CONST[24]
> 50: MAD TEMP[1], IN[6].yyyy, CONST[25], TEMP[1]
> 51: MAD TEMP[1], IN[6].zzzz, CONST[26], TEMP[1]
> 52: MAD OUT[5], IN[6].wwww, CONST[27], TEMP[1]
> 53: DP3 TEMP[2], TEMP[0], TEMP[6]
> 54: ADD TEMP[2], TEMP[2], TEMP[2]
> 55: MAD TEMP[1].xyz, -TEMP[2], TEMP[0], TEMP[6]
> 56: MOV TEMP[1].w, IN[7]
> 57: MUL TEMP[2], TEMP[1].xxxx, CONST[28]
> 58: MAD TEMP[2], TEMP[1].yyyy, CONST[29], TEMP[2]
> 59: MAD TEMP[2], TEMP[1].zzzz, CONST[30], TEMP[2]
> 60: MAD OUT[6], TEMP[1].wwww, CONST[31], TEMP[2]
> 61: MUL TEMP[1], IN[8].xxxx, CONST[32]
> 62: MAD TEMP[1], IN[8].yyyy, CONST[33], TEMP[1]
> 63: MAD TEMP[1], IN[8].zzzz, CONST[34], TEMP[1]
> 64: MAD OUT[7], IN[8].wwww, CONST[35], TEMP[1]
> 65: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 444)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 460)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 476)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %113 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 492)
>  %115 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %116 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %117 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %118 = call float @llvm.SI.load.const(<16 x i8> %10, i32 508)
>  %119 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %120 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %121 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %122 = call float @llvm.SI.load.const(<16 x i8> %10, i32 524)
>  %123 = call float @llvm.SI.load.const(<16 x i8> %10, i32 528)
>  %124 = call float @llvm.SI.load.const(<16 x i8> %10, i32 532)
>  %125 = call float @llvm.SI.load.const(<16 x i8> %10, i32 536)
>  %126 = call float @llvm.SI.load.const(<16 x i8> %10, i32 540)
>  %127 = call float @llvm.SI.load.const(<16 x i8> %10, i32 544)
>  %128 = call float @llvm.SI.load.const(<16 x i8> %10, i32 548)
>  %129 = call float @llvm.SI.load.const(<16 x i8> %10, i32 552)
>  %130 = call float @llvm.SI.load.const(<16 x i8> %10, i32 556)
>  %131 = call float @llvm.SI.load.const(<16 x i8> %10, i32 560)
>  %132 = call float @llvm.SI.load.const(<16 x i8> %10, i32 564)
>  %133 = call float @llvm.SI.load.const(<16 x i8> %10, i32 568)
>  %134 = call float @llvm.SI.load.const(<16 x i8> %10, i32 572)
>  %135 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %136 = load <16 x i8> addrspace(2)* %135, !tbaa !0
>  %137 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %136, i32 0, i32 %5)
>  %138 = extractelement <4 x float> %137, i32 0
>  %139 = extractelement <4 x float> %137, i32 1
>  %140 = extractelement <4 x float> %137, i32 2
>  %141 = extractelement <4 x float> %137, i32 3
>  %142 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %143 = load <16 x i8> addrspace(2)* %142, !tbaa !0
>  %144 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %143, i32 0, i32 %5)
>  %145 = extractelement <4 x float> %144, i32 0
>  %146 = extractelement <4 x float> %144, i32 1
>  %147 = extractelement <4 x float> %144, i32 2
>  %148 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %149 = load <16 x i8> addrspace(2)* %148, !tbaa !0
>  %150 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %149, i32 0, i32 %5)
>  %151 = extractelement <4 x float> %150, i32 0
>  %152 = extractelement <4 x float> %150, i32 1
>  %153 = extractelement <4 x float> %150, i32 2
>  %154 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %155 = load <16 x i8> addrspace(2)* %154, !tbaa !0
>  %156 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %155, i32 0, i32 %5)
>  %157 = extractelement <4 x float> %156, i32 3
>  %158 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %159 = load <16 x i8> addrspace(2)* %158, !tbaa !0
>  %160 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %159, i32 0, i32 %5)
>  %161 = extractelement <4 x float> %160, i32 0
>  %162 = extractelement <4 x float> %160, i32 1
>  %163 = extractelement <4 x float> %160, i32 2
>  %164 = extractelement <4 x float> %160, i32 3
>  %165 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %166 = load <16 x i8> addrspace(2)* %165, !tbaa !0
>  %167 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %166, i32 0, i32 %5)
>  %168 = extractelement <4 x float> %167, i32 0
>  %169 = extractelement <4 x float> %167, i32 1
>  %170 = extractelement <4 x float> %167, i32 2
>  %171 = extractelement <4 x float> %167, i32 3
>  %172 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
>  %173 = load <16 x i8> addrspace(2)* %172, !tbaa !0
>  %174 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %173, i32 0, i32 %5)
>  %175 = extractelement <4 x float> %174, i32 0
>  %176 = extractelement <4 x float> %174, i32 1
>  %177 = extractelement <4 x float> %174, i32 2
>  %178 = extractelement <4 x float> %174, i32 3
>  %179 = getelementptr <16 x i8> addrspace(2)* %3, i32 7
>  %180 = load <16 x i8> addrspace(2)* %179, !tbaa !0
>  %181 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %180, i32 0, i32 %5)
>  %182 = extractelement <4 x float> %181, i32 3
>  %183 = getelementptr <16 x i8> addrspace(2)* %3, i32 8
>  %184 = load <16 x i8> addrspace(2)* %183, !tbaa !0
>  %185 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %184, i32 0, i32 %5)
>  %186 = extractelement <4 x float> %185, i32 0
>  %187 = extractelement <4 x float> %185, i32 1
>  %188 = extractelement <4 x float> %185, i32 2
>  %189 = extractelement <4 x float> %185, i32 3
>  %190 = fmul float %138, %11
>  %191 = fmul float %138, %12
>  %192 = fmul float %138, %13
>  %193 = fmul float %138, %14
>  %194 = fmul float %139, %15
>  %195 = fadd float %194, %190
>  %196 = fmul float %139, %16
>  %197 = fadd float %196, %191
>  %198 = fmul float %139, %17
>  %199 = fadd float %198, %192
>  %200 = fmul float %139, %18
>  %201 = fadd float %200, %193
>  %202 = fmul float %140, %19
>  %203 = fadd float %202, %195
>  %204 = fmul float %140, %20
>  %205 = fadd float %204, %197
>  %206 = fmul float %140, %21
>  %207 = fadd float %206, %199
>  %208 = fmul float %140, %22
>  %209 = fadd float %208, %201
>  %210 = fmul float %141, %23
>  %211 = fadd float %210, %203
>  %212 = fmul float %141, %24
>  %213 = fadd float %212, %205
>  %214 = fmul float %141, %25
>  %215 = fadd float %214, %207
>  %216 = fmul float %141, %26
>  %217 = fadd float %216, %209
>  %218 = fmul float %145, %27
>  %219 = fmul float %146, %28
>  %220 = fadd float %219, %218
>  %221 = fmul float %147, %29
>  %222 = fadd float %220, %221
>  %223 = fmul float %145, %30
>  %224 = fmul float %146, %31
>  %225 = fadd float %224, %223
>  %226 = fmul float %147, %32
>  %227 = fadd float %225, %226
>  %228 = fmul float %145, %33
>  %229 = fmul float %146, %34
>  %230 = fadd float %229, %228
>  %231 = fmul float %147, %35
>  %232 = fadd float %230, %231
>  %233 = fmul float %222, %222
>  %234 = fmul float %227, %227
>  %235 = fadd float %234, %233
>  %236 = fmul float %232, %232
>  %237 = fadd float %235, %236
>  %238 = call float @fabs(float %237)
>  %239 = call float @llvm.AMDGPU.rsq(float %238)
>  %240 = fmul float %222, %239
>  %241 = fmul float %227, %239
>  %242 = fmul float %232, %239
>  %243 = fmul float %37, %40
>  %244 = fadd float %243, %151
>  %245 = fmul float %38, %41
>  %246 = fadd float %245, %152
>  %247 = fmul float %39, %42
>  %248 = fadd float %247, %153
>  %249 = call float @llvm.AMDIL.clamp.(float %244, float 0.000000e+00, float 1.000000e+00)
>  %250 = call float @llvm.AMDIL.clamp.(float %246, float 0.000000e+00, float 1.000000e+00)
>  %251 = call float @llvm.AMDIL.clamp.(float %248, float 0.000000e+00, float 1.000000e+00)
>  %252 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %253 = fmul float %138, %47
>  %254 = fmul float %138, %48
>  %255 = fmul float %138, %49
>  %256 = fmul float %139, %50
>  %257 = fadd float %256, %253
>  %258 = fmul float %139, %51
>  %259 = fadd float %258, %254
>  %260 = fmul float %139, %52
>  %261 = fadd float %260, %255
>  %262 = fmul float %140, %53
>  %263 = fadd float %262, %257
>  %264 = fmul float %140, %54
>  %265 = fadd float %264, %259
>  %266 = fmul float %140, %55
>  %267 = fadd float %266, %261
>  %268 = fmul float %141, %56
>  %269 = fadd float %268, %263
>  %270 = fmul float %141, %57
>  %271 = fadd float %270, %265
>  %272 = fmul float %141, %58
>  %273 = fadd float %272, %267
>  %274 = fsub float %44, %269
>  %275 = fsub float %45, %271
>  %276 = fsub float %46, %273
>  %277 = fmul float %274, %274
>  %278 = fmul float %275, %275
>  %279 = fadd float %278, %277
>  %280 = fmul float %276, %276
>  %281 = fadd float %279, %280
>  %282 = call float @fabs(float %281)
>  %283 = call float @llvm.AMDGPU.rsq(float %282)
>  %284 = fmul float %274, %283
>  %285 = fmul float %275, %283
>  %286 = fmul float %276, %283
>  %287 = fdiv float 1.000000e+00, %283
>  %288 = fmul float %283, %287
>  %289 = fmul float %287, %287
>  %290 = fmul float %59, %288
>  %291 = fmul float %60, %287
>  %292 = fadd float %291, %290
>  %293 = fmul float %61, %289
>  %294 = fadd float %292, %293
>  %295 = fdiv float 1.000000e+00, %294
>  %296 = fmul float %269, %269
>  %297 = fmul float %271, %271
>  %298 = fadd float %297, %296
>  %299 = fmul float %273, %273
>  %300 = fadd float %298, %299
>  %301 = call float @fabs(float %300)
>  %302 = call float @llvm.AMDGPU.rsq(float %301)
>  %303 = fmul float %269, %302
>  %304 = fmul float %271, %302
>  %305 = fmul float %273, %302
>  %306 = fsub float %284, %303
>  %307 = fsub float %285, %304
>  %308 = fsub float %286, %305
>  %309 = fmul float %306, %306
>  %310 = fmul float %307, %307
>  %311 = fadd float %310, %309
>  %312 = fmul float %308, %308
>  %313 = fadd float %311, %312
>  %314 = call float @fabs(float %313)
>  %315 = call float @llvm.AMDGPU.rsq(float %314)
>  %316 = fmul float %306, %315
>  %317 = fmul float %307, %315
>  %318 = fmul float %308, %315
>  %319 = fmul float %240, %284
>  %320 = fmul float %241, %285
>  %321 = fadd float %320, %319
>  %322 = fmul float %242, %286
>  %323 = fadd float %321, %322
>  %324 = fmul float %240, %316
>  %325 = fmul float %241, %317
>  %326 = fadd float %325, %324
>  %327 = fmul float %242, %318
>  %328 = fadd float %326, %327
>  %329 = fcmp uge float %323, 0.000000e+00
>  %330 = select i1 %329, float %323, float 0.000000e+00
>  %331 = fcmp uge float %328, 0.000000e+00
>  %332 = select i1 %331, float %328, float 0.000000e+00
>  %333 = call float @llvm.pow.f32(float %332, float %36)
>  %334 = call float @llvm.AMDGPU.cndlt(float %323, float 0.000000e+00, float %333)
>  %335 = fmul float 1.000000e+00, %295
>  %336 = fmul float %330, %295
>  %337 = fmul float %334, %295
>  %338 = fmul float %335, %62
>  %339 = fadd float %338, %244
>  %340 = fmul float %335, %63
>  %341 = fadd float %340, %246
>  %342 = fmul float %335, %64
>  %343 = fadd float %342, %248
>  %344 = fmul float %336, %65
>  %345 = fadd float %344, %339
>  %346 = fmul float %336, %66
>  %347 = fadd float %346, %341
>  %348 = fmul float %336, %67
>  %349 = fadd float %348, %343
>  %350 = fmul float %337, %68
>  %351 = fadd float %350, %345
>  %352 = fmul float %337, %69
>  %353 = fadd float %352, %347
>  %354 = fmul float %337, %70
>  %355 = fadd float %354, %349
>  %356 = call float @llvm.AMDIL.clamp.(float %351, float 0.000000e+00, float 1.000000e+00)
>  %357 = call float @llvm.AMDIL.clamp.(float %353, float 0.000000e+00, float 1.000000e+00)
>  %358 = call float @llvm.AMDIL.clamp.(float %355, float 0.000000e+00, float 1.000000e+00)
>  %359 = fmul float %240, %303
>  %360 = fmul float %241, %304
>  %361 = fadd float %360, %359
>  %362 = fmul float %242, %305
>  %363 = fadd float %361, %362
>  %364 = fadd float %363, %363
>  %365 = fadd float %363, %363
>  %366 = fadd float %363, %363
>  %367 = fsub float -0.000000e+00, %364
>  %368 = fmul float %367, %240
>  %369 = fadd float %368, %303
>  %370 = fsub float -0.000000e+00, %365
>  %371 = fmul float %370, %241
>  %372 = fadd float %371, %304
>  %373 = fsub float -0.000000e+00, %366
>  %374 = fmul float %373, %242
>  %375 = fadd float %374, %305
>  %376 = fmul float %161, %71
>  %377 = fmul float %161, %72
>  %378 = fmul float %161, %73
>  %379 = fmul float %161, %74
>  %380 = fmul float %162, %75
>  %381 = fadd float %380, %376
>  %382 = fmul float %162, %76
>  %383 = fadd float %382, %377
>  %384 = fmul float %162, %77
>  %385 = fadd float %384, %378
>  %386 = fmul float %162, %78
>  %387 = fadd float %386, %379
>  %388 = fmul float %163, %79
>  %389 = fadd float %388, %381
>  %390 = fmul float %163, %80
>  %391 = fadd float %390, %383
>  %392 = fmul float %163, %81
>  %393 = fadd float %392, %385
>  %394 = fmul float %163, %82
>  %395 = fadd float %394, %387
>  %396 = fmul float %164, %83
>  %397 = fadd float %396, %389
>  %398 = fmul float %164, %84
>  %399 = fadd float %398, %391
>  %400 = fmul float %164, %85
>  %401 = fadd float %400, %393
>  %402 = fmul float %164, %86
>  %403 = fadd float %402, %395
>  %404 = fmul float %175, %87
>  %405 = fmul float %175, %88
>  %406 = fmul float %175, %89
>  %407 = fmul float %175, %90
>  %408 = fmul float %176, %91
>  %409 = fadd float %408, %404
>  %410 = fmul float %176, %92
>  %411 = fadd float %410, %405
>  %412 = fmul float %176, %93
>  %413 = fadd float %412, %406
>  %414 = fmul float %176, %94
>  %415 = fadd float %414, %407
>  %416 = fmul float %177, %95
>  %417 = fadd float %416, %409
>  %418 = fmul float %177, %96
>  %419 = fadd float %418, %411
>  %420 = fmul float %177, %97
>  %421 = fadd float %420, %413
>  %422 = fmul float %177, %98
>  %423 = fadd float %422, %415
>  %424 = fmul float %178, %99
>  %425 = fadd float %424, %417
>  %426 = fmul float %178, %100
>  %427 = fadd float %426, %419
>  %428 = fmul float %178, %101
>  %429 = fadd float %428, %421
>  %430 = fmul float %178, %102
>  %431 = fadd float %430, %423
>  %432 = fmul float %240, %303
>  %433 = fmul float %241, %304
>  %434 = fadd float %433, %432
>  %435 = fmul float %242, %305
>  %436 = fadd float %434, %435
>  %437 = fadd float %436, %436
>  %438 = fadd float %436, %436
>  %439 = fadd float %436, %436
>  %440 = fsub float -0.000000e+00, %437
>  %441 = fmul float %440, %240
>  %442 = fadd float %441, %303
>  %443 = fsub float -0.000000e+00, %438
>  %444 = fmul float %443, %241
>  %445 = fadd float %444, %304
>  %446 = fsub float -0.000000e+00, %439
>  %447 = fmul float %446, %242
>  %448 = fadd float %447, %305
>  %449 = fmul float %442, %103
>  %450 = fmul float %442, %104
>  %451 = fmul float %442, %105
>  %452 = fmul float %442, %106
>  %453 = fmul float %445, %107
>  %454 = fadd float %453, %449
>  %455 = fmul float %445, %108
>  %456 = fadd float %455, %450
>  %457 = fmul float %445, %109
>  %458 = fadd float %457, %451
>  %459 = fmul float %445, %110
>  %460 = fadd float %459, %452
>  %461 = fmul float %448, %111
>  %462 = fadd float %461, %454
>  %463 = fmul float %448, %112
>  %464 = fadd float %463, %456
>  %465 = fmul float %448, %113
>  %466 = fadd float %465, %458
>  %467 = fmul float %448, %114
>  %468 = fadd float %467, %460
>  %469 = fmul float %182, %115
>  %470 = fadd float %469, %462
>  %471 = fmul float %182, %116
>  %472 = fadd float %471, %464
>  %473 = fmul float %182, %117
>  %474 = fadd float %473, %466
>  %475 = fmul float %182, %118
>  %476 = fadd float %475, %468
>  %477 = fmul float %186, %119
>  %478 = fmul float %186, %120
>  %479 = fmul float %186, %121
>  %480 = fmul float %186, %122
>  %481 = fmul float %187, %123
>  %482 = fadd float %481, %477
>  %483 = fmul float %187, %124
>  %484 = fadd float %483, %478
>  %485 = fmul float %187, %125
>  %486 = fadd float %485, %479
>  %487 = fmul float %187, %126
>  %488 = fadd float %487, %480
>  %489 = fmul float %188, %127
>  %490 = fadd float %489, %482
>  %491 = fmul float %188, %128
>  %492 = fadd float %491, %484
>  %493 = fmul float %188, %129
>  %494 = fadd float %493, %486
>  %495 = fmul float %188, %130
>  %496 = fadd float %495, %488
>  %497 = fmul float %189, %131
>  %498 = fadd float %497, %490
>  %499 = fmul float %189, %132
>  %500 = fadd float %499, %492
>  %501 = fmul float %189, %133
>  %502 = fadd float %501, %494
>  %503 = fmul float %189, %134
>  %504 = fadd float %503, %496
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %356, float %357, float %358, float %252)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %369, float %372, float %375, float %157)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %397, float %399, float %401, float %403)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %168, float %169, float %170, float %171)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %425, float %427, float %429, float %431)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %470, float %472, float %474, float %476)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %498, float %500, float %502, float %504)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %211, float %213, float %215, float %217)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820007
>04140904
>c2020130
>bf8c007f
>100a0204
>c2020134
>bf8c007f
>d2820005
>04140902
>c2020138
>bf8c007f
>d2820005
>04140903
>c202013c
>bf8c007f
>d2820006
>04140904
>100a0d06
>d2820005
>04160f07
>c2020132
>bf8c007f
>10100204
>c2020136
>bf8c007f
>d2820008
>04200902
>c202013a
>bf8c007f
>d2820008
>04200903
>c202013e
>bf8c007f
>d2820008
>04200904
>d2820005
>04161108
>d2060105
>02010105
>7e125b05
>100a1307
>c202012d
>bf8c007f
>080e0e04
>c202012c
>bf8c007f
>081a0c04
>10141b0d
>d282000b
>042a0f07
>c202012e
>bf8c007f
>08141004
>d282000b
>042e150a
>d206010b
>0201010b
>7e165b0b
>10181707
>08200b0c
>100e1306
>101a170d
>08220f0d
>100c2311
>d282000f
>041a2110
>100c1308
>101c170a
>08140d0e
>d2820008
>043e150a
>d2060108
>02010108
>7e1e5b08
>10201f10
>10121f11
>c0840704
>bf8c007f
>e00c2000
>80021100
>c2020114
>bf8c0070
>10102204
>c2020115
>bf8c007f
>d2820008
>04200912
>c2020116
>bf8c007f
>d2820015
>04200913
>c2020110
>bf8c007f
>10102204
>c2020111
>bf8c007f
>d2820008
>04200912
>c2020112
>bf8c007f
>d2820008
>04200913
>102c1108
>d2820016
>045a2b15
>c2020118
>bf8c007f
>102e2204
>c2020119
>bf8c007f
>d2820017
>045c0912
>c202011a
>bf8c007f
>d2820011
>045c0913
>d2820012
>045a2311
>d2060112
>02010112
>7e245b12
>10102508
>10261308
>10122515
>d2820010
>044e2109
>101e1f0a
>10142511
>d282000f
>04421f0a
>d00c0004
>0201010f
>d200000f
>00121e80
>7e1e4f0f
>c202011c
>bf8c007f
>0e1e1e04
>7e1e4b0f
>101a1b08
>d282000c
>04361909
>d282000d
>04321d0a
>d0080004
>02021a80
>d200000e
>0011010f
>7e18550b
>1016190b
>c2020140
>bf8c007f
>10161604
>c2020141
>bf8c007f
>d282000b
>042e1804
>1018190c
>c2020142
>bf8c007f
>d282000b
>042e1804
>7e18550b
>1016190e
>d00c0004
>0201010d
>d200000d
>00121a80
>101a190d
>c0840708
>bf8c007f
>e00c2000
>80020e00
>c2020122
>c2028126
>bf8c0070
>7e240205
>d2820012
>04422404
>c2020146
>bf8c007f
>d2820012
>0448090c
>c202014a
>bf8c007f
>d2820012
>0448090d
>c202014e
>bf8c007f
>d2820012
>0448090b
>d2060812
>02010112
>c2020121
>c2028125
>bf8c007f
>7e260205
>d2820013
>043e2604
>c2020145
>bf8c007f
>d2820013
>044c090c
>c2020149
>bf8c007f
>d2820013
>044c090d
>c202014d
>bf8c007f
>d2820013
>044c090b
>d2060813
>02010113
>c2020120
>c2028124
>bf8c007f
>7e280205
>d282000e
>043a2804
>c2020144
>bf8c007f
>d282000c
>0438090c
>c2020148
>bf8c007f
>d282000c
>0430090d
>c202014c
>bf8c007f
>d282000b
>0430090b
>d206080b
>0201010b
>c202012b
>bf8c007f
>d206080c
>02010004
>f800020f
>0c12130b
>bf8c070f
>10160f08
>d282000b
>042e0b09
>d282000b
>042e0d0a
>0616170b
>1014150b
>080c1506
>1012130b
>080a1305
>1010110b
>080e1107
>c084070c
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800021f
>0b060507
>c0840710
>bf8c000f
>e00c2000
>80020800
>c2020153
>bf8c0070
>10181004
>c2020157
>bf8c007f
>d282000c
>04300909
>c202015b
>bf8c007f
>d282000c
>0430090a
>c202015f
>bf8c007f
>d282000c
>0430090b
>c2020152
>bf8c007f
>101a1004
>c2020156
>bf8c007f
>d282000d
>04340909
>c202015a
>bf8c007f
>d282000d
>0434090a
>c202015e
>bf8c007f
>d282000d
>0434090b
>c2020151
>bf8c007f
>101c1004
>c2020155
>bf8c007f
>d282000e
>04380909
>c2020159
>bf8c007f
>d282000e
>0438090a
>c202015d
>bf8c007f
>d282000e
>0438090b
>c2020150
>bf8c007f
>101e1004
>c2020154
>bf8c007f
>d282000f
>043c0909
>c2020158
>bf8c007f
>d282000f
>043c090a
>c202015c
>bf8c007f
>d2820008
>043c090b
>f800022f
>0c0d0e08
>c0840714
>bf8c000f
>e00c2000
>80020800
>bf8c0770
>f800023f
>0b0a0908
>c0840718
>bf8c000f
>e00c2000
>80020800
>c2020163
>bf8c0070
>10181004
>c2020167
>bf8c007f
>d282000c
>04300909
>c202016b
>bf8c007f
>d282000c
>0430090a
>c202016f
>bf8c007f
>d282000c
>0430090b
>c2020162
>bf8c007f
>101a1004
>c2020166
>bf8c007f
>d282000d
>04340909
>c202016a
>bf8c007f
>d282000d
>0434090a
>c202016e
>bf8c007f
>d282000d
>0434090b
>c2020161
>bf8c007f
>101c1004
>c2020165
>bf8c007f
>d282000e
>04380909
>c2020169
>bf8c007f
>d282000e
>0438090a
>c202016d
>bf8c007f
>d282000e
>0438090b
>c2020160
>bf8c007f
>101e1004
>c2020164
>bf8c007f
>d282000f
>043c0909
>c2020168
>bf8c007f
>d282000f
>043c090a
>c202016c
>bf8c007f
>d2820008
>043c090b
>f800024f
>0c0d0e08
>c2020173
>bf8c000f
>10100e04
>c2020177
>bf8c007f
>d2820008
>04200905
>c202017b
>bf8c007f
>d282000c
>04200906
>c084071c
>bf8c007f
>e00c2000
>80020800
>c202017f
>bf8c0070
>d282000c
>0430090b
>c2020172
>bf8c007f
>101a0e04
>c2020176
>bf8c007f
>d282000d
>04340905
>c202017a
>bf8c007f
>d282000d
>04340906
>c202017e
>bf8c007f
>d282000d
>0434090b
>c2020171
>bf8c007f
>101c0e04
>c2020175
>bf8c007f
>d282000e
>04380905
>c2020179
>bf8c007f
>d282000e
>04380906
>c202017d
>bf8c007f
>d282000e
>0438090b
>c2020170
>bf8c007f
>100e0e04
>c2020174
>bf8c007f
>d2820005
>041c0905
>c2020178
>bf8c007f
>d2820005
>04140906
>c202017c
>bf8c007f
>d2820005
>0414090b
>f800025f
>0c0d0e05
>c0820720
>bf8c000f
>e00c2000
>80010500
>c2020183
>bf8c0070
>10000a04
>c2020187
>bf8c007f
>d2820000
>04000906
>c202018b
>bf8c007f
>d2820000
>04000907
>c202018f
>bf8c007f
>d2820000
>04000908
>c2020182
>bf8c007f
>10120a04
>c2020186
>bf8c007f
>d2820009
>04240906
>c202018a
>bf8c007f
>d2820009
>04240907
>c202018e
>bf8c007f
>d2820009
>04240908
>c2020181
>bf8c007f
>10140a04
>c2020185
>bf8c007f
>d282000a
>04280906
>c2020189
>bf8c007f
>d282000a
>04280907
>c202018d
>bf8c007f
>d282000a
>04280908
>c2020180
>bf8c007f
>10160a04
>c2020184
>bf8c007f
>d282000b
>042c0906
>c2020188
>bf8c007f
>d282000b
>042c0907
>c202018c
>bf8c007f
>d2820005
>042c0908
>f800026f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..23]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: MUL TEMP[1], IN[3].xxxx, CONST[20]
> 41: MAD TEMP[1], IN[3].yyyy, CONST[21], TEMP[1]
> 42: MAD TEMP[1], IN[3].zzzz, CONST[22], TEMP[1]
> 43: MAD OUT[2], IN[3].wwww, CONST[23], TEMP[1]
> 44: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %87 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
>  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %5)
>  %90 = extractelement <4 x float> %89, i32 0
>  %91 = extractelement <4 x float> %89, i32 1
>  %92 = extractelement <4 x float> %89, i32 2
>  %93 = extractelement <4 x float> %89, i32 3
>  %94 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %95 = load <16 x i8> addrspace(2)* %94, !tbaa !0
>  %96 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %95, i32 0, i32 %5)
>  %97 = extractelement <4 x float> %96, i32 0
>  %98 = extractelement <4 x float> %96, i32 1
>  %99 = extractelement <4 x float> %96, i32 2
>  %100 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %101 = load <16 x i8> addrspace(2)* %100, !tbaa !0
>  %102 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %101, i32 0, i32 %5)
>  %103 = extractelement <4 x float> %102, i32 0
>  %104 = extractelement <4 x float> %102, i32 1
>  %105 = extractelement <4 x float> %102, i32 2
>  %106 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %107 = load <16 x i8> addrspace(2)* %106, !tbaa !0
>  %108 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %107, i32 0, i32 %5)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = extractelement <4 x float> %108, i32 1
>  %111 = extractelement <4 x float> %108, i32 2
>  %112 = extractelement <4 x float> %108, i32 3
>  %113 = fmul float %90, %11
>  %114 = fmul float %90, %12
>  %115 = fmul float %90, %13
>  %116 = fmul float %90, %14
>  %117 = fmul float %91, %15
>  %118 = fadd float %117, %113
>  %119 = fmul float %91, %16
>  %120 = fadd float %119, %114
>  %121 = fmul float %91, %17
>  %122 = fadd float %121, %115
>  %123 = fmul float %91, %18
>  %124 = fadd float %123, %116
>  %125 = fmul float %92, %19
>  %126 = fadd float %125, %118
>  %127 = fmul float %92, %20
>  %128 = fadd float %127, %120
>  %129 = fmul float %92, %21
>  %130 = fadd float %129, %122
>  %131 = fmul float %92, %22
>  %132 = fadd float %131, %124
>  %133 = fmul float %93, %23
>  %134 = fadd float %133, %126
>  %135 = fmul float %93, %24
>  %136 = fadd float %135, %128
>  %137 = fmul float %93, %25
>  %138 = fadd float %137, %130
>  %139 = fmul float %93, %26
>  %140 = fadd float %139, %132
>  %141 = fmul float %97, %27
>  %142 = fmul float %98, %28
>  %143 = fadd float %142, %141
>  %144 = fmul float %99, %29
>  %145 = fadd float %143, %144
>  %146 = fmul float %97, %30
>  %147 = fmul float %98, %31
>  %148 = fadd float %147, %146
>  %149 = fmul float %99, %32
>  %150 = fadd float %148, %149
>  %151 = fmul float %97, %33
>  %152 = fmul float %98, %34
>  %153 = fadd float %152, %151
>  %154 = fmul float %99, %35
>  %155 = fadd float %153, %154
>  %156 = fmul float %145, %145
>  %157 = fmul float %150, %150
>  %158 = fadd float %157, %156
>  %159 = fmul float %155, %155
>  %160 = fadd float %158, %159
>  %161 = call float @fabs(float %160)
>  %162 = call float @llvm.AMDGPU.rsq(float %161)
>  %163 = fmul float %145, %162
>  %164 = fmul float %150, %162
>  %165 = fmul float %155, %162
>  %166 = fmul float %37, %40
>  %167 = fadd float %166, %103
>  %168 = fmul float %38, %41
>  %169 = fadd float %168, %104
>  %170 = fmul float %39, %42
>  %171 = fadd float %170, %105
>  %172 = call float @llvm.AMDIL.clamp.(float %167, float 0.000000e+00, float 1.000000e+00)
>  %173 = call float @llvm.AMDIL.clamp.(float %169, float 0.000000e+00, float 1.000000e+00)
>  %174 = call float @llvm.AMDIL.clamp.(float %171, float 0.000000e+00, float 1.000000e+00)
>  %175 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %176 = fmul float %90, %47
>  %177 = fmul float %90, %48
>  %178 = fmul float %90, %49
>  %179 = fmul float %91, %50
>  %180 = fadd float %179, %176
>  %181 = fmul float %91, %51
>  %182 = fadd float %181, %177
>  %183 = fmul float %91, %52
>  %184 = fadd float %183, %178
>  %185 = fmul float %92, %53
>  %186 = fadd float %185, %180
>  %187 = fmul float %92, %54
>  %188 = fadd float %187, %182
>  %189 = fmul float %92, %55
>  %190 = fadd float %189, %184
>  %191 = fmul float %93, %56
>  %192 = fadd float %191, %186
>  %193 = fmul float %93, %57
>  %194 = fadd float %193, %188
>  %195 = fmul float %93, %58
>  %196 = fadd float %195, %190
>  %197 = fsub float %44, %192
>  %198 = fsub float %45, %194
>  %199 = fsub float %46, %196
>  %200 = fmul float %197, %197
>  %201 = fmul float %198, %198
>  %202 = fadd float %201, %200
>  %203 = fmul float %199, %199
>  %204 = fadd float %202, %203
>  %205 = call float @fabs(float %204)
>  %206 = call float @llvm.AMDGPU.rsq(float %205)
>  %207 = fmul float %197, %206
>  %208 = fmul float %198, %206
>  %209 = fmul float %199, %206
>  %210 = fdiv float 1.000000e+00, %206
>  %211 = fmul float %206, %210
>  %212 = fmul float %210, %210
>  %213 = fmul float %59, %211
>  %214 = fmul float %60, %210
>  %215 = fadd float %214, %213
>  %216 = fmul float %61, %212
>  %217 = fadd float %215, %216
>  %218 = fdiv float 1.000000e+00, %217
>  %219 = fmul float %192, %192
>  %220 = fmul float %194, %194
>  %221 = fadd float %220, %219
>  %222 = fmul float %196, %196
>  %223 = fadd float %221, %222
>  %224 = call float @fabs(float %223)
>  %225 = call float @llvm.AMDGPU.rsq(float %224)
>  %226 = fmul float %192, %225
>  %227 = fmul float %194, %225
>  %228 = fmul float %196, %225
>  %229 = fsub float %207, %226
>  %230 = fsub float %208, %227
>  %231 = fsub float %209, %228
>  %232 = fmul float %229, %229
>  %233 = fmul float %230, %230
>  %234 = fadd float %233, %232
>  %235 = fmul float %231, %231
>  %236 = fadd float %234, %235
>  %237 = call float @fabs(float %236)
>  %238 = call float @llvm.AMDGPU.rsq(float %237)
>  %239 = fmul float %229, %238
>  %240 = fmul float %230, %238
>  %241 = fmul float %231, %238
>  %242 = fmul float %163, %207
>  %243 = fmul float %164, %208
>  %244 = fadd float %243, %242
>  %245 = fmul float %165, %209
>  %246 = fadd float %244, %245
>  %247 = fmul float %163, %239
>  %248 = fmul float %164, %240
>  %249 = fadd float %248, %247
>  %250 = fmul float %165, %241
>  %251 = fadd float %249, %250
>  %252 = fcmp uge float %246, 0.000000e+00
>  %253 = select i1 %252, float %246, float 0.000000e+00
>  %254 = fcmp uge float %251, 0.000000e+00
>  %255 = select i1 %254, float %251, float 0.000000e+00
>  %256 = call float @llvm.pow.f32(float %255, float %36)
>  %257 = call float @llvm.AMDGPU.cndlt(float %246, float 0.000000e+00, float %256)
>  %258 = fmul float 1.000000e+00, %218
>  %259 = fmul float %253, %218
>  %260 = fmul float %257, %218
>  %261 = fmul float %258, %62
>  %262 = fadd float %261, %167
>  %263 = fmul float %258, %63
>  %264 = fadd float %263, %169
>  %265 = fmul float %258, %64
>  %266 = fadd float %265, %171
>  %267 = fmul float %259, %65
>  %268 = fadd float %267, %262
>  %269 = fmul float %259, %66
>  %270 = fadd float %269, %264
>  %271 = fmul float %259, %67
>  %272 = fadd float %271, %266
>  %273 = fmul float %260, %68
>  %274 = fadd float %273, %268
>  %275 = fmul float %260, %69
>  %276 = fadd float %275, %270
>  %277 = fmul float %260, %70
>  %278 = fadd float %277, %272
>  %279 = call float @llvm.AMDIL.clamp.(float %274, float 0.000000e+00, float 1.000000e+00)
>  %280 = call float @llvm.AMDIL.clamp.(float %276, float 0.000000e+00, float 1.000000e+00)
>  %281 = call float @llvm.AMDIL.clamp.(float %278, float 0.000000e+00, float 1.000000e+00)
>  %282 = fmul float %109, %71
>  %283 = fmul float %109, %72
>  %284 = fmul float %109, %73
>  %285 = fmul float %109, %74
>  %286 = fmul float %110, %75
>  %287 = fadd float %286, %282
>  %288 = fmul float %110, %76
>  %289 = fadd float %288, %283
>  %290 = fmul float %110, %77
>  %291 = fadd float %290, %284
>  %292 = fmul float %110, %78
>  %293 = fadd float %292, %285
>  %294 = fmul float %111, %79
>  %295 = fadd float %294, %287
>  %296 = fmul float %111, %80
>  %297 = fadd float %296, %289
>  %298 = fmul float %111, %81
>  %299 = fadd float %298, %291
>  %300 = fmul float %111, %82
>  %301 = fadd float %300, %293
>  %302 = fmul float %112, %83
>  %303 = fadd float %302, %295
>  %304 = fmul float %112, %84
>  %305 = fadd float %304, %297
>  %306 = fmul float %112, %85
>  %307 = fadd float %306, %299
>  %308 = fmul float %112, %86
>  %309 = fadd float %308, %301
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %279, float %280, float %281, float %175)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %303, float %305, float %307, float %309)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %134, float %136, float %138, float %140)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
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>c2020110
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>10241a04
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>bf8c007f
>d2820012
>0448090e
>c2020112
>bf8c007f
>d2820012
>0448090f
>10262512
>d2820013
>044e2311
>c2020118
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>10281a04
>c2020119
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>0450090e
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>044e1d0e
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>0201010d
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>100a0d08
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>00120e80
>100e0d07
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>e00c2000
>80020800
>c2020122
>c2028126
>bf8c0070
>7e180205
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>042a1804
>c2020146
>bf8c007f
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>04300906
>c202014a
>bf8c007f
>d282000c
>04300907
>c202014e
>bf8c007f
>d282000c
>04300905
>d206080c
>0201010c
>c2020121
>c2028125
>bf8c007f
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>04261a04
>c2020145
>bf8c007f
>d282000d
>04340906
>c2020149
>bf8c007f
>d282000d
>04340907
>c202014d
>bf8c007f
>d282000d
>04340905
>d206080d
>0201010d
>c2020120
>c2028124
>bf8c007f
>7e1c0205
>d2820008
>04221c04
>c2020144
>bf8c007f
>d2820006
>04200906
>c2020148
>bf8c007f
>d2820006
>04180907
>c202014c
>bf8c007f
>d2820005
>04180905
>d2060805
>02010105
>c202012b
>bf8c007f
>d2060806
>02010004
>f800020f
>060c0d05
>c082070c
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>e00c2000
>80010500
>c2020153
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>10000a04
>c2020157
>bf8c007f
>d2820000
>04000906
>c202015b
>bf8c007f
>d2820000
>04000907
>c202015f
>bf8c007f
>d2820000
>04000908
>c2020152
>bf8c007f
>10120a04
>c2020156
>bf8c007f
>d2820009
>04240906
>c202015a
>bf8c007f
>d2820009
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>c202015e
>bf8c007f
>d2820009
>04240908
>c2020151
>bf8c007f
>10140a04
>c2020155
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>d282000a
>04280906
>c2020159
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>04280907
>c202015d
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>d282000a
>04280908
>c2020150
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>10160a04
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>04000904
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>100a0204
>c2020106
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>c202010a
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>04140903
>c202010e
>bf8c007f
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>04140904
>c2020101
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>100c0204
>c2020105
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>04180902
>c2020109
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>04180903
>c202010d
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>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..23]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: MOV OUT[2], IN[3]
> 41: MUL TEMP[1], IN[4].xxxx, CONST[20]
> 42: MAD TEMP[1], IN[4].yyyy, CONST[21], TEMP[1]
> 43: MAD TEMP[1], IN[4].zzzz, CONST[22], TEMP[1]
> 44: MAD OUT[3], IN[4].wwww, CONST[23], TEMP[1]
> 45: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %87 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
>  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %5)
>  %90 = extractelement <4 x float> %89, i32 0
>  %91 = extractelement <4 x float> %89, i32 1
>  %92 = extractelement <4 x float> %89, i32 2
>  %93 = extractelement <4 x float> %89, i32 3
>  %94 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %95 = load <16 x i8> addrspace(2)* %94, !tbaa !0
>  %96 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %95, i32 0, i32 %5)
>  %97 = extractelement <4 x float> %96, i32 0
>  %98 = extractelement <4 x float> %96, i32 1
>  %99 = extractelement <4 x float> %96, i32 2
>  %100 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %101 = load <16 x i8> addrspace(2)* %100, !tbaa !0
>  %102 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %101, i32 0, i32 %5)
>  %103 = extractelement <4 x float> %102, i32 0
>  %104 = extractelement <4 x float> %102, i32 1
>  %105 = extractelement <4 x float> %102, i32 2
>  %106 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %107 = load <16 x i8> addrspace(2)* %106, !tbaa !0
>  %108 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %107, i32 0, i32 %5)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = extractelement <4 x float> %108, i32 1
>  %111 = extractelement <4 x float> %108, i32 2
>  %112 = extractelement <4 x float> %108, i32 3
>  %113 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %114 = load <16 x i8> addrspace(2)* %113, !tbaa !0
>  %115 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %114, i32 0, i32 %5)
>  %116 = extractelement <4 x float> %115, i32 0
>  %117 = extractelement <4 x float> %115, i32 1
>  %118 = extractelement <4 x float> %115, i32 2
>  %119 = extractelement <4 x float> %115, i32 3
>  %120 = fmul float %90, %11
>  %121 = fmul float %90, %12
>  %122 = fmul float %90, %13
>  %123 = fmul float %90, %14
>  %124 = fmul float %91, %15
>  %125 = fadd float %124, %120
>  %126 = fmul float %91, %16
>  %127 = fadd float %126, %121
>  %128 = fmul float %91, %17
>  %129 = fadd float %128, %122
>  %130 = fmul float %91, %18
>  %131 = fadd float %130, %123
>  %132 = fmul float %92, %19
>  %133 = fadd float %132, %125
>  %134 = fmul float %92, %20
>  %135 = fadd float %134, %127
>  %136 = fmul float %92, %21
>  %137 = fadd float %136, %129
>  %138 = fmul float %92, %22
>  %139 = fadd float %138, %131
>  %140 = fmul float %93, %23
>  %141 = fadd float %140, %133
>  %142 = fmul float %93, %24
>  %143 = fadd float %142, %135
>  %144 = fmul float %93, %25
>  %145 = fadd float %144, %137
>  %146 = fmul float %93, %26
>  %147 = fadd float %146, %139
>  %148 = fmul float %97, %27
>  %149 = fmul float %98, %28
>  %150 = fadd float %149, %148
>  %151 = fmul float %99, %29
>  %152 = fadd float %150, %151
>  %153 = fmul float %97, %30
>  %154 = fmul float %98, %31
>  %155 = fadd float %154, %153
>  %156 = fmul float %99, %32
>  %157 = fadd float %155, %156
>  %158 = fmul float %97, %33
>  %159 = fmul float %98, %34
>  %160 = fadd float %159, %158
>  %161 = fmul float %99, %35
>  %162 = fadd float %160, %161
>  %163 = fmul float %152, %152
>  %164 = fmul float %157, %157
>  %165 = fadd float %164, %163
>  %166 = fmul float %162, %162
>  %167 = fadd float %165, %166
>  %168 = call float @fabs(float %167)
>  %169 = call float @llvm.AMDGPU.rsq(float %168)
>  %170 = fmul float %152, %169
>  %171 = fmul float %157, %169
>  %172 = fmul float %162, %169
>  %173 = fmul float %37, %40
>  %174 = fadd float %173, %103
>  %175 = fmul float %38, %41
>  %176 = fadd float %175, %104
>  %177 = fmul float %39, %42
>  %178 = fadd float %177, %105
>  %179 = call float @llvm.AMDIL.clamp.(float %174, float 0.000000e+00, float 1.000000e+00)
>  %180 = call float @llvm.AMDIL.clamp.(float %176, float 0.000000e+00, float 1.000000e+00)
>  %181 = call float @llvm.AMDIL.clamp.(float %178, float 0.000000e+00, float 1.000000e+00)
>  %182 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %183 = fmul float %90, %47
>  %184 = fmul float %90, %48
>  %185 = fmul float %90, %49
>  %186 = fmul float %91, %50
>  %187 = fadd float %186, %183
>  %188 = fmul float %91, %51
>  %189 = fadd float %188, %184
>  %190 = fmul float %91, %52
>  %191 = fadd float %190, %185
>  %192 = fmul float %92, %53
>  %193 = fadd float %192, %187
>  %194 = fmul float %92, %54
>  %195 = fadd float %194, %189
>  %196 = fmul float %92, %55
>  %197 = fadd float %196, %191
>  %198 = fmul float %93, %56
>  %199 = fadd float %198, %193
>  %200 = fmul float %93, %57
>  %201 = fadd float %200, %195
>  %202 = fmul float %93, %58
>  %203 = fadd float %202, %197
>  %204 = fsub float %44, %199
>  %205 = fsub float %45, %201
>  %206 = fsub float %46, %203
>  %207 = fmul float %204, %204
>  %208 = fmul float %205, %205
>  %209 = fadd float %208, %207
>  %210 = fmul float %206, %206
>  %211 = fadd float %209, %210
>  %212 = call float @fabs(float %211)
>  %213 = call float @llvm.AMDGPU.rsq(float %212)
>  %214 = fmul float %204, %213
>  %215 = fmul float %205, %213
>  %216 = fmul float %206, %213
>  %217 = fdiv float 1.000000e+00, %213
>  %218 = fmul float %213, %217
>  %219 = fmul float %217, %217
>  %220 = fmul float %59, %218
>  %221 = fmul float %60, %217
>  %222 = fadd float %221, %220
>  %223 = fmul float %61, %219
>  %224 = fadd float %222, %223
>  %225 = fdiv float 1.000000e+00, %224
>  %226 = fmul float %199, %199
>  %227 = fmul float %201, %201
>  %228 = fadd float %227, %226
>  %229 = fmul float %203, %203
>  %230 = fadd float %228, %229
>  %231 = call float @fabs(float %230)
>  %232 = call float @llvm.AMDGPU.rsq(float %231)
>  %233 = fmul float %199, %232
>  %234 = fmul float %201, %232
>  %235 = fmul float %203, %232
>  %236 = fsub float %214, %233
>  %237 = fsub float %215, %234
>  %238 = fsub float %216, %235
>  %239 = fmul float %236, %236
>  %240 = fmul float %237, %237
>  %241 = fadd float %240, %239
>  %242 = fmul float %238, %238
>  %243 = fadd float %241, %242
>  %244 = call float @fabs(float %243)
>  %245 = call float @llvm.AMDGPU.rsq(float %244)
>  %246 = fmul float %236, %245
>  %247 = fmul float %237, %245
>  %248 = fmul float %238, %245
>  %249 = fmul float %170, %214
>  %250 = fmul float %171, %215
>  %251 = fadd float %250, %249
>  %252 = fmul float %172, %216
>  %253 = fadd float %251, %252
>  %254 = fmul float %170, %246
>  %255 = fmul float %171, %247
>  %256 = fadd float %255, %254
>  %257 = fmul float %172, %248
>  %258 = fadd float %256, %257
>  %259 = fcmp uge float %253, 0.000000e+00
>  %260 = select i1 %259, float %253, float 0.000000e+00
>  %261 = fcmp uge float %258, 0.000000e+00
>  %262 = select i1 %261, float %258, float 0.000000e+00
>  %263 = call float @llvm.pow.f32(float %262, float %36)
>  %264 = call float @llvm.AMDGPU.cndlt(float %253, float 0.000000e+00, float %263)
>  %265 = fmul float 1.000000e+00, %225
>  %266 = fmul float %260, %225
>  %267 = fmul float %264, %225
>  %268 = fmul float %265, %62
>  %269 = fadd float %268, %174
>  %270 = fmul float %265, %63
>  %271 = fadd float %270, %176
>  %272 = fmul float %265, %64
>  %273 = fadd float %272, %178
>  %274 = fmul float %266, %65
>  %275 = fadd float %274, %269
>  %276 = fmul float %266, %66
>  %277 = fadd float %276, %271
>  %278 = fmul float %266, %67
>  %279 = fadd float %278, %273
>  %280 = fmul float %267, %68
>  %281 = fadd float %280, %275
>  %282 = fmul float %267, %69
>  %283 = fadd float %282, %277
>  %284 = fmul float %267, %70
>  %285 = fadd float %284, %279
>  %286 = call float @llvm.AMDIL.clamp.(float %281, float 0.000000e+00, float 1.000000e+00)
>  %287 = call float @llvm.AMDIL.clamp.(float %283, float 0.000000e+00, float 1.000000e+00)
>  %288 = call float @llvm.AMDIL.clamp.(float %285, float 0.000000e+00, float 1.000000e+00)
>  %289 = fmul float %116, %71
>  %290 = fmul float %116, %72
>  %291 = fmul float %116, %73
>  %292 = fmul float %116, %74
>  %293 = fmul float %117, %75
>  %294 = fadd float %293, %289
>  %295 = fmul float %117, %76
>  %296 = fadd float %295, %290
>  %297 = fmul float %117, %77
>  %298 = fadd float %297, %291
>  %299 = fmul float %117, %78
>  %300 = fadd float %299, %292
>  %301 = fmul float %118, %79
>  %302 = fadd float %301, %294
>  %303 = fmul float %118, %80
>  %304 = fadd float %303, %296
>  %305 = fmul float %118, %81
>  %306 = fadd float %305, %298
>  %307 = fmul float %118, %82
>  %308 = fadd float %307, %300
>  %309 = fmul float %119, %83
>  %310 = fadd float %309, %302
>  %311 = fmul float %119, %84
>  %312 = fadd float %311, %304
>  %313 = fmul float %119, %85
>  %314 = fadd float %313, %306
>  %315 = fmul float %119, %86
>  %316 = fadd float %315, %308
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %286, float %287, float %288, float %182)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %109, float %110, float %111, float %112)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %310, float %312, float %314, float %316)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %141, float %143, float %145, float %147)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820005
>04140904
>c2020130
>bf8c007f
>100c0204
>c2020134
>bf8c007f
>d2820006
>04180902
>c2020138
>bf8c007f
>d2820006
>04180903
>c202013c
>bf8c007f
>d2820007
>04180904
>100c0f07
>d2820006
>041a0b05
>c2020132
>bf8c007f
>10100204
>c2020136
>bf8c007f
>d2820008
>04200902
>c202013a
>bf8c007f
>d2820008
>04200903
>c202013e
>bf8c007f
>d2820008
>04200904
>d2820006
>041a1108
>d2060106
>02010106
>7e125b06
>10141305
>c202012d
>bf8c007f
>080c0a04
>c202012c
>bf8c007f
>081a0e04
>100a1b0d
>d2820005
>04160d06
>c202012e
>bf8c007f
>08161004
>d2820005
>0416170b
>d2060105
>02010105
>7e0a5b05
>100c0b06
>08181506
>10141307
>100e0b0d
>081a1507
>10141b0d
>d282000a
>042a190c
>10121308
>10100b0b
>08121308
>d282000a
>042a1309
>d206010a
>0201010a
>7e145b0a
>1016150c
>1018150d
>c0840704
>bf8c007f
>e00c2000
>80020d00
>c2020114
>bf8c0070
>10221a04
>c2020115
>bf8c007f
>d2820011
>0444090e
>c2020116
>bf8c007f
>d2820011
>0444090f
>c2020110
>bf8c007f
>10241a04
>c2020111
>bf8c007f
>d2820012
>0448090e
>c2020112
>bf8c007f
>d2820012
>0448090f
>10262512
>d2820013
>044e2311
>c2020118
>bf8c007f
>10281a04
>c2020119
>bf8c007f
>d2820014
>0450090e
>c202011a
>bf8c007f
>d282000e
>0450090f
>d282000d
>044e1d0e
>d206010d
>0201010d
>7e1e5b0d
>101a1f12
>1020190d
>10181f11
>d282000b
>0442170c
>10141509
>10121f0e
>d282000a
>042e1509
>d00c0004
>0201010a
>d200000a
>00121480
>7e144f0a
>c202011c
>bf8c007f
>0e141404
>7e144b0a
>100e0f0d
>d2820006
>041e0d0c
>d2820007
>041a1109
>d0080004
>02020e80
>d2000008
>0011010a
>7e0c5505
>100a0d05
>c2020140
>bf8c007f
>100a0a04
>c2020141
>bf8c007f
>d2820005
>04160c04
>100c0d06
>c2020142
>bf8c007f
>d2820005
>04160c04
>7e0c5505
>100a0d08
>d00c0004
>02010107
>d2000007
>00120e80
>100e0d07
>c0840708
>bf8c007f
>e00c2000
>80020800
>c2020122
>c2028126
>bf8c0070
>7e180205
>d282000c
>042a1804
>c2020146
>bf8c007f
>d282000c
>04300906
>c202014a
>bf8c007f
>d282000c
>04300907
>c202014e
>bf8c007f
>d282000c
>04300905
>d206080c
>0201010c
>c2020121
>c2028125
>bf8c007f
>7e1a0205
>d282000d
>04261a04
>c2020145
>bf8c007f
>d282000d
>04340906
>c2020149
>bf8c007f
>d282000d
>04340907
>c202014d
>bf8c007f
>d282000d
>04340905
>d206080d
>0201010d
>c2020120
>c2028124
>bf8c007f
>7e1c0205
>d2820008
>04221c04
>c2020144
>bf8c007f
>d2820006
>04200906
>c2020148
>bf8c007f
>d2820006
>04180907
>c202014c
>bf8c007f
>d2820005
>04180905
>d2060805
>02010105
>c202012b
>bf8c007f
>d2060806
>02010004
>f800020f
>060c0d05
>c084070c
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800021f
>08070605
>c0820710
>bf8c000f
>e00c2000
>80010500
>c2020153
>bf8c0070
>10000a04
>c2020157
>bf8c007f
>d2820000
>04000906
>c202015b
>bf8c007f
>d2820000
>04000907
>c202015f
>bf8c007f
>d2820000
>04000908
>c2020152
>bf8c007f
>10120a04
>c2020156
>bf8c007f
>d2820009
>04240906
>c202015a
>bf8c007f
>d2820009
>04240907
>c202015e
>bf8c007f
>d2820009
>04240908
>c2020151
>bf8c007f
>10140a04
>c2020155
>bf8c007f
>d282000a
>04280906
>c2020159
>bf8c007f
>d282000a
>04280907
>c202015d
>bf8c007f
>d282000a
>04280908
>c2020150
>bf8c007f
>10160a04
>c2020154
>bf8c007f
>d282000b
>042c0906
>c2020158
>bf8c007f
>d282000b
>042c0907
>c202015c
>bf8c007f
>d2820005
>042c0908
>f800022f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: MOV OUT[3], IN[3]
>  7: MOV OUT[4], IN[4]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %5)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = extractelement <4 x float> %50, i32 3
>  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
>  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
>  %58 = extractelement <4 x float> %57, i32 0
>  %59 = extractelement <4 x float> %57, i32 1
>  %60 = extractelement <4 x float> %57, i32 2
>  %61 = extractelement <4 x float> %57, i32 3
>  %62 = fmul float %30, %11
>  %63 = fmul float %30, %12
>  %64 = fmul float %30, %13
>  %65 = fmul float %30, %14
>  %66 = fmul float %31, %15
>  %67 = fadd float %66, %62
>  %68 = fmul float %31, %16
>  %69 = fadd float %68, %63
>  %70 = fmul float %31, %17
>  %71 = fadd float %70, %64
>  %72 = fmul float %31, %18
>  %73 = fadd float %72, %65
>  %74 = fmul float %32, %19
>  %75 = fadd float %74, %67
>  %76 = fmul float %32, %20
>  %77 = fadd float %76, %69
>  %78 = fmul float %32, %21
>  %79 = fadd float %78, %71
>  %80 = fmul float %32, %22
>  %81 = fadd float %80, %73
>  %82 = fmul float %33, %23
>  %83 = fadd float %82, %75
>  %84 = fmul float %33, %24
>  %85 = fadd float %84, %77
>  %86 = fmul float %33, %25
>  %87 = fadd float %86, %79
>  %88 = fmul float %33, %26
>  %89 = fadd float %88, %81
>  %90 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %91 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %92 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %93 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %90, float %91, float %92, float %93)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %51, float %52, float %53, float %54)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %58, float %59, float %60, float %61)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %83, float %85, float %87, float %89)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800022f
>04030201
>c0840710
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800023f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..10]
>DCL TEMP[0..3]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[2]
>  5: MOV OUT[2], IN[3]
>  6: DP3 TEMP[0].x, IN[1], CONST[4]
>  7: DP3 TEMP[0].y, IN[1], CONST[5]
>  8: DP3 TEMP[0].z, IN[1], CONST[6]
>  9: DP3 TEMP[1].x, TEMP[0], TEMP[0]
> 10: RSQ TEMP[1].x, |TEMP[1]|
> 11: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 12: MUL TEMP[1], IN[0].xxxx, CONST[7]
> 13: MAD TEMP[1], IN[0].yyyy, CONST[8], TEMP[1]
> 14: MAD TEMP[1], IN[0].zzzz, CONST[9], TEMP[1]
> 15: MAD TEMP[1], IN[0].wwww, CONST[10], TEMP[1]
> 16: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 17: RSQ TEMP[2].x, |TEMP[2]|
> 18: MUL TEMP[3], TEMP[1], TEMP[2].xxxx
> 19: DP3 TEMP[2], TEMP[0], TEMP[3]
> 20: ADD TEMP[2], TEMP[2], TEMP[2]
> 21: MAD OUT[3].xyz, -TEMP[2], TEMP[0], TEMP[3]
> 22: MOV OUT[3].w, IN[4]
> 23: MOV OUT[4], IN[5]
> 24: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %48 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %5)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = extractelement <4 x float> %50, i32 3
>  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
>  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
>  %58 = extractelement <4 x float> %57, i32 0
>  %59 = extractelement <4 x float> %57, i32 1
>  %60 = extractelement <4 x float> %57, i32 2
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 0
>  %65 = extractelement <4 x float> %63, i32 1
>  %66 = extractelement <4 x float> %63, i32 2
>  %67 = extractelement <4 x float> %63, i32 3
>  %68 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
>  %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %69, i32 0, i32 %5)
>  %71 = extractelement <4 x float> %70, i32 0
>  %72 = extractelement <4 x float> %70, i32 1
>  %73 = extractelement <4 x float> %70, i32 2
>  %74 = extractelement <4 x float> %70, i32 3
>  %75 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0
>  %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %76, i32 0, i32 %5)
>  %78 = extractelement <4 x float> %77, i32 3
>  %79 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %80 = load <16 x i8> addrspace(2)* %79, !tbaa !0
>  %81 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %80, i32 0, i32 %5)
>  %82 = extractelement <4 x float> %81, i32 0
>  %83 = extractelement <4 x float> %81, i32 1
>  %84 = extractelement <4 x float> %81, i32 2
>  %85 = extractelement <4 x float> %81, i32 3
>  %86 = fmul float %51, %11
>  %87 = fmul float %51, %12
>  %88 = fmul float %51, %13
>  %89 = fmul float %51, %14
>  %90 = fmul float %52, %15
>  %91 = fadd float %90, %86
>  %92 = fmul float %52, %16
>  %93 = fadd float %92, %87
>  %94 = fmul float %52, %17
>  %95 = fadd float %94, %88
>  %96 = fmul float %52, %18
>  %97 = fadd float %96, %89
>  %98 = fmul float %53, %19
>  %99 = fadd float %98, %91
>  %100 = fmul float %53, %20
>  %101 = fadd float %100, %93
>  %102 = fmul float %53, %21
>  %103 = fadd float %102, %95
>  %104 = fmul float %53, %22
>  %105 = fadd float %104, %97
>  %106 = fmul float %54, %23
>  %107 = fadd float %106, %99
>  %108 = fmul float %54, %24
>  %109 = fadd float %108, %101
>  %110 = fmul float %54, %25
>  %111 = fadd float %110, %103
>  %112 = fmul float %54, %26
>  %113 = fadd float %112, %105
>  %114 = call float @llvm.AMDIL.clamp.(float %64, float 0.000000e+00, float 1.000000e+00)
>  %115 = call float @llvm.AMDIL.clamp.(float %65, float 0.000000e+00, float 1.000000e+00)
>  %116 = call float @llvm.AMDIL.clamp.(float %66, float 0.000000e+00, float 1.000000e+00)
>  %117 = call float @llvm.AMDIL.clamp.(float %67, float 0.000000e+00, float 1.000000e+00)
>  %118 = fmul float %58, %27
>  %119 = fmul float %59, %28
>  %120 = fadd float %119, %118
>  %121 = fmul float %60, %29
>  %122 = fadd float %120, %121
>  %123 = fmul float %58, %30
>  %124 = fmul float %59, %31
>  %125 = fadd float %124, %123
>  %126 = fmul float %60, %32
>  %127 = fadd float %125, %126
>  %128 = fmul float %58, %33
>  %129 = fmul float %59, %34
>  %130 = fadd float %129, %128
>  %131 = fmul float %60, %35
>  %132 = fadd float %130, %131
>  %133 = fmul float %122, %122
>  %134 = fmul float %127, %127
>  %135 = fadd float %134, %133
>  %136 = fmul float %132, %132
>  %137 = fadd float %135, %136
>  %138 = call float @fabs(float %137)
>  %139 = call float @llvm.AMDGPU.rsq(float %138)
>  %140 = fmul float %122, %139
>  %141 = fmul float %127, %139
>  %142 = fmul float %132, %139
>  %143 = fmul float %51, %36
>  %144 = fmul float %51, %37
>  %145 = fmul float %51, %38
>  %146 = fmul float %52, %39
>  %147 = fadd float %146, %143
>  %148 = fmul float %52, %40
>  %149 = fadd float %148, %144
>  %150 = fmul float %52, %41
>  %151 = fadd float %150, %145
>  %152 = fmul float %53, %42
>  %153 = fadd float %152, %147
>  %154 = fmul float %53, %43
>  %155 = fadd float %154, %149
>  %156 = fmul float %53, %44
>  %157 = fadd float %156, %151
>  %158 = fmul float %54, %45
>  %159 = fadd float %158, %153
>  %160 = fmul float %54, %46
>  %161 = fadd float %160, %155
>  %162 = fmul float %54, %47
>  %163 = fadd float %162, %157
>  %164 = fmul float %159, %159
>  %165 = fmul float %161, %161
>  %166 = fadd float %165, %164
>  %167 = fmul float %163, %163
>  %168 = fadd float %166, %167
>  %169 = call float @fabs(float %168)
>  %170 = call float @llvm.AMDGPU.rsq(float %169)
>  %171 = fmul float %159, %170
>  %172 = fmul float %161, %170
>  %173 = fmul float %163, %170
>  %174 = fmul float %140, %171
>  %175 = fmul float %141, %172
>  %176 = fadd float %175, %174
>  %177 = fmul float %142, %173
>  %178 = fadd float %176, %177
>  %179 = fadd float %178, %178
>  %180 = fadd float %178, %178
>  %181 = fadd float %178, %178
>  %182 = fsub float -0.000000e+00, %179
>  %183 = fmul float %182, %140
>  %184 = fadd float %183, %171
>  %185 = fsub float -0.000000e+00, %180
>  %186 = fmul float %185, %141
>  %187 = fadd float %186, %172
>  %188 = fsub float -0.000000e+00, %181
>  %189 = fmul float %188, %142
>  %190 = fadd float %189, %173
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %114, float %115, float %116, float %117)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %71, float %72, float %73, float %74)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %184, float %187, float %190, float %78)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %82, float %83, float %84, float %85)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %107, float %109, float %111, float %113)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0840704
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020114
>bf8c007f
>100a0204
>c2020115
>bf8c007f
>d2820005
>04140902
>c2020116
>bf8c007f
>d2820005
>04140903
>c2020110
>bf8c007f
>100c0204
>c2020111
>bf8c007f
>d2820006
>04180902
>c2020112
>bf8c007f
>d2820006
>04180903
>100e0d06
>d2820008
>041e0b05
>c2020118
>bf8c007f
>100e0204
>c2020119
>bf8c007f
>d2820007
>041c0902
>c202011a
>bf8c007f
>d2820007
>041c0903
>d2820001
>04220f07
>d2060101
>02010101
>7e105b01
>100c1106
>c0840700
>bf8c007f
>e00c2000
>80020100
>c202011d
>bf8c0070
>10120204
>c2020121
>bf8c007f
>d2820009
>04240902
>c2020125
>bf8c007f
>d2820009
>04240903
>c2020129
>bf8c007f
>d2820009
>04240904
>c202011c
>bf8c007f
>10140204
>c2020120
>bf8c007f
>d282000a
>04280902
>c2020124
>bf8c007f
>d282000a
>04280903
>c2020128
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c202011e
>bf8c007f
>10160204
>c2020122
>bf8c007f
>d282000b
>042c0902
>c2020126
>bf8c007f
>d282000b
>042c0903
>c202012a
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101a1506
>100a1105
>10121909
>d282000d
>04361305
>100e1107
>1016190b
>d2820008
>04361707
>06101108
>100e0f08
>080e0f0b
>100a0b08
>080a0b09
>100c0d08
>080c0d0a
>c0840710
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800022f
>0b070506
>c0820714
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: MUL TEMP[0], IN[3].xxxx, CONST[4]
>  7: MAD TEMP[0], IN[3].yyyy, CONST[5], TEMP[0]
>  8: MAD TEMP[0], IN[3].zzzz, CONST[6], TEMP[0]
>  9: MAD OUT[3], IN[3].wwww, CONST[7], TEMP[0]
> 10: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = extractelement <4 x float> %59, i32 3
>  %64 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
>  %66 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %65, i32 0, i32 %5)
>  %67 = extractelement <4 x float> %66, i32 0
>  %68 = extractelement <4 x float> %66, i32 1
>  %69 = extractelement <4 x float> %66, i32 2
>  %70 = extractelement <4 x float> %66, i32 3
>  %71 = fmul float %46, %11
>  %72 = fmul float %46, %12
>  %73 = fmul float %46, %13
>  %74 = fmul float %46, %14
>  %75 = fmul float %47, %15
>  %76 = fadd float %75, %71
>  %77 = fmul float %47, %16
>  %78 = fadd float %77, %72
>  %79 = fmul float %47, %17
>  %80 = fadd float %79, %73
>  %81 = fmul float %47, %18
>  %82 = fadd float %81, %74
>  %83 = fmul float %48, %19
>  %84 = fadd float %83, %76
>  %85 = fmul float %48, %20
>  %86 = fadd float %85, %78
>  %87 = fmul float %48, %21
>  %88 = fadd float %87, %80
>  %89 = fmul float %48, %22
>  %90 = fadd float %89, %82
>  %91 = fmul float %49, %23
>  %92 = fadd float %91, %84
>  %93 = fmul float %49, %24
>  %94 = fadd float %93, %86
>  %95 = fmul float %49, %25
>  %96 = fadd float %95, %88
>  %97 = fmul float %49, %26
>  %98 = fadd float %97, %90
>  %99 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
>  %100 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %101 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %102 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
>  %103 = fmul float %67, %27
>  %104 = fmul float %67, %28
>  %105 = fmul float %67, %29
>  %106 = fmul float %67, %30
>  %107 = fmul float %68, %31
>  %108 = fadd float %107, %103
>  %109 = fmul float %68, %32
>  %110 = fadd float %109, %104
>  %111 = fmul float %68, %33
>  %112 = fadd float %111, %105
>  %113 = fmul float %68, %34
>  %114 = fadd float %113, %106
>  %115 = fmul float %69, %35
>  %116 = fadd float %115, %108
>  %117 = fmul float %69, %36
>  %118 = fadd float %117, %110
>  %119 = fmul float %69, %37
>  %120 = fadd float %119, %112
>  %121 = fmul float %69, %38
>  %122 = fadd float %121, %114
>  %123 = fmul float %70, %39
>  %124 = fadd float %123, %116
>  %125 = fmul float %70, %40
>  %126 = fadd float %125, %118
>  %127 = fmul float %70, %41
>  %128 = fadd float %127, %120
>  %129 = fmul float %70, %42
>  %130 = fadd float %129, %122
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %99, float %100, float %101, float %102)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %60, float %61, float %62, float %63)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %124, float %126, float %128, float %130)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %92, float %94, float %96, float %98)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c084070c
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800022f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL IN[6]
>DCL IN[7]
>DCL IN[8]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL OUT[5], GENERIC[3]
>DCL OUT[6], GENERIC[4]
>DCL OUT[7], GENERIC[6]
>DCL CONST[0..26]
>DCL TEMP[0..4]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[2]
>  5: DP3 TEMP[0].x, IN[1], CONST[4]
>  6: DP3 TEMP[0].y, IN[1], CONST[5]
>  7: DP3 TEMP[0].z, IN[1], CONST[6]
>  8: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  9: RSQ TEMP[1].x, |TEMP[1]|
> 10: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 11: MUL TEMP[1], IN[0].xxxx, CONST[7]
> 12: MAD TEMP[1], IN[0].yyyy, CONST[8], TEMP[1]
> 13: MAD TEMP[1], IN[0].zzzz, CONST[9], TEMP[1]
> 14: MAD TEMP[1], IN[0].wwww, CONST[10], TEMP[1]
> 15: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 16: RSQ TEMP[2].x, |TEMP[2]|
> 17: MUL TEMP[3], TEMP[1], TEMP[2].xxxx
> 18: DP3 TEMP[2], TEMP[0], TEMP[3]
> 19: ADD TEMP[2], TEMP[2], TEMP[2]
> 20: MAD OUT[2].xyz, -TEMP[2], TEMP[0], TEMP[3]
> 21: MOV OUT[2].w, IN[3]
> 22: MUL TEMP[2], IN[4].xxxx, CONST[11]
> 23: MAD TEMP[2], IN[4].yyyy, CONST[12], TEMP[2]
> 24: MAD TEMP[2], IN[4].zzzz, CONST[13], TEMP[2]
> 25: MAD OUT[3], IN[4].wwww, CONST[14], TEMP[2]
> 26: MOV OUT[4], IN[5]
> 27: MUL TEMP[2], IN[6].xxxx, CONST[15]
> 28: MAD TEMP[2], IN[6].yyyy, CONST[16], TEMP[2]
> 29: MAD TEMP[2], IN[6].zzzz, CONST[17], TEMP[2]
> 30: MAD OUT[5], IN[6].wwww, CONST[18], TEMP[2]
> 31: DP3 TEMP[4], TEMP[0], TEMP[3]
> 32: ADD TEMP[4], TEMP[4], TEMP[4]
> 33: MAD TEMP[2].xyz, -TEMP[4], TEMP[0], TEMP[3]
> 34: MOV TEMP[2].w, IN[7]
> 35: MUL TEMP[4], TEMP[2].xxxx, CONST[19]
> 36: MAD TEMP[4], TEMP[2].yyyy, CONST[20], TEMP[4]
> 37: MAD TEMP[4], TEMP[2].zzzz, CONST[21], TEMP[4]
> 38: MAD OUT[6], TEMP[2].wwww, CONST[22], TEMP[4]
> 39: MUL TEMP[2], IN[8].xxxx, CONST[23]
> 40: MAD TEMP[2], IN[8].yyyy, CONST[24], TEMP[2]
> 41: MAD TEMP[2], IN[8].zzzz, CONST[25], TEMP[2]
> 42: MAD OUT[7], IN[8].wwww, CONST[26], TEMP[2]
> 43: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 252)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 268)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 284)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 300)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
>  %112 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %113 = load <16 x i8> addrspace(2)* %112, !tbaa !0
>  %114 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %113, i32 0, i32 %5)
>  %115 = extractelement <4 x float> %114, i32 0
>  %116 = extractelement <4 x float> %114, i32 1
>  %117 = extractelement <4 x float> %114, i32 2
>  %118 = extractelement <4 x float> %114, i32 3
>  %119 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %120 = load <16 x i8> addrspace(2)* %119, !tbaa !0
>  %121 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %120, i32 0, i32 %5)
>  %122 = extractelement <4 x float> %121, i32 0
>  %123 = extractelement <4 x float> %121, i32 1
>  %124 = extractelement <4 x float> %121, i32 2
>  %125 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %126 = load <16 x i8> addrspace(2)* %125, !tbaa !0
>  %127 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %126, i32 0, i32 %5)
>  %128 = extractelement <4 x float> %127, i32 0
>  %129 = extractelement <4 x float> %127, i32 1
>  %130 = extractelement <4 x float> %127, i32 2
>  %131 = extractelement <4 x float> %127, i32 3
>  %132 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %133 = load <16 x i8> addrspace(2)* %132, !tbaa !0
>  %134 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %133, i32 0, i32 %5)
>  %135 = extractelement <4 x float> %134, i32 3
>  %136 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %137 = load <16 x i8> addrspace(2)* %136, !tbaa !0
>  %138 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %137, i32 0, i32 %5)
>  %139 = extractelement <4 x float> %138, i32 0
>  %140 = extractelement <4 x float> %138, i32 1
>  %141 = extractelement <4 x float> %138, i32 2
>  %142 = extractelement <4 x float> %138, i32 3
>  %143 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %144 = load <16 x i8> addrspace(2)* %143, !tbaa !0
>  %145 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %144, i32 0, i32 %5)
>  %146 = extractelement <4 x float> %145, i32 0
>  %147 = extractelement <4 x float> %145, i32 1
>  %148 = extractelement <4 x float> %145, i32 2
>  %149 = extractelement <4 x float> %145, i32 3
>  %150 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
>  %151 = load <16 x i8> addrspace(2)* %150, !tbaa !0
>  %152 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %151, i32 0, i32 %5)
>  %153 = extractelement <4 x float> %152, i32 0
>  %154 = extractelement <4 x float> %152, i32 1
>  %155 = extractelement <4 x float> %152, i32 2
>  %156 = extractelement <4 x float> %152, i32 3
>  %157 = getelementptr <16 x i8> addrspace(2)* %3, i32 7
>  %158 = load <16 x i8> addrspace(2)* %157, !tbaa !0
>  %159 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %158, i32 0, i32 %5)
>  %160 = extractelement <4 x float> %159, i32 3
>  %161 = getelementptr <16 x i8> addrspace(2)* %3, i32 8
>  %162 = load <16 x i8> addrspace(2)* %161, !tbaa !0
>  %163 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %162, i32 0, i32 %5)
>  %164 = extractelement <4 x float> %163, i32 0
>  %165 = extractelement <4 x float> %163, i32 1
>  %166 = extractelement <4 x float> %163, i32 2
>  %167 = extractelement <4 x float> %163, i32 3
>  %168 = fmul float %115, %11
>  %169 = fmul float %115, %12
>  %170 = fmul float %115, %13
>  %171 = fmul float %115, %14
>  %172 = fmul float %116, %15
>  %173 = fadd float %172, %168
>  %174 = fmul float %116, %16
>  %175 = fadd float %174, %169
>  %176 = fmul float %116, %17
>  %177 = fadd float %176, %170
>  %178 = fmul float %116, %18
>  %179 = fadd float %178, %171
>  %180 = fmul float %117, %19
>  %181 = fadd float %180, %173
>  %182 = fmul float %117, %20
>  %183 = fadd float %182, %175
>  %184 = fmul float %117, %21
>  %185 = fadd float %184, %177
>  %186 = fmul float %117, %22
>  %187 = fadd float %186, %179
>  %188 = fmul float %118, %23
>  %189 = fadd float %188, %181
>  %190 = fmul float %118, %24
>  %191 = fadd float %190, %183
>  %192 = fmul float %118, %25
>  %193 = fadd float %192, %185
>  %194 = fmul float %118, %26
>  %195 = fadd float %194, %187
>  %196 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
>  %197 = call float @llvm.AMDIL.clamp.(float %129, float 0.000000e+00, float 1.000000e+00)
>  %198 = call float @llvm.AMDIL.clamp.(float %130, float 0.000000e+00, float 1.000000e+00)
>  %199 = call float @llvm.AMDIL.clamp.(float %131, float 0.000000e+00, float 1.000000e+00)
>  %200 = fmul float %122, %27
>  %201 = fmul float %123, %28
>  %202 = fadd float %201, %200
>  %203 = fmul float %124, %29
>  %204 = fadd float %202, %203
>  %205 = fmul float %122, %30
>  %206 = fmul float %123, %31
>  %207 = fadd float %206, %205
>  %208 = fmul float %124, %32
>  %209 = fadd float %207, %208
>  %210 = fmul float %122, %33
>  %211 = fmul float %123, %34
>  %212 = fadd float %211, %210
>  %213 = fmul float %124, %35
>  %214 = fadd float %212, %213
>  %215 = fmul float %204, %204
>  %216 = fmul float %209, %209
>  %217 = fadd float %216, %215
>  %218 = fmul float %214, %214
>  %219 = fadd float %217, %218
>  %220 = call float @fabs(float %219)
>  %221 = call float @llvm.AMDGPU.rsq(float %220)
>  %222 = fmul float %204, %221
>  %223 = fmul float %209, %221
>  %224 = fmul float %214, %221
>  %225 = fmul float %115, %36
>  %226 = fmul float %115, %37
>  %227 = fmul float %115, %38
>  %228 = fmul float %116, %39
>  %229 = fadd float %228, %225
>  %230 = fmul float %116, %40
>  %231 = fadd float %230, %226
>  %232 = fmul float %116, %41
>  %233 = fadd float %232, %227
>  %234 = fmul float %117, %42
>  %235 = fadd float %234, %229
>  %236 = fmul float %117, %43
>  %237 = fadd float %236, %231
>  %238 = fmul float %117, %44
>  %239 = fadd float %238, %233
>  %240 = fmul float %118, %45
>  %241 = fadd float %240, %235
>  %242 = fmul float %118, %46
>  %243 = fadd float %242, %237
>  %244 = fmul float %118, %47
>  %245 = fadd float %244, %239
>  %246 = fmul float %241, %241
>  %247 = fmul float %243, %243
>  %248 = fadd float %247, %246
>  %249 = fmul float %245, %245
>  %250 = fadd float %248, %249
>  %251 = call float @fabs(float %250)
>  %252 = call float @llvm.AMDGPU.rsq(float %251)
>  %253 = fmul float %241, %252
>  %254 = fmul float %243, %252
>  %255 = fmul float %245, %252
>  %256 = fmul float %222, %253
>  %257 = fmul float %223, %254
>  %258 = fadd float %257, %256
>  %259 = fmul float %224, %255
>  %260 = fadd float %258, %259
>  %261 = fadd float %260, %260
>  %262 = fadd float %260, %260
>  %263 = fadd float %260, %260
>  %264 = fsub float -0.000000e+00, %261
>  %265 = fmul float %264, %222
>  %266 = fadd float %265, %253
>  %267 = fsub float -0.000000e+00, %262
>  %268 = fmul float %267, %223
>  %269 = fadd float %268, %254
>  %270 = fsub float -0.000000e+00, %263
>  %271 = fmul float %270, %224
>  %272 = fadd float %271, %255
>  %273 = fmul float %139, %48
>  %274 = fmul float %139, %49
>  %275 = fmul float %139, %50
>  %276 = fmul float %139, %51
>  %277 = fmul float %140, %52
>  %278 = fadd float %277, %273
>  %279 = fmul float %140, %53
>  %280 = fadd float %279, %274
>  %281 = fmul float %140, %54
>  %282 = fadd float %281, %275
>  %283 = fmul float %140, %55
>  %284 = fadd float %283, %276
>  %285 = fmul float %141, %56
>  %286 = fadd float %285, %278
>  %287 = fmul float %141, %57
>  %288 = fadd float %287, %280
>  %289 = fmul float %141, %58
>  %290 = fadd float %289, %282
>  %291 = fmul float %141, %59
>  %292 = fadd float %291, %284
>  %293 = fmul float %142, %60
>  %294 = fadd float %293, %286
>  %295 = fmul float %142, %61
>  %296 = fadd float %295, %288
>  %297 = fmul float %142, %62
>  %298 = fadd float %297, %290
>  %299 = fmul float %142, %63
>  %300 = fadd float %299, %292
>  %301 = fmul float %153, %64
>  %302 = fmul float %153, %65
>  %303 = fmul float %153, %66
>  %304 = fmul float %153, %67
>  %305 = fmul float %154, %68
>  %306 = fadd float %305, %301
>  %307 = fmul float %154, %69
>  %308 = fadd float %307, %302
>  %309 = fmul float %154, %70
>  %310 = fadd float %309, %303
>  %311 = fmul float %154, %71
>  %312 = fadd float %311, %304
>  %313 = fmul float %155, %72
>  %314 = fadd float %313, %306
>  %315 = fmul float %155, %73
>  %316 = fadd float %315, %308
>  %317 = fmul float %155, %74
>  %318 = fadd float %317, %310
>  %319 = fmul float %155, %75
>  %320 = fadd float %319, %312
>  %321 = fmul float %156, %76
>  %322 = fadd float %321, %314
>  %323 = fmul float %156, %77
>  %324 = fadd float %323, %316
>  %325 = fmul float %156, %78
>  %326 = fadd float %325, %318
>  %327 = fmul float %156, %79
>  %328 = fadd float %327, %320
>  %329 = fmul float %222, %253
>  %330 = fmul float %223, %254
>  %331 = fadd float %330, %329
>  %332 = fmul float %224, %255
>  %333 = fadd float %331, %332
>  %334 = fadd float %333, %333
>  %335 = fadd float %333, %333
>  %336 = fadd float %333, %333
>  %337 = fsub float -0.000000e+00, %334
>  %338 = fmul float %337, %222
>  %339 = fadd float %338, %253
>  %340 = fsub float -0.000000e+00, %335
>  %341 = fmul float %340, %223
>  %342 = fadd float %341, %254
>  %343 = fsub float -0.000000e+00, %336
>  %344 = fmul float %343, %224
>  %345 = fadd float %344, %255
>  %346 = fmul float %339, %80
>  %347 = fmul float %339, %81
>  %348 = fmul float %339, %82
>  %349 = fmul float %339, %83
>  %350 = fmul float %342, %84
>  %351 = fadd float %350, %346
>  %352 = fmul float %342, %85
>  %353 = fadd float %352, %347
>  %354 = fmul float %342, %86
>  %355 = fadd float %354, %348
>  %356 = fmul float %342, %87
>  %357 = fadd float %356, %349
>  %358 = fmul float %345, %88
>  %359 = fadd float %358, %351
>  %360 = fmul float %345, %89
>  %361 = fadd float %360, %353
>  %362 = fmul float %345, %90
>  %363 = fadd float %362, %355
>  %364 = fmul float %345, %91
>  %365 = fadd float %364, %357
>  %366 = fmul float %160, %92
>  %367 = fadd float %366, %359
>  %368 = fmul float %160, %93
>  %369 = fadd float %368, %361
>  %370 = fmul float %160, %94
>  %371 = fadd float %370, %363
>  %372 = fmul float %160, %95
>  %373 = fadd float %372, %365
>  %374 = fmul float %164, %96
>  %375 = fmul float %164, %97
>  %376 = fmul float %164, %98
>  %377 = fmul float %164, %99
>  %378 = fmul float %165, %100
>  %379 = fadd float %378, %374
>  %380 = fmul float %165, %101
>  %381 = fadd float %380, %375
>  %382 = fmul float %165, %102
>  %383 = fadd float %382, %376
>  %384 = fmul float %165, %103
>  %385 = fadd float %384, %377
>  %386 = fmul float %166, %104
>  %387 = fadd float %386, %379
>  %388 = fmul float %166, %105
>  %389 = fadd float %388, %381
>  %390 = fmul float %166, %106
>  %391 = fadd float %390, %383
>  %392 = fmul float %166, %107
>  %393 = fadd float %392, %385
>  %394 = fmul float %167, %108
>  %395 = fadd float %394, %387
>  %396 = fmul float %167, %109
>  %397 = fadd float %396, %389
>  %398 = fmul float %167, %110
>  %399 = fadd float %398, %391
>  %400 = fmul float %167, %111
>  %401 = fadd float %400, %393
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %196, float %197, float %198, float %199)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %266, float %269, float %272, float %135)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %294, float %296, float %298, float %300)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %146, float %147, float %148, float %149)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %322, float %324, float %326, float %328)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %367, float %369, float %371, float %373)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %395, float %397, float %399, float %401)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %189, float %191, float %193, float %195)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840704
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020114
>bf8c007f
>100a0204
>c2020115
>bf8c007f
>d2820005
>04140902
>c2020116
>bf8c007f
>d2820005
>04140903
>c2020110
>bf8c007f
>100c0204
>c2020111
>bf8c007f
>d2820006
>04180902
>c2020112
>bf8c007f
>d2820007
>04180903
>100c0f07
>d2820008
>041a0b05
>c2020118
>bf8c007f
>100c0204
>c2020119
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>d2820001
>04220d06
>d2060101
>02010101
>7e105b01
>100e1107
>c0840700
>bf8c007f
>e00c2000
>80020100
>c202011d
>bf8c0070
>10120204
>c2020121
>bf8c007f
>d2820009
>04240902
>c2020125
>bf8c007f
>d2820009
>04240903
>c2020129
>bf8c007f
>d2820009
>04240904
>c202011c
>bf8c007f
>10140204
>c2020120
>bf8c007f
>d282000a
>04280902
>c2020124
>bf8c007f
>d282000a
>04280903
>c2020128
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c202011e
>bf8c007f
>10160204
>c2020122
>bf8c007f
>d282000b
>042c0902
>c2020126
>bf8c007f
>d282000b
>042c0903
>c202012a
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e1a5b0c
>10141b0a
>101c1507
>10181105
>10121b09
>d282000e
>043a130c
>100a1106
>100c1b0b
>d2820008
>043a0d05
>06101108
>100a0b08
>080a0b06
>100c1908
>080c0d09
>100e0f08
>080e0f0a
>c084070c
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800021f
>0b050607
>c0840710
>bf8c000f
>e00c2000
>80020800
>c202012f
>bf8c0070
>10181004
>c2020133
>bf8c007f
>d282000c
>04300909
>c2020137
>bf8c007f
>d282000c
>0430090a
>c202013b
>bf8c007f
>d282000c
>0430090b
>c202012e
>bf8c007f
>101a1004
>c2020132
>bf8c007f
>d282000d
>04340909
>c2020136
>bf8c007f
>d282000d
>0434090a
>c202013a
>bf8c007f
>d282000d
>0434090b
>c202012d
>bf8c007f
>101c1004
>c2020131
>bf8c007f
>d282000e
>04380909
>c2020135
>bf8c007f
>d282000e
>0438090a
>c2020139
>bf8c007f
>d282000e
>0438090b
>c202012c
>bf8c007f
>101e1004
>c2020130
>bf8c007f
>d282000f
>043c0909
>c2020134
>bf8c007f
>d282000f
>043c090a
>c2020138
>bf8c007f
>d2820008
>043c090b
>f800022f
>0c0d0e08
>c0840714
>bf8c000f
>e00c2000
>80020800
>bf8c0770
>f800023f
>0b0a0908
>c0840718
>bf8c000f
>e00c2000
>80020800
>c202013f
>bf8c0070
>10181004
>c2020143
>bf8c007f
>d282000c
>04300909
>c2020147
>bf8c007f
>d282000c
>0430090a
>c202014b
>bf8c007f
>d282000c
>0430090b
>c202013e
>bf8c007f
>101a1004
>c2020142
>bf8c007f
>d282000d
>04340909
>c2020146
>bf8c007f
>d282000d
>0434090a
>c202014a
>bf8c007f
>d282000d
>0434090b
>c202013d
>bf8c007f
>101c1004
>c2020141
>bf8c007f
>d282000e
>04380909
>c2020145
>bf8c007f
>d282000e
>0438090a
>c2020149
>bf8c007f
>d282000e
>0438090b
>c202013c
>bf8c007f
>101e1004
>c2020140
>bf8c007f
>d282000f
>043c0909
>c2020144
>bf8c007f
>d282000f
>043c090a
>c2020148
>bf8c007f
>d2820008
>043c090b
>f800024f
>0c0d0e08
>c202014f
>bf8c000f
>10100e04
>c2020153
>bf8c007f
>d2820008
>04200906
>c2020157
>bf8c007f
>d282000c
>04200905
>c084071c
>bf8c007f
>e00c2000
>80020800
>c202015b
>bf8c0070
>d282000c
>0430090b
>c202014e
>bf8c007f
>101a0e04
>c2020152
>bf8c007f
>d282000d
>04340906
>c2020156
>bf8c007f
>d282000d
>04340905
>c202015a
>bf8c007f
>d282000d
>0434090b
>c202014d
>bf8c007f
>101c0e04
>c2020151
>bf8c007f
>d282000e
>04380906
>c2020155
>bf8c007f
>d282000e
>04380905
>c2020159
>bf8c007f
>d282000e
>0438090b
>c202014c
>bf8c007f
>100e0e04
>c2020150
>bf8c007f
>d2820006
>041c0906
>c2020154
>bf8c007f
>d2820005
>04180905
>c2020158
>bf8c007f
>d2820005
>0414090b
>f800025f
>0c0d0e05
>c0820720
>bf8c000f
>e00c2000
>80010500
>c202015f
>bf8c0070
>10000a04
>c2020163
>bf8c007f
>d2820000
>04000906
>c2020167
>bf8c007f
>d2820000
>04000907
>c202016b
>bf8c007f
>d2820000
>04000908
>c202015e
>bf8c007f
>10120a04
>c2020162
>bf8c007f
>d2820009
>04240906
>c2020166
>bf8c007f
>d2820009
>04240907
>c202016a
>bf8c007f
>d2820009
>04240908
>c202015d
>bf8c007f
>10140a04
>c2020161
>bf8c007f
>d282000a
>04280906
>c2020165
>bf8c007f
>d282000a
>04280907
>c2020169
>bf8c007f
>d282000a
>04280908
>c202015c
>bf8c007f
>10160a04
>c2020160
>bf8c007f
>d282000b
>042c0906
>c2020164
>bf8c007f
>d282000b
>042c0907
>c2020168
>bf8c007f
>d2820005
>042c0908
>f800026f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
>  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
>  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
>  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = extractelement <4 x float> %59, i32 3
>  %64 = fmul float %46, %11
>  %65 = fmul float %46, %12
>  %66 = fmul float %46, %13
>  %67 = fmul float %46, %14
>  %68 = fmul float %47, %15
>  %69 = fadd float %68, %64
>  %70 = fmul float %47, %16
>  %71 = fadd float %70, %65
>  %72 = fmul float %47, %17
>  %73 = fadd float %72, %66
>  %74 = fmul float %47, %18
>  %75 = fadd float %74, %67
>  %76 = fmul float %48, %19
>  %77 = fadd float %76, %69
>  %78 = fmul float %48, %20
>  %79 = fadd float %78, %71
>  %80 = fmul float %48, %21
>  %81 = fadd float %80, %73
>  %82 = fmul float %48, %22
>  %83 = fadd float %82, %75
>  %84 = fmul float %49, %23
>  %85 = fadd float %84, %77
>  %86 = fmul float %49, %24
>  %87 = fadd float %86, %79
>  %88 = fmul float %49, %25
>  %89 = fadd float %88, %81
>  %90 = fmul float %49, %26
>  %91 = fadd float %90, %83
>  %92 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
>  %93 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %94 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
>  %96 = fmul float %60, %27
>  %97 = fmul float %60, %28
>  %98 = fmul float %60, %29
>  %99 = fmul float %60, %30
>  %100 = fmul float %61, %31
>  %101 = fadd float %100, %96
>  %102 = fmul float %61, %32
>  %103 = fadd float %102, %97
>  %104 = fmul float %61, %33
>  %105 = fadd float %104, %98
>  %106 = fmul float %61, %34
>  %107 = fadd float %106, %99
>  %108 = fmul float %62, %35
>  %109 = fadd float %108, %101
>  %110 = fmul float %62, %36
>  %111 = fadd float %110, %103
>  %112 = fmul float %62, %37
>  %113 = fadd float %112, %105
>  %114 = fmul float %62, %38
>  %115 = fadd float %114, %107
>  %116 = fmul float %63, %39
>  %117 = fadd float %116, %109
>  %118 = fmul float %63, %40
>  %119 = fadd float %118, %111
>  %120 = fmul float %63, %41
>  %121 = fadd float %120, %113
>  %122 = fmul float %63, %42
>  %123 = fadd float %122, %115
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %92, float %93, float %94, float %95)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %117, float %119, float %121, float %123)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %85, float %87, float %89, float %91)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800021f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MOV TEMP[1].xy, IN[2].xyyy
>  4: MOV TEMP[1].w, IN[2].wwww
>  5: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  6: MAD TEMP[1].xyz, TEMP[0], TEMP[1].wwww, TEMP[1]
>  7: MOV_SAT TEMP[1].xyz, TEMP[1].xyzz
>  8: MOV TEMP[1].w, TEMP[0].wwww
>  9: MUL TEMP[1].xyz, IN[0], TEMP[1]
> 10: MOV TEMP[1].xyz, TEMP[1].xyzx
> 11: MOV TEMP[1].w, TEMP[0].wwww
> 12: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
> 13: MOV OUT[0], TEMP[0]
> 14: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %37 = fdiv float %31, %33
>  %38 = fdiv float %32, %33
>  %39 = bitcast float %37 to i32
>  %40 = bitcast float %38 to i32
>  %41 = insertelement <2 x i32> undef, i32 %39, i32 0
>  %42 = insertelement <2 x i32> %41, i32 %40, i32 1
>  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %42, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fdiv float %34, %36
>  %49 = fdiv float %35, %36
>  %50 = bitcast float %48 to i32
>  %51 = bitcast float %49 to i32
>  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
>  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
>  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %58 = extractelement <4 x float> %54, i32 3
>  %59 = fmul float %44, %58
>  %60 = fadd float %59, %55
>  %61 = fmul float %45, %58
>  %62 = fadd float %61, %56
>  %63 = fmul float %46, %58
>  %64 = fadd float %63, %57
>  %65 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %66 = call float @llvm.AMDIL.clamp.(float %62, float 0.000000e+00, float 1.000000e+00)
>  %67 = call float @llvm.AMDIL.clamp.(float %64, float 0.000000e+00, float 1.000000e+00)
>  %68 = fmul float %28, %65
>  %69 = fmul float %29, %66
>  %70 = fmul float %30, %67
>  %71 = fmul float %68, 2.000000e+00
>  %72 = fmul float %69, 2.000000e+00
>  %73 = fmul float %70, 2.000000e+00
>  %74 = fmul float %47, 1.000000e+00
>  %75 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %76 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %73, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00)
>  %79 = call i32 @llvm.SI.packf16(float %75, float %76)
>  %80 = bitcast i32 %79 to float
>  %81 = call i32 @llvm.SI.packf16(float %77, float %78)
>  %82 = bitcast i32 %81 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %80, float %82, float %80, float %82)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c8180500
>c8190501
>c81c0700
>c81d0701
>7e105507
>100e1106
>c8240400
>c8250401
>100c1109
>c0800304
>c0c40508
>bf8c0070
>f0800f00
>00020606
>bf8c0770
>d282000a
>040e0b07
>d206080a
>0201010a
>c82c0100
>c82d0101
>1018150b
>d282000a
>0432150b
>d206080a
>0201010a
>d282000b
>040a0b06
>d206080b
>0201010b
>c8300000
>c8310001
>101a170c
>d282000b
>0436170c
>d206080b
>0201010b
>5e14150b
>d2820002
>04120b08
>d2060802
>02010102
>c80c0200
>c80d0201
>10000503
>d2820000
>04020503
>d2060800
>02010100
>d2060801
>02010109
>5e000300
>f8001c0f
>000a000a
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..14]
>DCL TEMP[0..4]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[2]
>  5: MOV OUT[2], IN[3]
>  6: DP3 TEMP[1].x, IN[1], CONST[4]
>  7: DP3 TEMP[1].y, IN[1], CONST[5]
>  8: DP3 TEMP[1].z, IN[1], CONST[6]
>  9: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 10: RSQ TEMP[2].x, |TEMP[2]|
> 11: MUL TEMP[1], TEMP[1], TEMP[2].xxxx
> 12: MUL TEMP[2], IN[0].xxxx, CONST[7]
> 13: MAD TEMP[2], IN[0].yyyy, CONST[8], TEMP[2]
> 14: MAD TEMP[2], IN[0].zzzz, CONST[9], TEMP[2]
> 15: MAD TEMP[2], IN[0].wwww, CONST[10], TEMP[2]
> 16: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 17: RSQ TEMP[3].x, |TEMP[3]|
> 18: MUL TEMP[4], TEMP[2], TEMP[3].xxxx
> 19: DP3 TEMP[3], TEMP[1], TEMP[4]
> 20: ADD TEMP[3], TEMP[3], TEMP[3]
> 21: MAD TEMP[0].xyz, -TEMP[3], TEMP[1], TEMP[4]
> 22: MOV TEMP[0].w, IN[4]
> 23: MUL TEMP[3], TEMP[0].xxxx, CONST[11]
> 24: MAD TEMP[3], TEMP[0].yyyy, CONST[12], TEMP[3]
> 25: MAD TEMP[3], TEMP[0].zzzz, CONST[13], TEMP[3]
> 26: MAD OUT[3], TEMP[0].wwww, CONST[14], TEMP[3]
> 27: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
>  %64 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
>  %66 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %65, i32 0, i32 %5)
>  %67 = extractelement <4 x float> %66, i32 0
>  %68 = extractelement <4 x float> %66, i32 1
>  %69 = extractelement <4 x float> %66, i32 2
>  %70 = extractelement <4 x float> %66, i32 3
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %78 = load <16 x i8> addrspace(2)* %77, !tbaa !0
>  %79 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %78, i32 0, i32 %5)
>  %80 = extractelement <4 x float> %79, i32 0
>  %81 = extractelement <4 x float> %79, i32 1
>  %82 = extractelement <4 x float> %79, i32 2
>  %83 = extractelement <4 x float> %79, i32 3
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = extractelement <4 x float> %86, i32 3
>  %91 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0
>  %93 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %92, i32 0, i32 %5)
>  %94 = extractelement <4 x float> %93, i32 3
>  %95 = fmul float %67, %11
>  %96 = fmul float %67, %12
>  %97 = fmul float %67, %13
>  %98 = fmul float %67, %14
>  %99 = fmul float %68, %15
>  %100 = fadd float %99, %95
>  %101 = fmul float %68, %16
>  %102 = fadd float %101, %96
>  %103 = fmul float %68, %17
>  %104 = fadd float %103, %97
>  %105 = fmul float %68, %18
>  %106 = fadd float %105, %98
>  %107 = fmul float %69, %19
>  %108 = fadd float %107, %100
>  %109 = fmul float %69, %20
>  %110 = fadd float %109, %102
>  %111 = fmul float %69, %21
>  %112 = fadd float %111, %104
>  %113 = fmul float %69, %22
>  %114 = fadd float %113, %106
>  %115 = fmul float %70, %23
>  %116 = fadd float %115, %108
>  %117 = fmul float %70, %24
>  %118 = fadd float %117, %110
>  %119 = fmul float %70, %25
>  %120 = fadd float %119, %112
>  %121 = fmul float %70, %26
>  %122 = fadd float %121, %114
>  %123 = call float @llvm.AMDIL.clamp.(float %80, float 0.000000e+00, float 1.000000e+00)
>  %124 = call float @llvm.AMDIL.clamp.(float %81, float 0.000000e+00, float 1.000000e+00)
>  %125 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %126 = call float @llvm.AMDIL.clamp.(float %83, float 0.000000e+00, float 1.000000e+00)
>  %127 = fmul float %74, %27
>  %128 = fmul float %75, %28
>  %129 = fadd float %128, %127
>  %130 = fmul float %76, %29
>  %131 = fadd float %129, %130
>  %132 = fmul float %74, %30
>  %133 = fmul float %75, %31
>  %134 = fadd float %133, %132
>  %135 = fmul float %76, %32
>  %136 = fadd float %134, %135
>  %137 = fmul float %74, %33
>  %138 = fmul float %75, %34
>  %139 = fadd float %138, %137
>  %140 = fmul float %76, %35
>  %141 = fadd float %139, %140
>  %142 = fmul float %131, %131
>  %143 = fmul float %136, %136
>  %144 = fadd float %143, %142
>  %145 = fmul float %141, %141
>  %146 = fadd float %144, %145
>  %147 = call float @fabs(float %146)
>  %148 = call float @llvm.AMDGPU.rsq(float %147)
>  %149 = fmul float %131, %148
>  %150 = fmul float %136, %148
>  %151 = fmul float %141, %148
>  %152 = fmul float %67, %36
>  %153 = fmul float %67, %37
>  %154 = fmul float %67, %38
>  %155 = fmul float %68, %39
>  %156 = fadd float %155, %152
>  %157 = fmul float %68, %40
>  %158 = fadd float %157, %153
>  %159 = fmul float %68, %41
>  %160 = fadd float %159, %154
>  %161 = fmul float %69, %42
>  %162 = fadd float %161, %156
>  %163 = fmul float %69, %43
>  %164 = fadd float %163, %158
>  %165 = fmul float %69, %44
>  %166 = fadd float %165, %160
>  %167 = fmul float %70, %45
>  %168 = fadd float %167, %162
>  %169 = fmul float %70, %46
>  %170 = fadd float %169, %164
>  %171 = fmul float %70, %47
>  %172 = fadd float %171, %166
>  %173 = fmul float %168, %168
>  %174 = fmul float %170, %170
>  %175 = fadd float %174, %173
>  %176 = fmul float %172, %172
>  %177 = fadd float %175, %176
>  %178 = call float @fabs(float %177)
>  %179 = call float @llvm.AMDGPU.rsq(float %178)
>  %180 = fmul float %168, %179
>  %181 = fmul float %170, %179
>  %182 = fmul float %172, %179
>  %183 = fmul float %149, %180
>  %184 = fmul float %150, %181
>  %185 = fadd float %184, %183
>  %186 = fmul float %151, %182
>  %187 = fadd float %185, %186
>  %188 = fadd float %187, %187
>  %189 = fadd float %187, %187
>  %190 = fadd float %187, %187
>  %191 = fsub float -0.000000e+00, %188
>  %192 = fmul float %191, %149
>  %193 = fadd float %192, %180
>  %194 = fsub float -0.000000e+00, %189
>  %195 = fmul float %194, %150
>  %196 = fadd float %195, %181
>  %197 = fsub float -0.000000e+00, %190
>  %198 = fmul float %197, %151
>  %199 = fadd float %198, %182
>  %200 = fmul float %193, %48
>  %201 = fmul float %193, %49
>  %202 = fmul float %193, %50
>  %203 = fmul float %193, %51
>  %204 = fmul float %196, %52
>  %205 = fadd float %204, %200
>  %206 = fmul float %196, %53
>  %207 = fadd float %206, %201
>  %208 = fmul float %196, %54
>  %209 = fadd float %208, %202
>  %210 = fmul float %196, %55
>  %211 = fadd float %210, %203
>  %212 = fmul float %199, %56
>  %213 = fadd float %212, %205
>  %214 = fmul float %199, %57
>  %215 = fadd float %214, %207
>  %216 = fmul float %199, %58
>  %217 = fadd float %216, %209
>  %218 = fmul float %199, %59
>  %219 = fadd float %218, %211
>  %220 = fmul float %94, %60
>  %221 = fadd float %220, %213
>  %222 = fmul float %94, %61
>  %223 = fadd float %222, %215
>  %224 = fmul float %94, %62
>  %225 = fadd float %224, %217
>  %226 = fmul float %94, %63
>  %227 = fadd float %226, %219
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %123, float %124, float %125, float %126)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %87, float %88, float %89, float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %221, float %223, float %225, float %227)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %116, float %118, float %120, float %122)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0840704
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020114
>bf8c007f
>100a0204
>c2020115
>bf8c007f
>d2820005
>04140902
>c2020116
>bf8c007f
>d2820005
>04140903
>c2020110
>bf8c007f
>100c0204
>c2020111
>bf8c007f
>d2820006
>04180902
>c2020112
>bf8c007f
>d2820006
>04180903
>100e0d06
>d2820008
>041e0b05
>c2020118
>bf8c007f
>100e0204
>c2020119
>bf8c007f
>d2820007
>041c0902
>c202011a
>bf8c007f
>d2820007
>041c0903
>d2820001
>04220f07
>d2060101
>02010101
>7e105b01
>100c1106
>c0840700
>bf8c007f
>e00c2000
>80020100
>c202011d
>bf8c0070
>10120204
>c2020121
>bf8c007f
>d2820009
>04240902
>c2020125
>bf8c007f
>d2820009
>04240903
>c2020129
>bf8c007f
>d2820009
>04240904
>c202011c
>bf8c007f
>10140204
>c2020120
>bf8c007f
>d282000a
>04280902
>c2020124
>bf8c007f
>d282000a
>04280903
>c2020128
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c202011e
>bf8c007f
>10160204
>c2020122
>bf8c007f
>d282000b
>042c0902
>c2020126
>bf8c007f
>d282000b
>042c0903
>c202012a
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101c1506
>100a1105
>101a1909
>d2820009
>043a1b05
>100e1107
>1010190b
>d2820009
>04261107
>06121309
>100a0b09
>080a0b0d
>100c0d09
>080c0d0a
>c202012f
>bf8c007f
>10140c04
>c2020133
>bf8c007f
>d282000a
>04280905
>100e0f09
>080e0f08
>c2020137
>bf8c007f
>d282000c
>04280907
>c0820710
>bf8c007f
>e00c2000
>80010800
>c202013b
>bf8c0070
>d2820000
>0430090b
>c202012e
>bf8c007f
>10180c04
>c2020132
>bf8c007f
>d282000c
>04300905
>c2020136
>bf8c007f
>d282000c
>04300907
>c202013a
>bf8c007f
>d282000c
>0430090b
>c202012d
>bf8c007f
>101a0c04
>c2020131
>bf8c007f
>d282000d
>04340905
>c2020135
>bf8c007f
>d282000d
>04340907
>c2020139
>bf8c007f
>d282000d
>0434090b
>c202012c
>bf8c007f
>100c0c04
>c2020130
>bf8c007f
>d2820005
>04180905
>c2020134
>bf8c007f
>d2820005
>04140907
>c2020138
>bf8c007f
>d2820005
>0414090b
>f800022f
>000c0d05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL IN[6]
>DCL IN[7]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL OUT[5], GENERIC[4]
>DCL OUT[6], GENERIC[5]
>DCL CONST[0..10]
>DCL TEMP[0..3]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[2]
>  5: MOV OUT[2], IN[3]
>  6: DP3 TEMP[0].x, IN[1], CONST[4]
>  7: DP3 TEMP[0].y, IN[1], CONST[5]
>  8: DP3 TEMP[0].z, IN[1], CONST[6]
>  9: DP3 TEMP[1].x, TEMP[0], TEMP[0]
> 10: RSQ TEMP[1].x, |TEMP[1]|
> 11: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 12: MUL TEMP[1], IN[0].xxxx, CONST[7]
> 13: MAD TEMP[1], IN[0].yyyy, CONST[8], TEMP[1]
> 14: MAD TEMP[1], IN[0].zzzz, CONST[9], TEMP[1]
> 15: MAD TEMP[1], IN[0].wwww, CONST[10], TEMP[1]
> 16: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 17: RSQ TEMP[2].x, |TEMP[2]|
> 18: MUL TEMP[3], TEMP[1], TEMP[2].xxxx
> 19: DP3 TEMP[2], TEMP[0], TEMP[3]
> 20: ADD TEMP[2], TEMP[2], TEMP[2]
> 21: MAD OUT[3].xyz, -TEMP[2], TEMP[0], TEMP[3]
> 22: MOV OUT[3].w, IN[4]
> 23: MOV OUT[4], IN[5]
> 24: MOV OUT[5], IN[6]
> 25: MOV OUT[6], IN[7]
> 26: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %48 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %5)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = extractelement <4 x float> %50, i32 3
>  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
>  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
>  %58 = extractelement <4 x float> %57, i32 0
>  %59 = extractelement <4 x float> %57, i32 1
>  %60 = extractelement <4 x float> %57, i32 2
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 0
>  %65 = extractelement <4 x float> %63, i32 1
>  %66 = extractelement <4 x float> %63, i32 2
>  %67 = extractelement <4 x float> %63, i32 3
>  %68 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
>  %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %69, i32 0, i32 %5)
>  %71 = extractelement <4 x float> %70, i32 0
>  %72 = extractelement <4 x float> %70, i32 1
>  %73 = extractelement <4 x float> %70, i32 2
>  %74 = extractelement <4 x float> %70, i32 3
>  %75 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0
>  %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %76, i32 0, i32 %5)
>  %78 = extractelement <4 x float> %77, i32 3
>  %79 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %80 = load <16 x i8> addrspace(2)* %79, !tbaa !0
>  %81 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %80, i32 0, i32 %5)
>  %82 = extractelement <4 x float> %81, i32 0
>  %83 = extractelement <4 x float> %81, i32 1
>  %84 = extractelement <4 x float> %81, i32 2
>  %85 = extractelement <4 x float> %81, i32 3
>  %86 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
>  %87 = load <16 x i8> addrspace(2)* %86, !tbaa !0
>  %88 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %87, i32 0, i32 %5)
>  %89 = extractelement <4 x float> %88, i32 0
>  %90 = extractelement <4 x float> %88, i32 1
>  %91 = extractelement <4 x float> %88, i32 2
>  %92 = extractelement <4 x float> %88, i32 3
>  %93 = getelementptr <16 x i8> addrspace(2)* %3, i32 7
>  %94 = load <16 x i8> addrspace(2)* %93, !tbaa !0
>  %95 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %94, i32 0, i32 %5)
>  %96 = extractelement <4 x float> %95, i32 0
>  %97 = extractelement <4 x float> %95, i32 1
>  %98 = extractelement <4 x float> %95, i32 2
>  %99 = extractelement <4 x float> %95, i32 3
>  %100 = fmul float %51, %11
>  %101 = fmul float %51, %12
>  %102 = fmul float %51, %13
>  %103 = fmul float %51, %14
>  %104 = fmul float %52, %15
>  %105 = fadd float %104, %100
>  %106 = fmul float %52, %16
>  %107 = fadd float %106, %101
>  %108 = fmul float %52, %17
>  %109 = fadd float %108, %102
>  %110 = fmul float %52, %18
>  %111 = fadd float %110, %103
>  %112 = fmul float %53, %19
>  %113 = fadd float %112, %105
>  %114 = fmul float %53, %20
>  %115 = fadd float %114, %107
>  %116 = fmul float %53, %21
>  %117 = fadd float %116, %109
>  %118 = fmul float %53, %22
>  %119 = fadd float %118, %111
>  %120 = fmul float %54, %23
>  %121 = fadd float %120, %113
>  %122 = fmul float %54, %24
>  %123 = fadd float %122, %115
>  %124 = fmul float %54, %25
>  %125 = fadd float %124, %117
>  %126 = fmul float %54, %26
>  %127 = fadd float %126, %119
>  %128 = call float @llvm.AMDIL.clamp.(float %64, float 0.000000e+00, float 1.000000e+00)
>  %129 = call float @llvm.AMDIL.clamp.(float %65, float 0.000000e+00, float 1.000000e+00)
>  %130 = call float @llvm.AMDIL.clamp.(float %66, float 0.000000e+00, float 1.000000e+00)
>  %131 = call float @llvm.AMDIL.clamp.(float %67, float 0.000000e+00, float 1.000000e+00)
>  %132 = fmul float %58, %27
>  %133 = fmul float %59, %28
>  %134 = fadd float %133, %132
>  %135 = fmul float %60, %29
>  %136 = fadd float %134, %135
>  %137 = fmul float %58, %30
>  %138 = fmul float %59, %31
>  %139 = fadd float %138, %137
>  %140 = fmul float %60, %32
>  %141 = fadd float %139, %140
>  %142 = fmul float %58, %33
>  %143 = fmul float %59, %34
>  %144 = fadd float %143, %142
>  %145 = fmul float %60, %35
>  %146 = fadd float %144, %145
>  %147 = fmul float %136, %136
>  %148 = fmul float %141, %141
>  %149 = fadd float %148, %147
>  %150 = fmul float %146, %146
>  %151 = fadd float %149, %150
>  %152 = call float @fabs(float %151)
>  %153 = call float @llvm.AMDGPU.rsq(float %152)
>  %154 = fmul float %136, %153
>  %155 = fmul float %141, %153
>  %156 = fmul float %146, %153
>  %157 = fmul float %51, %36
>  %158 = fmul float %51, %37
>  %159 = fmul float %51, %38
>  %160 = fmul float %52, %39
>  %161 = fadd float %160, %157
>  %162 = fmul float %52, %40
>  %163 = fadd float %162, %158
>  %164 = fmul float %52, %41
>  %165 = fadd float %164, %159
>  %166 = fmul float %53, %42
>  %167 = fadd float %166, %161
>  %168 = fmul float %53, %43
>  %169 = fadd float %168, %163
>  %170 = fmul float %53, %44
>  %171 = fadd float %170, %165
>  %172 = fmul float %54, %45
>  %173 = fadd float %172, %167
>  %174 = fmul float %54, %46
>  %175 = fadd float %174, %169
>  %176 = fmul float %54, %47
>  %177 = fadd float %176, %171
>  %178 = fmul float %173, %173
>  %179 = fmul float %175, %175
>  %180 = fadd float %179, %178
>  %181 = fmul float %177, %177
>  %182 = fadd float %180, %181
>  %183 = call float @fabs(float %182)
>  %184 = call float @llvm.AMDGPU.rsq(float %183)
>  %185 = fmul float %173, %184
>  %186 = fmul float %175, %184
>  %187 = fmul float %177, %184
>  %188 = fmul float %154, %185
>  %189 = fmul float %155, %186
>  %190 = fadd float %189, %188
>  %191 = fmul float %156, %187
>  %192 = fadd float %190, %191
>  %193 = fadd float %192, %192
>  %194 = fadd float %192, %192
>  %195 = fadd float %192, %192
>  %196 = fsub float -0.000000e+00, %193
>  %197 = fmul float %196, %154
>  %198 = fadd float %197, %185
>  %199 = fsub float -0.000000e+00, %194
>  %200 = fmul float %199, %155
>  %201 = fadd float %200, %186
>  %202 = fsub float -0.000000e+00, %195
>  %203 = fmul float %202, %156
>  %204 = fadd float %203, %187
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %128, float %129, float %130, float %131)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %71, float %72, float %73, float %74)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %198, float %201, float %204, float %78)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %82, float %83, float %84, float %85)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %89, float %90, float %91, float %92)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %96, float %97, float %98, float %99)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %121, float %123, float %125, float %127)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0840704
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020114
>bf8c007f
>100a0204
>c2020115
>bf8c007f
>d2820005
>04140902
>c2020116
>bf8c007f
>d2820005
>04140903
>c2020110
>bf8c007f
>100c0204
>c2020111
>bf8c007f
>d2820006
>04180902
>c2020112
>bf8c007f
>d2820006
>04180903
>100e0d06
>d2820008
>041e0b05
>c2020118
>bf8c007f
>100e0204
>c2020119
>bf8c007f
>d2820007
>041c0902
>c202011a
>bf8c007f
>d2820007
>041c0903
>d2820001
>04220f07
>d2060101
>02010101
>7e105b01
>100c1106
>c0840700
>bf8c007f
>e00c2000
>80020100
>c202011d
>bf8c0070
>10120204
>c2020121
>bf8c007f
>d2820009
>04240902
>c2020125
>bf8c007f
>d2820009
>04240903
>c2020129
>bf8c007f
>d2820009
>04240904
>c202011c
>bf8c007f
>10140204
>c2020120
>bf8c007f
>d282000a
>04280902
>c2020124
>bf8c007f
>d282000a
>04280903
>c2020128
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c202011e
>bf8c007f
>10160204
>c2020122
>bf8c007f
>d282000b
>042c0902
>c2020126
>bf8c007f
>d282000b
>042c0903
>c202012a
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101a1506
>100a1105
>10121909
>d282000d
>04361305
>100e1107
>1016190b
>d2820008
>04361707
>06101108
>100e0f08
>080e0f0b
>100a0b08
>080a0b09
>100c0d08
>080c0d0a
>c0840710
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800022f
>0b070506
>c0840714
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800023f
>08070605
>c0840718
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800024f
>08070605
>c082071c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800025f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: MOV OUT[3], IN[3]
>  7: MOV OUT[4], IN[4]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %5)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = extractelement <4 x float> %50, i32 3
>  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
>  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
>  %58 = extractelement <4 x float> %57, i32 0
>  %59 = extractelement <4 x float> %57, i32 1
>  %60 = extractelement <4 x float> %57, i32 2
>  %61 = extractelement <4 x float> %57, i32 3
>  %62 = fmul float %30, %11
>  %63 = fmul float %30, %12
>  %64 = fmul float %30, %13
>  %65 = fmul float %30, %14
>  %66 = fmul float %31, %15
>  %67 = fadd float %66, %62
>  %68 = fmul float %31, %16
>  %69 = fadd float %68, %63
>  %70 = fmul float %31, %17
>  %71 = fadd float %70, %64
>  %72 = fmul float %31, %18
>  %73 = fadd float %72, %65
>  %74 = fmul float %32, %19
>  %75 = fadd float %74, %67
>  %76 = fmul float %32, %20
>  %77 = fadd float %76, %69
>  %78 = fmul float %32, %21
>  %79 = fadd float %78, %71
>  %80 = fmul float %32, %22
>  %81 = fadd float %80, %73
>  %82 = fmul float %33, %23
>  %83 = fadd float %82, %75
>  %84 = fmul float %33, %24
>  %85 = fadd float %84, %77
>  %86 = fmul float %33, %25
>  %87 = fadd float %86, %79
>  %88 = fmul float %33, %26
>  %89 = fadd float %88, %81
>  %90 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %91 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %92 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %93 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %90, float %91, float %92, float %93)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %51, float %52, float %53, float %54)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %58, float %59, float %60, float %61)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %83, float %85, float %87, float %89)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800022f
>04030201
>c0840710
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800023f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..10]
>DCL TEMP[0..3]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[2]
>  5: MOV OUT[2], IN[3]
>  6: DP3 TEMP[0].x, IN[1], CONST[4]
>  7: DP3 TEMP[0].y, IN[1], CONST[5]
>  8: DP3 TEMP[0].z, IN[1], CONST[6]
>  9: DP3 TEMP[1].x, TEMP[0], TEMP[0]
> 10: RSQ TEMP[1].x, |TEMP[1]|
> 11: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 12: MUL TEMP[1], IN[0].xxxx, CONST[7]
> 13: MAD TEMP[1], IN[0].yyyy, CONST[8], TEMP[1]
> 14: MAD TEMP[1], IN[0].zzzz, CONST[9], TEMP[1]
> 15: MAD TEMP[1], IN[0].wwww, CONST[10], TEMP[1]
> 16: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 17: RSQ TEMP[2].x, |TEMP[2]|
> 18: MUL TEMP[3], TEMP[1], TEMP[2].xxxx
> 19: DP3 TEMP[2], TEMP[0], TEMP[3]
> 20: ADD TEMP[2], TEMP[2], TEMP[2]
> 21: MAD OUT[3].xyz, -TEMP[2], TEMP[0], TEMP[3]
> 22: MOV OUT[3].w, IN[4]
> 23: MOV OUT[4], IN[5]
> 24: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %48 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %5)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = extractelement <4 x float> %50, i32 3
>  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
>  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
>  %58 = extractelement <4 x float> %57, i32 0
>  %59 = extractelement <4 x float> %57, i32 1
>  %60 = extractelement <4 x float> %57, i32 2
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 0
>  %65 = extractelement <4 x float> %63, i32 1
>  %66 = extractelement <4 x float> %63, i32 2
>  %67 = extractelement <4 x float> %63, i32 3
>  %68 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
>  %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %69, i32 0, i32 %5)
>  %71 = extractelement <4 x float> %70, i32 0
>  %72 = extractelement <4 x float> %70, i32 1
>  %73 = extractelement <4 x float> %70, i32 2
>  %74 = extractelement <4 x float> %70, i32 3
>  %75 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0
>  %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %76, i32 0, i32 %5)
>  %78 = extractelement <4 x float> %77, i32 3
>  %79 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %80 = load <16 x i8> addrspace(2)* %79, !tbaa !0
>  %81 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %80, i32 0, i32 %5)
>  %82 = extractelement <4 x float> %81, i32 0
>  %83 = extractelement <4 x float> %81, i32 1
>  %84 = extractelement <4 x float> %81, i32 2
>  %85 = extractelement <4 x float> %81, i32 3
>  %86 = fmul float %51, %11
>  %87 = fmul float %51, %12
>  %88 = fmul float %51, %13
>  %89 = fmul float %51, %14
>  %90 = fmul float %52, %15
>  %91 = fadd float %90, %86
>  %92 = fmul float %52, %16
>  %93 = fadd float %92, %87
>  %94 = fmul float %52, %17
>  %95 = fadd float %94, %88
>  %96 = fmul float %52, %18
>  %97 = fadd float %96, %89
>  %98 = fmul float %53, %19
>  %99 = fadd float %98, %91
>  %100 = fmul float %53, %20
>  %101 = fadd float %100, %93
>  %102 = fmul float %53, %21
>  %103 = fadd float %102, %95
>  %104 = fmul float %53, %22
>  %105 = fadd float %104, %97
>  %106 = fmul float %54, %23
>  %107 = fadd float %106, %99
>  %108 = fmul float %54, %24
>  %109 = fadd float %108, %101
>  %110 = fmul float %54, %25
>  %111 = fadd float %110, %103
>  %112 = fmul float %54, %26
>  %113 = fadd float %112, %105
>  %114 = call float @llvm.AMDIL.clamp.(float %64, float 0.000000e+00, float 1.000000e+00)
>  %115 = call float @llvm.AMDIL.clamp.(float %65, float 0.000000e+00, float 1.000000e+00)
>  %116 = call float @llvm.AMDIL.clamp.(float %66, float 0.000000e+00, float 1.000000e+00)
>  %117 = call float @llvm.AMDIL.clamp.(float %67, float 0.000000e+00, float 1.000000e+00)
>  %118 = fmul float %58, %27
>  %119 = fmul float %59, %28
>  %120 = fadd float %119, %118
>  %121 = fmul float %60, %29
>  %122 = fadd float %120, %121
>  %123 = fmul float %58, %30
>  %124 = fmul float %59, %31
>  %125 = fadd float %124, %123
>  %126 = fmul float %60, %32
>  %127 = fadd float %125, %126
>  %128 = fmul float %58, %33
>  %129 = fmul float %59, %34
>  %130 = fadd float %129, %128
>  %131 = fmul float %60, %35
>  %132 = fadd float %130, %131
>  %133 = fmul float %122, %122
>  %134 = fmul float %127, %127
>  %135 = fadd float %134, %133
>  %136 = fmul float %132, %132
>  %137 = fadd float %135, %136
>  %138 = call float @fabs(float %137)
>  %139 = call float @llvm.AMDGPU.rsq(float %138)
>  %140 = fmul float %122, %139
>  %141 = fmul float %127, %139
>  %142 = fmul float %132, %139
>  %143 = fmul float %51, %36
>  %144 = fmul float %51, %37
>  %145 = fmul float %51, %38
>  %146 = fmul float %52, %39
>  %147 = fadd float %146, %143
>  %148 = fmul float %52, %40
>  %149 = fadd float %148, %144
>  %150 = fmul float %52, %41
>  %151 = fadd float %150, %145
>  %152 = fmul float %53, %42
>  %153 = fadd float %152, %147
>  %154 = fmul float %53, %43
>  %155 = fadd float %154, %149
>  %156 = fmul float %53, %44
>  %157 = fadd float %156, %151
>  %158 = fmul float %54, %45
>  %159 = fadd float %158, %153
>  %160 = fmul float %54, %46
>  %161 = fadd float %160, %155
>  %162 = fmul float %54, %47
>  %163 = fadd float %162, %157
>  %164 = fmul float %159, %159
>  %165 = fmul float %161, %161
>  %166 = fadd float %165, %164
>  %167 = fmul float %163, %163
>  %168 = fadd float %166, %167
>  %169 = call float @fabs(float %168)
>  %170 = call float @llvm.AMDGPU.rsq(float %169)
>  %171 = fmul float %159, %170
>  %172 = fmul float %161, %170
>  %173 = fmul float %163, %170
>  %174 = fmul float %140, %171
>  %175 = fmul float %141, %172
>  %176 = fadd float %175, %174
>  %177 = fmul float %142, %173
>  %178 = fadd float %176, %177
>  %179 = fadd float %178, %178
>  %180 = fadd float %178, %178
>  %181 = fadd float %178, %178
>  %182 = fsub float -0.000000e+00, %179
>  %183 = fmul float %182, %140
>  %184 = fadd float %183, %171
>  %185 = fsub float -0.000000e+00, %180
>  %186 = fmul float %185, %141
>  %187 = fadd float %186, %172
>  %188 = fsub float -0.000000e+00, %181
>  %189 = fmul float %188, %142
>  %190 = fadd float %189, %173
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %114, float %115, float %116, float %117)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %71, float %72, float %73, float %74)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %184, float %187, float %190, float %78)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %82, float %83, float %84, float %85)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %107, float %109, float %111, float %113)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0840704
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020114
>bf8c007f
>100a0204
>c2020115
>bf8c007f
>d2820005
>04140902
>c2020116
>bf8c007f
>d2820005
>04140903
>c2020110
>bf8c007f
>100c0204
>c2020111
>bf8c007f
>d2820006
>04180902
>c2020112
>bf8c007f
>d2820006
>04180903
>100e0d06
>d2820008
>041e0b05
>c2020118
>bf8c007f
>100e0204
>c2020119
>bf8c007f
>d2820007
>041c0902
>c202011a
>bf8c007f
>d2820007
>041c0903
>d2820001
>04220f07
>d2060101
>02010101
>7e105b01
>100c1106
>c0840700
>bf8c007f
>e00c2000
>80020100
>c202011d
>bf8c0070
>10120204
>c2020121
>bf8c007f
>d2820009
>04240902
>c2020125
>bf8c007f
>d2820009
>04240903
>c2020129
>bf8c007f
>d2820009
>04240904
>c202011c
>bf8c007f
>10140204
>c2020120
>bf8c007f
>d282000a
>04280902
>c2020124
>bf8c007f
>d282000a
>04280903
>c2020128
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c202011e
>bf8c007f
>10160204
>c2020122
>bf8c007f
>d282000b
>042c0902
>c2020126
>bf8c007f
>d282000b
>042c0903
>c202012a
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101a1506
>100a1105
>10121909
>d282000d
>04361305
>100e1107
>1016190b
>d2820008
>04361707
>06101108
>100e0f08
>080e0f0b
>100a0b08
>080a0b09
>100c0d08
>080c0d0a
>c0840710
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800022f
>0b070506
>c0820714
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV TEMP[1].xy, IN[2].xyyy
>  5: MOV TEMP[1].w, IN[2].wwww
>  6: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  7: MUL_SAT TEMP[2], TEMP[0], IMM[0].xxxy
>  8: MUL TEMP[1].xyz, TEMP[1], TEMP[2]
>  9: MOV TEMP[1].xyz, TEMP[1].xyzx
> 10: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
> 11: MOV TEMP[1].w, TEMP[0].wwww
> 12: MOV OUT[0], TEMP[1]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %38 = fdiv float %32, %34
>  %39 = fdiv float %33, %34
>  %40 = bitcast float %38 to i32
>  %41 = bitcast float %39 to i32
>  %42 = insertelement <2 x i32> undef, i32 %40, i32 0
>  %43 = insertelement <2 x i32> %42, i32 %41, i32 1
>  %44 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %43, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = extractelement <4 x float> %44, i32 1
>  %47 = extractelement <4 x float> %44, i32 2
>  %48 = extractelement <4 x float> %44, i32 3
>  %49 = fmul float %45, %28
>  %50 = fmul float %46, %29
>  %51 = fmul float %47, %30
>  %52 = fmul float %48, %31
>  %53 = fdiv float %35, %37
>  %54 = fdiv float %36, %37
>  %55 = bitcast float %53 to i32
>  %56 = bitcast float %54 to i32
>  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
>  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
>  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = fmul float %49, 2.000000e+00
>  %64 = fmul float %50, 2.000000e+00
>  %65 = fmul float %51, 2.000000e+00
>  %66 = fmul float %52, 1.000000e+00
>  %67 = call float @llvm.AMDIL.clamp.(float %63, float 0.000000e+00, float 1.000000e+00)
>  %68 = call float @llvm.AMDIL.clamp.(float %64, float 0.000000e+00, float 1.000000e+00)
>  %69 = call float @llvm.AMDIL.clamp.(float %65, float 0.000000e+00, float 1.000000e+00)
>  %70 = call float @llvm.AMDIL.clamp.(float %66, float 0.000000e+00, float 1.000000e+00)
>  %71 = fmul float %60, %67
>  %72 = fmul float %61, %68
>  %73 = fmul float %62, %69
>  %74 = fmul float %49, 2.000000e+00
>  %75 = fmul float %50, 2.000000e+00
>  %76 = fmul float %51, 2.000000e+00
>  %77 = fmul float %52, 1.000000e+00
>  %78 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %75, float 0.000000e+00, float 1.000000e+00)
>  %80 = call float @llvm.AMDIL.clamp.(float %76, float 0.000000e+00, float 1.000000e+00)
>  %81 = call float @llvm.AMDIL.clamp.(float %77, float 0.000000e+00, float 1.000000e+00)
>  %82 = call i32 @llvm.SI.packf16(float %71, float %72)
>  %83 = bitcast i32 %82 to float
>  %84 = call i32 @llvm.SI.packf16(float %73, float %81)
>  %85 = bitcast i32 %84 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %83, float %85, float %83, float %85)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180100
>c8190101
>bf8c0770
>100e0d03
>d2820006
>041e0d03
>d2060806
>02010106
>c81c0900
>c81d0901
>c8200b00
>c8210b01
>7e125508
>10101307
>c8280800
>c8290801
>100e130a
>c0800300
>c0c40500
>bf8c007f
>f0800700
>00020707
>bf8c0770
>100c0d08
>c8280000
>c8290001
>10161502
>d282000a
>042e1502
>d206080a
>0201010a
>10141507
>5e0c0d0a
>c8280200
>c8290201
>10161504
>d282000a
>042e1504
>d206080a
>0201010a
>100e1509
>c8200300
>c8210301
>10001105
>d2060800
>02010100
>5e000107
>f8001c0f
>00060006
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: MOV OUT[3], IN[3]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %5)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = extractelement <4 x float> %50, i32 3
>  %55 = fmul float %30, %11
>  %56 = fmul float %30, %12
>  %57 = fmul float %30, %13
>  %58 = fmul float %30, %14
>  %59 = fmul float %31, %15
>  %60 = fadd float %59, %55
>  %61 = fmul float %31, %16
>  %62 = fadd float %61, %56
>  %63 = fmul float %31, %17
>  %64 = fadd float %63, %57
>  %65 = fmul float %31, %18
>  %66 = fadd float %65, %58
>  %67 = fmul float %32, %19
>  %68 = fadd float %67, %60
>  %69 = fmul float %32, %20
>  %70 = fadd float %69, %62
>  %71 = fmul float %32, %21
>  %72 = fadd float %71, %64
>  %73 = fmul float %32, %22
>  %74 = fadd float %73, %66
>  %75 = fmul float %33, %23
>  %76 = fadd float %75, %68
>  %77 = fmul float %33, %24
>  %78 = fadd float %77, %70
>  %79 = fmul float %33, %25
>  %80 = fadd float %79, %72
>  %81 = fmul float %33, %26
>  %82 = fadd float %81, %74
>  %83 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %84 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %85 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %86 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %83, float %84, float %85, float %86)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %51, float %52, float %53, float %54)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %76, float %78, float %80, float %82)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800022f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: MUL TEMP[0], IN[3].xxxx, CONST[4]
>  7: MAD TEMP[0], IN[3].yyyy, CONST[5], TEMP[0]
>  8: MAD TEMP[0], IN[3].zzzz, CONST[6], TEMP[0]
>  9: MAD OUT[3], IN[3].wwww, CONST[7], TEMP[0]
> 10: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = extractelement <4 x float> %59, i32 3
>  %64 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
>  %66 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %65, i32 0, i32 %5)
>  %67 = extractelement <4 x float> %66, i32 0
>  %68 = extractelement <4 x float> %66, i32 1
>  %69 = extractelement <4 x float> %66, i32 2
>  %70 = extractelement <4 x float> %66, i32 3
>  %71 = fmul float %46, %11
>  %72 = fmul float %46, %12
>  %73 = fmul float %46, %13
>  %74 = fmul float %46, %14
>  %75 = fmul float %47, %15
>  %76 = fadd float %75, %71
>  %77 = fmul float %47, %16
>  %78 = fadd float %77, %72
>  %79 = fmul float %47, %17
>  %80 = fadd float %79, %73
>  %81 = fmul float %47, %18
>  %82 = fadd float %81, %74
>  %83 = fmul float %48, %19
>  %84 = fadd float %83, %76
>  %85 = fmul float %48, %20
>  %86 = fadd float %85, %78
>  %87 = fmul float %48, %21
>  %88 = fadd float %87, %80
>  %89 = fmul float %48, %22
>  %90 = fadd float %89, %82
>  %91 = fmul float %49, %23
>  %92 = fadd float %91, %84
>  %93 = fmul float %49, %24
>  %94 = fadd float %93, %86
>  %95 = fmul float %49, %25
>  %96 = fadd float %95, %88
>  %97 = fmul float %49, %26
>  %98 = fadd float %97, %90
>  %99 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
>  %100 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %101 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %102 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
>  %103 = fmul float %67, %27
>  %104 = fmul float %67, %28
>  %105 = fmul float %67, %29
>  %106 = fmul float %67, %30
>  %107 = fmul float %68, %31
>  %108 = fadd float %107, %103
>  %109 = fmul float %68, %32
>  %110 = fadd float %109, %104
>  %111 = fmul float %68, %33
>  %112 = fadd float %111, %105
>  %113 = fmul float %68, %34
>  %114 = fadd float %113, %106
>  %115 = fmul float %69, %35
>  %116 = fadd float %115, %108
>  %117 = fmul float %69, %36
>  %118 = fadd float %117, %110
>  %119 = fmul float %69, %37
>  %120 = fadd float %119, %112
>  %121 = fmul float %69, %38
>  %122 = fadd float %121, %114
>  %123 = fmul float %70, %39
>  %124 = fadd float %123, %116
>  %125 = fmul float %70, %40
>  %126 = fadd float %125, %118
>  %127 = fmul float %70, %41
>  %128 = fadd float %127, %120
>  %129 = fmul float %70, %42
>  %130 = fadd float %129, %122
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %99, float %100, float %101, float %102)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %60, float %61, float %62, float %63)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %124, float %126, float %128, float %130)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %92, float %94, float %96, float %98)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c084070c
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800022f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL IN[3], GENERIC[2], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[2], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  5: MOV TEMP[0].xyz, TEMP[0].xyzx
>  6: MOV TEMP[1].xy, IN[2].xyyy
>  7: MOV TEMP[1].w, IN[2].wwww
>  8: TXP TEMP[1].w, TEMP[1], SAMP[1], 2D
>  9: MOV TEMP[0].w, TEMP[1].wwww
> 10: ADD TEMP[2].x, IMM[0].yyyy, -TEMP[1].wwww
> 11: TXP TEMP[3], IN[3], SAMP[0], CUBE
> 12: MUL TEMP[3], TEMP[3], TEMP[1].wwww
> 13: MAD TEMP[0].xyz, TEMP[0], TEMP[2].xxxx, TEMP[3]
> 14: MOV TEMP[0].xyz, TEMP[0].xyzx
> 15: MOV TEMP[0].w, TEMP[1].wwww
> 16: MOV OUT[0], TEMP[0]
> 17: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %46 = fdiv float %36, %38
>  %47 = fdiv float %37, %38
>  %48 = bitcast float %46 to i32
>  %49 = bitcast float %47 to i32
>  %50 = insertelement <2 x i32> undef, i32 %48, i32 0
>  %51 = insertelement <2 x i32> %50, i32 %49, i32 1
>  %52 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %51, <32 x i8> %29, <16 x i8> %31, i32 2)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = fmul float %53, %32
>  %58 = fmul float %54, %33
>  %59 = fmul float %55, %34
>  %60 = fmul float %56, %35
>  %61 = fmul float %57, 2.000000e+00
>  %62 = fmul float %58, 2.000000e+00
>  %63 = fmul float %59, 2.000000e+00
>  %64 = fmul float %60, 1.000000e+00
>  %65 = call float @llvm.AMDIL.clamp.(float %61, float 0.000000e+00, float 1.000000e+00)
>  %66 = call float @llvm.AMDIL.clamp.(float %62, float 0.000000e+00, float 1.000000e+00)
>  %67 = call float @llvm.AMDIL.clamp.(float %63, float 0.000000e+00, float 1.000000e+00)
>  %68 = call float @llvm.AMDIL.clamp.(float %64, float 0.000000e+00, float 1.000000e+00)
>  %69 = fdiv float %39, %41
>  %70 = fdiv float %40, %41
>  %71 = bitcast float %69 to i32
>  %72 = bitcast float %70 to i32
>  %73 = insertelement <2 x i32> undef, i32 %71, i32 0
>  %74 = insertelement <2 x i32> %73, i32 %72, i32 1
>  %75 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %74, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %76 = extractelement <4 x float> %75, i32 3
>  %77 = fsub float -0.000000e+00, %76
>  %78 = fadd float 1.000000e+00, %77
>  %79 = fdiv float %42, %45
>  %80 = fdiv float %43, %45
>  %81 = fdiv float %44, %45
>  %82 = insertelement <4 x float> undef, float %79, i32 0
>  %83 = insertelement <4 x float> %82, float %80, i32 1
>  %84 = insertelement <4 x float> %83, float %81, i32 2
>  %85 = insertelement <4 x float> %84, float 1.000000e+00, i32 3
>  %86 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %85)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = extractelement <4 x float> %86, i32 3
>  %91 = call float @fabs(float %89)
>  %92 = fdiv float 1.000000e+00, %91
>  %93 = fmul float %87, %92
>  %94 = fadd float %93, 1.500000e+00
>  %95 = fmul float %88, %92
>  %96 = fadd float %95, 1.500000e+00
>  %97 = bitcast float %96 to i32
>  %98 = bitcast float %94 to i32
>  %99 = bitcast float %90 to i32
>  %100 = insertelement <4 x i32> undef, i32 %97, i32 0
>  %101 = insertelement <4 x i32> %100, i32 %98, i32 1
>  %102 = insertelement <4 x i32> %101, i32 %99, i32 2
>  %103 = insertelement <4 x i32> %102, i32 undef, i32 3
>  %104 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %103, <32 x i8> %21, <16 x i8> %23, i32 4)
>  %105 = extractelement <4 x float> %104, i32 0
>  %106 = extractelement <4 x float> %104, i32 1
>  %107 = extractelement <4 x float> %104, i32 2
>  %108 = fmul float %105, %76
>  %109 = fmul float %106, %76
>  %110 = fmul float %107, %76
>  %111 = fmul float %65, %78
>  %112 = fadd float %111, %108
>  %113 = fmul float %66, %78
>  %114 = fadd float %113, %109
>  %115 = fmul float %67, %78
>  %116 = fadd float %115, %110
>  %117 = call i32 @llvm.SI.packf16(float %112, float %114)
>  %118 = bitcast i32 %117 to float
>  %119 = call i32 @llvm.SI.packf16(float %116, float %76)
>  %120 = bitcast i32 %119 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %118, float %120, float %118, float %120)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080d00
>c8090d01
>c80c0f00
>c80d0f01
>7e0c5503
>10060d02
>c81c0c00
>c81d0c01
>10040d07
>c81c0e00
>c81d0e01
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430207
>c8140900
>c8150901
>c8180b00
>c8190b01
>7e0e5506
>100c0f05
>c8200800
>c8210801
>100a0f08
>c0840304
>c0c60508
>bf8c0070
>f0800800
>00430505
>bf8c0770
>100c0b03
>c81c0500
>c81d0501
>c8200700
>c8210701
>7e125508
>10101307
>c8280400
>c8290401
>100e130a
>c0800308
>c0c40510
>bf8c007f
>f0800700
>00020707
>c8280100
>c8290101
>bf8c0770
>10161508
>d282000a
>042e1508
>d206080b
>0201010a
>08140af2
>d2820006
>041a150b
>10160b02
>c8300000
>c8310001
>101a1907
>d282000c
>04361907
>d206080c
>0201010c
>d282000b
>042e150c
>5e0c0d0b
>10040b04
>c80c0200
>c80d0201
>10000709
>d2820000
>04020709
>d2060800
>02010100
>d2820000
>040a1500
>5e000b00
>f8001c0f
>00060006
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..14]
>DCL TEMP[0..4]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[2]
>  5: MOV OUT[2], IN[3]
>  6: MOV OUT[3], IN[4]
>  7: DP3 TEMP[1].x, IN[1], CONST[4]
>  8: DP3 TEMP[1].y, IN[1], CONST[5]
>  9: DP3 TEMP[1].z, IN[1], CONST[6]
> 10: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 11: RSQ TEMP[2].x, |TEMP[2]|
> 12: MUL TEMP[1], TEMP[1], TEMP[2].xxxx
> 13: MUL TEMP[2], IN[0].xxxx, CONST[7]
> 14: MAD TEMP[2], IN[0].yyyy, CONST[8], TEMP[2]
> 15: MAD TEMP[2], IN[0].zzzz, CONST[9], TEMP[2]
> 16: MAD TEMP[2], IN[0].wwww, CONST[10], TEMP[2]
> 17: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 18: RSQ TEMP[3].x, |TEMP[3]|
> 19: MUL TEMP[4], TEMP[2], TEMP[3].xxxx
> 20: DP3 TEMP[3], TEMP[1], TEMP[4]
> 21: ADD TEMP[3], TEMP[3], TEMP[3]
> 22: MAD TEMP[0].xyz, -TEMP[3], TEMP[1], TEMP[4]
> 23: MOV TEMP[0].w, IN[5]
> 24: MUL TEMP[3], TEMP[0].xxxx, CONST[11]
> 25: MAD TEMP[3], TEMP[0].yyyy, CONST[12], TEMP[3]
> 26: MAD TEMP[3], TEMP[0].zzzz, CONST[13], TEMP[3]
> 27: MAD OUT[4], TEMP[0].wwww, CONST[14], TEMP[3]
> 28: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
>  %64 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
>  %66 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %65, i32 0, i32 %5)
>  %67 = extractelement <4 x float> %66, i32 0
>  %68 = extractelement <4 x float> %66, i32 1
>  %69 = extractelement <4 x float> %66, i32 2
>  %70 = extractelement <4 x float> %66, i32 3
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %78 = load <16 x i8> addrspace(2)* %77, !tbaa !0
>  %79 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %78, i32 0, i32 %5)
>  %80 = extractelement <4 x float> %79, i32 0
>  %81 = extractelement <4 x float> %79, i32 1
>  %82 = extractelement <4 x float> %79, i32 2
>  %83 = extractelement <4 x float> %79, i32 3
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = extractelement <4 x float> %86, i32 3
>  %91 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0
>  %93 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %92, i32 0, i32 %5)
>  %94 = extractelement <4 x float> %93, i32 0
>  %95 = extractelement <4 x float> %93, i32 1
>  %96 = extractelement <4 x float> %93, i32 2
>  %97 = extractelement <4 x float> %93, i32 3
>  %98 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %99 = load <16 x i8> addrspace(2)* %98, !tbaa !0
>  %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %99, i32 0, i32 %5)
>  %101 = extractelement <4 x float> %100, i32 3
>  %102 = fmul float %67, %11
>  %103 = fmul float %67, %12
>  %104 = fmul float %67, %13
>  %105 = fmul float %67, %14
>  %106 = fmul float %68, %15
>  %107 = fadd float %106, %102
>  %108 = fmul float %68, %16
>  %109 = fadd float %108, %103
>  %110 = fmul float %68, %17
>  %111 = fadd float %110, %104
>  %112 = fmul float %68, %18
>  %113 = fadd float %112, %105
>  %114 = fmul float %69, %19
>  %115 = fadd float %114, %107
>  %116 = fmul float %69, %20
>  %117 = fadd float %116, %109
>  %118 = fmul float %69, %21
>  %119 = fadd float %118, %111
>  %120 = fmul float %69, %22
>  %121 = fadd float %120, %113
>  %122 = fmul float %70, %23
>  %123 = fadd float %122, %115
>  %124 = fmul float %70, %24
>  %125 = fadd float %124, %117
>  %126 = fmul float %70, %25
>  %127 = fadd float %126, %119
>  %128 = fmul float %70, %26
>  %129 = fadd float %128, %121
>  %130 = call float @llvm.AMDIL.clamp.(float %80, float 0.000000e+00, float 1.000000e+00)
>  %131 = call float @llvm.AMDIL.clamp.(float %81, float 0.000000e+00, float 1.000000e+00)
>  %132 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %133 = call float @llvm.AMDIL.clamp.(float %83, float 0.000000e+00, float 1.000000e+00)
>  %134 = fmul float %74, %27
>  %135 = fmul float %75, %28
>  %136 = fadd float %135, %134
>  %137 = fmul float %76, %29
>  %138 = fadd float %136, %137
>  %139 = fmul float %74, %30
>  %140 = fmul float %75, %31
>  %141 = fadd float %140, %139
>  %142 = fmul float %76, %32
>  %143 = fadd float %141, %142
>  %144 = fmul float %74, %33
>  %145 = fmul float %75, %34
>  %146 = fadd float %145, %144
>  %147 = fmul float %76, %35
>  %148 = fadd float %146, %147
>  %149 = fmul float %138, %138
>  %150 = fmul float %143, %143
>  %151 = fadd float %150, %149
>  %152 = fmul float %148, %148
>  %153 = fadd float %151, %152
>  %154 = call float @fabs(float %153)
>  %155 = call float @llvm.AMDGPU.rsq(float %154)
>  %156 = fmul float %138, %155
>  %157 = fmul float %143, %155
>  %158 = fmul float %148, %155
>  %159 = fmul float %67, %36
>  %160 = fmul float %67, %37
>  %161 = fmul float %67, %38
>  %162 = fmul float %68, %39
>  %163 = fadd float %162, %159
>  %164 = fmul float %68, %40
>  %165 = fadd float %164, %160
>  %166 = fmul float %68, %41
>  %167 = fadd float %166, %161
>  %168 = fmul float %69, %42
>  %169 = fadd float %168, %163
>  %170 = fmul float %69, %43
>  %171 = fadd float %170, %165
>  %172 = fmul float %69, %44
>  %173 = fadd float %172, %167
>  %174 = fmul float %70, %45
>  %175 = fadd float %174, %169
>  %176 = fmul float %70, %46
>  %177 = fadd float %176, %171
>  %178 = fmul float %70, %47
>  %179 = fadd float %178, %173
>  %180 = fmul float %175, %175
>  %181 = fmul float %177, %177
>  %182 = fadd float %181, %180
>  %183 = fmul float %179, %179
>  %184 = fadd float %182, %183
>  %185 = call float @fabs(float %184)
>  %186 = call float @llvm.AMDGPU.rsq(float %185)
>  %187 = fmul float %175, %186
>  %188 = fmul float %177, %186
>  %189 = fmul float %179, %186
>  %190 = fmul float %156, %187
>  %191 = fmul float %157, %188
>  %192 = fadd float %191, %190
>  %193 = fmul float %158, %189
>  %194 = fadd float %192, %193
>  %195 = fadd float %194, %194
>  %196 = fadd float %194, %194
>  %197 = fadd float %194, %194
>  %198 = fsub float -0.000000e+00, %195
>  %199 = fmul float %198, %156
>  %200 = fadd float %199, %187
>  %201 = fsub float -0.000000e+00, %196
>  %202 = fmul float %201, %157
>  %203 = fadd float %202, %188
>  %204 = fsub float -0.000000e+00, %197
>  %205 = fmul float %204, %158
>  %206 = fadd float %205, %189
>  %207 = fmul float %200, %48
>  %208 = fmul float %200, %49
>  %209 = fmul float %200, %50
>  %210 = fmul float %200, %51
>  %211 = fmul float %203, %52
>  %212 = fadd float %211, %207
>  %213 = fmul float %203, %53
>  %214 = fadd float %213, %208
>  %215 = fmul float %203, %54
>  %216 = fadd float %215, %209
>  %217 = fmul float %203, %55
>  %218 = fadd float %217, %210
>  %219 = fmul float %206, %56
>  %220 = fadd float %219, %212
>  %221 = fmul float %206, %57
>  %222 = fadd float %221, %214
>  %223 = fmul float %206, %58
>  %224 = fadd float %223, %216
>  %225 = fmul float %206, %59
>  %226 = fadd float %225, %218
>  %227 = fmul float %101, %60
>  %228 = fadd float %227, %220
>  %229 = fmul float %101, %61
>  %230 = fadd float %229, %222
>  %231 = fmul float %101, %62
>  %232 = fadd float %231, %224
>  %233 = fmul float %101, %63
>  %234 = fadd float %233, %226
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %130, float %131, float %132, float %133)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %87, float %88, float %89, float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %94, float %95, float %96, float %97)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %228, float %230, float %232, float %234)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %123, float %125, float %127, float %129)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0840710
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800022f
>04030201
>c0840704
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020114
>bf8c007f
>100a0204
>c2020115
>bf8c007f
>d2820005
>04140902
>c2020116
>bf8c007f
>d2820005
>04140903
>c2020110
>bf8c007f
>100c0204
>c2020111
>bf8c007f
>d2820006
>04180902
>c2020112
>bf8c007f
>d2820006
>04180903
>100e0d06
>d2820008
>041e0b05
>c2020118
>bf8c007f
>100e0204
>c2020119
>bf8c007f
>d2820007
>041c0902
>c202011a
>bf8c007f
>d2820007
>041c0903
>d2820001
>04220f07
>d2060101
>02010101
>7e105b01
>100c1106
>c0840700
>bf8c007f
>e00c2000
>80020100
>c202011d
>bf8c0070
>10120204
>c2020121
>bf8c007f
>d2820009
>04240902
>c2020125
>bf8c007f
>d2820009
>04240903
>c2020129
>bf8c007f
>d2820009
>04240904
>c202011c
>bf8c007f
>10140204
>c2020120
>bf8c007f
>d282000a
>04280902
>c2020124
>bf8c007f
>d282000a
>04280903
>c2020128
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c202011e
>bf8c007f
>10160204
>c2020122
>bf8c007f
>d282000b
>042c0902
>c2020126
>bf8c007f
>d282000b
>042c0903
>c202012a
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101c1506
>100a1105
>101a1909
>d2820009
>043a1b05
>100e1107
>1010190b
>d2820009
>04261107
>06121309
>100a0b09
>080a0b0d
>100c0d09
>080c0d0a
>c202012f
>bf8c007f
>10140c04
>c2020133
>bf8c007f
>d282000a
>04280905
>100e0f09
>080e0f08
>c2020137
>bf8c007f
>d282000c
>04280907
>c0820714
>bf8c007f
>e00c2000
>80010800
>c202013b
>bf8c0070
>d2820000
>0430090b
>c202012e
>bf8c007f
>10180c04
>c2020132
>bf8c007f
>d282000c
>04300905
>c2020136
>bf8c007f
>d282000c
>04300907
>c202013a
>bf8c007f
>d282000c
>0430090b
>c202012d
>bf8c007f
>101a0c04
>c2020131
>bf8c007f
>d282000d
>04340905
>c2020135
>bf8c007f
>d282000d
>04340907
>c2020139
>bf8c007f
>d282000d
>0434090b
>c202012c
>bf8c007f
>100c0c04
>c2020130
>bf8c007f
>d2820005
>04180905
>c2020134
>bf8c007f
>d2820005
>04140907
>c2020138
>bf8c007f
>d2820005
>0414090b
>f800023f
>000c0d05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..14]
>DCL TEMP[0..4]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[2]
>  5: MOV OUT[2], IN[3]
>  6: DP3 TEMP[1].x, IN[1], CONST[4]
>  7: DP3 TEMP[1].y, IN[1], CONST[5]
>  8: DP3 TEMP[1].z, IN[1], CONST[6]
>  9: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 10: RSQ TEMP[2].x, |TEMP[2]|
> 11: MUL TEMP[1], TEMP[1], TEMP[2].xxxx
> 12: MUL TEMP[2], IN[0].xxxx, CONST[7]
> 13: MAD TEMP[2], IN[0].yyyy, CONST[8], TEMP[2]
> 14: MAD TEMP[2], IN[0].zzzz, CONST[9], TEMP[2]
> 15: MAD TEMP[2], IN[0].wwww, CONST[10], TEMP[2]
> 16: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 17: RSQ TEMP[3].x, |TEMP[3]|
> 18: MUL TEMP[4], TEMP[2], TEMP[3].xxxx
> 19: DP3 TEMP[3], TEMP[1], TEMP[4]
> 20: ADD TEMP[3], TEMP[3], TEMP[3]
> 21: MAD TEMP[0].xyz, -TEMP[3], TEMP[1], TEMP[4]
> 22: MOV TEMP[0].w, IN[4]
> 23: MUL TEMP[3], TEMP[0].xxxx, CONST[11]
> 24: MAD TEMP[3], TEMP[0].yyyy, CONST[12], TEMP[3]
> 25: MAD TEMP[3], TEMP[0].zzzz, CONST[13], TEMP[3]
> 26: MAD OUT[3], TEMP[0].wwww, CONST[14], TEMP[3]
> 27: MOV OUT[4], IN[5]
> 28: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
>  %64 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
>  %66 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %65, i32 0, i32 %5)
>  %67 = extractelement <4 x float> %66, i32 0
>  %68 = extractelement <4 x float> %66, i32 1
>  %69 = extractelement <4 x float> %66, i32 2
>  %70 = extractelement <4 x float> %66, i32 3
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %78 = load <16 x i8> addrspace(2)* %77, !tbaa !0
>  %79 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %78, i32 0, i32 %5)
>  %80 = extractelement <4 x float> %79, i32 0
>  %81 = extractelement <4 x float> %79, i32 1
>  %82 = extractelement <4 x float> %79, i32 2
>  %83 = extractelement <4 x float> %79, i32 3
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = extractelement <4 x float> %86, i32 3
>  %91 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0
>  %93 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %92, i32 0, i32 %5)
>  %94 = extractelement <4 x float> %93, i32 3
>  %95 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %96 = load <16 x i8> addrspace(2)* %95, !tbaa !0
>  %97 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %96, i32 0, i32 %5)
>  %98 = extractelement <4 x float> %97, i32 0
>  %99 = extractelement <4 x float> %97, i32 1
>  %100 = extractelement <4 x float> %97, i32 2
>  %101 = extractelement <4 x float> %97, i32 3
>  %102 = fmul float %67, %11
>  %103 = fmul float %67, %12
>  %104 = fmul float %67, %13
>  %105 = fmul float %67, %14
>  %106 = fmul float %68, %15
>  %107 = fadd float %106, %102
>  %108 = fmul float %68, %16
>  %109 = fadd float %108, %103
>  %110 = fmul float %68, %17
>  %111 = fadd float %110, %104
>  %112 = fmul float %68, %18
>  %113 = fadd float %112, %105
>  %114 = fmul float %69, %19
>  %115 = fadd float %114, %107
>  %116 = fmul float %69, %20
>  %117 = fadd float %116, %109
>  %118 = fmul float %69, %21
>  %119 = fadd float %118, %111
>  %120 = fmul float %69, %22
>  %121 = fadd float %120, %113
>  %122 = fmul float %70, %23
>  %123 = fadd float %122, %115
>  %124 = fmul float %70, %24
>  %125 = fadd float %124, %117
>  %126 = fmul float %70, %25
>  %127 = fadd float %126, %119
>  %128 = fmul float %70, %26
>  %129 = fadd float %128, %121
>  %130 = call float @llvm.AMDIL.clamp.(float %80, float 0.000000e+00, float 1.000000e+00)
>  %131 = call float @llvm.AMDIL.clamp.(float %81, float 0.000000e+00, float 1.000000e+00)
>  %132 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %133 = call float @llvm.AMDIL.clamp.(float %83, float 0.000000e+00, float 1.000000e+00)
>  %134 = fmul float %74, %27
>  %135 = fmul float %75, %28
>  %136 = fadd float %135, %134
>  %137 = fmul float %76, %29
>  %138 = fadd float %136, %137
>  %139 = fmul float %74, %30
>  %140 = fmul float %75, %31
>  %141 = fadd float %140, %139
>  %142 = fmul float %76, %32
>  %143 = fadd float %141, %142
>  %144 = fmul float %74, %33
>  %145 = fmul float %75, %34
>  %146 = fadd float %145, %144
>  %147 = fmul float %76, %35
>  %148 = fadd float %146, %147
>  %149 = fmul float %138, %138
>  %150 = fmul float %143, %143
>  %151 = fadd float %150, %149
>  %152 = fmul float %148, %148
>  %153 = fadd float %151, %152
>  %154 = call float @fabs(float %153)
>  %155 = call float @llvm.AMDGPU.rsq(float %154)
>  %156 = fmul float %138, %155
>  %157 = fmul float %143, %155
>  %158 = fmul float %148, %155
>  %159 = fmul float %67, %36
>  %160 = fmul float %67, %37
>  %161 = fmul float %67, %38
>  %162 = fmul float %68, %39
>  %163 = fadd float %162, %159
>  %164 = fmul float %68, %40
>  %165 = fadd float %164, %160
>  %166 = fmul float %68, %41
>  %167 = fadd float %166, %161
>  %168 = fmul float %69, %42
>  %169 = fadd float %168, %163
>  %170 = fmul float %69, %43
>  %171 = fadd float %170, %165
>  %172 = fmul float %69, %44
>  %173 = fadd float %172, %167
>  %174 = fmul float %70, %45
>  %175 = fadd float %174, %169
>  %176 = fmul float %70, %46
>  %177 = fadd float %176, %171
>  %178 = fmul float %70, %47
>  %179 = fadd float %178, %173
>  %180 = fmul float %175, %175
>  %181 = fmul float %177, %177
>  %182 = fadd float %181, %180
>  %183 = fmul float %179, %179
>  %184 = fadd float %182, %183
>  %185 = call float @fabs(float %184)
>  %186 = call float @llvm.AMDGPU.rsq(float %185)
>  %187 = fmul float %175, %186
>  %188 = fmul float %177, %186
>  %189 = fmul float %179, %186
>  %190 = fmul float %156, %187
>  %191 = fmul float %157, %188
>  %192 = fadd float %191, %190
>  %193 = fmul float %158, %189
>  %194 = fadd float %192, %193
>  %195 = fadd float %194, %194
>  %196 = fadd float %194, %194
>  %197 = fadd float %194, %194
>  %198 = fsub float -0.000000e+00, %195
>  %199 = fmul float %198, %156
>  %200 = fadd float %199, %187
>  %201 = fsub float -0.000000e+00, %196
>  %202 = fmul float %201, %157
>  %203 = fadd float %202, %188
>  %204 = fsub float -0.000000e+00, %197
>  %205 = fmul float %204, %158
>  %206 = fadd float %205, %189
>  %207 = fmul float %200, %48
>  %208 = fmul float %200, %49
>  %209 = fmul float %200, %50
>  %210 = fmul float %200, %51
>  %211 = fmul float %203, %52
>  %212 = fadd float %211, %207
>  %213 = fmul float %203, %53
>  %214 = fadd float %213, %208
>  %215 = fmul float %203, %54
>  %216 = fadd float %215, %209
>  %217 = fmul float %203, %55
>  %218 = fadd float %217, %210
>  %219 = fmul float %206, %56
>  %220 = fadd float %219, %212
>  %221 = fmul float %206, %57
>  %222 = fadd float %221, %214
>  %223 = fmul float %206, %58
>  %224 = fadd float %223, %216
>  %225 = fmul float %206, %59
>  %226 = fadd float %225, %218
>  %227 = fmul float %94, %60
>  %228 = fadd float %227, %220
>  %229 = fmul float %94, %61
>  %230 = fadd float %229, %222
>  %231 = fmul float %94, %62
>  %232 = fadd float %231, %224
>  %233 = fmul float %94, %63
>  %234 = fadd float %233, %226
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %130, float %131, float %132, float %133)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %87, float %88, float %89, float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %228, float %230, float %232, float %234)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %98, float %99, float %100, float %101)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %123, float %125, float %127, float %129)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0840704
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020114
>bf8c007f
>100a0204
>c2020115
>bf8c007f
>d2820005
>04140902
>c2020116
>bf8c007f
>d2820005
>04140903
>c2020110
>bf8c007f
>100c0204
>c2020111
>bf8c007f
>d2820006
>04180902
>c2020112
>bf8c007f
>d2820006
>04180903
>100e0d06
>d2820008
>041e0b05
>c2020118
>bf8c007f
>100e0204
>c2020119
>bf8c007f
>d2820007
>041c0902
>c202011a
>bf8c007f
>d2820007
>041c0903
>d2820001
>04220f07
>d2060101
>02010101
>7e105b01
>100c1106
>c0840700
>bf8c007f
>e00c2000
>80020100
>c202011d
>bf8c0070
>10120204
>c2020121
>bf8c007f
>d2820009
>04240902
>c2020125
>bf8c007f
>d2820009
>04240903
>c2020129
>bf8c007f
>d2820009
>04240904
>c202011c
>bf8c007f
>10140204
>c2020120
>bf8c007f
>d282000a
>04280902
>c2020124
>bf8c007f
>d282000a
>04280903
>c2020128
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c202011e
>bf8c007f
>10160204
>c2020122
>bf8c007f
>d282000b
>042c0902
>c2020126
>bf8c007f
>d282000b
>042c0903
>c202012a
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101c1506
>100a1105
>101a1909
>d2820009
>043a1b05
>100e1107
>1010190b
>d2820009
>04261107
>06121309
>100a0b09
>080a0b0d
>100c0d09
>080c0d0a
>c202012f
>bf8c007f
>10140c04
>c2020133
>bf8c007f
>d282000a
>04280905
>100e0f09
>080e0f08
>c2020137
>bf8c007f
>d282000c
>04280907
>c0840710
>bf8c007f
>e00c2000
>80020800
>c202013b
>bf8c0070
>d282000c
>0430090b
>c202012e
>bf8c007f
>101a0c04
>c2020132
>bf8c007f
>d282000d
>04340905
>c2020136
>bf8c007f
>d282000d
>04340907
>c202013a
>bf8c007f
>d282000d
>0434090b
>c202012d
>bf8c007f
>101c0c04
>c2020131
>bf8c007f
>d282000e
>04380905
>c2020135
>bf8c007f
>d282000e
>04380907
>c2020139
>bf8c007f
>d282000e
>0438090b
>c202012c
>bf8c007f
>100c0c04
>c2020130
>bf8c007f
>d2820005
>04180905
>c2020134
>bf8c007f
>d2820005
>04140907
>c2020138
>bf8c007f
>d2820005
>0414090b
>f800022f
>0c0d0e05
>c0820714
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[1], PERSPECTIVE
>DCL IN[1], GENERIC[2], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2]
>DCL TEMP[0..1], LOCAL
>  0: TXP TEMP[0], IN[0], SAMP[1], CUBE
>  1: MUL TEMP[0].xyz, TEMP[0], CONST[2]
>  2: MOV TEMP[0].xyz, TEMP[0].xyzx
>  3: MOV TEMP[1].xy, IN[1].xyyy
>  4: MOV TEMP[1].w, IN[1].wwww
>  5: TXP TEMP[1].w, TEMP[1], SAMP[0], 2D
>  6: MOV TEMP[0].w, TEMP[1].wwww
>  7: MOV OUT[0], TEMP[0]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %25 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %26 = load <32 x i8> addrspace(2)* %25, !tbaa !0
>  %27 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %30 = load <32 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %40 = fdiv float %33, %36
>  %41 = fdiv float %34, %36
>  %42 = fdiv float %35, %36
>  %43 = insertelement <4 x float> undef, float %40, i32 0
>  %44 = insertelement <4 x float> %43, float %41, i32 1
>  %45 = insertelement <4 x float> %44, float %42, i32 2
>  %46 = insertelement <4 x float> %45, float 1.000000e+00, i32 3
>  %47 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %46)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = call float @fabs(float %50)
>  %53 = fdiv float 1.000000e+00, %52
>  %54 = fmul float %48, %53
>  %55 = fadd float %54, 1.500000e+00
>  %56 = fmul float %49, %53
>  %57 = fadd float %56, 1.500000e+00
>  %58 = bitcast float %57 to i32
>  %59 = bitcast float %55 to i32
>  %60 = bitcast float %51 to i32
>  %61 = insertelement <4 x i32> undef, i32 %58, i32 0
>  %62 = insertelement <4 x i32> %61, i32 %59, i32 1
>  %63 = insertelement <4 x i32> %62, i32 %60, i32 2
>  %64 = insertelement <4 x i32> %63, i32 undef, i32 3
>  %65 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %64, <32 x i8> %30, <16 x i8> %32, i32 4)
>  %66 = extractelement <4 x float> %65, i32 0
>  %67 = extractelement <4 x float> %65, i32 1
>  %68 = extractelement <4 x float> %65, i32 2
>  %69 = fmul float %66, %22
>  %70 = fmul float %67, %23
>  %71 = fmul float %68, %24
>  %72 = fdiv float %37, %39
>  %73 = fdiv float %38, %39
>  %74 = bitcast float %72 to i32
>  %75 = bitcast float %73 to i32
>  %76 = insertelement <2 x i32> undef, i32 %74, i32 0
>  %77 = insertelement <2 x i32> %76, i32 %75, i32 1
>  %78 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %77, <32 x i8> %26, <16 x i8> %28, i32 2)
>  %79 = extractelement <4 x float> %78, i32 3
>  %80 = call i32 @llvm.SI.packf16(float %69, float %70)
>  %81 = bitcast i32 %80 to float
>  %82 = call i32 @llvm.SI.packf16(float %71, float %79)
>  %83 = bitcast i32 %82 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %81, float %83, float %81, float %83)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0300
>c80d0301
>7e0c5503
>10060d02
>c81c0000
>c81d0001
>10040d07
>c81c0200
>c81d0201
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c0840304
>c0c60508
>bf8c007f
>f0800700
>00430307
>c0840100
>bf8c0070
>c2000909
>bf8c007f
>10040800
>c2000908
>bf8c007f
>100c0600
>5e040506
>c200090a
>bf8c007f
>10060a00
>c8100500
>c8110501
>c8140700
>c8150701
>7e0c5505
>100a0d04
>c81c0400
>c81d0401
>10080d07
>c0800300
>c0c20500
>bf8c007f
>f0800800
>00010004
>bf8c0770
>5e000103
>f8001c0f
>00020002
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[1]
>DCL OUT[2], GENERIC[2]
>DCL CONST[0..10]
>DCL TEMP[0..3]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MUL TEMP[1], IN[0].xxxx, CONST[7]
> 11: MAD TEMP[1], IN[0].yyyy, CONST[8], TEMP[1]
> 12: MAD TEMP[1], IN[0].zzzz, CONST[9], TEMP[1]
> 13: MAD TEMP[1], IN[0].wwww, CONST[10], TEMP[1]
> 14: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 15: RSQ TEMP[2].x, |TEMP[2]|
> 16: MUL TEMP[3], TEMP[1], TEMP[2].xxxx
> 17: DP3 TEMP[2], TEMP[0], TEMP[3]
> 18: ADD TEMP[2], TEMP[2], TEMP[2]
> 19: MAD OUT[1].xyz, -TEMP[2], TEMP[0], TEMP[3]
> 20: MOV OUT[1].w, IN[2]
> 21: MOV OUT[2], IN[3]
> 22: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %48 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %5)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = extractelement <4 x float> %50, i32 3
>  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
>  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
>  %58 = extractelement <4 x float> %57, i32 0
>  %59 = extractelement <4 x float> %57, i32 1
>  %60 = extractelement <4 x float> %57, i32 2
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 3
>  %65 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %66 = load <16 x i8> addrspace(2)* %65, !tbaa !0
>  %67 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %66, i32 0, i32 %5)
>  %68 = extractelement <4 x float> %67, i32 0
>  %69 = extractelement <4 x float> %67, i32 1
>  %70 = extractelement <4 x float> %67, i32 2
>  %71 = extractelement <4 x float> %67, i32 3
>  %72 = fmul float %51, %11
>  %73 = fmul float %51, %12
>  %74 = fmul float %51, %13
>  %75 = fmul float %51, %14
>  %76 = fmul float %52, %15
>  %77 = fadd float %76, %72
>  %78 = fmul float %52, %16
>  %79 = fadd float %78, %73
>  %80 = fmul float %52, %17
>  %81 = fadd float %80, %74
>  %82 = fmul float %52, %18
>  %83 = fadd float %82, %75
>  %84 = fmul float %53, %19
>  %85 = fadd float %84, %77
>  %86 = fmul float %53, %20
>  %87 = fadd float %86, %79
>  %88 = fmul float %53, %21
>  %89 = fadd float %88, %81
>  %90 = fmul float %53, %22
>  %91 = fadd float %90, %83
>  %92 = fmul float %54, %23
>  %93 = fadd float %92, %85
>  %94 = fmul float %54, %24
>  %95 = fadd float %94, %87
>  %96 = fmul float %54, %25
>  %97 = fadd float %96, %89
>  %98 = fmul float %54, %26
>  %99 = fadd float %98, %91
>  %100 = fmul float %58, %27
>  %101 = fmul float %59, %28
>  %102 = fadd float %101, %100
>  %103 = fmul float %60, %29
>  %104 = fadd float %102, %103
>  %105 = fmul float %58, %30
>  %106 = fmul float %59, %31
>  %107 = fadd float %106, %105
>  %108 = fmul float %60, %32
>  %109 = fadd float %107, %108
>  %110 = fmul float %58, %33
>  %111 = fmul float %59, %34
>  %112 = fadd float %111, %110
>  %113 = fmul float %60, %35
>  %114 = fadd float %112, %113
>  %115 = fmul float %104, %104
>  %116 = fmul float %109, %109
>  %117 = fadd float %116, %115
>  %118 = fmul float %114, %114
>  %119 = fadd float %117, %118
>  %120 = call float @fabs(float %119)
>  %121 = call float @llvm.AMDGPU.rsq(float %120)
>  %122 = fmul float %104, %121
>  %123 = fmul float %109, %121
>  %124 = fmul float %114, %121
>  %125 = fmul float %51, %36
>  %126 = fmul float %51, %37
>  %127 = fmul float %51, %38
>  %128 = fmul float %52, %39
>  %129 = fadd float %128, %125
>  %130 = fmul float %52, %40
>  %131 = fadd float %130, %126
>  %132 = fmul float %52, %41
>  %133 = fadd float %132, %127
>  %134 = fmul float %53, %42
>  %135 = fadd float %134, %129
>  %136 = fmul float %53, %43
>  %137 = fadd float %136, %131
>  %138 = fmul float %53, %44
>  %139 = fadd float %138, %133
>  %140 = fmul float %54, %45
>  %141 = fadd float %140, %135
>  %142 = fmul float %54, %46
>  %143 = fadd float %142, %137
>  %144 = fmul float %54, %47
>  %145 = fadd float %144, %139
>  %146 = fmul float %141, %141
>  %147 = fmul float %143, %143
>  %148 = fadd float %147, %146
>  %149 = fmul float %145, %145
>  %150 = fadd float %148, %149
>  %151 = call float @fabs(float %150)
>  %152 = call float @llvm.AMDGPU.rsq(float %151)
>  %153 = fmul float %141, %152
>  %154 = fmul float %143, %152
>  %155 = fmul float %145, %152
>  %156 = fmul float %122, %153
>  %157 = fmul float %123, %154
>  %158 = fadd float %157, %156
>  %159 = fmul float %124, %155
>  %160 = fadd float %158, %159
>  %161 = fadd float %160, %160
>  %162 = fadd float %160, %160
>  %163 = fadd float %160, %160
>  %164 = fsub float -0.000000e+00, %161
>  %165 = fmul float %164, %122
>  %166 = fadd float %165, %153
>  %167 = fsub float -0.000000e+00, %162
>  %168 = fmul float %167, %123
>  %169 = fadd float %168, %154
>  %170 = fsub float -0.000000e+00, %163
>  %171 = fmul float %170, %124
>  %172 = fadd float %171, %155
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %166, float %169, float %172, float %64)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %68, float %69, float %70, float %71)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %93, float %95, float %97, float %99)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020114
>bf8c007f
>100a0204
>c2020115
>bf8c007f
>d2820005
>04140902
>c2020116
>bf8c007f
>d2820005
>04140903
>c2020110
>bf8c007f
>100c0204
>c2020111
>bf8c007f
>d2820006
>04180902
>c2020112
>bf8c007f
>d2820006
>04180903
>100e0d06
>d2820008
>041e0b05
>c2020118
>bf8c007f
>100e0204
>c2020119
>bf8c007f
>d2820007
>041c0902
>c202011a
>bf8c007f
>d2820007
>041c0903
>d2820001
>04220f07
>d2060101
>02010101
>7e105b01
>100c1106
>c0840700
>bf8c007f
>e00c2000
>80020100
>c202011d
>bf8c0070
>10120204
>c2020121
>bf8c007f
>d2820009
>04240902
>c2020125
>bf8c007f
>d2820009
>04240903
>c2020129
>bf8c007f
>d2820009
>04240904
>c202011c
>bf8c007f
>10140204
>c2020120
>bf8c007f
>d282000a
>04280902
>c2020124
>bf8c007f
>d282000a
>04280903
>c2020128
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c202011e
>bf8c007f
>10160204
>c2020122
>bf8c007f
>d282000b
>042c0902
>c2020126
>bf8c007f
>d282000b
>042c0903
>c202012a
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101a1506
>100a1105
>10121909
>d282000d
>04361305
>100e1107
>1016190b
>d2820008
>04361707
>06101108
>100e0f08
>080e0f0b
>100a0b08
>080a0b09
>100c0d08
>080c0d0a
>c0840708
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800020f
>0b070506
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV TEMP[1].xy, IN[2].xyyy
>  5: MOV TEMP[1].w, IN[2].wwww
>  6: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  7: MUL_SAT TEMP[2], TEMP[0], IMM[0].xxxy
>  8: MUL TEMP[1].xyz, TEMP[1], TEMP[2]
>  9: MOV TEMP[1].xyz, TEMP[1].xyzx
> 10: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
> 11: MOV TEMP[1].w, TEMP[0].wwww
> 12: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
> 13: MOV OUT[0], TEMP[0]
> 14: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %38 = fdiv float %32, %34
>  %39 = fdiv float %33, %34
>  %40 = bitcast float %38 to i32
>  %41 = bitcast float %39 to i32
>  %42 = insertelement <2 x i32> undef, i32 %40, i32 0
>  %43 = insertelement <2 x i32> %42, i32 %41, i32 1
>  %44 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %43, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = extractelement <4 x float> %44, i32 1
>  %47 = extractelement <4 x float> %44, i32 2
>  %48 = extractelement <4 x float> %44, i32 3
>  %49 = fmul float %45, %28
>  %50 = fmul float %46, %29
>  %51 = fmul float %47, %30
>  %52 = fmul float %48, %31
>  %53 = fdiv float %35, %37
>  %54 = fdiv float %36, %37
>  %55 = bitcast float %53 to i32
>  %56 = bitcast float %54 to i32
>  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
>  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
>  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = fmul float %49, 2.000000e+00
>  %64 = fmul float %50, 2.000000e+00
>  %65 = fmul float %51, 2.000000e+00
>  %66 = fmul float %52, 1.000000e+00
>  %67 = call float @llvm.AMDIL.clamp.(float %63, float 0.000000e+00, float 1.000000e+00)
>  %68 = call float @llvm.AMDIL.clamp.(float %64, float 0.000000e+00, float 1.000000e+00)
>  %69 = call float @llvm.AMDIL.clamp.(float %65, float 0.000000e+00, float 1.000000e+00)
>  %70 = call float @llvm.AMDIL.clamp.(float %66, float 0.000000e+00, float 1.000000e+00)
>  %71 = fmul float %60, %67
>  %72 = fmul float %61, %68
>  %73 = fmul float %62, %69
>  %74 = fmul float %49, 2.000000e+00
>  %75 = fmul float %50, 2.000000e+00
>  %76 = fmul float %51, 2.000000e+00
>  %77 = fmul float %52, 1.000000e+00
>  %78 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %75, float 0.000000e+00, float 1.000000e+00)
>  %80 = call float @llvm.AMDIL.clamp.(float %76, float 0.000000e+00, float 1.000000e+00)
>  %81 = call float @llvm.AMDIL.clamp.(float %77, float 0.000000e+00, float 1.000000e+00)
>  %82 = fmul float %71, 2.000000e+00
>  %83 = fmul float %72, 2.000000e+00
>  %84 = fmul float %73, 2.000000e+00
>  %85 = fmul float %81, 1.000000e+00
>  %86 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %87 = call float @llvm.AMDIL.clamp.(float %83, float 0.000000e+00, float 1.000000e+00)
>  %88 = call float @llvm.AMDIL.clamp.(float %84, float 0.000000e+00, float 1.000000e+00)
>  %89 = call float @llvm.AMDIL.clamp.(float %85, float 0.000000e+00, float 1.000000e+00)
>  %90 = fcmp ugt float %89, 0x3FDFDFDFE0000000
>  %91 = sext i1 %90 to i32
>  %92 = trunc i32 %91 to i1
>  %93 = select i1 %92, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %93)
>  %94 = call i32 @llvm.SI.packf16(float %86, float %87)
>  %95 = bitcast i32 %94 to float
>  %96 = call i32 @llvm.SI.packf16(float %88, float %89)
>  %97 = bitcast i32 %96 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %95, float %97, float %95, float %97)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>d2060806
>02010106
>d2060806
>02010106
>7e0e02ff
>3efefeff
>d0080000
>02020f06
>d2000007
>0001e4f3
>7c260e80
>c81c0100
>c81d0101
>10100f03
>d2820007
>04220f03
>d206080a
>02010107
>c81c0900
>c81d0901
>c8200b00
>c8210b01
>7e125508
>10101307
>c82c0800
>c82d0801
>100e130b
>c0800300
>c0c40500
>bf8c007f
>f0800700
>00020707
>bf8c0770
>10161508
>d282000a
>042e1508
>d206080a
>0201010a
>c82c0000
>c82d0001
>10181702
>d282000b
>04321702
>d206080b
>0201010b
>10181707
>d282000b
>04321707
>d206080b
>0201010b
>5e14150b
>c82c0200
>c82d0201
>10001704
>d2820000
>04021704
>d2060800
>02010100
>10020109
>d2820000
>04060109
>d2060800
>02010100
>5e000d00
>f8001c0f
>000a000a
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL IN[3], GENERIC[2], PERSPECTIVE
>DCL IN[4], GENERIC[3], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL CONST[4..8]
>DCL TEMP[0..4], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[4].xyyy
>  1: MOV TEMP[0].w, IN[4].wwww
>  2: TXP TEMP[0].w, TEMP[0], SAMP[0], 2D
>  3: MOV TEMP[1].xy, IN[1].xyyy
>  4: MOV TEMP[1].w, IN[1].wwww
>  5: TXP TEMP[1].xyz, TEMP[1], SAMP[3], 2D
>  6: MOV TEMP[1].xyz, TEMP[1].xyzx
>  7: MOV TEMP[2].xy, IN[2].xyyy
>  8: MOV TEMP[2].w, IN[2].wwww
>  9: TXP TEMP[2].w, TEMP[2], SAMP[2], 2D
> 10: MOV TEMP[1].w, TEMP[2].wwww
> 11: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].wwww
> 12: TXP TEMP[4], IN[3], SAMP[1], CUBE
> 13: MUL TEMP[4], TEMP[4], TEMP[2].wwww
> 14: MAD TEMP[1].xyz, TEMP[1], TEMP[3].xxxx, TEMP[4]
> 15: MOV TEMP[1].xyz, TEMP[1].xyzx
> 16: MOV TEMP[1].w, TEMP[2].wwww
> 17: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[0].wwww
> 18: MUL TEMP[0], TEMP[1], TEMP[0].wwww
> 19: MAD TEMP[0].xyz, CONST[7], TEMP[3].xxxx, TEMP[0]
> 20: MOV TEMP[0].xyz, TEMP[0].xyzx
> 21: MOV TEMP[0].w, TEMP[2].wwww
> 22: ADD TEMP[1].x, IMM[0].xxxx, -IN[0].wwww
> 23: MUL TEMP[0], TEMP[0], IN[0].wwww
> 24: MAD TEMP[0].xyz, CONST[8], TEMP[1].xxxx, TEMP[0]
> 25: MOV TEMP[0].xyz, TEMP[0].xyzx
> 26: MOV TEMP[0].w, TEMP[2].wwww
> 27: MOV OUT[0], TEMP[0]
> 28: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 116)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 120)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 136)
>  %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %33 = load <32 x i8> addrspace(2)* %32, !tbaa !0
>  %34 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %37 = load <32 x i8> addrspace(2)* %36, !tbaa !0
>  %38 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
>  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
>  %42 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
>  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
>  %44 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %46 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %47 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %48 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %49 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %50 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %51 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %52 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %53 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
>  %54 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %55 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %56 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %57 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %58 = fdiv float %55, %57
>  %59 = fdiv float %56, %57
>  %60 = bitcast float %58 to i32
>  %61 = bitcast float %59 to i32
>  %62 = insertelement <2 x i32> undef, i32 %60, i32 0
>  %63 = insertelement <2 x i32> %62, i32 %61, i32 1
>  %64 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %63, <32 x i8> %29, <16 x i8> %31, i32 2)
>  %65 = extractelement <4 x float> %64, i32 3
>  %66 = fdiv float %45, %47
>  %67 = fdiv float %46, %47
>  %68 = bitcast float %66 to i32
>  %69 = bitcast float %67 to i32
>  %70 = insertelement <2 x i32> undef, i32 %68, i32 0
>  %71 = insertelement <2 x i32> %70, i32 %69, i32 1
>  %72 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %71, <32 x i8> %41, <16 x i8> %43, i32 2)
>  %73 = extractelement <4 x float> %72, i32 0
>  %74 = extractelement <4 x float> %72, i32 1
>  %75 = extractelement <4 x float> %72, i32 2
>  %76 = fdiv float %48, %50
>  %77 = fdiv float %49, %50
>  %78 = bitcast float %76 to i32
>  %79 = bitcast float %77 to i32
>  %80 = insertelement <2 x i32> undef, i32 %78, i32 0
>  %81 = insertelement <2 x i32> %80, i32 %79, i32 1
>  %82 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %81, <32 x i8> %37, <16 x i8> %39, i32 2)
>  %83 = extractelement <4 x float> %82, i32 3
>  %84 = fsub float -0.000000e+00, %83
>  %85 = fadd float 1.000000e+00, %84
>  %86 = fdiv float %51, %54
>  %87 = fdiv float %52, %54
>  %88 = fdiv float %53, %54
>  %89 = insertelement <4 x float> undef, float %86, i32 0
>  %90 = insertelement <4 x float> %89, float %87, i32 1
>  %91 = insertelement <4 x float> %90, float %88, i32 2
>  %92 = insertelement <4 x float> %91, float 1.000000e+00, i32 3
>  %93 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %92)
>  %94 = extractelement <4 x float> %93, i32 0
>  %95 = extractelement <4 x float> %93, i32 1
>  %96 = extractelement <4 x float> %93, i32 2
>  %97 = extractelement <4 x float> %93, i32 3
>  %98 = call float @fabs(float %96)
>  %99 = fdiv float 1.000000e+00, %98
>  %100 = fmul float %94, %99
>  %101 = fadd float %100, 1.500000e+00
>  %102 = fmul float %95, %99
>  %103 = fadd float %102, 1.500000e+00
>  %104 = bitcast float %103 to i32
>  %105 = bitcast float %101 to i32
>  %106 = bitcast float %97 to i32
>  %107 = insertelement <4 x i32> undef, i32 %104, i32 0
>  %108 = insertelement <4 x i32> %107, i32 %105, i32 1
>  %109 = insertelement <4 x i32> %108, i32 %106, i32 2
>  %110 = insertelement <4 x i32> %109, i32 undef, i32 3
>  %111 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %110, <32 x i8> %33, <16 x i8> %35, i32 4)
>  %112 = extractelement <4 x float> %111, i32 0
>  %113 = extractelement <4 x float> %111, i32 1
>  %114 = extractelement <4 x float> %111, i32 2
>  %115 = fmul float %112, %83
>  %116 = fmul float %113, %83
>  %117 = fmul float %114, %83
>  %118 = fmul float %73, %85
>  %119 = fadd float %118, %115
>  %120 = fmul float %74, %85
>  %121 = fadd float %120, %116
>  %122 = fmul float %75, %85
>  %123 = fadd float %122, %117
>  %124 = fsub float -0.000000e+00, %65
>  %125 = fadd float 1.000000e+00, %124
>  %126 = fmul float %119, %65
>  %127 = fmul float %121, %65
>  %128 = fmul float %123, %65
>  %129 = fmul float %22, %125
>  %130 = fadd float %129, %126
>  %131 = fmul float %23, %125
>  %132 = fadd float %131, %127
>  %133 = fmul float %24, %125
>  %134 = fadd float %133, %128
>  %135 = fsub float -0.000000e+00, %44
>  %136 = fadd float 1.000000e+00, %135
>  %137 = fmul float %130, %44
>  %138 = fmul float %132, %44
>  %139 = fmul float %134, %44
>  %140 = fmul float %25, %136
>  %141 = fadd float %140, %137
>  %142 = fmul float %26, %136
>  %143 = fadd float %142, %138
>  %144 = fmul float %27, %136
>  %145 = fadd float %144, %139
>  %146 = call i32 @llvm.SI.packf16(float %141, float %143)
>  %147 = bitcast i32 %146 to float
>  %148 = call i32 @llvm.SI.packf16(float %145, float %83)
>  %149 = bitcast i32 %148 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %147, float %149, float %147, float %149)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080d00
>c8090d01
>c80c0f00
>c80d0f01
>7e0c5503
>10060d02
>c81c0c00
>c81d0c01
>10040d07
>c81c0e00
>c81d0e01
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c0840304
>c0c60508
>bf8c007f
>f0800700
>00430207
>c8140900
>c8150901
>c8180b00
>c8190b01
>7e0e5506
>100c0f05
>c8200800
>c8210801
>100a0f08
>c0840308
>c0c60510
>bf8c0070
>f0800800
>00430505
>bf8c0770
>10140b03
>c8180500
>c8190501
>c81c0700
>c81d0701
>7e105507
>100e1106
>c8240400
>c8250401
>100c1109
>c084030c
>c0c60518
>bf8c007f
>f0800700
>00430606
>08120af2
>bf8c0770
>d282000b
>042a1307
>c8281100
>c8291101
>c8301300
>c8311301
>7e1c550c
>101a1d0a
>c8281000
>c8291001
>10181d0a
>c0840300
>c0c60500
>bf8c007f
>f0800800
>00430a0c
>bf8c0770
>1018150b
>081614f2
>c0800100
>bf8c007f
>c202011d
>bf8c007f
>d282000d
>04321604
>c8300300
>c8310301
>1002190d
>080018f2
>c2020121
>bf8c007f
>d2820001
>04060004
>101a0b02
>d282000d
>04361306
>101a150d
>c202011c
>bf8c007f
>d282000d
>04361604
>101a190d
>c2020120
>bf8c007f
>d282000d
>04360004
>5e02030d
>10040b04
>d2820002
>040a1308
>10041502
>c202011e
>bf8c007f
>d2820002
>040a1604
>10041902
>c2000122
>bf8c007f
>d2820000
>040a0000
>5e000b00
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL OUT[5], GENERIC[3]
>DCL CONST[0..23]
>DCL TEMP[0..4]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
>  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
>  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
>  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
>  9: MUL TEMP[0], IN[3].xxxx, CONST[8]
> 10: MAD TEMP[0], IN[3].yyyy, CONST[9], TEMP[0]
> 11: MAD TEMP[0], IN[3].zzzz, CONST[10], TEMP[0]
> 12: MAD OUT[3], IN[3].wwww, CONST[11], TEMP[0]
> 13: DP3 TEMP[1].x, CONST[12], CONST[13]
> 14: DP3 TEMP[1].y, CONST[12], CONST[14]
> 15: DP3 TEMP[1].z, CONST[12], CONST[15]
> 16: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 17: RSQ TEMP[2].x, |TEMP[2]|
> 18: MUL TEMP[1], TEMP[1], TEMP[2].xxxx
> 19: MUL TEMP[2], IN[0].xxxx, CONST[16]
> 20: MAD TEMP[2], IN[0].yyyy, CONST[17], TEMP[2]
> 21: MAD TEMP[2], IN[0].zzzz, CONST[18], TEMP[2]
> 22: MAD TEMP[2], IN[0].wwww, CONST[19], TEMP[2]
> 23: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 24: RSQ TEMP[3].x, |TEMP[3]|
> 25: MUL TEMP[4], TEMP[2], TEMP[3].xxxx
> 26: DP3 TEMP[3], TEMP[1], TEMP[4]
> 27: ADD TEMP[3], TEMP[3], TEMP[3]
> 28: MAD TEMP[0].xyz, -TEMP[3], TEMP[1], TEMP[4]
> 29: MOV TEMP[0].w, IN[4]
> 30: MUL TEMP[3], TEMP[0].xxxx, CONST[20]
> 31: MAD TEMP[3], TEMP[0].yyyy, CONST[21], TEMP[3]
> 32: MAD TEMP[3], TEMP[0].zzzz, CONST[22], TEMP[3]
> 33: MAD OUT[4], TEMP[0].wwww, CONST[23], TEMP[3]
> 34: MOV OUT[5], IN[5]
> 35: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %99 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %100 = load <16 x i8> addrspace(2)* %99, !tbaa !0
>  %101 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %100, i32 0, i32 %5)
>  %102 = extractelement <4 x float> %101, i32 0
>  %103 = extractelement <4 x float> %101, i32 1
>  %104 = extractelement <4 x float> %101, i32 2
>  %105 = extractelement <4 x float> %101, i32 3
>  %106 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %107 = load <16 x i8> addrspace(2)* %106, !tbaa !0
>  %108 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %107, i32 0, i32 %5)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = extractelement <4 x float> %108, i32 1
>  %111 = extractelement <4 x float> %108, i32 2
>  %112 = extractelement <4 x float> %108, i32 3
>  %113 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %114 = load <16 x i8> addrspace(2)* %113, !tbaa !0
>  %115 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %114, i32 0, i32 %5)
>  %116 = extractelement <4 x float> %115, i32 0
>  %117 = extractelement <4 x float> %115, i32 1
>  %118 = extractelement <4 x float> %115, i32 2
>  %119 = extractelement <4 x float> %115, i32 3
>  %120 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
>  %122 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %121, i32 0, i32 %5)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = extractelement <4 x float> %122, i32 1
>  %125 = extractelement <4 x float> %122, i32 2
>  %126 = extractelement <4 x float> %122, i32 3
>  %127 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %128 = load <16 x i8> addrspace(2)* %127, !tbaa !0
>  %129 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %128, i32 0, i32 %5)
>  %130 = extractelement <4 x float> %129, i32 3
>  %131 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %132 = load <16 x i8> addrspace(2)* %131, !tbaa !0
>  %133 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %132, i32 0, i32 %5)
>  %134 = extractelement <4 x float> %133, i32 0
>  %135 = extractelement <4 x float> %133, i32 1
>  %136 = extractelement <4 x float> %133, i32 2
>  %137 = extractelement <4 x float> %133, i32 3
>  %138 = fmul float %102, %11
>  %139 = fmul float %102, %12
>  %140 = fmul float %102, %13
>  %141 = fmul float %102, %14
>  %142 = fmul float %103, %15
>  %143 = fadd float %142, %138
>  %144 = fmul float %103, %16
>  %145 = fadd float %144, %139
>  %146 = fmul float %103, %17
>  %147 = fadd float %146, %140
>  %148 = fmul float %103, %18
>  %149 = fadd float %148, %141
>  %150 = fmul float %104, %19
>  %151 = fadd float %150, %143
>  %152 = fmul float %104, %20
>  %153 = fadd float %152, %145
>  %154 = fmul float %104, %21
>  %155 = fadd float %154, %147
>  %156 = fmul float %104, %22
>  %157 = fadd float %156, %149
>  %158 = fmul float %105, %23
>  %159 = fadd float %158, %151
>  %160 = fmul float %105, %24
>  %161 = fadd float %160, %153
>  %162 = fmul float %105, %25
>  %163 = fadd float %162, %155
>  %164 = fmul float %105, %26
>  %165 = fadd float %164, %157
>  %166 = call float @llvm.AMDIL.clamp.(float %109, float 0.000000e+00, float 1.000000e+00)
>  %167 = call float @llvm.AMDIL.clamp.(float %110, float 0.000000e+00, float 1.000000e+00)
>  %168 = call float @llvm.AMDIL.clamp.(float %111, float 0.000000e+00, float 1.000000e+00)
>  %169 = call float @llvm.AMDIL.clamp.(float %112, float 0.000000e+00, float 1.000000e+00)
>  %170 = fmul float %116, %27
>  %171 = fmul float %116, %28
>  %172 = fmul float %116, %29
>  %173 = fmul float %116, %30
>  %174 = fmul float %117, %31
>  %175 = fadd float %174, %170
>  %176 = fmul float %117, %32
>  %177 = fadd float %176, %171
>  %178 = fmul float %117, %33
>  %179 = fadd float %178, %172
>  %180 = fmul float %117, %34
>  %181 = fadd float %180, %173
>  %182 = fmul float %118, %35
>  %183 = fadd float %182, %175
>  %184 = fmul float %118, %36
>  %185 = fadd float %184, %177
>  %186 = fmul float %118, %37
>  %187 = fadd float %186, %179
>  %188 = fmul float %118, %38
>  %189 = fadd float %188, %181
>  %190 = fmul float %119, %39
>  %191 = fadd float %190, %183
>  %192 = fmul float %119, %40
>  %193 = fadd float %192, %185
>  %194 = fmul float %119, %41
>  %195 = fadd float %194, %187
>  %196 = fmul float %119, %42
>  %197 = fadd float %196, %189
>  %198 = fmul float %123, %43
>  %199 = fmul float %123, %44
>  %200 = fmul float %123, %45
>  %201 = fmul float %123, %46
>  %202 = fmul float %124, %47
>  %203 = fadd float %202, %198
>  %204 = fmul float %124, %48
>  %205 = fadd float %204, %199
>  %206 = fmul float %124, %49
>  %207 = fadd float %206, %200
>  %208 = fmul float %124, %50
>  %209 = fadd float %208, %201
>  %210 = fmul float %125, %51
>  %211 = fadd float %210, %203
>  %212 = fmul float %125, %52
>  %213 = fadd float %212, %205
>  %214 = fmul float %125, %53
>  %215 = fadd float %214, %207
>  %216 = fmul float %125, %54
>  %217 = fadd float %216, %209
>  %218 = fmul float %126, %55
>  %219 = fadd float %218, %211
>  %220 = fmul float %126, %56
>  %221 = fadd float %220, %213
>  %222 = fmul float %126, %57
>  %223 = fadd float %222, %215
>  %224 = fmul float %126, %58
>  %225 = fadd float %224, %217
>  %226 = fmul float %59, %62
>  %227 = fmul float %60, %63
>  %228 = fadd float %227, %226
>  %229 = fmul float %61, %64
>  %230 = fadd float %228, %229
>  %231 = fmul float %59, %65
>  %232 = fmul float %60, %66
>  %233 = fadd float %232, %231
>  %234 = fmul float %61, %67
>  %235 = fadd float %233, %234
>  %236 = fmul float %59, %68
>  %237 = fmul float %60, %69
>  %238 = fadd float %237, %236
>  %239 = fmul float %61, %70
>  %240 = fadd float %238, %239
>  %241 = fmul float %230, %230
>  %242 = fmul float %235, %235
>  %243 = fadd float %242, %241
>  %244 = fmul float %240, %240
>  %245 = fadd float %243, %244
>  %246 = call float @fabs(float %245)
>  %247 = call float @llvm.AMDGPU.rsq(float %246)
>  %248 = fmul float %230, %247
>  %249 = fmul float %235, %247
>  %250 = fmul float %240, %247
>  %251 = fmul float %102, %71
>  %252 = fmul float %102, %72
>  %253 = fmul float %102, %73
>  %254 = fmul float %103, %74
>  %255 = fadd float %254, %251
>  %256 = fmul float %103, %75
>  %257 = fadd float %256, %252
>  %258 = fmul float %103, %76
>  %259 = fadd float %258, %253
>  %260 = fmul float %104, %77
>  %261 = fadd float %260, %255
>  %262 = fmul float %104, %78
>  %263 = fadd float %262, %257
>  %264 = fmul float %104, %79
>  %265 = fadd float %264, %259
>  %266 = fmul float %105, %80
>  %267 = fadd float %266, %261
>  %268 = fmul float %105, %81
>  %269 = fadd float %268, %263
>  %270 = fmul float %105, %82
>  %271 = fadd float %270, %265
>  %272 = fmul float %267, %267
>  %273 = fmul float %269, %269
>  %274 = fadd float %273, %272
>  %275 = fmul float %271, %271
>  %276 = fadd float %274, %275
>  %277 = call float @fabs(float %276)
>  %278 = call float @llvm.AMDGPU.rsq(float %277)
>  %279 = fmul float %267, %278
>  %280 = fmul float %269, %278
>  %281 = fmul float %271, %278
>  %282 = fmul float %248, %279
>  %283 = fmul float %249, %280
>  %284 = fadd float %283, %282
>  %285 = fmul float %250, %281
>  %286 = fadd float %284, %285
>  %287 = fadd float %286, %286
>  %288 = fadd float %286, %286
>  %289 = fadd float %286, %286
>  %290 = fsub float -0.000000e+00, %287
>  %291 = fmul float %290, %248
>  %292 = fadd float %291, %279
>  %293 = fsub float -0.000000e+00, %288
>  %294 = fmul float %293, %249
>  %295 = fadd float %294, %280
>  %296 = fsub float -0.000000e+00, %289
>  %297 = fmul float %296, %250
>  %298 = fadd float %297, %281
>  %299 = fmul float %292, %83
>  %300 = fmul float %292, %84
>  %301 = fmul float %292, %85
>  %302 = fmul float %292, %86
>  %303 = fmul float %295, %87
>  %304 = fadd float %303, %299
>  %305 = fmul float %295, %88
>  %306 = fadd float %305, %300
>  %307 = fmul float %295, %89
>  %308 = fadd float %307, %301
>  %309 = fmul float %295, %90
>  %310 = fadd float %309, %302
>  %311 = fmul float %298, %91
>  %312 = fadd float %311, %304
>  %313 = fmul float %298, %92
>  %314 = fadd float %313, %306
>  %315 = fmul float %298, %93
>  %316 = fadd float %315, %308
>  %317 = fmul float %298, %94
>  %318 = fadd float %317, %310
>  %319 = fmul float %130, %95
>  %320 = fadd float %319, %312
>  %321 = fmul float %130, %96
>  %322 = fadd float %321, %314
>  %323 = fmul float %130, %97
>  %324 = fadd float %323, %316
>  %325 = fmul float %130, %98
>  %326 = fadd float %325, %318
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %166, float %167, float %168, float %169)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %191, float %193, float %195, float %197)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %219, float %221, float %223, float %225)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %320, float %322, float %324, float %326)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %134, float %135, float %136, float %137)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %159, float %161, float %163, float %165)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800021f
>05060701
>c084070c
>bf8c000f
>e00c2000
>80020100
>c2020123
>bf8c0070
>100a0204
>c2020127
>bf8c007f
>d2820005
>04140902
>c202012b
>bf8c007f
>d2820005
>04140903
>c202012f
>bf8c007f
>d2820005
>04140904
>c2020122
>bf8c007f
>100c0204
>c2020126
>bf8c007f
>d2820006
>04180902
>c202012a
>bf8c007f
>d2820006
>04180903
>c202012e
>bf8c007f
>d2820006
>04180904
>c2020121
>bf8c007f
>100e0204
>c2020125
>bf8c007f
>d2820007
>041c0902
>c2020129
>bf8c007f
>d2820007
>041c0903
>c202012d
>bf8c007f
>d2820007
>041c0904
>c2020120
>bf8c007f
>10100204
>c2020124
>bf8c007f
>d2820008
>04200902
>c2020128
>bf8c007f
>d2820008
>04200903
>c202012c
>bf8c007f
>d2820001
>04200904
>f800022f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c2020141
>bf8c0070
>100a0204
>c2020145
>bf8c007f
>d2820005
>04140902
>c2020149
>bf8c007f
>d2820005
>04140903
>c202014d
>bf8c007f
>d2820005
>04140904
>c2020140
>bf8c007f
>100c0204
>c2020144
>bf8c007f
>d2820006
>04180902
>c2020148
>bf8c007f
>d2820006
>04180903
>c202014c
>bf8c007f
>d2820009
>04180904
>100c1309
>d2820006
>041a0b05
>c2020142
>bf8c007f
>100e0204
>c2020146
>bf8c007f
>d2820007
>041c0902
>c202014a
>bf8c007f
>d2820007
>041c0903
>c202014e
>bf8c007f
>d2820007
>041c0904
>d2820006
>041a0f07
>d2060106
>02010106
>7e105b06
>100c1105
>100a1109
>c2020130
>c2028138
>bf8c007f
>7e120205
>d2100009
>02021204
>c2028131
>c2040139
>bf8c007f
>7e140208
>d2820009
>04261405
>c2040132
>c204813a
>bf8c007f
>7e140209
>d2820009
>04261408
>c2048134
>bf8c007f
>7e140209
>d210000a
>02021404
>c2048135
>bf8c007f
>7e160209
>d282000a
>042a1605
>c2048136
>bf8c007f
>7e160209
>d282000a
>042a1608
>1016150a
>d282000b
>042e1309
>c204813c
>bf8c007f
>7e180209
>d210000c
>02021804
>c202013d
>bf8c007f
>7e1a0204
>d282000c
>04321a05
>c202013e
>bf8c007f
>7e1a0204
>d282000c
>04321a08
>d282000b
>042e190c
>d206010b
>0201010b
>7e165b0b
>1014170a
>101c0b0a
>101a1709
>d2820009
>043a0d0d
>100e1107
>1010170c
>d2820009
>04260f08
>06121309
>10161b09
>080c1706
>10141509
>080a1505
>c2020153
>bf8c007f
>10140a04
>c2020157
>bf8c007f
>d282000a
>04280906
>10101109
>080e1107
>c202015b
>bf8c007f
>d282000c
>04280907
>c0840710
>bf8c007f
>e00c2000
>80020800
>c202015f
>bf8c0070
>d282000c
>0430090b
>c2020152
>bf8c007f
>101a0a04
>c2020156
>bf8c007f
>d282000d
>04340906
>c202015a
>bf8c007f
>d282000d
>04340907
>c202015e
>bf8c007f
>d282000d
>0434090b
>c2020151
>bf8c007f
>101c0a04
>c2020155
>bf8c007f
>d282000e
>04380906
>c2020159
>bf8c007f
>d282000e
>04380907
>c202015d
>bf8c007f
>d282000e
>0438090b
>c2020150
>bf8c007f
>100a0a04
>c2020154
>bf8c007f
>d2820005
>04140906
>c2020158
>bf8c007f
>d2820005
>04140907
>c202015c
>bf8c007f
>d2820005
>0414090b
>f800023f
>0c0d0e05
>c0820714
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800024f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL IN[3], GENERIC[2], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL CONST[3..6]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0].xyz, TEMP[0], SAMP[2], 2D
>  3: MOV TEMP[0].xyz, TEMP[0].xyzx
>  4: MOV TEMP[1].xy, IN[2].xyyy
>  5: MOV TEMP[1].w, IN[2].wwww
>  6: TXP TEMP[1].w, TEMP[1], SAMP[1], 2D
>  7: MOV TEMP[0].w, TEMP[1].wwww
>  8: ADD TEMP[2].x, IMM[0].xxxx, -TEMP[1].wwww
>  9: TXP TEMP[3], IN[3], SAMP[0], CUBE
> 10: MUL TEMP[3], TEMP[3], TEMP[1].wwww
> 11: MAD TEMP[0].xyz, TEMP[0], TEMP[2].xxxx, TEMP[3]
> 12: MOV TEMP[0].xyz, TEMP[0].xyzx
> 13: MOV TEMP[0].w, TEMP[1].wwww
> 14: ADD TEMP[2].x, IMM[0].xxxx, -IN[0].wwww
> 15: MUL TEMP[0], TEMP[0], IN[0].wwww
> 16: MAD TEMP[0].xyz, CONST[6], TEMP[2].xxxx, TEMP[0]
> 17: MOV TEMP[0].xyz, TEMP[0].xyzx
> 18: MOV TEMP[0].w, TEMP[1].wwww
> 19: MOV OUT[0], TEMP[0]
> 20: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 100)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 104)
>  %25 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %26 = load <32 x i8> addrspace(2)* %25, !tbaa !0
>  %27 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %30 = load <32 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
>  %37 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %46 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
>  %47 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %48 = fdiv float %38, %40
>  %49 = fdiv float %39, %40
>  %50 = bitcast float %48 to i32
>  %51 = bitcast float %49 to i32
>  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
>  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
>  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %58 = fdiv float %41, %43
>  %59 = fdiv float %42, %43
>  %60 = bitcast float %58 to i32
>  %61 = bitcast float %59 to i32
>  %62 = insertelement <2 x i32> undef, i32 %60, i32 0
>  %63 = insertelement <2 x i32> %62, i32 %61, i32 1
>  %64 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %63, <32 x i8> %30, <16 x i8> %32, i32 2)
>  %65 = extractelement <4 x float> %64, i32 3
>  %66 = fsub float -0.000000e+00, %65
>  %67 = fadd float 1.000000e+00, %66
>  %68 = fdiv float %44, %47
>  %69 = fdiv float %45, %47
>  %70 = fdiv float %46, %47
>  %71 = insertelement <4 x float> undef, float %68, i32 0
>  %72 = insertelement <4 x float> %71, float %69, i32 1
>  %73 = insertelement <4 x float> %72, float %70, i32 2
>  %74 = insertelement <4 x float> %73, float 1.000000e+00, i32 3
>  %75 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %74)
>  %76 = extractelement <4 x float> %75, i32 0
>  %77 = extractelement <4 x float> %75, i32 1
>  %78 = extractelement <4 x float> %75, i32 2
>  %79 = extractelement <4 x float> %75, i32 3
>  %80 = call float @fabs(float %78)
>  %81 = fdiv float 1.000000e+00, %80
>  %82 = fmul float %76, %81
>  %83 = fadd float %82, 1.500000e+00
>  %84 = fmul float %77, %81
>  %85 = fadd float %84, 1.500000e+00
>  %86 = bitcast float %85 to i32
>  %87 = bitcast float %83 to i32
>  %88 = bitcast float %79 to i32
>  %89 = insertelement <4 x i32> undef, i32 %86, i32 0
>  %90 = insertelement <4 x i32> %89, i32 %87, i32 1
>  %91 = insertelement <4 x i32> %90, i32 %88, i32 2
>  %92 = insertelement <4 x i32> %91, i32 undef, i32 3
>  %93 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %92, <32 x i8> %26, <16 x i8> %28, i32 4)
>  %94 = extractelement <4 x float> %93, i32 0
>  %95 = extractelement <4 x float> %93, i32 1
>  %96 = extractelement <4 x float> %93, i32 2
>  %97 = fmul float %94, %65
>  %98 = fmul float %95, %65
>  %99 = fmul float %96, %65
>  %100 = fmul float %55, %67
>  %101 = fadd float %100, %97
>  %102 = fmul float %56, %67
>  %103 = fadd float %102, %98
>  %104 = fmul float %57, %67
>  %105 = fadd float %104, %99
>  %106 = fsub float -0.000000e+00, %37
>  %107 = fadd float 1.000000e+00, %106
>  %108 = fmul float %101, %37
>  %109 = fmul float %103, %37
>  %110 = fmul float %105, %37
>  %111 = fmul float %22, %107
>  %112 = fadd float %111, %108
>  %113 = fmul float %23, %107
>  %114 = fadd float %113, %109
>  %115 = fmul float %24, %107
>  %116 = fadd float %115, %110
>  %117 = call i32 @llvm.SI.packf16(float %112, float %114)
>  %118 = bitcast i32 %117 to float
>  %119 = call i32 @llvm.SI.packf16(float %116, float %65)
>  %120 = bitcast i32 %119 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %118, float %120, float %118, float %120)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080d00
>c8090d01
>c80c0f00
>c80d0f01
>7e0c5503
>10060d02
>c81c0c00
>c81d0c01
>10040d07
>c81c0e00
>c81d0e01
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430207
>c8140900
>c8150901
>c8180b00
>c8190b01
>7e0e5506
>100c0f05
>c8200800
>c8210801
>100a0f08
>c0840304
>c0c60508
>bf8c0070
>f0800800
>00430505
>bf8c0770
>100c0b03
>c81c0500
>c81d0501
>c8200700
>c8210701
>7e125508
>10101307
>c8280400
>c8290401
>100e130a
>c0840308
>c0c60510
>bf8c007f
>f0800700
>00430707
>08140af2
>bf8c0770
>d282000b
>041a1508
>c8180300
>c8190301
>10020d0b
>08000cf2
>c0800100
>bf8c007f
>c2020119
>bf8c007f
>d2820001
>04060004
>10160b02
>d282000b
>042e1507
>10160d0b
>c2020118
>bf8c007f
>d282000b
>042e0004
>5e02030b
>10040b04
>d2820002
>040a1509
>10040d02
>c200011a
>bf8c007f
>d2820000
>040a0000
>5e000b00
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..23]
>DCL TEMP[0..4]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
>  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
>  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
>  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
>  9: MUL TEMP[0], IN[3].xxxx, CONST[8]
> 10: MAD TEMP[0], IN[3].yyyy, CONST[9], TEMP[0]
> 11: MAD TEMP[0], IN[3].zzzz, CONST[10], TEMP[0]
> 12: MAD OUT[3], IN[3].wwww, CONST[11], TEMP[0]
> 13: DP3 TEMP[1].x, CONST[12], CONST[13]
> 14: DP3 TEMP[1].y, CONST[12], CONST[14]
> 15: DP3 TEMP[1].z, CONST[12], CONST[15]
> 16: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 17: RSQ TEMP[2].x, |TEMP[2]|
> 18: MUL TEMP[1], TEMP[1], TEMP[2].xxxx
> 19: MUL TEMP[2], IN[0].xxxx, CONST[16]
> 20: MAD TEMP[2], IN[0].yyyy, CONST[17], TEMP[2]
> 21: MAD TEMP[2], IN[0].zzzz, CONST[18], TEMP[2]
> 22: MAD TEMP[2], IN[0].wwww, CONST[19], TEMP[2]
> 23: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 24: RSQ TEMP[3].x, |TEMP[3]|
> 25: MUL TEMP[4], TEMP[2], TEMP[3].xxxx
> 26: DP3 TEMP[3], TEMP[1], TEMP[4]
> 27: ADD TEMP[3], TEMP[3], TEMP[3]
> 28: MAD TEMP[0].xyz, -TEMP[3], TEMP[1], TEMP[4]
> 29: MOV TEMP[0].w, IN[4]
> 30: MUL TEMP[3], TEMP[0].xxxx, CONST[20]
> 31: MAD TEMP[3], TEMP[0].yyyy, CONST[21], TEMP[3]
> 32: MAD TEMP[3], TEMP[0].zzzz, CONST[22], TEMP[3]
> 33: MAD OUT[4], TEMP[0].wwww, CONST[23], TEMP[3]
> 34: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %99 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %100 = load <16 x i8> addrspace(2)* %99, !tbaa !0
>  %101 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %100, i32 0, i32 %5)
>  %102 = extractelement <4 x float> %101, i32 0
>  %103 = extractelement <4 x float> %101, i32 1
>  %104 = extractelement <4 x float> %101, i32 2
>  %105 = extractelement <4 x float> %101, i32 3
>  %106 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %107 = load <16 x i8> addrspace(2)* %106, !tbaa !0
>  %108 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %107, i32 0, i32 %5)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = extractelement <4 x float> %108, i32 1
>  %111 = extractelement <4 x float> %108, i32 2
>  %112 = extractelement <4 x float> %108, i32 3
>  %113 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %114 = load <16 x i8> addrspace(2)* %113, !tbaa !0
>  %115 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %114, i32 0, i32 %5)
>  %116 = extractelement <4 x float> %115, i32 0
>  %117 = extractelement <4 x float> %115, i32 1
>  %118 = extractelement <4 x float> %115, i32 2
>  %119 = extractelement <4 x float> %115, i32 3
>  %120 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
>  %122 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %121, i32 0, i32 %5)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = extractelement <4 x float> %122, i32 1
>  %125 = extractelement <4 x float> %122, i32 2
>  %126 = extractelement <4 x float> %122, i32 3
>  %127 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %128 = load <16 x i8> addrspace(2)* %127, !tbaa !0
>  %129 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %128, i32 0, i32 %5)
>  %130 = extractelement <4 x float> %129, i32 3
>  %131 = fmul float %102, %11
>  %132 = fmul float %102, %12
>  %133 = fmul float %102, %13
>  %134 = fmul float %102, %14
>  %135 = fmul float %103, %15
>  %136 = fadd float %135, %131
>  %137 = fmul float %103, %16
>  %138 = fadd float %137, %132
>  %139 = fmul float %103, %17
>  %140 = fadd float %139, %133
>  %141 = fmul float %103, %18
>  %142 = fadd float %141, %134
>  %143 = fmul float %104, %19
>  %144 = fadd float %143, %136
>  %145 = fmul float %104, %20
>  %146 = fadd float %145, %138
>  %147 = fmul float %104, %21
>  %148 = fadd float %147, %140
>  %149 = fmul float %104, %22
>  %150 = fadd float %149, %142
>  %151 = fmul float %105, %23
>  %152 = fadd float %151, %144
>  %153 = fmul float %105, %24
>  %154 = fadd float %153, %146
>  %155 = fmul float %105, %25
>  %156 = fadd float %155, %148
>  %157 = fmul float %105, %26
>  %158 = fadd float %157, %150
>  %159 = call float @llvm.AMDIL.clamp.(float %109, float 0.000000e+00, float 1.000000e+00)
>  %160 = call float @llvm.AMDIL.clamp.(float %110, float 0.000000e+00, float 1.000000e+00)
>  %161 = call float @llvm.AMDIL.clamp.(float %111, float 0.000000e+00, float 1.000000e+00)
>  %162 = call float @llvm.AMDIL.clamp.(float %112, float 0.000000e+00, float 1.000000e+00)
>  %163 = fmul float %116, %27
>  %164 = fmul float %116, %28
>  %165 = fmul float %116, %29
>  %166 = fmul float %116, %30
>  %167 = fmul float %117, %31
>  %168 = fadd float %167, %163
>  %169 = fmul float %117, %32
>  %170 = fadd float %169, %164
>  %171 = fmul float %117, %33
>  %172 = fadd float %171, %165
>  %173 = fmul float %117, %34
>  %174 = fadd float %173, %166
>  %175 = fmul float %118, %35
>  %176 = fadd float %175, %168
>  %177 = fmul float %118, %36
>  %178 = fadd float %177, %170
>  %179 = fmul float %118, %37
>  %180 = fadd float %179, %172
>  %181 = fmul float %118, %38
>  %182 = fadd float %181, %174
>  %183 = fmul float %119, %39
>  %184 = fadd float %183, %176
>  %185 = fmul float %119, %40
>  %186 = fadd float %185, %178
>  %187 = fmul float %119, %41
>  %188 = fadd float %187, %180
>  %189 = fmul float %119, %42
>  %190 = fadd float %189, %182
>  %191 = fmul float %123, %43
>  %192 = fmul float %123, %44
>  %193 = fmul float %123, %45
>  %194 = fmul float %123, %46
>  %195 = fmul float %124, %47
>  %196 = fadd float %195, %191
>  %197 = fmul float %124, %48
>  %198 = fadd float %197, %192
>  %199 = fmul float %124, %49
>  %200 = fadd float %199, %193
>  %201 = fmul float %124, %50
>  %202 = fadd float %201, %194
>  %203 = fmul float %125, %51
>  %204 = fadd float %203, %196
>  %205 = fmul float %125, %52
>  %206 = fadd float %205, %198
>  %207 = fmul float %125, %53
>  %208 = fadd float %207, %200
>  %209 = fmul float %125, %54
>  %210 = fadd float %209, %202
>  %211 = fmul float %126, %55
>  %212 = fadd float %211, %204
>  %213 = fmul float %126, %56
>  %214 = fadd float %213, %206
>  %215 = fmul float %126, %57
>  %216 = fadd float %215, %208
>  %217 = fmul float %126, %58
>  %218 = fadd float %217, %210
>  %219 = fmul float %59, %62
>  %220 = fmul float %60, %63
>  %221 = fadd float %220, %219
>  %222 = fmul float %61, %64
>  %223 = fadd float %221, %222
>  %224 = fmul float %59, %65
>  %225 = fmul float %60, %66
>  %226 = fadd float %225, %224
>  %227 = fmul float %61, %67
>  %228 = fadd float %226, %227
>  %229 = fmul float %59, %68
>  %230 = fmul float %60, %69
>  %231 = fadd float %230, %229
>  %232 = fmul float %61, %70
>  %233 = fadd float %231, %232
>  %234 = fmul float %223, %223
>  %235 = fmul float %228, %228
>  %236 = fadd float %235, %234
>  %237 = fmul float %233, %233
>  %238 = fadd float %236, %237
>  %239 = call float @fabs(float %238)
>  %240 = call float @llvm.AMDGPU.rsq(float %239)
>  %241 = fmul float %223, %240
>  %242 = fmul float %228, %240
>  %243 = fmul float %233, %240
>  %244 = fmul float %102, %71
>  %245 = fmul float %102, %72
>  %246 = fmul float %102, %73
>  %247 = fmul float %103, %74
>  %248 = fadd float %247, %244
>  %249 = fmul float %103, %75
>  %250 = fadd float %249, %245
>  %251 = fmul float %103, %76
>  %252 = fadd float %251, %246
>  %253 = fmul float %104, %77
>  %254 = fadd float %253, %248
>  %255 = fmul float %104, %78
>  %256 = fadd float %255, %250
>  %257 = fmul float %104, %79
>  %258 = fadd float %257, %252
>  %259 = fmul float %105, %80
>  %260 = fadd float %259, %254
>  %261 = fmul float %105, %81
>  %262 = fadd float %261, %256
>  %263 = fmul float %105, %82
>  %264 = fadd float %263, %258
>  %265 = fmul float %260, %260
>  %266 = fmul float %262, %262
>  %267 = fadd float %266, %265
>  %268 = fmul float %264, %264
>  %269 = fadd float %267, %268
>  %270 = call float @fabs(float %269)
>  %271 = call float @llvm.AMDGPU.rsq(float %270)
>  %272 = fmul float %260, %271
>  %273 = fmul float %262, %271
>  %274 = fmul float %264, %271
>  %275 = fmul float %241, %272
>  %276 = fmul float %242, %273
>  %277 = fadd float %276, %275
>  %278 = fmul float %243, %274
>  %279 = fadd float %277, %278
>  %280 = fadd float %279, %279
>  %281 = fadd float %279, %279
>  %282 = fadd float %279, %279
>  %283 = fsub float -0.000000e+00, %280
>  %284 = fmul float %283, %241
>  %285 = fadd float %284, %272
>  %286 = fsub float -0.000000e+00, %281
>  %287 = fmul float %286, %242
>  %288 = fadd float %287, %273
>  %289 = fsub float -0.000000e+00, %282
>  %290 = fmul float %289, %243
>  %291 = fadd float %290, %274
>  %292 = fmul float %285, %83
>  %293 = fmul float %285, %84
>  %294 = fmul float %285, %85
>  %295 = fmul float %285, %86
>  %296 = fmul float %288, %87
>  %297 = fadd float %296, %292
>  %298 = fmul float %288, %88
>  %299 = fadd float %298, %293
>  %300 = fmul float %288, %89
>  %301 = fadd float %300, %294
>  %302 = fmul float %288, %90
>  %303 = fadd float %302, %295
>  %304 = fmul float %291, %91
>  %305 = fadd float %304, %297
>  %306 = fmul float %291, %92
>  %307 = fadd float %306, %299
>  %308 = fmul float %291, %93
>  %309 = fadd float %308, %301
>  %310 = fmul float %291, %94
>  %311 = fadd float %310, %303
>  %312 = fmul float %130, %95
>  %313 = fadd float %312, %305
>  %314 = fmul float %130, %96
>  %315 = fadd float %314, %307
>  %316 = fmul float %130, %97
>  %317 = fadd float %316, %309
>  %318 = fmul float %130, %98
>  %319 = fadd float %318, %311
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %159, float %160, float %161, float %162)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %184, float %186, float %188, float %190)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %212, float %214, float %216, float %218)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %313, float %315, float %317, float %319)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %152, float %154, float %156, float %158)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800021f
>05060701
>c084070c
>bf8c000f
>e00c2000
>80020100
>c2020123
>bf8c0070
>100a0204
>c2020127
>bf8c007f
>d2820005
>04140902
>c202012b
>bf8c007f
>d2820005
>04140903
>c202012f
>bf8c007f
>d2820005
>04140904
>c2020122
>bf8c007f
>100c0204
>c2020126
>bf8c007f
>d2820006
>04180902
>c202012a
>bf8c007f
>d2820006
>04180903
>c202012e
>bf8c007f
>d2820006
>04180904
>c2020121
>bf8c007f
>100e0204
>c2020125
>bf8c007f
>d2820007
>041c0902
>c2020129
>bf8c007f
>d2820007
>041c0903
>c202012d
>bf8c007f
>d2820007
>041c0904
>c2020120
>bf8c007f
>10100204
>c2020124
>bf8c007f
>d2820008
>04200902
>c2020128
>bf8c007f
>d2820008
>04200903
>c202012c
>bf8c007f
>d2820001
>04200904
>f800022f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c2020141
>bf8c0070
>100a0204
>c2020145
>bf8c007f
>d2820005
>04140902
>c2020149
>bf8c007f
>d2820005
>04140903
>c202014d
>bf8c007f
>d2820005
>04140904
>c2020140
>bf8c007f
>100c0204
>c2020144
>bf8c007f
>d2820006
>04180902
>c2020148
>bf8c007f
>d2820006
>04180903
>c202014c
>bf8c007f
>d2820009
>04180904
>100c1309
>d2820006
>041a0b05
>c2020142
>bf8c007f
>100e0204
>c2020146
>bf8c007f
>d2820007
>041c0902
>c202014a
>bf8c007f
>d2820007
>041c0903
>c202014e
>bf8c007f
>d2820007
>041c0904
>d2820006
>041a0f07
>d2060106
>02010106
>7e105b06
>100c1105
>100a1109
>c2020130
>c2028138
>bf8c007f
>7e120205
>d2100009
>02021204
>c2028131
>c2040139
>bf8c007f
>7e140208
>d2820009
>04261405
>c2040132
>c204813a
>bf8c007f
>7e140209
>d2820009
>04261408
>c2048134
>bf8c007f
>7e140209
>d210000a
>02021404
>c2048135
>bf8c007f
>7e160209
>d282000a
>042a1605
>c2048136
>bf8c007f
>7e160209
>d282000a
>042a1608
>1016150a
>d282000b
>042e1309
>c204813c
>bf8c007f
>7e180209
>d210000c
>02021804
>c202013d
>bf8c007f
>7e1a0204
>d282000c
>04321a05
>c202013e
>bf8c007f
>7e1a0204
>d282000c
>04321a08
>d282000b
>042e190c
>d206010b
>0201010b
>7e165b0b
>1014170a
>101c0b0a
>101a1709
>d2820009
>043a0d0d
>100e1107
>1010170c
>d2820009
>04260f08
>06121309
>10161b09
>080c1706
>10141509
>080a1505
>c2020153
>bf8c007f
>10140a04
>c2020157
>bf8c007f
>d282000a
>04280906
>10101109
>080e1107
>c202015b
>bf8c007f
>d282000c
>04280907
>c0820710
>bf8c007f
>e00c2000
>80010800
>c202015f
>bf8c0070
>d2820000
>0430090b
>c2020152
>bf8c007f
>10180a04
>c2020156
>bf8c007f
>d282000c
>04300906
>c202015a
>bf8c007f
>d282000c
>04300907
>c202015e
>bf8c007f
>d282000c
>0430090b
>c2020151
>bf8c007f
>101a0a04
>c2020155
>bf8c007f
>d282000d
>04340906
>c2020159
>bf8c007f
>d282000d
>04340907
>c202015d
>bf8c007f
>d282000d
>0434090b
>c2020150
>bf8c007f
>100a0a04
>c2020154
>bf8c007f
>d2820005
>04140906
>c2020158
>bf8c007f
>d2820005
>04140907
>c202015c
>bf8c007f
>d2820005
>0414090b
>f800023f
>000c0d05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1]
>DCL TEMP[0..1], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[1].xyz, TEMP[0], CONST[1]
>  4: MOV TEMP[1].xyz, TEMP[1].xyzx
>  5: MOV TEMP[1].w, TEMP[0].wwww
>  6: MUL TEMP[1].xyz, IN[0].wwww, TEMP[1]
>  7: MOV TEMP[1].xyz, TEMP[1].xyzx
>  8: MOV TEMP[1].w, TEMP[0].wwww
>  9: MOV OUT[0], TEMP[1]
> 10: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
>  %25 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %26 = load <32 x i8> addrspace(2)* %25, !tbaa !0
>  %27 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %33 = fdiv float %30, %32
>  %34 = fdiv float %31, %32
>  %35 = bitcast float %33 to i32
>  %36 = bitcast float %34 to i32
>  %37 = insertelement <2 x i32> undef, i32 %35, i32 0
>  %38 = insertelement <2 x i32> %37, i32 %36, i32 1
>  %39 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %38, <32 x i8> %26, <16 x i8> %28, i32 2)
>  %40 = extractelement <4 x float> %39, i32 0
>  %41 = extractelement <4 x float> %39, i32 1
>  %42 = extractelement <4 x float> %39, i32 2
>  %43 = extractelement <4 x float> %39, i32 3
>  %44 = fmul float %40, %22
>  %45 = fmul float %41, %23
>  %46 = fmul float %42, %24
>  %47 = fmul float %29, %44
>  %48 = fmul float %29, %45
>  %49 = fmul float %29, %46
>  %50 = call i32 @llvm.SI.packf16(float %47, float %48)
>  %51 = bitcast i32 %50 to float
>  %52 = call i32 @llvm.SI.packf16(float %49, float %43)
>  %53 = bitcast i32 %52 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %51, float %53, float %51, float %53)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c0800100
>bf8c0070
>c2020106
>bf8c007f
>100e0804
>c8180300
>c8190301
>10000f06
>5e000b00
>c2020105
>bf8c007f
>10020604
>10020306
>c2000104
>bf8c007f
>10040400
>10040506
>5e020302
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[1]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
>  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
>  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
>  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = extractelement <4 x float> %59, i32 3
>  %64 = fmul float %46, %11
>  %65 = fmul float %46, %12
>  %66 = fmul float %46, %13
>  %67 = fmul float %46, %14
>  %68 = fmul float %47, %15
>  %69 = fadd float %68, %64
>  %70 = fmul float %47, %16
>  %71 = fadd float %70, %65
>  %72 = fmul float %47, %17
>  %73 = fadd float %72, %66
>  %74 = fmul float %47, %18
>  %75 = fadd float %74, %67
>  %76 = fmul float %48, %19
>  %77 = fadd float %76, %69
>  %78 = fmul float %48, %20
>  %79 = fadd float %78, %71
>  %80 = fmul float %48, %21
>  %81 = fadd float %80, %73
>  %82 = fmul float %48, %22
>  %83 = fadd float %82, %75
>  %84 = fmul float %49, %23
>  %85 = fadd float %84, %77
>  %86 = fmul float %49, %24
>  %87 = fadd float %86, %79
>  %88 = fmul float %49, %25
>  %89 = fadd float %88, %81
>  %90 = fmul float %49, %26
>  %91 = fadd float %90, %83
>  %92 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
>  %93 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %94 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
>  %96 = fmul float %60, %27
>  %97 = fmul float %60, %28
>  %98 = fmul float %60, %29
>  %99 = fmul float %60, %30
>  %100 = fmul float %61, %31
>  %101 = fadd float %100, %96
>  %102 = fmul float %61, %32
>  %103 = fadd float %102, %97
>  %104 = fmul float %61, %33
>  %105 = fadd float %104, %98
>  %106 = fmul float %61, %34
>  %107 = fadd float %106, %99
>  %108 = fmul float %62, %35
>  %109 = fadd float %108, %101
>  %110 = fmul float %62, %36
>  %111 = fadd float %110, %103
>  %112 = fmul float %62, %37
>  %113 = fadd float %112, %105
>  %114 = fmul float %62, %38
>  %115 = fadd float %114, %107
>  %116 = fmul float %63, %39
>  %117 = fadd float %116, %109
>  %118 = fmul float %63, %40
>  %119 = fadd float %118, %111
>  %120 = fmul float %63, %41
>  %121 = fadd float %120, %113
>  %122 = fmul float %63, %42
>  %123 = fadd float %122, %115
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %92, float %93, float %94, float %95)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %117, float %119, float %121, float %123)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %85, float %87, float %89, float %91)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800021f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  5: MOV OUT[0], TEMP[0]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %31 = fdiv float %28, %30
>  %32 = fdiv float %29, %30
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, %24
>  %43 = fmul float %39, %25
>  %44 = fmul float %40, %26
>  %45 = fmul float %41, %27
>  %46 = fmul float %42, 2.000000e+00
>  %47 = fmul float %43, 2.000000e+00
>  %48 = fmul float %44, 2.000000e+00
>  %49 = fmul float %45, 1.000000e+00
>  %50 = call float @llvm.AMDIL.clamp.(float %46, float 0.000000e+00, float 1.000000e+00)
>  %51 = call float @llvm.AMDIL.clamp.(float %47, float 0.000000e+00, float 1.000000e+00)
>  %52 = call float @llvm.AMDIL.clamp.(float %48, float 0.000000e+00, float 1.000000e+00)
>  %53 = call float @llvm.AMDIL.clamp.(float %49, float 0.000000e+00, float 1.000000e+00)
>  %54 = fcmp ugt float %53, 0.000000e+00
>  %55 = sext i1 %54 to i32
>  %56 = trunc i32 %55 to i1
>  %57 = select i1 %56, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %57)
>  %58 = call i32 @llvm.SI.packf16(float %50, float %51)
>  %59 = bitcast i32 %58 to float
>  %60 = call i32 @llvm.SI.packf16(float %52, float %53)
>  %61 = bitcast i32 %60 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %59, float %61, float %59, float %61)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>d2060806
>02010106
>d0080000
>02010106
>d2000007
>0001e4f3
>7c260e80
>c81c0100
>c81d0101
>10100f03
>d2820007
>04220f03
>d2060807
>02010107
>c8200000
>c8210001
>10121102
>d2820008
>04261102
>d2060808
>02010108
>5e0e0f08
>c8200200
>c8210201
>10001104
>d2820000
>04021104
>d2060800
>02010100
>5e000d00
>f8001c0f
>00070007
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MOV OUT[0], TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %27 = fdiv float %24, %26
>  %28 = fdiv float %25, %26
>  %29 = bitcast float %27 to i32
>  %30 = bitcast float %28 to i32
>  %31 = insertelement <2 x i32> undef, i32 %29, i32 0
>  %32 = insertelement <2 x i32> %31, i32 %30, i32 1
>  %33 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %32, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = fcmp ugt float %37, 0.000000e+00
>  %39 = sext i1 %38 to i32
>  %40 = trunc i32 %39 to i1
>  %41 = select i1 %40, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %41)
>  %42 = call i32 @llvm.SI.packf16(float %34, float %35)
>  %43 = bitcast i32 %42 to float
>  %44 = call i32 @llvm.SI.packf16(float %36, float %37)
>  %45 = bitcast i32 %44 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %43, float %45, float %43, float %45)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0300
>c80d0301
>7e085503
>10060902
>c8140000
>c8150001
>10040905
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>d0080000
>02010103
>d2000004
>0001e4f3
>7c260880
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  5: MOV TEMP[0].xyz, TEMP[0].xyzx
>  6: MOV TEMP[1].xy, IN[2].xyyy
>  7: MOV TEMP[1].w, IN[2].wwww
>  8: TXP TEMP[1].w, TEMP[1], SAMP[0], 2D
>  9: MOV TEMP[0].w, TEMP[1].wwww
> 10: MOV OUT[0], TEMP[0]
> 11: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %38 = fdiv float %32, %34
>  %39 = fdiv float %33, %34
>  %40 = bitcast float %38 to i32
>  %41 = bitcast float %39 to i32
>  %42 = insertelement <2 x i32> undef, i32 %40, i32 0
>  %43 = insertelement <2 x i32> %42, i32 %41, i32 1
>  %44 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %43, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = extractelement <4 x float> %44, i32 1
>  %47 = extractelement <4 x float> %44, i32 2
>  %48 = extractelement <4 x float> %44, i32 3
>  %49 = fmul float %45, %28
>  %50 = fmul float %46, %29
>  %51 = fmul float %47, %30
>  %52 = fmul float %48, %31
>  %53 = fmul float %49, 2.000000e+00
>  %54 = fmul float %50, 2.000000e+00
>  %55 = fmul float %51, 2.000000e+00
>  %56 = fmul float %52, 1.000000e+00
>  %57 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
>  %58 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %59 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %60 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
>  %61 = fdiv float %35, %37
>  %62 = fdiv float %36, %37
>  %63 = bitcast float %61 to i32
>  %64 = bitcast float %62 to i32
>  %65 = insertelement <2 x i32> undef, i32 %63, i32 0
>  %66 = insertelement <2 x i32> %65, i32 %64, i32 1
>  %67 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %66, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %68 = extractelement <4 x float> %67, i32 3
>  %69 = fcmp ugt float %68, 0.000000e+00
>  %70 = sext i1 %69 to i32
>  %71 = trunc i32 %70 to i1
>  %72 = select i1 %71, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %72)
>  %73 = call i32 @llvm.SI.packf16(float %57, float %58)
>  %74 = bitcast i32 %73 to float
>  %75 = call i32 @llvm.SI.packf16(float %59, float %68)
>  %76 = bitcast i32 %75 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %74, float %76, float %74, float %76)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800800
>00430202
>bf8c0770
>d0080000
>02010102
>d2000003
>0001e4f3
>7c260680
>c80c0500
>c80d0501
>c8100700
>c8110701
>7e0a5504
>10080b03
>c8180400
>c8190401
>10060b06
>c0800304
>c0c40508
>bf8c007f
>f0800700
>00020303
>c8180100
>c8190101
>bf8c0770
>100e0d04
>d2820006
>041e0d04
>d2060806
>02010106
>c81c0000
>c81d0001
>10100f03
>d2820007
>04220f03
>d2060807
>02010107
>5e0c0d07
>c81c0200
>c81d0201
>10000f05
>d2820000
>04020f05
>d2060800
>02010100
>5e000500
>f8001c0f
>00060006
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MOV TEMP[1].xy, IN[2].xyyy
>  4: MOV TEMP[1].w, IN[2].wwww
>  5: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  6: MUL TEMP[1].xyz, TEMP[1], TEMP[0]
>  7: MOV TEMP[1].xyz, TEMP[1].xyzx
>  8: MOV TEMP[1].w, TEMP[0].wwww
>  9: MUL TEMP[1].xyz, IN[0], TEMP[1]
> 10: MOV TEMP[1].xyz, TEMP[1].xyzx
> 11: MOV TEMP[1].w, TEMP[0].wwww
> 12: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
> 13: MOV OUT[0], TEMP[0]
> 14: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %37 = fdiv float %31, %33
>  %38 = fdiv float %32, %33
>  %39 = bitcast float %37 to i32
>  %40 = bitcast float %38 to i32
>  %41 = insertelement <2 x i32> undef, i32 %39, i32 0
>  %42 = insertelement <2 x i32> %41, i32 %40, i32 1
>  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %42, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fdiv float %34, %36
>  %49 = fdiv float %35, %36
>  %50 = bitcast float %48 to i32
>  %51 = bitcast float %49 to i32
>  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
>  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
>  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %58 = fmul float %55, %44
>  %59 = fmul float %56, %45
>  %60 = fmul float %57, %46
>  %61 = fmul float %28, %58
>  %62 = fmul float %29, %59
>  %63 = fmul float %30, %60
>  %64 = fmul float %61, 2.000000e+00
>  %65 = fmul float %62, 2.000000e+00
>  %66 = fmul float %63, 2.000000e+00
>  %67 = fmul float %47, 1.000000e+00
>  %68 = call float @llvm.AMDIL.clamp.(float %64, float 0.000000e+00, float 1.000000e+00)
>  %69 = call float @llvm.AMDIL.clamp.(float %65, float 0.000000e+00, float 1.000000e+00)
>  %70 = call float @llvm.AMDIL.clamp.(float %66, float 0.000000e+00, float 1.000000e+00)
>  %71 = call float @llvm.AMDIL.clamp.(float %67, float 0.000000e+00, float 1.000000e+00)
>  %72 = call i32 @llvm.SI.packf16(float %68, float %69)
>  %73 = bitcast i32 %72 to float
>  %74 = call i32 @llvm.SI.packf16(float %70, float %71)
>  %75 = bitcast i32 %74 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %73, float %75, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180900
>c8190901
>c81c0b00
>c81d0b01
>7e105507
>100e1106
>c8240800
>c8250801
>100c1109
>c0800300
>c0c40500
>bf8c0070
>f0800700
>00020606
>bf8c0770
>10120707
>c8280100
>c8290101
>1016130a
>d2820009
>042e130a
>d2060809
>02010109
>10140506
>c82c0000
>c82d0001
>1018150b
>d282000a
>0432150b
>d206080a
>0201010a
>5e12130a
>100c0908
>c81c0200
>c81d0201
>10000d07
>d2820000
>04020d07
>d2060800
>02010100
>d2060801
>02010105
>5e000300
>f8001c0f
>00090009
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: MOV OUT[3], IN[3]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %5)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = extractelement <4 x float> %50, i32 3
>  %55 = fmul float %30, %11
>  %56 = fmul float %30, %12
>  %57 = fmul float %30, %13
>  %58 = fmul float %30, %14
>  %59 = fmul float %31, %15
>  %60 = fadd float %59, %55
>  %61 = fmul float %31, %16
>  %62 = fadd float %61, %56
>  %63 = fmul float %31, %17
>  %64 = fadd float %63, %57
>  %65 = fmul float %31, %18
>  %66 = fadd float %65, %58
>  %67 = fmul float %32, %19
>  %68 = fadd float %67, %60
>  %69 = fmul float %32, %20
>  %70 = fadd float %69, %62
>  %71 = fmul float %32, %21
>  %72 = fadd float %71, %64
>  %73 = fmul float %32, %22
>  %74 = fadd float %73, %66
>  %75 = fmul float %33, %23
>  %76 = fadd float %75, %68
>  %77 = fmul float %33, %24
>  %78 = fadd float %77, %70
>  %79 = fmul float %33, %25
>  %80 = fadd float %79, %72
>  %81 = fmul float %33, %26
>  %82 = fadd float %81, %74
>  %83 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %84 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %85 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %86 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %83, float %84, float %85, float %86)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %51, float %52, float %53, float %54)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %76, float %78, float %80, float %82)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800022f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[1].xyz, TEMP[0], CONST[1]
>  4: MOV TEMP[1].xyz, TEMP[1].xyzx
>  5: MOV TEMP[1].w, TEMP[0].wwww
>  6: MUL TEMP[1].xyz, IN[0], TEMP[1]
>  7: MOV TEMP[1].xyz, TEMP[1].xyzx
>  8: MOV TEMP[1].w, TEMP[0].wwww
>  9: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
> 10: MOV OUT[0], TEMP[0]
> 11: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
>  %25 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %26 = load <32 x i8> addrspace(2)* %25, !tbaa !0
>  %27 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %35 = fdiv float %32, %34
>  %36 = fdiv float %33, %34
>  %37 = bitcast float %35 to i32
>  %38 = bitcast float %36 to i32
>  %39 = insertelement <2 x i32> undef, i32 %37, i32 0
>  %40 = insertelement <2 x i32> %39, i32 %38, i32 1
>  %41 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %26, <16 x i8> %28, i32 2)
>  %42 = extractelement <4 x float> %41, i32 0
>  %43 = extractelement <4 x float> %41, i32 1
>  %44 = extractelement <4 x float> %41, i32 2
>  %45 = extractelement <4 x float> %41, i32 3
>  %46 = fmul float %42, %22
>  %47 = fmul float %43, %23
>  %48 = fmul float %44, %24
>  %49 = fmul float %29, %46
>  %50 = fmul float %30, %47
>  %51 = fmul float %31, %48
>  %52 = fmul float %49, 2.000000e+00
>  %53 = fmul float %50, 2.000000e+00
>  %54 = fmul float %51, 2.000000e+00
>  %55 = fmul float %45, 1.000000e+00
>  %56 = call float @llvm.AMDIL.clamp.(float %52, float 0.000000e+00, float 1.000000e+00)
>  %57 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
>  %58 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %59 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %60 = call i32 @llvm.SI.packf16(float %56, float %57)
>  %61 = bitcast i32 %60 to float
>  %62 = call i32 @llvm.SI.packf16(float %58, float %59)
>  %63 = bitcast i32 %62 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %61, float %63, float %61, float %63)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c0800100
>bf8c0070
>c2020105
>bf8c007f
>100c0604
>c81c0100
>c81d0101
>10100d07
>d2820006
>04220d07
>d2060806
>02010106
>c2020104
>bf8c007f
>100e0404
>c8200000
>c8210001
>10120f08
>d2820007
>04260f08
>d2060807
>02010107
>5e0c0d07
>c2000106
>bf8c007f
>100e0800
>c8200200
>c8210201
>10000f08
>d2820000
>04020f08
>d2060800
>02010100
>d2060801
>02010105
>5e000300
>f8001c0f
>00060006
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[1]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  5: MOV OUT[0], TEMP[0]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %31 = fdiv float %28, %30
>  %32 = fdiv float %29, %30
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, %24
>  %43 = fmul float %39, %25
>  %44 = fmul float %40, %26
>  %45 = fmul float %41, %27
>  %46 = fmul float %42, 2.000000e+00
>  %47 = fmul float %43, 2.000000e+00
>  %48 = fmul float %44, 2.000000e+00
>  %49 = fmul float %45, 1.000000e+00
>  %50 = call float @llvm.AMDIL.clamp.(float %46, float 0.000000e+00, float 1.000000e+00)
>  %51 = call float @llvm.AMDIL.clamp.(float %47, float 0.000000e+00, float 1.000000e+00)
>  %52 = call float @llvm.AMDIL.clamp.(float %48, float 0.000000e+00, float 1.000000e+00)
>  %53 = call float @llvm.AMDIL.clamp.(float %49, float 0.000000e+00, float 1.000000e+00)
>  %54 = fcmp ugt float %53, 0x3FD9191920000000
>  %55 = sext i1 %54 to i32
>  %56 = trunc i32 %55 to i1
>  %57 = select i1 %56, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %57)
>  %58 = call i32 @llvm.SI.packf16(float %50, float %51)
>  %59 = bitcast i32 %58 to float
>  %60 = call i32 @llvm.SI.packf16(float %52, float %53)
>  %61 = bitcast i32 %60 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %59, float %61, float %59, float %61)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>d2060806
>02010106
>7e0e02ff
>3ec8c8c9
>d0080000
>02020f06
>d2000007
>0001e4f3
>7c260e80
>c81c0100
>c81d0101
>10100f03
>d2820007
>04220f03
>d2060807
>02010107
>c8200000
>c8210001
>10121102
>d2820008
>04261102
>d2060808
>02010108
>5e0e0f08
>c8200200
>c8210201
>10001104
>d2820000
>04021104
>d2060800
>02010100
>5e000d00
>f8001c0f
>00070007
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL IN[1], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..1], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0].xyz, TEMP[0], SAMP[1], 2D
>  3: MOV TEMP[0].xyz, TEMP[0].xyzx
>  4: MOV TEMP[1].xy, IN[1].xyyy
>  5: MOV TEMP[1].w, IN[1].wwww
>  6: TXP TEMP[1].w, TEMP[1], SAMP[0], 2D
>  7: MOV TEMP[0].w, TEMP[1].wwww
>  8: MOV OUT[0], TEMP[0]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %34 = fdiv float %28, %30
>  %35 = fdiv float %29, %30
>  %36 = bitcast float %34 to i32
>  %37 = bitcast float %35 to i32
>  %38 = insertelement <2 x i32> undef, i32 %36, i32 0
>  %39 = insertelement <2 x i32> %38, i32 %37, i32 1
>  %40 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %39, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = fdiv float %31, %33
>  %45 = fdiv float %32, %33
>  %46 = bitcast float %44 to i32
>  %47 = bitcast float %45 to i32
>  %48 = insertelement <2 x i32> undef, i32 %46, i32 0
>  %49 = insertelement <2 x i32> %48, i32 %47, i32 1
>  %50 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %49, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %51 = extractelement <4 x float> %50, i32 3
>  %52 = fcmp ugt float %51, 0.000000e+00
>  %53 = sext i1 %52 to i32
>  %54 = trunc i32 %53 to i1
>  %55 = select i1 %54, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %55)
>  %56 = call i32 @llvm.SI.packf16(float %41, float %42)
>  %57 = bitcast i32 %56 to float
>  %58 = call i32 @llvm.SI.packf16(float %43, float %51)
>  %59 = bitcast i32 %58 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %57, float %59, float %57, float %59)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800800
>00430202
>bf8c0770
>d0080000
>02010102
>d2000003
>0001e4f3
>7c260680
>c80c0100
>c80d0101
>c8100300
>c8110301
>7e0a5504
>10080b03
>c8180000
>c8190001
>10060b06
>c0800304
>c0c20508
>bf8c007f
>f0800700
>00010303
>bf8c0770
>5e000505
>5e020903
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL OUT[2], GENERIC[1]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MUL TEMP[0], IN[1].xxxx, CONST[4]
>  5: MAD TEMP[0], IN[1].yyyy, CONST[5], TEMP[0]
>  6: MAD TEMP[0], IN[1].zzzz, CONST[6], TEMP[0]
>  7: MAD OUT[1], IN[1].wwww, CONST[7], TEMP[0]
>  8: MOV OUT[2], IN[2]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = extractelement <4 x float> %59, i32 3
>  %64 = fmul float %46, %11
>  %65 = fmul float %46, %12
>  %66 = fmul float %46, %13
>  %67 = fmul float %46, %14
>  %68 = fmul float %47, %15
>  %69 = fadd float %68, %64
>  %70 = fmul float %47, %16
>  %71 = fadd float %70, %65
>  %72 = fmul float %47, %17
>  %73 = fadd float %72, %66
>  %74 = fmul float %47, %18
>  %75 = fadd float %74, %67
>  %76 = fmul float %48, %19
>  %77 = fadd float %76, %69
>  %78 = fmul float %48, %20
>  %79 = fadd float %78, %71
>  %80 = fmul float %48, %21
>  %81 = fadd float %80, %73
>  %82 = fmul float %48, %22
>  %83 = fadd float %82, %75
>  %84 = fmul float %49, %23
>  %85 = fadd float %84, %77
>  %86 = fmul float %49, %24
>  %87 = fadd float %86, %79
>  %88 = fmul float %49, %25
>  %89 = fadd float %88, %81
>  %90 = fmul float %49, %26
>  %91 = fadd float %90, %83
>  %92 = fmul float %53, %27
>  %93 = fmul float %53, %28
>  %94 = fmul float %53, %29
>  %95 = fmul float %53, %30
>  %96 = fmul float %54, %31
>  %97 = fadd float %96, %92
>  %98 = fmul float %54, %32
>  %99 = fadd float %98, %93
>  %100 = fmul float %54, %33
>  %101 = fadd float %100, %94
>  %102 = fmul float %54, %34
>  %103 = fadd float %102, %95
>  %104 = fmul float %55, %35
>  %105 = fadd float %104, %97
>  %106 = fmul float %55, %36
>  %107 = fadd float %106, %99
>  %108 = fmul float %55, %37
>  %109 = fadd float %108, %101
>  %110 = fmul float %55, %38
>  %111 = fadd float %110, %103
>  %112 = fmul float %56, %39
>  %113 = fadd float %112, %105
>  %114 = fmul float %56, %40
>  %115 = fadd float %114, %107
>  %116 = fmul float %56, %41
>  %117 = fadd float %116, %109
>  %118 = fmul float %56, %42
>  %119 = fadd float %118, %111
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %113, float %115, float %117, float %119)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %60, float %61, float %62, float %63)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %85, float %87, float %89, float %91)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL OUT[2], GENERIC[1]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL IN[1], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..1], LOCAL
>  0: TXP TEMP[0].xyz, IN[0], SAMP[1], CUBE
>  1: MOV TEMP[0].xyz, TEMP[0].xyzx
>  2: MOV TEMP[1].xy, IN[1].xyyy
>  3: MOV TEMP[1].w, IN[1].wwww
>  4: TXP TEMP[1].w, TEMP[1], SAMP[0], 2D
>  5: MOV TEMP[0].w, TEMP[1].wwww
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %35 = fdiv float %28, %31
>  %36 = fdiv float %29, %31
>  %37 = fdiv float %30, %31
>  %38 = insertelement <4 x float> undef, float %35, i32 0
>  %39 = insertelement <4 x float> %38, float %36, i32 1
>  %40 = insertelement <4 x float> %39, float %37, i32 2
>  %41 = insertelement <4 x float> %40, float 1.000000e+00, i32 3
>  %42 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %41)
>  %43 = extractelement <4 x float> %42, i32 0
>  %44 = extractelement <4 x float> %42, i32 1
>  %45 = extractelement <4 x float> %42, i32 2
>  %46 = extractelement <4 x float> %42, i32 3
>  %47 = call float @fabs(float %45)
>  %48 = fdiv float 1.000000e+00, %47
>  %49 = fmul float %43, %48
>  %50 = fadd float %49, 1.500000e+00
>  %51 = fmul float %44, %48
>  %52 = fadd float %51, 1.500000e+00
>  %53 = bitcast float %52 to i32
>  %54 = bitcast float %50 to i32
>  %55 = bitcast float %46 to i32
>  %56 = insertelement <4 x i32> undef, i32 %53, i32 0
>  %57 = insertelement <4 x i32> %56, i32 %54, i32 1
>  %58 = insertelement <4 x i32> %57, i32 %55, i32 2
>  %59 = insertelement <4 x i32> %58, i32 undef, i32 3
>  %60 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %59, <32 x i8> %25, <16 x i8> %27, i32 4)
>  %61 = extractelement <4 x float> %60, i32 0
>  %62 = extractelement <4 x float> %60, i32 1
>  %63 = extractelement <4 x float> %60, i32 2
>  %64 = fdiv float %32, %34
>  %65 = fdiv float %33, %34
>  %66 = bitcast float %64 to i32
>  %67 = bitcast float %65 to i32
>  %68 = insertelement <2 x i32> undef, i32 %66, i32 0
>  %69 = insertelement <2 x i32> %68, i32 %67, i32 1
>  %70 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %69, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %71 = extractelement <4 x float> %70, i32 3
>  %72 = call i32 @llvm.SI.packf16(float %61, float %62)
>  %73 = bitcast i32 %72 to float
>  %74 = call i32 @llvm.SI.packf16(float %63, float %71)
>  %75 = bitcast i32 %74 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %73, float %75, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0300
>c80d0301
>7e0c5503
>10060d02
>c81c0000
>c81d0001
>10040d07
>c81c0200
>c81d0201
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c0840304
>c0c60508
>bf8c007f
>f0800700
>00430207
>bf8c0770
>5e0a0702
>c8180500
>c8190501
>c81c0700
>c81d0701
>7e105507
>100e1106
>c8240400
>c8250401
>100c1109
>c0800300
>c0c20500
>bf8c007f
>f0800800
>00010006
>bf8c0770
>5e000104
>f8001c0f
>00050005
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL OUT[2], GENERIC[1]
>DCL CONST[0..14]
>DCL TEMP[0..4]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[1].x, IN[1], CONST[4]
>  5: DP3 TEMP[1].y, IN[1], CONST[5]
>  6: DP3 TEMP[1].z, IN[1], CONST[6]
>  7: DP3 TEMP[2].x, TEMP[1], TEMP[1]
>  8: RSQ TEMP[2].x, |TEMP[2]|
>  9: MUL TEMP[1], TEMP[1], TEMP[2].xxxx
> 10: MUL TEMP[2], IN[0].xxxx, CONST[7]
> 11: MAD TEMP[2], IN[0].yyyy, CONST[8], TEMP[2]
> 12: MAD TEMP[2], IN[0].zzzz, CONST[9], TEMP[2]
> 13: MAD TEMP[2], IN[0].wwww, CONST[10], TEMP[2]
> 14: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 15: RSQ TEMP[3].x, |TEMP[3]|
> 16: MUL TEMP[4], TEMP[2], TEMP[3].xxxx
> 17: DP3 TEMP[3], TEMP[1], TEMP[4]
> 18: ADD TEMP[3], TEMP[3], TEMP[3]
> 19: MAD TEMP[0].xyz, -TEMP[3], TEMP[1], TEMP[4]
> 20: MOV TEMP[0].w, IN[2]
> 21: MUL TEMP[3], TEMP[0].xxxx, CONST[11]
> 22: MAD TEMP[3], TEMP[0].yyyy, CONST[12], TEMP[3]
> 23: MAD TEMP[3], TEMP[0].zzzz, CONST[13], TEMP[3]
> 24: MAD OUT[1], TEMP[0].wwww, CONST[14], TEMP[3]
> 25: MOV OUT[2], IN[3]
> 26: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
>  %64 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
>  %66 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %65, i32 0, i32 %5)
>  %67 = extractelement <4 x float> %66, i32 0
>  %68 = extractelement <4 x float> %66, i32 1
>  %69 = extractelement <4 x float> %66, i32 2
>  %70 = extractelement <4 x float> %66, i32 3
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %78 = load <16 x i8> addrspace(2)* %77, !tbaa !0
>  %79 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %78, i32 0, i32 %5)
>  %80 = extractelement <4 x float> %79, i32 3
>  %81 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %82 = load <16 x i8> addrspace(2)* %81, !tbaa !0
>  %83 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %82, i32 0, i32 %5)
>  %84 = extractelement <4 x float> %83, i32 0
>  %85 = extractelement <4 x float> %83, i32 1
>  %86 = extractelement <4 x float> %83, i32 2
>  %87 = extractelement <4 x float> %83, i32 3
>  %88 = fmul float %67, %11
>  %89 = fmul float %67, %12
>  %90 = fmul float %67, %13
>  %91 = fmul float %67, %14
>  %92 = fmul float %68, %15
>  %93 = fadd float %92, %88
>  %94 = fmul float %68, %16
>  %95 = fadd float %94, %89
>  %96 = fmul float %68, %17
>  %97 = fadd float %96, %90
>  %98 = fmul float %68, %18
>  %99 = fadd float %98, %91
>  %100 = fmul float %69, %19
>  %101 = fadd float %100, %93
>  %102 = fmul float %69, %20
>  %103 = fadd float %102, %95
>  %104 = fmul float %69, %21
>  %105 = fadd float %104, %97
>  %106 = fmul float %69, %22
>  %107 = fadd float %106, %99
>  %108 = fmul float %70, %23
>  %109 = fadd float %108, %101
>  %110 = fmul float %70, %24
>  %111 = fadd float %110, %103
>  %112 = fmul float %70, %25
>  %113 = fadd float %112, %105
>  %114 = fmul float %70, %26
>  %115 = fadd float %114, %107
>  %116 = fmul float %74, %27
>  %117 = fmul float %75, %28
>  %118 = fadd float %117, %116
>  %119 = fmul float %76, %29
>  %120 = fadd float %118, %119
>  %121 = fmul float %74, %30
>  %122 = fmul float %75, %31
>  %123 = fadd float %122, %121
>  %124 = fmul float %76, %32
>  %125 = fadd float %123, %124
>  %126 = fmul float %74, %33
>  %127 = fmul float %75, %34
>  %128 = fadd float %127, %126
>  %129 = fmul float %76, %35
>  %130 = fadd float %128, %129
>  %131 = fmul float %120, %120
>  %132 = fmul float %125, %125
>  %133 = fadd float %132, %131
>  %134 = fmul float %130, %130
>  %135 = fadd float %133, %134
>  %136 = call float @fabs(float %135)
>  %137 = call float @llvm.AMDGPU.rsq(float %136)
>  %138 = fmul float %120, %137
>  %139 = fmul float %125, %137
>  %140 = fmul float %130, %137
>  %141 = fmul float %67, %36
>  %142 = fmul float %67, %37
>  %143 = fmul float %67, %38
>  %144 = fmul float %68, %39
>  %145 = fadd float %144, %141
>  %146 = fmul float %68, %40
>  %147 = fadd float %146, %142
>  %148 = fmul float %68, %41
>  %149 = fadd float %148, %143
>  %150 = fmul float %69, %42
>  %151 = fadd float %150, %145
>  %152 = fmul float %69, %43
>  %153 = fadd float %152, %147
>  %154 = fmul float %69, %44
>  %155 = fadd float %154, %149
>  %156 = fmul float %70, %45
>  %157 = fadd float %156, %151
>  %158 = fmul float %70, %46
>  %159 = fadd float %158, %153
>  %160 = fmul float %70, %47
>  %161 = fadd float %160, %155
>  %162 = fmul float %157, %157
>  %163 = fmul float %159, %159
>  %164 = fadd float %163, %162
>  %165 = fmul float %161, %161
>  %166 = fadd float %164, %165
>  %167 = call float @fabs(float %166)
>  %168 = call float @llvm.AMDGPU.rsq(float %167)
>  %169 = fmul float %157, %168
>  %170 = fmul float %159, %168
>  %171 = fmul float %161, %168
>  %172 = fmul float %138, %169
>  %173 = fmul float %139, %170
>  %174 = fadd float %173, %172
>  %175 = fmul float %140, %171
>  %176 = fadd float %174, %175
>  %177 = fadd float %176, %176
>  %178 = fadd float %176, %176
>  %179 = fadd float %176, %176
>  %180 = fsub float -0.000000e+00, %177
>  %181 = fmul float %180, %138
>  %182 = fadd float %181, %169
>  %183 = fsub float -0.000000e+00, %178
>  %184 = fmul float %183, %139
>  %185 = fadd float %184, %170
>  %186 = fsub float -0.000000e+00, %179
>  %187 = fmul float %186, %140
>  %188 = fadd float %187, %171
>  %189 = fmul float %182, %48
>  %190 = fmul float %182, %49
>  %191 = fmul float %182, %50
>  %192 = fmul float %182, %51
>  %193 = fmul float %185, %52
>  %194 = fadd float %193, %189
>  %195 = fmul float %185, %53
>  %196 = fadd float %195, %190
>  %197 = fmul float %185, %54
>  %198 = fadd float %197, %191
>  %199 = fmul float %185, %55
>  %200 = fadd float %199, %192
>  %201 = fmul float %188, %56
>  %202 = fadd float %201, %194
>  %203 = fmul float %188, %57
>  %204 = fadd float %203, %196
>  %205 = fmul float %188, %58
>  %206 = fadd float %205, %198
>  %207 = fmul float %188, %59
>  %208 = fadd float %207, %200
>  %209 = fmul float %80, %60
>  %210 = fadd float %209, %202
>  %211 = fmul float %80, %61
>  %212 = fadd float %211, %204
>  %213 = fmul float %80, %62
>  %214 = fadd float %213, %206
>  %215 = fmul float %80, %63
>  %216 = fadd float %215, %208
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %210, float %212, float %214, float %216)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %84, float %85, float %86, float %87)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %109, float %111, float %113, float %115)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020114
>bf8c007f
>100a0204
>c2020115
>bf8c007f
>d2820005
>04140902
>c2020116
>bf8c007f
>d2820005
>04140903
>c2020110
>bf8c007f
>100c0204
>c2020111
>bf8c007f
>d2820006
>04180902
>c2020112
>bf8c007f
>d2820006
>04180903
>100e0d06
>d2820008
>041e0b05
>c2020118
>bf8c007f
>100e0204
>c2020119
>bf8c007f
>d2820007
>041c0902
>c202011a
>bf8c007f
>d2820007
>041c0903
>d2820001
>04220f07
>d2060101
>02010101
>7e105b01
>100c1106
>c0840700
>bf8c007f
>e00c2000
>80020100
>c202011d
>bf8c0070
>10120204
>c2020121
>bf8c007f
>d2820009
>04240902
>c2020125
>bf8c007f
>d2820009
>04240903
>c2020129
>bf8c007f
>d2820009
>04240904
>c202011c
>bf8c007f
>10140204
>c2020120
>bf8c007f
>d282000a
>04280902
>c2020124
>bf8c007f
>d282000a
>04280903
>c2020128
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c202011e
>bf8c007f
>10160204
>c2020122
>bf8c007f
>d282000b
>042c0902
>c2020126
>bf8c007f
>d282000b
>042c0903
>c202012a
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101c1506
>100a1105
>101a1909
>d2820009
>043a1b05
>100e1107
>1010190b
>d2820009
>04261107
>06121309
>100a0b09
>080a0b0d
>100c0d09
>080c0d0a
>c202012f
>bf8c007f
>10140c04
>c2020133
>bf8c007f
>d282000a
>04280905
>100e0f09
>080e0f08
>c2020137
>bf8c007f
>d282000c
>04280907
>c0840708
>bf8c007f
>e00c2000
>80020800
>c202013b
>bf8c0070
>d282000c
>0430090b
>c202012e
>bf8c007f
>101a0c04
>c2020132
>bf8c007f
>d282000d
>04340905
>c2020136
>bf8c007f
>d282000d
>04340907
>c202013a
>bf8c007f
>d282000d
>0434090b
>c202012d
>bf8c007f
>101c0c04
>c2020131
>bf8c007f
>d282000e
>04380905
>c2020135
>bf8c007f
>d282000e
>04380907
>c2020139
>bf8c007f
>d282000e
>0438090b
>c202012c
>bf8c007f
>100c0c04
>c2020130
>bf8c007f
>d2820005
>04180905
>c2020134
>bf8c007f
>d2820005
>04140907
>c2020138
>bf8c007f
>d2820005
>0414090b
>f800020f
>0c0d0e05
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..19]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: MOV OUT[2], IN[3]
> 41: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = extractelement <4 x float> %73, i32 3
>  %78 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %79 = load <16 x i8> addrspace(2)* %78, !tbaa !0
>  %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %79, i32 0, i32 %5)
>  %81 = extractelement <4 x float> %80, i32 0
>  %82 = extractelement <4 x float> %80, i32 1
>  %83 = extractelement <4 x float> %80, i32 2
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = extractelement <4 x float> %92, i32 3
>  %97 = fmul float %74, %11
>  %98 = fmul float %74, %12
>  %99 = fmul float %74, %13
>  %100 = fmul float %74, %14
>  %101 = fmul float %75, %15
>  %102 = fadd float %101, %97
>  %103 = fmul float %75, %16
>  %104 = fadd float %103, %98
>  %105 = fmul float %75, %17
>  %106 = fadd float %105, %99
>  %107 = fmul float %75, %18
>  %108 = fadd float %107, %100
>  %109 = fmul float %76, %19
>  %110 = fadd float %109, %102
>  %111 = fmul float %76, %20
>  %112 = fadd float %111, %104
>  %113 = fmul float %76, %21
>  %114 = fadd float %113, %106
>  %115 = fmul float %76, %22
>  %116 = fadd float %115, %108
>  %117 = fmul float %77, %23
>  %118 = fadd float %117, %110
>  %119 = fmul float %77, %24
>  %120 = fadd float %119, %112
>  %121 = fmul float %77, %25
>  %122 = fadd float %121, %114
>  %123 = fmul float %77, %26
>  %124 = fadd float %123, %116
>  %125 = fmul float %81, %27
>  %126 = fmul float %82, %28
>  %127 = fadd float %126, %125
>  %128 = fmul float %83, %29
>  %129 = fadd float %127, %128
>  %130 = fmul float %81, %30
>  %131 = fmul float %82, %31
>  %132 = fadd float %131, %130
>  %133 = fmul float %83, %32
>  %134 = fadd float %132, %133
>  %135 = fmul float %81, %33
>  %136 = fmul float %82, %34
>  %137 = fadd float %136, %135
>  %138 = fmul float %83, %35
>  %139 = fadd float %137, %138
>  %140 = fmul float %129, %129
>  %141 = fmul float %134, %134
>  %142 = fadd float %141, %140
>  %143 = fmul float %139, %139
>  %144 = fadd float %142, %143
>  %145 = call float @fabs(float %144)
>  %146 = call float @llvm.AMDGPU.rsq(float %145)
>  %147 = fmul float %129, %146
>  %148 = fmul float %134, %146
>  %149 = fmul float %139, %146
>  %150 = fmul float %37, %40
>  %151 = fadd float %150, %87
>  %152 = fmul float %38, %41
>  %153 = fadd float %152, %88
>  %154 = fmul float %39, %42
>  %155 = fadd float %154, %89
>  %156 = call float @llvm.AMDIL.clamp.(float %151, float 0.000000e+00, float 1.000000e+00)
>  %157 = call float @llvm.AMDIL.clamp.(float %153, float 0.000000e+00, float 1.000000e+00)
>  %158 = call float @llvm.AMDIL.clamp.(float %155, float 0.000000e+00, float 1.000000e+00)
>  %159 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %160 = fmul float %74, %47
>  %161 = fmul float %74, %48
>  %162 = fmul float %74, %49
>  %163 = fmul float %75, %50
>  %164 = fadd float %163, %160
>  %165 = fmul float %75, %51
>  %166 = fadd float %165, %161
>  %167 = fmul float %75, %52
>  %168 = fadd float %167, %162
>  %169 = fmul float %76, %53
>  %170 = fadd float %169, %164
>  %171 = fmul float %76, %54
>  %172 = fadd float %171, %166
>  %173 = fmul float %76, %55
>  %174 = fadd float %173, %168
>  %175 = fmul float %77, %56
>  %176 = fadd float %175, %170
>  %177 = fmul float %77, %57
>  %178 = fadd float %177, %172
>  %179 = fmul float %77, %58
>  %180 = fadd float %179, %174
>  %181 = fsub float %44, %176
>  %182 = fsub float %45, %178
>  %183 = fsub float %46, %180
>  %184 = fmul float %181, %181
>  %185 = fmul float %182, %182
>  %186 = fadd float %185, %184
>  %187 = fmul float %183, %183
>  %188 = fadd float %186, %187
>  %189 = call float @fabs(float %188)
>  %190 = call float @llvm.AMDGPU.rsq(float %189)
>  %191 = fmul float %181, %190
>  %192 = fmul float %182, %190
>  %193 = fmul float %183, %190
>  %194 = fdiv float 1.000000e+00, %190
>  %195 = fmul float %190, %194
>  %196 = fmul float %194, %194
>  %197 = fmul float %59, %195
>  %198 = fmul float %60, %194
>  %199 = fadd float %198, %197
>  %200 = fmul float %61, %196
>  %201 = fadd float %199, %200
>  %202 = fdiv float 1.000000e+00, %201
>  %203 = fmul float %176, %176
>  %204 = fmul float %178, %178
>  %205 = fadd float %204, %203
>  %206 = fmul float %180, %180
>  %207 = fadd float %205, %206
>  %208 = call float @fabs(float %207)
>  %209 = call float @llvm.AMDGPU.rsq(float %208)
>  %210 = fmul float %176, %209
>  %211 = fmul float %178, %209
>  %212 = fmul float %180, %209
>  %213 = fsub float %191, %210
>  %214 = fsub float %192, %211
>  %215 = fsub float %193, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fmul float %147, %191
>  %227 = fmul float %148, %192
>  %228 = fadd float %227, %226
>  %229 = fmul float %149, %193
>  %230 = fadd float %228, %229
>  %231 = fmul float %147, %223
>  %232 = fmul float %148, %224
>  %233 = fadd float %232, %231
>  %234 = fmul float %149, %225
>  %235 = fadd float %233, %234
>  %236 = fcmp uge float %230, 0.000000e+00
>  %237 = select i1 %236, float %230, float 0.000000e+00
>  %238 = fcmp uge float %235, 0.000000e+00
>  %239 = select i1 %238, float %235, float 0.000000e+00
>  %240 = call float @llvm.pow.f32(float %239, float %36)
>  %241 = call float @llvm.AMDGPU.cndlt(float %230, float 0.000000e+00, float %240)
>  %242 = fmul float 1.000000e+00, %202
>  %243 = fmul float %237, %202
>  %244 = fmul float %241, %202
>  %245 = fmul float %242, %62
>  %246 = fadd float %245, %151
>  %247 = fmul float %242, %63
>  %248 = fadd float %247, %153
>  %249 = fmul float %242, %64
>  %250 = fadd float %249, %155
>  %251 = fmul float %243, %65
>  %252 = fadd float %251, %246
>  %253 = fmul float %243, %66
>  %254 = fadd float %253, %248
>  %255 = fmul float %243, %67
>  %256 = fadd float %255, %250
>  %257 = fmul float %244, %68
>  %258 = fadd float %257, %252
>  %259 = fmul float %244, %69
>  %260 = fadd float %259, %254
>  %261 = fmul float %244, %70
>  %262 = fadd float %261, %256
>  %263 = call float @llvm.AMDIL.clamp.(float %258, float 0.000000e+00, float 1.000000e+00)
>  %264 = call float @llvm.AMDIL.clamp.(float %260, float 0.000000e+00, float 1.000000e+00)
>  %265 = call float @llvm.AMDIL.clamp.(float %262, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %263, float %264, float %265, float %159)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %93, float %94, float %95, float %96)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %118, float %120, float %122, float %124)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820005
>04140904
>c2020130
>bf8c007f
>100c0204
>c2020134
>bf8c007f
>d2820006
>04180902
>c2020138
>bf8c007f
>d2820006
>04180903
>c202013c
>bf8c007f
>d2820007
>04180904
>100c0f07
>d2820006
>041a0b05
>c2020132
>bf8c007f
>10100204
>c2020136
>bf8c007f
>d2820008
>04200902
>c202013a
>bf8c007f
>d2820008
>04200903
>c202013e
>bf8c007f
>d2820008
>04200904
>d2820006
>041a1108
>d2060106
>02010106
>7e125b06
>10141305
>c202012d
>bf8c007f
>080c0a04
>c202012c
>bf8c007f
>081a0e04
>100a1b0d
>d2820005
>04160d06
>c202012e
>bf8c007f
>08161004
>d2820005
>0416170b
>d2060105
>02010105
>7e0a5b05
>100c0b06
>08181506
>10141307
>100e0b0d
>081a1507
>10141b0d
>d282000a
>042a190c
>10121308
>10100b0b
>08121308
>d282000a
>042a1309
>d206010a
>0201010a
>7e145b0a
>1016150c
>1018150d
>c0840704
>bf8c007f
>e00c2000
>80020d00
>c2020114
>bf8c0070
>10221a04
>c2020115
>bf8c007f
>d2820011
>0444090e
>c2020116
>bf8c007f
>d2820011
>0444090f
>c2020110
>bf8c007f
>10241a04
>c2020111
>bf8c007f
>d2820012
>0448090e
>c2020112
>bf8c007f
>d2820012
>0448090f
>10262512
>d2820013
>044e2311
>c2020118
>bf8c007f
>10281a04
>c2020119
>bf8c007f
>d2820014
>0450090e
>c202011a
>bf8c007f
>d282000e
>0450090f
>d282000d
>044e1d0e
>d206010d
>0201010d
>7e1e5b0d
>101a1f12
>1020190d
>10181f11
>d282000b
>0442170c
>10141509
>10121f0e
>d282000a
>042e1509
>d00c0004
>0201010a
>d200000a
>00121480
>7e144f0a
>c202011c
>bf8c007f
>0e141404
>7e144b0a
>100e0f0d
>d2820006
>041e0d0c
>d2820007
>041a1109
>d0080004
>02020e80
>d2000008
>0011010a
>7e0c5505
>100a0d05
>c2020140
>bf8c007f
>100a0a04
>c2020141
>bf8c007f
>d2820005
>04160c04
>100c0d06
>c2020142
>bf8c007f
>d2820005
>04160c04
>7e0c5505
>100a0d08
>d00c0004
>02010107
>d2000007
>00120e80
>100e0d07
>c0840708
>bf8c007f
>e00c2000
>80020800
>c2020122
>c2028126
>bf8c0070
>7e180205
>d282000c
>042a1804
>c2020146
>bf8c007f
>d282000c
>04300906
>c202014a
>bf8c007f
>d282000c
>04300907
>c202014e
>bf8c007f
>d282000c
>04300905
>d206080c
>0201010c
>c2020121
>c2028125
>bf8c007f
>7e1a0205
>d282000d
>04261a04
>c2020145
>bf8c007f
>d282000d
>04340906
>c2020149
>bf8c007f
>d282000d
>04340907
>c202014d
>bf8c007f
>d282000d
>04340905
>d206080d
>0201010d
>c2020120
>c2028124
>bf8c007f
>7e1c0205
>d2820008
>04221c04
>c2020144
>bf8c007f
>d2820006
>04200906
>c2020148
>bf8c007f
>d2820006
>04180907
>c202014c
>bf8c007f
>d2820005
>04180905
>d2060805
>02010105
>c202012b
>bf8c007f
>d2060806
>02010004
>f800020f
>060c0d05
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..23]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: MUL TEMP[1], IN[3].xxxx, CONST[20]
> 41: MAD TEMP[1], IN[3].yyyy, CONST[21], TEMP[1]
> 42: MAD TEMP[1], IN[3].zzzz, CONST[22], TEMP[1]
> 43: MAD OUT[2], IN[3].wwww, CONST[23], TEMP[1]
> 44: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %87 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
>  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %5)
>  %90 = extractelement <4 x float> %89, i32 0
>  %91 = extractelement <4 x float> %89, i32 1
>  %92 = extractelement <4 x float> %89, i32 2
>  %93 = extractelement <4 x float> %89, i32 3
>  %94 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %95 = load <16 x i8> addrspace(2)* %94, !tbaa !0
>  %96 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %95, i32 0, i32 %5)
>  %97 = extractelement <4 x float> %96, i32 0
>  %98 = extractelement <4 x float> %96, i32 1
>  %99 = extractelement <4 x float> %96, i32 2
>  %100 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %101 = load <16 x i8> addrspace(2)* %100, !tbaa !0
>  %102 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %101, i32 0, i32 %5)
>  %103 = extractelement <4 x float> %102, i32 0
>  %104 = extractelement <4 x float> %102, i32 1
>  %105 = extractelement <4 x float> %102, i32 2
>  %106 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %107 = load <16 x i8> addrspace(2)* %106, !tbaa !0
>  %108 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %107, i32 0, i32 %5)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = extractelement <4 x float> %108, i32 1
>  %111 = extractelement <4 x float> %108, i32 2
>  %112 = extractelement <4 x float> %108, i32 3
>  %113 = fmul float %90, %11
>  %114 = fmul float %90, %12
>  %115 = fmul float %90, %13
>  %116 = fmul float %90, %14
>  %117 = fmul float %91, %15
>  %118 = fadd float %117, %113
>  %119 = fmul float %91, %16
>  %120 = fadd float %119, %114
>  %121 = fmul float %91, %17
>  %122 = fadd float %121, %115
>  %123 = fmul float %91, %18
>  %124 = fadd float %123, %116
>  %125 = fmul float %92, %19
>  %126 = fadd float %125, %118
>  %127 = fmul float %92, %20
>  %128 = fadd float %127, %120
>  %129 = fmul float %92, %21
>  %130 = fadd float %129, %122
>  %131 = fmul float %92, %22
>  %132 = fadd float %131, %124
>  %133 = fmul float %93, %23
>  %134 = fadd float %133, %126
>  %135 = fmul float %93, %24
>  %136 = fadd float %135, %128
>  %137 = fmul float %93, %25
>  %138 = fadd float %137, %130
>  %139 = fmul float %93, %26
>  %140 = fadd float %139, %132
>  %141 = fmul float %97, %27
>  %142 = fmul float %98, %28
>  %143 = fadd float %142, %141
>  %144 = fmul float %99, %29
>  %145 = fadd float %143, %144
>  %146 = fmul float %97, %30
>  %147 = fmul float %98, %31
>  %148 = fadd float %147, %146
>  %149 = fmul float %99, %32
>  %150 = fadd float %148, %149
>  %151 = fmul float %97, %33
>  %152 = fmul float %98, %34
>  %153 = fadd float %152, %151
>  %154 = fmul float %99, %35
>  %155 = fadd float %153, %154
>  %156 = fmul float %145, %145
>  %157 = fmul float %150, %150
>  %158 = fadd float %157, %156
>  %159 = fmul float %155, %155
>  %160 = fadd float %158, %159
>  %161 = call float @fabs(float %160)
>  %162 = call float @llvm.AMDGPU.rsq(float %161)
>  %163 = fmul float %145, %162
>  %164 = fmul float %150, %162
>  %165 = fmul float %155, %162
>  %166 = fmul float %37, %40
>  %167 = fadd float %166, %103
>  %168 = fmul float %38, %41
>  %169 = fadd float %168, %104
>  %170 = fmul float %39, %42
>  %171 = fadd float %170, %105
>  %172 = call float @llvm.AMDIL.clamp.(float %167, float 0.000000e+00, float 1.000000e+00)
>  %173 = call float @llvm.AMDIL.clamp.(float %169, float 0.000000e+00, float 1.000000e+00)
>  %174 = call float @llvm.AMDIL.clamp.(float %171, float 0.000000e+00, float 1.000000e+00)
>  %175 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %176 = fmul float %90, %47
>  %177 = fmul float %90, %48
>  %178 = fmul float %90, %49
>  %179 = fmul float %91, %50
>  %180 = fadd float %179, %176
>  %181 = fmul float %91, %51
>  %182 = fadd float %181, %177
>  %183 = fmul float %91, %52
>  %184 = fadd float %183, %178
>  %185 = fmul float %92, %53
>  %186 = fadd float %185, %180
>  %187 = fmul float %92, %54
>  %188 = fadd float %187, %182
>  %189 = fmul float %92, %55
>  %190 = fadd float %189, %184
>  %191 = fmul float %93, %56
>  %192 = fadd float %191, %186
>  %193 = fmul float %93, %57
>  %194 = fadd float %193, %188
>  %195 = fmul float %93, %58
>  %196 = fadd float %195, %190
>  %197 = fsub float %44, %192
>  %198 = fsub float %45, %194
>  %199 = fsub float %46, %196
>  %200 = fmul float %197, %197
>  %201 = fmul float %198, %198
>  %202 = fadd float %201, %200
>  %203 = fmul float %199, %199
>  %204 = fadd float %202, %203
>  %205 = call float @fabs(float %204)
>  %206 = call float @llvm.AMDGPU.rsq(float %205)
>  %207 = fmul float %197, %206
>  %208 = fmul float %198, %206
>  %209 = fmul float %199, %206
>  %210 = fdiv float 1.000000e+00, %206
>  %211 = fmul float %206, %210
>  %212 = fmul float %210, %210
>  %213 = fmul float %59, %211
>  %214 = fmul float %60, %210
>  %215 = fadd float %214, %213
>  %216 = fmul float %61, %212
>  %217 = fadd float %215, %216
>  %218 = fdiv float 1.000000e+00, %217
>  %219 = fmul float %192, %192
>  %220 = fmul float %194, %194
>  %221 = fadd float %220, %219
>  %222 = fmul float %196, %196
>  %223 = fadd float %221, %222
>  %224 = call float @fabs(float %223)
>  %225 = call float @llvm.AMDGPU.rsq(float %224)
>  %226 = fmul float %192, %225
>  %227 = fmul float %194, %225
>  %228 = fmul float %196, %225
>  %229 = fsub float %207, %226
>  %230 = fsub float %208, %227
>  %231 = fsub float %209, %228
>  %232 = fmul float %229, %229
>  %233 = fmul float %230, %230
>  %234 = fadd float %233, %232
>  %235 = fmul float %231, %231
>  %236 = fadd float %234, %235
>  %237 = call float @fabs(float %236)
>  %238 = call float @llvm.AMDGPU.rsq(float %237)
>  %239 = fmul float %229, %238
>  %240 = fmul float %230, %238
>  %241 = fmul float %231, %238
>  %242 = fmul float %163, %207
>  %243 = fmul float %164, %208
>  %244 = fadd float %243, %242
>  %245 = fmul float %165, %209
>  %246 = fadd float %244, %245
>  %247 = fmul float %163, %239
>  %248 = fmul float %164, %240
>  %249 = fadd float %248, %247
>  %250 = fmul float %165, %241
>  %251 = fadd float %249, %250
>  %252 = fcmp uge float %246, 0.000000e+00
>  %253 = select i1 %252, float %246, float 0.000000e+00
>  %254 = fcmp uge float %251, 0.000000e+00
>  %255 = select i1 %254, float %251, float 0.000000e+00
>  %256 = call float @llvm.pow.f32(float %255, float %36)
>  %257 = call float @llvm.AMDGPU.cndlt(float %246, float 0.000000e+00, float %256)
>  %258 = fmul float 1.000000e+00, %218
>  %259 = fmul float %253, %218
>  %260 = fmul float %257, %218
>  %261 = fmul float %258, %62
>  %262 = fadd float %261, %167
>  %263 = fmul float %258, %63
>  %264 = fadd float %263, %169
>  %265 = fmul float %258, %64
>  %266 = fadd float %265, %171
>  %267 = fmul float %259, %65
>  %268 = fadd float %267, %262
>  %269 = fmul float %259, %66
>  %270 = fadd float %269, %264
>  %271 = fmul float %259, %67
>  %272 = fadd float %271, %266
>  %273 = fmul float %260, %68
>  %274 = fadd float %273, %268
>  %275 = fmul float %260, %69
>  %276 = fadd float %275, %270
>  %277 = fmul float %260, %70
>  %278 = fadd float %277, %272
>  %279 = call float @llvm.AMDIL.clamp.(float %274, float 0.000000e+00, float 1.000000e+00)
>  %280 = call float @llvm.AMDIL.clamp.(float %276, float 0.000000e+00, float 1.000000e+00)
>  %281 = call float @llvm.AMDIL.clamp.(float %278, float 0.000000e+00, float 1.000000e+00)
>  %282 = fmul float %109, %71
>  %283 = fmul float %109, %72
>  %284 = fmul float %109, %73
>  %285 = fmul float %109, %74
>  %286 = fmul float %110, %75
>  %287 = fadd float %286, %282
>  %288 = fmul float %110, %76
>  %289 = fadd float %288, %283
>  %290 = fmul float %110, %77
>  %291 = fadd float %290, %284
>  %292 = fmul float %110, %78
>  %293 = fadd float %292, %285
>  %294 = fmul float %111, %79
>  %295 = fadd float %294, %287
>  %296 = fmul float %111, %80
>  %297 = fadd float %296, %289
>  %298 = fmul float %111, %81
>  %299 = fadd float %298, %291
>  %300 = fmul float %111, %82
>  %301 = fadd float %300, %293
>  %302 = fmul float %112, %83
>  %303 = fadd float %302, %295
>  %304 = fmul float %112, %84
>  %305 = fadd float %304, %297
>  %306 = fmul float %112, %85
>  %307 = fadd float %306, %299
>  %308 = fmul float %112, %86
>  %309 = fadd float %308, %301
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %279, float %280, float %281, float %175)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %303, float %305, float %307, float %309)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %134, float %136, float %138, float %140)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820005
>04140904
>c2020130
>bf8c007f
>100c0204
>c2020134
>bf8c007f
>d2820006
>04180902
>c2020138
>bf8c007f
>d2820006
>04180903
>c202013c
>bf8c007f
>d2820007
>04180904
>100c0f07
>d2820006
>041a0b05
>c2020132
>bf8c007f
>10100204
>c2020136
>bf8c007f
>d2820008
>04200902
>c202013a
>bf8c007f
>d2820008
>04200903
>c202013e
>bf8c007f
>d2820008
>04200904
>d2820006
>041a1108
>d2060106
>02010106
>7e125b06
>10141305
>c202012d
>bf8c007f
>080c0a04
>c202012c
>bf8c007f
>081a0e04
>100a1b0d
>d2820005
>04160d06
>c202012e
>bf8c007f
>08161004
>d2820005
>0416170b
>d2060105
>02010105
>7e0a5b05
>100c0b06
>08181506
>10141307
>100e0b0d
>081a1507
>10141b0d
>d282000a
>042a190c
>10121308
>10100b0b
>08121308
>d282000a
>042a1309
>d206010a
>0201010a
>7e145b0a
>1016150c
>1018150d
>c0840704
>bf8c007f
>e00c2000
>80020d00
>c2020114
>bf8c0070
>10221a04
>c2020115
>bf8c007f
>d2820011
>0444090e
>c2020116
>bf8c007f
>d2820011
>0444090f
>c2020110
>bf8c007f
>10241a04
>c2020111
>bf8c007f
>d2820012
>0448090e
>c2020112
>bf8c007f
>d2820012
>0448090f
>10262512
>d2820013
>044e2311
>c2020118
>bf8c007f
>10281a04
>c2020119
>bf8c007f
>d2820014
>0450090e
>c202011a
>bf8c007f
>d282000e
>0450090f
>d282000d
>044e1d0e
>d206010d
>0201010d
>7e1e5b0d
>101a1f12
>1020190d
>10181f11
>d282000b
>0442170c
>10141509
>10121f0e
>d282000a
>042e1509
>d00c0004
>0201010a
>d200000a
>00121480
>7e144f0a
>c202011c
>bf8c007f
>0e141404
>7e144b0a
>100e0f0d
>d2820006
>041e0d0c
>d2820007
>041a1109
>d0080004
>02020e80
>d2000008
>0011010a
>7e0c5505
>100a0d05
>c2020140
>bf8c007f
>100a0a04
>c2020141
>bf8c007f
>d2820005
>04160c04
>100c0d06
>c2020142
>bf8c007f
>d2820005
>04160c04
>7e0c5505
>100a0d08
>d00c0004
>02010107
>d2000007
>00120e80
>100e0d07
>c0840708
>bf8c007f
>e00c2000
>80020800
>c2020122
>c2028126
>bf8c0070
>7e180205
>d282000c
>042a1804
>c2020146
>bf8c007f
>d282000c
>04300906
>c202014a
>bf8c007f
>d282000c
>04300907
>c202014e
>bf8c007f
>d282000c
>04300905
>d206080c
>0201010c
>c2020121
>c2028125
>bf8c007f
>7e1a0205
>d282000d
>04261a04
>c2020145
>bf8c007f
>d282000d
>04340906
>c2020149
>bf8c007f
>d282000d
>04340907
>c202014d
>bf8c007f
>d282000d
>04340905
>d206080d
>0201010d
>c2020120
>c2028124
>bf8c007f
>7e1c0205
>d2820008
>04221c04
>c2020144
>bf8c007f
>d2820006
>04200906
>c2020148
>bf8c007f
>d2820006
>04180907
>c202014c
>bf8c007f
>d2820005
>04180905
>d2060805
>02010105
>c202012b
>bf8c007f
>d2060806
>02010004
>f800020f
>060c0d05
>c082070c
>bf8c000f
>e00c2000
>80010500
>c2020153
>bf8c0070
>10000a04
>c2020157
>bf8c007f
>d2820000
>04000906
>c202015b
>bf8c007f
>d2820000
>04000907
>c202015f
>bf8c007f
>d2820000
>04000908
>c2020152
>bf8c007f
>10120a04
>c2020156
>bf8c007f
>d2820009
>04240906
>c202015a
>bf8c007f
>d2820009
>04240907
>c202015e
>bf8c007f
>d2820009
>04240908
>c2020151
>bf8c007f
>10140a04
>c2020155
>bf8c007f
>d282000a
>04280906
>c2020159
>bf8c007f
>d282000a
>04280907
>c202015d
>bf8c007f
>d282000a
>04280908
>c2020150
>bf8c007f
>10160a04
>c2020154
>bf8c007f
>d282000b
>042c0906
>c2020158
>bf8c007f
>d282000b
>042c0907
>c202015c
>bf8c007f
>d2820005
>042c0908
>f800021f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
>  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
>  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
>  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = extractelement <4 x float> %59, i32 3
>  %64 = fmul float %46, %11
>  %65 = fmul float %46, %12
>  %66 = fmul float %46, %13
>  %67 = fmul float %46, %14
>  %68 = fmul float %47, %15
>  %69 = fadd float %68, %64
>  %70 = fmul float %47, %16
>  %71 = fadd float %70, %65
>  %72 = fmul float %47, %17
>  %73 = fadd float %72, %66
>  %74 = fmul float %47, %18
>  %75 = fadd float %74, %67
>  %76 = fmul float %48, %19
>  %77 = fadd float %76, %69
>  %78 = fmul float %48, %20
>  %79 = fadd float %78, %71
>  %80 = fmul float %48, %21
>  %81 = fadd float %80, %73
>  %82 = fmul float %48, %22
>  %83 = fadd float %82, %75
>  %84 = fmul float %49, %23
>  %85 = fadd float %84, %77
>  %86 = fmul float %49, %24
>  %87 = fadd float %86, %79
>  %88 = fmul float %49, %25
>  %89 = fadd float %88, %81
>  %90 = fmul float %49, %26
>  %91 = fadd float %90, %83
>  %92 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
>  %93 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %94 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
>  %96 = fmul float %60, %27
>  %97 = fmul float %60, %28
>  %98 = fmul float %60, %29
>  %99 = fmul float %60, %30
>  %100 = fmul float %61, %31
>  %101 = fadd float %100, %96
>  %102 = fmul float %61, %32
>  %103 = fadd float %102, %97
>  %104 = fmul float %61, %33
>  %105 = fadd float %104, %98
>  %106 = fmul float %61, %34
>  %107 = fadd float %106, %99
>  %108 = fmul float %62, %35
>  %109 = fadd float %108, %101
>  %110 = fmul float %62, %36
>  %111 = fadd float %110, %103
>  %112 = fmul float %62, %37
>  %113 = fadd float %112, %105
>  %114 = fmul float %62, %38
>  %115 = fadd float %114, %107
>  %116 = fmul float %63, %39
>  %117 = fadd float %116, %109
>  %118 = fmul float %63, %40
>  %119 = fadd float %118, %111
>  %120 = fmul float %63, %41
>  %121 = fadd float %120, %113
>  %122 = fmul float %63, %42
>  %123 = fadd float %122, %115
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %92, float %93, float %94, float %95)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %117, float %119, float %121, float %123)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %85, float %87, float %89, float %91)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800021f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..14]
>DCL TEMP[0..4]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[2]
>  5: MOV OUT[2], IN[3]
>  6: MOV OUT[3], IN[4]
>  7: DP3 TEMP[1].x, IN[1], CONST[4]
>  8: DP3 TEMP[1].y, IN[1], CONST[5]
>  9: DP3 TEMP[1].z, IN[1], CONST[6]
> 10: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 11: RSQ TEMP[2].x, |TEMP[2]|
> 12: MUL TEMP[1], TEMP[1], TEMP[2].xxxx
> 13: MUL TEMP[2], IN[0].xxxx, CONST[7]
> 14: MAD TEMP[2], IN[0].yyyy, CONST[8], TEMP[2]
> 15: MAD TEMP[2], IN[0].zzzz, CONST[9], TEMP[2]
> 16: MAD TEMP[2], IN[0].wwww, CONST[10], TEMP[2]
> 17: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 18: RSQ TEMP[3].x, |TEMP[3]|
> 19: MUL TEMP[4], TEMP[2], TEMP[3].xxxx
> 20: DP3 TEMP[3], TEMP[1], TEMP[4]
> 21: ADD TEMP[3], TEMP[3], TEMP[3]
> 22: MAD TEMP[0].xyz, -TEMP[3], TEMP[1], TEMP[4]
> 23: MOV TEMP[0].w, IN[5]
> 24: MUL TEMP[3], TEMP[0].xxxx, CONST[11]
> 25: MAD TEMP[3], TEMP[0].yyyy, CONST[12], TEMP[3]
> 26: MAD TEMP[3], TEMP[0].zzzz, CONST[13], TEMP[3]
> 27: MAD OUT[4], TEMP[0].wwww, CONST[14], TEMP[3]
> 28: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
>  %64 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
>  %66 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %65, i32 0, i32 %5)
>  %67 = extractelement <4 x float> %66, i32 0
>  %68 = extractelement <4 x float> %66, i32 1
>  %69 = extractelement <4 x float> %66, i32 2
>  %70 = extractelement <4 x float> %66, i32 3
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %78 = load <16 x i8> addrspace(2)* %77, !tbaa !0
>  %79 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %78, i32 0, i32 %5)
>  %80 = extractelement <4 x float> %79, i32 0
>  %81 = extractelement <4 x float> %79, i32 1
>  %82 = extractelement <4 x float> %79, i32 2
>  %83 = extractelement <4 x float> %79, i32 3
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = extractelement <4 x float> %86, i32 3
>  %91 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0
>  %93 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %92, i32 0, i32 %5)
>  %94 = extractelement <4 x float> %93, i32 0
>  %95 = extractelement <4 x float> %93, i32 1
>  %96 = extractelement <4 x float> %93, i32 2
>  %97 = extractelement <4 x float> %93, i32 3
>  %98 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %99 = load <16 x i8> addrspace(2)* %98, !tbaa !0
>  %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %99, i32 0, i32 %5)
>  %101 = extractelement <4 x float> %100, i32 3
>  %102 = fmul float %67, %11
>  %103 = fmul float %67, %12
>  %104 = fmul float %67, %13
>  %105 = fmul float %67, %14
>  %106 = fmul float %68, %15
>  %107 = fadd float %106, %102
>  %108 = fmul float %68, %16
>  %109 = fadd float %108, %103
>  %110 = fmul float %68, %17
>  %111 = fadd float %110, %104
>  %112 = fmul float %68, %18
>  %113 = fadd float %112, %105
>  %114 = fmul float %69, %19
>  %115 = fadd float %114, %107
>  %116 = fmul float %69, %20
>  %117 = fadd float %116, %109
>  %118 = fmul float %69, %21
>  %119 = fadd float %118, %111
>  %120 = fmul float %69, %22
>  %121 = fadd float %120, %113
>  %122 = fmul float %70, %23
>  %123 = fadd float %122, %115
>  %124 = fmul float %70, %24
>  %125 = fadd float %124, %117
>  %126 = fmul float %70, %25
>  %127 = fadd float %126, %119
>  %128 = fmul float %70, %26
>  %129 = fadd float %128, %121
>  %130 = call float @llvm.AMDIL.clamp.(float %80, float 0.000000e+00, float 1.000000e+00)
>  %131 = call float @llvm.AMDIL.clamp.(float %81, float 0.000000e+00, float 1.000000e+00)
>  %132 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %133 = call float @llvm.AMDIL.clamp.(float %83, float 0.000000e+00, float 1.000000e+00)
>  %134 = fmul float %74, %27
>  %135 = fmul float %75, %28
>  %136 = fadd float %135, %134
>  %137 = fmul float %76, %29
>  %138 = fadd float %136, %137
>  %139 = fmul float %74, %30
>  %140 = fmul float %75, %31
>  %141 = fadd float %140, %139
>  %142 = fmul float %76, %32
>  %143 = fadd float %141, %142
>  %144 = fmul float %74, %33
>  %145 = fmul float %75, %34
>  %146 = fadd float %145, %144
>  %147 = fmul float %76, %35
>  %148 = fadd float %146, %147
>  %149 = fmul float %138, %138
>  %150 = fmul float %143, %143
>  %151 = fadd float %150, %149
>  %152 = fmul float %148, %148
>  %153 = fadd float %151, %152
>  %154 = call float @fabs(float %153)
>  %155 = call float @llvm.AMDGPU.rsq(float %154)
>  %156 = fmul float %138, %155
>  %157 = fmul float %143, %155
>  %158 = fmul float %148, %155
>  %159 = fmul float %67, %36
>  %160 = fmul float %67, %37
>  %161 = fmul float %67, %38
>  %162 = fmul float %68, %39
>  %163 = fadd float %162, %159
>  %164 = fmul float %68, %40
>  %165 = fadd float %164, %160
>  %166 = fmul float %68, %41
>  %167 = fadd float %166, %161
>  %168 = fmul float %69, %42
>  %169 = fadd float %168, %163
>  %170 = fmul float %69, %43
>  %171 = fadd float %170, %165
>  %172 = fmul float %69, %44
>  %173 = fadd float %172, %167
>  %174 = fmul float %70, %45
>  %175 = fadd float %174, %169
>  %176 = fmul float %70, %46
>  %177 = fadd float %176, %171
>  %178 = fmul float %70, %47
>  %179 = fadd float %178, %173
>  %180 = fmul float %175, %175
>  %181 = fmul float %177, %177
>  %182 = fadd float %181, %180
>  %183 = fmul float %179, %179
>  %184 = fadd float %182, %183
>  %185 = call float @fabs(float %184)
>  %186 = call float @llvm.AMDGPU.rsq(float %185)
>  %187 = fmul float %175, %186
>  %188 = fmul float %177, %186
>  %189 = fmul float %179, %186
>  %190 = fmul float %156, %187
>  %191 = fmul float %157, %188
>  %192 = fadd float %191, %190
>  %193 = fmul float %158, %189
>  %194 = fadd float %192, %193
>  %195 = fadd float %194, %194
>  %196 = fadd float %194, %194
>  %197 = fadd float %194, %194
>  %198 = fsub float -0.000000e+00, %195
>  %199 = fmul float %198, %156
>  %200 = fadd float %199, %187
>  %201 = fsub float -0.000000e+00, %196
>  %202 = fmul float %201, %157
>  %203 = fadd float %202, %188
>  %204 = fsub float -0.000000e+00, %197
>  %205 = fmul float %204, %158
>  %206 = fadd float %205, %189
>  %207 = fmul float %200, %48
>  %208 = fmul float %200, %49
>  %209 = fmul float %200, %50
>  %210 = fmul float %200, %51
>  %211 = fmul float %203, %52
>  %212 = fadd float %211, %207
>  %213 = fmul float %203, %53
>  %214 = fadd float %213, %208
>  %215 = fmul float %203, %54
>  %216 = fadd float %215, %209
>  %217 = fmul float %203, %55
>  %218 = fadd float %217, %210
>  %219 = fmul float %206, %56
>  %220 = fadd float %219, %212
>  %221 = fmul float %206, %57
>  %222 = fadd float %221, %214
>  %223 = fmul float %206, %58
>  %224 = fadd float %223, %216
>  %225 = fmul float %206, %59
>  %226 = fadd float %225, %218
>  %227 = fmul float %101, %60
>  %228 = fadd float %227, %220
>  %229 = fmul float %101, %61
>  %230 = fadd float %229, %222
>  %231 = fmul float %101, %62
>  %232 = fadd float %231, %224
>  %233 = fmul float %101, %63
>  %234 = fadd float %233, %226
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %130, float %131, float %132, float %133)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %87, float %88, float %89, float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %94, float %95, float %96, float %97)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %228, float %230, float %232, float %234)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %123, float %125, float %127, float %129)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0840710
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800022f
>04030201
>c0840704
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020114
>bf8c007f
>100a0204
>c2020115
>bf8c007f
>d2820005
>04140902
>c2020116
>bf8c007f
>d2820005
>04140903
>c2020110
>bf8c007f
>100c0204
>c2020111
>bf8c007f
>d2820006
>04180902
>c2020112
>bf8c007f
>d2820006
>04180903
>100e0d06
>d2820008
>041e0b05
>c2020118
>bf8c007f
>100e0204
>c2020119
>bf8c007f
>d2820007
>041c0902
>c202011a
>bf8c007f
>d2820007
>041c0903
>d2820001
>04220f07
>d2060101
>02010101
>7e105b01
>100c1106
>c0840700
>bf8c007f
>e00c2000
>80020100
>c202011d
>bf8c0070
>10120204
>c2020121
>bf8c007f
>d2820009
>04240902
>c2020125
>bf8c007f
>d2820009
>04240903
>c2020129
>bf8c007f
>d2820009
>04240904
>c202011c
>bf8c007f
>10140204
>c2020120
>bf8c007f
>d282000a
>04280902
>c2020124
>bf8c007f
>d282000a
>04280903
>c2020128
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c202011e
>bf8c007f
>10160204
>c2020122
>bf8c007f
>d282000b
>042c0902
>c2020126
>bf8c007f
>d282000b
>042c0903
>c202012a
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101c1506
>100a1105
>101a1909
>d2820009
>043a1b05
>100e1107
>1010190b
>d2820009
>04261107
>06121309
>100a0b09
>080a0b0d
>100c0d09
>080c0d0a
>c202012f
>bf8c007f
>10140c04
>c2020133
>bf8c007f
>d282000a
>04280905
>100e0f09
>080e0f08
>c2020137
>bf8c007f
>d282000c
>04280907
>c0820714
>bf8c007f
>e00c2000
>80010800
>c202013b
>bf8c0070
>d2820000
>0430090b
>c202012e
>bf8c007f
>10180c04
>c2020132
>bf8c007f
>d282000c
>04300905
>c2020136
>bf8c007f
>d282000c
>04300907
>c202013a
>bf8c007f
>d282000c
>0430090b
>c202012d
>bf8c007f
>101a0c04
>c2020131
>bf8c007f
>d282000d
>04340905
>c2020135
>bf8c007f
>d282000d
>04340907
>c2020139
>bf8c007f
>d282000d
>0434090b
>c202012c
>bf8c007f
>100c0c04
>c2020130
>bf8c007f
>d2820005
>04180905
>c2020134
>bf8c007f
>d2820005
>04140907
>c2020138
>bf8c007f
>d2820005
>0414090b
>f800023f
>000c0d05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: MUL TEMP[0], IN[3].xxxx, CONST[4]
>  7: MAD TEMP[0], IN[3].yyyy, CONST[5], TEMP[0]
>  8: MAD TEMP[0], IN[3].zzzz, CONST[6], TEMP[0]
>  9: MAD OUT[3], IN[3].wwww, CONST[7], TEMP[0]
> 10: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = extractelement <4 x float> %59, i32 3
>  %64 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
>  %66 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %65, i32 0, i32 %5)
>  %67 = extractelement <4 x float> %66, i32 0
>  %68 = extractelement <4 x float> %66, i32 1
>  %69 = extractelement <4 x float> %66, i32 2
>  %70 = extractelement <4 x float> %66, i32 3
>  %71 = fmul float %46, %11
>  %72 = fmul float %46, %12
>  %73 = fmul float %46, %13
>  %74 = fmul float %46, %14
>  %75 = fmul float %47, %15
>  %76 = fadd float %75, %71
>  %77 = fmul float %47, %16
>  %78 = fadd float %77, %72
>  %79 = fmul float %47, %17
>  %80 = fadd float %79, %73
>  %81 = fmul float %47, %18
>  %82 = fadd float %81, %74
>  %83 = fmul float %48, %19
>  %84 = fadd float %83, %76
>  %85 = fmul float %48, %20
>  %86 = fadd float %85, %78
>  %87 = fmul float %48, %21
>  %88 = fadd float %87, %80
>  %89 = fmul float %48, %22
>  %90 = fadd float %89, %82
>  %91 = fmul float %49, %23
>  %92 = fadd float %91, %84
>  %93 = fmul float %49, %24
>  %94 = fadd float %93, %86
>  %95 = fmul float %49, %25
>  %96 = fadd float %95, %88
>  %97 = fmul float %49, %26
>  %98 = fadd float %97, %90
>  %99 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
>  %100 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %101 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %102 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
>  %103 = fmul float %67, %27
>  %104 = fmul float %67, %28
>  %105 = fmul float %67, %29
>  %106 = fmul float %67, %30
>  %107 = fmul float %68, %31
>  %108 = fadd float %107, %103
>  %109 = fmul float %68, %32
>  %110 = fadd float %109, %104
>  %111 = fmul float %68, %33
>  %112 = fadd float %111, %105
>  %113 = fmul float %68, %34
>  %114 = fadd float %113, %106
>  %115 = fmul float %69, %35
>  %116 = fadd float %115, %108
>  %117 = fmul float %69, %36
>  %118 = fadd float %117, %110
>  %119 = fmul float %69, %37
>  %120 = fadd float %119, %112
>  %121 = fmul float %69, %38
>  %122 = fadd float %121, %114
>  %123 = fmul float %70, %39
>  %124 = fadd float %123, %116
>  %125 = fmul float %70, %40
>  %126 = fadd float %125, %118
>  %127 = fmul float %70, %41
>  %128 = fadd float %127, %120
>  %129 = fmul float %70, %42
>  %130 = fadd float %129, %122
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %99, float %100, float %101, float %102)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %60, float %61, float %62, float %63)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %124, float %126, float %128, float %130)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %92, float %94, float %96, float %98)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c084070c
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800022f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: MOV OUT[3], IN[3]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %5)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = extractelement <4 x float> %50, i32 3
>  %55 = fmul float %30, %11
>  %56 = fmul float %30, %12
>  %57 = fmul float %30, %13
>  %58 = fmul float %30, %14
>  %59 = fmul float %31, %15
>  %60 = fadd float %59, %55
>  %61 = fmul float %31, %16
>  %62 = fadd float %61, %56
>  %63 = fmul float %31, %17
>  %64 = fadd float %63, %57
>  %65 = fmul float %31, %18
>  %66 = fadd float %65, %58
>  %67 = fmul float %32, %19
>  %68 = fadd float %67, %60
>  %69 = fmul float %32, %20
>  %70 = fadd float %69, %62
>  %71 = fmul float %32, %21
>  %72 = fadd float %71, %64
>  %73 = fmul float %32, %22
>  %74 = fadd float %73, %66
>  %75 = fmul float %33, %23
>  %76 = fadd float %75, %68
>  %77 = fmul float %33, %24
>  %78 = fadd float %77, %70
>  %79 = fmul float %33, %25
>  %80 = fadd float %79, %72
>  %81 = fmul float %33, %26
>  %82 = fadd float %81, %74
>  %83 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %84 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %85 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %86 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %83, float %84, float %85, float %86)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %51, float %52, float %53, float %54)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %76, float %78, float %80, float %82)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800022f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL OUT[2], GENERIC[1]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MUL TEMP[0], IN[1].xxxx, CONST[4]
>  5: MAD TEMP[0], IN[1].yyyy, CONST[5], TEMP[0]
>  6: MAD TEMP[0], IN[1].zzzz, CONST[6], TEMP[0]
>  7: MAD OUT[1], IN[1].wwww, CONST[7], TEMP[0]
>  8: MOV OUT[2], IN[2]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = extractelement <4 x float> %59, i32 3
>  %64 = fmul float %46, %11
>  %65 = fmul float %46, %12
>  %66 = fmul float %46, %13
>  %67 = fmul float %46, %14
>  %68 = fmul float %47, %15
>  %69 = fadd float %68, %64
>  %70 = fmul float %47, %16
>  %71 = fadd float %70, %65
>  %72 = fmul float %47, %17
>  %73 = fadd float %72, %66
>  %74 = fmul float %47, %18
>  %75 = fadd float %74, %67
>  %76 = fmul float %48, %19
>  %77 = fadd float %76, %69
>  %78 = fmul float %48, %20
>  %79 = fadd float %78, %71
>  %80 = fmul float %48, %21
>  %81 = fadd float %80, %73
>  %82 = fmul float %48, %22
>  %83 = fadd float %82, %75
>  %84 = fmul float %49, %23
>  %85 = fadd float %84, %77
>  %86 = fmul float %49, %24
>  %87 = fadd float %86, %79
>  %88 = fmul float %49, %25
>  %89 = fadd float %88, %81
>  %90 = fmul float %49, %26
>  %91 = fadd float %90, %83
>  %92 = fmul float %53, %27
>  %93 = fmul float %53, %28
>  %94 = fmul float %53, %29
>  %95 = fmul float %53, %30
>  %96 = fmul float %54, %31
>  %97 = fadd float %96, %92
>  %98 = fmul float %54, %32
>  %99 = fadd float %98, %93
>  %100 = fmul float %54, %33
>  %101 = fadd float %100, %94
>  %102 = fmul float %54, %34
>  %103 = fadd float %102, %95
>  %104 = fmul float %55, %35
>  %105 = fadd float %104, %97
>  %106 = fmul float %55, %36
>  %107 = fadd float %106, %99
>  %108 = fmul float %55, %37
>  %109 = fadd float %108, %101
>  %110 = fmul float %55, %38
>  %111 = fadd float %110, %103
>  %112 = fmul float %56, %39
>  %113 = fadd float %112, %105
>  %114 = fmul float %56, %40
>  %115 = fadd float %114, %107
>  %116 = fmul float %56, %41
>  %117 = fadd float %116, %109
>  %118 = fmul float %56, %42
>  %119 = fadd float %118, %111
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %113, float %115, float %117, float %119)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %60, float %61, float %62, float %63)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %85, float %87, float %89, float %91)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL OUT[2], GENERIC[1]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..3]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  5: MOV TEMP[1].w, TEMP[0]
>  6: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  7: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
>  8: MUL TEMP[3].xyz, CONST[2].xyzz, TEMP[3].xxxx
>  9: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 10: MOV OUT[0], TEMP[1]
> 11: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %39 = fdiv float %36, %38
>  %40 = fdiv float %37, %38
>  %41 = bitcast float %39 to i32
>  %42 = bitcast float %40 to i32
>  %43 = insertelement <2 x i32> undef, i32 %41, i32 0
>  %44 = insertelement <2 x i32> %43, i32 %42, i32 1
>  %45 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %44, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = fmul float %46, %31
>  %51 = fmul float %47, %32
>  %52 = fmul float %48, %33
>  %53 = fmul float %49, %34
>  %54 = fmul float %50, 2.000000e+00
>  %55 = fmul float %51, 2.000000e+00
>  %56 = fmul float %52, 2.000000e+00
>  %57 = fmul float %53, 1.000000e+00
>  %58 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %59 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %60 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
>  %61 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %62 = fmul float %35, %22
>  %63 = fadd float %62, %23
>  %64 = call float @llvm.AMDIL.clamp.(float %63, float 0.000000e+00, float 1.000000e+00)
>  %65 = fsub float -0.000000e+00, %64
>  %66 = fadd float 1.000000e+00, %65
>  %67 = fmul float %24, %66
>  %68 = fmul float %25, %66
>  %69 = fmul float %26, %66
>  %70 = fmul float %58, %64
>  %71 = fadd float %70, %67
>  %72 = fmul float %59, %64
>  %73 = fadd float %72, %68
>  %74 = fmul float %60, %64
>  %75 = fadd float %74, %69
>  %76 = call i32 @llvm.SI.packf16(float %71, float %73)
>  %77 = bitcast i32 %76 to float
>  %78 = call i32 @llvm.SI.packf16(float %75, float %61)
>  %79 = bitcast i32 %78 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %77, float %79, float %77, float %79)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c8180100
>c8190101
>bf8c0770
>100e0d03
>d2820006
>041e0d03
>d2060808
>02010106
>c8180400
>c8190401
>c0800100
>bf8c007f
>c2020104
>c2028105
>bf8c007f
>7e0e0205
>d2820006
>041c0906
>d2060806
>02010106
>080e0cf2
>c2020109
>bf8c007f
>10120e04
>d2820008
>04260d08
>c8240000
>c8250001
>10141302
>d2820009
>042a1302
>d2060809
>02010109
>c2020108
>bf8c007f
>10140e04
>d2820009
>042a0d09
>5e101109
>c8240200
>c8250201
>10141304
>d2820009
>042a1304
>d2060809
>02010109
>c200010a
>bf8c007f
>100e0e00
>d2820006
>041e0d09
>c81c0300
>c81d0301
>10000f05
>d2060800
>02010100
>5e000106
>f8001c0f
>00080008
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = fmul float %34, %11
>  %53 = fmul float %34, %12
>  %54 = fmul float %34, %13
>  %55 = fmul float %34, %14
>  %56 = fmul float %35, %15
>  %57 = fadd float %56, %52
>  %58 = fmul float %35, %16
>  %59 = fadd float %58, %53
>  %60 = fmul float %35, %17
>  %61 = fadd float %60, %54
>  %62 = fmul float %35, %18
>  %63 = fadd float %62, %55
>  %64 = fmul float %36, %19
>  %65 = fadd float %64, %57
>  %66 = fmul float %36, %20
>  %67 = fadd float %66, %59
>  %68 = fmul float %36, %21
>  %69 = fadd float %68, %61
>  %70 = fmul float %36, %22
>  %71 = fadd float %70, %63
>  %72 = fmul float %37, %23
>  %73 = fadd float %72, %65
>  %74 = fmul float %37, %24
>  %75 = fadd float %74, %67
>  %76 = fmul float %37, %25
>  %77 = fadd float %76, %69
>  %78 = fmul float %37, %26
>  %79 = fadd float %78, %71
>  %80 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %81 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %82 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %83 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %84 = fmul float %34, %27
>  %85 = fmul float %35, %28
>  %86 = fadd float %84, %85
>  %87 = fmul float %36, %29
>  %88 = fadd float %86, %87
>  %89 = fmul float %37, %30
>  %90 = fadd float %88, %89
>  %91 = call float @fabs(float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %80, float %81, float %82, float %83)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %91, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %73, float %75, float %77, float %79)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[1].xyz, TEMP[0], IN[0]
>  4: MOV TEMP[1].xyz, TEMP[1].xyzx
>  5: MOV TEMP[1].w, TEMP[0].wwww
>  6: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
>  7: MOV TEMP[1].xy, IN[3].xyyy
>  8: MOV TEMP[1].w, IN[3].wwww
>  9: TXP TEMP[1].w, TEMP[1], SAMP[0], 2D
> 10: MOV TEMP[1].w, TEMP[1].wwww
> 11: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[2].xxxx, CONST[2].yyyy
> 12: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
> 13: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
> 14: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 15: MOV OUT[0], TEMP[1]
> 16: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %45 = fdiv float %39, %41
>  %46 = fdiv float %40, %41
>  %47 = bitcast float %45 to i32
>  %48 = bitcast float %46 to i32
>  %49 = insertelement <2 x i32> undef, i32 %47, i32 0
>  %50 = insertelement <2 x i32> %49, i32 %48, i32 1
>  %51 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %50, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %52 = extractelement <4 x float> %51, i32 0
>  %53 = extractelement <4 x float> %51, i32 1
>  %54 = extractelement <4 x float> %51, i32 2
>  %55 = extractelement <4 x float> %51, i32 3
>  %56 = fmul float %52, %35
>  %57 = fmul float %53, %36
>  %58 = fmul float %54, %37
>  %59 = fmul float %56, 2.000000e+00
>  %60 = fmul float %57, 2.000000e+00
>  %61 = fmul float %58, 2.000000e+00
>  %62 = fmul float %55, 1.000000e+00
>  %63 = call float @llvm.AMDIL.clamp.(float %59, float 0.000000e+00, float 1.000000e+00)
>  %64 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %65 = call float @llvm.AMDIL.clamp.(float %61, float 0.000000e+00, float 1.000000e+00)
>  %66 = call float @llvm.AMDIL.clamp.(float %62, float 0.000000e+00, float 1.000000e+00)
>  %67 = fdiv float %42, %44
>  %68 = fdiv float %43, %44
>  %69 = bitcast float %67 to i32
>  %70 = bitcast float %68 to i32
>  %71 = insertelement <2 x i32> undef, i32 %69, i32 0
>  %72 = insertelement <2 x i32> %71, i32 %70, i32 1
>  %73 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %72, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %74 = extractelement <4 x float> %73, i32 3
>  %75 = fmul float %38, %22
>  %76 = fadd float %75, %23
>  %77 = call float @llvm.AMDIL.clamp.(float %76, float 0.000000e+00, float 1.000000e+00)
>  %78 = fsub float -0.000000e+00, %77
>  %79 = fadd float 1.000000e+00, %78
>  %80 = fmul float %24, %79
>  %81 = fmul float %25, %79
>  %82 = fmul float %26, %79
>  %83 = fmul float %63, %77
>  %84 = fadd float %83, %80
>  %85 = fmul float %64, %77
>  %86 = fadd float %85, %81
>  %87 = fmul float %65, %77
>  %88 = fadd float %87, %82
>  %89 = call i32 @llvm.SI.packf16(float %84, float %86)
>  %90 = bitcast i32 %89 to float
>  %91 = call i32 @llvm.SI.packf16(float %88, float %74)
>  %92 = bitcast i32 %91 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %90, float %92, float %90, float %92)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800700
>00430202
>c8140100
>c8150101
>bf8c0770
>100c0b03
>d2820005
>041a0b03
>d2060805
>02010105
>c8180400
>c8190401
>c0840100
>bf8c007f
>c2000908
>c2008909
>bf8c007f
>7e0e0201
>d2820006
>041c0106
>d2060806
>02010106
>080e0cf2
>c200090d
>bf8c007f
>10100e00
>d2820005
>04220d05
>c8200000
>c8210001
>10121102
>d2820008
>04261102
>d2060808
>02010108
>c200090c
>bf8c007f
>10120e00
>d2820008
>04260d08
>5e0a0b08
>c8200200
>c8210201
>10121104
>d2820002
>04261104
>d2060802
>02010102
>c200090e
>bf8c007f
>10060e00
>d2820002
>040e0d02
>c80c0d00
>c80d0d01
>c8100f00
>c8110f01
>7e0c5504
>10080d03
>c81c0c00
>c81d0c01
>10060d07
>c0800300
>c0c20500
>bf8c007f
>f0800800
>00010003
>bf8c0770
>5e000102
>f8001c0f
>00050005
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..14]
>DCL CONST[16..22]
>DCL TEMP[0..3]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: DP4 TEMP[1], IN[0], CONST[13]
> 15: ABS OUT[2].x, TEMP[1]
> 16: MOV OUT[2].yzw, IMM[0].xxxy
> 17: DP4 TEMP[2].x, IN[0], CONST[16]
> 18: DP4 TEMP[2].y, IN[0], CONST[17]
> 19: DP4 TEMP[2].z, IN[0], CONST[18]
> 20: MOV TEMP[2].w, IN[3]
> 21: MUL TEMP[3], TEMP[2].xxxx, CONST[19]
> 22: MAD TEMP[3], TEMP[2].yyyy, CONST[20], TEMP[3]
> 23: MAD TEMP[3], TEMP[2].zzzz, CONST[21], TEMP[3]
> 24: MAD OUT[3], TEMP[2].wwww, CONST[22], TEMP[3]
> 25: MOV OUT[4], IN[4]
> 26: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 268)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 284)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 300)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %75 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0
>  %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %76, i32 0, i32 %5)
>  %78 = extractelement <4 x float> %77, i32 0
>  %79 = extractelement <4 x float> %77, i32 1
>  %80 = extractelement <4 x float> %77, i32 2
>  %81 = extractelement <4 x float> %77, i32 3
>  %82 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %83 = load <16 x i8> addrspace(2)* %82, !tbaa !0
>  %84 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %83, i32 0, i32 %5)
>  %85 = extractelement <4 x float> %84, i32 0
>  %86 = extractelement <4 x float> %84, i32 1
>  %87 = extractelement <4 x float> %84, i32 2
>  %88 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %89 = load <16 x i8> addrspace(2)* %88, !tbaa !0
>  %90 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %89, i32 0, i32 %5)
>  %91 = extractelement <4 x float> %90, i32 0
>  %92 = extractelement <4 x float> %90, i32 1
>  %93 = extractelement <4 x float> %90, i32 2
>  %94 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %95 = load <16 x i8> addrspace(2)* %94, !tbaa !0
>  %96 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %95, i32 0, i32 %5)
>  %97 = extractelement <4 x float> %96, i32 3
>  %98 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %99 = load <16 x i8> addrspace(2)* %98, !tbaa !0
>  %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %99, i32 0, i32 %5)
>  %101 = extractelement <4 x float> %100, i32 0
>  %102 = extractelement <4 x float> %100, i32 1
>  %103 = extractelement <4 x float> %100, i32 2
>  %104 = extractelement <4 x float> %100, i32 3
>  %105 = fmul float %78, %11
>  %106 = fmul float %78, %12
>  %107 = fmul float %78, %13
>  %108 = fmul float %78, %14
>  %109 = fmul float %79, %15
>  %110 = fadd float %109, %105
>  %111 = fmul float %79, %16
>  %112 = fadd float %111, %106
>  %113 = fmul float %79, %17
>  %114 = fadd float %113, %107
>  %115 = fmul float %79, %18
>  %116 = fadd float %115, %108
>  %117 = fmul float %80, %19
>  %118 = fadd float %117, %110
>  %119 = fmul float %80, %20
>  %120 = fadd float %119, %112
>  %121 = fmul float %80, %21
>  %122 = fadd float %121, %114
>  %123 = fmul float %80, %22
>  %124 = fadd float %123, %116
>  %125 = fmul float %81, %23
>  %126 = fadd float %125, %118
>  %127 = fmul float %81, %24
>  %128 = fadd float %127, %120
>  %129 = fmul float %81, %25
>  %130 = fadd float %129, %122
>  %131 = fmul float %81, %26
>  %132 = fadd float %131, %124
>  %133 = fmul float %85, %27
>  %134 = fmul float %86, %28
>  %135 = fadd float %134, %133
>  %136 = fmul float %87, %29
>  %137 = fadd float %135, %136
>  %138 = fmul float %85, %30
>  %139 = fmul float %86, %31
>  %140 = fadd float %139, %138
>  %141 = fmul float %87, %32
>  %142 = fadd float %140, %141
>  %143 = fmul float %85, %33
>  %144 = fmul float %86, %34
>  %145 = fadd float %144, %143
>  %146 = fmul float %87, %35
>  %147 = fadd float %145, %146
>  %148 = fmul float %137, %137
>  %149 = fmul float %142, %142
>  %150 = fadd float %149, %148
>  %151 = fmul float %147, %147
>  %152 = fadd float %150, %151
>  %153 = call float @fabs(float %152)
>  %154 = call float @llvm.AMDGPU.rsq(float %153)
>  %155 = fmul float %36, %39
>  %156 = fadd float %155, %91
>  %157 = fmul float %37, %40
>  %158 = fadd float %157, %92
>  %159 = fmul float %38, %41
>  %160 = fadd float %159, %93
>  %161 = call float @llvm.AMDIL.clamp.(float %156, float 0.000000e+00, float 1.000000e+00)
>  %162 = call float @llvm.AMDIL.clamp.(float %158, float 0.000000e+00, float 1.000000e+00)
>  %163 = call float @llvm.AMDIL.clamp.(float %160, float 0.000000e+00, float 1.000000e+00)
>  %164 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %165 = fmul float %78, %43
>  %166 = fmul float %79, %44
>  %167 = fadd float %165, %166
>  %168 = fmul float %80, %45
>  %169 = fadd float %167, %168
>  %170 = fmul float %81, %46
>  %171 = fadd float %169, %170
>  %172 = call float @fabs(float %171)
>  %173 = fmul float %78, %47
>  %174 = fmul float %79, %48
>  %175 = fadd float %173, %174
>  %176 = fmul float %80, %49
>  %177 = fadd float %175, %176
>  %178 = fmul float %81, %50
>  %179 = fadd float %177, %178
>  %180 = fmul float %78, %51
>  %181 = fmul float %79, %52
>  %182 = fadd float %180, %181
>  %183 = fmul float %80, %53
>  %184 = fadd float %182, %183
>  %185 = fmul float %81, %54
>  %186 = fadd float %184, %185
>  %187 = fmul float %78, %55
>  %188 = fmul float %79, %56
>  %189 = fadd float %187, %188
>  %190 = fmul float %80, %57
>  %191 = fadd float %189, %190
>  %192 = fmul float %81, %58
>  %193 = fadd float %191, %192
>  %194 = fmul float %179, %59
>  %195 = fmul float %179, %60
>  %196 = fmul float %179, %61
>  %197 = fmul float %179, %62
>  %198 = fmul float %186, %63
>  %199 = fadd float %198, %194
>  %200 = fmul float %186, %64
>  %201 = fadd float %200, %195
>  %202 = fmul float %186, %65
>  %203 = fadd float %202, %196
>  %204 = fmul float %186, %66
>  %205 = fadd float %204, %197
>  %206 = fmul float %193, %67
>  %207 = fadd float %206, %199
>  %208 = fmul float %193, %68
>  %209 = fadd float %208, %201
>  %210 = fmul float %193, %69
>  %211 = fadd float %210, %203
>  %212 = fmul float %193, %70
>  %213 = fadd float %212, %205
>  %214 = fmul float %97, %71
>  %215 = fadd float %214, %207
>  %216 = fmul float %97, %72
>  %217 = fadd float %216, %209
>  %218 = fmul float %97, %73
>  %219 = fadd float %218, %211
>  %220 = fmul float %97, %74
>  %221 = fadd float %220, %213
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %161, float %162, float %163, float %164)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %172, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %215, float %217, float %219, float %221)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %101, float %102, float %103, float %104)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %126, float %128, float %130, float %132)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c0840700
>bf8c000f
>e00c2000
>80020100
>c2020135
>bf8c0070
>100a0404
>c2020134
>bf8c007f
>d2820005
>04140901
>c2020136
>bf8c007f
>d2820005
>04140903
>c2020137
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c2020145
>bf8c000f
>100a0404
>c2020144
>bf8c007f
>d2820005
>04140901
>c2020146
>bf8c007f
>d2820005
>04140903
>c2020147
>bf8c007f
>d2820005
>04140904
>c2020141
>bf8c007f
>100c0404
>c2020140
>bf8c007f
>d2820006
>04180901
>c2020142
>bf8c007f
>d2820006
>04180903
>c2020143
>bf8c007f
>d2820006
>04180904
>c202014f
>bf8c007f
>100e0c04
>c2020153
>bf8c007f
>d2820008
>041c0905
>c2020149
>bf8c007f
>100e0404
>c2020148
>bf8c007f
>d2820007
>041c0901
>c202014a
>bf8c007f
>d2820007
>041c0903
>c202014b
>bf8c007f
>d2820007
>041c0904
>c2020157
>bf8c007f
>d282000c
>04200907
>c084070c
>bf8c007f
>e00c2000
>80020800
>c202015b
>bf8c0070
>d282000c
>0430090b
>c202014e
>bf8c007f
>101a0c04
>c2020152
>bf8c007f
>d282000d
>04340905
>c2020156
>bf8c007f
>d282000d
>04340907
>c202015a
>bf8c007f
>d282000d
>0434090b
>c202014d
>bf8c007f
>101c0c04
>c2020151
>bf8c007f
>d282000e
>04380905
>c2020155
>bf8c007f
>d282000e
>04380907
>c2020159
>bf8c007f
>d282000e
>0438090b
>c202014c
>bf8c007f
>100c0c04
>c2020150
>bf8c007f
>d2820005
>04180905
>c2020154
>bf8c007f
>d2820005
>04140907
>c2020158
>bf8c007f
>d2820005
>0414090b
>f800022f
>0c0d0e05
>c0820710
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..19]
>DCL CONST[21..27]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: ABS OUT[2].x, TEMP[4].zzzz
> 41: MOV OUT[2].yzw, IMM[0].xxxy
> 42: DP4 TEMP[1].x, IN[0], CONST[21]
> 43: DP4 TEMP[1].y, IN[0], CONST[22]
> 44: DP4 TEMP[1].z, IN[0], CONST[23]
> 45: MOV TEMP[1].w, IN[3]
> 46: MUL TEMP[2], TEMP[1].xxxx, CONST[24]
> 47: MAD TEMP[2], TEMP[1].yyyy, CONST[25], TEMP[2]
> 48: MAD TEMP[2], TEMP[1].zzzz, CONST[26], TEMP[2]
> 49: MAD OUT[3], TEMP[1].wwww, CONST[27], TEMP[2]
> 50: MOV OUT[4], IN[4]
> 51: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 444)
>  %99 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %100 = load <16 x i8> addrspace(2)* %99, !tbaa !0
>  %101 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %100, i32 0, i32 %5)
>  %102 = extractelement <4 x float> %101, i32 0
>  %103 = extractelement <4 x float> %101, i32 1
>  %104 = extractelement <4 x float> %101, i32 2
>  %105 = extractelement <4 x float> %101, i32 3
>  %106 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %107 = load <16 x i8> addrspace(2)* %106, !tbaa !0
>  %108 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %107, i32 0, i32 %5)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = extractelement <4 x float> %108, i32 1
>  %111 = extractelement <4 x float> %108, i32 2
>  %112 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %113 = load <16 x i8> addrspace(2)* %112, !tbaa !0
>  %114 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %113, i32 0, i32 %5)
>  %115 = extractelement <4 x float> %114, i32 0
>  %116 = extractelement <4 x float> %114, i32 1
>  %117 = extractelement <4 x float> %114, i32 2
>  %118 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %119 = load <16 x i8> addrspace(2)* %118, !tbaa !0
>  %120 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %119, i32 0, i32 %5)
>  %121 = extractelement <4 x float> %120, i32 3
>  %122 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
>  %124 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %123, i32 0, i32 %5)
>  %125 = extractelement <4 x float> %124, i32 0
>  %126 = extractelement <4 x float> %124, i32 1
>  %127 = extractelement <4 x float> %124, i32 2
>  %128 = extractelement <4 x float> %124, i32 3
>  %129 = fmul float %102, %11
>  %130 = fmul float %102, %12
>  %131 = fmul float %102, %13
>  %132 = fmul float %102, %14
>  %133 = fmul float %103, %15
>  %134 = fadd float %133, %129
>  %135 = fmul float %103, %16
>  %136 = fadd float %135, %130
>  %137 = fmul float %103, %17
>  %138 = fadd float %137, %131
>  %139 = fmul float %103, %18
>  %140 = fadd float %139, %132
>  %141 = fmul float %104, %19
>  %142 = fadd float %141, %134
>  %143 = fmul float %104, %20
>  %144 = fadd float %143, %136
>  %145 = fmul float %104, %21
>  %146 = fadd float %145, %138
>  %147 = fmul float %104, %22
>  %148 = fadd float %147, %140
>  %149 = fmul float %105, %23
>  %150 = fadd float %149, %142
>  %151 = fmul float %105, %24
>  %152 = fadd float %151, %144
>  %153 = fmul float %105, %25
>  %154 = fadd float %153, %146
>  %155 = fmul float %105, %26
>  %156 = fadd float %155, %148
>  %157 = fmul float %109, %27
>  %158 = fmul float %110, %28
>  %159 = fadd float %158, %157
>  %160 = fmul float %111, %29
>  %161 = fadd float %159, %160
>  %162 = fmul float %109, %30
>  %163 = fmul float %110, %31
>  %164 = fadd float %163, %162
>  %165 = fmul float %111, %32
>  %166 = fadd float %164, %165
>  %167 = fmul float %109, %33
>  %168 = fmul float %110, %34
>  %169 = fadd float %168, %167
>  %170 = fmul float %111, %35
>  %171 = fadd float %169, %170
>  %172 = fmul float %161, %161
>  %173 = fmul float %166, %166
>  %174 = fadd float %173, %172
>  %175 = fmul float %171, %171
>  %176 = fadd float %174, %175
>  %177 = call float @fabs(float %176)
>  %178 = call float @llvm.AMDGPU.rsq(float %177)
>  %179 = fmul float %161, %178
>  %180 = fmul float %166, %178
>  %181 = fmul float %171, %178
>  %182 = fmul float %37, %40
>  %183 = fadd float %182, %115
>  %184 = fmul float %38, %41
>  %185 = fadd float %184, %116
>  %186 = fmul float %39, %42
>  %187 = fadd float %186, %117
>  %188 = call float @llvm.AMDIL.clamp.(float %183, float 0.000000e+00, float 1.000000e+00)
>  %189 = call float @llvm.AMDIL.clamp.(float %185, float 0.000000e+00, float 1.000000e+00)
>  %190 = call float @llvm.AMDIL.clamp.(float %187, float 0.000000e+00, float 1.000000e+00)
>  %191 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %192 = fmul float %102, %47
>  %193 = fmul float %102, %48
>  %194 = fmul float %102, %49
>  %195 = fmul float %103, %50
>  %196 = fadd float %195, %192
>  %197 = fmul float %103, %51
>  %198 = fadd float %197, %193
>  %199 = fmul float %103, %52
>  %200 = fadd float %199, %194
>  %201 = fmul float %104, %53
>  %202 = fadd float %201, %196
>  %203 = fmul float %104, %54
>  %204 = fadd float %203, %198
>  %205 = fmul float %104, %55
>  %206 = fadd float %205, %200
>  %207 = fmul float %105, %56
>  %208 = fadd float %207, %202
>  %209 = fmul float %105, %57
>  %210 = fadd float %209, %204
>  %211 = fmul float %105, %58
>  %212 = fadd float %211, %206
>  %213 = fsub float %44, %208
>  %214 = fsub float %45, %210
>  %215 = fsub float %46, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fdiv float 1.000000e+00, %222
>  %227 = fmul float %222, %226
>  %228 = fmul float %226, %226
>  %229 = fmul float %59, %227
>  %230 = fmul float %60, %226
>  %231 = fadd float %230, %229
>  %232 = fmul float %61, %228
>  %233 = fadd float %231, %232
>  %234 = fdiv float 1.000000e+00, %233
>  %235 = fmul float %208, %208
>  %236 = fmul float %210, %210
>  %237 = fadd float %236, %235
>  %238 = fmul float %212, %212
>  %239 = fadd float %237, %238
>  %240 = call float @fabs(float %239)
>  %241 = call float @llvm.AMDGPU.rsq(float %240)
>  %242 = fmul float %208, %241
>  %243 = fmul float %210, %241
>  %244 = fmul float %212, %241
>  %245 = fsub float %223, %242
>  %246 = fsub float %224, %243
>  %247 = fsub float %225, %244
>  %248 = fmul float %245, %245
>  %249 = fmul float %246, %246
>  %250 = fadd float %249, %248
>  %251 = fmul float %247, %247
>  %252 = fadd float %250, %251
>  %253 = call float @fabs(float %252)
>  %254 = call float @llvm.AMDGPU.rsq(float %253)
>  %255 = fmul float %245, %254
>  %256 = fmul float %246, %254
>  %257 = fmul float %247, %254
>  %258 = fmul float %179, %223
>  %259 = fmul float %180, %224
>  %260 = fadd float %259, %258
>  %261 = fmul float %181, %225
>  %262 = fadd float %260, %261
>  %263 = fmul float %179, %255
>  %264 = fmul float %180, %256
>  %265 = fadd float %264, %263
>  %266 = fmul float %181, %257
>  %267 = fadd float %265, %266
>  %268 = fcmp uge float %262, 0.000000e+00
>  %269 = select i1 %268, float %262, float 0.000000e+00
>  %270 = fcmp uge float %267, 0.000000e+00
>  %271 = select i1 %270, float %267, float 0.000000e+00
>  %272 = call float @llvm.pow.f32(float %271, float %36)
>  %273 = call float @llvm.AMDGPU.cndlt(float %262, float 0.000000e+00, float %272)
>  %274 = fmul float 1.000000e+00, %234
>  %275 = fmul float %269, %234
>  %276 = fmul float %273, %234
>  %277 = fmul float %274, %62
>  %278 = fadd float %277, %183
>  %279 = fmul float %274, %63
>  %280 = fadd float %279, %185
>  %281 = fmul float %274, %64
>  %282 = fadd float %281, %187
>  %283 = fmul float %275, %65
>  %284 = fadd float %283, %278
>  %285 = fmul float %275, %66
>  %286 = fadd float %285, %280
>  %287 = fmul float %275, %67
>  %288 = fadd float %287, %282
>  %289 = fmul float %276, %68
>  %290 = fadd float %289, %284
>  %291 = fmul float %276, %69
>  %292 = fadd float %291, %286
>  %293 = fmul float %276, %70
>  %294 = fadd float %293, %288
>  %295 = call float @llvm.AMDIL.clamp.(float %290, float 0.000000e+00, float 1.000000e+00)
>  %296 = call float @llvm.AMDIL.clamp.(float %292, float 0.000000e+00, float 1.000000e+00)
>  %297 = call float @llvm.AMDIL.clamp.(float %294, float 0.000000e+00, float 1.000000e+00)
>  %298 = call float @fabs(float %212)
>  %299 = fmul float %102, %71
>  %300 = fmul float %103, %72
>  %301 = fadd float %299, %300
>  %302 = fmul float %104, %73
>  %303 = fadd float %301, %302
>  %304 = fmul float %105, %74
>  %305 = fadd float %303, %304
>  %306 = fmul float %102, %75
>  %307 = fmul float %103, %76
>  %308 = fadd float %306, %307
>  %309 = fmul float %104, %77
>  %310 = fadd float %308, %309
>  %311 = fmul float %105, %78
>  %312 = fadd float %310, %311
>  %313 = fmul float %102, %79
>  %314 = fmul float %103, %80
>  %315 = fadd float %313, %314
>  %316 = fmul float %104, %81
>  %317 = fadd float %315, %316
>  %318 = fmul float %105, %82
>  %319 = fadd float %317, %318
>  %320 = fmul float %305, %83
>  %321 = fmul float %305, %84
>  %322 = fmul float %305, %85
>  %323 = fmul float %305, %86
>  %324 = fmul float %312, %87
>  %325 = fadd float %324, %320
>  %326 = fmul float %312, %88
>  %327 = fadd float %326, %321
>  %328 = fmul float %312, %89
>  %329 = fadd float %328, %322
>  %330 = fmul float %312, %90
>  %331 = fadd float %330, %323
>  %332 = fmul float %319, %91
>  %333 = fadd float %332, %325
>  %334 = fmul float %319, %92
>  %335 = fadd float %334, %327
>  %336 = fmul float %319, %93
>  %337 = fadd float %336, %329
>  %338 = fmul float %319, %94
>  %339 = fadd float %338, %331
>  %340 = fmul float %121, %95
>  %341 = fadd float %340, %333
>  %342 = fmul float %121, %96
>  %343 = fadd float %342, %335
>  %344 = fmul float %121, %97
>  %345 = fadd float %344, %337
>  %346 = fmul float %121, %98
>  %347 = fadd float %346, %339
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %295, float %296, float %297, float %191)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %298, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %341, float %343, float %345, float %347)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %125, float %126, float %127, float %128)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %150, float %152, float %154, float %156)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>d2820013
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>04522512
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>80020900
>c2020122
>c2028126
>bf8c0070
>7e1a0205
>d282000d
>042e1a04
>c2020146
>bf8c007f
>d282000d
>04340907
>c202014a
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>c202014e
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>04340906
>d206080d
>0201010d
>c2020121
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>c2020145
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>c2020149
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>04380908
>c202014d
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>d206080e
>0201010e
>c2020120
>c2028124
>bf8c007f
>7e1e0205
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>04261e04
>c2020144
>bf8c007f
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>04240907
>c2020148
>bf8c007f
>d2820007
>041c0908
>c202014c
>bf8c007f
>d2820006
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>d2060806
>02010106
>c202012b
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>c202015b
>bf8c007f
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>04180904
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>041c0905
>c202015d
>bf8c007f
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>041c0901
>c202015e
>bf8c007f
>d2820007
>041c0903
>c202015f
>bf8c007f
>d2820007
>041c0904
>c202016b
>bf8c007f
>d282000c
>04200907
>c084070c
>bf8c007f
>e00c2000
>80020800
>c202016f
>bf8c0070
>d282000c
>0430090b
>c2020162
>bf8c007f
>101a0c04
>c2020166
>bf8c007f
>d282000d
>04340905
>c202016a
>bf8c007f
>d282000d
>04340907
>c202016e
>bf8c007f
>d282000d
>0434090b
>c2020161
>bf8c007f
>101c0c04
>c2020165
>bf8c007f
>d282000e
>04380905
>c2020169
>bf8c007f
>d282000e
>04380907
>c202016d
>bf8c007f
>d282000e
>0438090b
>c2020160
>bf8c007f
>100c0c04
>c2020164
>bf8c007f
>d2820005
>04180905
>c2020168
>bf8c007f
>d2820005
>04140907
>c202016c
>bf8c007f
>d2820005
>0414090b
>f800022f
>0c0d0e05
>c0820710
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[1].xyz, TEMP[0], IN[0]
>  4: MOV TEMP[1].xyz, TEMP[1].xyzx
>  5: MOV TEMP[1].w, TEMP[0].wwww
>  6: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
>  7: MOV TEMP[1].xy, IN[3].xyyy
>  8: MOV TEMP[1].w, IN[3].wwww
>  9: TXP TEMP[1].w, TEMP[1], SAMP[0], 2D
> 10: MOV TEMP[1].w, TEMP[1].wwww
> 11: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[2].xxxx, CONST[2].yyyy
> 12: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
> 13: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
> 14: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 15: MOV OUT[0], TEMP[1]
> 16: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %45 = fdiv float %39, %41
>  %46 = fdiv float %40, %41
>  %47 = bitcast float %45 to i32
>  %48 = bitcast float %46 to i32
>  %49 = insertelement <2 x i32> undef, i32 %47, i32 0
>  %50 = insertelement <2 x i32> %49, i32 %48, i32 1
>  %51 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %50, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %52 = extractelement <4 x float> %51, i32 0
>  %53 = extractelement <4 x float> %51, i32 1
>  %54 = extractelement <4 x float> %51, i32 2
>  %55 = extractelement <4 x float> %51, i32 3
>  %56 = fmul float %52, %35
>  %57 = fmul float %53, %36
>  %58 = fmul float %54, %37
>  %59 = fmul float %56, 2.000000e+00
>  %60 = fmul float %57, 2.000000e+00
>  %61 = fmul float %58, 2.000000e+00
>  %62 = fmul float %55, 1.000000e+00
>  %63 = call float @llvm.AMDIL.clamp.(float %59, float 0.000000e+00, float 1.000000e+00)
>  %64 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %65 = call float @llvm.AMDIL.clamp.(float %61, float 0.000000e+00, float 1.000000e+00)
>  %66 = call float @llvm.AMDIL.clamp.(float %62, float 0.000000e+00, float 1.000000e+00)
>  %67 = fdiv float %42, %44
>  %68 = fdiv float %43, %44
>  %69 = bitcast float %67 to i32
>  %70 = bitcast float %68 to i32
>  %71 = insertelement <2 x i32> undef, i32 %69, i32 0
>  %72 = insertelement <2 x i32> %71, i32 %70, i32 1
>  %73 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %72, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %74 = extractelement <4 x float> %73, i32 3
>  %75 = fmul float %38, %22
>  %76 = fadd float %75, %23
>  %77 = call float @llvm.AMDIL.clamp.(float %76, float 0.000000e+00, float 1.000000e+00)
>  %78 = fsub float -0.000000e+00, %77
>  %79 = fadd float 1.000000e+00, %78
>  %80 = fmul float %24, %79
>  %81 = fmul float %25, %79
>  %82 = fmul float %26, %79
>  %83 = fmul float %63, %77
>  %84 = fadd float %83, %80
>  %85 = fmul float %64, %77
>  %86 = fadd float %85, %81
>  %87 = fmul float %65, %77
>  %88 = fadd float %87, %82
>  %89 = fcmp ugt float %74, 0.000000e+00
>  %90 = sext i1 %89 to i32
>  %91 = trunc i32 %90 to i1
>  %92 = select i1 %91, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %92)
>  %93 = call i32 @llvm.SI.packf16(float %84, float %86)
>  %94 = bitcast i32 %93 to float
>  %95 = call i32 @llvm.SI.packf16(float %88, float %74)
>  %96 = bitcast i32 %95 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %94, float %96, float %94, float %96)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080d00
>c8090d01
>c80c0f00
>c80d0f01
>7e085503
>10060902
>c8140c00
>c8150c01
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800800
>00430202
>bf8c0770
>d0080008
>02010102
>d2000003
>0021e4f3
>7c260680
>c80c0900
>c80d0901
>c8100b00
>c8110b01
>7e0a5504
>10080b03
>c8180800
>c8190801
>10060b06
>c0840304
>c0c60508
>bf8c007f
>f0800700
>00430303
>c8180100
>c8190101
>bf8c0770
>100e0d04
>d2820006
>041e0d04
>d2060808
>02010106
>c8180400
>c8190401
>c0800100
>bf8c007f
>c2020108
>c2028109
>bf8c007f
>7e0e0205
>d2820006
>041c0906
>d2060806
>02010106
>080e0cf2
>c202010d
>bf8c007f
>10120e04
>d2820008
>04260d08
>c8240000
>c8250001
>10141303
>d2820009
>042a1303
>d2060809
>02010109
>c202010c
>bf8c007f
>10140e04
>d2820009
>042a0d09
>5e101109
>c8240200
>c8250201
>10001305
>d2820000
>04021305
>d2060800
>02010100
>c200010e
>bf8c007f
>10020e00
>d2820000
>04060d00
>5e000500
>f8001c0f
>00080008
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], FOG, PERSPECTIVE
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MOV TEMP[1].xy, IN[2].xyyy
>  4: MOV TEMP[1].w, IN[2].wwww
>  5: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  6: MUL TEMP[1].xyz, TEMP[1], TEMP[0]
>  7: MOV TEMP[1].xyz, TEMP[1].xyzx
>  8: MOV TEMP[1].w, TEMP[0].wwww
>  9: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
> 10: MOV TEMP[1].w, TEMP[0]
> 11: MAD_SAT TEMP[2].x, IN[0].xxxx, CONST[2].xxxx, CONST[2].yyyy
> 12: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
> 13: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
> 14: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 15: MOV OUT[0], TEMP[1]
> 16: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %42 = fdiv float %36, %38
>  %43 = fdiv float %37, %38
>  %44 = bitcast float %42 to i32
>  %45 = bitcast float %43 to i32
>  %46 = insertelement <2 x i32> undef, i32 %44, i32 0
>  %47 = insertelement <2 x i32> %46, i32 %45, i32 1
>  %48 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %47, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %49 = extractelement <4 x float> %48, i32 0
>  %50 = extractelement <4 x float> %48, i32 1
>  %51 = extractelement <4 x float> %48, i32 2
>  %52 = extractelement <4 x float> %48, i32 3
>  %53 = fdiv float %39, %41
>  %54 = fdiv float %40, %41
>  %55 = bitcast float %53 to i32
>  %56 = bitcast float %54 to i32
>  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
>  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
>  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = fmul float %60, %49
>  %64 = fmul float %61, %50
>  %65 = fmul float %62, %51
>  %66 = fmul float %63, 2.000000e+00
>  %67 = fmul float %64, 2.000000e+00
>  %68 = fmul float %65, 2.000000e+00
>  %69 = fmul float %52, 1.000000e+00
>  %70 = call float @llvm.AMDIL.clamp.(float %66, float 0.000000e+00, float 1.000000e+00)
>  %71 = call float @llvm.AMDIL.clamp.(float %67, float 0.000000e+00, float 1.000000e+00)
>  %72 = call float @llvm.AMDIL.clamp.(float %68, float 0.000000e+00, float 1.000000e+00)
>  %73 = call float @llvm.AMDIL.clamp.(float %69, float 0.000000e+00, float 1.000000e+00)
>  %74 = fmul float %35, %22
>  %75 = fadd float %74, %23
>  %76 = call float @llvm.AMDIL.clamp.(float %75, float 0.000000e+00, float 1.000000e+00)
>  %77 = fsub float -0.000000e+00, %76
>  %78 = fadd float 1.000000e+00, %77
>  %79 = fmul float %24, %78
>  %80 = fmul float %25, %78
>  %81 = fmul float %26, %78
>  %82 = fmul float %70, %76
>  %83 = fadd float %82, %79
>  %84 = fmul float %71, %76
>  %85 = fadd float %84, %80
>  %86 = fmul float %72, %76
>  %87 = fadd float %86, %81
>  %88 = call i32 @llvm.SI.packf16(float %83, float %85)
>  %89 = bitcast i32 %88 to float
>  %90 = call i32 @llvm.SI.packf16(float %87, float %73)
>  %91 = bitcast i32 %90 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %89, float %91, float %89, float %91)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180900
>c8190901
>c81c0b00
>c81d0b01
>7e105507
>100e1106
>c8240800
>c8250801
>100c1109
>c0840300
>c0c60500
>bf8c0070
>f0800700
>00430606
>bf8c0770
>10120707
>d2820009
>04260707
>d2060809
>02010109
>c8280000
>c8290001
>c0800100
>bf8c007f
>c2020108
>c2028109
>bf8c007f
>7e000205
>d2820000
>0400090a
>d2060800
>02010100
>080200f2
>c202010d
>bf8c007f
>10140204
>d2820009
>042a0109
>10140506
>d282000a
>042a0506
>d206080a
>0201010a
>c202010c
>bf8c007f
>10160204
>d282000a
>042e010a
>5e12130a
>10140908
>d2820006
>042a0908
>d2060806
>02010106
>c200010e
>bf8c007f
>10020200
>d2820000
>04060106
>d2060801
>02010105
>5e000300
>f8001c0f
>00090009
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], FOG
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP4 TEMP[0], IN[0], CONST[6]
>  5: ABS OUT[1].x, TEMP[0]
>  6: MOV OUT[1].yzw, IMM[0].xxxy
>  7: MOV OUT[2], IN[1]
>  8: MOV OUT[3], IN[2]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = fmul float %34, %11
>  %53 = fmul float %34, %12
>  %54 = fmul float %34, %13
>  %55 = fmul float %34, %14
>  %56 = fmul float %35, %15
>  %57 = fadd float %56, %52
>  %58 = fmul float %35, %16
>  %59 = fadd float %58, %53
>  %60 = fmul float %35, %17
>  %61 = fadd float %60, %54
>  %62 = fmul float %35, %18
>  %63 = fadd float %62, %55
>  %64 = fmul float %36, %19
>  %65 = fadd float %64, %57
>  %66 = fmul float %36, %20
>  %67 = fadd float %66, %59
>  %68 = fmul float %36, %21
>  %69 = fadd float %68, %61
>  %70 = fmul float %36, %22
>  %71 = fadd float %70, %63
>  %72 = fmul float %37, %23
>  %73 = fadd float %72, %65
>  %74 = fmul float %37, %24
>  %75 = fadd float %74, %67
>  %76 = fmul float %37, %25
>  %77 = fadd float %76, %69
>  %78 = fmul float %37, %26
>  %79 = fadd float %78, %71
>  %80 = fmul float %34, %27
>  %81 = fmul float %35, %28
>  %82 = fadd float %80, %81
>  %83 = fmul float %36, %29
>  %84 = fadd float %82, %83
>  %85 = fmul float %37, %30
>  %86 = fadd float %84, %85
>  %87 = call float @fabs(float %86)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %87, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %41, float %42, float %43, float %44)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %73, float %75, float %77, float %79)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800020f
>06070705
>c0840704
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800021f
>08070605
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL IN[4], GENERIC[2], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL CONST[3..5]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[2], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV TEMP[1].xy, IN[3].xyyy
>  5: MOV TEMP[1].w, IN[3].wwww
>  6: TXP TEMP[1], TEMP[1], SAMP[1], 2D
>  7: MUL_SAT TEMP[2], TEMP[0], IMM[0].xxxy
>  8: MUL TEMP[1].xyz, TEMP[1], TEMP[2]
>  9: MOV TEMP[1].xyz, TEMP[1].xyzx
> 10: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
> 11: MOV TEMP[1].w, TEMP[0].wwww
> 12: TXP TEMP[0], IN[4], SAMP[0], CUBE
> 13: MUL_SAT TEMP[2], TEMP[1], IMM[0].xxxy
> 14: MUL_SAT TEMP[3], TEMP[1], IMM[0].xxxy
> 15: MAD TEMP[0].xyz, TEMP[0], TEMP[2].wwww, TEMP[3]
> 16: MOV_SAT TEMP[0].xyz, TEMP[0].xyzz
> 17: MUL_SAT TEMP[1], TEMP[1], IMM[0].xxxy
> 18: MOV TEMP[1].w, TEMP[1].wwww
> 19: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[3].xxxx, CONST[3].yyyy
> 20: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
> 21: MUL TEMP[3].xyz, CONST[4].xyzz, TEMP[3].xxxx
> 22: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 23: MOV OUT[0], TEMP[1]
> 24: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %36 = load <32 x i8> addrspace(2)* %35, !tbaa !0
>  %37 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %46 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %47 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %48 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %49 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %50 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %51 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %52 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
>  %53 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %54 = fdiv float %44, %46
>  %55 = fdiv float %45, %46
>  %56 = bitcast float %54 to i32
>  %57 = bitcast float %55 to i32
>  %58 = insertelement <2 x i32> undef, i32 %56, i32 0
>  %59 = insertelement <2 x i32> %58, i32 %57, i32 1
>  %60 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %59, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %61 = extractelement <4 x float> %60, i32 0
>  %62 = extractelement <4 x float> %60, i32 1
>  %63 = extractelement <4 x float> %60, i32 2
>  %64 = extractelement <4 x float> %60, i32 3
>  %65 = fmul float %61, %39
>  %66 = fmul float %62, %40
>  %67 = fmul float %63, %41
>  %68 = fmul float %64, %42
>  %69 = fdiv float %47, %49
>  %70 = fdiv float %48, %49
>  %71 = bitcast float %69 to i32
>  %72 = bitcast float %70 to i32
>  %73 = insertelement <2 x i32> undef, i32 %71, i32 0
>  %74 = insertelement <2 x i32> %73, i32 %72, i32 1
>  %75 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %74, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %76 = extractelement <4 x float> %75, i32 0
>  %77 = extractelement <4 x float> %75, i32 1
>  %78 = extractelement <4 x float> %75, i32 2
>  %79 = fmul float %65, 2.000000e+00
>  %80 = fmul float %66, 2.000000e+00
>  %81 = fmul float %67, 2.000000e+00
>  %82 = fmul float %68, 1.000000e+00
>  %83 = call float @llvm.AMDIL.clamp.(float %79, float 0.000000e+00, float 1.000000e+00)
>  %84 = call float @llvm.AMDIL.clamp.(float %80, float 0.000000e+00, float 1.000000e+00)
>  %85 = call float @llvm.AMDIL.clamp.(float %81, float 0.000000e+00, float 1.000000e+00)
>  %86 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %87 = fmul float %76, %83
>  %88 = fmul float %77, %84
>  %89 = fmul float %78, %85
>  %90 = fmul float %65, 2.000000e+00
>  %91 = fmul float %66, 2.000000e+00
>  %92 = fmul float %67, 2.000000e+00
>  %93 = fmul float %68, 1.000000e+00
>  %94 = call float @llvm.AMDIL.clamp.(float %90, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %91, float 0.000000e+00, float 1.000000e+00)
>  %96 = call float @llvm.AMDIL.clamp.(float %92, float 0.000000e+00, float 1.000000e+00)
>  %97 = call float @llvm.AMDIL.clamp.(float %93, float 0.000000e+00, float 1.000000e+00)
>  %98 = fdiv float %50, %53
>  %99 = fdiv float %51, %53
>  %100 = fdiv float %52, %53
>  %101 = insertelement <4 x float> undef, float %98, i32 0
>  %102 = insertelement <4 x float> %101, float %99, i32 1
>  %103 = insertelement <4 x float> %102, float %100, i32 2
>  %104 = insertelement <4 x float> %103, float 1.000000e+00, i32 3
>  %105 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %104)
>  %106 = extractelement <4 x float> %105, i32 0
>  %107 = extractelement <4 x float> %105, i32 1
>  %108 = extractelement <4 x float> %105, i32 2
>  %109 = extractelement <4 x float> %105, i32 3
>  %110 = call float @fabs(float %108)
>  %111 = fdiv float 1.000000e+00, %110
>  %112 = fmul float %106, %111
>  %113 = fadd float %112, 1.500000e+00
>  %114 = fmul float %107, %111
>  %115 = fadd float %114, 1.500000e+00
>  %116 = bitcast float %115 to i32
>  %117 = bitcast float %113 to i32
>  %118 = bitcast float %109 to i32
>  %119 = insertelement <4 x i32> undef, i32 %116, i32 0
>  %120 = insertelement <4 x i32> %119, i32 %117, i32 1
>  %121 = insertelement <4 x i32> %120, i32 %118, i32 2
>  %122 = insertelement <4 x i32> %121, i32 undef, i32 3
>  %123 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %122, <32 x i8> %28, <16 x i8> %30, i32 4)
>  %124 = extractelement <4 x float> %123, i32 0
>  %125 = extractelement <4 x float> %123, i32 1
>  %126 = extractelement <4 x float> %123, i32 2
>  %127 = fmul float %87, 2.000000e+00
>  %128 = fmul float %88, 2.000000e+00
>  %129 = fmul float %89, 2.000000e+00
>  %130 = fmul float %97, 1.000000e+00
>  %131 = call float @llvm.AMDIL.clamp.(float %127, float 0.000000e+00, float 1.000000e+00)
>  %132 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
>  %133 = call float @llvm.AMDIL.clamp.(float %129, float 0.000000e+00, float 1.000000e+00)
>  %134 = call float @llvm.AMDIL.clamp.(float %130, float 0.000000e+00, float 1.000000e+00)
>  %135 = fmul float %87, 2.000000e+00
>  %136 = fmul float %88, 2.000000e+00
>  %137 = fmul float %89, 2.000000e+00
>  %138 = fmul float %97, 1.000000e+00
>  %139 = call float @llvm.AMDIL.clamp.(float %135, float 0.000000e+00, float 1.000000e+00)
>  %140 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
>  %141 = call float @llvm.AMDIL.clamp.(float %137, float 0.000000e+00, float 1.000000e+00)
>  %142 = call float @llvm.AMDIL.clamp.(float %138, float 0.000000e+00, float 1.000000e+00)
>  %143 = fmul float %124, %134
>  %144 = fadd float %143, %139
>  %145 = fmul float %125, %134
>  %146 = fadd float %145, %140
>  %147 = fmul float %126, %134
>  %148 = fadd float %147, %141
>  %149 = call float @llvm.AMDIL.clamp.(float %144, float 0.000000e+00, float 1.000000e+00)
>  %150 = call float @llvm.AMDIL.clamp.(float %146, float 0.000000e+00, float 1.000000e+00)
>  %151 = call float @llvm.AMDIL.clamp.(float %148, float 0.000000e+00, float 1.000000e+00)
>  %152 = fmul float %87, 2.000000e+00
>  %153 = fmul float %88, 2.000000e+00
>  %154 = fmul float %89, 2.000000e+00
>  %155 = fmul float %97, 1.000000e+00
>  %156 = call float @llvm.AMDIL.clamp.(float %152, float 0.000000e+00, float 1.000000e+00)
>  %157 = call float @llvm.AMDIL.clamp.(float %153, float 0.000000e+00, float 1.000000e+00)
>  %158 = call float @llvm.AMDIL.clamp.(float %154, float 0.000000e+00, float 1.000000e+00)
>  %159 = call float @llvm.AMDIL.clamp.(float %155, float 0.000000e+00, float 1.000000e+00)
>  %160 = fmul float %43, %22
>  %161 = fadd float %160, %23
>  %162 = call float @llvm.AMDIL.clamp.(float %161, float 0.000000e+00, float 1.000000e+00)
>  %163 = fsub float -0.000000e+00, %162
>  %164 = fadd float 1.000000e+00, %163
>  %165 = fmul float %24, %164
>  %166 = fmul float %25, %164
>  %167 = fmul float %26, %164
>  %168 = fmul float %149, %162
>  %169 = fadd float %168, %165
>  %170 = fmul float %150, %162
>  %171 = fadd float %170, %166
>  %172 = fmul float %151, %162
>  %173 = fadd float %172, %167
>  %174 = call i32 @llvm.SI.packf16(float %169, float %171)
>  %175 = bitcast i32 %174 to float
>  %176 = call i32 @llvm.SI.packf16(float %173, float %159)
>  %177 = bitcast i32 %176 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %175, float %177, float %175, float %177)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8081100
>c8091101
>c80c1300
>c80d1301
>7e0c5503
>10060d02
>c81c1000
>c81d1001
>10040d07
>c81c1200
>c81d1201
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430207
>c8140900
>c8150901
>c8180b00
>c8190b01
>7e0e5506
>100c0f05
>c8200800
>c8210801
>100a0f08
>c0840308
>c0c60510
>bf8c0070
>f0800f00
>00430505
>c8240100
>c8250101
>bf8c0770
>10141306
>d2820009
>042a1306
>d206080c
>02010109
>c8240d00
>c8250d01
>c8280f00
>c8290f01
>7e16550a
>10141709
>c8340c00
>c8350c01
>1012170d
>c0840304
>c0c60508
>bf8c007f
>f0800700
>00430909
>bf8c0770
>101a190a
>d282000c
>0436190a
>d206080d
>0201010c
>c8300300
>c8310301
>10181908
>d206080c
>0201010c
>d206080c
>0201010c
>d282000d
>04361903
>d206080f
>0201010d
>c8340400
>c8350401
>c0800100
>bf8c007f
>c202010c
>c202810d
>bf8c007f
>7e1c0205
>d282000d
>0438090d
>d206080d
>0201010d
>081c1af2
>c2020111
>bf8c007f
>10201c04
>d282000f
>04421b0f
>c8400000
>c8410001
>10222105
>d2820010
>04462105
>d2060810
>02010110
>10222109
>d2820010
>04462109
>d2060810
>02010110
>d2820010
>04421902
>d2060810
>02010110
>c2020110
>bf8c007f
>10221c04
>d2820010
>04461b10
>5e1e1f10
>c8400200
>c8410201
>10002107
>d2820000
>04022107
>d2060800
>02010100
>1002010b
>d2820000
>0406010b
>d2060800
>02010100
>d2820000
>04021904
>d2060800
>02010100
>c2000112
>bf8c007f
>10021c00
>d2820000
>04061b00
>5e001900
>f8001c0f
>000f000f
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL OUT[5], GENERIC[2]
>DCL CONST[0..14]
>DCL CONST[16..27]
>DCL TEMP[0..5]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: DP4 TEMP[1], IN[0], CONST[13]
> 15: ABS OUT[2].x, TEMP[1]
> 16: MOV OUT[2].yzw, IMM[0].xxxy
> 17: MOV OUT[3], IN[3]
> 18: MUL TEMP[2], IN[4].xxxx, CONST[16]
> 19: MAD TEMP[2], IN[4].yyyy, CONST[17], TEMP[2]
> 20: MAD TEMP[2], IN[4].zzzz, CONST[18], TEMP[2]
> 21: MAD OUT[4], IN[4].wwww, CONST[19], TEMP[2]
> 22: MUL TEMP[3], IN[0].xxxx, CONST[20]
> 23: MAD TEMP[3], IN[0].yyyy, CONST[21], TEMP[3]
> 24: MAD TEMP[3], IN[0].zzzz, CONST[22], TEMP[3]
> 25: MAD TEMP[3], IN[0].wwww, CONST[23], TEMP[3]
> 26: DP3 TEMP[4].x, TEMP[3], TEMP[3]
> 27: RSQ TEMP[4].x, |TEMP[4]|
> 28: MUL TEMP[5], TEMP[3], TEMP[4].xxxx
> 29: DP3 TEMP[4], TEMP[0], TEMP[5]
> 30: ADD TEMP[4], TEMP[4], TEMP[4]
> 31: MAD TEMP[2].xyz, -TEMP[4], TEMP[0], TEMP[5]
> 32: MOV TEMP[2].w, IN[5]
> 33: MUL TEMP[4], TEMP[2].xxxx, CONST[24]
> 34: MAD TEMP[4], TEMP[2].yyyy, CONST[25], TEMP[4]
> 35: MAD TEMP[4], TEMP[2].zzzz, CONST[26], TEMP[4]
> 36: MAD OUT[5], TEMP[2].wwww, CONST[27], TEMP[4]
> 37: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 268)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 284)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 300)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 444)
>  %91 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0
>  %93 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %92, i32 0, i32 %5)
>  %94 = extractelement <4 x float> %93, i32 0
>  %95 = extractelement <4 x float> %93, i32 1
>  %96 = extractelement <4 x float> %93, i32 2
>  %97 = extractelement <4 x float> %93, i32 3
>  %98 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %99 = load <16 x i8> addrspace(2)* %98, !tbaa !0
>  %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %99, i32 0, i32 %5)
>  %101 = extractelement <4 x float> %100, i32 0
>  %102 = extractelement <4 x float> %100, i32 1
>  %103 = extractelement <4 x float> %100, i32 2
>  %104 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %105 = load <16 x i8> addrspace(2)* %104, !tbaa !0
>  %106 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %105, i32 0, i32 %5)
>  %107 = extractelement <4 x float> %106, i32 0
>  %108 = extractelement <4 x float> %106, i32 1
>  %109 = extractelement <4 x float> %106, i32 2
>  %110 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %111 = load <16 x i8> addrspace(2)* %110, !tbaa !0
>  %112 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %111, i32 0, i32 %5)
>  %113 = extractelement <4 x float> %112, i32 0
>  %114 = extractelement <4 x float> %112, i32 1
>  %115 = extractelement <4 x float> %112, i32 2
>  %116 = extractelement <4 x float> %112, i32 3
>  %117 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %118 = load <16 x i8> addrspace(2)* %117, !tbaa !0
>  %119 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %118, i32 0, i32 %5)
>  %120 = extractelement <4 x float> %119, i32 0
>  %121 = extractelement <4 x float> %119, i32 1
>  %122 = extractelement <4 x float> %119, i32 2
>  %123 = extractelement <4 x float> %119, i32 3
>  %124 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %125 = load <16 x i8> addrspace(2)* %124, !tbaa !0
>  %126 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %125, i32 0, i32 %5)
>  %127 = extractelement <4 x float> %126, i32 3
>  %128 = fmul float %94, %11
>  %129 = fmul float %94, %12
>  %130 = fmul float %94, %13
>  %131 = fmul float %94, %14
>  %132 = fmul float %95, %15
>  %133 = fadd float %132, %128
>  %134 = fmul float %95, %16
>  %135 = fadd float %134, %129
>  %136 = fmul float %95, %17
>  %137 = fadd float %136, %130
>  %138 = fmul float %95, %18
>  %139 = fadd float %138, %131
>  %140 = fmul float %96, %19
>  %141 = fadd float %140, %133
>  %142 = fmul float %96, %20
>  %143 = fadd float %142, %135
>  %144 = fmul float %96, %21
>  %145 = fadd float %144, %137
>  %146 = fmul float %96, %22
>  %147 = fadd float %146, %139
>  %148 = fmul float %97, %23
>  %149 = fadd float %148, %141
>  %150 = fmul float %97, %24
>  %151 = fadd float %150, %143
>  %152 = fmul float %97, %25
>  %153 = fadd float %152, %145
>  %154 = fmul float %97, %26
>  %155 = fadd float %154, %147
>  %156 = fmul float %101, %27
>  %157 = fmul float %102, %28
>  %158 = fadd float %157, %156
>  %159 = fmul float %103, %29
>  %160 = fadd float %158, %159
>  %161 = fmul float %101, %30
>  %162 = fmul float %102, %31
>  %163 = fadd float %162, %161
>  %164 = fmul float %103, %32
>  %165 = fadd float %163, %164
>  %166 = fmul float %101, %33
>  %167 = fmul float %102, %34
>  %168 = fadd float %167, %166
>  %169 = fmul float %103, %35
>  %170 = fadd float %168, %169
>  %171 = fmul float %160, %160
>  %172 = fmul float %165, %165
>  %173 = fadd float %172, %171
>  %174 = fmul float %170, %170
>  %175 = fadd float %173, %174
>  %176 = call float @fabs(float %175)
>  %177 = call float @llvm.AMDGPU.rsq(float %176)
>  %178 = fmul float %160, %177
>  %179 = fmul float %165, %177
>  %180 = fmul float %170, %177
>  %181 = fmul float %36, %39
>  %182 = fadd float %181, %107
>  %183 = fmul float %37, %40
>  %184 = fadd float %183, %108
>  %185 = fmul float %38, %41
>  %186 = fadd float %185, %109
>  %187 = call float @llvm.AMDIL.clamp.(float %182, float 0.000000e+00, float 1.000000e+00)
>  %188 = call float @llvm.AMDIL.clamp.(float %184, float 0.000000e+00, float 1.000000e+00)
>  %189 = call float @llvm.AMDIL.clamp.(float %186, float 0.000000e+00, float 1.000000e+00)
>  %190 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %191 = fmul float %94, %43
>  %192 = fmul float %95, %44
>  %193 = fadd float %191, %192
>  %194 = fmul float %96, %45
>  %195 = fadd float %193, %194
>  %196 = fmul float %97, %46
>  %197 = fadd float %195, %196
>  %198 = call float @fabs(float %197)
>  %199 = fmul float %120, %47
>  %200 = fmul float %120, %48
>  %201 = fmul float %120, %49
>  %202 = fmul float %120, %50
>  %203 = fmul float %121, %51
>  %204 = fadd float %203, %199
>  %205 = fmul float %121, %52
>  %206 = fadd float %205, %200
>  %207 = fmul float %121, %53
>  %208 = fadd float %207, %201
>  %209 = fmul float %121, %54
>  %210 = fadd float %209, %202
>  %211 = fmul float %122, %55
>  %212 = fadd float %211, %204
>  %213 = fmul float %122, %56
>  %214 = fadd float %213, %206
>  %215 = fmul float %122, %57
>  %216 = fadd float %215, %208
>  %217 = fmul float %122, %58
>  %218 = fadd float %217, %210
>  %219 = fmul float %123, %59
>  %220 = fadd float %219, %212
>  %221 = fmul float %123, %60
>  %222 = fadd float %221, %214
>  %223 = fmul float %123, %61
>  %224 = fadd float %223, %216
>  %225 = fmul float %123, %62
>  %226 = fadd float %225, %218
>  %227 = fmul float %94, %63
>  %228 = fmul float %94, %64
>  %229 = fmul float %94, %65
>  %230 = fmul float %95, %66
>  %231 = fadd float %230, %227
>  %232 = fmul float %95, %67
>  %233 = fadd float %232, %228
>  %234 = fmul float %95, %68
>  %235 = fadd float %234, %229
>  %236 = fmul float %96, %69
>  %237 = fadd float %236, %231
>  %238 = fmul float %96, %70
>  %239 = fadd float %238, %233
>  %240 = fmul float %96, %71
>  %241 = fadd float %240, %235
>  %242 = fmul float %97, %72
>  %243 = fadd float %242, %237
>  %244 = fmul float %97, %73
>  %245 = fadd float %244, %239
>  %246 = fmul float %97, %74
>  %247 = fadd float %246, %241
>  %248 = fmul float %243, %243
>  %249 = fmul float %245, %245
>  %250 = fadd float %249, %248
>  %251 = fmul float %247, %247
>  %252 = fadd float %250, %251
>  %253 = call float @fabs(float %252)
>  %254 = call float @llvm.AMDGPU.rsq(float %253)
>  %255 = fmul float %243, %254
>  %256 = fmul float %245, %254
>  %257 = fmul float %247, %254
>  %258 = fmul float %178, %255
>  %259 = fmul float %179, %256
>  %260 = fadd float %259, %258
>  %261 = fmul float %180, %257
>  %262 = fadd float %260, %261
>  %263 = fadd float %262, %262
>  %264 = fadd float %262, %262
>  %265 = fadd float %262, %262
>  %266 = fsub float -0.000000e+00, %263
>  %267 = fmul float %266, %178
>  %268 = fadd float %267, %255
>  %269 = fsub float -0.000000e+00, %264
>  %270 = fmul float %269, %179
>  %271 = fadd float %270, %256
>  %272 = fsub float -0.000000e+00, %265
>  %273 = fmul float %272, %180
>  %274 = fadd float %273, %257
>  %275 = fmul float %268, %75
>  %276 = fmul float %268, %76
>  %277 = fmul float %268, %77
>  %278 = fmul float %268, %78
>  %279 = fmul float %271, %79
>  %280 = fadd float %279, %275
>  %281 = fmul float %271, %80
>  %282 = fadd float %281, %276
>  %283 = fmul float %271, %81
>  %284 = fadd float %283, %277
>  %285 = fmul float %271, %82
>  %286 = fadd float %285, %278
>  %287 = fmul float %274, %83
>  %288 = fadd float %287, %280
>  %289 = fmul float %274, %84
>  %290 = fadd float %289, %282
>  %291 = fmul float %274, %85
>  %292 = fadd float %291, %284
>  %293 = fmul float %274, %86
>  %294 = fadd float %293, %286
>  %295 = fmul float %127, %87
>  %296 = fadd float %295, %288
>  %297 = fmul float %127, %88
>  %298 = fadd float %297, %290
>  %299 = fmul float %127, %89
>  %300 = fadd float %299, %292
>  %301 = fmul float %127, %90
>  %302 = fadd float %301, %294
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %187, float %188, float %189, float %190)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %198, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %113, float %114, float %115, float %116)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %220, float %222, float %224, float %226)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %296, float %298, float %300, float %302)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %149, float %151, float %153, float %155)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c0840700
>bf8c000f
>e00c2000
>80020100
>c2020135
>bf8c0070
>100a0404
>c2020134
>bf8c007f
>d2820005
>04140901
>c2020136
>bf8c007f
>d2820005
>04140903
>c2020137
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c084070c
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800022f
>08070605
>c0840710
>bf8c000f
>e00c2000
>80020500
>c2020143
>bf8c0070
>10120a04
>c2020147
>bf8c007f
>d2820009
>04240906
>c202014b
>bf8c007f
>d2820009
>04240907
>c202014f
>bf8c007f
>d2820009
>04240908
>c2020142
>bf8c007f
>10140a04
>c2020146
>bf8c007f
>d282000a
>04280906
>c202014a
>bf8c007f
>d282000a
>04280907
>c202014e
>bf8c007f
>d282000a
>04280908
>c2020141
>bf8c007f
>10160a04
>c2020145
>bf8c007f
>d282000b
>042c0906
>c2020149
>bf8c007f
>d282000b
>042c0907
>c202014d
>bf8c007f
>d282000b
>042c0908
>c2020140
>bf8c007f
>10180a04
>c2020144
>bf8c007f
>d282000c
>04300906
>c2020148
>bf8c007f
>d282000c
>04300907
>c202014c
>bf8c007f
>d2820005
>04300908
>f800023f
>090a0b05
>c0840704
>bf8c000f
>e00c2000
>80020600
>c2020114
>bf8c0070
>100a0c04
>c2020115
>bf8c007f
>d2820005
>04140907
>c2020116
>bf8c007f
>d2820005
>04140908
>c2020110
>bf8c007f
>10140c04
>c2020111
>bf8c007f
>d282000a
>04280907
>c2020112
>bf8c007f
>d282000a
>04280908
>1016150a
>d282000b
>042e0b05
>c2020118
>bf8c007f
>10180c04
>c2020119
>bf8c007f
>d282000c
>04300907
>c202011a
>bf8c007f
>d2820007
>04300908
>d2820006
>042e0f07
>d2060106
>02010106
>7e105b06
>100c110a
>c2020151
>bf8c007f
>10120204
>c2020155
>bf8c007f
>d2820009
>04240902
>c2020159
>bf8c007f
>d2820009
>04240903
>c202015d
>bf8c007f
>d2820009
>04240904
>c2020150
>bf8c007f
>10140204
>c2020154
>bf8c007f
>d282000a
>04280902
>c2020158
>bf8c007f
>d282000a
>04280903
>c202015c
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c2020152
>bf8c007f
>10160204
>c2020156
>bf8c007f
>d282000b
>042c0902
>c202015a
>bf8c007f
>d282000b
>042c0903
>c202015e
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101c1506
>100a1105
>101a1909
>d2820009
>043a1b05
>100e1107
>1010190b
>d2820009
>04261107
>06121309
>100a0b09
>080a0b0d
>100c0d09
>080c0d0a
>c2020163
>bf8c007f
>10140c04
>c2020167
>bf8c007f
>d282000a
>04280905
>100e0f09
>080e0f08
>c202016b
>bf8c007f
>d282000c
>04280907
>c0820714
>bf8c007f
>e00c2000
>80010800
>c202016f
>bf8c0070
>d2820000
>0430090b
>c2020162
>bf8c007f
>10180c04
>c2020166
>bf8c007f
>d282000c
>04300905
>c202016a
>bf8c007f
>d282000c
>04300907
>c202016e
>bf8c007f
>d282000c
>0430090b
>c2020161
>bf8c007f
>101a0c04
>c2020165
>bf8c007f
>d282000d
>04340905
>c2020169
>bf8c007f
>d282000d
>04340907
>c202016d
>bf8c007f
>d282000d
>0434090b
>c2020160
>bf8c007f
>100c0c04
>c2020164
>bf8c007f
>d2820005
>04180905
>c2020168
>bf8c007f
>d2820005
>04140907
>c202016c
>bf8c007f
>d2820005
>0414090b
>f800024f
>000c0d05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..14]
>DCL TEMP[0..3]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: DP4 TEMP[1], IN[0], CONST[13]
> 15: ABS OUT[2].x, TEMP[1]
> 16: MOV OUT[2].yzw, IMM[0].xxxy
> 17: MOV OUT[3], IN[3]
> 18: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
>  %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %5)
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = extractelement <4 x float> %62, i32 1
>  %65 = extractelement <4 x float> %62, i32 2
>  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
>  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
>  %69 = extractelement <4 x float> %68, i32 0
>  %70 = extractelement <4 x float> %68, i32 1
>  %71 = extractelement <4 x float> %68, i32 2
>  %72 = extractelement <4 x float> %68, i32 3
>  %73 = fmul float %50, %11
>  %74 = fmul float %50, %12
>  %75 = fmul float %50, %13
>  %76 = fmul float %50, %14
>  %77 = fmul float %51, %15
>  %78 = fadd float %77, %73
>  %79 = fmul float %51, %16
>  %80 = fadd float %79, %74
>  %81 = fmul float %51, %17
>  %82 = fadd float %81, %75
>  %83 = fmul float %51, %18
>  %84 = fadd float %83, %76
>  %85 = fmul float %52, %19
>  %86 = fadd float %85, %78
>  %87 = fmul float %52, %20
>  %88 = fadd float %87, %80
>  %89 = fmul float %52, %21
>  %90 = fadd float %89, %82
>  %91 = fmul float %52, %22
>  %92 = fadd float %91, %84
>  %93 = fmul float %53, %23
>  %94 = fadd float %93, %86
>  %95 = fmul float %53, %24
>  %96 = fadd float %95, %88
>  %97 = fmul float %53, %25
>  %98 = fadd float %97, %90
>  %99 = fmul float %53, %26
>  %100 = fadd float %99, %92
>  %101 = fmul float %57, %27
>  %102 = fmul float %58, %28
>  %103 = fadd float %102, %101
>  %104 = fmul float %59, %29
>  %105 = fadd float %103, %104
>  %106 = fmul float %57, %30
>  %107 = fmul float %58, %31
>  %108 = fadd float %107, %106
>  %109 = fmul float %59, %32
>  %110 = fadd float %108, %109
>  %111 = fmul float %57, %33
>  %112 = fmul float %58, %34
>  %113 = fadd float %112, %111
>  %114 = fmul float %59, %35
>  %115 = fadd float %113, %114
>  %116 = fmul float %105, %105
>  %117 = fmul float %110, %110
>  %118 = fadd float %117, %116
>  %119 = fmul float %115, %115
>  %120 = fadd float %118, %119
>  %121 = call float @fabs(float %120)
>  %122 = call float @llvm.AMDGPU.rsq(float %121)
>  %123 = fmul float %36, %39
>  %124 = fadd float %123, %63
>  %125 = fmul float %37, %40
>  %126 = fadd float %125, %64
>  %127 = fmul float %38, %41
>  %128 = fadd float %127, %65
>  %129 = call float @llvm.AMDIL.clamp.(float %124, float 0.000000e+00, float 1.000000e+00)
>  %130 = call float @llvm.AMDIL.clamp.(float %126, float 0.000000e+00, float 1.000000e+00)
>  %131 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
>  %132 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %133 = fmul float %50, %43
>  %134 = fmul float %51, %44
>  %135 = fadd float %133, %134
>  %136 = fmul float %52, %45
>  %137 = fadd float %135, %136
>  %138 = fmul float %53, %46
>  %139 = fadd float %137, %138
>  %140 = call float @fabs(float %139)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %129, float %130, float %131, float %132)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %140, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %69, float %70, float %71, float %72)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %94, float %96, float %98, float %100)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c0840700
>bf8c000f
>e00c2000
>80020100
>c2020135
>bf8c0070
>100a0404
>c2020134
>bf8c007f
>d2820005
>04140901
>c2020136
>bf8c007f
>d2820005
>04140903
>c2020137
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = fmul float %34, %11
>  %53 = fmul float %34, %12
>  %54 = fmul float %34, %13
>  %55 = fmul float %34, %14
>  %56 = fmul float %35, %15
>  %57 = fadd float %56, %52
>  %58 = fmul float %35, %16
>  %59 = fadd float %58, %53
>  %60 = fmul float %35, %17
>  %61 = fadd float %60, %54
>  %62 = fmul float %35, %18
>  %63 = fadd float %62, %55
>  %64 = fmul float %36, %19
>  %65 = fadd float %64, %57
>  %66 = fmul float %36, %20
>  %67 = fadd float %66, %59
>  %68 = fmul float %36, %21
>  %69 = fadd float %68, %61
>  %70 = fmul float %36, %22
>  %71 = fadd float %70, %63
>  %72 = fmul float %37, %23
>  %73 = fadd float %72, %65
>  %74 = fmul float %37, %24
>  %75 = fadd float %74, %67
>  %76 = fmul float %37, %25
>  %77 = fadd float %76, %69
>  %78 = fmul float %37, %26
>  %79 = fadd float %78, %71
>  %80 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %81 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %82 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %83 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %84 = fmul float %34, %27
>  %85 = fmul float %35, %28
>  %86 = fadd float %84, %85
>  %87 = fmul float %36, %29
>  %88 = fadd float %86, %87
>  %89 = fmul float %37, %30
>  %90 = fadd float %88, %89
>  %91 = call float @fabs(float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %80, float %81, float %82, float %83)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %91, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %73, float %75, float %77, float %79)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL IN[4], GENERIC[2], PERSPECTIVE
>DCL IN[5], GENERIC[3], PERSPECTIVE
>DCL IN[6], GENERIC[4], PERSPECTIVE
>DCL IN[7], GENERIC[6], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL SAMP[4]
>DCL SAMP[5]
>DCL CONST[6..8]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     2.0000,     0.0000,     0.0000}
>  0: TXP TEMP[0], IN[2], SAMP[5], CUBE
>  1: MOV TEMP[1].xy, IN[3].xyyy
>  2: MOV TEMP[1].w, IN[3].wwww
>  3: TXP TEMP[1], TEMP[1], SAMP[4], 2D
>  4: MOV TEMP[2].xy, IN[4].xyyy
>  5: MOV TEMP[2].w, IN[4].wwww
>  6: TXP TEMP[2], TEMP[2], SAMP[3], 2D
>  7: MAD TEMP[0].xyz, IN[0], TEMP[0].wwww, TEMP[0]
>  8: MOV_SAT TEMP[0].xyz, TEMP[0].xyzz
>  9: MOV TEMP[0].w, IN[0].wwww
> 10: MUL TEMP[0].xyz, TEMP[1], TEMP[0]
> 11: MOV TEMP[0].xyz, TEMP[0].xyzx
> 12: MOV TEMP[0].w, TEMP[1].wwww
> 13: ADD TEMP[1].x, IMM[0].xxxx, -TEMP[2].wwww
> 14: MUL_SAT TEMP[0], TEMP[0], IMM[0].yyyx
> 15: MUL TEMP[0], TEMP[0], TEMP[2].wwww
> 16: MAD TEMP[0].xyz, TEMP[2], TEMP[1].xxxx, TEMP[0]
> 17: MOV TEMP[0].xyz, TEMP[0].xyzx
> 18: MOV TEMP[1].xy, IN[5].xyyy
> 19: MOV TEMP[1].w, IN[5].wwww
> 20: TXP TEMP[1].w, TEMP[1], SAMP[2], 2D
> 21: MOV TEMP[0].w, TEMP[1].wwww
> 22: ADD TEMP[2].x, IMM[0].xxxx, -TEMP[1].wwww
> 23: TXP TEMP[3], IN[6], SAMP[1], CUBE
> 24: MUL TEMP[3], TEMP[3], TEMP[1].wwww
> 25: MAD TEMP[0].xyz, TEMP[0], TEMP[2].xxxx, TEMP[3]
> 26: MOV TEMP[0].xyz, TEMP[0].xyzx
> 27: MOV TEMP[0].w, TEMP[1].wwww
> 28: MUL TEMP[0].xyz, IN[0], TEMP[0]
> 29: MOV TEMP[0].xyz, TEMP[0].xyzx
> 30: MOV TEMP[0].w, TEMP[1].wwww
> 31: MOV TEMP[1].xy, IN[7].xyyy
> 32: MOV TEMP[1].w, IN[7].wwww
> 33: TXP TEMP[1], TEMP[1], SAMP[0], 2D
> 34: MUL_SAT TEMP[2], TEMP[0], IMM[0].yyyx
> 35: MUL TEMP[1].xyz, TEMP[1], TEMP[2]
> 36: MOV TEMP[1].xyz, TEMP[1].xyzx
> 37: MUL_SAT TEMP[0], TEMP[0], IMM[0].yyyx
> 38: MOV TEMP[1].w, TEMP[0].wwww
> 39: MUL_SAT TEMP[0], TEMP[1], IMM[0].yyyx
> 40: MOV TEMP[1].w, TEMP[0]
> 41: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[6].xxxx, CONST[6].yyyy
> 42: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].xxxx
> 43: MUL TEMP[3].xyz, CONST[7].xyzz, TEMP[3].xxxx
> 44: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 45: MOV OUT[0], TEMP[1]
> 46: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 100)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 116)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 120)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %36 = load <32 x i8> addrspace(2)* %35, !tbaa !0
>  %37 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
>  %39 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
>  %40 = load <32 x i8> addrspace(2)* %39, !tbaa !0
>  %41 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
>  %44 = load <32 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
>  %48 = load <32 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
>  %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0
>  %51 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %52 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %53 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %54 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %55 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %56 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %57 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
>  %58 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %59 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %60 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %61 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %62 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %63 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %64 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %65 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
>  %66 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
>  %67 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %3, <2 x i32> %5)
>  %68 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %5)
>  %69 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %5)
>  %70 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %3, <2 x i32> %5)
>  %71 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %3, <2 x i32> %5)
>  %72 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %3, <2 x i32> %5)
>  %73 = call float @llvm.SI.fs.interp(i32 1, i32 7, i32 %3, <2 x i32> %5)
>  %74 = call float @llvm.SI.fs.interp(i32 3, i32 7, i32 %3, <2 x i32> %5)
>  %75 = fdiv float %55, %58
>  %76 = fdiv float %56, %58
>  %77 = fdiv float %57, %58
>  %78 = insertelement <4 x float> undef, float %75, i32 0
>  %79 = insertelement <4 x float> %78, float %76, i32 1
>  %80 = insertelement <4 x float> %79, float %77, i32 2
>  %81 = insertelement <4 x float> %80, float 1.000000e+00, i32 3
>  %82 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %81)
>  %83 = extractelement <4 x float> %82, i32 0
>  %84 = extractelement <4 x float> %82, i32 1
>  %85 = extractelement <4 x float> %82, i32 2
>  %86 = extractelement <4 x float> %82, i32 3
>  %87 = call float @fabs(float %85)
>  %88 = fdiv float 1.000000e+00, %87
>  %89 = fmul float %83, %88
>  %90 = fadd float %89, 1.500000e+00
>  %91 = fmul float %84, %88
>  %92 = fadd float %91, 1.500000e+00
>  %93 = bitcast float %92 to i32
>  %94 = bitcast float %90 to i32
>  %95 = bitcast float %86 to i32
>  %96 = insertelement <4 x i32> undef, i32 %93, i32 0
>  %97 = insertelement <4 x i32> %96, i32 %94, i32 1
>  %98 = insertelement <4 x i32> %97, i32 %95, i32 2
>  %99 = insertelement <4 x i32> %98, i32 undef, i32 3
>  %100 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %99, <32 x i8> %48, <16 x i8> %50, i32 4)
>  %101 = extractelement <4 x float> %100, i32 0
>  %102 = extractelement <4 x float> %100, i32 1
>  %103 = extractelement <4 x float> %100, i32 2
>  %104 = extractelement <4 x float> %100, i32 3
>  %105 = fdiv float %59, %61
>  %106 = fdiv float %60, %61
>  %107 = bitcast float %105 to i32
>  %108 = bitcast float %106 to i32
>  %109 = insertelement <2 x i32> undef, i32 %107, i32 0
>  %110 = insertelement <2 x i32> %109, i32 %108, i32 1
>  %111 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %110, <32 x i8> %44, <16 x i8> %46, i32 2)
>  %112 = extractelement <4 x float> %111, i32 0
>  %113 = extractelement <4 x float> %111, i32 1
>  %114 = extractelement <4 x float> %111, i32 2
>  %115 = extractelement <4 x float> %111, i32 3
>  %116 = fdiv float %62, %64
>  %117 = fdiv float %63, %64
>  %118 = bitcast float %116 to i32
>  %119 = bitcast float %117 to i32
>  %120 = insertelement <2 x i32> undef, i32 %118, i32 0
>  %121 = insertelement <2 x i32> %120, i32 %119, i32 1
>  %122 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %121, <32 x i8> %40, <16 x i8> %42, i32 2)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = extractelement <4 x float> %122, i32 1
>  %125 = extractelement <4 x float> %122, i32 2
>  %126 = extractelement <4 x float> %122, i32 3
>  %127 = fmul float %51, %104
>  %128 = fadd float %127, %101
>  %129 = fmul float %52, %104
>  %130 = fadd float %129, %102
>  %131 = fmul float %53, %104
>  %132 = fadd float %131, %103
>  %133 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
>  %134 = call float @llvm.AMDIL.clamp.(float %130, float 0.000000e+00, float 1.000000e+00)
>  %135 = call float @llvm.AMDIL.clamp.(float %132, float 0.000000e+00, float 1.000000e+00)
>  %136 = fmul float %112, %133
>  %137 = fmul float %113, %134
>  %138 = fmul float %114, %135
>  %139 = fsub float -0.000000e+00, %126
>  %140 = fadd float 1.000000e+00, %139
>  %141 = fmul float %136, 2.000000e+00
>  %142 = fmul float %137, 2.000000e+00
>  %143 = fmul float %138, 2.000000e+00
>  %144 = fmul float %115, 1.000000e+00
>  %145 = call float @llvm.AMDIL.clamp.(float %141, float 0.000000e+00, float 1.000000e+00)
>  %146 = call float @llvm.AMDIL.clamp.(float %142, float 0.000000e+00, float 1.000000e+00)
>  %147 = call float @llvm.AMDIL.clamp.(float %143, float 0.000000e+00, float 1.000000e+00)
>  %148 = call float @llvm.AMDIL.clamp.(float %144, float 0.000000e+00, float 1.000000e+00)
>  %149 = fmul float %145, %126
>  %150 = fmul float %146, %126
>  %151 = fmul float %147, %126
>  %152 = fmul float %123, %140
>  %153 = fadd float %152, %149
>  %154 = fmul float %124, %140
>  %155 = fadd float %154, %150
>  %156 = fmul float %125, %140
>  %157 = fadd float %156, %151
>  %158 = fdiv float %65, %67
>  %159 = fdiv float %66, %67
>  %160 = bitcast float %158 to i32
>  %161 = bitcast float %159 to i32
>  %162 = insertelement <2 x i32> undef, i32 %160, i32 0
>  %163 = insertelement <2 x i32> %162, i32 %161, i32 1
>  %164 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %163, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %165 = extractelement <4 x float> %164, i32 3
>  %166 = fsub float -0.000000e+00, %165
>  %167 = fadd float 1.000000e+00, %166
>  %168 = fdiv float %68, %71
>  %169 = fdiv float %69, %71
>  %170 = fdiv float %70, %71
>  %171 = insertelement <4 x float> undef, float %168, i32 0
>  %172 = insertelement <4 x float> %171, float %169, i32 1
>  %173 = insertelement <4 x float> %172, float %170, i32 2
>  %174 = insertelement <4 x float> %173, float 1.000000e+00, i32 3
>  %175 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %174)
>  %176 = extractelement <4 x float> %175, i32 0
>  %177 = extractelement <4 x float> %175, i32 1
>  %178 = extractelement <4 x float> %175, i32 2
>  %179 = extractelement <4 x float> %175, i32 3
>  %180 = call float @fabs(float %178)
>  %181 = fdiv float 1.000000e+00, %180
>  %182 = fmul float %176, %181
>  %183 = fadd float %182, 1.500000e+00
>  %184 = fmul float %177, %181
>  %185 = fadd float %184, 1.500000e+00
>  %186 = bitcast float %185 to i32
>  %187 = bitcast float %183 to i32
>  %188 = bitcast float %179 to i32
>  %189 = insertelement <4 x i32> undef, i32 %186, i32 0
>  %190 = insertelement <4 x i32> %189, i32 %187, i32 1
>  %191 = insertelement <4 x i32> %190, i32 %188, i32 2
>  %192 = insertelement <4 x i32> %191, i32 undef, i32 3
>  %193 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %192, <32 x i8> %32, <16 x i8> %34, i32 4)
>  %194 = extractelement <4 x float> %193, i32 0
>  %195 = extractelement <4 x float> %193, i32 1
>  %196 = extractelement <4 x float> %193, i32 2
>  %197 = fmul float %194, %165
>  %198 = fmul float %195, %165
>  %199 = fmul float %196, %165
>  %200 = fmul float %153, %167
>  %201 = fadd float %200, %197
>  %202 = fmul float %155, %167
>  %203 = fadd float %202, %198
>  %204 = fmul float %157, %167
>  %205 = fadd float %204, %199
>  %206 = fmul float %51, %201
>  %207 = fmul float %52, %203
>  %208 = fmul float %53, %205
>  %209 = fdiv float %72, %74
>  %210 = fdiv float %73, %74
>  %211 = bitcast float %209 to i32
>  %212 = bitcast float %210 to i32
>  %213 = insertelement <2 x i32> undef, i32 %211, i32 0
>  %214 = insertelement <2 x i32> %213, i32 %212, i32 1
>  %215 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %214, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %216 = extractelement <4 x float> %215, i32 0
>  %217 = extractelement <4 x float> %215, i32 1
>  %218 = extractelement <4 x float> %215, i32 2
>  %219 = fmul float %206, 2.000000e+00
>  %220 = fmul float %207, 2.000000e+00
>  %221 = fmul float %208, 2.000000e+00
>  %222 = fmul float %165, 1.000000e+00
>  %223 = call float @llvm.AMDIL.clamp.(float %219, float 0.000000e+00, float 1.000000e+00)
>  %224 = call float @llvm.AMDIL.clamp.(float %220, float 0.000000e+00, float 1.000000e+00)
>  %225 = call float @llvm.AMDIL.clamp.(float %221, float 0.000000e+00, float 1.000000e+00)
>  %226 = call float @llvm.AMDIL.clamp.(float %222, float 0.000000e+00, float 1.000000e+00)
>  %227 = fmul float %216, %223
>  %228 = fmul float %217, %224
>  %229 = fmul float %218, %225
>  %230 = fmul float %206, 2.000000e+00
>  %231 = fmul float %207, 2.000000e+00
>  %232 = fmul float %208, 2.000000e+00
>  %233 = fmul float %165, 1.000000e+00
>  %234 = call float @llvm.AMDIL.clamp.(float %230, float 0.000000e+00, float 1.000000e+00)
>  %235 = call float @llvm.AMDIL.clamp.(float %231, float 0.000000e+00, float 1.000000e+00)
>  %236 = call float @llvm.AMDIL.clamp.(float %232, float 0.000000e+00, float 1.000000e+00)
>  %237 = call float @llvm.AMDIL.clamp.(float %233, float 0.000000e+00, float 1.000000e+00)
>  %238 = fmul float %227, 2.000000e+00
>  %239 = fmul float %228, 2.000000e+00
>  %240 = fmul float %229, 2.000000e+00
>  %241 = fmul float %237, 1.000000e+00
>  %242 = call float @llvm.AMDIL.clamp.(float %238, float 0.000000e+00, float 1.000000e+00)
>  %243 = call float @llvm.AMDIL.clamp.(float %239, float 0.000000e+00, float 1.000000e+00)
>  %244 = call float @llvm.AMDIL.clamp.(float %240, float 0.000000e+00, float 1.000000e+00)
>  %245 = call float @llvm.AMDIL.clamp.(float %241, float 0.000000e+00, float 1.000000e+00)
>  %246 = fmul float %54, %22
>  %247 = fadd float %246, %23
>  %248 = call float @llvm.AMDIL.clamp.(float %247, float 0.000000e+00, float 1.000000e+00)
>  %249 = fsub float -0.000000e+00, %248
>  %250 = fadd float 1.000000e+00, %249
>  %251 = fmul float %24, %250
>  %252 = fmul float %25, %250
>  %253 = fmul float %26, %250
>  %254 = fmul float %242, %248
>  %255 = fadd float %254, %251
>  %256 = fmul float %243, %248
>  %257 = fadd float %256, %252
>  %258 = fmul float %244, %248
>  %259 = fadd float %258, %253
>  %260 = call i32 @llvm.SI.packf16(float %255, float %257)
>  %261 = bitcast i32 %260 to float
>  %262 = call i32 @llvm.SI.packf16(float %259, float %245)
>  %263 = bitcast i32 %262 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %261, float %263, float %261, float %263)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0900
>c80d0901
>c8080b00
>c8090b01
>7e045502
>101e0503
>c80c0800
>c80d0801
>101c0503
>c80c0a00
>c80d0a01
>10200503
>7e2202f2
>d28a0003
>04421f0e
>d28c0002
>04421f0e
>d28e0004
>04421f0e
>d2880005
>04421f0e
>d206010a
>02010104
>7e14550a
>7e2602ff
>3fc00000
>d2820004
>044e1502
>d2820003
>044e1503
>c0840314
>c0c60528
>bf8c007f
>f0800f00
>00430203
>c8480100
>c8490101
>bf8c0770
>d2820006
>040e0b12
>d2060809
>02010106
>c8180d00
>c8190d01
>c81c0f00
>c81d0f01
>7e105507
>100e1106
>c8280c00
>c8290c01
>100c110a
>c0840310
>c0c60520
>bf8c007f
>f0800700
>00430606
>bf8c0770
>10141307
>d2820009
>042a1307
>d206080d
>02010109
>c8241100
>c8251101
>c8281300
>c8291301
>7e16550a
>10141709
>c8301000
>c8311001
>1012170c
>c084030c
>c0c60518
>bf8c007f
>f0800f00
>00430909
>bf8c0770
>1028190d
>081a18f2
>d2820014
>04521b0a
>c8581900
>c8591901
>c8541b00
>c8551b01
>7e2a5515
>101e2b16
>c8581800
>c8591801
>101c2b16
>c8581a00
>c8591a01
>10202b16
>d28a0016
>04421f0e
>d28c0015
>04421f0e
>d28e0017
>04421f0e
>d2880018
>04421f0e
>d206010e
>02010117
>7e1c550e
>d2820017
>044e1d15
>d2820016
>044e1d16
>c0840304
>c0c60508
>bf8c007f
>f0800700
>00430e16
>c8441500
>c8451501
>c84c1700
>c84d1701
>7e265513
>102c2711
>c8441400
>c8451401
>102a2711
>c0840308
>c0c60510
>bf8c0070
>f0800800
>00431115
>bf8c0770
>102a230f
>082622f2
>d2820014
>04562714
>102a2912
>d2820012
>04562912
>d2060812
>02010112
>c8501d00
>c8511d01
>c8541f00
>c8551f01
>7e2c5515
>102a2d14
>c85c1c00
>c85d1c01
>10282d17
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00431414
>bf8c0770
>102e2515
>d2820012
>045e2515
>d2060818
>02010112
>c8480400
>c8490401
>c0800100
>bf8c007f
>c2020118
>c2028119
>bf8c007f
>7e2e0205
>d2820012
>045c0912
>d2060812
>02010112
>082e24f2
>c202011d
>bf8c007f
>10322e04
>d2820018
>04662518
>c8640000
>c8650001
>d282001a
>040a0b19
>d206081a
>0201011a
>10363506
>d282001a
>046e3506
>d206081a
>0201011a
>1034191a
>d282001a
>046a1b09
>1036230e
>d282001a
>046e271a
>10363519
>d2820019
>046e3519
>d2060819
>02010119
>10343314
>d2820019
>046a3314
>d2060819
>02010119
>c202011c
>bf8c007f
>10342e04
>d2820019
>046a2519
>5e303119
>c8640200
>c8650201
>d2820000
>04120b19
>d2060800
>02010100
>10020108
>d2820000
>04060108
>d2060800
>02010100
>10001900
>d2820000
>04021b0b
>10022310
>d2820000
>04062700
>10020119
>d2820000
>04060119
>d2060800
>02010100
>10020116
>d2820000
>04060116
>d2060800
>02010100
>c200011e
>bf8c007f
>10022e00
>d2820000
>04062500
>d2060801
>02010111
>d2060801
>02010101
>5e000300
>f8001c0f
>00180018
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL IN[6]
>DCL IN[7]
>DCL IN[8]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL OUT[5], GENERIC[2]
>DCL OUT[6], GENERIC[3]
>DCL OUT[7], GENERIC[4]
>DCL OUT[8], GENERIC[6]
>DCL CONST[0..7]
>DCL CONST[9..31]
>DCL TEMP[0..5]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[2]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: DP3 TEMP[1].x, IN[1], CONST[9]
>  9: DP3 TEMP[1].y, IN[1], CONST[10]
> 10: DP3 TEMP[1].z, IN[1], CONST[11]
> 11: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 12: RSQ TEMP[2].x, |TEMP[2]|
> 13: MUL TEMP[1], TEMP[1], TEMP[2].xxxx
> 14: MUL TEMP[2], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[2], IN[0].yyyy, CONST[13], TEMP[2]
> 16: MAD TEMP[2], IN[0].zzzz, CONST[14], TEMP[2]
> 17: MAD TEMP[2], IN[0].wwww, CONST[15], TEMP[2]
> 18: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 19: RSQ TEMP[3].x, |TEMP[3]|
> 20: MUL TEMP[4], TEMP[2], TEMP[3].xxxx
> 21: DP3 TEMP[3], TEMP[1], TEMP[4]
> 22: ADD TEMP[3], TEMP[3], TEMP[3]
> 23: MAD OUT[3].xyz, -TEMP[3], TEMP[1], TEMP[4]
> 24: MOV OUT[3].w, IN[3]
> 25: MUL TEMP[3], IN[4].xxxx, CONST[16]
> 26: MAD TEMP[3], IN[4].yyyy, CONST[17], TEMP[3]
> 27: MAD TEMP[3], IN[4].zzzz, CONST[18], TEMP[3]
> 28: MAD OUT[4], IN[4].wwww, CONST[19], TEMP[3]
> 29: MOV OUT[5], IN[5]
> 30: MUL TEMP[3], IN[6].xxxx, CONST[20]
> 31: MAD TEMP[3], IN[6].yyyy, CONST[21], TEMP[3]
> 32: MAD TEMP[3], IN[6].zzzz, CONST[22], TEMP[3]
> 33: MAD OUT[6], IN[6].wwww, CONST[23], TEMP[3]
> 34: DP3 TEMP[5], TEMP[1], TEMP[4]
> 35: ADD TEMP[5], TEMP[5], TEMP[5]
> 36: MAD TEMP[3].xyz, -TEMP[5], TEMP[1], TEMP[4]
> 37: MOV TEMP[3].w, IN[7]
> 38: MUL TEMP[5], TEMP[3].xxxx, CONST[24]
> 39: MAD TEMP[5], TEMP[3].yyyy, CONST[25], TEMP[5]
> 40: MAD TEMP[5], TEMP[3].zzzz, CONST[26], TEMP[5]
> 41: MAD OUT[7], TEMP[3].wwww, CONST[27], TEMP[5]
> 42: MUL TEMP[3], IN[8].xxxx, CONST[28]
> 43: MAD TEMP[3], IN[8].yyyy, CONST[29], TEMP[3]
> 44: MAD TEMP[3], IN[8].zzzz, CONST[30], TEMP[3]
> 45: MAD OUT[8], IN[8].wwww, CONST[31], TEMP[3]
> 46: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 268)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 284)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 300)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 444)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 460)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 476)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 492)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %113 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %115 = call float @llvm.SI.load.const(<16 x i8> %10, i32 508)
>  %116 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %117 = load <16 x i8> addrspace(2)* %116, !tbaa !0
>  %118 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %117, i32 0, i32 %5)
>  %119 = extractelement <4 x float> %118, i32 0
>  %120 = extractelement <4 x float> %118, i32 1
>  %121 = extractelement <4 x float> %118, i32 2
>  %122 = extractelement <4 x float> %118, i32 3
>  %123 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %124 = load <16 x i8> addrspace(2)* %123, !tbaa !0
>  %125 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %124, i32 0, i32 %5)
>  %126 = extractelement <4 x float> %125, i32 0
>  %127 = extractelement <4 x float> %125, i32 1
>  %128 = extractelement <4 x float> %125, i32 2
>  %129 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %130 = load <16 x i8> addrspace(2)* %129, !tbaa !0
>  %131 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %130, i32 0, i32 %5)
>  %132 = extractelement <4 x float> %131, i32 0
>  %133 = extractelement <4 x float> %131, i32 1
>  %134 = extractelement <4 x float> %131, i32 2
>  %135 = extractelement <4 x float> %131, i32 3
>  %136 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %137 = load <16 x i8> addrspace(2)* %136, !tbaa !0
>  %138 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %137, i32 0, i32 %5)
>  %139 = extractelement <4 x float> %138, i32 3
>  %140 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %141 = load <16 x i8> addrspace(2)* %140, !tbaa !0
>  %142 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %141, i32 0, i32 %5)
>  %143 = extractelement <4 x float> %142, i32 0
>  %144 = extractelement <4 x float> %142, i32 1
>  %145 = extractelement <4 x float> %142, i32 2
>  %146 = extractelement <4 x float> %142, i32 3
>  %147 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %148 = load <16 x i8> addrspace(2)* %147, !tbaa !0
>  %149 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %148, i32 0, i32 %5)
>  %150 = extractelement <4 x float> %149, i32 0
>  %151 = extractelement <4 x float> %149, i32 1
>  %152 = extractelement <4 x float> %149, i32 2
>  %153 = extractelement <4 x float> %149, i32 3
>  %154 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
>  %155 = load <16 x i8> addrspace(2)* %154, !tbaa !0
>  %156 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %155, i32 0, i32 %5)
>  %157 = extractelement <4 x float> %156, i32 0
>  %158 = extractelement <4 x float> %156, i32 1
>  %159 = extractelement <4 x float> %156, i32 2
>  %160 = extractelement <4 x float> %156, i32 3
>  %161 = getelementptr <16 x i8> addrspace(2)* %3, i32 7
>  %162 = load <16 x i8> addrspace(2)* %161, !tbaa !0
>  %163 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %162, i32 0, i32 %5)
>  %164 = extractelement <4 x float> %163, i32 3
>  %165 = getelementptr <16 x i8> addrspace(2)* %3, i32 8
>  %166 = load <16 x i8> addrspace(2)* %165, !tbaa !0
>  %167 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %166, i32 0, i32 %5)
>  %168 = extractelement <4 x float> %167, i32 0
>  %169 = extractelement <4 x float> %167, i32 1
>  %170 = extractelement <4 x float> %167, i32 2
>  %171 = extractelement <4 x float> %167, i32 3
>  %172 = fmul float %119, %11
>  %173 = fmul float %119, %12
>  %174 = fmul float %119, %13
>  %175 = fmul float %119, %14
>  %176 = fmul float %120, %15
>  %177 = fadd float %176, %172
>  %178 = fmul float %120, %16
>  %179 = fadd float %178, %173
>  %180 = fmul float %120, %17
>  %181 = fadd float %180, %174
>  %182 = fmul float %120, %18
>  %183 = fadd float %182, %175
>  %184 = fmul float %121, %19
>  %185 = fadd float %184, %177
>  %186 = fmul float %121, %20
>  %187 = fadd float %186, %179
>  %188 = fmul float %121, %21
>  %189 = fadd float %188, %181
>  %190 = fmul float %121, %22
>  %191 = fadd float %190, %183
>  %192 = fmul float %122, %23
>  %193 = fadd float %192, %185
>  %194 = fmul float %122, %24
>  %195 = fadd float %194, %187
>  %196 = fmul float %122, %25
>  %197 = fadd float %196, %189
>  %198 = fmul float %122, %26
>  %199 = fadd float %198, %191
>  %200 = call float @llvm.AMDIL.clamp.(float %132, float 0.000000e+00, float 1.000000e+00)
>  %201 = call float @llvm.AMDIL.clamp.(float %133, float 0.000000e+00, float 1.000000e+00)
>  %202 = call float @llvm.AMDIL.clamp.(float %134, float 0.000000e+00, float 1.000000e+00)
>  %203 = call float @llvm.AMDIL.clamp.(float %135, float 0.000000e+00, float 1.000000e+00)
>  %204 = fmul float %119, %27
>  %205 = fmul float %120, %28
>  %206 = fadd float %204, %205
>  %207 = fmul float %121, %29
>  %208 = fadd float %206, %207
>  %209 = fmul float %122, %30
>  %210 = fadd float %208, %209
>  %211 = call float @fabs(float %210)
>  %212 = fmul float %126, %31
>  %213 = fmul float %127, %32
>  %214 = fadd float %213, %212
>  %215 = fmul float %128, %33
>  %216 = fadd float %214, %215
>  %217 = fmul float %126, %34
>  %218 = fmul float %127, %35
>  %219 = fadd float %218, %217
>  %220 = fmul float %128, %36
>  %221 = fadd float %219, %220
>  %222 = fmul float %126, %37
>  %223 = fmul float %127, %38
>  %224 = fadd float %223, %222
>  %225 = fmul float %128, %39
>  %226 = fadd float %224, %225
>  %227 = fmul float %216, %216
>  %228 = fmul float %221, %221
>  %229 = fadd float %228, %227
>  %230 = fmul float %226, %226
>  %231 = fadd float %229, %230
>  %232 = call float @fabs(float %231)
>  %233 = call float @llvm.AMDGPU.rsq(float %232)
>  %234 = fmul float %216, %233
>  %235 = fmul float %221, %233
>  %236 = fmul float %226, %233
>  %237 = fmul float %119, %40
>  %238 = fmul float %119, %41
>  %239 = fmul float %119, %42
>  %240 = fmul float %120, %43
>  %241 = fadd float %240, %237
>  %242 = fmul float %120, %44
>  %243 = fadd float %242, %238
>  %244 = fmul float %120, %45
>  %245 = fadd float %244, %239
>  %246 = fmul float %121, %46
>  %247 = fadd float %246, %241
>  %248 = fmul float %121, %47
>  %249 = fadd float %248, %243
>  %250 = fmul float %121, %48
>  %251 = fadd float %250, %245
>  %252 = fmul float %122, %49
>  %253 = fadd float %252, %247
>  %254 = fmul float %122, %50
>  %255 = fadd float %254, %249
>  %256 = fmul float %122, %51
>  %257 = fadd float %256, %251
>  %258 = fmul float %253, %253
>  %259 = fmul float %255, %255
>  %260 = fadd float %259, %258
>  %261 = fmul float %257, %257
>  %262 = fadd float %260, %261
>  %263 = call float @fabs(float %262)
>  %264 = call float @llvm.AMDGPU.rsq(float %263)
>  %265 = fmul float %253, %264
>  %266 = fmul float %255, %264
>  %267 = fmul float %257, %264
>  %268 = fmul float %234, %265
>  %269 = fmul float %235, %266
>  %270 = fadd float %269, %268
>  %271 = fmul float %236, %267
>  %272 = fadd float %270, %271
>  %273 = fadd float %272, %272
>  %274 = fadd float %272, %272
>  %275 = fadd float %272, %272
>  %276 = fsub float -0.000000e+00, %273
>  %277 = fmul float %276, %234
>  %278 = fadd float %277, %265
>  %279 = fsub float -0.000000e+00, %274
>  %280 = fmul float %279, %235
>  %281 = fadd float %280, %266
>  %282 = fsub float -0.000000e+00, %275
>  %283 = fmul float %282, %236
>  %284 = fadd float %283, %267
>  %285 = fmul float %143, %52
>  %286 = fmul float %143, %53
>  %287 = fmul float %143, %54
>  %288 = fmul float %143, %55
>  %289 = fmul float %144, %56
>  %290 = fadd float %289, %285
>  %291 = fmul float %144, %57
>  %292 = fadd float %291, %286
>  %293 = fmul float %144, %58
>  %294 = fadd float %293, %287
>  %295 = fmul float %144, %59
>  %296 = fadd float %295, %288
>  %297 = fmul float %145, %60
>  %298 = fadd float %297, %290
>  %299 = fmul float %145, %61
>  %300 = fadd float %299, %292
>  %301 = fmul float %145, %62
>  %302 = fadd float %301, %294
>  %303 = fmul float %145, %63
>  %304 = fadd float %303, %296
>  %305 = fmul float %146, %64
>  %306 = fadd float %305, %298
>  %307 = fmul float %146, %65
>  %308 = fadd float %307, %300
>  %309 = fmul float %146, %66
>  %310 = fadd float %309, %302
>  %311 = fmul float %146, %67
>  %312 = fadd float %311, %304
>  %313 = fmul float %157, %68
>  %314 = fmul float %157, %69
>  %315 = fmul float %157, %70
>  %316 = fmul float %157, %71
>  %317 = fmul float %158, %72
>  %318 = fadd float %317, %313
>  %319 = fmul float %158, %73
>  %320 = fadd float %319, %314
>  %321 = fmul float %158, %74
>  %322 = fadd float %321, %315
>  %323 = fmul float %158, %75
>  %324 = fadd float %323, %316
>  %325 = fmul float %159, %76
>  %326 = fadd float %325, %318
>  %327 = fmul float %159, %77
>  %328 = fadd float %327, %320
>  %329 = fmul float %159, %78
>  %330 = fadd float %329, %322
>  %331 = fmul float %159, %79
>  %332 = fadd float %331, %324
>  %333 = fmul float %160, %80
>  %334 = fadd float %333, %326
>  %335 = fmul float %160, %81
>  %336 = fadd float %335, %328
>  %337 = fmul float %160, %82
>  %338 = fadd float %337, %330
>  %339 = fmul float %160, %83
>  %340 = fadd float %339, %332
>  %341 = fmul float %234, %265
>  %342 = fmul float %235, %266
>  %343 = fadd float %342, %341
>  %344 = fmul float %236, %267
>  %345 = fadd float %343, %344
>  %346 = fadd float %345, %345
>  %347 = fadd float %345, %345
>  %348 = fadd float %345, %345
>  %349 = fsub float -0.000000e+00, %346
>  %350 = fmul float %349, %234
>  %351 = fadd float %350, %265
>  %352 = fsub float -0.000000e+00, %347
>  %353 = fmul float %352, %235
>  %354 = fadd float %353, %266
>  %355 = fsub float -0.000000e+00, %348
>  %356 = fmul float %355, %236
>  %357 = fadd float %356, %267
>  %358 = fmul float %351, %84
>  %359 = fmul float %351, %85
>  %360 = fmul float %351, %86
>  %361 = fmul float %351, %87
>  %362 = fmul float %354, %88
>  %363 = fadd float %362, %358
>  %364 = fmul float %354, %89
>  %365 = fadd float %364, %359
>  %366 = fmul float %354, %90
>  %367 = fadd float %366, %360
>  %368 = fmul float %354, %91
>  %369 = fadd float %368, %361
>  %370 = fmul float %357, %92
>  %371 = fadd float %370, %363
>  %372 = fmul float %357, %93
>  %373 = fadd float %372, %365
>  %374 = fmul float %357, %94
>  %375 = fadd float %374, %367
>  %376 = fmul float %357, %95
>  %377 = fadd float %376, %369
>  %378 = fmul float %164, %96
>  %379 = fadd float %378, %371
>  %380 = fmul float %164, %97
>  %381 = fadd float %380, %373
>  %382 = fmul float %164, %98
>  %383 = fadd float %382, %375
>  %384 = fmul float %164, %99
>  %385 = fadd float %384, %377
>  %386 = fmul float %168, %100
>  %387 = fmul float %168, %101
>  %388 = fmul float %168, %102
>  %389 = fmul float %168, %103
>  %390 = fmul float %169, %104
>  %391 = fadd float %390, %386
>  %392 = fmul float %169, %105
>  %393 = fadd float %392, %387
>  %394 = fmul float %169, %106
>  %395 = fadd float %394, %388
>  %396 = fmul float %169, %107
>  %397 = fadd float %396, %389
>  %398 = fmul float %170, %108
>  %399 = fadd float %398, %391
>  %400 = fmul float %170, %109
>  %401 = fadd float %400, %393
>  %402 = fmul float %170, %110
>  %403 = fadd float %402, %395
>  %404 = fmul float %170, %111
>  %405 = fadd float %404, %397
>  %406 = fmul float %171, %112
>  %407 = fadd float %406, %399
>  %408 = fmul float %171, %113
>  %409 = fadd float %408, %401
>  %410 = fmul float %171, %114
>  %411 = fadd float %410, %403
>  %412 = fmul float %171, %115
>  %413 = fadd float %412, %405
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %200, float %201, float %202, float %203)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %211, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %278, float %281, float %284, float %139)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %306, float %308, float %310, float %312)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %150, float %151, float %152, float %153)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %334, float %336, float %338, float %340)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %379, float %381, float %383, float %385)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %407, float %409, float %411, float %413)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %193, float %195, float %197, float %199)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0840704
>bf8c000f
>e00c2000
>80020600
>c2020128
>bf8c0070
>100a0c04
>c2020129
>bf8c007f
>d2820005
>04140907
>c202012a
>bf8c007f
>d2820005
>04140908
>c2020124
>bf8c007f
>10140c04
>c2020125
>bf8c007f
>d282000a
>04280907
>c2020126
>bf8c007f
>d282000a
>04280908
>1016150a
>d282000b
>042e0b05
>c202012c
>bf8c007f
>10180c04
>c202012d
>bf8c007f
>d282000c
>04300907
>c202012e
>bf8c007f
>d2820006
>04300908
>d2820007
>042e0d06
>d2060107
>02010107
>7e105b07
>100e110a
>c2020131
>bf8c007f
>10120204
>c2020135
>bf8c007f
>d2820009
>04240902
>c2020139
>bf8c007f
>d2820009
>04240903
>c202013d
>bf8c007f
>d2820009
>04240904
>c2020130
>bf8c007f
>10140204
>c2020134
>bf8c007f
>d282000a
>04280902
>c2020138
>bf8c007f
>d282000a
>04280903
>c202013c
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c2020132
>bf8c007f
>10160204
>c2020136
>bf8c007f
>d282000b
>042c0902
>c202013a
>bf8c007f
>d282000b
>042c0903
>c202013e
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e1a5b0c
>10141b0a
>101c1507
>10181105
>10121b09
>d282000e
>043a130c
>100a1106
>100c1b0b
>d2820008
>043a0d05
>06101108
>100a0b08
>080a0b06
>100c1908
>080c0d09
>100e0f08
>080e0f0a
>c084070c
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800022f
>0b050607
>c0840710
>bf8c000f
>e00c2000
>80020800
>c2020143
>bf8c0070
>10181004
>c2020147
>bf8c007f
>d282000c
>04300909
>c202014b
>bf8c007f
>d282000c
>0430090a
>c202014f
>bf8c007f
>d282000c
>0430090b
>c2020142
>bf8c007f
>101a1004
>c2020146
>bf8c007f
>d282000d
>04340909
>c202014a
>bf8c007f
>d282000d
>0434090a
>c202014e
>bf8c007f
>d282000d
>0434090b
>c2020141
>bf8c007f
>101c1004
>c2020145
>bf8c007f
>d282000e
>04380909
>c2020149
>bf8c007f
>d282000e
>0438090a
>c202014d
>bf8c007f
>d282000e
>0438090b
>c2020140
>bf8c007f
>101e1004
>c2020144
>bf8c007f
>d282000f
>043c0909
>c2020148
>bf8c007f
>d282000f
>043c090a
>c202014c
>bf8c007f
>d2820008
>043c090b
>f800023f
>0c0d0e08
>c0840714
>bf8c000f
>e00c2000
>80020800
>bf8c0770
>f800024f
>0b0a0908
>c0840718
>bf8c000f
>e00c2000
>80020800
>c2020153
>bf8c0070
>10181004
>c2020157
>bf8c007f
>d282000c
>04300909
>c202015b
>bf8c007f
>d282000c
>0430090a
>c202015f
>bf8c007f
>d282000c
>0430090b
>c2020152
>bf8c007f
>101a1004
>c2020156
>bf8c007f
>d282000d
>04340909
>c202015a
>bf8c007f
>d282000d
>0434090a
>c202015e
>bf8c007f
>d282000d
>0434090b
>c2020151
>bf8c007f
>101c1004
>c2020155
>bf8c007f
>d282000e
>04380909
>c2020159
>bf8c007f
>d282000e
>0438090a
>c202015d
>bf8c007f
>d282000e
>0438090b
>c2020150
>bf8c007f
>101e1004
>c2020154
>bf8c007f
>d282000f
>043c0909
>c2020158
>bf8c007f
>d282000f
>043c090a
>c202015c
>bf8c007f
>d2820008
>043c090b
>f800025f
>0c0d0e08
>c2020163
>bf8c000f
>10100e04
>c2020167
>bf8c007f
>d2820008
>04200906
>c202016b
>bf8c007f
>d282000c
>04200905
>c084071c
>bf8c007f
>e00c2000
>80020800
>c202016f
>bf8c0070
>d282000c
>0430090b
>c2020162
>bf8c007f
>101a0e04
>c2020166
>bf8c007f
>d282000d
>04340906
>c202016a
>bf8c007f
>d282000d
>04340905
>c202016e
>bf8c007f
>d282000d
>0434090b
>c2020161
>bf8c007f
>101c0e04
>c2020165
>bf8c007f
>d282000e
>04380906
>c2020169
>bf8c007f
>d282000e
>04380905
>c202016d
>bf8c007f
>d282000e
>0438090b
>c2020160
>bf8c007f
>100e0e04
>c2020164
>bf8c007f
>d2820006
>041c0906
>c2020168
>bf8c007f
>d2820005
>04180905
>c202016c
>bf8c007f
>d2820005
>0414090b
>f800026f
>0c0d0e05
>c0820720
>bf8c000f
>e00c2000
>80010500
>c2020173
>bf8c0070
>10000a04
>c2020177
>bf8c007f
>d2820000
>04000906
>c202017b
>bf8c007f
>d2820000
>04000907
>c202017f
>bf8c007f
>d2820000
>04000908
>c2020172
>bf8c007f
>10120a04
>c2020176
>bf8c007f
>d2820009
>04240906
>c202017a
>bf8c007f
>d2820009
>04240907
>c202017e
>bf8c007f
>d2820009
>04240908
>c2020171
>bf8c007f
>10140a04
>c2020175
>bf8c007f
>d282000a
>04280906
>c2020179
>bf8c007f
>d282000a
>04280907
>c202017d
>bf8c007f
>d282000a
>04280908
>c2020170
>bf8c007f
>10160a04
>c2020174
>bf8c007f
>d282000b
>042c0906
>c2020178
>bf8c007f
>d282000b
>042c0907
>c202017c
>bf8c007f
>d2820005
>042c0908
>f800027f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = fmul float %34, %11
>  %53 = fmul float %34, %12
>  %54 = fmul float %34, %13
>  %55 = fmul float %34, %14
>  %56 = fmul float %35, %15
>  %57 = fadd float %56, %52
>  %58 = fmul float %35, %16
>  %59 = fadd float %58, %53
>  %60 = fmul float %35, %17
>  %61 = fadd float %60, %54
>  %62 = fmul float %35, %18
>  %63 = fadd float %62, %55
>  %64 = fmul float %36, %19
>  %65 = fadd float %64, %57
>  %66 = fmul float %36, %20
>  %67 = fadd float %66, %59
>  %68 = fmul float %36, %21
>  %69 = fadd float %68, %61
>  %70 = fmul float %36, %22
>  %71 = fadd float %70, %63
>  %72 = fmul float %37, %23
>  %73 = fadd float %72, %65
>  %74 = fmul float %37, %24
>  %75 = fadd float %74, %67
>  %76 = fmul float %37, %25
>  %77 = fadd float %76, %69
>  %78 = fmul float %37, %26
>  %79 = fadd float %78, %71
>  %80 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %81 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %82 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %83 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %84 = fmul float %34, %27
>  %85 = fmul float %35, %28
>  %86 = fadd float %84, %85
>  %87 = fmul float %36, %29
>  %88 = fadd float %86, %87
>  %89 = fmul float %37, %30
>  %90 = fadd float %88, %89
>  %91 = call float @fabs(float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %80, float %81, float %82, float %83)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %91, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %73, float %75, float %77, float %79)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..3]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  5: MOV TEMP[1].w, TEMP[0]
>  6: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  7: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
>  8: MUL TEMP[3].xyz, CONST[2].xyzz, TEMP[3].xxxx
>  9: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 10: MOV OUT[0], TEMP[1]
> 11: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %39 = fdiv float %36, %38
>  %40 = fdiv float %37, %38
>  %41 = bitcast float %39 to i32
>  %42 = bitcast float %40 to i32
>  %43 = insertelement <2 x i32> undef, i32 %41, i32 0
>  %44 = insertelement <2 x i32> %43, i32 %42, i32 1
>  %45 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %44, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = fmul float %46, %31
>  %51 = fmul float %47, %32
>  %52 = fmul float %48, %33
>  %53 = fmul float %49, %34
>  %54 = fmul float %50, 2.000000e+00
>  %55 = fmul float %51, 2.000000e+00
>  %56 = fmul float %52, 2.000000e+00
>  %57 = fmul float %53, 1.000000e+00
>  %58 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %59 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %60 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
>  %61 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %62 = fmul float %35, %22
>  %63 = fadd float %62, %23
>  %64 = call float @llvm.AMDIL.clamp.(float %63, float 0.000000e+00, float 1.000000e+00)
>  %65 = fsub float -0.000000e+00, %64
>  %66 = fadd float 1.000000e+00, %65
>  %67 = fmul float %24, %66
>  %68 = fmul float %25, %66
>  %69 = fmul float %26, %66
>  %70 = fmul float %58, %64
>  %71 = fadd float %70, %67
>  %72 = fmul float %59, %64
>  %73 = fadd float %72, %68
>  %74 = fmul float %60, %64
>  %75 = fadd float %74, %69
>  %76 = fcmp ugt float %61, 0x3FDFDFDFE0000000
>  %77 = sext i1 %76 to i32
>  %78 = trunc i32 %77 to i1
>  %79 = select i1 %78, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %79)
>  %80 = call i32 @llvm.SI.packf16(float %71, float %73)
>  %81 = bitcast i32 %80 to float
>  %82 = call i32 @llvm.SI.packf16(float %75, float %61)
>  %83 = bitcast i32 %82 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %81, float %83, float %81, float %83)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>d2060806
>02010106
>7e0e02ff
>3efefeff
>d0080002
>02020f06
>d2000007
>0009e4f3
>7c260e80
>c81c0100
>c81d0101
>10100f03
>d2820007
>04220f03
>d2060809
>02010107
>c81c0400
>c81d0401
>c0800100
>bf8c007f
>c2020104
>c2028105
>bf8c007f
>7e100205
>d2820007
>04200907
>d2060807
>02010107
>08100ef2
>c2020109
>bf8c007f
>10141004
>d2820009
>042a0f09
>c8280000
>c8290001
>10161502
>d282000a
>042e1502
>d206080a
>0201010a
>c2020108
>bf8c007f
>10161004
>d282000a
>042e0f0a
>5e12130a
>c8280200
>c8290201
>10001504
>d2820000
>04021504
>d2060800
>02010100
>c200010a
>bf8c007f
>10021000
>d2820000
>04060f00
>5e000d00
>f8001c0f
>00090009
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL IN[4], GENERIC[2], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL CONST[3..5]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[2], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  5: MOV TEMP[0].xyz, TEMP[0].xyzx
>  6: MOV TEMP[1].xy, IN[3].xyyy
>  7: MOV TEMP[1].w, IN[3].wwww
>  8: TXP TEMP[1].w, TEMP[1], SAMP[1], 2D
>  9: MOV TEMP[0].w, TEMP[1].wwww
> 10: ADD TEMP[2].x, IMM[0].yyyy, -TEMP[1].wwww
> 11: MOV TEMP[3].xy, IN[4].xyyy
> 12: MOV TEMP[3].w, IN[4].wwww
> 13: TXP TEMP[3], TEMP[3], SAMP[0], 2D
> 14: MUL TEMP[3], TEMP[3], TEMP[1].wwww
> 15: MAD TEMP[0].xyz, TEMP[0], TEMP[2].xxxx, TEMP[3]
> 16: MOV TEMP[1].w, TEMP[1].wwww
> 17: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[3].xxxx, CONST[3].yyyy
> 18: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
> 19: MUL TEMP[3].xyz, CONST[4].xyzz, TEMP[3].xxxx
> 20: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 21: MOV OUT[0], TEMP[1]
> 22: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %36 = load <32 x i8> addrspace(2)* %35, !tbaa !0
>  %37 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %46 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %47 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %48 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %49 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %50 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %51 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %52 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %53 = fdiv float %44, %46
>  %54 = fdiv float %45, %46
>  %55 = bitcast float %53 to i32
>  %56 = bitcast float %54 to i32
>  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
>  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
>  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = extractelement <4 x float> %59, i32 3
>  %64 = fmul float %60, %39
>  %65 = fmul float %61, %40
>  %66 = fmul float %62, %41
>  %67 = fmul float %63, %42
>  %68 = fmul float %64, 2.000000e+00
>  %69 = fmul float %65, 2.000000e+00
>  %70 = fmul float %66, 2.000000e+00
>  %71 = fmul float %67, 1.000000e+00
>  %72 = call float @llvm.AMDIL.clamp.(float %68, float 0.000000e+00, float 1.000000e+00)
>  %73 = call float @llvm.AMDIL.clamp.(float %69, float 0.000000e+00, float 1.000000e+00)
>  %74 = call float @llvm.AMDIL.clamp.(float %70, float 0.000000e+00, float 1.000000e+00)
>  %75 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %76 = fdiv float %47, %49
>  %77 = fdiv float %48, %49
>  %78 = bitcast float %76 to i32
>  %79 = bitcast float %77 to i32
>  %80 = insertelement <2 x i32> undef, i32 %78, i32 0
>  %81 = insertelement <2 x i32> %80, i32 %79, i32 1
>  %82 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %81, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %83 = extractelement <4 x float> %82, i32 3
>  %84 = fsub float -0.000000e+00, %83
>  %85 = fadd float 1.000000e+00, %84
>  %86 = fdiv float %50, %52
>  %87 = fdiv float %51, %52
>  %88 = bitcast float %86 to i32
>  %89 = bitcast float %87 to i32
>  %90 = insertelement <2 x i32> undef, i32 %88, i32 0
>  %91 = insertelement <2 x i32> %90, i32 %89, i32 1
>  %92 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %91, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = fmul float %93, %83
>  %97 = fmul float %94, %83
>  %98 = fmul float %95, %83
>  %99 = fmul float %72, %85
>  %100 = fadd float %99, %96
>  %101 = fmul float %73, %85
>  %102 = fadd float %101, %97
>  %103 = fmul float %74, %85
>  %104 = fadd float %103, %98
>  %105 = fmul float %43, %22
>  %106 = fadd float %105, %23
>  %107 = call float @llvm.AMDIL.clamp.(float %106, float 0.000000e+00, float 1.000000e+00)
>  %108 = fsub float -0.000000e+00, %107
>  %109 = fadd float 1.000000e+00, %108
>  %110 = fmul float %24, %109
>  %111 = fmul float %25, %109
>  %112 = fmul float %26, %109
>  %113 = fmul float %100, %107
>  %114 = fadd float %113, %110
>  %115 = fmul float %102, %107
>  %116 = fadd float %115, %111
>  %117 = fmul float %104, %107
>  %118 = fadd float %117, %112
>  %119 = call i32 @llvm.SI.packf16(float %114, float %116)
>  %120 = bitcast i32 %119 to float
>  %121 = call i32 @llvm.SI.packf16(float %118, float %83)
>  %122 = bitcast i32 %121 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %120, float %122, float %120, float %122)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080d00
>c8090d01
>c80c0f00
>c80d0f01
>7e085503
>10060902
>c8140c00
>c8150c01
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800800
>00430202
>c80c1100
>c80d1101
>c8101300
>c8111301
>7e0a5504
>10080b03
>c8181000
>c8191001
>10060b06
>c0840300
>c0c60500
>bf8c0070
>f0800700
>00430303
>bf8c0770
>10140504
>c8180900
>c8190901
>c81c0b00
>c81d0b01
>7e105507
>100e1106
>c8240800
>c8250801
>100c1109
>c0840308
>c0c60510
>bf8c007f
>f0800700
>00430606
>c8240100
>c8250101
>bf8c0770
>10161307
>d2820009
>042e1307
>d206080b
>02010109
>081204f2
>d282000c
>042a130b
>c8280400
>c8290401
>c0800100
>bf8c007f
>c202010c
>c202810d
>bf8c007f
>7e160205
>d282000a
>042c090a
>d206080a
>0201010a
>081614f2
>c2020111
>bf8c007f
>101a1604
>d282000c
>0436150c
>101a0503
>c8380000
>c8390001
>101e1d06
>d282000e
>043e1d06
>d206080e
>0201010e
>d282000d
>0436130e
>c2020110
>bf8c007f
>101c1604
>d282000d
>043a150d
>5e18190d
>10060505
>c8100200
>c8110201
>10000908
>d2820000
>04020908
>d2060800
>02010100
>d2820000
>040e1300
>c2000112
>bf8c007f
>10021600
>d2820000
>04061500
>5e000500
>f8001c0f
>000c000c
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL OUT[5], GENERIC[2]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: MOV OUT[4], IN[3]
> 10: MOV OUT[5], IN[4]
> 11: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %53 = load <16 x i8> addrspace(2)* %52, !tbaa !0
>  %54 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %53, i32 0, i32 %5)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %58 = extractelement <4 x float> %54, i32 3
>  %59 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
>  %61 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %60, i32 0, i32 %5)
>  %62 = extractelement <4 x float> %61, i32 0
>  %63 = extractelement <4 x float> %61, i32 1
>  %64 = extractelement <4 x float> %61, i32 2
>  %65 = extractelement <4 x float> %61, i32 3
>  %66 = fmul float %34, %11
>  %67 = fmul float %34, %12
>  %68 = fmul float %34, %13
>  %69 = fmul float %34, %14
>  %70 = fmul float %35, %15
>  %71 = fadd float %70, %66
>  %72 = fmul float %35, %16
>  %73 = fadd float %72, %67
>  %74 = fmul float %35, %17
>  %75 = fadd float %74, %68
>  %76 = fmul float %35, %18
>  %77 = fadd float %76, %69
>  %78 = fmul float %36, %19
>  %79 = fadd float %78, %71
>  %80 = fmul float %36, %20
>  %81 = fadd float %80, %73
>  %82 = fmul float %36, %21
>  %83 = fadd float %82, %75
>  %84 = fmul float %36, %22
>  %85 = fadd float %84, %77
>  %86 = fmul float %37, %23
>  %87 = fadd float %86, %79
>  %88 = fmul float %37, %24
>  %89 = fadd float %88, %81
>  %90 = fmul float %37, %25
>  %91 = fadd float %90, %83
>  %92 = fmul float %37, %26
>  %93 = fadd float %92, %85
>  %94 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %96 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %97 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %98 = fmul float %34, %27
>  %99 = fmul float %35, %28
>  %100 = fadd float %98, %99
>  %101 = fmul float %36, %29
>  %102 = fadd float %100, %101
>  %103 = fmul float %37, %30
>  %104 = fadd float %102, %103
>  %105 = call float @fabs(float %104)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %94, float %95, float %96, float %97)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %105, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %55, float %56, float %57, float %58)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %62, float %63, float %64, float %65)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %87, float %89, float %91, float %93)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0840708
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800022f
>08070605
>c084070c
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800023f
>08070605
>c0820710
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800024f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], FOG, PERSPECTIVE
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..3]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MOV TEMP[1].w, TEMP[0].wwww
>  4: MAD_SAT TEMP[2].x, IN[0].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  5: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].xxxx
>  6: MUL TEMP[3].xyz, CONST[2].xyzz, TEMP[3].xxxx
>  7: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
>  8: MOV OUT[0], TEMP[1]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %35 = fdiv float %32, %34
>  %36 = fdiv float %33, %34
>  %37 = bitcast float %35 to i32
>  %38 = bitcast float %36 to i32
>  %39 = insertelement <2 x i32> undef, i32 %37, i32 0
>  %40 = insertelement <2 x i32> %39, i32 %38, i32 1
>  %41 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %42 = extractelement <4 x float> %41, i32 0
>  %43 = extractelement <4 x float> %41, i32 1
>  %44 = extractelement <4 x float> %41, i32 2
>  %45 = extractelement <4 x float> %41, i32 3
>  %46 = fmul float %31, %22
>  %47 = fadd float %46, %23
>  %48 = call float @llvm.AMDIL.clamp.(float %47, float 0.000000e+00, float 1.000000e+00)
>  %49 = fsub float -0.000000e+00, %48
>  %50 = fadd float 1.000000e+00, %49
>  %51 = fmul float %24, %50
>  %52 = fmul float %25, %50
>  %53 = fmul float %26, %50
>  %54 = fmul float %42, %48
>  %55 = fadd float %54, %51
>  %56 = fmul float %43, %48
>  %57 = fadd float %56, %52
>  %58 = fmul float %44, %48
>  %59 = fadd float %58, %53
>  %60 = call i32 @llvm.SI.packf16(float %55, float %57)
>  %61 = bitcast i32 %60 to float
>  %62 = call i32 @llvm.SI.packf16(float %59, float %45)
>  %63 = bitcast i32 %62 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %61, float %63, float %61, float %63)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c8180000
>c8190001
>c0800100
>bf8c0070
>c2020104
>c2028105
>bf8c007f
>7e000205
>d2820000
>04000906
>d2060800
>02010100
>080200f2
>c202010a
>bf8c007f
>100c0204
>d2820006
>041a0104
>5e0c0b06
>c2020109
>bf8c007f
>100e0204
>d2820007
>041e0103
>c2000108
>bf8c007f
>10020200
>d2820000
>04060102
>5e000f00
>f8001c0f
>06000600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], FOG
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP4 TEMP[0], IN[0], CONST[6]
>  5: ABS OUT[1].x, TEMP[0]
>  6: MOV OUT[1].yzw, IMM[0].xxxy
>  7: MOV OUT[2], IN[1]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = fmul float %34, %11
>  %46 = fmul float %34, %12
>  %47 = fmul float %34, %13
>  %48 = fmul float %34, %14
>  %49 = fmul float %35, %15
>  %50 = fadd float %49, %45
>  %51 = fmul float %35, %16
>  %52 = fadd float %51, %46
>  %53 = fmul float %35, %17
>  %54 = fadd float %53, %47
>  %55 = fmul float %35, %18
>  %56 = fadd float %55, %48
>  %57 = fmul float %36, %19
>  %58 = fadd float %57, %50
>  %59 = fmul float %36, %20
>  %60 = fadd float %59, %52
>  %61 = fmul float %36, %21
>  %62 = fadd float %61, %54
>  %63 = fmul float %36, %22
>  %64 = fadd float %63, %56
>  %65 = fmul float %37, %23
>  %66 = fadd float %65, %58
>  %67 = fmul float %37, %24
>  %68 = fadd float %67, %60
>  %69 = fmul float %37, %25
>  %70 = fadd float %69, %62
>  %71 = fmul float %37, %26
>  %72 = fadd float %71, %64
>  %73 = fmul float %34, %27
>  %74 = fmul float %35, %28
>  %75 = fadd float %73, %74
>  %76 = fmul float %36, %29
>  %77 = fadd float %75, %76
>  %78 = fmul float %37, %30
>  %79 = fadd float %77, %78
>  %80 = call float @fabs(float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %80, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %41, float %42, float %43, float %44)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %66, float %68, float %70, float %72)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800020f
>06070705
>c0820704
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL IN[4], GENERIC[2], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL CONST[3..5]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     2.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[2], 2D
>  3: TXP TEMP[1], IN[3], SAMP[1], CUBE
>  4: MOV TEMP[2].xy, IN[4].xyyy
>  5: MOV TEMP[2].w, IN[4].wwww
>  6: TXP TEMP[2], TEMP[2], SAMP[0], 2D
>  7: MAD TEMP[1].xyz, TEMP[0], TEMP[1].wwww, TEMP[1]
>  8: MOV_SAT TEMP[1].xyz, TEMP[1].xyzz
>  9: MOV TEMP[1].w, TEMP[0].wwww
> 10: ADD TEMP[0].x, IMM[0].xxxx, -TEMP[2].wwww
> 11: MUL TEMP[1], TEMP[1], TEMP[2].wwww
> 12: MAD TEMP[0].xyz, TEMP[2], TEMP[0].xxxx, TEMP[1]
> 13: MOV TEMP[0].xyz, TEMP[0].xyzx
> 14: MOV TEMP[0].w, TEMP[2].wwww
> 15: MUL TEMP[0].xyz, IN[0], TEMP[0]
> 16: MOV TEMP[0].xyz, TEMP[0].xyzx
> 17: MOV TEMP[0].w, TEMP[2].wwww
> 18: MUL_SAT TEMP[0], TEMP[0], IMM[0].yyyx
> 19: MOV TEMP[1].w, TEMP[0]
> 20: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[3].xxxx, CONST[3].yyyy
> 21: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].xxxx
> 22: MUL TEMP[3].xyz, CONST[4].xyzz, TEMP[3].xxxx
> 23: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 24: MOV OUT[0], TEMP[1]
> 25: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %36 = load <32 x i8> addrspace(2)* %35, !tbaa !0
>  %37 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %46 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %47 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %48 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
>  %49 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %50 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %51 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %52 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %53 = fdiv float %43, %45
>  %54 = fdiv float %44, %45
>  %55 = bitcast float %53 to i32
>  %56 = bitcast float %54 to i32
>  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
>  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
>  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = fdiv float %46, %49
>  %64 = fdiv float %47, %49
>  %65 = fdiv float %48, %49
>  %66 = insertelement <4 x float> undef, float %63, i32 0
>  %67 = insertelement <4 x float> %66, float %64, i32 1
>  %68 = insertelement <4 x float> %67, float %65, i32 2
>  %69 = insertelement <4 x float> %68, float 1.000000e+00, i32 3
>  %70 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %69)
>  %71 = extractelement <4 x float> %70, i32 0
>  %72 = extractelement <4 x float> %70, i32 1
>  %73 = extractelement <4 x float> %70, i32 2
>  %74 = extractelement <4 x float> %70, i32 3
>  %75 = call float @fabs(float %73)
>  %76 = fdiv float 1.000000e+00, %75
>  %77 = fmul float %71, %76
>  %78 = fadd float %77, 1.500000e+00
>  %79 = fmul float %72, %76
>  %80 = fadd float %79, 1.500000e+00
>  %81 = bitcast float %80 to i32
>  %82 = bitcast float %78 to i32
>  %83 = bitcast float %74 to i32
>  %84 = insertelement <4 x i32> undef, i32 %81, i32 0
>  %85 = insertelement <4 x i32> %84, i32 %82, i32 1
>  %86 = insertelement <4 x i32> %85, i32 %83, i32 2
>  %87 = insertelement <4 x i32> %86, i32 undef, i32 3
>  %88 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %87, <32 x i8> %32, <16 x i8> %34, i32 4)
>  %89 = extractelement <4 x float> %88, i32 0
>  %90 = extractelement <4 x float> %88, i32 1
>  %91 = extractelement <4 x float> %88, i32 2
>  %92 = extractelement <4 x float> %88, i32 3
>  %93 = fdiv float %50, %52
>  %94 = fdiv float %51, %52
>  %95 = bitcast float %93 to i32
>  %96 = bitcast float %94 to i32
>  %97 = insertelement <2 x i32> undef, i32 %95, i32 0
>  %98 = insertelement <2 x i32> %97, i32 %96, i32 1
>  %99 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %98, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %100 = extractelement <4 x float> %99, i32 0
>  %101 = extractelement <4 x float> %99, i32 1
>  %102 = extractelement <4 x float> %99, i32 2
>  %103 = extractelement <4 x float> %99, i32 3
>  %104 = fmul float %60, %92
>  %105 = fadd float %104, %89
>  %106 = fmul float %61, %92
>  %107 = fadd float %106, %90
>  %108 = fmul float %62, %92
>  %109 = fadd float %108, %91
>  %110 = call float @llvm.AMDIL.clamp.(float %105, float 0.000000e+00, float 1.000000e+00)
>  %111 = call float @llvm.AMDIL.clamp.(float %107, float 0.000000e+00, float 1.000000e+00)
>  %112 = call float @llvm.AMDIL.clamp.(float %109, float 0.000000e+00, float 1.000000e+00)
>  %113 = fsub float -0.000000e+00, %103
>  %114 = fadd float 1.000000e+00, %113
>  %115 = fmul float %110, %103
>  %116 = fmul float %111, %103
>  %117 = fmul float %112, %103
>  %118 = fmul float %100, %114
>  %119 = fadd float %118, %115
>  %120 = fmul float %101, %114
>  %121 = fadd float %120, %116
>  %122 = fmul float %102, %114
>  %123 = fadd float %122, %117
>  %124 = fmul float %39, %119
>  %125 = fmul float %40, %121
>  %126 = fmul float %41, %123
>  %127 = fmul float %124, 2.000000e+00
>  %128 = fmul float %125, 2.000000e+00
>  %129 = fmul float %126, 2.000000e+00
>  %130 = fmul float %103, 1.000000e+00
>  %131 = call float @llvm.AMDIL.clamp.(float %127, float 0.000000e+00, float 1.000000e+00)
>  %132 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
>  %133 = call float @llvm.AMDIL.clamp.(float %129, float 0.000000e+00, float 1.000000e+00)
>  %134 = call float @llvm.AMDIL.clamp.(float %130, float 0.000000e+00, float 1.000000e+00)
>  %135 = fmul float %42, %22
>  %136 = fadd float %135, %23
>  %137 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
>  %138 = fsub float -0.000000e+00, %137
>  %139 = fadd float 1.000000e+00, %138
>  %140 = fmul float %24, %139
>  %141 = fmul float %25, %139
>  %142 = fmul float %26, %139
>  %143 = fmul float %131, %137
>  %144 = fadd float %143, %140
>  %145 = fmul float %132, %137
>  %146 = fadd float %145, %141
>  %147 = fmul float %133, %137
>  %148 = fadd float %147, %142
>  %149 = call i32 @llvm.SI.packf16(float %144, float %146)
>  %150 = bitcast i32 %149 to float
>  %151 = call i32 @llvm.SI.packf16(float %148, float %134)
>  %152 = bitcast i32 %151 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %150, float %152, float %150, float %152)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080d00
>c8090d01
>c80c0f00
>c80d0f01
>7e0c5503
>10060d02
>c81c0c00
>c81d0c01
>10040d07
>c81c0e00
>c81d0e01
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430207
>c8180900
>c8190901
>c81c0b00
>c81d0b01
>7e105507
>100e1106
>c8240800
>c8250801
>100c1109
>c0840308
>c0c60510
>bf8c0070
>f0800700
>00430606
>bf8c0770
>d2820009
>040e0b07
>d206080d
>02010109
>c8241100
>c8251101
>c8281300
>c8291301
>7e16550a
>10141709
>c8301000
>c8311001
>1012170c
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430909
>bf8c0770
>101c190d
>081a18f2
>d282000e
>043a1b0a
>c83c0100
>c83d0101
>10201d0f
>d282000e
>04421d0f
>d2060810
>0201010e
>c8380400
>c8390401
>c0800100
>bf8c007f
>c202010c
>c202810d
>bf8c007f
>7e1e0205
>d282000e
>043c090e
>d206080e
>0201010e
>081e1cf2
>c2020111
>bf8c007f
>10221e04
>d2820010
>04461d10
>d2820011
>040a0b06
>d2060811
>02010111
>10221911
>d2820011
>04461b09
>c8480000
>c8490001
>10262312
>d2820011
>044e2312
>d2060811
>02010111
>c2020110
>bf8c007f
>10241e04
>d2820011
>044a1d11
>5e202111
>d2820002
>04120b08
>d2060802
>02010102
>10041902
>d2820002
>040a1b0b
>c80c0200
>c80d0201
>10000503
>d2820000
>04020503
>d2060800
>02010100
>c2000112
>bf8c007f
>10021e00
>d2820000
>04061d00
>d2060801
>0201010c
>5e000300
>f8001c0f
>00100010
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL OUT[5], GENERIC[2]
>DCL CONST[0..7]
>DCL CONST[9..15]
>DCL TEMP[0..4]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[2]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[3]
>  9: DP3 TEMP[1].x, IN[1], CONST[9]
> 10: DP3 TEMP[1].y, IN[1], CONST[10]
> 11: DP3 TEMP[1].z, IN[1], CONST[11]
> 12: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 13: RSQ TEMP[2].x, |TEMP[2]|
> 14: MUL TEMP[1], TEMP[1], TEMP[2].xxxx
> 15: MUL TEMP[2], IN[0].xxxx, CONST[12]
> 16: MAD TEMP[2], IN[0].yyyy, CONST[13], TEMP[2]
> 17: MAD TEMP[2], IN[0].zzzz, CONST[14], TEMP[2]
> 18: MAD TEMP[2], IN[0].wwww, CONST[15], TEMP[2]
> 19: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 20: RSQ TEMP[3].x, |TEMP[3]|
> 21: MUL TEMP[4], TEMP[2], TEMP[3].xxxx
> 22: DP3 TEMP[3], TEMP[1], TEMP[4]
> 23: ADD TEMP[3], TEMP[3], TEMP[3]
> 24: MAD OUT[4].xyz, -TEMP[3], TEMP[1], TEMP[4]
> 25: MOV OUT[4].w, IN[4]
> 26: MOV OUT[5], IN[5]
> 27: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %52 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %53 = load <16 x i8> addrspace(2)* %52, !tbaa !0
>  %54 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %53, i32 0, i32 %5)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %58 = extractelement <4 x float> %54, i32 3
>  %59 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
>  %61 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %60, i32 0, i32 %5)
>  %62 = extractelement <4 x float> %61, i32 0
>  %63 = extractelement <4 x float> %61, i32 1
>  %64 = extractelement <4 x float> %61, i32 2
>  %65 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %66 = load <16 x i8> addrspace(2)* %65, !tbaa !0
>  %67 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %66, i32 0, i32 %5)
>  %68 = extractelement <4 x float> %67, i32 0
>  %69 = extractelement <4 x float> %67, i32 1
>  %70 = extractelement <4 x float> %67, i32 2
>  %71 = extractelement <4 x float> %67, i32 3
>  %72 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %73 = load <16 x i8> addrspace(2)* %72, !tbaa !0
>  %74 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %73, i32 0, i32 %5)
>  %75 = extractelement <4 x float> %74, i32 0
>  %76 = extractelement <4 x float> %74, i32 1
>  %77 = extractelement <4 x float> %74, i32 2
>  %78 = extractelement <4 x float> %74, i32 3
>  %79 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %80 = load <16 x i8> addrspace(2)* %79, !tbaa !0
>  %81 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %80, i32 0, i32 %5)
>  %82 = extractelement <4 x float> %81, i32 3
>  %83 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %84 = load <16 x i8> addrspace(2)* %83, !tbaa !0
>  %85 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %84, i32 0, i32 %5)
>  %86 = extractelement <4 x float> %85, i32 0
>  %87 = extractelement <4 x float> %85, i32 1
>  %88 = extractelement <4 x float> %85, i32 2
>  %89 = extractelement <4 x float> %85, i32 3
>  %90 = fmul float %55, %11
>  %91 = fmul float %55, %12
>  %92 = fmul float %55, %13
>  %93 = fmul float %55, %14
>  %94 = fmul float %56, %15
>  %95 = fadd float %94, %90
>  %96 = fmul float %56, %16
>  %97 = fadd float %96, %91
>  %98 = fmul float %56, %17
>  %99 = fadd float %98, %92
>  %100 = fmul float %56, %18
>  %101 = fadd float %100, %93
>  %102 = fmul float %57, %19
>  %103 = fadd float %102, %95
>  %104 = fmul float %57, %20
>  %105 = fadd float %104, %97
>  %106 = fmul float %57, %21
>  %107 = fadd float %106, %99
>  %108 = fmul float %57, %22
>  %109 = fadd float %108, %101
>  %110 = fmul float %58, %23
>  %111 = fadd float %110, %103
>  %112 = fmul float %58, %24
>  %113 = fadd float %112, %105
>  %114 = fmul float %58, %25
>  %115 = fadd float %114, %107
>  %116 = fmul float %58, %26
>  %117 = fadd float %116, %109
>  %118 = call float @llvm.AMDIL.clamp.(float %68, float 0.000000e+00, float 1.000000e+00)
>  %119 = call float @llvm.AMDIL.clamp.(float %69, float 0.000000e+00, float 1.000000e+00)
>  %120 = call float @llvm.AMDIL.clamp.(float %70, float 0.000000e+00, float 1.000000e+00)
>  %121 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %122 = fmul float %55, %27
>  %123 = fmul float %56, %28
>  %124 = fadd float %122, %123
>  %125 = fmul float %57, %29
>  %126 = fadd float %124, %125
>  %127 = fmul float %58, %30
>  %128 = fadd float %126, %127
>  %129 = call float @fabs(float %128)
>  %130 = fmul float %62, %31
>  %131 = fmul float %63, %32
>  %132 = fadd float %131, %130
>  %133 = fmul float %64, %33
>  %134 = fadd float %132, %133
>  %135 = fmul float %62, %34
>  %136 = fmul float %63, %35
>  %137 = fadd float %136, %135
>  %138 = fmul float %64, %36
>  %139 = fadd float %137, %138
>  %140 = fmul float %62, %37
>  %141 = fmul float %63, %38
>  %142 = fadd float %141, %140
>  %143 = fmul float %64, %39
>  %144 = fadd float %142, %143
>  %145 = fmul float %134, %134
>  %146 = fmul float %139, %139
>  %147 = fadd float %146, %145
>  %148 = fmul float %144, %144
>  %149 = fadd float %147, %148
>  %150 = call float @fabs(float %149)
>  %151 = call float @llvm.AMDGPU.rsq(float %150)
>  %152 = fmul float %134, %151
>  %153 = fmul float %139, %151
>  %154 = fmul float %144, %151
>  %155 = fmul float %55, %40
>  %156 = fmul float %55, %41
>  %157 = fmul float %55, %42
>  %158 = fmul float %56, %43
>  %159 = fadd float %158, %155
>  %160 = fmul float %56, %44
>  %161 = fadd float %160, %156
>  %162 = fmul float %56, %45
>  %163 = fadd float %162, %157
>  %164 = fmul float %57, %46
>  %165 = fadd float %164, %159
>  %166 = fmul float %57, %47
>  %167 = fadd float %166, %161
>  %168 = fmul float %57, %48
>  %169 = fadd float %168, %163
>  %170 = fmul float %58, %49
>  %171 = fadd float %170, %165
>  %172 = fmul float %58, %50
>  %173 = fadd float %172, %167
>  %174 = fmul float %58, %51
>  %175 = fadd float %174, %169
>  %176 = fmul float %171, %171
>  %177 = fmul float %173, %173
>  %178 = fadd float %177, %176
>  %179 = fmul float %175, %175
>  %180 = fadd float %178, %179
>  %181 = call float @fabs(float %180)
>  %182 = call float @llvm.AMDGPU.rsq(float %181)
>  %183 = fmul float %171, %182
>  %184 = fmul float %173, %182
>  %185 = fmul float %175, %182
>  %186 = fmul float %152, %183
>  %187 = fmul float %153, %184
>  %188 = fadd float %187, %186
>  %189 = fmul float %154, %185
>  %190 = fadd float %188, %189
>  %191 = fadd float %190, %190
>  %192 = fadd float %190, %190
>  %193 = fadd float %190, %190
>  %194 = fsub float -0.000000e+00, %191
>  %195 = fmul float %194, %152
>  %196 = fadd float %195, %183
>  %197 = fsub float -0.000000e+00, %192
>  %198 = fmul float %197, %153
>  %199 = fadd float %198, %184
>  %200 = fsub float -0.000000e+00, %193
>  %201 = fmul float %200, %154
>  %202 = fadd float %201, %185
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %118, float %119, float %120, float %121)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %129, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %75, float %76, float %77, float %78)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %196, float %199, float %202, float %82)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %86, float %87, float %88, float %89)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %111, float %113, float %115, float %117)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c084070c
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800022f
>08070605
>c0840704
>bf8c000f
>e00c2000
>80020600
>c2020128
>bf8c0070
>100a0c04
>c2020129
>bf8c007f
>d2820005
>04140907
>c202012a
>bf8c007f
>d2820005
>04140908
>c2020124
>bf8c007f
>10140c04
>c2020125
>bf8c007f
>d282000a
>04280907
>c2020126
>bf8c007f
>d282000a
>04280908
>1016150a
>d282000b
>042e0b05
>c202012c
>bf8c007f
>10180c04
>c202012d
>bf8c007f
>d282000c
>04300907
>c202012e
>bf8c007f
>d2820007
>04300908
>d2820006
>042e0f07
>d2060106
>02010106
>7e105b06
>100c110a
>c2020131
>bf8c007f
>10120204
>c2020135
>bf8c007f
>d2820009
>04240902
>c2020139
>bf8c007f
>d2820009
>04240903
>c202013d
>bf8c007f
>d2820009
>04240904
>c2020130
>bf8c007f
>10140204
>c2020134
>bf8c007f
>d282000a
>04280902
>c2020138
>bf8c007f
>d282000a
>04280903
>c202013c
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c2020132
>bf8c007f
>10160204
>c2020136
>bf8c007f
>d282000b
>042c0902
>c202013a
>bf8c007f
>d282000b
>042c0903
>c202013e
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101a1506
>100a1105
>10121909
>d282000d
>04361305
>100e1107
>1016190b
>d2820008
>04361707
>06101108
>100e0f08
>080e0f0b
>100a0b08
>080a0b09
>100c0d08
>080c0d0a
>c0840710
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800023f
>0b070506
>c0820714
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800024f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = fmul float %34, %11
>  %53 = fmul float %34, %12
>  %54 = fmul float %34, %13
>  %55 = fmul float %34, %14
>  %56 = fmul float %35, %15
>  %57 = fadd float %56, %52
>  %58 = fmul float %35, %16
>  %59 = fadd float %58, %53
>  %60 = fmul float %35, %17
>  %61 = fadd float %60, %54
>  %62 = fmul float %35, %18
>  %63 = fadd float %62, %55
>  %64 = fmul float %36, %19
>  %65 = fadd float %64, %57
>  %66 = fmul float %36, %20
>  %67 = fadd float %66, %59
>  %68 = fmul float %36, %21
>  %69 = fadd float %68, %61
>  %70 = fmul float %36, %22
>  %71 = fadd float %70, %63
>  %72 = fmul float %37, %23
>  %73 = fadd float %72, %65
>  %74 = fmul float %37, %24
>  %75 = fadd float %74, %67
>  %76 = fmul float %37, %25
>  %77 = fadd float %76, %69
>  %78 = fmul float %37, %26
>  %79 = fadd float %78, %71
>  %80 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %81 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %82 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %83 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %84 = fmul float %34, %27
>  %85 = fmul float %35, %28
>  %86 = fadd float %84, %85
>  %87 = fmul float %36, %29
>  %88 = fadd float %86, %87
>  %89 = fmul float %37, %30
>  %90 = fadd float %88, %89
>  %91 = call float @fabs(float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %80, float %81, float %82, float %83)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %91, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %73, float %75, float %77, float %79)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV TEMP[1].xy, IN[3].xyyy
>  5: MOV TEMP[1].w, IN[3].wwww
>  6: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  7: MUL_SAT TEMP[2], TEMP[0], IMM[0].xxxy
>  8: MUL TEMP[1].xyz, TEMP[1], TEMP[2]
>  9: MOV TEMP[1].xyz, TEMP[1].xyzx
> 10: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
> 11: MOV TEMP[1].w, TEMP[0].wwww
> 12: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
> 13: MOV TEMP[1].w, TEMP[0]
> 14: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[2].xxxx, CONST[2].yyyy
> 15: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
> 16: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
> 17: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 18: MOV OUT[0], TEMP[1]
> 19: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %46 = fdiv float %40, %42
>  %47 = fdiv float %41, %42
>  %48 = bitcast float %46 to i32
>  %49 = bitcast float %47 to i32
>  %50 = insertelement <2 x i32> undef, i32 %48, i32 0
>  %51 = insertelement <2 x i32> %50, i32 %49, i32 1
>  %52 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %51, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = fmul float %53, %35
>  %58 = fmul float %54, %36
>  %59 = fmul float %55, %37
>  %60 = fmul float %56, %38
>  %61 = fdiv float %43, %45
>  %62 = fdiv float %44, %45
>  %63 = bitcast float %61 to i32
>  %64 = bitcast float %62 to i32
>  %65 = insertelement <2 x i32> undef, i32 %63, i32 0
>  %66 = insertelement <2 x i32> %65, i32 %64, i32 1
>  %67 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %66, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %68 = extractelement <4 x float> %67, i32 0
>  %69 = extractelement <4 x float> %67, i32 1
>  %70 = extractelement <4 x float> %67, i32 2
>  %71 = fmul float %57, 2.000000e+00
>  %72 = fmul float %58, 2.000000e+00
>  %73 = fmul float %59, 2.000000e+00
>  %74 = fmul float %60, 1.000000e+00
>  %75 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %76 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %73, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00)
>  %79 = fmul float %68, %75
>  %80 = fmul float %69, %76
>  %81 = fmul float %70, %77
>  %82 = fmul float %57, 2.000000e+00
>  %83 = fmul float %58, 2.000000e+00
>  %84 = fmul float %59, 2.000000e+00
>  %85 = fmul float %60, 1.000000e+00
>  %86 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %87 = call float @llvm.AMDIL.clamp.(float %83, float 0.000000e+00, float 1.000000e+00)
>  %88 = call float @llvm.AMDIL.clamp.(float %84, float 0.000000e+00, float 1.000000e+00)
>  %89 = call float @llvm.AMDIL.clamp.(float %85, float 0.000000e+00, float 1.000000e+00)
>  %90 = fmul float %79, 2.000000e+00
>  %91 = fmul float %80, 2.000000e+00
>  %92 = fmul float %81, 2.000000e+00
>  %93 = fmul float %89, 1.000000e+00
>  %94 = call float @llvm.AMDIL.clamp.(float %90, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %91, float 0.000000e+00, float 1.000000e+00)
>  %96 = call float @llvm.AMDIL.clamp.(float %92, float 0.000000e+00, float 1.000000e+00)
>  %97 = call float @llvm.AMDIL.clamp.(float %93, float 0.000000e+00, float 1.000000e+00)
>  %98 = fmul float %39, %22
>  %99 = fadd float %98, %23
>  %100 = call float @llvm.AMDIL.clamp.(float %99, float 0.000000e+00, float 1.000000e+00)
>  %101 = fsub float -0.000000e+00, %100
>  %102 = fadd float 1.000000e+00, %101
>  %103 = fmul float %24, %102
>  %104 = fmul float %25, %102
>  %105 = fmul float %26, %102
>  %106 = fmul float %94, %100
>  %107 = fadd float %106, %103
>  %108 = fmul float %95, %100
>  %109 = fadd float %108, %104
>  %110 = fmul float %96, %100
>  %111 = fadd float %110, %105
>  %112 = fcmp ugt float %97, 0x3FDFDFDFE0000000
>  %113 = sext i1 %112 to i32
>  %114 = trunc i32 %113 to i1
>  %115 = select i1 %114, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %115)
>  %116 = call i32 @llvm.SI.packf16(float %107, float %109)
>  %117 = bitcast i32 %116 to float
>  %118 = call i32 @llvm.SI.packf16(float %111, float %97)
>  %119 = bitcast i32 %118 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %117, float %119, float %117, float %119)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>d2060806
>02010106
>d2060806
>02010106
>7e0e02ff
>3efefeff
>d0080008
>02020f06
>d2000007
>0021e4f3
>7c260e80
>c81c0100
>c81d0101
>10100f03
>d2820007
>04220f03
>d206080a
>02010107
>c81c0d00
>c81d0d01
>c8200f00
>c8210f01
>7e125508
>10101307
>c82c0c00
>c82d0c01
>100e130b
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430707
>bf8c0770
>10161508
>d282000a
>042e1508
>d206080c
>0201010a
>c8280400
>c8290401
>c0800100
>bf8c007f
>c2020108
>c2028109
>bf8c007f
>7e160205
>d282000a
>042c090a
>d206080a
>0201010a
>081614f2
>c202010d
>bf8c007f
>101a1604
>d282000c
>0436150c
>c8340000
>c8350001
>101c1b02
>d282000d
>043a1b02
>d206080d
>0201010d
>101c1b07
>d282000d
>043a1b07
>d206080d
>0201010d
>c202010c
>bf8c007f
>101c1604
>d282000d
>043a150d
>5e18190d
>c8340200
>c8350201
>10001b04
>d2820000
>04021b04
>d2060800
>02010100
>10020109
>d2820000
>04060109
>d2060800
>02010100
>c200010e
>bf8c007f
>10021600
>d2820000
>04061500
>5e000d00
>f8001c0f
>000c000c
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..7]
>DCL CONST[9..12]
>DCL TEMP[0..1]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: MUL TEMP[1], IN[3].xxxx, CONST[9]
> 10: MAD TEMP[1], IN[3].yyyy, CONST[10], TEMP[1]
> 11: MAD TEMP[1], IN[3].zzzz, CONST[11], TEMP[1]
> 12: MAD OUT[4], IN[3].wwww, CONST[12], TEMP[1]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = extractelement <4 x float> %56, i32 3
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 0
>  %65 = extractelement <4 x float> %63, i32 1
>  %66 = extractelement <4 x float> %63, i32 2
>  %67 = extractelement <4 x float> %63, i32 3
>  %68 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
>  %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %69, i32 0, i32 %5)
>  %71 = extractelement <4 x float> %70, i32 0
>  %72 = extractelement <4 x float> %70, i32 1
>  %73 = extractelement <4 x float> %70, i32 2
>  %74 = extractelement <4 x float> %70, i32 3
>  %75 = fmul float %50, %11
>  %76 = fmul float %50, %12
>  %77 = fmul float %50, %13
>  %78 = fmul float %50, %14
>  %79 = fmul float %51, %15
>  %80 = fadd float %79, %75
>  %81 = fmul float %51, %16
>  %82 = fadd float %81, %76
>  %83 = fmul float %51, %17
>  %84 = fadd float %83, %77
>  %85 = fmul float %51, %18
>  %86 = fadd float %85, %78
>  %87 = fmul float %52, %19
>  %88 = fadd float %87, %80
>  %89 = fmul float %52, %20
>  %90 = fadd float %89, %82
>  %91 = fmul float %52, %21
>  %92 = fadd float %91, %84
>  %93 = fmul float %52, %22
>  %94 = fadd float %93, %86
>  %95 = fmul float %53, %23
>  %96 = fadd float %95, %88
>  %97 = fmul float %53, %24
>  %98 = fadd float %97, %90
>  %99 = fmul float %53, %25
>  %100 = fadd float %99, %92
>  %101 = fmul float %53, %26
>  %102 = fadd float %101, %94
>  %103 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %104 = call float @llvm.AMDIL.clamp.(float %58, float 0.000000e+00, float 1.000000e+00)
>  %105 = call float @llvm.AMDIL.clamp.(float %59, float 0.000000e+00, float 1.000000e+00)
>  %106 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %107 = fmul float %50, %27
>  %108 = fmul float %51, %28
>  %109 = fadd float %107, %108
>  %110 = fmul float %52, %29
>  %111 = fadd float %109, %110
>  %112 = fmul float %53, %30
>  %113 = fadd float %111, %112
>  %114 = call float @fabs(float %113)
>  %115 = fmul float %71, %31
>  %116 = fmul float %71, %32
>  %117 = fmul float %71, %33
>  %118 = fmul float %71, %34
>  %119 = fmul float %72, %35
>  %120 = fadd float %119, %115
>  %121 = fmul float %72, %36
>  %122 = fadd float %121, %116
>  %123 = fmul float %72, %37
>  %124 = fadd float %123, %117
>  %125 = fmul float %72, %38
>  %126 = fadd float %125, %118
>  %127 = fmul float %73, %39
>  %128 = fadd float %127, %120
>  %129 = fmul float %73, %40
>  %130 = fadd float %129, %122
>  %131 = fmul float %73, %41
>  %132 = fadd float %131, %124
>  %133 = fmul float %73, %42
>  %134 = fadd float %133, %126
>  %135 = fmul float %74, %43
>  %136 = fadd float %135, %128
>  %137 = fmul float %74, %44
>  %138 = fadd float %137, %130
>  %139 = fmul float %74, %45
>  %140 = fadd float %139, %132
>  %141 = fmul float %74, %46
>  %142 = fadd float %141, %134
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %103, float %104, float %105, float %106)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %114, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %64, float %65, float %66, float %67)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %136, float %138, float %140, float %142)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %96, float %98, float %100, float %102)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0840708
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800022f
>08070605
>c082070c
>bf8c000f
>e00c2000
>80010500
>c2020127
>bf8c0070
>10000a04
>c202012b
>bf8c007f
>d2820000
>04000906
>c202012f
>bf8c007f
>d2820000
>04000907
>c2020133
>bf8c007f
>d2820000
>04000908
>c2020126
>bf8c007f
>10120a04
>c202012a
>bf8c007f
>d2820009
>04240906
>c202012e
>bf8c007f
>d2820009
>04240907
>c2020132
>bf8c007f
>d2820009
>04240908
>c2020125
>bf8c007f
>10140a04
>c2020129
>bf8c007f
>d282000a
>04280906
>c202012d
>bf8c007f
>d282000a
>04280907
>c2020131
>bf8c007f
>d282000a
>04280908
>c2020124
>bf8c007f
>10160a04
>c2020128
>bf8c007f
>d282000b
>042c0906
>c202012c
>bf8c007f
>d282000b
>042c0907
>c2020130
>bf8c007f
>d2820005
>042c0908
>f800023f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MOV TEMP[1].xy, IN[3].xyyy
>  4: MOV TEMP[1].w, IN[3].wwww
>  5: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  6: MAD TEMP[1].xyz, TEMP[0], TEMP[1].wwww, TEMP[1]
>  7: MOV_SAT TEMP[1].xyz, TEMP[1].xyzz
>  8: MOV TEMP[1].w, TEMP[0].wwww
>  9: MUL TEMP[1].xyz, IN[0], TEMP[1]
> 10: MOV TEMP[1].xyz, TEMP[1].xyzx
> 11: MOV TEMP[1].w, TEMP[0].wwww
> 12: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
> 13: MOV TEMP[1].w, TEMP[0]
> 14: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[2].xxxx, CONST[2].yyyy
> 15: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
> 16: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
> 17: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 18: MOV OUT[0], TEMP[1]
> 19: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %45 = fdiv float %39, %41
>  %46 = fdiv float %40, %41
>  %47 = bitcast float %45 to i32
>  %48 = bitcast float %46 to i32
>  %49 = insertelement <2 x i32> undef, i32 %47, i32 0
>  %50 = insertelement <2 x i32> %49, i32 %48, i32 1
>  %51 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %50, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %52 = extractelement <4 x float> %51, i32 0
>  %53 = extractelement <4 x float> %51, i32 1
>  %54 = extractelement <4 x float> %51, i32 2
>  %55 = extractelement <4 x float> %51, i32 3
>  %56 = fdiv float %42, %44
>  %57 = fdiv float %43, %44
>  %58 = bitcast float %56 to i32
>  %59 = bitcast float %57 to i32
>  %60 = insertelement <2 x i32> undef, i32 %58, i32 0
>  %61 = insertelement <2 x i32> %60, i32 %59, i32 1
>  %62 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %61, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = extractelement <4 x float> %62, i32 1
>  %65 = extractelement <4 x float> %62, i32 2
>  %66 = extractelement <4 x float> %62, i32 3
>  %67 = fmul float %52, %66
>  %68 = fadd float %67, %63
>  %69 = fmul float %53, %66
>  %70 = fadd float %69, %64
>  %71 = fmul float %54, %66
>  %72 = fadd float %71, %65
>  %73 = call float @llvm.AMDIL.clamp.(float %68, float 0.000000e+00, float 1.000000e+00)
>  %74 = call float @llvm.AMDIL.clamp.(float %70, float 0.000000e+00, float 1.000000e+00)
>  %75 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
>  %76 = fmul float %35, %73
>  %77 = fmul float %36, %74
>  %78 = fmul float %37, %75
>  %79 = fmul float %76, 2.000000e+00
>  %80 = fmul float %77, 2.000000e+00
>  %81 = fmul float %78, 2.000000e+00
>  %82 = fmul float %55, 1.000000e+00
>  %83 = call float @llvm.AMDIL.clamp.(float %79, float 0.000000e+00, float 1.000000e+00)
>  %84 = call float @llvm.AMDIL.clamp.(float %80, float 0.000000e+00, float 1.000000e+00)
>  %85 = call float @llvm.AMDIL.clamp.(float %81, float 0.000000e+00, float 1.000000e+00)
>  %86 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %87 = fmul float %38, %22
>  %88 = fadd float %87, %23
>  %89 = call float @llvm.AMDIL.clamp.(float %88, float 0.000000e+00, float 1.000000e+00)
>  %90 = fsub float -0.000000e+00, %89
>  %91 = fadd float 1.000000e+00, %90
>  %92 = fmul float %24, %91
>  %93 = fmul float %25, %91
>  %94 = fmul float %26, %91
>  %95 = fmul float %83, %89
>  %96 = fadd float %95, %92
>  %97 = fmul float %84, %89
>  %98 = fadd float %97, %93
>  %99 = fmul float %85, %89
>  %100 = fadd float %99, %94
>  %101 = call i32 @llvm.SI.packf16(float %96, float %98)
>  %102 = bitcast i32 %101 to float
>  %103 = call i32 @llvm.SI.packf16(float %100, float %86)
>  %104 = bitcast i32 %103 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %102, float %104, float %102, float %104)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080d00
>c8090d01
>c80c0f00
>c80d0f01
>7e085503
>10060902
>c8140c00
>c8150c01
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c8180900
>c8190901
>c81c0b00
>c81d0b01
>7e105507
>100e1106
>c8240800
>c8250801
>100c1109
>c0840304
>c0c60508
>bf8c0070
>f0800f00
>00430606
>bf8c0770
>d282000a
>040e0b07
>d206080a
>0201010a
>c82c0100
>c82d0101
>1018150b
>d282000a
>0432150b
>d206080c
>0201010a
>c8280400
>c8290401
>c0800100
>bf8c007f
>c2020108
>c2028109
>bf8c007f
>7e160205
>d282000a
>042c090a
>d206080a
>0201010a
>081614f2
>c202010d
>bf8c007f
>101a1604
>d282000c
>0436150c
>d282000d
>040a0b06
>d206080d
>0201010d
>c8380000
>c8390001
>101e1b0e
>d282000d
>043e1b0e
>d206080d
>0201010d
>c202010c
>bf8c007f
>101c1604
>d282000d
>043a150d
>5e18190d
>d2820002
>04120b08
>d2060802
>02010102
>c80c0200
>c80d0201
>10000503
>d2820000
>04020503
>d2060800
>02010100
>c200010e
>bf8c007f
>10021600
>d2820000
>04061500
>d2060801
>02010109
>5e000300
>f8001c0f
>000c000c
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..7]
>DCL CONST[9..19]
>DCL TEMP[0..5]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[2]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[3]
>  9: DP3 TEMP[1].x, IN[1], CONST[9]
> 10: DP3 TEMP[1].y, IN[1], CONST[10]
> 11: DP3 TEMP[1].z, IN[1], CONST[11]
> 12: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 13: RSQ TEMP[2].x, |TEMP[2]|
> 14: MUL TEMP[1], TEMP[1], TEMP[2].xxxx
> 15: MUL TEMP[2], IN[0].xxxx, CONST[12]
> 16: MAD TEMP[2], IN[0].yyyy, CONST[13], TEMP[2]
> 17: MAD TEMP[2], IN[0].zzzz, CONST[14], TEMP[2]
> 18: MAD TEMP[2], IN[0].wwww, CONST[15], TEMP[2]
> 19: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 20: RSQ TEMP[3].x, |TEMP[3]|
> 21: MUL TEMP[4], TEMP[2], TEMP[3].xxxx
> 22: DP3 TEMP[3], TEMP[1], TEMP[4]
> 23: ADD TEMP[3], TEMP[3], TEMP[3]
> 24: MAD TEMP[5].xyz, -TEMP[3], TEMP[1], TEMP[4]
> 25: MOV TEMP[5].w, IN[4]
> 26: MUL TEMP[3], TEMP[5].xxxx, CONST[16]
> 27: MAD TEMP[3], TEMP[5].yyyy, CONST[17], TEMP[3]
> 28: MAD TEMP[3], TEMP[5].zzzz, CONST[18], TEMP[3]
> 29: MAD OUT[4], TEMP[5].wwww, CONST[19], TEMP[3]
> 30: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 268)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 284)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 300)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
>  %68 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
>  %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %69, i32 0, i32 %5)
>  %71 = extractelement <4 x float> %70, i32 0
>  %72 = extractelement <4 x float> %70, i32 1
>  %73 = extractelement <4 x float> %70, i32 2
>  %74 = extractelement <4 x float> %70, i32 3
>  %75 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0
>  %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %76, i32 0, i32 %5)
>  %78 = extractelement <4 x float> %77, i32 0
>  %79 = extractelement <4 x float> %77, i32 1
>  %80 = extractelement <4 x float> %77, i32 2
>  %81 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %82 = load <16 x i8> addrspace(2)* %81, !tbaa !0
>  %83 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %82, i32 0, i32 %5)
>  %84 = extractelement <4 x float> %83, i32 0
>  %85 = extractelement <4 x float> %83, i32 1
>  %86 = extractelement <4 x float> %83, i32 2
>  %87 = extractelement <4 x float> %83, i32 3
>  %88 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %89 = load <16 x i8> addrspace(2)* %88, !tbaa !0
>  %90 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %89, i32 0, i32 %5)
>  %91 = extractelement <4 x float> %90, i32 0
>  %92 = extractelement <4 x float> %90, i32 1
>  %93 = extractelement <4 x float> %90, i32 2
>  %94 = extractelement <4 x float> %90, i32 3
>  %95 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %96 = load <16 x i8> addrspace(2)* %95, !tbaa !0
>  %97 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %96, i32 0, i32 %5)
>  %98 = extractelement <4 x float> %97, i32 3
>  %99 = fmul float %71, %11
>  %100 = fmul float %71, %12
>  %101 = fmul float %71, %13
>  %102 = fmul float %71, %14
>  %103 = fmul float %72, %15
>  %104 = fadd float %103, %99
>  %105 = fmul float %72, %16
>  %106 = fadd float %105, %100
>  %107 = fmul float %72, %17
>  %108 = fadd float %107, %101
>  %109 = fmul float %72, %18
>  %110 = fadd float %109, %102
>  %111 = fmul float %73, %19
>  %112 = fadd float %111, %104
>  %113 = fmul float %73, %20
>  %114 = fadd float %113, %106
>  %115 = fmul float %73, %21
>  %116 = fadd float %115, %108
>  %117 = fmul float %73, %22
>  %118 = fadd float %117, %110
>  %119 = fmul float %74, %23
>  %120 = fadd float %119, %112
>  %121 = fmul float %74, %24
>  %122 = fadd float %121, %114
>  %123 = fmul float %74, %25
>  %124 = fadd float %123, %116
>  %125 = fmul float %74, %26
>  %126 = fadd float %125, %118
>  %127 = call float @llvm.AMDIL.clamp.(float %84, float 0.000000e+00, float 1.000000e+00)
>  %128 = call float @llvm.AMDIL.clamp.(float %85, float 0.000000e+00, float 1.000000e+00)
>  %129 = call float @llvm.AMDIL.clamp.(float %86, float 0.000000e+00, float 1.000000e+00)
>  %130 = call float @llvm.AMDIL.clamp.(float %87, float 0.000000e+00, float 1.000000e+00)
>  %131 = fmul float %71, %27
>  %132 = fmul float %72, %28
>  %133 = fadd float %131, %132
>  %134 = fmul float %73, %29
>  %135 = fadd float %133, %134
>  %136 = fmul float %74, %30
>  %137 = fadd float %135, %136
>  %138 = call float @fabs(float %137)
>  %139 = fmul float %78, %31
>  %140 = fmul float %79, %32
>  %141 = fadd float %140, %139
>  %142 = fmul float %80, %33
>  %143 = fadd float %141, %142
>  %144 = fmul float %78, %34
>  %145 = fmul float %79, %35
>  %146 = fadd float %145, %144
>  %147 = fmul float %80, %36
>  %148 = fadd float %146, %147
>  %149 = fmul float %78, %37
>  %150 = fmul float %79, %38
>  %151 = fadd float %150, %149
>  %152 = fmul float %80, %39
>  %153 = fadd float %151, %152
>  %154 = fmul float %143, %143
>  %155 = fmul float %148, %148
>  %156 = fadd float %155, %154
>  %157 = fmul float %153, %153
>  %158 = fadd float %156, %157
>  %159 = call float @fabs(float %158)
>  %160 = call float @llvm.AMDGPU.rsq(float %159)
>  %161 = fmul float %143, %160
>  %162 = fmul float %148, %160
>  %163 = fmul float %153, %160
>  %164 = fmul float %71, %40
>  %165 = fmul float %71, %41
>  %166 = fmul float %71, %42
>  %167 = fmul float %72, %43
>  %168 = fadd float %167, %164
>  %169 = fmul float %72, %44
>  %170 = fadd float %169, %165
>  %171 = fmul float %72, %45
>  %172 = fadd float %171, %166
>  %173 = fmul float %73, %46
>  %174 = fadd float %173, %168
>  %175 = fmul float %73, %47
>  %176 = fadd float %175, %170
>  %177 = fmul float %73, %48
>  %178 = fadd float %177, %172
>  %179 = fmul float %74, %49
>  %180 = fadd float %179, %174
>  %181 = fmul float %74, %50
>  %182 = fadd float %181, %176
>  %183 = fmul float %74, %51
>  %184 = fadd float %183, %178
>  %185 = fmul float %180, %180
>  %186 = fmul float %182, %182
>  %187 = fadd float %186, %185
>  %188 = fmul float %184, %184
>  %189 = fadd float %187, %188
>  %190 = call float @fabs(float %189)
>  %191 = call float @llvm.AMDGPU.rsq(float %190)
>  %192 = fmul float %180, %191
>  %193 = fmul float %182, %191
>  %194 = fmul float %184, %191
>  %195 = fmul float %161, %192
>  %196 = fmul float %162, %193
>  %197 = fadd float %196, %195
>  %198 = fmul float %163, %194
>  %199 = fadd float %197, %198
>  %200 = fadd float %199, %199
>  %201 = fadd float %199, %199
>  %202 = fadd float %199, %199
>  %203 = fsub float -0.000000e+00, %200
>  %204 = fmul float %203, %161
>  %205 = fadd float %204, %192
>  %206 = fsub float -0.000000e+00, %201
>  %207 = fmul float %206, %162
>  %208 = fadd float %207, %193
>  %209 = fsub float -0.000000e+00, %202
>  %210 = fmul float %209, %163
>  %211 = fadd float %210, %194
>  %212 = fmul float %205, %52
>  %213 = fmul float %205, %53
>  %214 = fmul float %205, %54
>  %215 = fmul float %205, %55
>  %216 = fmul float %208, %56
>  %217 = fadd float %216, %212
>  %218 = fmul float %208, %57
>  %219 = fadd float %218, %213
>  %220 = fmul float %208, %58
>  %221 = fadd float %220, %214
>  %222 = fmul float %208, %59
>  %223 = fadd float %222, %215
>  %224 = fmul float %211, %60
>  %225 = fadd float %224, %217
>  %226 = fmul float %211, %61
>  %227 = fadd float %226, %219
>  %228 = fmul float %211, %62
>  %229 = fadd float %228, %221
>  %230 = fmul float %211, %63
>  %231 = fadd float %230, %223
>  %232 = fmul float %98, %64
>  %233 = fadd float %232, %225
>  %234 = fmul float %98, %65
>  %235 = fadd float %234, %227
>  %236 = fmul float %98, %66
>  %237 = fadd float %236, %229
>  %238 = fmul float %98, %67
>  %239 = fadd float %238, %231
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %127, float %128, float %129, float %130)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %138, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %91, float %92, float %93, float %94)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %233, float %235, float %237, float %239)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %120, float %122, float %124, float %126)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c084070c
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800022f
>08070605
>c0840704
>bf8c000f
>e00c2000
>80020600
>c2020128
>bf8c0070
>100a0c04
>c2020129
>bf8c007f
>d2820005
>04140907
>c202012a
>bf8c007f
>d2820005
>04140908
>c2020124
>bf8c007f
>10140c04
>c2020125
>bf8c007f
>d282000a
>04280907
>c2020126
>bf8c007f
>d282000a
>04280908
>1016150a
>d282000b
>042e0b05
>c202012c
>bf8c007f
>10180c04
>c202012d
>bf8c007f
>d282000c
>04300907
>c202012e
>bf8c007f
>d2820007
>04300908
>d2820006
>042e0f07
>d2060106
>02010106
>7e105b06
>100c110a
>c2020131
>bf8c007f
>10120204
>c2020135
>bf8c007f
>d2820009
>04240902
>c2020139
>bf8c007f
>d2820009
>04240903
>c202013d
>bf8c007f
>d2820009
>04240904
>c2020130
>bf8c007f
>10140204
>c2020134
>bf8c007f
>d282000a
>04280902
>c2020138
>bf8c007f
>d282000a
>04280903
>c202013c
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c2020132
>bf8c007f
>10160204
>c2020136
>bf8c007f
>d282000b
>042c0902
>c202013a
>bf8c007f
>d282000b
>042c0903
>c202013e
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101c1506
>100a1105
>101a1909
>d2820009
>043a1b05
>100e1107
>1010190b
>d2820009
>04261107
>06121309
>100a0b09
>080a0b0d
>100c0d09
>080c0d0a
>c2020143
>bf8c007f
>10140c04
>c2020147
>bf8c007f
>d282000a
>04280905
>100e0f09
>080e0f08
>c202014b
>bf8c007f
>d282000c
>04280907
>c0820710
>bf8c007f
>e00c2000
>80010800
>c202014f
>bf8c0070
>d2820000
>0430090b
>c2020142
>bf8c007f
>10180c04
>c2020146
>bf8c007f
>d282000c
>04300905
>c202014a
>bf8c007f
>d282000c
>04300907
>c202014e
>bf8c007f
>d282000c
>0430090b
>c2020141
>bf8c007f
>101a0c04
>c2020145
>bf8c007f
>d282000d
>04340905
>c2020149
>bf8c007f
>d282000d
>04340907
>c202014d
>bf8c007f
>d282000d
>0434090b
>c2020140
>bf8c007f
>100c0c04
>c2020144
>bf8c007f
>d2820005
>04180905
>c2020148
>bf8c007f
>d2820005
>04140907
>c202014c
>bf8c007f
>d2820005
>0414090b
>f800023f
>000c0d05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV TEMP[1].xy, IN[3].xyyy
>  5: MOV TEMP[1].w, IN[3].wwww
>  6: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  7: MUL_SAT TEMP[2], TEMP[0], IMM[0].xxxy
>  8: MUL TEMP[1].xyz, TEMP[1], TEMP[2]
>  9: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
> 10: MOV TEMP[0].w, TEMP[0].wwww
> 11: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[2].xxxx, CONST[2].yyyy
> 12: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
> 13: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
> 14: MAD TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 15: MOV OUT[0], TEMP[0]
> 16: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %46 = fdiv float %40, %42
>  %47 = fdiv float %41, %42
>  %48 = bitcast float %46 to i32
>  %49 = bitcast float %47 to i32
>  %50 = insertelement <2 x i32> undef, i32 %48, i32 0
>  %51 = insertelement <2 x i32> %50, i32 %49, i32 1
>  %52 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %51, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = fmul float %53, %35
>  %58 = fmul float %54, %36
>  %59 = fmul float %55, %37
>  %60 = fmul float %56, %38
>  %61 = fdiv float %43, %45
>  %62 = fdiv float %44, %45
>  %63 = bitcast float %61 to i32
>  %64 = bitcast float %62 to i32
>  %65 = insertelement <2 x i32> undef, i32 %63, i32 0
>  %66 = insertelement <2 x i32> %65, i32 %64, i32 1
>  %67 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %66, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %68 = extractelement <4 x float> %67, i32 0
>  %69 = extractelement <4 x float> %67, i32 1
>  %70 = extractelement <4 x float> %67, i32 2
>  %71 = fmul float %57, 2.000000e+00
>  %72 = fmul float %58, 2.000000e+00
>  %73 = fmul float %59, 2.000000e+00
>  %74 = fmul float %60, 1.000000e+00
>  %75 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %76 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %73, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00)
>  %79 = fmul float %68, %75
>  %80 = fmul float %69, %76
>  %81 = fmul float %70, %77
>  %82 = fmul float %57, 2.000000e+00
>  %83 = fmul float %58, 2.000000e+00
>  %84 = fmul float %59, 2.000000e+00
>  %85 = fmul float %60, 1.000000e+00
>  %86 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %87 = call float @llvm.AMDIL.clamp.(float %83, float 0.000000e+00, float 1.000000e+00)
>  %88 = call float @llvm.AMDIL.clamp.(float %84, float 0.000000e+00, float 1.000000e+00)
>  %89 = call float @llvm.AMDIL.clamp.(float %85, float 0.000000e+00, float 1.000000e+00)
>  %90 = fmul float %39, %22
>  %91 = fadd float %90, %23
>  %92 = call float @llvm.AMDIL.clamp.(float %91, float 0.000000e+00, float 1.000000e+00)
>  %93 = fsub float -0.000000e+00, %92
>  %94 = fadd float 1.000000e+00, %93
>  %95 = fmul float %24, %94
>  %96 = fmul float %25, %94
>  %97 = fmul float %26, %94
>  %98 = fmul float %79, %92
>  %99 = fadd float %98, %95
>  %100 = fmul float %80, %92
>  %101 = fadd float %100, %96
>  %102 = fmul float %81, %92
>  %103 = fadd float %102, %97
>  %104 = call i32 @llvm.SI.packf16(float %99, float %101)
>  %105 = bitcast i32 %104 to float
>  %106 = call i32 @llvm.SI.packf16(float %103, float %89)
>  %107 = bitcast i32 %106 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %105, float %107, float %105, float %107)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180100
>c8190101
>bf8c0770
>100e0d03
>d2820006
>041e0d03
>d2060809
>02010106
>c8180d00
>c8190d01
>c81c0f00
>c81d0f01
>7e105507
>100e1106
>c8280c00
>c8290c01
>100c110a
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430606
>bf8c0770
>10161307
>c8240400
>c8250401
>c0800100
>bf8c007f
>c2020108
>c2028109
>bf8c007f
>7e140205
>d2820009
>04280909
>d2060809
>02010109
>081412f2
>c202010d
>bf8c007f
>10181404
>d282000b
>0432130b
>c8300000
>c8310001
>101a1902
>d282000c
>04361902
>d206080c
>0201010c
>10181906
>c202010c
>bf8c007f
>101a1404
>d282000c
>0436130c
>5e16170c
>c8300200
>c8310201
>101a1904
>d282000c
>04361904
>d206080c
>0201010c
>100c1908
>c200010e
>bf8c007f
>100e1400
>d2820006
>041e1306
>c81c0300
>c81d0301
>10000f05
>d2060800
>02010100
>5e000106
>f8001c0f
>000b000b
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: MOV OUT[4], IN[3]
> 10: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %53 = load <16 x i8> addrspace(2)* %52, !tbaa !0
>  %54 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %53, i32 0, i32 %5)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %58 = extractelement <4 x float> %54, i32 3
>  %59 = fmul float %34, %11
>  %60 = fmul float %34, %12
>  %61 = fmul float %34, %13
>  %62 = fmul float %34, %14
>  %63 = fmul float %35, %15
>  %64 = fadd float %63, %59
>  %65 = fmul float %35, %16
>  %66 = fadd float %65, %60
>  %67 = fmul float %35, %17
>  %68 = fadd float %67, %61
>  %69 = fmul float %35, %18
>  %70 = fadd float %69, %62
>  %71 = fmul float %36, %19
>  %72 = fadd float %71, %64
>  %73 = fmul float %36, %20
>  %74 = fadd float %73, %66
>  %75 = fmul float %36, %21
>  %76 = fadd float %75, %68
>  %77 = fmul float %36, %22
>  %78 = fadd float %77, %70
>  %79 = fmul float %37, %23
>  %80 = fadd float %79, %72
>  %81 = fmul float %37, %24
>  %82 = fadd float %81, %74
>  %83 = fmul float %37, %25
>  %84 = fadd float %83, %76
>  %85 = fmul float %37, %26
>  %86 = fadd float %85, %78
>  %87 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %88 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %89 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %90 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %91 = fmul float %34, %27
>  %92 = fmul float %35, %28
>  %93 = fadd float %91, %92
>  %94 = fmul float %36, %29
>  %95 = fadd float %93, %94
>  %96 = fmul float %37, %30
>  %97 = fadd float %95, %96
>  %98 = call float @fabs(float %97)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %87, float %88, float %89, float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %98, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %55, float %56, float %57, float %58)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %80, float %82, float %84, float %86)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0840708
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800022f
>08070605
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..7]
>DCL CONST[9..12]
>DCL TEMP[0..1]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MUL TEMP[1], IN[2].xxxx, CONST[9]
>  9: MAD TEMP[1], IN[2].yyyy, CONST[10], TEMP[1]
> 10: MAD TEMP[1], IN[2].zzzz, CONST[11], TEMP[1]
> 11: MAD OUT[3], IN[2].wwww, CONST[12], TEMP[1]
> 12: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = extractelement <4 x float> %56, i32 3
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 0
>  %65 = extractelement <4 x float> %63, i32 1
>  %66 = extractelement <4 x float> %63, i32 2
>  %67 = extractelement <4 x float> %63, i32 3
>  %68 = fmul float %50, %11
>  %69 = fmul float %50, %12
>  %70 = fmul float %50, %13
>  %71 = fmul float %50, %14
>  %72 = fmul float %51, %15
>  %73 = fadd float %72, %68
>  %74 = fmul float %51, %16
>  %75 = fadd float %74, %69
>  %76 = fmul float %51, %17
>  %77 = fadd float %76, %70
>  %78 = fmul float %51, %18
>  %79 = fadd float %78, %71
>  %80 = fmul float %52, %19
>  %81 = fadd float %80, %73
>  %82 = fmul float %52, %20
>  %83 = fadd float %82, %75
>  %84 = fmul float %52, %21
>  %85 = fadd float %84, %77
>  %86 = fmul float %52, %22
>  %87 = fadd float %86, %79
>  %88 = fmul float %53, %23
>  %89 = fadd float %88, %81
>  %90 = fmul float %53, %24
>  %91 = fadd float %90, %83
>  %92 = fmul float %53, %25
>  %93 = fadd float %92, %85
>  %94 = fmul float %53, %26
>  %95 = fadd float %94, %87
>  %96 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %97 = call float @llvm.AMDIL.clamp.(float %58, float 0.000000e+00, float 1.000000e+00)
>  %98 = call float @llvm.AMDIL.clamp.(float %59, float 0.000000e+00, float 1.000000e+00)
>  %99 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %100 = fmul float %50, %27
>  %101 = fmul float %51, %28
>  %102 = fadd float %100, %101
>  %103 = fmul float %52, %29
>  %104 = fadd float %102, %103
>  %105 = fmul float %53, %30
>  %106 = fadd float %104, %105
>  %107 = call float @fabs(float %106)
>  %108 = fmul float %64, %31
>  %109 = fmul float %64, %32
>  %110 = fmul float %64, %33
>  %111 = fmul float %64, %34
>  %112 = fmul float %65, %35
>  %113 = fadd float %112, %108
>  %114 = fmul float %65, %36
>  %115 = fadd float %114, %109
>  %116 = fmul float %65, %37
>  %117 = fadd float %116, %110
>  %118 = fmul float %65, %38
>  %119 = fadd float %118, %111
>  %120 = fmul float %66, %39
>  %121 = fadd float %120, %113
>  %122 = fmul float %66, %40
>  %123 = fadd float %122, %115
>  %124 = fmul float %66, %41
>  %125 = fadd float %124, %117
>  %126 = fmul float %66, %42
>  %127 = fadd float %126, %119
>  %128 = fmul float %67, %43
>  %129 = fadd float %128, %121
>  %130 = fmul float %67, %44
>  %131 = fadd float %130, %123
>  %132 = fmul float %67, %45
>  %133 = fadd float %132, %125
>  %134 = fmul float %67, %46
>  %135 = fadd float %134, %127
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %96, float %97, float %98, float %99)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %107, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %129, float %131, float %133, float %135)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %89, float %91, float %93, float %95)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>c2020127
>bf8c0070
>10000a04
>c202012b
>bf8c007f
>d2820000
>04000906
>c202012f
>bf8c007f
>d2820000
>04000907
>c2020133
>bf8c007f
>d2820000
>04000908
>c2020126
>bf8c007f
>10120a04
>c202012a
>bf8c007f
>d2820009
>04240906
>c202012e
>bf8c007f
>d2820009
>04240907
>c2020132
>bf8c007f
>d2820009
>04240908
>c2020125
>bf8c007f
>10140a04
>c2020129
>bf8c007f
>d282000a
>04280906
>c202012d
>bf8c007f
>d282000a
>04280907
>c2020131
>bf8c007f
>d282000a
>04280908
>c2020124
>bf8c007f
>10160a04
>c2020128
>bf8c007f
>d282000b
>042c0906
>c202012c
>bf8c007f
>d282000b
>042c0907
>c2020130
>bf8c007f
>d2820005
>042c0908
>f800022f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV TEMP[1].xy, IN[3].xyyy
>  5: MOV TEMP[1].w, IN[3].wwww
>  6: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  7: MUL_SAT TEMP[2], TEMP[0], IMM[0].xxxy
>  8: MUL TEMP[1].xyz, TEMP[1], TEMP[2]
>  9: MOV TEMP[1].xyz, TEMP[1].xyzx
> 10: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
> 11: MOV TEMP[1].w, TEMP[0].wwww
> 12: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
> 13: MOV TEMP[1].w, TEMP[0]
> 14: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[2].xxxx, CONST[2].yyyy
> 15: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
> 16: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
> 17: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 18: MOV OUT[0], TEMP[1]
> 19: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %46 = fdiv float %40, %42
>  %47 = fdiv float %41, %42
>  %48 = bitcast float %46 to i32
>  %49 = bitcast float %47 to i32
>  %50 = insertelement <2 x i32> undef, i32 %48, i32 0
>  %51 = insertelement <2 x i32> %50, i32 %49, i32 1
>  %52 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %51, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = fmul float %53, %35
>  %58 = fmul float %54, %36
>  %59 = fmul float %55, %37
>  %60 = fmul float %56, %38
>  %61 = fdiv float %43, %45
>  %62 = fdiv float %44, %45
>  %63 = bitcast float %61 to i32
>  %64 = bitcast float %62 to i32
>  %65 = insertelement <2 x i32> undef, i32 %63, i32 0
>  %66 = insertelement <2 x i32> %65, i32 %64, i32 1
>  %67 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %66, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %68 = extractelement <4 x float> %67, i32 0
>  %69 = extractelement <4 x float> %67, i32 1
>  %70 = extractelement <4 x float> %67, i32 2
>  %71 = fmul float %57, 2.000000e+00
>  %72 = fmul float %58, 2.000000e+00
>  %73 = fmul float %59, 2.000000e+00
>  %74 = fmul float %60, 1.000000e+00
>  %75 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %76 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %73, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00)
>  %79 = fmul float %68, %75
>  %80 = fmul float %69, %76
>  %81 = fmul float %70, %77
>  %82 = fmul float %57, 2.000000e+00
>  %83 = fmul float %58, 2.000000e+00
>  %84 = fmul float %59, 2.000000e+00
>  %85 = fmul float %60, 1.000000e+00
>  %86 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %87 = call float @llvm.AMDIL.clamp.(float %83, float 0.000000e+00, float 1.000000e+00)
>  %88 = call float @llvm.AMDIL.clamp.(float %84, float 0.000000e+00, float 1.000000e+00)
>  %89 = call float @llvm.AMDIL.clamp.(float %85, float 0.000000e+00, float 1.000000e+00)
>  %90 = fmul float %79, 2.000000e+00
>  %91 = fmul float %80, 2.000000e+00
>  %92 = fmul float %81, 2.000000e+00
>  %93 = fmul float %89, 1.000000e+00
>  %94 = call float @llvm.AMDIL.clamp.(float %90, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %91, float 0.000000e+00, float 1.000000e+00)
>  %96 = call float @llvm.AMDIL.clamp.(float %92, float 0.000000e+00, float 1.000000e+00)
>  %97 = call float @llvm.AMDIL.clamp.(float %93, float 0.000000e+00, float 1.000000e+00)
>  %98 = fmul float %39, %22
>  %99 = fadd float %98, %23
>  %100 = call float @llvm.AMDIL.clamp.(float %99, float 0.000000e+00, float 1.000000e+00)
>  %101 = fsub float -0.000000e+00, %100
>  %102 = fadd float 1.000000e+00, %101
>  %103 = fmul float %24, %102
>  %104 = fmul float %25, %102
>  %105 = fmul float %26, %102
>  %106 = fmul float %94, %100
>  %107 = fadd float %106, %103
>  %108 = fmul float %95, %100
>  %109 = fadd float %108, %104
>  %110 = fmul float %96, %100
>  %111 = fadd float %110, %105
>  %112 = call i32 @llvm.SI.packf16(float %107, float %109)
>  %113 = bitcast i32 %112 to float
>  %114 = call i32 @llvm.SI.packf16(float %111, float %97)
>  %115 = bitcast i32 %114 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %113, float %115, float %113, float %115)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180100
>c8190101
>bf8c0770
>100e0d03
>d2820006
>041e0d03
>d2060809
>02010106
>c8180d00
>c8190d01
>c81c0f00
>c81d0f01
>7e105507
>100e1106
>c8280c00
>c8290c01
>100c110a
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430606
>bf8c0770
>10141307
>d2820009
>042a1307
>d206080b
>02010109
>c8240400
>c8250401
>c0800100
>bf8c007f
>c2020108
>c2028109
>bf8c007f
>7e140205
>d2820009
>04280909
>d2060809
>02010109
>081412f2
>c202010d
>bf8c007f
>10181404
>d282000b
>0432130b
>c8300000
>c8310001
>101a1902
>d282000c
>04361902
>d206080c
>0201010c
>101a1906
>d282000c
>04361906
>d206080c
>0201010c
>c202010c
>bf8c007f
>101a1404
>d282000c
>0436130c
>5e16170c
>c8300200
>c8310201
>101a1904
>d282000c
>04361904
>d206080c
>0201010c
>101a1908
>d2820006
>04361908
>d2060806
>02010106
>c200010e
>bf8c007f
>100e1400
>d2820006
>041e1306
>c81c0300
>c81d0301
>10000f05
>d2060800
>02010100
>d2060800
>02010100
>5e000106
>f8001c0f
>000b000b
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[1].xyz, TEMP[0], CONST[2]
>  4: MOV TEMP[1].xyz, TEMP[1].xyzx
>  5: MOV TEMP[1].w, TEMP[0].wwww
>  6: MUL TEMP[1].xyz, IN[0].wwww, TEMP[1]
>  7: MOV TEMP[0].w, TEMP[0].wwww
>  8: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  9: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].xxxx
> 10: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
> 11: MAD TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 12: MOV OUT[0], TEMP[0]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %30 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %31 = load <32 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %39 = fdiv float %36, %38
>  %40 = fdiv float %37, %38
>  %41 = bitcast float %39 to i32
>  %42 = bitcast float %40 to i32
>  %43 = insertelement <2 x i32> undef, i32 %41, i32 0
>  %44 = insertelement <2 x i32> %43, i32 %42, i32 1
>  %45 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %44, <32 x i8> %31, <16 x i8> %33, i32 2)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = fmul float %46, %24
>  %51 = fmul float %47, %25
>  %52 = fmul float %48, %26
>  %53 = fmul float %34, %50
>  %54 = fmul float %34, %51
>  %55 = fmul float %34, %52
>  %56 = fmul float %35, %22
>  %57 = fadd float %56, %23
>  %58 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %59 = fsub float -0.000000e+00, %58
>  %60 = fadd float 1.000000e+00, %59
>  %61 = fmul float %27, %60
>  %62 = fmul float %28, %60
>  %63 = fmul float %29, %60
>  %64 = fmul float %53, %58
>  %65 = fadd float %64, %61
>  %66 = fmul float %54, %58
>  %67 = fadd float %66, %62
>  %68 = fmul float %55, %58
>  %69 = fadd float %68, %63
>  %70 = call i32 @llvm.SI.packf16(float %65, float %67)
>  %71 = bitcast i32 %70 to float
>  %72 = call i32 @llvm.SI.packf16(float %69, float %49)
>  %73 = bitcast i32 %72 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %71, float %73, float %71, float %73)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c0800100
>bf8c0070
>c202010a
>bf8c007f
>100e0804
>c8180300
>c8190301
>100e0f06
>c8200400
>c8210401
>c2020104
>c2028105
>bf8c007f
>7e000205
>d2820000
>04000908
>d2060800
>02010100
>080200f2
>c202010e
>bf8c007f
>10100204
>d2820007
>04220107
>5e0e0b07
>c2020109
>bf8c007f
>10100604
>10101106
>c202010d
>bf8c007f
>10120204
>d2820008
>04260108
>c2020108
>bf8c007f
>10040404
>10040506
>c200010c
>bf8c007f
>10020200
>d2820000
>04060102
>5e001100
>f8001c0f
>07000700
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..7]
>DCL CONST[9..12]
>DCL TEMP[0..1]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MUL TEMP[1], IN[2].xxxx, CONST[9]
>  9: MAD TEMP[1], IN[2].yyyy, CONST[10], TEMP[1]
> 10: MAD TEMP[1], IN[2].zzzz, CONST[11], TEMP[1]
> 11: MAD OUT[3], IN[2].wwww, CONST[12], TEMP[1]
> 12: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = extractelement <4 x float> %56, i32 3
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 0
>  %65 = extractelement <4 x float> %63, i32 1
>  %66 = extractelement <4 x float> %63, i32 2
>  %67 = extractelement <4 x float> %63, i32 3
>  %68 = fmul float %50, %11
>  %69 = fmul float %50, %12
>  %70 = fmul float %50, %13
>  %71 = fmul float %50, %14
>  %72 = fmul float %51, %15
>  %73 = fadd float %72, %68
>  %74 = fmul float %51, %16
>  %75 = fadd float %74, %69
>  %76 = fmul float %51, %17
>  %77 = fadd float %76, %70
>  %78 = fmul float %51, %18
>  %79 = fadd float %78, %71
>  %80 = fmul float %52, %19
>  %81 = fadd float %80, %73
>  %82 = fmul float %52, %20
>  %83 = fadd float %82, %75
>  %84 = fmul float %52, %21
>  %85 = fadd float %84, %77
>  %86 = fmul float %52, %22
>  %87 = fadd float %86, %79
>  %88 = fmul float %53, %23
>  %89 = fadd float %88, %81
>  %90 = fmul float %53, %24
>  %91 = fadd float %90, %83
>  %92 = fmul float %53, %25
>  %93 = fadd float %92, %85
>  %94 = fmul float %53, %26
>  %95 = fadd float %94, %87
>  %96 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %97 = call float @llvm.AMDIL.clamp.(float %58, float 0.000000e+00, float 1.000000e+00)
>  %98 = call float @llvm.AMDIL.clamp.(float %59, float 0.000000e+00, float 1.000000e+00)
>  %99 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %100 = fmul float %50, %27
>  %101 = fmul float %51, %28
>  %102 = fadd float %100, %101
>  %103 = fmul float %52, %29
>  %104 = fadd float %102, %103
>  %105 = fmul float %53, %30
>  %106 = fadd float %104, %105
>  %107 = call float @fabs(float %106)
>  %108 = fmul float %64, %31
>  %109 = fmul float %64, %32
>  %110 = fmul float %64, %33
>  %111 = fmul float %64, %34
>  %112 = fmul float %65, %35
>  %113 = fadd float %112, %108
>  %114 = fmul float %65, %36
>  %115 = fadd float %114, %109
>  %116 = fmul float %65, %37
>  %117 = fadd float %116, %110
>  %118 = fmul float %65, %38
>  %119 = fadd float %118, %111
>  %120 = fmul float %66, %39
>  %121 = fadd float %120, %113
>  %122 = fmul float %66, %40
>  %123 = fadd float %122, %115
>  %124 = fmul float %66, %41
>  %125 = fadd float %124, %117
>  %126 = fmul float %66, %42
>  %127 = fadd float %126, %119
>  %128 = fmul float %67, %43
>  %129 = fadd float %128, %121
>  %130 = fmul float %67, %44
>  %131 = fadd float %130, %123
>  %132 = fmul float %67, %45
>  %133 = fadd float %132, %125
>  %134 = fmul float %67, %46
>  %135 = fadd float %134, %127
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %96, float %97, float %98, float %99)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %107, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %129, float %131, float %133, float %135)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %89, float %91, float %93, float %95)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>c2020127
>bf8c0070
>10000a04
>c202012b
>bf8c007f
>d2820000
>04000906
>c202012f
>bf8c007f
>d2820000
>04000907
>c2020133
>bf8c007f
>d2820000
>04000908
>c2020126
>bf8c007f
>10120a04
>c202012a
>bf8c007f
>d2820009
>04240906
>c202012e
>bf8c007f
>d2820009
>04240907
>c2020132
>bf8c007f
>d2820009
>04240908
>c2020125
>bf8c007f
>10140a04
>c2020129
>bf8c007f
>d282000a
>04280906
>c202012d
>bf8c007f
>d282000a
>04280907
>c2020131
>bf8c007f
>d282000a
>04280908
>c2020124
>bf8c007f
>10160a04
>c2020128
>bf8c007f
>d282000b
>042c0906
>c202012c
>bf8c007f
>d282000b
>042c0907
>c2020130
>bf8c007f
>d2820005
>042c0908
>f800022f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL IN[4], GENERIC[2], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL CONST[3..9]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0].xyz, TEMP[0], SAMP[2], 2D
>  3: MOV TEMP[0].xyz, TEMP[0].xyzx
>  4: MOV TEMP[1].xy, IN[3].xyyy
>  5: MOV TEMP[1].w, IN[3].wwww
>  6: TXP TEMP[1].w, TEMP[1], SAMP[1], 2D
>  7: MOV TEMP[0].w, TEMP[1].wwww
>  8: ADD TEMP[2].x, IMM[0].xxxx, -TEMP[1].wwww
>  9: TXP TEMP[3], IN[4], SAMP[0], CUBE
> 10: MUL TEMP[3], TEMP[3], TEMP[1].wwww
> 11: MAD TEMP[0].xyz, TEMP[0], TEMP[2].xxxx, TEMP[3]
> 12: MOV TEMP[0].xyz, TEMP[0].xyzx
> 13: MOV TEMP[0].w, TEMP[1].wwww
> 14: ADD TEMP[2].x, IMM[0].xxxx, -IN[0].wwww
> 15: MUL TEMP[0], TEMP[0], IN[0].wwww
> 16: MAD TEMP[0].xyz, CONST[7], TEMP[2].xxxx, TEMP[0]
> 17: MOV TEMP[1].w, TEMP[1].wwww
> 18: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[3].xxxx, CONST[3].yyyy
> 19: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].xxxx
> 20: MUL TEMP[3].xyz, CONST[8].xyzz, TEMP[3].xxxx
> 21: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 22: MOV OUT[0], TEMP[1]
> 23: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 116)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 120)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 136)
>  %30 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %31 = load <32 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0
>  %34 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %35 = load <32 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
>  %38 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %39 = load <32 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0
>  %42 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %46 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %47 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %48 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %49 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %50 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %51 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %52 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
>  %53 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %54 = fdiv float %44, %46
>  %55 = fdiv float %45, %46
>  %56 = bitcast float %54 to i32
>  %57 = bitcast float %55 to i32
>  %58 = insertelement <2 x i32> undef, i32 %56, i32 0
>  %59 = insertelement <2 x i32> %58, i32 %57, i32 1
>  %60 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %59, <32 x i8> %39, <16 x i8> %41, i32 2)
>  %61 = extractelement <4 x float> %60, i32 0
>  %62 = extractelement <4 x float> %60, i32 1
>  %63 = extractelement <4 x float> %60, i32 2
>  %64 = fdiv float %47, %49
>  %65 = fdiv float %48, %49
>  %66 = bitcast float %64 to i32
>  %67 = bitcast float %65 to i32
>  %68 = insertelement <2 x i32> undef, i32 %66, i32 0
>  %69 = insertelement <2 x i32> %68, i32 %67, i32 1
>  %70 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %69, <32 x i8> %35, <16 x i8> %37, i32 2)
>  %71 = extractelement <4 x float> %70, i32 3
>  %72 = fsub float -0.000000e+00, %71
>  %73 = fadd float 1.000000e+00, %72
>  %74 = fdiv float %50, %53
>  %75 = fdiv float %51, %53
>  %76 = fdiv float %52, %53
>  %77 = insertelement <4 x float> undef, float %74, i32 0
>  %78 = insertelement <4 x float> %77, float %75, i32 1
>  %79 = insertelement <4 x float> %78, float %76, i32 2
>  %80 = insertelement <4 x float> %79, float 1.000000e+00, i32 3
>  %81 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %80)
>  %82 = extractelement <4 x float> %81, i32 0
>  %83 = extractelement <4 x float> %81, i32 1
>  %84 = extractelement <4 x float> %81, i32 2
>  %85 = extractelement <4 x float> %81, i32 3
>  %86 = call float @fabs(float %84)
>  %87 = fdiv float 1.000000e+00, %86
>  %88 = fmul float %82, %87
>  %89 = fadd float %88, 1.500000e+00
>  %90 = fmul float %83, %87
>  %91 = fadd float %90, 1.500000e+00
>  %92 = bitcast float %91 to i32
>  %93 = bitcast float %89 to i32
>  %94 = bitcast float %85 to i32
>  %95 = insertelement <4 x i32> undef, i32 %92, i32 0
>  %96 = insertelement <4 x i32> %95, i32 %93, i32 1
>  %97 = insertelement <4 x i32> %96, i32 %94, i32 2
>  %98 = insertelement <4 x i32> %97, i32 undef, i32 3
>  %99 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %98, <32 x i8> %31, <16 x i8> %33, i32 4)
>  %100 = extractelement <4 x float> %99, i32 0
>  %101 = extractelement <4 x float> %99, i32 1
>  %102 = extractelement <4 x float> %99, i32 2
>  %103 = fmul float %100, %71
>  %104 = fmul float %101, %71
>  %105 = fmul float %102, %71
>  %106 = fmul float %61, %73
>  %107 = fadd float %106, %103
>  %108 = fmul float %62, %73
>  %109 = fadd float %108, %104
>  %110 = fmul float %63, %73
>  %111 = fadd float %110, %105
>  %112 = fsub float -0.000000e+00, %42
>  %113 = fadd float 1.000000e+00, %112
>  %114 = fmul float %107, %42
>  %115 = fmul float %109, %42
>  %116 = fmul float %111, %42
>  %117 = fmul float %24, %113
>  %118 = fadd float %117, %114
>  %119 = fmul float %25, %113
>  %120 = fadd float %119, %115
>  %121 = fmul float %26, %113
>  %122 = fadd float %121, %116
>  %123 = fmul float %43, %22
>  %124 = fadd float %123, %23
>  %125 = call float @llvm.AMDIL.clamp.(float %124, float 0.000000e+00, float 1.000000e+00)
>  %126 = fsub float -0.000000e+00, %125
>  %127 = fadd float 1.000000e+00, %126
>  %128 = fmul float %27, %127
>  %129 = fmul float %28, %127
>  %130 = fmul float %29, %127
>  %131 = fmul float %118, %125
>  %132 = fadd float %131, %128
>  %133 = fmul float %120, %125
>  %134 = fadd float %133, %129
>  %135 = fmul float %122, %125
>  %136 = fadd float %135, %130
>  %137 = call i32 @llvm.SI.packf16(float %132, float %134)
>  %138 = bitcast i32 %137 to float
>  %139 = call i32 @llvm.SI.packf16(float %136, float %71)
>  %140 = bitcast i32 %139 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %138, float %140, float %138, float %140)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8081100
>c8091101
>c80c1300
>c80d1301
>7e0c5503
>10060d02
>c81c1000
>c81d1001
>10040d07
>c81c1200
>c81d1201
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430207
>c8140d00
>c8150d01
>c8180f00
>c8190f01
>7e0e5506
>100c0f05
>c8200c00
>c8210c01
>100a0f08
>c0840304
>c0c60508
>bf8c0070
>f0800800
>00430505
>bf8c0770
>10140b03
>c8180900
>c8190901
>c81c0b00
>c81d0b01
>7e105507
>100e1106
>c8240800
>c8250801
>100c1109
>c0840308
>c0c60510
>bf8c007f
>f0800700
>00430606
>08120af2
>bf8c0770
>d282000b
>042a1307
>c8280300
>c8290301
>1018150b
>081614f2
>c0800100
>bf8c007f
>c202011d
>bf8c007f
>d282000c
>04321604
>c8340400
>c8350401
>c202010c
>c202810d
>bf8c007f
>7e000205
>d2820000
>0400090d
>d2060800
>02010100
>080200f2
>c2020121
>bf8c007f
>101a0204
>d282000c
>0436010c
>101a0b02
>d282000d
>04361306
>101a150d
>c202011c
>bf8c007f
>d282000d
>04361604
>c2020120
>bf8c007f
>101c0204
>d282000d
>043a010d
>5e18190d
>10040b04
>d2820002
>040a1308
>10041502
>c202011e
>bf8c007f
>d2820002
>040a1604
>c2000122
>bf8c007f
>10020200
>d2820000
>04060102
>5e000b00
>f8001c0f
>000c000c
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL OUT[5], GENERIC[2]
>DCL CONST[0..7]
>DCL CONST[9..28]
>DCL TEMP[0..5]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MUL TEMP[1], IN[2].xxxx, CONST[9]
>  9: MAD TEMP[1], IN[2].yyyy, CONST[10], TEMP[1]
> 10: MAD TEMP[1], IN[2].zzzz, CONST[11], TEMP[1]
> 11: MAD OUT[3], IN[2].wwww, CONST[12], TEMP[1]
> 12: MUL TEMP[1], IN[3].xxxx, CONST[13]
> 13: MAD TEMP[1], IN[3].yyyy, CONST[14], TEMP[1]
> 14: MAD TEMP[1], IN[3].zzzz, CONST[15], TEMP[1]
> 15: MAD OUT[4], IN[3].wwww, CONST[16], TEMP[1]
> 16: DP3 TEMP[2].x, CONST[17], CONST[18]
> 17: DP3 TEMP[2].y, CONST[17], CONST[19]
> 18: DP3 TEMP[2].z, CONST[17], CONST[20]
> 19: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 20: RSQ TEMP[3].x, |TEMP[3]|
> 21: MUL TEMP[2], TEMP[2], TEMP[3].xxxx
> 22: MUL TEMP[3], IN[0].xxxx, CONST[21]
> 23: MAD TEMP[3], IN[0].yyyy, CONST[22], TEMP[3]
> 24: MAD TEMP[3], IN[0].zzzz, CONST[23], TEMP[3]
> 25: MAD TEMP[3], IN[0].wwww, CONST[24], TEMP[3]
> 26: DP3 TEMP[4].x, TEMP[3], TEMP[3]
> 27: RSQ TEMP[4].x, |TEMP[4]|
> 28: MUL TEMP[5], TEMP[3], TEMP[4].xxxx
> 29: DP3 TEMP[4], TEMP[2], TEMP[5]
> 30: ADD TEMP[4], TEMP[4], TEMP[4]
> 31: MAD TEMP[1].xyz, -TEMP[4], TEMP[2], TEMP[5]
> 32: MOV TEMP[1].w, IN[4]
> 33: MUL TEMP[4], TEMP[1].xxxx, CONST[25]
> 34: MAD TEMP[4], TEMP[1].yyyy, CONST[26], TEMP[4]
> 35: MAD TEMP[4], TEMP[1].zzzz, CONST[27], TEMP[4]
> 36: MAD OUT[5], TEMP[1].wwww, CONST[28], TEMP[4]
> 37: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 252)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 268)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 444)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 460)
>  %103 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %104 = load <16 x i8> addrspace(2)* %103, !tbaa !0
>  %105 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %104, i32 0, i32 %5)
>  %106 = extractelement <4 x float> %105, i32 0
>  %107 = extractelement <4 x float> %105, i32 1
>  %108 = extractelement <4 x float> %105, i32 2
>  %109 = extractelement <4 x float> %105, i32 3
>  %110 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %111 = load <16 x i8> addrspace(2)* %110, !tbaa !0
>  %112 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %111, i32 0, i32 %5)
>  %113 = extractelement <4 x float> %112, i32 0
>  %114 = extractelement <4 x float> %112, i32 1
>  %115 = extractelement <4 x float> %112, i32 2
>  %116 = extractelement <4 x float> %112, i32 3
>  %117 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %118 = load <16 x i8> addrspace(2)* %117, !tbaa !0
>  %119 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %118, i32 0, i32 %5)
>  %120 = extractelement <4 x float> %119, i32 0
>  %121 = extractelement <4 x float> %119, i32 1
>  %122 = extractelement <4 x float> %119, i32 2
>  %123 = extractelement <4 x float> %119, i32 3
>  %124 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %125 = load <16 x i8> addrspace(2)* %124, !tbaa !0
>  %126 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %125, i32 0, i32 %5)
>  %127 = extractelement <4 x float> %126, i32 0
>  %128 = extractelement <4 x float> %126, i32 1
>  %129 = extractelement <4 x float> %126, i32 2
>  %130 = extractelement <4 x float> %126, i32 3
>  %131 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %132 = load <16 x i8> addrspace(2)* %131, !tbaa !0
>  %133 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %132, i32 0, i32 %5)
>  %134 = extractelement <4 x float> %133, i32 3
>  %135 = fmul float %106, %11
>  %136 = fmul float %106, %12
>  %137 = fmul float %106, %13
>  %138 = fmul float %106, %14
>  %139 = fmul float %107, %15
>  %140 = fadd float %139, %135
>  %141 = fmul float %107, %16
>  %142 = fadd float %141, %136
>  %143 = fmul float %107, %17
>  %144 = fadd float %143, %137
>  %145 = fmul float %107, %18
>  %146 = fadd float %145, %138
>  %147 = fmul float %108, %19
>  %148 = fadd float %147, %140
>  %149 = fmul float %108, %20
>  %150 = fadd float %149, %142
>  %151 = fmul float %108, %21
>  %152 = fadd float %151, %144
>  %153 = fmul float %108, %22
>  %154 = fadd float %153, %146
>  %155 = fmul float %109, %23
>  %156 = fadd float %155, %148
>  %157 = fmul float %109, %24
>  %158 = fadd float %157, %150
>  %159 = fmul float %109, %25
>  %160 = fadd float %159, %152
>  %161 = fmul float %109, %26
>  %162 = fadd float %161, %154
>  %163 = call float @llvm.AMDIL.clamp.(float %113, float 0.000000e+00, float 1.000000e+00)
>  %164 = call float @llvm.AMDIL.clamp.(float %114, float 0.000000e+00, float 1.000000e+00)
>  %165 = call float @llvm.AMDIL.clamp.(float %115, float 0.000000e+00, float 1.000000e+00)
>  %166 = call float @llvm.AMDIL.clamp.(float %116, float 0.000000e+00, float 1.000000e+00)
>  %167 = fmul float %106, %27
>  %168 = fmul float %107, %28
>  %169 = fadd float %167, %168
>  %170 = fmul float %108, %29
>  %171 = fadd float %169, %170
>  %172 = fmul float %109, %30
>  %173 = fadd float %171, %172
>  %174 = call float @fabs(float %173)
>  %175 = fmul float %120, %31
>  %176 = fmul float %120, %32
>  %177 = fmul float %120, %33
>  %178 = fmul float %120, %34
>  %179 = fmul float %121, %35
>  %180 = fadd float %179, %175
>  %181 = fmul float %121, %36
>  %182 = fadd float %181, %176
>  %183 = fmul float %121, %37
>  %184 = fadd float %183, %177
>  %185 = fmul float %121, %38
>  %186 = fadd float %185, %178
>  %187 = fmul float %122, %39
>  %188 = fadd float %187, %180
>  %189 = fmul float %122, %40
>  %190 = fadd float %189, %182
>  %191 = fmul float %122, %41
>  %192 = fadd float %191, %184
>  %193 = fmul float %122, %42
>  %194 = fadd float %193, %186
>  %195 = fmul float %123, %43
>  %196 = fadd float %195, %188
>  %197 = fmul float %123, %44
>  %198 = fadd float %197, %190
>  %199 = fmul float %123, %45
>  %200 = fadd float %199, %192
>  %201 = fmul float %123, %46
>  %202 = fadd float %201, %194
>  %203 = fmul float %127, %47
>  %204 = fmul float %127, %48
>  %205 = fmul float %127, %49
>  %206 = fmul float %127, %50
>  %207 = fmul float %128, %51
>  %208 = fadd float %207, %203
>  %209 = fmul float %128, %52
>  %210 = fadd float %209, %204
>  %211 = fmul float %128, %53
>  %212 = fadd float %211, %205
>  %213 = fmul float %128, %54
>  %214 = fadd float %213, %206
>  %215 = fmul float %129, %55
>  %216 = fadd float %215, %208
>  %217 = fmul float %129, %56
>  %218 = fadd float %217, %210
>  %219 = fmul float %129, %57
>  %220 = fadd float %219, %212
>  %221 = fmul float %129, %58
>  %222 = fadd float %221, %214
>  %223 = fmul float %130, %59
>  %224 = fadd float %223, %216
>  %225 = fmul float %130, %60
>  %226 = fadd float %225, %218
>  %227 = fmul float %130, %61
>  %228 = fadd float %227, %220
>  %229 = fmul float %130, %62
>  %230 = fadd float %229, %222
>  %231 = fmul float %63, %66
>  %232 = fmul float %64, %67
>  %233 = fadd float %232, %231
>  %234 = fmul float %65, %68
>  %235 = fadd float %233, %234
>  %236 = fmul float %63, %69
>  %237 = fmul float %64, %70
>  %238 = fadd float %237, %236
>  %239 = fmul float %65, %71
>  %240 = fadd float %238, %239
>  %241 = fmul float %63, %72
>  %242 = fmul float %64, %73
>  %243 = fadd float %242, %241
>  %244 = fmul float %65, %74
>  %245 = fadd float %243, %244
>  %246 = fmul float %235, %235
>  %247 = fmul float %240, %240
>  %248 = fadd float %247, %246
>  %249 = fmul float %245, %245
>  %250 = fadd float %248, %249
>  %251 = call float @fabs(float %250)
>  %252 = call float @llvm.AMDGPU.rsq(float %251)
>  %253 = fmul float %235, %252
>  %254 = fmul float %240, %252
>  %255 = fmul float %245, %252
>  %256 = fmul float %106, %75
>  %257 = fmul float %106, %76
>  %258 = fmul float %106, %77
>  %259 = fmul float %107, %78
>  %260 = fadd float %259, %256
>  %261 = fmul float %107, %79
>  %262 = fadd float %261, %257
>  %263 = fmul float %107, %80
>  %264 = fadd float %263, %258
>  %265 = fmul float %108, %81
>  %266 = fadd float %265, %260
>  %267 = fmul float %108, %82
>  %268 = fadd float %267, %262
>  %269 = fmul float %108, %83
>  %270 = fadd float %269, %264
>  %271 = fmul float %109, %84
>  %272 = fadd float %271, %266
>  %273 = fmul float %109, %85
>  %274 = fadd float %273, %268
>  %275 = fmul float %109, %86
>  %276 = fadd float %275, %270
>  %277 = fmul float %272, %272
>  %278 = fmul float %274, %274
>  %279 = fadd float %278, %277
>  %280 = fmul float %276, %276
>  %281 = fadd float %279, %280
>  %282 = call float @fabs(float %281)
>  %283 = call float @llvm.AMDGPU.rsq(float %282)
>  %284 = fmul float %272, %283
>  %285 = fmul float %274, %283
>  %286 = fmul float %276, %283
>  %287 = fmul float %253, %284
>  %288 = fmul float %254, %285
>  %289 = fadd float %288, %287
>  %290 = fmul float %255, %286
>  %291 = fadd float %289, %290
>  %292 = fadd float %291, %291
>  %293 = fadd float %291, %291
>  %294 = fadd float %291, %291
>  %295 = fsub float -0.000000e+00, %292
>  %296 = fmul float %295, %253
>  %297 = fadd float %296, %284
>  %298 = fsub float -0.000000e+00, %293
>  %299 = fmul float %298, %254
>  %300 = fadd float %299, %285
>  %301 = fsub float -0.000000e+00, %294
>  %302 = fmul float %301, %255
>  %303 = fadd float %302, %286
>  %304 = fmul float %297, %87
>  %305 = fmul float %297, %88
>  %306 = fmul float %297, %89
>  %307 = fmul float %297, %90
>  %308 = fmul float %300, %91
>  %309 = fadd float %308, %304
>  %310 = fmul float %300, %92
>  %311 = fadd float %310, %305
>  %312 = fmul float %300, %93
>  %313 = fadd float %312, %306
>  %314 = fmul float %300, %94
>  %315 = fadd float %314, %307
>  %316 = fmul float %303, %95
>  %317 = fadd float %316, %309
>  %318 = fmul float %303, %96
>  %319 = fadd float %318, %311
>  %320 = fmul float %303, %97
>  %321 = fadd float %320, %313
>  %322 = fmul float %303, %98
>  %323 = fadd float %322, %315
>  %324 = fmul float %134, %99
>  %325 = fadd float %324, %317
>  %326 = fmul float %134, %100
>  %327 = fadd float %326, %319
>  %328 = fmul float %134, %101
>  %329 = fadd float %328, %321
>  %330 = fmul float %134, %102
>  %331 = fadd float %330, %323
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %163, float %164, float %165, float %166)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %174, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %196, float %198, float %200, float %202)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %224, float %226, float %228, float %230)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %325, float %327, float %329, float %331)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %156, float %158, float %160, float %162)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
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>c202011a
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>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0840708
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>e00c2000
>80020500
>c2020127
>bf8c0070
>10120a04
>c202012b
>bf8c007f
>d2820009
>04240906
>c202012f
>bf8c007f
>d2820009
>04240907
>c2020133
>bf8c007f
>d2820009
>04240908
>c2020126
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>10140a04
>c202012a
>bf8c007f
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>04280906
>c202012e
>bf8c007f
>d282000a
>04280907
>c2020132
>bf8c007f
>d282000a
>04280908
>c2020125
>bf8c007f
>10160a04
>c2020129
>bf8c007f
>d282000b
>042c0906
>c202012d
>bf8c007f
>d282000b
>042c0907
>c2020131
>bf8c007f
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>c2020124
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>10180a04
>c2020128
>bf8c007f
>d282000c
>04300906
>c202012c
>bf8c007f
>d282000c
>04300907
>c2020130
>bf8c007f
>d2820005
>04300908
>f800022f
>090a0b05
>c084070c
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>e00c2000
>80020500
>c2020137
>bf8c0070
>10120a04
>c202013b
>bf8c007f
>d2820009
>04240906
>c202013f
>bf8c007f
>d2820009
>04240907
>c2020143
>bf8c007f
>d2820009
>04240908
>c2020136
>bf8c007f
>10140a04
>c202013a
>bf8c007f
>d282000a
>04280906
>c202013e
>bf8c007f
>d282000a
>04280907
>c2020142
>bf8c007f
>d282000a
>04280908
>c2020135
>bf8c007f
>10160a04
>c2020139
>bf8c007f
>d282000b
>042c0906
>c202013d
>bf8c007f
>d282000b
>042c0907
>c2020141
>bf8c007f
>d282000b
>042c0908
>c2020134
>bf8c007f
>10180a04
>c2020138
>bf8c007f
>d282000c
>04300906
>c202013c
>bf8c007f
>d282000c
>04300907
>c2020140
>bf8c007f
>d2820005
>04300908
>f800023f
>090a0b05
>c2020155
>bf8c000f
>100a0204
>c2020159
>bf8c007f
>d2820005
>04140902
>c202015d
>bf8c007f
>d2820005
>04140903
>c2020161
>bf8c007f
>d2820005
>04140904
>c2020154
>bf8c007f
>100c0204
>c2020158
>bf8c007f
>d2820006
>04180902
>c202015c
>bf8c007f
>d2820006
>04180903
>c2020160
>bf8c007f
>d2820009
>04180904
>100c1309
>d2820006
>041a0b05
>c2020156
>bf8c007f
>100e0204
>c202015a
>bf8c007f
>d2820007
>041c0902
>c202015e
>bf8c007f
>d2820007
>041c0903
>c2020162
>bf8c007f
>d2820007
>041c0904
>d2820006
>041a0f07
>d2060106
>02010106
>7e105b06
>100c1105
>100a1109
>c2020144
>c202814c
>bf8c007f
>7e120205
>d2100009
>02021204
>c2028145
>c204014d
>bf8c007f
>7e140208
>d2820009
>04261405
>c2040146
>c204814e
>bf8c007f
>7e140209
>d2820009
>04261408
>c2048148
>bf8c007f
>7e140209
>d210000a
>02021404
>c2048149
>bf8c007f
>7e160209
>d282000a
>042a1605
>c204814a
>bf8c007f
>7e160209
>d282000a
>042a1608
>1016150a
>d282000b
>042e1309
>c2048150
>bf8c007f
>7e180209
>d210000c
>02021804
>c2020151
>bf8c007f
>7e1a0204
>d282000c
>04321a05
>c2020152
>bf8c007f
>7e1a0204
>d282000c
>04321a08
>d282000b
>042e190c
>d206010b
>0201010b
>7e165b0b
>1014170a
>101c0b0a
>101a1709
>d2820009
>043a0d0d
>100e1107
>1010170c
>d2820009
>04260f08
>06121309
>10161b09
>080c1706
>10141509
>080a1505
>c2020167
>bf8c007f
>10140a04
>c202016b
>bf8c007f
>d282000a
>04280906
>10101109
>080e1107
>c202016f
>bf8c007f
>d282000c
>04280907
>c0820710
>bf8c007f
>e00c2000
>80010800
>c2020173
>bf8c0070
>d2820000
>0430090b
>c2020166
>bf8c007f
>10180a04
>c202016a
>bf8c007f
>d282000c
>04300906
>c202016e
>bf8c007f
>d282000c
>04300907
>c2020172
>bf8c007f
>d282000c
>0430090b
>c2020165
>bf8c007f
>101a0a04
>c2020169
>bf8c007f
>d282000d
>04340906
>c202016d
>bf8c007f
>d282000d
>04340907
>c2020171
>bf8c007f
>d282000d
>0434090b
>c2020164
>bf8c007f
>100a0a04
>c2020168
>bf8c007f
>d2820005
>04140906
>c202016c
>bf8c007f
>d2820005
>04140907
>c2020170
>bf8c007f
>d2820005
>0414090b
>f800024f
>000c0d05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..7]
>DCL CONST[9..12]
>DCL TEMP[0..1]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: MUL TEMP[1], IN[3].xxxx, CONST[9]
> 10: MAD TEMP[1], IN[3].yyyy, CONST[10], TEMP[1]
> 11: MAD TEMP[1], IN[3].zzzz, CONST[11], TEMP[1]
> 12: MAD OUT[4], IN[3].wwww, CONST[12], TEMP[1]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = extractelement <4 x float> %56, i32 3
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 0
>  %65 = extractelement <4 x float> %63, i32 1
>  %66 = extractelement <4 x float> %63, i32 2
>  %67 = extractelement <4 x float> %63, i32 3
>  %68 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
>  %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %69, i32 0, i32 %5)
>  %71 = extractelement <4 x float> %70, i32 0
>  %72 = extractelement <4 x float> %70, i32 1
>  %73 = extractelement <4 x float> %70, i32 2
>  %74 = extractelement <4 x float> %70, i32 3
>  %75 = fmul float %50, %11
>  %76 = fmul float %50, %12
>  %77 = fmul float %50, %13
>  %78 = fmul float %50, %14
>  %79 = fmul float %51, %15
>  %80 = fadd float %79, %75
>  %81 = fmul float %51, %16
>  %82 = fadd float %81, %76
>  %83 = fmul float %51, %17
>  %84 = fadd float %83, %77
>  %85 = fmul float %51, %18
>  %86 = fadd float %85, %78
>  %87 = fmul float %52, %19
>  %88 = fadd float %87, %80
>  %89 = fmul float %52, %20
>  %90 = fadd float %89, %82
>  %91 = fmul float %52, %21
>  %92 = fadd float %91, %84
>  %93 = fmul float %52, %22
>  %94 = fadd float %93, %86
>  %95 = fmul float %53, %23
>  %96 = fadd float %95, %88
>  %97 = fmul float %53, %24
>  %98 = fadd float %97, %90
>  %99 = fmul float %53, %25
>  %100 = fadd float %99, %92
>  %101 = fmul float %53, %26
>  %102 = fadd float %101, %94
>  %103 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %104 = call float @llvm.AMDIL.clamp.(float %58, float 0.000000e+00, float 1.000000e+00)
>  %105 = call float @llvm.AMDIL.clamp.(float %59, float 0.000000e+00, float 1.000000e+00)
>  %106 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %107 = fmul float %50, %27
>  %108 = fmul float %51, %28
>  %109 = fadd float %107, %108
>  %110 = fmul float %52, %29
>  %111 = fadd float %109, %110
>  %112 = fmul float %53, %30
>  %113 = fadd float %111, %112
>  %114 = call float @fabs(float %113)
>  %115 = fmul float %71, %31
>  %116 = fmul float %71, %32
>  %117 = fmul float %71, %33
>  %118 = fmul float %71, %34
>  %119 = fmul float %72, %35
>  %120 = fadd float %119, %115
>  %121 = fmul float %72, %36
>  %122 = fadd float %121, %116
>  %123 = fmul float %72, %37
>  %124 = fadd float %123, %117
>  %125 = fmul float %72, %38
>  %126 = fadd float %125, %118
>  %127 = fmul float %73, %39
>  %128 = fadd float %127, %120
>  %129 = fmul float %73, %40
>  %130 = fadd float %129, %122
>  %131 = fmul float %73, %41
>  %132 = fadd float %131, %124
>  %133 = fmul float %73, %42
>  %134 = fadd float %133, %126
>  %135 = fmul float %74, %43
>  %136 = fadd float %135, %128
>  %137 = fmul float %74, %44
>  %138 = fadd float %137, %130
>  %139 = fmul float %74, %45
>  %140 = fadd float %139, %132
>  %141 = fmul float %74, %46
>  %142 = fadd float %141, %134
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %103, float %104, float %105, float %106)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %114, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %64, float %65, float %66, float %67)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %136, float %138, float %140, float %142)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %96, float %98, float %100, float %102)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0840708
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800022f
>08070605
>c082070c
>bf8c000f
>e00c2000
>80010500
>c2020127
>bf8c0070
>10000a04
>c202012b
>bf8c007f
>d2820000
>04000906
>c202012f
>bf8c007f
>d2820000
>04000907
>c2020133
>bf8c007f
>d2820000
>04000908
>c2020126
>bf8c007f
>10120a04
>c202012a
>bf8c007f
>d2820009
>04240906
>c202012e
>bf8c007f
>d2820009
>04240907
>c2020132
>bf8c007f
>d2820009
>04240908
>c2020125
>bf8c007f
>10140a04
>c2020129
>bf8c007f
>d282000a
>04280906
>c202012d
>bf8c007f
>d282000a
>04280907
>c2020131
>bf8c007f
>d282000a
>04280908
>c2020124
>bf8c007f
>10160a04
>c2020128
>bf8c007f
>d282000b
>042c0906
>c202012c
>bf8c007f
>d282000b
>042c0907
>c2020130
>bf8c007f
>d2820005
>042c0908
>f800023f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = fmul float %34, %11
>  %53 = fmul float %34, %12
>  %54 = fmul float %34, %13
>  %55 = fmul float %34, %14
>  %56 = fmul float %35, %15
>  %57 = fadd float %56, %52
>  %58 = fmul float %35, %16
>  %59 = fadd float %58, %53
>  %60 = fmul float %35, %17
>  %61 = fadd float %60, %54
>  %62 = fmul float %35, %18
>  %63 = fadd float %62, %55
>  %64 = fmul float %36, %19
>  %65 = fadd float %64, %57
>  %66 = fmul float %36, %20
>  %67 = fadd float %66, %59
>  %68 = fmul float %36, %21
>  %69 = fadd float %68, %61
>  %70 = fmul float %36, %22
>  %71 = fadd float %70, %63
>  %72 = fmul float %37, %23
>  %73 = fadd float %72, %65
>  %74 = fmul float %37, %24
>  %75 = fadd float %74, %67
>  %76 = fmul float %37, %25
>  %77 = fadd float %76, %69
>  %78 = fmul float %37, %26
>  %79 = fadd float %78, %71
>  %80 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %81 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %82 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %83 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %84 = fmul float %34, %27
>  %85 = fmul float %35, %28
>  %86 = fadd float %84, %85
>  %87 = fmul float %36, %29
>  %88 = fadd float %86, %87
>  %89 = fmul float %37, %30
>  %90 = fadd float %88, %89
>  %91 = call float @fabs(float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %80, float %81, float %82, float %83)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %91, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %73, float %75, float %77, float %79)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..3]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  5: MOV TEMP[1].w, TEMP[0]
>  6: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  7: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
>  8: MUL TEMP[3].xyz, CONST[2].xyzz, TEMP[3].xxxx
>  9: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 10: MOV OUT[0], TEMP[1]
> 11: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %39 = fdiv float %36, %38
>  %40 = fdiv float %37, %38
>  %41 = bitcast float %39 to i32
>  %42 = bitcast float %40 to i32
>  %43 = insertelement <2 x i32> undef, i32 %41, i32 0
>  %44 = insertelement <2 x i32> %43, i32 %42, i32 1
>  %45 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %44, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = fmul float %46, %31
>  %51 = fmul float %47, %32
>  %52 = fmul float %48, %33
>  %53 = fmul float %49, %34
>  %54 = fmul float %50, 2.000000e+00
>  %55 = fmul float %51, 2.000000e+00
>  %56 = fmul float %52, 2.000000e+00
>  %57 = fmul float %53, 1.000000e+00
>  %58 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %59 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %60 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
>  %61 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %62 = fmul float %35, %22
>  %63 = fadd float %62, %23
>  %64 = call float @llvm.AMDIL.clamp.(float %63, float 0.000000e+00, float 1.000000e+00)
>  %65 = fsub float -0.000000e+00, %64
>  %66 = fadd float 1.000000e+00, %65
>  %67 = fmul float %24, %66
>  %68 = fmul float %25, %66
>  %69 = fmul float %26, %66
>  %70 = fmul float %58, %64
>  %71 = fadd float %70, %67
>  %72 = fmul float %59, %64
>  %73 = fadd float %72, %68
>  %74 = fmul float %60, %64
>  %75 = fadd float %74, %69
>  %76 = fcmp ugt float %61, 0.000000e+00
>  %77 = sext i1 %76 to i32
>  %78 = trunc i32 %77 to i1
>  %79 = select i1 %78, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %79)
>  %80 = call i32 @llvm.SI.packf16(float %71, float %73)
>  %81 = bitcast i32 %80 to float
>  %82 = call i32 @llvm.SI.packf16(float %75, float %61)
>  %83 = bitcast i32 %82 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %81, float %83, float %81, float %83)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>d2060806
>02010106
>d0080002
>02010106
>d2000007
>0009e4f3
>7c260e80
>c81c0100
>c81d0101
>10100f03
>d2820007
>04220f03
>d2060809
>02010107
>c81c0400
>c81d0401
>c0800100
>bf8c007f
>c2020104
>c2028105
>bf8c007f
>7e100205
>d2820007
>04200907
>d2060807
>02010107
>08100ef2
>c2020109
>bf8c007f
>10141004
>d2820009
>042a0f09
>c8280000
>c8290001
>10161502
>d282000a
>042e1502
>d206080a
>0201010a
>c2020108
>bf8c007f
>10161004
>d282000a
>042e0f0a
>5e12130a
>c8280200
>c8290201
>10001504
>d2820000
>04021504
>d2060800
>02010100
>c200010a
>bf8c007f
>10021000
>d2820000
>04060f00
>5e000d00
>f8001c0f
>00090009
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..3]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  5: MOV TEMP[1].w, TEMP[0]
>  6: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  7: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
>  8: MUL TEMP[3].xyz, CONST[2].xyzz, TEMP[3].xxxx
>  9: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 10: MOV OUT[0], TEMP[1]
> 11: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %39 = fdiv float %36, %38
>  %40 = fdiv float %37, %38
>  %41 = bitcast float %39 to i32
>  %42 = bitcast float %40 to i32
>  %43 = insertelement <2 x i32> undef, i32 %41, i32 0
>  %44 = insertelement <2 x i32> %43, i32 %42, i32 1
>  %45 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %44, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = fmul float %46, %31
>  %51 = fmul float %47, %32
>  %52 = fmul float %48, %33
>  %53 = fmul float %49, %34
>  %54 = fmul float %50, 2.000000e+00
>  %55 = fmul float %51, 2.000000e+00
>  %56 = fmul float %52, 2.000000e+00
>  %57 = fmul float %53, 1.000000e+00
>  %58 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
>  %59 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %60 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
>  %61 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %62 = fmul float %35, %22
>  %63 = fadd float %62, %23
>  %64 = call float @llvm.AMDIL.clamp.(float %63, float 0.000000e+00, float 1.000000e+00)
>  %65 = fsub float -0.000000e+00, %64
>  %66 = fadd float 1.000000e+00, %65
>  %67 = fmul float %24, %66
>  %68 = fmul float %25, %66
>  %69 = fmul float %26, %66
>  %70 = fmul float %58, %64
>  %71 = fadd float %70, %67
>  %72 = fmul float %59, %64
>  %73 = fadd float %72, %68
>  %74 = fmul float %60, %64
>  %75 = fadd float %74, %69
>  %76 = fcmp ugt float %61, 0x3FD9191920000000
>  %77 = sext i1 %76 to i32
>  %78 = trunc i32 %77 to i1
>  %79 = select i1 %78, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %79)
>  %80 = call i32 @llvm.SI.packf16(float %71, float %73)
>  %81 = bitcast i32 %80 to float
>  %82 = call i32 @llvm.SI.packf16(float %75, float %61)
>  %83 = bitcast i32 %82 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %81, float %83, float %81, float %83)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>d2060806
>02010106
>7e0e02ff
>3ec8c8c9
>d0080002
>02020f06
>d2000007
>0009e4f3
>7c260e80
>c81c0100
>c81d0101
>10100f03
>d2820007
>04220f03
>d2060809
>02010107
>c81c0400
>c81d0401
>c0800100
>bf8c007f
>c2020104
>c2028105
>bf8c007f
>7e100205
>d2820007
>04200907
>d2060807
>02010107
>08100ef2
>c2020109
>bf8c007f
>10141004
>d2820009
>042a0f09
>c8280000
>c8290001
>10161502
>d282000a
>042e1502
>d206080a
>0201010a
>c2020108
>bf8c007f
>10161004
>d282000a
>042e0f0a
>5e12130a
>c8280200
>c8290201
>10001504
>d2820000
>04021504
>d2060800
>02010100
>c200010a
>bf8c007f
>10021000
>d2820000
>04060f00
>5e000d00
>f8001c0f
>00090009
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MOV TEMP[1].xy, IN[3].xyyy
>  4: MOV TEMP[1].w, IN[3].wwww
>  5: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  6: MUL TEMP[1].xyz, TEMP[1], TEMP[0]
>  7: MOV TEMP[1].xyz, TEMP[1].xyzx
>  8: MOV TEMP[1].w, TEMP[0].wwww
>  9: MUL TEMP[1].xyz, IN[0], TEMP[1]
> 10: MOV TEMP[1].xyz, TEMP[1].xyzx
> 11: MOV TEMP[1].w, TEMP[0].wwww
> 12: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
> 13: MOV TEMP[1].w, TEMP[0]
> 14: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[2].xxxx, CONST[2].yyyy
> 15: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
> 16: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
> 17: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 18: MOV OUT[0], TEMP[1]
> 19: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %45 = fdiv float %39, %41
>  %46 = fdiv float %40, %41
>  %47 = bitcast float %45 to i32
>  %48 = bitcast float %46 to i32
>  %49 = insertelement <2 x i32> undef, i32 %47, i32 0
>  %50 = insertelement <2 x i32> %49, i32 %48, i32 1
>  %51 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %50, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %52 = extractelement <4 x float> %51, i32 0
>  %53 = extractelement <4 x float> %51, i32 1
>  %54 = extractelement <4 x float> %51, i32 2
>  %55 = extractelement <4 x float> %51, i32 3
>  %56 = fdiv float %42, %44
>  %57 = fdiv float %43, %44
>  %58 = bitcast float %56 to i32
>  %59 = bitcast float %57 to i32
>  %60 = insertelement <2 x i32> undef, i32 %58, i32 0
>  %61 = insertelement <2 x i32> %60, i32 %59, i32 1
>  %62 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %61, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = extractelement <4 x float> %62, i32 1
>  %65 = extractelement <4 x float> %62, i32 2
>  %66 = fmul float %63, %52
>  %67 = fmul float %64, %53
>  %68 = fmul float %65, %54
>  %69 = fmul float %35, %66
>  %70 = fmul float %36, %67
>  %71 = fmul float %37, %68
>  %72 = fmul float %69, 2.000000e+00
>  %73 = fmul float %70, 2.000000e+00
>  %74 = fmul float %71, 2.000000e+00
>  %75 = fmul float %55, 1.000000e+00
>  %76 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %73, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %75, float 0.000000e+00, float 1.000000e+00)
>  %80 = fmul float %38, %22
>  %81 = fadd float %80, %23
>  %82 = call float @llvm.AMDIL.clamp.(float %81, float 0.000000e+00, float 1.000000e+00)
>  %83 = fsub float -0.000000e+00, %82
>  %84 = fadd float 1.000000e+00, %83
>  %85 = fmul float %24, %84
>  %86 = fmul float %25, %84
>  %87 = fmul float %26, %84
>  %88 = fmul float %76, %82
>  %89 = fadd float %88, %85
>  %90 = fmul float %77, %82
>  %91 = fadd float %90, %86
>  %92 = fmul float %78, %82
>  %93 = fadd float %92, %87
>  %94 = call i32 @llvm.SI.packf16(float %89, float %91)
>  %95 = bitcast i32 %94 to float
>  %96 = call i32 @llvm.SI.packf16(float %93, float %79)
>  %97 = bitcast i32 %96 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %95, float %97, float %95, float %97)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180d00
>c8190d01
>c81c0f00
>c81d0f01
>7e105507
>100e1106
>c8240c00
>c8250c01
>100c1109
>c0840300
>c0c60500
>bf8c0070
>f0800700
>00430606
>bf8c0770
>10120707
>c8280100
>c8290101
>1016130a
>d2820009
>042e130a
>d206080b
>02010109
>c8240400
>c8250401
>c0800100
>bf8c007f
>c2020108
>c2028109
>bf8c007f
>7e140205
>d2820009
>04280909
>d2060809
>02010109
>081412f2
>c202010d
>bf8c007f
>10181404
>d282000b
>0432130b
>10180506
>c8340000
>c8350001
>101c190d
>d282000c
>043a190d
>d206080c
>0201010c
>c202010c
>bf8c007f
>101a1404
>d282000c
>0436130c
>5e16170c
>100c0908
>c81c0200
>c81d0201
>10000d07
>d2820000
>04020d07
>d2060800
>02010100
>c200010e
>bf8c007f
>10021400
>d2820000
>04061300
>d2060801
>02010105
>5e000300
>f8001c0f
>000b000b
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: MOV OUT[4], IN[3]
> 10: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %53 = load <16 x i8> addrspace(2)* %52, !tbaa !0
>  %54 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %53, i32 0, i32 %5)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %58 = extractelement <4 x float> %54, i32 3
>  %59 = fmul float %34, %11
>  %60 = fmul float %34, %12
>  %61 = fmul float %34, %13
>  %62 = fmul float %34, %14
>  %63 = fmul float %35, %15
>  %64 = fadd float %63, %59
>  %65 = fmul float %35, %16
>  %66 = fadd float %65, %60
>  %67 = fmul float %35, %17
>  %68 = fadd float %67, %61
>  %69 = fmul float %35, %18
>  %70 = fadd float %69, %62
>  %71 = fmul float %36, %19
>  %72 = fadd float %71, %64
>  %73 = fmul float %36, %20
>  %74 = fadd float %73, %66
>  %75 = fmul float %36, %21
>  %76 = fadd float %75, %68
>  %77 = fmul float %36, %22
>  %78 = fadd float %77, %70
>  %79 = fmul float %37, %23
>  %80 = fadd float %79, %72
>  %81 = fmul float %37, %24
>  %82 = fadd float %81, %74
>  %83 = fmul float %37, %25
>  %84 = fadd float %83, %76
>  %85 = fmul float %37, %26
>  %86 = fadd float %85, %78
>  %87 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %88 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %89 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %90 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %91 = fmul float %34, %27
>  %92 = fmul float %35, %28
>  %93 = fadd float %91, %92
>  %94 = fmul float %36, %29
>  %95 = fadd float %93, %94
>  %96 = fmul float %37, %30
>  %97 = fadd float %95, %96
>  %98 = call float @fabs(float %97)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %87, float %88, float %89, float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %98, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %55, float %56, float %57, float %58)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %80, float %82, float %84, float %86)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0840708
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800022f
>08070605
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..3]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV TEMP[1].w, TEMP[0].wwww
>  5: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  6: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].xxxx
>  7: MUL TEMP[3].xyz, CONST[2].xyzz, TEMP[3].xxxx
>  8: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
>  9: MOV OUT[0], TEMP[1]
> 10: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %39 = fdiv float %36, %38
>  %40 = fdiv float %37, %38
>  %41 = bitcast float %39 to i32
>  %42 = bitcast float %40 to i32
>  %43 = insertelement <2 x i32> undef, i32 %41, i32 0
>  %44 = insertelement <2 x i32> %43, i32 %42, i32 1
>  %45 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %44, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = fmul float %46, %31
>  %51 = fmul float %47, %32
>  %52 = fmul float %48, %33
>  %53 = fmul float %49, %34
>  %54 = fmul float %35, %22
>  %55 = fadd float %54, %23
>  %56 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
>  %57 = fsub float -0.000000e+00, %56
>  %58 = fadd float 1.000000e+00, %57
>  %59 = fmul float %24, %58
>  %60 = fmul float %25, %58
>  %61 = fmul float %26, %58
>  %62 = fmul float %50, %56
>  %63 = fadd float %62, %59
>  %64 = fmul float %51, %56
>  %65 = fadd float %64, %60
>  %66 = fmul float %52, %56
>  %67 = fadd float %66, %61
>  %68 = fcmp ugt float %53, 0.000000e+00
>  %69 = sext i1 %68 to i32
>  %70 = trunc i32 %69 to i1
>  %71 = select i1 %70, float 1.000000e+00, float -1.000000e+00
>  call void @llvm.AMDGPU.kill(float %71)
>  %72 = call i32 @llvm.SI.packf16(float %63, float %65)
>  %73 = bitcast i32 %72 to float
>  %74 = call i32 @llvm.SI.packf16(float %67, float %53)
>  %75 = bitcast i32 %74 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %73, float %75, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>d0080002
>02010106
>d2000007
>0009e4f3
>7c260e80
>c81c0200
>c81d0201
>10120f04
>c81c0400
>c81d0401
>c0800100
>bf8c007f
>c2020104
>c2028105
>bf8c007f
>7e100205
>d2820007
>04200907
>d2060807
>02010107
>08100ef2
>c202010a
>bf8c007f
>10141004
>d2820009
>042a0f09
>5e0c0d09
>c8240100
>c8250101
>10121303
>c2020109
>bf8c007f
>10141004
>d2820009
>042a0f09
>c8280000
>c8290001
>10001502
>c2000108
>bf8c007f
>10021000
>d2820000
>04060f00
>5e001300
>f8001c0f
>06000600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = fmul float %34, %11
>  %53 = fmul float %34, %12
>  %54 = fmul float %34, %13
>  %55 = fmul float %34, %14
>  %56 = fmul float %35, %15
>  %57 = fadd float %56, %52
>  %58 = fmul float %35, %16
>  %59 = fadd float %58, %53
>  %60 = fmul float %35, %17
>  %61 = fadd float %60, %54
>  %62 = fmul float %35, %18
>  %63 = fadd float %62, %55
>  %64 = fmul float %36, %19
>  %65 = fadd float %64, %57
>  %66 = fmul float %36, %20
>  %67 = fadd float %66, %59
>  %68 = fmul float %36, %21
>  %69 = fadd float %68, %61
>  %70 = fmul float %36, %22
>  %71 = fadd float %70, %63
>  %72 = fmul float %37, %23
>  %73 = fadd float %72, %65
>  %74 = fmul float %37, %24
>  %75 = fadd float %74, %67
>  %76 = fmul float %37, %25
>  %77 = fadd float %76, %69
>  %78 = fmul float %37, %26
>  %79 = fadd float %78, %71
>  %80 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %81 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %82 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %83 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %84 = fmul float %34, %27
>  %85 = fmul float %35, %28
>  %86 = fadd float %84, %85
>  %87 = fmul float %36, %29
>  %88 = fadd float %86, %87
>  %89 = fmul float %37, %30
>  %90 = fadd float %88, %89
>  %91 = call float @fabs(float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %80, float %81, float %82, float %83)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %91, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %73, float %75, float %77, float %79)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..11]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
>  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
>  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
>  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
>  9: MUL TEMP[0], IN[3].xxxx, CONST[8]
> 10: MAD TEMP[0], IN[3].yyyy, CONST[9], TEMP[0]
> 11: MAD TEMP[0], IN[3].zzzz, CONST[10], TEMP[0]
> 12: MAD OUT[3], IN[3].wwww, CONST[11], TEMP[0]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %59 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
>  %61 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %60, i32 0, i32 %5)
>  %62 = extractelement <4 x float> %61, i32 0
>  %63 = extractelement <4 x float> %61, i32 1
>  %64 = extractelement <4 x float> %61, i32 2
>  %65 = extractelement <4 x float> %61, i32 3
>  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
>  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
>  %69 = extractelement <4 x float> %68, i32 0
>  %70 = extractelement <4 x float> %68, i32 1
>  %71 = extractelement <4 x float> %68, i32 2
>  %72 = extractelement <4 x float> %68, i32 3
>  %73 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %74 = load <16 x i8> addrspace(2)* %73, !tbaa !0
>  %75 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %74, i32 0, i32 %5)
>  %76 = extractelement <4 x float> %75, i32 0
>  %77 = extractelement <4 x float> %75, i32 1
>  %78 = extractelement <4 x float> %75, i32 2
>  %79 = extractelement <4 x float> %75, i32 3
>  %80 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %81 = load <16 x i8> addrspace(2)* %80, !tbaa !0
>  %82 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %81, i32 0, i32 %5)
>  %83 = extractelement <4 x float> %82, i32 0
>  %84 = extractelement <4 x float> %82, i32 1
>  %85 = extractelement <4 x float> %82, i32 2
>  %86 = extractelement <4 x float> %82, i32 3
>  %87 = fmul float %62, %11
>  %88 = fmul float %62, %12
>  %89 = fmul float %62, %13
>  %90 = fmul float %62, %14
>  %91 = fmul float %63, %15
>  %92 = fadd float %91, %87
>  %93 = fmul float %63, %16
>  %94 = fadd float %93, %88
>  %95 = fmul float %63, %17
>  %96 = fadd float %95, %89
>  %97 = fmul float %63, %18
>  %98 = fadd float %97, %90
>  %99 = fmul float %64, %19
>  %100 = fadd float %99, %92
>  %101 = fmul float %64, %20
>  %102 = fadd float %101, %94
>  %103 = fmul float %64, %21
>  %104 = fadd float %103, %96
>  %105 = fmul float %64, %22
>  %106 = fadd float %105, %98
>  %107 = fmul float %65, %23
>  %108 = fadd float %107, %100
>  %109 = fmul float %65, %24
>  %110 = fadd float %109, %102
>  %111 = fmul float %65, %25
>  %112 = fadd float %111, %104
>  %113 = fmul float %65, %26
>  %114 = fadd float %113, %106
>  %115 = call float @llvm.AMDIL.clamp.(float %69, float 0.000000e+00, float 1.000000e+00)
>  %116 = call float @llvm.AMDIL.clamp.(float %70, float 0.000000e+00, float 1.000000e+00)
>  %117 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %118 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
>  %119 = fmul float %76, %27
>  %120 = fmul float %76, %28
>  %121 = fmul float %76, %29
>  %122 = fmul float %76, %30
>  %123 = fmul float %77, %31
>  %124 = fadd float %123, %119
>  %125 = fmul float %77, %32
>  %126 = fadd float %125, %120
>  %127 = fmul float %77, %33
>  %128 = fadd float %127, %121
>  %129 = fmul float %77, %34
>  %130 = fadd float %129, %122
>  %131 = fmul float %78, %35
>  %132 = fadd float %131, %124
>  %133 = fmul float %78, %36
>  %134 = fadd float %133, %126
>  %135 = fmul float %78, %37
>  %136 = fadd float %135, %128
>  %137 = fmul float %78, %38
>  %138 = fadd float %137, %130
>  %139 = fmul float %79, %39
>  %140 = fadd float %139, %132
>  %141 = fmul float %79, %40
>  %142 = fadd float %141, %134
>  %143 = fmul float %79, %41
>  %144 = fadd float %143, %136
>  %145 = fmul float %79, %42
>  %146 = fadd float %145, %138
>  %147 = fmul float %83, %43
>  %148 = fmul float %83, %44
>  %149 = fmul float %83, %45
>  %150 = fmul float %83, %46
>  %151 = fmul float %84, %47
>  %152 = fadd float %151, %147
>  %153 = fmul float %84, %48
>  %154 = fadd float %153, %148
>  %155 = fmul float %84, %49
>  %156 = fadd float %155, %149
>  %157 = fmul float %84, %50
>  %158 = fadd float %157, %150
>  %159 = fmul float %85, %51
>  %160 = fadd float %159, %152
>  %161 = fmul float %85, %52
>  %162 = fadd float %161, %154
>  %163 = fmul float %85, %53
>  %164 = fadd float %163, %156
>  %165 = fmul float %85, %54
>  %166 = fadd float %165, %158
>  %167 = fmul float %86, %55
>  %168 = fadd float %167, %160
>  %169 = fmul float %86, %56
>  %170 = fadd float %169, %162
>  %171 = fmul float %86, %57
>  %172 = fadd float %171, %164
>  %173 = fmul float %86, %58
>  %174 = fadd float %173, %166
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %115, float %116, float %117, float %118)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %140, float %142, float %144, float %146)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %168, float %170, float %172, float %174)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %108, float %110, float %112, float %114)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800021f
>05060701
>c084070c
>bf8c000f
>e00c2000
>80020100
>c2020123
>bf8c0070
>100a0204
>c2020127
>bf8c007f
>d2820005
>04140902
>c202012b
>bf8c007f
>d2820005
>04140903
>c202012f
>bf8c007f
>d2820005
>04140904
>c2020122
>bf8c007f
>100c0204
>c2020126
>bf8c007f
>d2820006
>04180902
>c202012a
>bf8c007f
>d2820006
>04180903
>c202012e
>bf8c007f
>d2820006
>04180904
>c2020121
>bf8c007f
>100e0204
>c2020125
>bf8c007f
>d2820007
>041c0902
>c2020129
>bf8c007f
>d2820007
>041c0903
>c202012d
>bf8c007f
>d2820007
>041c0904
>c2020120
>bf8c007f
>10100204
>c2020124
>bf8c007f
>d2820008
>04200902
>c2020128
>bf8c007f
>d2820008
>04200903
>c202012c
>bf8c007f
>d2820001
>04200904
>f800022f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  %69 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %69, float %70, float %71, float %72)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %21 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %22 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %23 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
>  %25 = bitcast i32 %24 to float
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8080300
>c8090301
>c80c0200
>c80d0201
>5e040503
>c80c0100
>c80d0101
>c8100000
>c8110001
>5e000704
>f8001c0f
>02000200
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..14]
>DCL CONST[16..22]
>DCL TEMP[0..3]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: DP4 TEMP[1], IN[0], CONST[13]
> 15: ABS OUT[2].x, TEMP[1]
> 16: MOV OUT[2].yzw, IMM[0].xxxy
> 17: DP4 TEMP[2].x, IN[0], CONST[16]
> 18: DP4 TEMP[2].y, IN[0], CONST[17]
> 19: DP4 TEMP[2].z, IN[0], CONST[18]
> 20: MOV TEMP[2].w, IN[3]
> 21: MUL TEMP[3], TEMP[2].xxxx, CONST[19]
> 22: MAD TEMP[3], TEMP[2].yyyy, CONST[20], TEMP[3]
> 23: MAD TEMP[3], TEMP[2].zzzz, CONST[21], TEMP[3]
> 24: MAD OUT[3], TEMP[2].wwww, CONST[22], TEMP[3]
> 25: MOV OUT[4], IN[4]
> 26: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 268)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 284)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 300)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %75 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0
>  %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %76, i32 0, i32 %5)
>  %78 = extractelement <4 x float> %77, i32 0
>  %79 = extractelement <4 x float> %77, i32 1
>  %80 = extractelement <4 x float> %77, i32 2
>  %81 = extractelement <4 x float> %77, i32 3
>  %82 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %83 = load <16 x i8> addrspace(2)* %82, !tbaa !0
>  %84 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %83, i32 0, i32 %5)
>  %85 = extractelement <4 x float> %84, i32 0
>  %86 = extractelement <4 x float> %84, i32 1
>  %87 = extractelement <4 x float> %84, i32 2
>  %88 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %89 = load <16 x i8> addrspace(2)* %88, !tbaa !0
>  %90 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %89, i32 0, i32 %5)
>  %91 = extractelement <4 x float> %90, i32 0
>  %92 = extractelement <4 x float> %90, i32 1
>  %93 = extractelement <4 x float> %90, i32 2
>  %94 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %95 = load <16 x i8> addrspace(2)* %94, !tbaa !0
>  %96 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %95, i32 0, i32 %5)
>  %97 = extractelement <4 x float> %96, i32 3
>  %98 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %99 = load <16 x i8> addrspace(2)* %98, !tbaa !0
>  %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %99, i32 0, i32 %5)
>  %101 = extractelement <4 x float> %100, i32 0
>  %102 = extractelement <4 x float> %100, i32 1
>  %103 = extractelement <4 x float> %100, i32 2
>  %104 = extractelement <4 x float> %100, i32 3
>  %105 = fmul float %78, %11
>  %106 = fmul float %78, %12
>  %107 = fmul float %78, %13
>  %108 = fmul float %78, %14
>  %109 = fmul float %79, %15
>  %110 = fadd float %109, %105
>  %111 = fmul float %79, %16
>  %112 = fadd float %111, %106
>  %113 = fmul float %79, %17
>  %114 = fadd float %113, %107
>  %115 = fmul float %79, %18
>  %116 = fadd float %115, %108
>  %117 = fmul float %80, %19
>  %118 = fadd float %117, %110
>  %119 = fmul float %80, %20
>  %120 = fadd float %119, %112
>  %121 = fmul float %80, %21
>  %122 = fadd float %121, %114
>  %123 = fmul float %80, %22
>  %124 = fadd float %123, %116
>  %125 = fmul float %81, %23
>  %126 = fadd float %125, %118
>  %127 = fmul float %81, %24
>  %128 = fadd float %127, %120
>  %129 = fmul float %81, %25
>  %130 = fadd float %129, %122
>  %131 = fmul float %81, %26
>  %132 = fadd float %131, %124
>  %133 = fmul float %85, %27
>  %134 = fmul float %86, %28
>  %135 = fadd float %134, %133
>  %136 = fmul float %87, %29
>  %137 = fadd float %135, %136
>  %138 = fmul float %85, %30
>  %139 = fmul float %86, %31
>  %140 = fadd float %139, %138
>  %141 = fmul float %87, %32
>  %142 = fadd float %140, %141
>  %143 = fmul float %85, %33
>  %144 = fmul float %86, %34
>  %145 = fadd float %144, %143
>  %146 = fmul float %87, %35
>  %147 = fadd float %145, %146
>  %148 = fmul float %137, %137
>  %149 = fmul float %142, %142
>  %150 = fadd float %149, %148
>  %151 = fmul float %147, %147
>  %152 = fadd float %150, %151
>  %153 = call float @fabs(float %152)
>  %154 = call float @llvm.AMDGPU.rsq(float %153)
>  %155 = fmul float %36, %39
>  %156 = fadd float %155, %91
>  %157 = fmul float %37, %40
>  %158 = fadd float %157, %92
>  %159 = fmul float %38, %41
>  %160 = fadd float %159, %93
>  %161 = call float @llvm.AMDIL.clamp.(float %156, float 0.000000e+00, float 1.000000e+00)
>  %162 = call float @llvm.AMDIL.clamp.(float %158, float 0.000000e+00, float 1.000000e+00)
>  %163 = call float @llvm.AMDIL.clamp.(float %160, float 0.000000e+00, float 1.000000e+00)
>  %164 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %165 = fmul float %78, %43
>  %166 = fmul float %79, %44
>  %167 = fadd float %165, %166
>  %168 = fmul float %80, %45
>  %169 = fadd float %167, %168
>  %170 = fmul float %81, %46
>  %171 = fadd float %169, %170
>  %172 = call float @fabs(float %171)
>  %173 = fmul float %78, %47
>  %174 = fmul float %79, %48
>  %175 = fadd float %173, %174
>  %176 = fmul float %80, %49
>  %177 = fadd float %175, %176
>  %178 = fmul float %81, %50
>  %179 = fadd float %177, %178
>  %180 = fmul float %78, %51
>  %181 = fmul float %79, %52
>  %182 = fadd float %180, %181
>  %183 = fmul float %80, %53
>  %184 = fadd float %182, %183
>  %185 = fmul float %81, %54
>  %186 = fadd float %184, %185
>  %187 = fmul float %78, %55
>  %188 = fmul float %79, %56
>  %189 = fadd float %187, %188
>  %190 = fmul float %80, %57
>  %191 = fadd float %189, %190
>  %192 = fmul float %81, %58
>  %193 = fadd float %191, %192
>  %194 = fmul float %179, %59
>  %195 = fmul float %179, %60
>  %196 = fmul float %179, %61
>  %197 = fmul float %179, %62
>  %198 = fmul float %186, %63
>  %199 = fadd float %198, %194
>  %200 = fmul float %186, %64
>  %201 = fadd float %200, %195
>  %202 = fmul float %186, %65
>  %203 = fadd float %202, %196
>  %204 = fmul float %186, %66
>  %205 = fadd float %204, %197
>  %206 = fmul float %193, %67
>  %207 = fadd float %206, %199
>  %208 = fmul float %193, %68
>  %209 = fadd float %208, %201
>  %210 = fmul float %193, %69
>  %211 = fadd float %210, %203
>  %212 = fmul float %193, %70
>  %213 = fadd float %212, %205
>  %214 = fmul float %97, %71
>  %215 = fadd float %214, %207
>  %216 = fmul float %97, %72
>  %217 = fadd float %216, %209
>  %218 = fmul float %97, %73
>  %219 = fadd float %218, %211
>  %220 = fmul float %97, %74
>  %221 = fadd float %220, %213
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %161, float %162, float %163, float %164)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %172, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %215, float %217, float %219, float %221)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %101, float %102, float %103, float %104)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %126, float %128, float %130, float %132)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c0840700
>bf8c000f
>e00c2000
>80020100
>c2020135
>bf8c0070
>100a0404
>c2020134
>bf8c007f
>d2820005
>04140901
>c2020136
>bf8c007f
>d2820005
>04140903
>c2020137
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c2020145
>bf8c000f
>100a0404
>c2020144
>bf8c007f
>d2820005
>04140901
>c2020146
>bf8c007f
>d2820005
>04140903
>c2020147
>bf8c007f
>d2820005
>04140904
>c2020141
>bf8c007f
>100c0404
>c2020140
>bf8c007f
>d2820006
>04180901
>c2020142
>bf8c007f
>d2820006
>04180903
>c2020143
>bf8c007f
>d2820006
>04180904
>c202014f
>bf8c007f
>100e0c04
>c2020153
>bf8c007f
>d2820008
>041c0905
>c2020149
>bf8c007f
>100e0404
>c2020148
>bf8c007f
>d2820007
>041c0901
>c202014a
>bf8c007f
>d2820007
>041c0903
>c202014b
>bf8c007f
>d2820007
>041c0904
>c2020157
>bf8c007f
>d282000c
>04200907
>c084070c
>bf8c007f
>e00c2000
>80020800
>c202015b
>bf8c0070
>d282000c
>0430090b
>c202014e
>bf8c007f
>101a0c04
>c2020152
>bf8c007f
>d282000d
>04340905
>c2020156
>bf8c007f
>d282000d
>04340907
>c202015a
>bf8c007f
>d282000d
>0434090b
>c202014d
>bf8c007f
>101c0c04
>c2020151
>bf8c007f
>d282000e
>04380905
>c2020155
>bf8c007f
>d282000e
>04380907
>c2020159
>bf8c007f
>d282000e
>0438090b
>c202014c
>bf8c007f
>100c0c04
>c2020150
>bf8c007f
>d2820005
>04180905
>c2020154
>bf8c007f
>d2820005
>04140907
>c2020158
>bf8c007f
>d2820005
>0414090b
>f800022f
>0c0d0e05
>c0820710
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..19]
>DCL CONST[21..27]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: ABS OUT[2].x, TEMP[4].zzzz
> 41: MOV OUT[2].yzw, IMM[0].xxxy
> 42: DP4 TEMP[1].x, IN[0], CONST[21]
> 43: DP4 TEMP[1].y, IN[0], CONST[22]
> 44: DP4 TEMP[1].z, IN[0], CONST[23]
> 45: MOV TEMP[1].w, IN[3]
> 46: MUL TEMP[2], TEMP[1].xxxx, CONST[24]
> 47: MAD TEMP[2], TEMP[1].yyyy, CONST[25], TEMP[2]
> 48: MAD TEMP[2], TEMP[1].zzzz, CONST[26], TEMP[2]
> 49: MAD OUT[3], TEMP[1].wwww, CONST[27], TEMP[2]
> 50: MOV OUT[4], IN[4]
> 51: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 444)
>  %99 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %100 = load <16 x i8> addrspace(2)* %99, !tbaa !0
>  %101 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %100, i32 0, i32 %5)
>  %102 = extractelement <4 x float> %101, i32 0
>  %103 = extractelement <4 x float> %101, i32 1
>  %104 = extractelement <4 x float> %101, i32 2
>  %105 = extractelement <4 x float> %101, i32 3
>  %106 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %107 = load <16 x i8> addrspace(2)* %106, !tbaa !0
>  %108 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %107, i32 0, i32 %5)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = extractelement <4 x float> %108, i32 1
>  %111 = extractelement <4 x float> %108, i32 2
>  %112 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %113 = load <16 x i8> addrspace(2)* %112, !tbaa !0
>  %114 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %113, i32 0, i32 %5)
>  %115 = extractelement <4 x float> %114, i32 0
>  %116 = extractelement <4 x float> %114, i32 1
>  %117 = extractelement <4 x float> %114, i32 2
>  %118 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %119 = load <16 x i8> addrspace(2)* %118, !tbaa !0
>  %120 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %119, i32 0, i32 %5)
>  %121 = extractelement <4 x float> %120, i32 3
>  %122 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
>  %124 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %123, i32 0, i32 %5)
>  %125 = extractelement <4 x float> %124, i32 0
>  %126 = extractelement <4 x float> %124, i32 1
>  %127 = extractelement <4 x float> %124, i32 2
>  %128 = extractelement <4 x float> %124, i32 3
>  %129 = fmul float %102, %11
>  %130 = fmul float %102, %12
>  %131 = fmul float %102, %13
>  %132 = fmul float %102, %14
>  %133 = fmul float %103, %15
>  %134 = fadd float %133, %129
>  %135 = fmul float %103, %16
>  %136 = fadd float %135, %130
>  %137 = fmul float %103, %17
>  %138 = fadd float %137, %131
>  %139 = fmul float %103, %18
>  %140 = fadd float %139, %132
>  %141 = fmul float %104, %19
>  %142 = fadd float %141, %134
>  %143 = fmul float %104, %20
>  %144 = fadd float %143, %136
>  %145 = fmul float %104, %21
>  %146 = fadd float %145, %138
>  %147 = fmul float %104, %22
>  %148 = fadd float %147, %140
>  %149 = fmul float %105, %23
>  %150 = fadd float %149, %142
>  %151 = fmul float %105, %24
>  %152 = fadd float %151, %144
>  %153 = fmul float %105, %25
>  %154 = fadd float %153, %146
>  %155 = fmul float %105, %26
>  %156 = fadd float %155, %148
>  %157 = fmul float %109, %27
>  %158 = fmul float %110, %28
>  %159 = fadd float %158, %157
>  %160 = fmul float %111, %29
>  %161 = fadd float %159, %160
>  %162 = fmul float %109, %30
>  %163 = fmul float %110, %31
>  %164 = fadd float %163, %162
>  %165 = fmul float %111, %32
>  %166 = fadd float %164, %165
>  %167 = fmul float %109, %33
>  %168 = fmul float %110, %34
>  %169 = fadd float %168, %167
>  %170 = fmul float %111, %35
>  %171 = fadd float %169, %170
>  %172 = fmul float %161, %161
>  %173 = fmul float %166, %166
>  %174 = fadd float %173, %172
>  %175 = fmul float %171, %171
>  %176 = fadd float %174, %175
>  %177 = call float @fabs(float %176)
>  %178 = call float @llvm.AMDGPU.rsq(float %177)
>  %179 = fmul float %161, %178
>  %180 = fmul float %166, %178
>  %181 = fmul float %171, %178
>  %182 = fmul float %37, %40
>  %183 = fadd float %182, %115
>  %184 = fmul float %38, %41
>  %185 = fadd float %184, %116
>  %186 = fmul float %39, %42
>  %187 = fadd float %186, %117
>  %188 = call float @llvm.AMDIL.clamp.(float %183, float 0.000000e+00, float 1.000000e+00)
>  %189 = call float @llvm.AMDIL.clamp.(float %185, float 0.000000e+00, float 1.000000e+00)
>  %190 = call float @llvm.AMDIL.clamp.(float %187, float 0.000000e+00, float 1.000000e+00)
>  %191 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %192 = fmul float %102, %47
>  %193 = fmul float %102, %48
>  %194 = fmul float %102, %49
>  %195 = fmul float %103, %50
>  %196 = fadd float %195, %192
>  %197 = fmul float %103, %51
>  %198 = fadd float %197, %193
>  %199 = fmul float %103, %52
>  %200 = fadd float %199, %194
>  %201 = fmul float %104, %53
>  %202 = fadd float %201, %196
>  %203 = fmul float %104, %54
>  %204 = fadd float %203, %198
>  %205 = fmul float %104, %55
>  %206 = fadd float %205, %200
>  %207 = fmul float %105, %56
>  %208 = fadd float %207, %202
>  %209 = fmul float %105, %57
>  %210 = fadd float %209, %204
>  %211 = fmul float %105, %58
>  %212 = fadd float %211, %206
>  %213 = fsub float %44, %208
>  %214 = fsub float %45, %210
>  %215 = fsub float %46, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fdiv float 1.000000e+00, %222
>  %227 = fmul float %222, %226
>  %228 = fmul float %226, %226
>  %229 = fmul float %59, %227
>  %230 = fmul float %60, %226
>  %231 = fadd float %230, %229
>  %232 = fmul float %61, %228
>  %233 = fadd float %231, %232
>  %234 = fdiv float 1.000000e+00, %233
>  %235 = fmul float %208, %208
>  %236 = fmul float %210, %210
>  %237 = fadd float %236, %235
>  %238 = fmul float %212, %212
>  %239 = fadd float %237, %238
>  %240 = call float @fabs(float %239)
>  %241 = call float @llvm.AMDGPU.rsq(float %240)
>  %242 = fmul float %208, %241
>  %243 = fmul float %210, %241
>  %244 = fmul float %212, %241
>  %245 = fsub float %223, %242
>  %246 = fsub float %224, %243
>  %247 = fsub float %225, %244
>  %248 = fmul float %245, %245
>  %249 = fmul float %246, %246
>  %250 = fadd float %249, %248
>  %251 = fmul float %247, %247
>  %252 = fadd float %250, %251
>  %253 = call float @fabs(float %252)
>  %254 = call float @llvm.AMDGPU.rsq(float %253)
>  %255 = fmul float %245, %254
>  %256 = fmul float %246, %254
>  %257 = fmul float %247, %254
>  %258 = fmul float %179, %223
>  %259 = fmul float %180, %224
>  %260 = fadd float %259, %258
>  %261 = fmul float %181, %225
>  %262 = fadd float %260, %261
>  %263 = fmul float %179, %255
>  %264 = fmul float %180, %256
>  %265 = fadd float %264, %263
>  %266 = fmul float %181, %257
>  %267 = fadd float %265, %266
>  %268 = fcmp uge float %262, 0.000000e+00
>  %269 = select i1 %268, float %262, float 0.000000e+00
>  %270 = fcmp uge float %267, 0.000000e+00
>  %271 = select i1 %270, float %267, float 0.000000e+00
>  %272 = call float @llvm.pow.f32(float %271, float %36)
>  %273 = call float @llvm.AMDGPU.cndlt(float %262, float 0.000000e+00, float %272)
>  %274 = fmul float 1.000000e+00, %234
>  %275 = fmul float %269, %234
>  %276 = fmul float %273, %234
>  %277 = fmul float %274, %62
>  %278 = fadd float %277, %183
>  %279 = fmul float %274, %63
>  %280 = fadd float %279, %185
>  %281 = fmul float %274, %64
>  %282 = fadd float %281, %187
>  %283 = fmul float %275, %65
>  %284 = fadd float %283, %278
>  %285 = fmul float %275, %66
>  %286 = fadd float %285, %280
>  %287 = fmul float %275, %67
>  %288 = fadd float %287, %282
>  %289 = fmul float %276, %68
>  %290 = fadd float %289, %284
>  %291 = fmul float %276, %69
>  %292 = fadd float %291, %286
>  %293 = fmul float %276, %70
>  %294 = fadd float %293, %288
>  %295 = call float @llvm.AMDIL.clamp.(float %290, float 0.000000e+00, float 1.000000e+00)
>  %296 = call float @llvm.AMDIL.clamp.(float %292, float 0.000000e+00, float 1.000000e+00)
>  %297 = call float @llvm.AMDIL.clamp.(float %294, float 0.000000e+00, float 1.000000e+00)
>  %298 = call float @fabs(float %212)
>  %299 = fmul float %102, %71
>  %300 = fmul float %103, %72
>  %301 = fadd float %299, %300
>  %302 = fmul float %104, %73
>  %303 = fadd float %301, %302
>  %304 = fmul float %105, %74
>  %305 = fadd float %303, %304
>  %306 = fmul float %102, %75
>  %307 = fmul float %103, %76
>  %308 = fadd float %306, %307
>  %309 = fmul float %104, %77
>  %310 = fadd float %308, %309
>  %311 = fmul float %105, %78
>  %312 = fadd float %310, %311
>  %313 = fmul float %102, %79
>  %314 = fmul float %103, %80
>  %315 = fadd float %313, %314
>  %316 = fmul float %104, %81
>  %317 = fadd float %315, %316
>  %318 = fmul float %105, %82
>  %319 = fadd float %317, %318
>  %320 = fmul float %305, %83
>  %321 = fmul float %305, %84
>  %322 = fmul float %305, %85
>  %323 = fmul float %305, %86
>  %324 = fmul float %312, %87
>  %325 = fadd float %324, %320
>  %326 = fmul float %312, %88
>  %327 = fadd float %326, %321
>  %328 = fmul float %312, %89
>  %329 = fadd float %328, %322
>  %330 = fmul float %312, %90
>  %331 = fadd float %330, %323
>  %332 = fmul float %319, %91
>  %333 = fadd float %332, %325
>  %334 = fmul float %319, %92
>  %335 = fadd float %334, %327
>  %336 = fmul float %319, %93
>  %337 = fadd float %336, %329
>  %338 = fmul float %319, %94
>  %339 = fadd float %338, %331
>  %340 = fmul float %121, %95
>  %341 = fadd float %340, %333
>  %342 = fmul float %121, %96
>  %343 = fadd float %342, %335
>  %344 = fmul float %121, %97
>  %345 = fadd float %344, %337
>  %346 = fmul float %121, %98
>  %347 = fadd float %346, %339
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %295, float %296, float %297, float %191)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %298, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %341, float %343, float %345, float %347)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %125, float %126, float %127, float %128)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %150, float %152, float %154, float %156)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
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>c2020139
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>c202013d
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>04140904
>c2020130
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>c2020134
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>04140902
>c2020138
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>04140903
>c202013c
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>04140904
>100a1108
>d2820007
>04160d06
>c2020132
>bf8c007f
>100a0204
>c2020136
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>04140902
>c202013a
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>04140903
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>04140904
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>041e0b05
>d2060107
>02010107
>7e125b07
>10141306
>c202012d
>bf8c007f
>080e0c04
>c202012c
>bf8c007f
>081a1004
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>041a0f07
>c202012e
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>08160a04
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>02010106
>7e0c5b06
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>08181507
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>08141509
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>043a150a
>d206010b
>0201010b
>7e165b0b
>1018170c
>101a170d
>c0840704
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>e00c2000
>80020e00
>c2020114
>bf8c0070
>10241c04
>c2020115
>bf8c007f
>d2820012
>0448090f
>c2020116
>bf8c007f
>d2820012
>04480910
>c2020110
>bf8c007f
>10261c04
>c2020111
>bf8c007f
>d2820013
>044c090f
>c2020112
>bf8c007f
>d2820013
>044c0910
>10282713
>d2820014
>04522512
>c2020118
>bf8c007f
>102a1c04
>c2020119
>bf8c007f
>d2820015
>0454090f
>c202011a
>bf8c007f
>d282000f
>04540910
>d282000e
>04521f0f
>d206010e
>0201010e
>7e205b0e
>101c2113
>10221b0e
>101a2112
>d282000c
>0446190d
>1016170a
>1014210f
>d282000b
>0432170a
>d00c0004
>0201010b
>d200000b
>00121680
>7e164f0b
>c202011c
>bf8c007f
>0e161604
>7e164b0b
>1010110e
>d2820007
>04220f0d
>d2820008
>041e130a
>d0080004
>02021080
>d2000009
>0011010b
>7e0e5506
>100c0f06
>c2020140
>bf8c007f
>100c0c04
>c2020141
>bf8c007f
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>041a0e04
>100e0f07
>c2020142
>bf8c007f
>d2820006
>041a0e04
>7e0e5506
>100c0f09
>d00c0004
>02010108
>d2000008
>00121080
>10100f08
>c0840708
>bf8c007f
>e00c2000
>80020900
>c2020122
>c2028126
>bf8c0070
>7e1a0205
>d282000d
>042e1a04
>c2020146
>bf8c007f
>d282000d
>04340907
>c202014a
>bf8c007f
>d282000d
>04340908
>c202014e
>bf8c007f
>d282000d
>04340906
>d206080d
>0201010d
>c2020121
>c2028125
>bf8c007f
>7e1c0205
>d282000e
>042a1c04
>c2020145
>bf8c007f
>d282000e
>04380907
>c2020149
>bf8c007f
>d282000e
>04380908
>c202014d
>bf8c007f
>d282000e
>04380906
>d206080e
>0201010e
>c2020120
>c2028124
>bf8c007f
>7e1e0205
>d2820009
>04261e04
>c2020144
>bf8c007f
>d2820007
>04240907
>c2020148
>bf8c007f
>d2820007
>041c0908
>c202014c
>bf8c007f
>d2820006
>041c0906
>d2060806
>02010106
>c202012b
>bf8c007f
>d2060807
>02010004
>f800020f
>070d0e06
>d2060105
>02010105
>bf8c070f
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c2020159
>bf8c000f
>100a0404
>c2020158
>bf8c007f
>d2820005
>04140901
>c202015a
>bf8c007f
>d2820005
>04140903
>c202015b
>bf8c007f
>d2820005
>04140904
>c2020155
>bf8c007f
>100c0404
>c2020154
>bf8c007f
>d2820006
>04180901
>c2020156
>bf8c007f
>d2820006
>04180903
>c2020157
>bf8c007f
>d2820006
>04180904
>c2020163
>bf8c007f
>100e0c04
>c2020167
>bf8c007f
>d2820008
>041c0905
>c202015d
>bf8c007f
>100e0404
>c202015c
>bf8c007f
>d2820007
>041c0901
>c202015e
>bf8c007f
>d2820007
>041c0903
>c202015f
>bf8c007f
>d2820007
>041c0904
>c202016b
>bf8c007f
>d282000c
>04200907
>c084070c
>bf8c007f
>e00c2000
>80020800
>c202016f
>bf8c0070
>d282000c
>0430090b
>c2020162
>bf8c007f
>101a0c04
>c2020166
>bf8c007f
>d282000d
>04340905
>c202016a
>bf8c007f
>d282000d
>04340907
>c202016e
>bf8c007f
>d282000d
>0434090b
>c2020161
>bf8c007f
>101c0c04
>c2020165
>bf8c007f
>d282000e
>04380905
>c2020169
>bf8c007f
>d282000e
>04380907
>c202016d
>bf8c007f
>d282000e
>0438090b
>c2020160
>bf8c007f
>100c0c04
>c2020164
>bf8c007f
>d2820005
>04180905
>c2020168
>bf8c007f
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>04140907
>c202016c
>bf8c007f
>d2820005
>0414090b
>f800022f
>0c0d0e05
>c0820710
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], FOG
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP4 TEMP[0], IN[0], CONST[6]
>  5: ABS OUT[1].x, TEMP[0]
>  6: MOV OUT[1].yzw, IMM[0].xxxy
>  7: MOV OUT[2], IN[1]
>  8: MOV OUT[3], IN[2]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = fmul float %34, %11
>  %53 = fmul float %34, %12
>  %54 = fmul float %34, %13
>  %55 = fmul float %34, %14
>  %56 = fmul float %35, %15
>  %57 = fadd float %56, %52
>  %58 = fmul float %35, %16
>  %59 = fadd float %58, %53
>  %60 = fmul float %35, %17
>  %61 = fadd float %60, %54
>  %62 = fmul float %35, %18
>  %63 = fadd float %62, %55
>  %64 = fmul float %36, %19
>  %65 = fadd float %64, %57
>  %66 = fmul float %36, %20
>  %67 = fadd float %66, %59
>  %68 = fmul float %36, %21
>  %69 = fadd float %68, %61
>  %70 = fmul float %36, %22
>  %71 = fadd float %70, %63
>  %72 = fmul float %37, %23
>  %73 = fadd float %72, %65
>  %74 = fmul float %37, %24
>  %75 = fadd float %74, %67
>  %76 = fmul float %37, %25
>  %77 = fadd float %76, %69
>  %78 = fmul float %37, %26
>  %79 = fadd float %78, %71
>  %80 = fmul float %34, %27
>  %81 = fmul float %35, %28
>  %82 = fadd float %80, %81
>  %83 = fmul float %36, %29
>  %84 = fadd float %82, %83
>  %85 = fmul float %37, %30
>  %86 = fadd float %84, %85
>  %87 = call float @fabs(float %86)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %87, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %41, float %42, float %43, float %44)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %73, float %75, float %77, float %79)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800020f
>06070705
>c0840704
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800021f
>08070605
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL OUT[5], GENERIC[2]
>DCL CONST[0..14]
>DCL CONST[16..27]
>DCL TEMP[0..5]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: DP4 TEMP[1], IN[0], CONST[13]
> 15: ABS OUT[2].x, TEMP[1]
> 16: MOV OUT[2].yzw, IMM[0].xxxy
> 17: MOV OUT[3], IN[3]
> 18: MUL TEMP[2], IN[4].xxxx, CONST[16]
> 19: MAD TEMP[2], IN[4].yyyy, CONST[17], TEMP[2]
> 20: MAD TEMP[2], IN[4].zzzz, CONST[18], TEMP[2]
> 21: MAD OUT[4], IN[4].wwww, CONST[19], TEMP[2]
> 22: MUL TEMP[3], IN[0].xxxx, CONST[20]
> 23: MAD TEMP[3], IN[0].yyyy, CONST[21], TEMP[3]
> 24: MAD TEMP[3], IN[0].zzzz, CONST[22], TEMP[3]
> 25: MAD TEMP[3], IN[0].wwww, CONST[23], TEMP[3]
> 26: DP3 TEMP[4].x, TEMP[3], TEMP[3]
> 27: RSQ TEMP[4].x, |TEMP[4]|
> 28: MUL TEMP[5], TEMP[3], TEMP[4].xxxx
> 29: DP3 TEMP[4], TEMP[0], TEMP[5]
> 30: ADD TEMP[4], TEMP[4], TEMP[4]
> 31: MAD TEMP[2].xyz, -TEMP[4], TEMP[0], TEMP[5]
> 32: MOV TEMP[2].w, IN[5]
> 33: MUL TEMP[4], TEMP[2].xxxx, CONST[24]
> 34: MAD TEMP[4], TEMP[2].yyyy, CONST[25], TEMP[4]
> 35: MAD TEMP[4], TEMP[2].zzzz, CONST[26], TEMP[4]
> 36: MAD OUT[5], TEMP[2].wwww, CONST[27], TEMP[4]
> 37: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 268)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 284)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 300)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 444)
>  %91 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0
>  %93 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %92, i32 0, i32 %5)
>  %94 = extractelement <4 x float> %93, i32 0
>  %95 = extractelement <4 x float> %93, i32 1
>  %96 = extractelement <4 x float> %93, i32 2
>  %97 = extractelement <4 x float> %93, i32 3
>  %98 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %99 = load <16 x i8> addrspace(2)* %98, !tbaa !0
>  %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %99, i32 0, i32 %5)
>  %101 = extractelement <4 x float> %100, i32 0
>  %102 = extractelement <4 x float> %100, i32 1
>  %103 = extractelement <4 x float> %100, i32 2
>  %104 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %105 = load <16 x i8> addrspace(2)* %104, !tbaa !0
>  %106 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %105, i32 0, i32 %5)
>  %107 = extractelement <4 x float> %106, i32 0
>  %108 = extractelement <4 x float> %106, i32 1
>  %109 = extractelement <4 x float> %106, i32 2
>  %110 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %111 = load <16 x i8> addrspace(2)* %110, !tbaa !0
>  %112 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %111, i32 0, i32 %5)
>  %113 = extractelement <4 x float> %112, i32 0
>  %114 = extractelement <4 x float> %112, i32 1
>  %115 = extractelement <4 x float> %112, i32 2
>  %116 = extractelement <4 x float> %112, i32 3
>  %117 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %118 = load <16 x i8> addrspace(2)* %117, !tbaa !0
>  %119 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %118, i32 0, i32 %5)
>  %120 = extractelement <4 x float> %119, i32 0
>  %121 = extractelement <4 x float> %119, i32 1
>  %122 = extractelement <4 x float> %119, i32 2
>  %123 = extractelement <4 x float> %119, i32 3
>  %124 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %125 = load <16 x i8> addrspace(2)* %124, !tbaa !0
>  %126 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %125, i32 0, i32 %5)
>  %127 = extractelement <4 x float> %126, i32 3
>  %128 = fmul float %94, %11
>  %129 = fmul float %94, %12
>  %130 = fmul float %94, %13
>  %131 = fmul float %94, %14
>  %132 = fmul float %95, %15
>  %133 = fadd float %132, %128
>  %134 = fmul float %95, %16
>  %135 = fadd float %134, %129
>  %136 = fmul float %95, %17
>  %137 = fadd float %136, %130
>  %138 = fmul float %95, %18
>  %139 = fadd float %138, %131
>  %140 = fmul float %96, %19
>  %141 = fadd float %140, %133
>  %142 = fmul float %96, %20
>  %143 = fadd float %142, %135
>  %144 = fmul float %96, %21
>  %145 = fadd float %144, %137
>  %146 = fmul float %96, %22
>  %147 = fadd float %146, %139
>  %148 = fmul float %97, %23
>  %149 = fadd float %148, %141
>  %150 = fmul float %97, %24
>  %151 = fadd float %150, %143
>  %152 = fmul float %97, %25
>  %153 = fadd float %152, %145
>  %154 = fmul float %97, %26
>  %155 = fadd float %154, %147
>  %156 = fmul float %101, %27
>  %157 = fmul float %102, %28
>  %158 = fadd float %157, %156
>  %159 = fmul float %103, %29
>  %160 = fadd float %158, %159
>  %161 = fmul float %101, %30
>  %162 = fmul float %102, %31
>  %163 = fadd float %162, %161
>  %164 = fmul float %103, %32
>  %165 = fadd float %163, %164
>  %166 = fmul float %101, %33
>  %167 = fmul float %102, %34
>  %168 = fadd float %167, %166
>  %169 = fmul float %103, %35
>  %170 = fadd float %168, %169
>  %171 = fmul float %160, %160
>  %172 = fmul float %165, %165
>  %173 = fadd float %172, %171
>  %174 = fmul float %170, %170
>  %175 = fadd float %173, %174
>  %176 = call float @fabs(float %175)
>  %177 = call float @llvm.AMDGPU.rsq(float %176)
>  %178 = fmul float %160, %177
>  %179 = fmul float %165, %177
>  %180 = fmul float %170, %177
>  %181 = fmul float %36, %39
>  %182 = fadd float %181, %107
>  %183 = fmul float %37, %40
>  %184 = fadd float %183, %108
>  %185 = fmul float %38, %41
>  %186 = fadd float %185, %109
>  %187 = call float @llvm.AMDIL.clamp.(float %182, float 0.000000e+00, float 1.000000e+00)
>  %188 = call float @llvm.AMDIL.clamp.(float %184, float 0.000000e+00, float 1.000000e+00)
>  %189 = call float @llvm.AMDIL.clamp.(float %186, float 0.000000e+00, float 1.000000e+00)
>  %190 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %191 = fmul float %94, %43
>  %192 = fmul float %95, %44
>  %193 = fadd float %191, %192
>  %194 = fmul float %96, %45
>  %195 = fadd float %193, %194
>  %196 = fmul float %97, %46
>  %197 = fadd float %195, %196
>  %198 = call float @fabs(float %197)
>  %199 = fmul float %120, %47
>  %200 = fmul float %120, %48
>  %201 = fmul float %120, %49
>  %202 = fmul float %120, %50
>  %203 = fmul float %121, %51
>  %204 = fadd float %203, %199
>  %205 = fmul float %121, %52
>  %206 = fadd float %205, %200
>  %207 = fmul float %121, %53
>  %208 = fadd float %207, %201
>  %209 = fmul float %121, %54
>  %210 = fadd float %209, %202
>  %211 = fmul float %122, %55
>  %212 = fadd float %211, %204
>  %213 = fmul float %122, %56
>  %214 = fadd float %213, %206
>  %215 = fmul float %122, %57
>  %216 = fadd float %215, %208
>  %217 = fmul float %122, %58
>  %218 = fadd float %217, %210
>  %219 = fmul float %123, %59
>  %220 = fadd float %219, %212
>  %221 = fmul float %123, %60
>  %222 = fadd float %221, %214
>  %223 = fmul float %123, %61
>  %224 = fadd float %223, %216
>  %225 = fmul float %123, %62
>  %226 = fadd float %225, %218
>  %227 = fmul float %94, %63
>  %228 = fmul float %94, %64
>  %229 = fmul float %94, %65
>  %230 = fmul float %95, %66
>  %231 = fadd float %230, %227
>  %232 = fmul float %95, %67
>  %233 = fadd float %232, %228
>  %234 = fmul float %95, %68
>  %235 = fadd float %234, %229
>  %236 = fmul float %96, %69
>  %237 = fadd float %236, %231
>  %238 = fmul float %96, %70
>  %239 = fadd float %238, %233
>  %240 = fmul float %96, %71
>  %241 = fadd float %240, %235
>  %242 = fmul float %97, %72
>  %243 = fadd float %242, %237
>  %244 = fmul float %97, %73
>  %245 = fadd float %244, %239
>  %246 = fmul float %97, %74
>  %247 = fadd float %246, %241
>  %248 = fmul float %243, %243
>  %249 = fmul float %245, %245
>  %250 = fadd float %249, %248
>  %251 = fmul float %247, %247
>  %252 = fadd float %250, %251
>  %253 = call float @fabs(float %252)
>  %254 = call float @llvm.AMDGPU.rsq(float %253)
>  %255 = fmul float %243, %254
>  %256 = fmul float %245, %254
>  %257 = fmul float %247, %254
>  %258 = fmul float %178, %255
>  %259 = fmul float %179, %256
>  %260 = fadd float %259, %258
>  %261 = fmul float %180, %257
>  %262 = fadd float %260, %261
>  %263 = fadd float %262, %262
>  %264 = fadd float %262, %262
>  %265 = fadd float %262, %262
>  %266 = fsub float -0.000000e+00, %263
>  %267 = fmul float %266, %178
>  %268 = fadd float %267, %255
>  %269 = fsub float -0.000000e+00, %264
>  %270 = fmul float %269, %179
>  %271 = fadd float %270, %256
>  %272 = fsub float -0.000000e+00, %265
>  %273 = fmul float %272, %180
>  %274 = fadd float %273, %257
>  %275 = fmul float %268, %75
>  %276 = fmul float %268, %76
>  %277 = fmul float %268, %77
>  %278 = fmul float %268, %78
>  %279 = fmul float %271, %79
>  %280 = fadd float %279, %275
>  %281 = fmul float %271, %80
>  %282 = fadd float %281, %276
>  %283 = fmul float %271, %81
>  %284 = fadd float %283, %277
>  %285 = fmul float %271, %82
>  %286 = fadd float %285, %278
>  %287 = fmul float %274, %83
>  %288 = fadd float %287, %280
>  %289 = fmul float %274, %84
>  %290 = fadd float %289, %282
>  %291 = fmul float %274, %85
>  %292 = fadd float %291, %284
>  %293 = fmul float %274, %86
>  %294 = fadd float %293, %286
>  %295 = fmul float %127, %87
>  %296 = fadd float %295, %288
>  %297 = fmul float %127, %88
>  %298 = fadd float %297, %290
>  %299 = fmul float %127, %89
>  %300 = fadd float %299, %292
>  %301 = fmul float %127, %90
>  %302 = fadd float %301, %294
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %187, float %188, float %189, float %190)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %198, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %113, float %114, float %115, float %116)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %220, float %222, float %224, float %226)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %296, float %298, float %300, float %302)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %149, float %151, float %153, float %155)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c0840700
>bf8c000f
>e00c2000
>80020100
>c2020135
>bf8c0070
>100a0404
>c2020134
>bf8c007f
>d2820005
>04140901
>c2020136
>bf8c007f
>d2820005
>04140903
>c2020137
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c084070c
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800022f
>08070605
>c0840710
>bf8c000f
>e00c2000
>80020500
>c2020143
>bf8c0070
>10120a04
>c2020147
>bf8c007f
>d2820009
>04240906
>c202014b
>bf8c007f
>d2820009
>04240907
>c202014f
>bf8c007f
>d2820009
>04240908
>c2020142
>bf8c007f
>10140a04
>c2020146
>bf8c007f
>d282000a
>04280906
>c202014a
>bf8c007f
>d282000a
>04280907
>c202014e
>bf8c007f
>d282000a
>04280908
>c2020141
>bf8c007f
>10160a04
>c2020145
>bf8c007f
>d282000b
>042c0906
>c2020149
>bf8c007f
>d282000b
>042c0907
>c202014d
>bf8c007f
>d282000b
>042c0908
>c2020140
>bf8c007f
>10180a04
>c2020144
>bf8c007f
>d282000c
>04300906
>c2020148
>bf8c007f
>d282000c
>04300907
>c202014c
>bf8c007f
>d2820005
>04300908
>f800023f
>090a0b05
>c0840704
>bf8c000f
>e00c2000
>80020600
>c2020114
>bf8c0070
>100a0c04
>c2020115
>bf8c007f
>d2820005
>04140907
>c2020116
>bf8c007f
>d2820005
>04140908
>c2020110
>bf8c007f
>10140c04
>c2020111
>bf8c007f
>d282000a
>04280907
>c2020112
>bf8c007f
>d282000a
>04280908
>1016150a
>d282000b
>042e0b05
>c2020118
>bf8c007f
>10180c04
>c2020119
>bf8c007f
>d282000c
>04300907
>c202011a
>bf8c007f
>d2820007
>04300908
>d2820006
>042e0f07
>d2060106
>02010106
>7e105b06
>100c110a
>c2020151
>bf8c007f
>10120204
>c2020155
>bf8c007f
>d2820009
>04240902
>c2020159
>bf8c007f
>d2820009
>04240903
>c202015d
>bf8c007f
>d2820009
>04240904
>c2020150
>bf8c007f
>10140204
>c2020154
>bf8c007f
>d282000a
>04280902
>c2020158
>bf8c007f
>d282000a
>04280903
>c202015c
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c2020152
>bf8c007f
>10160204
>c2020156
>bf8c007f
>d282000b
>042c0902
>c202015a
>bf8c007f
>d282000b
>042c0903
>c202015e
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101c1506
>100a1105
>101a1909
>d2820009
>043a1b05
>100e1107
>1010190b
>d2820009
>04261107
>06121309
>100a0b09
>080a0b0d
>100c0d09
>080c0d0a
>c2020163
>bf8c007f
>10140c04
>c2020167
>bf8c007f
>d282000a
>04280905
>100e0f09
>080e0f08
>c202016b
>bf8c007f
>d282000c
>04280907
>c0820714
>bf8c007f
>e00c2000
>80010800
>c202016f
>bf8c0070
>d2820000
>0430090b
>c2020162
>bf8c007f
>10180c04
>c2020166
>bf8c007f
>d282000c
>04300905
>c202016a
>bf8c007f
>d282000c
>04300907
>c202016e
>bf8c007f
>d282000c
>0430090b
>c2020161
>bf8c007f
>101a0c04
>c2020165
>bf8c007f
>d282000d
>04340905
>c2020169
>bf8c007f
>d282000d
>04340907
>c202016d
>bf8c007f
>d282000d
>0434090b
>c2020160
>bf8c007f
>100c0c04
>c2020164
>bf8c007f
>d2820005
>04180905
>c2020168
>bf8c007f
>d2820005
>04140907
>c202016c
>bf8c007f
>d2820005
>0414090b
>f800024f
>000c0d05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..14]
>DCL TEMP[0..3]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: DP4 TEMP[1], IN[0], CONST[13]
> 15: ABS OUT[2].x, TEMP[1]
> 16: MOV OUT[2].yzw, IMM[0].xxxy
> 17: MOV OUT[3], IN[3]
> 18: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
>  %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %5)
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = extractelement <4 x float> %62, i32 1
>  %65 = extractelement <4 x float> %62, i32 2
>  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
>  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
>  %69 = extractelement <4 x float> %68, i32 0
>  %70 = extractelement <4 x float> %68, i32 1
>  %71 = extractelement <4 x float> %68, i32 2
>  %72 = extractelement <4 x float> %68, i32 3
>  %73 = fmul float %50, %11
>  %74 = fmul float %50, %12
>  %75 = fmul float %50, %13
>  %76 = fmul float %50, %14
>  %77 = fmul float %51, %15
>  %78 = fadd float %77, %73
>  %79 = fmul float %51, %16
>  %80 = fadd float %79, %74
>  %81 = fmul float %51, %17
>  %82 = fadd float %81, %75
>  %83 = fmul float %51, %18
>  %84 = fadd float %83, %76
>  %85 = fmul float %52, %19
>  %86 = fadd float %85, %78
>  %87 = fmul float %52, %20
>  %88 = fadd float %87, %80
>  %89 = fmul float %52, %21
>  %90 = fadd float %89, %82
>  %91 = fmul float %52, %22
>  %92 = fadd float %91, %84
>  %93 = fmul float %53, %23
>  %94 = fadd float %93, %86
>  %95 = fmul float %53, %24
>  %96 = fadd float %95, %88
>  %97 = fmul float %53, %25
>  %98 = fadd float %97, %90
>  %99 = fmul float %53, %26
>  %100 = fadd float %99, %92
>  %101 = fmul float %57, %27
>  %102 = fmul float %58, %28
>  %103 = fadd float %102, %101
>  %104 = fmul float %59, %29
>  %105 = fadd float %103, %104
>  %106 = fmul float %57, %30
>  %107 = fmul float %58, %31
>  %108 = fadd float %107, %106
>  %109 = fmul float %59, %32
>  %110 = fadd float %108, %109
>  %111 = fmul float %57, %33
>  %112 = fmul float %58, %34
>  %113 = fadd float %112, %111
>  %114 = fmul float %59, %35
>  %115 = fadd float %113, %114
>  %116 = fmul float %105, %105
>  %117 = fmul float %110, %110
>  %118 = fadd float %117, %116
>  %119 = fmul float %115, %115
>  %120 = fadd float %118, %119
>  %121 = call float @fabs(float %120)
>  %122 = call float @llvm.AMDGPU.rsq(float %121)
>  %123 = fmul float %36, %39
>  %124 = fadd float %123, %63
>  %125 = fmul float %37, %40
>  %126 = fadd float %125, %64
>  %127 = fmul float %38, %41
>  %128 = fadd float %127, %65
>  %129 = call float @llvm.AMDIL.clamp.(float %124, float 0.000000e+00, float 1.000000e+00)
>  %130 = call float @llvm.AMDIL.clamp.(float %126, float 0.000000e+00, float 1.000000e+00)
>  %131 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
>  %132 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %133 = fmul float %50, %43
>  %134 = fmul float %51, %44
>  %135 = fadd float %133, %134
>  %136 = fmul float %52, %45
>  %137 = fadd float %135, %136
>  %138 = fmul float %53, %46
>  %139 = fadd float %137, %138
>  %140 = call float @fabs(float %139)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %129, float %130, float %131, float %132)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %140, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %69, float %70, float %71, float %72)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %94, float %96, float %98, float %100)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c0840700
>bf8c000f
>e00c2000
>80020100
>c2020135
>bf8c0070
>100a0404
>c2020134
>bf8c007f
>d2820005
>04140901
>c2020136
>bf8c007f
>d2820005
>04140903
>c2020137
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], CONST[2], IN[0]
>  1: MOV TEMP[1].xy, IN[2].xyyy
>  2: MOV TEMP[1].w, IN[2].wwww
>  3: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  4: MUL_SAT TEMP[2], TEMP[0], IMM[0].xxxy
>  5: MUL TEMP[1].xyz, TEMP[1], TEMP[2]
>  6: MOV TEMP[1].xyz, TEMP[1].xyzx
>  7: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
>  8: MOV TEMP[1].w, TEMP[0].wwww
>  9: MUL_SAT TEMP[0], TEMP[1], IMM[0].xxxy
> 10: MOV TEMP[1].w, TEMP[0]
> 11: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[1].xxxx, CONST[1].yyyy
> 12: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
> 13: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
> 14: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 15: MOV OUT[0], TEMP[1]
> 16: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %43 = fmul float %24, %35
>  %44 = fmul float %25, %36
>  %45 = fmul float %26, %37
>  %46 = fmul float %27, %38
>  %47 = fdiv float %40, %42
>  %48 = fdiv float %41, %42
>  %49 = bitcast float %47 to i32
>  %50 = bitcast float %48 to i32
>  %51 = insertelement <2 x i32> undef, i32 %49, i32 0
>  %52 = insertelement <2 x i32> %51, i32 %50, i32 1
>  %53 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %52, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %54 = extractelement <4 x float> %53, i32 0
>  %55 = extractelement <4 x float> %53, i32 1
>  %56 = extractelement <4 x float> %53, i32 2
>  %57 = fmul float %43, 2.000000e+00
>  %58 = fmul float %44, 2.000000e+00
>  %59 = fmul float %45, 2.000000e+00
>  %60 = fmul float %46, 1.000000e+00
>  %61 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %62 = call float @llvm.AMDIL.clamp.(float %58, float 0.000000e+00, float 1.000000e+00)
>  %63 = call float @llvm.AMDIL.clamp.(float %59, float 0.000000e+00, float 1.000000e+00)
>  %64 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %65 = fmul float %54, %61
>  %66 = fmul float %55, %62
>  %67 = fmul float %56, %63
>  %68 = fmul float %43, 2.000000e+00
>  %69 = fmul float %44, 2.000000e+00
>  %70 = fmul float %45, 2.000000e+00
>  %71 = fmul float %46, 1.000000e+00
>  %72 = call float @llvm.AMDIL.clamp.(float %68, float 0.000000e+00, float 1.000000e+00)
>  %73 = call float @llvm.AMDIL.clamp.(float %69, float 0.000000e+00, float 1.000000e+00)
>  %74 = call float @llvm.AMDIL.clamp.(float %70, float 0.000000e+00, float 1.000000e+00)
>  %75 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %76 = fmul float %65, 2.000000e+00
>  %77 = fmul float %66, 2.000000e+00
>  %78 = fmul float %67, 2.000000e+00
>  %79 = fmul float %75, 1.000000e+00
>  %80 = call float @llvm.AMDIL.clamp.(float %76, float 0.000000e+00, float 1.000000e+00)
>  %81 = call float @llvm.AMDIL.clamp.(float %77, float 0.000000e+00, float 1.000000e+00)
>  %82 = call float @llvm.AMDIL.clamp.(float %78, float 0.000000e+00, float 1.000000e+00)
>  %83 = call float @llvm.AMDIL.clamp.(float %79, float 0.000000e+00, float 1.000000e+00)
>  %84 = fmul float %39, %22
>  %85 = fadd float %84, %23
>  %86 = call float @llvm.AMDIL.clamp.(float %85, float 0.000000e+00, float 1.000000e+00)
>  %87 = fsub float -0.000000e+00, %86
>  %88 = fadd float 1.000000e+00, %87
>  %89 = fmul float %28, %88
>  %90 = fmul float %29, %88
>  %91 = fmul float %30, %88
>  %92 = fmul float %80, %86
>  %93 = fadd float %92, %89
>  %94 = fmul float %81, %86
>  %95 = fadd float %94, %90
>  %96 = fmul float %82, %86
>  %97 = fadd float %96, %91
>  %98 = call i32 @llvm.SI.packf16(float %93, float %95)
>  %99 = bitcast i32 %98 to float
>  %100 = call i32 @llvm.SI.packf16(float %97, float %83)
>  %101 = bitcast i32 %100 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %99, float %101, float %99, float %101)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430202
>c8140100
>c8150101
>c0800100
>bf8c0070
>c2020109
>bf8c007f
>100c0a04
>d2820005
>041a0a04
>d2060805
>02010105
>100c0b03
>d2820005
>041a0b03
>d2060807
>02010105
>c8140400
>c8150401
>c2020104
>c2028105
>bf8c007f
>7e0c0205
>d2820005
>04180905
>d2060805
>02010105
>080c0af2
>c202010d
>bf8c007f
>10100c04
>d2820007
>04220b07
>c8200000
>c8210001
>c2020108
>bf8c007f
>10121004
>d2820008
>04261004
>d2060808
>02010108
>10121102
>d2820008
>04261102
>d2060808
>02010108
>c202010c
>bf8c007f
>10120c04
>d2820008
>04260b08
>5e0e0f08
>c8200200
>c8210201
>c202010a
>bf8c007f
>10121004
>d2820008
>04261004
>d2060808
>02010108
>10121104
>d2820002
>04261104
>d2060802
>02010102
>c202010e
>bf8c007f
>10060c04
>d2820002
>040e0b02
>c80c0300
>c80d0301
>c200010b
>bf8c007f
>10000600
>d2060800
>02010100
>d2060800
>02010100
>5e000102
>f8001c0f
>00070007
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..33]
>DCL TEMP[0..10]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: DP3 TEMP[8], -TEMP[5], CONST[25]
> 63: SLT TEMP[9], CONST[25].wwww, TEMP[8]
> 64: POW TEMP[8], TEMP[8], CONST[24].wwww
> 65: MUL TEMP[10], TEMP[9], TEMP[8]
> 66: RCP TEMP[7].yz, TEMP[7]
> 67: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 68: DP3 TEMP[7], CONST[24], TEMP[7]
> 69: RCP TEMP[7], TEMP[7]
> 70: MUL TEMP[10], TEMP[7], TEMP[10]
> 71: SUB TEMP[7], TEMP[5], TEMP[6]
> 72: DP3 TEMP[8].x, TEMP[7], TEMP[7]
> 73: RSQ TEMP[8].x, |TEMP[8]|
> 74: MUL TEMP[7], TEMP[7], TEMP[8].xxxx
> 75: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 76: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 77: LIT TEMP[1], TEMP[2]
> 78: MUL TEMP[1], TEMP[1], TEMP[10]
> 79: MAD TEMP[3], TEMP[1].xxxx, CONST[26], TEMP[3]
> 80: MAD TEMP[3], TEMP[1].yyyy, CONST[27], TEMP[3]
> 81: MAD TEMP[3], TEMP[1].zzzz, CONST[28], TEMP[3]
> 82: SUB TEMP[5], CONST[29], TEMP[6]
> 83: DP3 TEMP[7].x, TEMP[5], TEMP[5]
> 84: RSQ TEMP[7].x, |TEMP[7]|
> 85: MUL TEMP[5], TEMP[5], TEMP[7].xxxx
> 86: DP3 TEMP[2].x, TEMP[0], CONST[29]
> 87: DP3 TEMP[2].y, TEMP[0], TEMP[5]
> 88: LIT TEMP[1], TEMP[2]
> 89: ADD TEMP[3], CONST[31], TEMP[3]
> 90: MAD TEMP[3], TEMP[1].yyyy, CONST[32], TEMP[3]
> 91: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[33], TEMP[3]
> 92: ABS OUT[2].x, TEMP[4].zzzz
> 93: MOV OUT[2].yzw, IMM[0].xxxy
> 94: MOV OUT[3], IN[2]
> 95: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 528)
>  %113 = call float @llvm.SI.load.const(<16 x i8> %10, i32 532)
>  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 536)
>  %115 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %116 = load <16 x i8> addrspace(2)* %115, !tbaa !0
>  %117 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %116, i32 0, i32 %5)
>  %118 = extractelement <4 x float> %117, i32 0
>  %119 = extractelement <4 x float> %117, i32 1
>  %120 = extractelement <4 x float> %117, i32 2
>  %121 = extractelement <4 x float> %117, i32 3
>  %122 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
>  %124 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %123, i32 0, i32 %5)
>  %125 = extractelement <4 x float> %124, i32 0
>  %126 = extractelement <4 x float> %124, i32 1
>  %127 = extractelement <4 x float> %124, i32 2
>  %128 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %129 = load <16 x i8> addrspace(2)* %128, !tbaa !0
>  %130 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %129, i32 0, i32 %5)
>  %131 = extractelement <4 x float> %130, i32 0
>  %132 = extractelement <4 x float> %130, i32 1
>  %133 = extractelement <4 x float> %130, i32 2
>  %134 = extractelement <4 x float> %130, i32 3
>  %135 = fmul float %118, %11
>  %136 = fmul float %118, %12
>  %137 = fmul float %118, %13
>  %138 = fmul float %118, %14
>  %139 = fmul float %119, %15
>  %140 = fadd float %139, %135
>  %141 = fmul float %119, %16
>  %142 = fadd float %141, %136
>  %143 = fmul float %119, %17
>  %144 = fadd float %143, %137
>  %145 = fmul float %119, %18
>  %146 = fadd float %145, %138
>  %147 = fmul float %120, %19
>  %148 = fadd float %147, %140
>  %149 = fmul float %120, %20
>  %150 = fadd float %149, %142
>  %151 = fmul float %120, %21
>  %152 = fadd float %151, %144
>  %153 = fmul float %120, %22
>  %154 = fadd float %153, %146
>  %155 = fmul float %121, %23
>  %156 = fadd float %155, %148
>  %157 = fmul float %121, %24
>  %158 = fadd float %157, %150
>  %159 = fmul float %121, %25
>  %160 = fadd float %159, %152
>  %161 = fmul float %121, %26
>  %162 = fadd float %161, %154
>  %163 = fmul float %125, %27
>  %164 = fmul float %126, %28
>  %165 = fadd float %164, %163
>  %166 = fmul float %127, %29
>  %167 = fadd float %165, %166
>  %168 = fmul float %125, %30
>  %169 = fmul float %126, %31
>  %170 = fadd float %169, %168
>  %171 = fmul float %127, %32
>  %172 = fadd float %170, %171
>  %173 = fmul float %125, %33
>  %174 = fmul float %126, %34
>  %175 = fadd float %174, %173
>  %176 = fmul float %127, %35
>  %177 = fadd float %175, %176
>  %178 = fmul float %167, %167
>  %179 = fmul float %172, %172
>  %180 = fadd float %179, %178
>  %181 = fmul float %177, %177
>  %182 = fadd float %180, %181
>  %183 = call float @fabs(float %182)
>  %184 = call float @llvm.AMDGPU.rsq(float %183)
>  %185 = fmul float %167, %184
>  %186 = fmul float %172, %184
>  %187 = fmul float %177, %184
>  %188 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %189 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %190 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %191 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %192 = fmul float %118, %44
>  %193 = fmul float %118, %45
>  %194 = fmul float %118, %46
>  %195 = fmul float %119, %47
>  %196 = fadd float %195, %192
>  %197 = fmul float %119, %48
>  %198 = fadd float %197, %193
>  %199 = fmul float %119, %49
>  %200 = fadd float %199, %194
>  %201 = fmul float %120, %50
>  %202 = fadd float %201, %196
>  %203 = fmul float %120, %51
>  %204 = fadd float %203, %198
>  %205 = fmul float %120, %52
>  %206 = fadd float %205, %200
>  %207 = fmul float %121, %53
>  %208 = fadd float %207, %202
>  %209 = fmul float %121, %54
>  %210 = fadd float %209, %204
>  %211 = fmul float %121, %55
>  %212 = fadd float %211, %206
>  %213 = fsub float %41, %208
>  %214 = fsub float %42, %210
>  %215 = fsub float %43, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fdiv float 1.000000e+00, %222
>  %227 = fmul float %222, %226
>  %228 = fmul float %226, %226
>  %229 = fmul float %56, %227
>  %230 = fmul float %57, %226
>  %231 = fadd float %230, %229
>  %232 = fmul float %58, %228
>  %233 = fadd float %231, %232
>  %234 = fdiv float 1.000000e+00, %233
>  %235 = fmul float %208, %208
>  %236 = fmul float %210, %210
>  %237 = fadd float %236, %235
>  %238 = fmul float %212, %212
>  %239 = fadd float %237, %238
>  %240 = call float @fabs(float %239)
>  %241 = call float @llvm.AMDGPU.rsq(float %240)
>  %242 = fmul float %208, %241
>  %243 = fmul float %210, %241
>  %244 = fmul float %212, %241
>  %245 = fsub float %223, %242
>  %246 = fsub float %224, %243
>  %247 = fsub float %225, %244
>  %248 = fmul float %245, %245
>  %249 = fmul float %246, %246
>  %250 = fadd float %249, %248
>  %251 = fmul float %247, %247
>  %252 = fadd float %250, %251
>  %253 = call float @fabs(float %252)
>  %254 = call float @llvm.AMDGPU.rsq(float %253)
>  %255 = fmul float %245, %254
>  %256 = fmul float %246, %254
>  %257 = fmul float %247, %254
>  %258 = fmul float %185, %223
>  %259 = fmul float %186, %224
>  %260 = fadd float %259, %258
>  %261 = fmul float %187, %225
>  %262 = fadd float %260, %261
>  %263 = fmul float %185, %255
>  %264 = fmul float %186, %256
>  %265 = fadd float %264, %263
>  %266 = fmul float %187, %257
>  %267 = fadd float %265, %266
>  %268 = fcmp uge float %262, 0.000000e+00
>  %269 = select i1 %268, float %262, float 0.000000e+00
>  %270 = fcmp uge float %267, 0.000000e+00
>  %271 = select i1 %270, float %267, float 0.000000e+00
>  %272 = call float @llvm.pow.f32(float %271, float %36)
>  %273 = call float @llvm.AMDGPU.cndlt(float %262, float 0.000000e+00, float %272)
>  %274 = fmul float 1.000000e+00, %234
>  %275 = fmul float %269, %234
>  %276 = fmul float %273, %234
>  %277 = fmul float %274, %59
>  %278 = fadd float %277, %37
>  %279 = fmul float %274, %60
>  %280 = fadd float %279, %38
>  %281 = fmul float %274, %61
>  %282 = fadd float %281, %39
>  %283 = fmul float %275, %62
>  %284 = fadd float %283, %278
>  %285 = fmul float %275, %63
>  %286 = fadd float %285, %280
>  %287 = fmul float %275, %64
>  %288 = fadd float %287, %282
>  %289 = fmul float %276, %65
>  %290 = fadd float %289, %284
>  %291 = fmul float %276, %66
>  %292 = fadd float %291, %286
>  %293 = fmul float %276, %67
>  %294 = fadd float %293, %288
>  %295 = fsub float %68, %208
>  %296 = fsub float %69, %210
>  %297 = fsub float %70, %212
>  %298 = fmul float %295, %295
>  %299 = fmul float %296, %296
>  %300 = fadd float %299, %298
>  %301 = fmul float %297, %297
>  %302 = fadd float %300, %301
>  %303 = call float @fabs(float %302)
>  %304 = call float @llvm.AMDGPU.rsq(float %303)
>  %305 = fmul float %295, %304
>  %306 = fmul float %296, %304
>  %307 = fmul float %297, %304
>  %308 = fdiv float 1.000000e+00, %304
>  %309 = fmul float %304, %308
>  %310 = fmul float %308, %308
>  %311 = fmul float %71, %309
>  %312 = fmul float %72, %308
>  %313 = fadd float %312, %311
>  %314 = fmul float %73, %310
>  %315 = fadd float %313, %314
>  %316 = fdiv float 1.000000e+00, %315
>  %317 = fsub float %305, %242
>  %318 = fsub float %306, %243
>  %319 = fsub float %307, %244
>  %320 = fmul float %317, %317
>  %321 = fmul float %318, %318
>  %322 = fadd float %321, %320
>  %323 = fmul float %319, %319
>  %324 = fadd float %322, %323
>  %325 = call float @fabs(float %324)
>  %326 = call float @llvm.AMDGPU.rsq(float %325)
>  %327 = fmul float %317, %326
>  %328 = fmul float %318, %326
>  %329 = fmul float %319, %326
>  %330 = fmul float %185, %305
>  %331 = fmul float %186, %306
>  %332 = fadd float %331, %330
>  %333 = fmul float %187, %307
>  %334 = fadd float %332, %333
>  %335 = fmul float %185, %327
>  %336 = fmul float %186, %328
>  %337 = fadd float %336, %335
>  %338 = fmul float %187, %329
>  %339 = fadd float %337, %338
>  %340 = fcmp uge float %334, 0.000000e+00
>  %341 = select i1 %340, float %334, float 0.000000e+00
>  %342 = fcmp uge float %339, 0.000000e+00
>  %343 = select i1 %342, float %339, float 0.000000e+00
>  %344 = call float @llvm.pow.f32(float %343, float %36)
>  %345 = call float @llvm.AMDGPU.cndlt(float %334, float 0.000000e+00, float %344)
>  %346 = fmul float 1.000000e+00, %316
>  %347 = fmul float %341, %316
>  %348 = fmul float %345, %316
>  %349 = fmul float %346, %74
>  %350 = fadd float %349, %290
>  %351 = fmul float %346, %75
>  %352 = fadd float %351, %292
>  %353 = fmul float %346, %76
>  %354 = fadd float %353, %294
>  %355 = fmul float %347, %77
>  %356 = fadd float %355, %350
>  %357 = fmul float %347, %78
>  %358 = fadd float %357, %352
>  %359 = fmul float %347, %79
>  %360 = fadd float %359, %354
>  %361 = fmul float %348, %80
>  %362 = fadd float %361, %356
>  %363 = fmul float %348, %81
>  %364 = fadd float %363, %358
>  %365 = fmul float %348, %82
>  %366 = fadd float %365, %360
>  %367 = fsub float %83, %208
>  %368 = fsub float %84, %210
>  %369 = fsub float %85, %212
>  %370 = fmul float %367, %367
>  %371 = fmul float %368, %368
>  %372 = fadd float %371, %370
>  %373 = fmul float %369, %369
>  %374 = fadd float %372, %373
>  %375 = call float @fabs(float %374)
>  %376 = call float @llvm.AMDGPU.rsq(float %375)
>  %377 = fmul float %367, %376
>  %378 = fmul float %368, %376
>  %379 = fmul float %369, %376
>  %380 = fsub float -0.000000e+00, %377
>  %381 = fsub float -0.000000e+00, %378
>  %382 = fsub float -0.000000e+00, %379
>  %383 = fmul float %380, %90
>  %384 = fmul float %381, %91
>  %385 = fadd float %384, %383
>  %386 = fmul float %382, %92
>  %387 = fadd float %385, %386
>  %388 = fcmp olt float %93, %387
>  %389 = select i1 %388, float 1.000000e+00, float 0.000000e+00
>  %390 = fcmp olt float %93, %387
>  %391 = select i1 %390, float 1.000000e+00, float 0.000000e+00
>  %392 = fcmp olt float %93, %387
>  %393 = select i1 %392, float 1.000000e+00, float 0.000000e+00
>  %394 = call float @llvm.pow.f32(float %387, float %89)
>  %395 = fmul float %389, %394
>  %396 = fmul float %391, %394
>  %397 = fmul float %393, %394
>  %398 = fdiv float 1.000000e+00, %376
>  %399 = fmul float %376, %398
>  %400 = fmul float %398, %398
>  %401 = fmul float %86, %399
>  %402 = fmul float %87, %398
>  %403 = fadd float %402, %401
>  %404 = fmul float %88, %400
>  %405 = fadd float %403, %404
>  %406 = fdiv float 1.000000e+00, %405
>  %407 = fmul float %406, %395
>  %408 = fmul float %406, %396
>  %409 = fmul float %406, %397
>  %410 = fsub float %377, %242
>  %411 = fsub float %378, %243
>  %412 = fsub float %379, %244
>  %413 = fmul float %410, %410
>  %414 = fmul float %411, %411
>  %415 = fadd float %414, %413
>  %416 = fmul float %412, %412
>  %417 = fadd float %415, %416
>  %418 = call float @fabs(float %417)
>  %419 = call float @llvm.AMDGPU.rsq(float %418)
>  %420 = fmul float %410, %419
>  %421 = fmul float %411, %419
>  %422 = fmul float %412, %419
>  %423 = fmul float %185, %377
>  %424 = fmul float %186, %378
>  %425 = fadd float %424, %423
>  %426 = fmul float %187, %379
>  %427 = fadd float %425, %426
>  %428 = fmul float %185, %420
>  %429 = fmul float %186, %421
>  %430 = fadd float %429, %428
>  %431 = fmul float %187, %422
>  %432 = fadd float %430, %431
>  %433 = fcmp uge float %427, 0.000000e+00
>  %434 = select i1 %433, float %427, float 0.000000e+00
>  %435 = fcmp uge float %432, 0.000000e+00
>  %436 = select i1 %435, float %432, float 0.000000e+00
>  %437 = call float @llvm.pow.f32(float %436, float %36)
>  %438 = call float @llvm.AMDGPU.cndlt(float %427, float 0.000000e+00, float %437)
>  %439 = fmul float 1.000000e+00, %407
>  %440 = fmul float %434, %408
>  %441 = fmul float %438, %409
>  %442 = fmul float %439, %94
>  %443 = fadd float %442, %362
>  %444 = fmul float %439, %95
>  %445 = fadd float %444, %364
>  %446 = fmul float %439, %96
>  %447 = fadd float %446, %366
>  %448 = fmul float %440, %97
>  %449 = fadd float %448, %443
>  %450 = fmul float %440, %98
>  %451 = fadd float %450, %445
>  %452 = fmul float %440, %99
>  %453 = fadd float %452, %447
>  %454 = fmul float %441, %100
>  %455 = fadd float %454, %449
>  %456 = fmul float %441, %101
>  %457 = fadd float %456, %451
>  %458 = fmul float %441, %102
>  %459 = fadd float %458, %453
>  %460 = fsub float %103, %242
>  %461 = fsub float %104, %243
>  %462 = fsub float %105, %244
>  %463 = fmul float %460, %460
>  %464 = fmul float %461, %461
>  %465 = fadd float %464, %463
>  %466 = fmul float %462, %462
>  %467 = fadd float %465, %466
>  %468 = call float @fabs(float %467)
>  %469 = call float @llvm.AMDGPU.rsq(float %468)
>  %470 = fmul float %460, %469
>  %471 = fmul float %461, %469
>  %472 = fmul float %462, %469
>  %473 = fmul float %185, %103
>  %474 = fmul float %186, %104
>  %475 = fadd float %474, %473
>  %476 = fmul float %187, %105
>  %477 = fadd float %475, %476
>  %478 = fmul float %185, %470
>  %479 = fmul float %186, %471
>  %480 = fadd float %479, %478
>  %481 = fmul float %187, %472
>  %482 = fadd float %480, %481
>  %483 = fcmp uge float %477, 0.000000e+00
>  %484 = select i1 %483, float %477, float 0.000000e+00
>  %485 = fcmp uge float %482, 0.000000e+00
>  %486 = select i1 %485, float %482, float 0.000000e+00
>  %487 = call float @llvm.pow.f32(float %486, float %36)
>  %488 = call float @llvm.AMDGPU.cndlt(float %477, float 0.000000e+00, float %487)
>  %489 = fadd float %106, %455
>  %490 = fadd float %107, %457
>  %491 = fadd float %108, %459
>  %492 = fmul float %484, %109
>  %493 = fadd float %492, %489
>  %494 = fmul float %484, %110
>  %495 = fadd float %494, %490
>  %496 = fmul float %484, %111
>  %497 = fadd float %496, %491
>  %498 = fmul float %488, %112
>  %499 = fadd float %498, %493
>  %500 = fmul float %488, %113
>  %501 = fadd float %500, %495
>  %502 = fmul float %488, %114
>  %503 = fadd float %502, %497
>  %504 = call float @llvm.AMDIL.clamp.(float %499, float 0.000000e+00, float 1.000000e+00)
>  %505 = call float @llvm.AMDIL.clamp.(float %501, float 0.000000e+00, float 1.000000e+00)
>  %506 = call float @llvm.AMDIL.clamp.(float %503, float 0.000000e+00, float 1.000000e+00)
>  %507 = call float @fabs(float %212)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %504, float %505, float %506, float %191)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %507, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %131, float %132, float %133, float %134)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %156, float %158, float %160, float %162)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
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>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..32]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD TEMP[3], TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: SUB TEMP[5], CONST[28], TEMP[6]
> 78: DP3 TEMP[7].x, TEMP[5], TEMP[5]
> 79: RSQ TEMP[7].x, |TEMP[7]|
> 80: MUL TEMP[5], TEMP[5], TEMP[7].xxxx
> 81: DP3 TEMP[2].x, TEMP[0], CONST[28]
> 82: DP3 TEMP[2].y, TEMP[0], TEMP[5]
> 83: LIT TEMP[1], TEMP[2]
> 84: ADD TEMP[3], CONST[30], TEMP[3]
> 85: MAD TEMP[3], TEMP[1].yyyy, CONST[31], TEMP[3]
> 86: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[32], TEMP[3]
> 87: ABS OUT[2].x, TEMP[4].zzzz
> 88: MOV OUT[2].yzw, IMM[0].xxxy
> 89: MOV OUT[3], IN[2]
> 90: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %110 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %111 = load <16 x i8> addrspace(2)* %110, !tbaa !0
>  %112 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %111, i32 0, i32 %5)
>  %113 = extractelement <4 x float> %112, i32 0
>  %114 = extractelement <4 x float> %112, i32 1
>  %115 = extractelement <4 x float> %112, i32 2
>  %116 = extractelement <4 x float> %112, i32 3
>  %117 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %118 = load <16 x i8> addrspace(2)* %117, !tbaa !0
>  %119 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %118, i32 0, i32 %5)
>  %120 = extractelement <4 x float> %119, i32 0
>  %121 = extractelement <4 x float> %119, i32 1
>  %122 = extractelement <4 x float> %119, i32 2
>  %123 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %124 = load <16 x i8> addrspace(2)* %123, !tbaa !0
>  %125 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %124, i32 0, i32 %5)
>  %126 = extractelement <4 x float> %125, i32 0
>  %127 = extractelement <4 x float> %125, i32 1
>  %128 = extractelement <4 x float> %125, i32 2
>  %129 = extractelement <4 x float> %125, i32 3
>  %130 = fmul float %113, %11
>  %131 = fmul float %113, %12
>  %132 = fmul float %113, %13
>  %133 = fmul float %113, %14
>  %134 = fmul float %114, %15
>  %135 = fadd float %134, %130
>  %136 = fmul float %114, %16
>  %137 = fadd float %136, %131
>  %138 = fmul float %114, %17
>  %139 = fadd float %138, %132
>  %140 = fmul float %114, %18
>  %141 = fadd float %140, %133
>  %142 = fmul float %115, %19
>  %143 = fadd float %142, %135
>  %144 = fmul float %115, %20
>  %145 = fadd float %144, %137
>  %146 = fmul float %115, %21
>  %147 = fadd float %146, %139
>  %148 = fmul float %115, %22
>  %149 = fadd float %148, %141
>  %150 = fmul float %116, %23
>  %151 = fadd float %150, %143
>  %152 = fmul float %116, %24
>  %153 = fadd float %152, %145
>  %154 = fmul float %116, %25
>  %155 = fadd float %154, %147
>  %156 = fmul float %116, %26
>  %157 = fadd float %156, %149
>  %158 = fmul float %120, %27
>  %159 = fmul float %121, %28
>  %160 = fadd float %159, %158
>  %161 = fmul float %122, %29
>  %162 = fadd float %160, %161
>  %163 = fmul float %120, %30
>  %164 = fmul float %121, %31
>  %165 = fadd float %164, %163
>  %166 = fmul float %122, %32
>  %167 = fadd float %165, %166
>  %168 = fmul float %120, %33
>  %169 = fmul float %121, %34
>  %170 = fadd float %169, %168
>  %171 = fmul float %122, %35
>  %172 = fadd float %170, %171
>  %173 = fmul float %162, %162
>  %174 = fmul float %167, %167
>  %175 = fadd float %174, %173
>  %176 = fmul float %172, %172
>  %177 = fadd float %175, %176
>  %178 = call float @fabs(float %177)
>  %179 = call float @llvm.AMDGPU.rsq(float %178)
>  %180 = fmul float %162, %179
>  %181 = fmul float %167, %179
>  %182 = fmul float %172, %179
>  %183 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %184 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %185 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %186 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %187 = fmul float %113, %44
>  %188 = fmul float %113, %45
>  %189 = fmul float %113, %46
>  %190 = fmul float %114, %47
>  %191 = fadd float %190, %187
>  %192 = fmul float %114, %48
>  %193 = fadd float %192, %188
>  %194 = fmul float %114, %49
>  %195 = fadd float %194, %189
>  %196 = fmul float %115, %50
>  %197 = fadd float %196, %191
>  %198 = fmul float %115, %51
>  %199 = fadd float %198, %193
>  %200 = fmul float %115, %52
>  %201 = fadd float %200, %195
>  %202 = fmul float %116, %53
>  %203 = fadd float %202, %197
>  %204 = fmul float %116, %54
>  %205 = fadd float %204, %199
>  %206 = fmul float %116, %55
>  %207 = fadd float %206, %201
>  %208 = fsub float %41, %203
>  %209 = fsub float %42, %205
>  %210 = fsub float %43, %207
>  %211 = fmul float %208, %208
>  %212 = fmul float %209, %209
>  %213 = fadd float %212, %211
>  %214 = fmul float %210, %210
>  %215 = fadd float %213, %214
>  %216 = call float @fabs(float %215)
>  %217 = call float @llvm.AMDGPU.rsq(float %216)
>  %218 = fmul float %208, %217
>  %219 = fmul float %209, %217
>  %220 = fmul float %210, %217
>  %221 = fdiv float 1.000000e+00, %217
>  %222 = fmul float %217, %221
>  %223 = fmul float %221, %221
>  %224 = fmul float %56, %222
>  %225 = fmul float %57, %221
>  %226 = fadd float %225, %224
>  %227 = fmul float %58, %223
>  %228 = fadd float %226, %227
>  %229 = fdiv float 1.000000e+00, %228
>  %230 = fmul float %203, %203
>  %231 = fmul float %205, %205
>  %232 = fadd float %231, %230
>  %233 = fmul float %207, %207
>  %234 = fadd float %232, %233
>  %235 = call float @fabs(float %234)
>  %236 = call float @llvm.AMDGPU.rsq(float %235)
>  %237 = fmul float %203, %236
>  %238 = fmul float %205, %236
>  %239 = fmul float %207, %236
>  %240 = fsub float %218, %237
>  %241 = fsub float %219, %238
>  %242 = fsub float %220, %239
>  %243 = fmul float %240, %240
>  %244 = fmul float %241, %241
>  %245 = fadd float %244, %243
>  %246 = fmul float %242, %242
>  %247 = fadd float %245, %246
>  %248 = call float @fabs(float %247)
>  %249 = call float @llvm.AMDGPU.rsq(float %248)
>  %250 = fmul float %240, %249
>  %251 = fmul float %241, %249
>  %252 = fmul float %242, %249
>  %253 = fmul float %180, %218
>  %254 = fmul float %181, %219
>  %255 = fadd float %254, %253
>  %256 = fmul float %182, %220
>  %257 = fadd float %255, %256
>  %258 = fmul float %180, %250
>  %259 = fmul float %181, %251
>  %260 = fadd float %259, %258
>  %261 = fmul float %182, %252
>  %262 = fadd float %260, %261
>  %263 = fcmp uge float %257, 0.000000e+00
>  %264 = select i1 %263, float %257, float 0.000000e+00
>  %265 = fcmp uge float %262, 0.000000e+00
>  %266 = select i1 %265, float %262, float 0.000000e+00
>  %267 = call float @llvm.pow.f32(float %266, float %36)
>  %268 = call float @llvm.AMDGPU.cndlt(float %257, float 0.000000e+00, float %267)
>  %269 = fmul float 1.000000e+00, %229
>  %270 = fmul float %264, %229
>  %271 = fmul float %268, %229
>  %272 = fmul float %269, %59
>  %273 = fadd float %272, %37
>  %274 = fmul float %269, %60
>  %275 = fadd float %274, %38
>  %276 = fmul float %269, %61
>  %277 = fadd float %276, %39
>  %278 = fmul float %270, %62
>  %279 = fadd float %278, %273
>  %280 = fmul float %270, %63
>  %281 = fadd float %280, %275
>  %282 = fmul float %270, %64
>  %283 = fadd float %282, %277
>  %284 = fmul float %271, %65
>  %285 = fadd float %284, %279
>  %286 = fmul float %271, %66
>  %287 = fadd float %286, %281
>  %288 = fmul float %271, %67
>  %289 = fadd float %288, %283
>  %290 = fsub float %68, %203
>  %291 = fsub float %69, %205
>  %292 = fsub float %70, %207
>  %293 = fmul float %290, %290
>  %294 = fmul float %291, %291
>  %295 = fadd float %294, %293
>  %296 = fmul float %292, %292
>  %297 = fadd float %295, %296
>  %298 = call float @fabs(float %297)
>  %299 = call float @llvm.AMDGPU.rsq(float %298)
>  %300 = fmul float %290, %299
>  %301 = fmul float %291, %299
>  %302 = fmul float %292, %299
>  %303 = fdiv float 1.000000e+00, %299
>  %304 = fmul float %299, %303
>  %305 = fmul float %303, %303
>  %306 = fmul float %71, %304
>  %307 = fmul float %72, %303
>  %308 = fadd float %307, %306
>  %309 = fmul float %73, %305
>  %310 = fadd float %308, %309
>  %311 = fdiv float 1.000000e+00, %310
>  %312 = fsub float %300, %237
>  %313 = fsub float %301, %238
>  %314 = fsub float %302, %239
>  %315 = fmul float %312, %312
>  %316 = fmul float %313, %313
>  %317 = fadd float %316, %315
>  %318 = fmul float %314, %314
>  %319 = fadd float %317, %318
>  %320 = call float @fabs(float %319)
>  %321 = call float @llvm.AMDGPU.rsq(float %320)
>  %322 = fmul float %312, %321
>  %323 = fmul float %313, %321
>  %324 = fmul float %314, %321
>  %325 = fmul float %180, %300
>  %326 = fmul float %181, %301
>  %327 = fadd float %326, %325
>  %328 = fmul float %182, %302
>  %329 = fadd float %327, %328
>  %330 = fmul float %180, %322
>  %331 = fmul float %181, %323
>  %332 = fadd float %331, %330
>  %333 = fmul float %182, %324
>  %334 = fadd float %332, %333
>  %335 = fcmp uge float %329, 0.000000e+00
>  %336 = select i1 %335, float %329, float 0.000000e+00
>  %337 = fcmp uge float %334, 0.000000e+00
>  %338 = select i1 %337, float %334, float 0.000000e+00
>  %339 = call float @llvm.pow.f32(float %338, float %36)
>  %340 = call float @llvm.AMDGPU.cndlt(float %329, float 0.000000e+00, float %339)
>  %341 = fmul float 1.000000e+00, %311
>  %342 = fmul float %336, %311
>  %343 = fmul float %340, %311
>  %344 = fmul float %341, %74
>  %345 = fadd float %344, %285
>  %346 = fmul float %341, %75
>  %347 = fadd float %346, %287
>  %348 = fmul float %341, %76
>  %349 = fadd float %348, %289
>  %350 = fmul float %342, %77
>  %351 = fadd float %350, %345
>  %352 = fmul float %342, %78
>  %353 = fadd float %352, %347
>  %354 = fmul float %342, %79
>  %355 = fadd float %354, %349
>  %356 = fmul float %343, %80
>  %357 = fadd float %356, %351
>  %358 = fmul float %343, %81
>  %359 = fadd float %358, %353
>  %360 = fmul float %343, %82
>  %361 = fadd float %360, %355
>  %362 = fsub float %83, %203
>  %363 = fsub float %84, %205
>  %364 = fsub float %85, %207
>  %365 = fmul float %362, %362
>  %366 = fmul float %363, %363
>  %367 = fadd float %366, %365
>  %368 = fmul float %364, %364
>  %369 = fadd float %367, %368
>  %370 = call float @fabs(float %369)
>  %371 = call float @llvm.AMDGPU.rsq(float %370)
>  %372 = fmul float %362, %371
>  %373 = fmul float %363, %371
>  %374 = fmul float %364, %371
>  %375 = fdiv float 1.000000e+00, %371
>  %376 = fmul float %371, %375
>  %377 = fmul float %375, %375
>  %378 = fmul float %86, %376
>  %379 = fmul float %87, %375
>  %380 = fadd float %379, %378
>  %381 = fmul float %88, %377
>  %382 = fadd float %380, %381
>  %383 = fdiv float 1.000000e+00, %382
>  %384 = fsub float %372, %237
>  %385 = fsub float %373, %238
>  %386 = fsub float %374, %239
>  %387 = fmul float %384, %384
>  %388 = fmul float %385, %385
>  %389 = fadd float %388, %387
>  %390 = fmul float %386, %386
>  %391 = fadd float %389, %390
>  %392 = call float @fabs(float %391)
>  %393 = call float @llvm.AMDGPU.rsq(float %392)
>  %394 = fmul float %384, %393
>  %395 = fmul float %385, %393
>  %396 = fmul float %386, %393
>  %397 = fmul float %180, %372
>  %398 = fmul float %181, %373
>  %399 = fadd float %398, %397
>  %400 = fmul float %182, %374
>  %401 = fadd float %399, %400
>  %402 = fmul float %180, %394
>  %403 = fmul float %181, %395
>  %404 = fadd float %403, %402
>  %405 = fmul float %182, %396
>  %406 = fadd float %404, %405
>  %407 = fcmp uge float %401, 0.000000e+00
>  %408 = select i1 %407, float %401, float 0.000000e+00
>  %409 = fcmp uge float %406, 0.000000e+00
>  %410 = select i1 %409, float %406, float 0.000000e+00
>  %411 = call float @llvm.pow.f32(float %410, float %36)
>  %412 = call float @llvm.AMDGPU.cndlt(float %401, float 0.000000e+00, float %411)
>  %413 = fmul float 1.000000e+00, %383
>  %414 = fmul float %408, %383
>  %415 = fmul float %412, %383
>  %416 = fmul float %413, %89
>  %417 = fadd float %416, %357
>  %418 = fmul float %413, %90
>  %419 = fadd float %418, %359
>  %420 = fmul float %413, %91
>  %421 = fadd float %420, %361
>  %422 = fmul float %414, %92
>  %423 = fadd float %422, %417
>  %424 = fmul float %414, %93
>  %425 = fadd float %424, %419
>  %426 = fmul float %414, %94
>  %427 = fadd float %426, %421
>  %428 = fmul float %415, %95
>  %429 = fadd float %428, %423
>  %430 = fmul float %415, %96
>  %431 = fadd float %430, %425
>  %432 = fmul float %415, %97
>  %433 = fadd float %432, %427
>  %434 = fsub float %98, %237
>  %435 = fsub float %99, %238
>  %436 = fsub float %100, %239
>  %437 = fmul float %434, %434
>  %438 = fmul float %435, %435
>  %439 = fadd float %438, %437
>  %440 = fmul float %436, %436
>  %441 = fadd float %439, %440
>  %442 = call float @fabs(float %441)
>  %443 = call float @llvm.AMDGPU.rsq(float %442)
>  %444 = fmul float %434, %443
>  %445 = fmul float %435, %443
>  %446 = fmul float %436, %443
>  %447 = fmul float %180, %98
>  %448 = fmul float %181, %99
>  %449 = fadd float %448, %447
>  %450 = fmul float %182, %100
>  %451 = fadd float %449, %450
>  %452 = fmul float %180, %444
>  %453 = fmul float %181, %445
>  %454 = fadd float %453, %452
>  %455 = fmul float %182, %446
>  %456 = fadd float %454, %455
>  %457 = fcmp uge float %451, 0.000000e+00
>  %458 = select i1 %457, float %451, float 0.000000e+00
>  %459 = fcmp uge float %456, 0.000000e+00
>  %460 = select i1 %459, float %456, float 0.000000e+00
>  %461 = call float @llvm.pow.f32(float %460, float %36)
>  %462 = call float @llvm.AMDGPU.cndlt(float %451, float 0.000000e+00, float %461)
>  %463 = fadd float %101, %429
>  %464 = fadd float %102, %431
>  %465 = fadd float %103, %433
>  %466 = fmul float %458, %104
>  %467 = fadd float %466, %463
>  %468 = fmul float %458, %105
>  %469 = fadd float %468, %464
>  %470 = fmul float %458, %106
>  %471 = fadd float %470, %465
>  %472 = fmul float %462, %107
>  %473 = fadd float %472, %467
>  %474 = fmul float %462, %108
>  %475 = fadd float %474, %469
>  %476 = fmul float %462, %109
>  %477 = fadd float %476, %471
>  %478 = call float @llvm.AMDIL.clamp.(float %473, float 0.000000e+00, float 1.000000e+00)
>  %479 = call float @llvm.AMDIL.clamp.(float %475, float 0.000000e+00, float 1.000000e+00)
>  %480 = call float @llvm.AMDIL.clamp.(float %477, float 0.000000e+00, float 1.000000e+00)
>  %481 = call float @fabs(float %207)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %478, float %479, float %480, float %186)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %481, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %126, float %127, float %128, float %129)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %151, float %153, float %155, float %157)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
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>02010107
>c2020123
>bf8c007f
>d2060809
>02010004
>f800020f
>09060807
>d2060105
>02010105
>bf8c070f
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL IN[3], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    2.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV TEMP[1].xy, IN[3].xyyy
>  5: MOV TEMP[1].w, IN[3].wwww
>  6: TXP TEMP[1], TEMP[1], SAMP[0], 2D
>  7: MUL_SAT TEMP[2], TEMP[0], IMM[0].xxxy
>  8: MUL_SAT TEMP[3], TEMP[0], IMM[0].xxxy
>  9: MAD TEMP[1].xyz, TEMP[1], TEMP[2].wwww, TEMP[3]
> 10: MOV_SAT TEMP[1].xyz, TEMP[1].xyzz
> 11: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
> 12: MOV TEMP[0].w, TEMP[0].wwww
> 13: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[2].xxxx, CONST[2].yyyy
> 14: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[2].xxxx
> 15: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
> 16: MAD TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 17: MOV OUT[0], TEMP[0]
> 18: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %46 = fdiv float %40, %42
>  %47 = fdiv float %41, %42
>  %48 = bitcast float %46 to i32
>  %49 = bitcast float %47 to i32
>  %50 = insertelement <2 x i32> undef, i32 %48, i32 0
>  %51 = insertelement <2 x i32> %50, i32 %49, i32 1
>  %52 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %51, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = fmul float %53, %35
>  %58 = fmul float %54, %36
>  %59 = fmul float %55, %37
>  %60 = fmul float %56, %38
>  %61 = fdiv float %43, %45
>  %62 = fdiv float %44, %45
>  %63 = bitcast float %61 to i32
>  %64 = bitcast float %62 to i32
>  %65 = insertelement <2 x i32> undef, i32 %63, i32 0
>  %66 = insertelement <2 x i32> %65, i32 %64, i32 1
>  %67 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %66, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %68 = extractelement <4 x float> %67, i32 0
>  %69 = extractelement <4 x float> %67, i32 1
>  %70 = extractelement <4 x float> %67, i32 2
>  %71 = fmul float %57, 2.000000e+00
>  %72 = fmul float %58, 2.000000e+00
>  %73 = fmul float %59, 2.000000e+00
>  %74 = fmul float %60, 1.000000e+00
>  %75 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
>  %76 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %73, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00)
>  %79 = fmul float %57, 2.000000e+00
>  %80 = fmul float %58, 2.000000e+00
>  %81 = fmul float %59, 2.000000e+00
>  %82 = fmul float %60, 1.000000e+00
>  %83 = call float @llvm.AMDIL.clamp.(float %79, float 0.000000e+00, float 1.000000e+00)
>  %84 = call float @llvm.AMDIL.clamp.(float %80, float 0.000000e+00, float 1.000000e+00)
>  %85 = call float @llvm.AMDIL.clamp.(float %81, float 0.000000e+00, float 1.000000e+00)
>  %86 = call float @llvm.AMDIL.clamp.(float %82, float 0.000000e+00, float 1.000000e+00)
>  %87 = fmul float %68, %78
>  %88 = fadd float %87, %83
>  %89 = fmul float %69, %78
>  %90 = fadd float %89, %84
>  %91 = fmul float %70, %78
>  %92 = fadd float %91, %85
>  %93 = call float @llvm.AMDIL.clamp.(float %88, float 0.000000e+00, float 1.000000e+00)
>  %94 = call float @llvm.AMDIL.clamp.(float %90, float 0.000000e+00, float 1.000000e+00)
>  %95 = call float @llvm.AMDIL.clamp.(float %92, float 0.000000e+00, float 1.000000e+00)
>  %96 = fmul float %57, 2.000000e+00
>  %97 = fmul float %58, 2.000000e+00
>  %98 = fmul float %59, 2.000000e+00
>  %99 = fmul float %60, 1.000000e+00
>  %100 = call float @llvm.AMDIL.clamp.(float %96, float 0.000000e+00, float 1.000000e+00)
>  %101 = call float @llvm.AMDIL.clamp.(float %97, float 0.000000e+00, float 1.000000e+00)
>  %102 = call float @llvm.AMDIL.clamp.(float %98, float 0.000000e+00, float 1.000000e+00)
>  %103 = call float @llvm.AMDIL.clamp.(float %99, float 0.000000e+00, float 1.000000e+00)
>  %104 = fmul float %39, %22
>  %105 = fadd float %104, %23
>  %106 = call float @llvm.AMDIL.clamp.(float %105, float 0.000000e+00, float 1.000000e+00)
>  %107 = fsub float -0.000000e+00, %106
>  %108 = fadd float 1.000000e+00, %107
>  %109 = fmul float %24, %108
>  %110 = fmul float %25, %108
>  %111 = fmul float %26, %108
>  %112 = fmul float %93, %106
>  %113 = fadd float %112, %109
>  %114 = fmul float %94, %106
>  %115 = fadd float %114, %110
>  %116 = fmul float %95, %106
>  %117 = fadd float %116, %111
>  %118 = call i32 @llvm.SI.packf16(float %113, float %115)
>  %119 = bitcast i32 %118 to float
>  %120 = call i32 @llvm.SI.packf16(float %117, float %103)
>  %121 = bitcast i32 %120 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %119, float %121, float %119, float %121)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180100
>c8190101
>bf8c0770
>100e0d03
>d2820006
>041e0d03
>d206080a
>02010106
>c8180d00
>c8190d01
>c81c0f00
>c81d0f01
>7e105507
>100e1106
>c8240c00
>c8250c01
>100c1109
>c0840300
>c0c60500
>bf8c007f
>f0800700
>00430606
>c8240300
>c8250301
>10121305
>d2060809
>02010109
>bf8c0770
>d282000a
>042a1307
>d206080c
>0201010a
>c8280400
>c8290401
>c0800100
>bf8c007f
>c2020108
>c2028109
>bf8c007f
>7e160205
>d282000a
>042c090a
>d206080a
>0201010a
>081614f2
>c202010d
>bf8c007f
>101a1604
>d282000c
>0436150c
>c8340000
>c8350001
>101c1b02
>d282000d
>043a1b02
>d206080d
>0201010d
>d282000d
>04361306
>d206080d
>0201010d
>c202010c
>bf8c007f
>101c1604
>d282000d
>043a150d
>5e18190d
>c8340200
>c8350201
>10001b04
>d2820000
>04021b04
>d2060800
>02010100
>d2820000
>04021308
>d2060800
>02010100
>c200010e
>bf8c007f
>10021600
>d2820000
>04061500
>5e001300
>f8001c0f
>000c000c
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..33]
>DCL TEMP[0..10]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD TEMP[3], TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: SUB TEMP[5], CONST[28], TEMP[4]
> 78: DP3 TEMP[7], TEMP[5], TEMP[5]
> 79: RSQ TEMP[7], |TEMP[7]|
> 80: MUL TEMP[5], TEMP[5], TEMP[7]
> 81: DP3 TEMP[8], -TEMP[5], CONST[30]
> 82: SLT TEMP[9], CONST[30].wwww, TEMP[8]
> 83: POW TEMP[8], TEMP[8], CONST[29].wwww
> 84: MUL TEMP[10], TEMP[9], TEMP[8]
> 85: RCP TEMP[7].yz, TEMP[7]
> 86: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 87: DP3 TEMP[7], CONST[29], TEMP[7]
> 88: RCP TEMP[7], TEMP[7]
> 89: MUL TEMP[10], TEMP[7], TEMP[10]
> 90: SUB TEMP[7], TEMP[5], TEMP[6]
> 91: DP3 TEMP[8].x, TEMP[7], TEMP[7]
> 92: RSQ TEMP[8].x, |TEMP[8]|
> 93: MUL TEMP[7], TEMP[7], TEMP[8].xxxx
> 94: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 95: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 96: LIT TEMP[1], TEMP[2]
> 97: MUL TEMP[1], TEMP[1], TEMP[10]
> 98: MAD TEMP[3], TEMP[1].xxxx, CONST[31], TEMP[3]
> 99: MAD TEMP[3], TEMP[1].yyyy, CONST[32], TEMP[3]
>100: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[33], TEMP[3]
>101: ABS OUT[2].x, TEMP[4].zzzz
>102: MOV OUT[2].yzw, IMM[0].xxxy
>103: MOV OUT[3], IN[2]
>104: MOV OUT[4], IN[3]
>105: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 476)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 492)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %113 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %115 = call float @llvm.SI.load.const(<16 x i8> %10, i32 528)
>  %116 = call float @llvm.SI.load.const(<16 x i8> %10, i32 532)
>  %117 = call float @llvm.SI.load.const(<16 x i8> %10, i32 536)
>  %118 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %119 = load <16 x i8> addrspace(2)* %118, !tbaa !0
>  %120 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %119, i32 0, i32 %5)
>  %121 = extractelement <4 x float> %120, i32 0
>  %122 = extractelement <4 x float> %120, i32 1
>  %123 = extractelement <4 x float> %120, i32 2
>  %124 = extractelement <4 x float> %120, i32 3
>  %125 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %126 = load <16 x i8> addrspace(2)* %125, !tbaa !0
>  %127 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %126, i32 0, i32 %5)
>  %128 = extractelement <4 x float> %127, i32 0
>  %129 = extractelement <4 x float> %127, i32 1
>  %130 = extractelement <4 x float> %127, i32 2
>  %131 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %132 = load <16 x i8> addrspace(2)* %131, !tbaa !0
>  %133 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %132, i32 0, i32 %5)
>  %134 = extractelement <4 x float> %133, i32 0
>  %135 = extractelement <4 x float> %133, i32 1
>  %136 = extractelement <4 x float> %133, i32 2
>  %137 = extractelement <4 x float> %133, i32 3
>  %138 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %139 = load <16 x i8> addrspace(2)* %138, !tbaa !0
>  %140 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %139, i32 0, i32 %5)
>  %141 = extractelement <4 x float> %140, i32 0
>  %142 = extractelement <4 x float> %140, i32 1
>  %143 = extractelement <4 x float> %140, i32 2
>  %144 = extractelement <4 x float> %140, i32 3
>  %145 = fmul float %121, %11
>  %146 = fmul float %121, %12
>  %147 = fmul float %121, %13
>  %148 = fmul float %121, %14
>  %149 = fmul float %122, %15
>  %150 = fadd float %149, %145
>  %151 = fmul float %122, %16
>  %152 = fadd float %151, %146
>  %153 = fmul float %122, %17
>  %154 = fadd float %153, %147
>  %155 = fmul float %122, %18
>  %156 = fadd float %155, %148
>  %157 = fmul float %123, %19
>  %158 = fadd float %157, %150
>  %159 = fmul float %123, %20
>  %160 = fadd float %159, %152
>  %161 = fmul float %123, %21
>  %162 = fadd float %161, %154
>  %163 = fmul float %123, %22
>  %164 = fadd float %163, %156
>  %165 = fmul float %124, %23
>  %166 = fadd float %165, %158
>  %167 = fmul float %124, %24
>  %168 = fadd float %167, %160
>  %169 = fmul float %124, %25
>  %170 = fadd float %169, %162
>  %171 = fmul float %124, %26
>  %172 = fadd float %171, %164
>  %173 = fmul float %128, %27
>  %174 = fmul float %129, %28
>  %175 = fadd float %174, %173
>  %176 = fmul float %130, %29
>  %177 = fadd float %175, %176
>  %178 = fmul float %128, %30
>  %179 = fmul float %129, %31
>  %180 = fadd float %179, %178
>  %181 = fmul float %130, %32
>  %182 = fadd float %180, %181
>  %183 = fmul float %128, %33
>  %184 = fmul float %129, %34
>  %185 = fadd float %184, %183
>  %186 = fmul float %130, %35
>  %187 = fadd float %185, %186
>  %188 = fmul float %177, %177
>  %189 = fmul float %182, %182
>  %190 = fadd float %189, %188
>  %191 = fmul float %187, %187
>  %192 = fadd float %190, %191
>  %193 = call float @fabs(float %192)
>  %194 = call float @llvm.AMDGPU.rsq(float %193)
>  %195 = fmul float %177, %194
>  %196 = fmul float %182, %194
>  %197 = fmul float %187, %194
>  %198 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %199 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %200 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %201 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %202 = fmul float %121, %44
>  %203 = fmul float %121, %45
>  %204 = fmul float %121, %46
>  %205 = fmul float %122, %47
>  %206 = fadd float %205, %202
>  %207 = fmul float %122, %48
>  %208 = fadd float %207, %203
>  %209 = fmul float %122, %49
>  %210 = fadd float %209, %204
>  %211 = fmul float %123, %50
>  %212 = fadd float %211, %206
>  %213 = fmul float %123, %51
>  %214 = fadd float %213, %208
>  %215 = fmul float %123, %52
>  %216 = fadd float %215, %210
>  %217 = fmul float %124, %53
>  %218 = fadd float %217, %212
>  %219 = fmul float %124, %54
>  %220 = fadd float %219, %214
>  %221 = fmul float %124, %55
>  %222 = fadd float %221, %216
>  %223 = fsub float %41, %218
>  %224 = fsub float %42, %220
>  %225 = fsub float %43, %222
>  %226 = fmul float %223, %223
>  %227 = fmul float %224, %224
>  %228 = fadd float %227, %226
>  %229 = fmul float %225, %225
>  %230 = fadd float %228, %229
>  %231 = call float @fabs(float %230)
>  %232 = call float @llvm.AMDGPU.rsq(float %231)
>  %233 = fmul float %223, %232
>  %234 = fmul float %224, %232
>  %235 = fmul float %225, %232
>  %236 = fdiv float 1.000000e+00, %232
>  %237 = fmul float %232, %236
>  %238 = fmul float %236, %236
>  %239 = fmul float %56, %237
>  %240 = fmul float %57, %236
>  %241 = fadd float %240, %239
>  %242 = fmul float %58, %238
>  %243 = fadd float %241, %242
>  %244 = fdiv float 1.000000e+00, %243
>  %245 = fmul float %218, %218
>  %246 = fmul float %220, %220
>  %247 = fadd float %246, %245
>  %248 = fmul float %222, %222
>  %249 = fadd float %247, %248
>  %250 = call float @fabs(float %249)
>  %251 = call float @llvm.AMDGPU.rsq(float %250)
>  %252 = fmul float %218, %251
>  %253 = fmul float %220, %251
>  %254 = fmul float %222, %251
>  %255 = fsub float %233, %252
>  %256 = fsub float %234, %253
>  %257 = fsub float %235, %254
>  %258 = fmul float %255, %255
>  %259 = fmul float %256, %256
>  %260 = fadd float %259, %258
>  %261 = fmul float %257, %257
>  %262 = fadd float %260, %261
>  %263 = call float @fabs(float %262)
>  %264 = call float @llvm.AMDGPU.rsq(float %263)
>  %265 = fmul float %255, %264
>  %266 = fmul float %256, %264
>  %267 = fmul float %257, %264
>  %268 = fmul float %195, %233
>  %269 = fmul float %196, %234
>  %270 = fadd float %269, %268
>  %271 = fmul float %197, %235
>  %272 = fadd float %270, %271
>  %273 = fmul float %195, %265
>  %274 = fmul float %196, %266
>  %275 = fadd float %274, %273
>  %276 = fmul float %197, %267
>  %277 = fadd float %275, %276
>  %278 = fcmp uge float %272, 0.000000e+00
>  %279 = select i1 %278, float %272, float 0.000000e+00
>  %280 = fcmp uge float %277, 0.000000e+00
>  %281 = select i1 %280, float %277, float 0.000000e+00
>  %282 = call float @llvm.pow.f32(float %281, float %36)
>  %283 = call float @llvm.AMDGPU.cndlt(float %272, float 0.000000e+00, float %282)
>  %284 = fmul float 1.000000e+00, %244
>  %285 = fmul float %279, %244
>  %286 = fmul float %283, %244
>  %287 = fmul float %284, %59
>  %288 = fadd float %287, %37
>  %289 = fmul float %284, %60
>  %290 = fadd float %289, %38
>  %291 = fmul float %284, %61
>  %292 = fadd float %291, %39
>  %293 = fmul float %285, %62
>  %294 = fadd float %293, %288
>  %295 = fmul float %285, %63
>  %296 = fadd float %295, %290
>  %297 = fmul float %285, %64
>  %298 = fadd float %297, %292
>  %299 = fmul float %286, %65
>  %300 = fadd float %299, %294
>  %301 = fmul float %286, %66
>  %302 = fadd float %301, %296
>  %303 = fmul float %286, %67
>  %304 = fadd float %303, %298
>  %305 = fsub float %68, %218
>  %306 = fsub float %69, %220
>  %307 = fsub float %70, %222
>  %308 = fmul float %305, %305
>  %309 = fmul float %306, %306
>  %310 = fadd float %309, %308
>  %311 = fmul float %307, %307
>  %312 = fadd float %310, %311
>  %313 = call float @fabs(float %312)
>  %314 = call float @llvm.AMDGPU.rsq(float %313)
>  %315 = fmul float %305, %314
>  %316 = fmul float %306, %314
>  %317 = fmul float %307, %314
>  %318 = fdiv float 1.000000e+00, %314
>  %319 = fmul float %314, %318
>  %320 = fmul float %318, %318
>  %321 = fmul float %71, %319
>  %322 = fmul float %72, %318
>  %323 = fadd float %322, %321
>  %324 = fmul float %73, %320
>  %325 = fadd float %323, %324
>  %326 = fdiv float 1.000000e+00, %325
>  %327 = fsub float %315, %252
>  %328 = fsub float %316, %253
>  %329 = fsub float %317, %254
>  %330 = fmul float %327, %327
>  %331 = fmul float %328, %328
>  %332 = fadd float %331, %330
>  %333 = fmul float %329, %329
>  %334 = fadd float %332, %333
>  %335 = call float @fabs(float %334)
>  %336 = call float @llvm.AMDGPU.rsq(float %335)
>  %337 = fmul float %327, %336
>  %338 = fmul float %328, %336
>  %339 = fmul float %329, %336
>  %340 = fmul float %195, %315
>  %341 = fmul float %196, %316
>  %342 = fadd float %341, %340
>  %343 = fmul float %197, %317
>  %344 = fadd float %342, %343
>  %345 = fmul float %195, %337
>  %346 = fmul float %196, %338
>  %347 = fadd float %346, %345
>  %348 = fmul float %197, %339
>  %349 = fadd float %347, %348
>  %350 = fcmp uge float %344, 0.000000e+00
>  %351 = select i1 %350, float %344, float 0.000000e+00
>  %352 = fcmp uge float %349, 0.000000e+00
>  %353 = select i1 %352, float %349, float 0.000000e+00
>  %354 = call float @llvm.pow.f32(float %353, float %36)
>  %355 = call float @llvm.AMDGPU.cndlt(float %344, float 0.000000e+00, float %354)
>  %356 = fmul float 1.000000e+00, %326
>  %357 = fmul float %351, %326
>  %358 = fmul float %355, %326
>  %359 = fmul float %356, %74
>  %360 = fadd float %359, %300
>  %361 = fmul float %356, %75
>  %362 = fadd float %361, %302
>  %363 = fmul float %356, %76
>  %364 = fadd float %363, %304
>  %365 = fmul float %357, %77
>  %366 = fadd float %365, %360
>  %367 = fmul float %357, %78
>  %368 = fadd float %367, %362
>  %369 = fmul float %357, %79
>  %370 = fadd float %369, %364
>  %371 = fmul float %358, %80
>  %372 = fadd float %371, %366
>  %373 = fmul float %358, %81
>  %374 = fadd float %373, %368
>  %375 = fmul float %358, %82
>  %376 = fadd float %375, %370
>  %377 = fsub float %83, %218
>  %378 = fsub float %84, %220
>  %379 = fsub float %85, %222
>  %380 = fmul float %377, %377
>  %381 = fmul float %378, %378
>  %382 = fadd float %381, %380
>  %383 = fmul float %379, %379
>  %384 = fadd float %382, %383
>  %385 = call float @fabs(float %384)
>  %386 = call float @llvm.AMDGPU.rsq(float %385)
>  %387 = fmul float %377, %386
>  %388 = fmul float %378, %386
>  %389 = fmul float %379, %386
>  %390 = fdiv float 1.000000e+00, %386
>  %391 = fmul float %386, %390
>  %392 = fmul float %390, %390
>  %393 = fmul float %86, %391
>  %394 = fmul float %87, %390
>  %395 = fadd float %394, %393
>  %396 = fmul float %88, %392
>  %397 = fadd float %395, %396
>  %398 = fdiv float 1.000000e+00, %397
>  %399 = fsub float %387, %252
>  %400 = fsub float %388, %253
>  %401 = fsub float %389, %254
>  %402 = fmul float %399, %399
>  %403 = fmul float %400, %400
>  %404 = fadd float %403, %402
>  %405 = fmul float %401, %401
>  %406 = fadd float %404, %405
>  %407 = call float @fabs(float %406)
>  %408 = call float @llvm.AMDGPU.rsq(float %407)
>  %409 = fmul float %399, %408
>  %410 = fmul float %400, %408
>  %411 = fmul float %401, %408
>  %412 = fmul float %195, %387
>  %413 = fmul float %196, %388
>  %414 = fadd float %413, %412
>  %415 = fmul float %197, %389
>  %416 = fadd float %414, %415
>  %417 = fmul float %195, %409
>  %418 = fmul float %196, %410
>  %419 = fadd float %418, %417
>  %420 = fmul float %197, %411
>  %421 = fadd float %419, %420
>  %422 = fcmp uge float %416, 0.000000e+00
>  %423 = select i1 %422, float %416, float 0.000000e+00
>  %424 = fcmp uge float %421, 0.000000e+00
>  %425 = select i1 %424, float %421, float 0.000000e+00
>  %426 = call float @llvm.pow.f32(float %425, float %36)
>  %427 = call float @llvm.AMDGPU.cndlt(float %416, float 0.000000e+00, float %426)
>  %428 = fmul float 1.000000e+00, %398
>  %429 = fmul float %423, %398
>  %430 = fmul float %427, %398
>  %431 = fmul float %428, %89
>  %432 = fadd float %431, %372
>  %433 = fmul float %428, %90
>  %434 = fadd float %433, %374
>  %435 = fmul float %428, %91
>  %436 = fadd float %435, %376
>  %437 = fmul float %429, %92
>  %438 = fadd float %437, %432
>  %439 = fmul float %429, %93
>  %440 = fadd float %439, %434
>  %441 = fmul float %429, %94
>  %442 = fadd float %441, %436
>  %443 = fmul float %430, %95
>  %444 = fadd float %443, %438
>  %445 = fmul float %430, %96
>  %446 = fadd float %445, %440
>  %447 = fmul float %430, %97
>  %448 = fadd float %447, %442
>  %449 = fsub float %98, %218
>  %450 = fsub float %99, %220
>  %451 = fsub float %100, %222
>  %452 = fmul float %449, %449
>  %453 = fmul float %450, %450
>  %454 = fadd float %453, %452
>  %455 = fmul float %451, %451
>  %456 = fadd float %454, %455
>  %457 = call float @fabs(float %456)
>  %458 = call float @llvm.AMDGPU.rsq(float %457)
>  %459 = fmul float %449, %458
>  %460 = fmul float %450, %458
>  %461 = fmul float %451, %458
>  %462 = fsub float -0.000000e+00, %459
>  %463 = fsub float -0.000000e+00, %460
>  %464 = fsub float -0.000000e+00, %461
>  %465 = fmul float %462, %105
>  %466 = fmul float %463, %106
>  %467 = fadd float %466, %465
>  %468 = fmul float %464, %107
>  %469 = fadd float %467, %468
>  %470 = fcmp olt float %108, %469
>  %471 = select i1 %470, float 1.000000e+00, float 0.000000e+00
>  %472 = fcmp olt float %108, %469
>  %473 = select i1 %472, float 1.000000e+00, float 0.000000e+00
>  %474 = fcmp olt float %108, %469
>  %475 = select i1 %474, float 1.000000e+00, float 0.000000e+00
>  %476 = call float @llvm.pow.f32(float %469, float %104)
>  %477 = fmul float %471, %476
>  %478 = fmul float %473, %476
>  %479 = fmul float %475, %476
>  %480 = fdiv float 1.000000e+00, %458
>  %481 = fmul float %458, %480
>  %482 = fmul float %480, %480
>  %483 = fmul float %101, %481
>  %484 = fmul float %102, %480
>  %485 = fadd float %484, %483
>  %486 = fmul float %103, %482
>  %487 = fadd float %485, %486
>  %488 = fdiv float 1.000000e+00, %487
>  %489 = fmul float %488, %477
>  %490 = fmul float %488, %478
>  %491 = fmul float %488, %479
>  %492 = fsub float %459, %252
>  %493 = fsub float %460, %253
>  %494 = fsub float %461, %254
>  %495 = fmul float %492, %492
>  %496 = fmul float %493, %493
>  %497 = fadd float %496, %495
>  %498 = fmul float %494, %494
>  %499 = fadd float %497, %498
>  %500 = call float @fabs(float %499)
>  %501 = call float @llvm.AMDGPU.rsq(float %500)
>  %502 = fmul float %492, %501
>  %503 = fmul float %493, %501
>  %504 = fmul float %494, %501
>  %505 = fmul float %195, %459
>  %506 = fmul float %196, %460
>  %507 = fadd float %506, %505
>  %508 = fmul float %197, %461
>  %509 = fadd float %507, %508
>  %510 = fmul float %195, %502
>  %511 = fmul float %196, %503
>  %512 = fadd float %511, %510
>  %513 = fmul float %197, %504
>  %514 = fadd float %512, %513
>  %515 = fcmp uge float %509, 0.000000e+00
>  %516 = select i1 %515, float %509, float 0.000000e+00
>  %517 = fcmp uge float %514, 0.000000e+00
>  %518 = select i1 %517, float %514, float 0.000000e+00
>  %519 = call float @llvm.pow.f32(float %518, float %36)
>  %520 = call float @llvm.AMDGPU.cndlt(float %509, float 0.000000e+00, float %519)
>  %521 = fmul float 1.000000e+00, %489
>  %522 = fmul float %516, %490
>  %523 = fmul float %520, %491
>  %524 = fmul float %521, %109
>  %525 = fadd float %524, %444
>  %526 = fmul float %521, %110
>  %527 = fadd float %526, %446
>  %528 = fmul float %521, %111
>  %529 = fadd float %528, %448
>  %530 = fmul float %522, %112
>  %531 = fadd float %530, %525
>  %532 = fmul float %522, %113
>  %533 = fadd float %532, %527
>  %534 = fmul float %522, %114
>  %535 = fadd float %534, %529
>  %536 = fmul float %523, %115
>  %537 = fadd float %536, %531
>  %538 = fmul float %523, %116
>  %539 = fadd float %538, %533
>  %540 = fmul float %523, %117
>  %541 = fadd float %540, %535
>  %542 = call float @llvm.AMDIL.clamp.(float %537, float 0.000000e+00, float 1.000000e+00)
>  %543 = call float @llvm.AMDIL.clamp.(float %539, float 0.000000e+00, float 1.000000e+00)
>  %544 = call float @llvm.AMDIL.clamp.(float %541, float 0.000000e+00, float 1.000000e+00)
>  %545 = call float @fabs(float %222)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %542, float %543, float %544, float %201)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %545, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %134, float %135, float %136, float %137)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %141, float %142, float %143, float %144)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %166, float %168, float %170, float %172)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020129
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>044a2110
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>0201010e
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>e00c2000
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>101c2804
>c2020115
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>d282000e
>04380915
>c2020116
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>d2820018
>04380916
>c2020110
>bf8c007f
>101c2804
>c2020111
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>d282000e
>04380915
>c2020112
>bf8c007f
>d282000e
>04380916
>10321d0e
>d2820019
>04663118
>c2020118
>bf8c007f
>10342804
>c2020119
>bf8c007f
>d282001a
>04680915
>c202011a
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>d2820014
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>04662914
>d2060115
>02010115
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>00221880
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>c202813e
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>04440b0a
>c2028142
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>04440b09
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>bf8c007f
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>04240915
>c202016c
>bf8c007f
>d2820009
>04240916
>c202017c
>bf8c007f
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>0424090b
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>7e0c02f2
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>06070705
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>e00c2000
>80020500
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>08070605
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    4.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MOV TEMP[1].xy, IN[1].xyyy
>  4: MOV TEMP[1].w, IN[1].wwww
>  5: TXP TEMP[1], TEMP[1], SAMP[1], 2D
>  6: MUL TEMP[0], TEMP[0], TEMP[1]
>  7: MUL_SAT TEMP[1], TEMP[0], IMM[0].xxxy
>  8: MUL TEMP[1].xyz, IN[0], TEMP[1]
>  9: MOV TEMP[1].xyz, TEMP[1].xyzx
> 10: MUL_SAT TEMP[0], TEMP[0], IMM[0].xxxy
> 11: MOV TEMP[1].w, TEMP[0].wwww
> 12: MOV OUT[0], TEMP[1]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %37 = fdiv float %34, %36
>  %38 = fdiv float %35, %36
>  %39 = bitcast float %37 to i32
>  %40 = bitcast float %38 to i32
>  %41 = insertelement <2 x i32> undef, i32 %39, i32 0
>  %42 = insertelement <2 x i32> %41, i32 %40, i32 1
>  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %42, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fdiv float %31, %33
>  %49 = fdiv float %32, %33
>  %50 = bitcast float %48 to i32
>  %51 = bitcast float %49 to i32
>  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
>  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
>  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %58 = extractelement <4 x float> %54, i32 3
>  %59 = fmul float %44, %55
>  %60 = fmul float %45, %56
>  %61 = fmul float %46, %57
>  %62 = fmul float %47, %58
>  %63 = fmul float %59, 4.000000e+00
>  %64 = fmul float %60, 4.000000e+00
>  %65 = fmul float %61, 4.000000e+00
>  %66 = fmul float %62, 1.000000e+00
>  %67 = call float @llvm.AMDIL.clamp.(float %63, float 0.000000e+00, float 1.000000e+00)
>  %68 = call float @llvm.AMDIL.clamp.(float %64, float 0.000000e+00, float 1.000000e+00)
>  %69 = call float @llvm.AMDIL.clamp.(float %65, float 0.000000e+00, float 1.000000e+00)
>  %70 = call float @llvm.AMDIL.clamp.(float %66, float 0.000000e+00, float 1.000000e+00)
>  %71 = fmul float %28, %67
>  %72 = fmul float %29, %68
>  %73 = fmul float %30, %69
>  %74 = fmul float %59, 4.000000e+00
>  %75 = fmul float %60, 4.000000e+00
>  %76 = fmul float %61, 4.000000e+00
>  %77 = fmul float %62, 1.000000e+00
>  %78 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %75, float 0.000000e+00, float 1.000000e+00)
>  %80 = call float @llvm.AMDIL.clamp.(float %76, float 0.000000e+00, float 1.000000e+00)
>  %81 = call float @llvm.AMDIL.clamp.(float %77, float 0.000000e+00, float 1.000000e+00)
>  %82 = call i32 @llvm.SI.packf16(float %71, float %72)
>  %83 = bitcast i32 %82 to float
>  %84 = call i32 @llvm.SI.packf16(float %73, float %81)
>  %85 = bitcast i32 %84 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %83, float %85, float %83, float %85)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430202
>c8180900
>c8190901
>c81c0b00
>c81d0b01
>7e105507
>100e1106
>c8240800
>c8250801
>100c1109
>c0800300
>c0c40500
>bf8c0070
>f0800f00
>00020606
>bf8c0770
>10140908
>101414f6
>d206080a
>0201010a
>c82c0200
>c82d0201
>1014150b
>10160b09
>d206080b
>0201010b
>5e14170a
>10160707
>101616f6
>d206080b
>0201010b
>c8300100
>c8310101
>1016170c
>10040506
>100404f6
>d2060802
>02010102
>c80c0000
>c80d0001
>10000503
>5e001700
>f8001c0f
>0a000a00
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: MOV OUT[3], IN[3]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %5)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = extractelement <4 x float> %50, i32 3
>  %55 = fmul float %30, %11
>  %56 = fmul float %30, %12
>  %57 = fmul float %30, %13
>  %58 = fmul float %30, %14
>  %59 = fmul float %31, %15
>  %60 = fadd float %59, %55
>  %61 = fmul float %31, %16
>  %62 = fadd float %61, %56
>  %63 = fmul float %31, %17
>  %64 = fadd float %63, %57
>  %65 = fmul float %31, %18
>  %66 = fadd float %65, %58
>  %67 = fmul float %32, %19
>  %68 = fadd float %67, %60
>  %69 = fmul float %32, %20
>  %70 = fadd float %69, %62
>  %71 = fmul float %32, %21
>  %72 = fadd float %71, %64
>  %73 = fmul float %32, %22
>  %74 = fadd float %73, %66
>  %75 = fmul float %33, %23
>  %76 = fadd float %75, %68
>  %77 = fmul float %33, %24
>  %78 = fadd float %77, %70
>  %79 = fmul float %33, %25
>  %80 = fadd float %79, %72
>  %81 = fmul float %33, %26
>  %82 = fadd float %81, %74
>  %83 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %84 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %85 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %86 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %83, float %84, float %85, float %86)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %51, float %52, float %53, float %54)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %76, float %78, float %80, float %82)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c084070c
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800022f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..19]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: ABS OUT[2].x, TEMP[4].zzzz
> 41: MOV OUT[2].yzw, IMM[0].xxxy
> 42: MOV OUT[3], IN[3]
> 43: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = extractelement <4 x float> %73, i32 3
>  %78 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %79 = load <16 x i8> addrspace(2)* %78, !tbaa !0
>  %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %79, i32 0, i32 %5)
>  %81 = extractelement <4 x float> %80, i32 0
>  %82 = extractelement <4 x float> %80, i32 1
>  %83 = extractelement <4 x float> %80, i32 2
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = extractelement <4 x float> %92, i32 3
>  %97 = fmul float %74, %11
>  %98 = fmul float %74, %12
>  %99 = fmul float %74, %13
>  %100 = fmul float %74, %14
>  %101 = fmul float %75, %15
>  %102 = fadd float %101, %97
>  %103 = fmul float %75, %16
>  %104 = fadd float %103, %98
>  %105 = fmul float %75, %17
>  %106 = fadd float %105, %99
>  %107 = fmul float %75, %18
>  %108 = fadd float %107, %100
>  %109 = fmul float %76, %19
>  %110 = fadd float %109, %102
>  %111 = fmul float %76, %20
>  %112 = fadd float %111, %104
>  %113 = fmul float %76, %21
>  %114 = fadd float %113, %106
>  %115 = fmul float %76, %22
>  %116 = fadd float %115, %108
>  %117 = fmul float %77, %23
>  %118 = fadd float %117, %110
>  %119 = fmul float %77, %24
>  %120 = fadd float %119, %112
>  %121 = fmul float %77, %25
>  %122 = fadd float %121, %114
>  %123 = fmul float %77, %26
>  %124 = fadd float %123, %116
>  %125 = fmul float %81, %27
>  %126 = fmul float %82, %28
>  %127 = fadd float %126, %125
>  %128 = fmul float %83, %29
>  %129 = fadd float %127, %128
>  %130 = fmul float %81, %30
>  %131 = fmul float %82, %31
>  %132 = fadd float %131, %130
>  %133 = fmul float %83, %32
>  %134 = fadd float %132, %133
>  %135 = fmul float %81, %33
>  %136 = fmul float %82, %34
>  %137 = fadd float %136, %135
>  %138 = fmul float %83, %35
>  %139 = fadd float %137, %138
>  %140 = fmul float %129, %129
>  %141 = fmul float %134, %134
>  %142 = fadd float %141, %140
>  %143 = fmul float %139, %139
>  %144 = fadd float %142, %143
>  %145 = call float @fabs(float %144)
>  %146 = call float @llvm.AMDGPU.rsq(float %145)
>  %147 = fmul float %129, %146
>  %148 = fmul float %134, %146
>  %149 = fmul float %139, %146
>  %150 = fmul float %37, %40
>  %151 = fadd float %150, %87
>  %152 = fmul float %38, %41
>  %153 = fadd float %152, %88
>  %154 = fmul float %39, %42
>  %155 = fadd float %154, %89
>  %156 = call float @llvm.AMDIL.clamp.(float %151, float 0.000000e+00, float 1.000000e+00)
>  %157 = call float @llvm.AMDIL.clamp.(float %153, float 0.000000e+00, float 1.000000e+00)
>  %158 = call float @llvm.AMDIL.clamp.(float %155, float 0.000000e+00, float 1.000000e+00)
>  %159 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %160 = fmul float %74, %47
>  %161 = fmul float %74, %48
>  %162 = fmul float %74, %49
>  %163 = fmul float %75, %50
>  %164 = fadd float %163, %160
>  %165 = fmul float %75, %51
>  %166 = fadd float %165, %161
>  %167 = fmul float %75, %52
>  %168 = fadd float %167, %162
>  %169 = fmul float %76, %53
>  %170 = fadd float %169, %164
>  %171 = fmul float %76, %54
>  %172 = fadd float %171, %166
>  %173 = fmul float %76, %55
>  %174 = fadd float %173, %168
>  %175 = fmul float %77, %56
>  %176 = fadd float %175, %170
>  %177 = fmul float %77, %57
>  %178 = fadd float %177, %172
>  %179 = fmul float %77, %58
>  %180 = fadd float %179, %174
>  %181 = fsub float %44, %176
>  %182 = fsub float %45, %178
>  %183 = fsub float %46, %180
>  %184 = fmul float %181, %181
>  %185 = fmul float %182, %182
>  %186 = fadd float %185, %184
>  %187 = fmul float %183, %183
>  %188 = fadd float %186, %187
>  %189 = call float @fabs(float %188)
>  %190 = call float @llvm.AMDGPU.rsq(float %189)
>  %191 = fmul float %181, %190
>  %192 = fmul float %182, %190
>  %193 = fmul float %183, %190
>  %194 = fdiv float 1.000000e+00, %190
>  %195 = fmul float %190, %194
>  %196 = fmul float %194, %194
>  %197 = fmul float %59, %195
>  %198 = fmul float %60, %194
>  %199 = fadd float %198, %197
>  %200 = fmul float %61, %196
>  %201 = fadd float %199, %200
>  %202 = fdiv float 1.000000e+00, %201
>  %203 = fmul float %176, %176
>  %204 = fmul float %178, %178
>  %205 = fadd float %204, %203
>  %206 = fmul float %180, %180
>  %207 = fadd float %205, %206
>  %208 = call float @fabs(float %207)
>  %209 = call float @llvm.AMDGPU.rsq(float %208)
>  %210 = fmul float %176, %209
>  %211 = fmul float %178, %209
>  %212 = fmul float %180, %209
>  %213 = fsub float %191, %210
>  %214 = fsub float %192, %211
>  %215 = fsub float %193, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fmul float %147, %191
>  %227 = fmul float %148, %192
>  %228 = fadd float %227, %226
>  %229 = fmul float %149, %193
>  %230 = fadd float %228, %229
>  %231 = fmul float %147, %223
>  %232 = fmul float %148, %224
>  %233 = fadd float %232, %231
>  %234 = fmul float %149, %225
>  %235 = fadd float %233, %234
>  %236 = fcmp uge float %230, 0.000000e+00
>  %237 = select i1 %236, float %230, float 0.000000e+00
>  %238 = fcmp uge float %235, 0.000000e+00
>  %239 = select i1 %238, float %235, float 0.000000e+00
>  %240 = call float @llvm.pow.f32(float %239, float %36)
>  %241 = call float @llvm.AMDGPU.cndlt(float %230, float 0.000000e+00, float %240)
>  %242 = fmul float 1.000000e+00, %202
>  %243 = fmul float %237, %202
>  %244 = fmul float %241, %202
>  %245 = fmul float %242, %62
>  %246 = fadd float %245, %151
>  %247 = fmul float %242, %63
>  %248 = fadd float %247, %153
>  %249 = fmul float %242, %64
>  %250 = fadd float %249, %155
>  %251 = fmul float %243, %65
>  %252 = fadd float %251, %246
>  %253 = fmul float %243, %66
>  %254 = fadd float %253, %248
>  %255 = fmul float %243, %67
>  %256 = fadd float %255, %250
>  %257 = fmul float %244, %68
>  %258 = fadd float %257, %252
>  %259 = fmul float %244, %69
>  %260 = fadd float %259, %254
>  %261 = fmul float %244, %70
>  %262 = fadd float %261, %256
>  %263 = call float @llvm.AMDIL.clamp.(float %258, float 0.000000e+00, float 1.000000e+00)
>  %264 = call float @llvm.AMDIL.clamp.(float %260, float 0.000000e+00, float 1.000000e+00)
>  %265 = call float @llvm.AMDIL.clamp.(float %262, float 0.000000e+00, float 1.000000e+00)
>  %266 = call float @fabs(float %180)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %263, float %264, float %265, float %159)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %266, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %93, float %94, float %95, float %96)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %118, float %120, float %122, float %124)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820006
>04140904
>c2020130
>bf8c007f
>100a0204
>c2020134
>bf8c007f
>d2820005
>04140902
>c2020138
>bf8c007f
>d2820005
>04140903
>c202013c
>bf8c007f
>d2820008
>04140904
>100a1108
>d2820007
>04160d06
>c2020132
>bf8c007f
>100a0204
>c2020136
>bf8c007f
>d2820005
>04140902
>c202013a
>bf8c007f
>d2820005
>04140903
>c202013e
>bf8c007f
>d2820005
>04140904
>d2820007
>041e0b05
>d2060107
>02010107
>7e125b07
>10141306
>c202012d
>bf8c007f
>080e0c04
>c202012c
>bf8c007f
>081a1004
>100c1b0d
>d2820006
>041a0f07
>c202012e
>bf8c007f
>08160a04
>d2820006
>041a170b
>d2060106
>02010106
>7e0c5b06
>100e0d07
>08181507
>10141308
>10100d0d
>081a1508
>10141b0d
>d282000e
>042a190c
>10141305
>10120d0b
>08141509
>d282000b
>043a150a
>d206010b
>0201010b
>7e165b0b
>1018170c
>101a170d
>c0840704
>bf8c007f
>e00c2000
>80020e00
>c2020114
>bf8c0070
>10241c04
>c2020115
>bf8c007f
>d2820012
>0448090f
>c2020116
>bf8c007f
>d2820012
>04480910
>c2020110
>bf8c007f
>10261c04
>c2020111
>bf8c007f
>d2820013
>044c090f
>c2020112
>bf8c007f
>d2820013
>044c0910
>10282713
>d2820014
>04522512
>c2020118
>bf8c007f
>102a1c04
>c2020119
>bf8c007f
>d2820015
>0454090f
>c202011a
>bf8c007f
>d282000f
>04540910
>d282000e
>04521f0f
>d206010e
>0201010e
>7e205b0e
>101c2113
>10221b0e
>101a2112
>d282000c
>0446190d
>1016170a
>1014210f
>d282000b
>0432170a
>d00c0004
>0201010b
>d200000b
>00121680
>7e164f0b
>c202011c
>bf8c007f
>0e161604
>7e164b0b
>1010110e
>d2820007
>04220f0d
>d2820008
>041e130a
>d0080004
>02021080
>d2000009
>0011010b
>7e0e5506
>100c0f06
>c2020140
>bf8c007f
>100c0c04
>c2020141
>bf8c007f
>d2820006
>041a0e04
>100e0f07
>c2020142
>bf8c007f
>d2820006
>041a0e04
>7e0e5506
>100c0f09
>d00c0004
>02010108
>d2000008
>00121080
>10100f08
>c0840708
>bf8c007f
>e00c2000
>80020900
>c2020122
>c2028126
>bf8c0070
>7e1a0205
>d282000d
>042e1a04
>c2020146
>bf8c007f
>d282000d
>04340907
>c202014a
>bf8c007f
>d282000d
>04340908
>c202014e
>bf8c007f
>d282000d
>04340906
>d206080d
>0201010d
>c2020121
>c2028125
>bf8c007f
>7e1c0205
>d282000e
>042a1c04
>c2020145
>bf8c007f
>d282000e
>04380907
>c2020149
>bf8c007f
>d282000e
>04380908
>c202014d
>bf8c007f
>d282000e
>04380906
>d206080e
>0201010e
>c2020120
>c2028124
>bf8c007f
>7e1e0205
>d2820009
>04261e04
>c2020144
>bf8c007f
>d2820007
>04240907
>c2020148
>bf8c007f
>d2820007
>041c0908
>c202014c
>bf8c007f
>d2820006
>041c0906
>d2060806
>02010106
>c202012b
>bf8c007f
>d2060807
>02010004
>f800020f
>070d0e06
>d2060105
>02010105
>bf8c070f
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..32]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD TEMP[3], TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: SUB TEMP[5], CONST[28], TEMP[6]
> 78: DP3 TEMP[7].x, TEMP[5], TEMP[5]
> 79: RSQ TEMP[7].x, |TEMP[7]|
> 80: MUL TEMP[5], TEMP[5], TEMP[7].xxxx
> 81: DP3 TEMP[2].x, TEMP[0], CONST[28]
> 82: DP3 TEMP[2].y, TEMP[0], TEMP[5]
> 83: LIT TEMP[1], TEMP[2]
> 84: ADD TEMP[3], CONST[30], TEMP[3]
> 85: MAD TEMP[3], TEMP[1].yyyy, CONST[31], TEMP[3]
> 86: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[32], TEMP[3]
> 87: ABS OUT[2].x, TEMP[4].zzzz
> 88: MOV OUT[2].yzw, IMM[0].xxxy
> 89: MOV OUT[3], IN[2]
> 90: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %110 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %111 = load <16 x i8> addrspace(2)* %110, !tbaa !0
>  %112 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %111, i32 0, i32 %5)
>  %113 = extractelement <4 x float> %112, i32 0
>  %114 = extractelement <4 x float> %112, i32 1
>  %115 = extractelement <4 x float> %112, i32 2
>  %116 = extractelement <4 x float> %112, i32 3
>  %117 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %118 = load <16 x i8> addrspace(2)* %117, !tbaa !0
>  %119 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %118, i32 0, i32 %5)
>  %120 = extractelement <4 x float> %119, i32 0
>  %121 = extractelement <4 x float> %119, i32 1
>  %122 = extractelement <4 x float> %119, i32 2
>  %123 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %124 = load <16 x i8> addrspace(2)* %123, !tbaa !0
>  %125 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %124, i32 0, i32 %5)
>  %126 = extractelement <4 x float> %125, i32 0
>  %127 = extractelement <4 x float> %125, i32 1
>  %128 = extractelement <4 x float> %125, i32 2
>  %129 = extractelement <4 x float> %125, i32 3
>  %130 = fmul float %113, %11
>  %131 = fmul float %113, %12
>  %132 = fmul float %113, %13
>  %133 = fmul float %113, %14
>  %134 = fmul float %114, %15
>  %135 = fadd float %134, %130
>  %136 = fmul float %114, %16
>  %137 = fadd float %136, %131
>  %138 = fmul float %114, %17
>  %139 = fadd float %138, %132
>  %140 = fmul float %114, %18
>  %141 = fadd float %140, %133
>  %142 = fmul float %115, %19
>  %143 = fadd float %142, %135
>  %144 = fmul float %115, %20
>  %145 = fadd float %144, %137
>  %146 = fmul float %115, %21
>  %147 = fadd float %146, %139
>  %148 = fmul float %115, %22
>  %149 = fadd float %148, %141
>  %150 = fmul float %116, %23
>  %151 = fadd float %150, %143
>  %152 = fmul float %116, %24
>  %153 = fadd float %152, %145
>  %154 = fmul float %116, %25
>  %155 = fadd float %154, %147
>  %156 = fmul float %116, %26
>  %157 = fadd float %156, %149
>  %158 = fmul float %120, %27
>  %159 = fmul float %121, %28
>  %160 = fadd float %159, %158
>  %161 = fmul float %122, %29
>  %162 = fadd float %160, %161
>  %163 = fmul float %120, %30
>  %164 = fmul float %121, %31
>  %165 = fadd float %164, %163
>  %166 = fmul float %122, %32
>  %167 = fadd float %165, %166
>  %168 = fmul float %120, %33
>  %169 = fmul float %121, %34
>  %170 = fadd float %169, %168
>  %171 = fmul float %122, %35
>  %172 = fadd float %170, %171
>  %173 = fmul float %162, %162
>  %174 = fmul float %167, %167
>  %175 = fadd float %174, %173
>  %176 = fmul float %172, %172
>  %177 = fadd float %175, %176
>  %178 = call float @fabs(float %177)
>  %179 = call float @llvm.AMDGPU.rsq(float %178)
>  %180 = fmul float %162, %179
>  %181 = fmul float %167, %179
>  %182 = fmul float %172, %179
>  %183 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %184 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %185 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %186 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %187 = fmul float %113, %44
>  %188 = fmul float %113, %45
>  %189 = fmul float %113, %46
>  %190 = fmul float %114, %47
>  %191 = fadd float %190, %187
>  %192 = fmul float %114, %48
>  %193 = fadd float %192, %188
>  %194 = fmul float %114, %49
>  %195 = fadd float %194, %189
>  %196 = fmul float %115, %50
>  %197 = fadd float %196, %191
>  %198 = fmul float %115, %51
>  %199 = fadd float %198, %193
>  %200 = fmul float %115, %52
>  %201 = fadd float %200, %195
>  %202 = fmul float %116, %53
>  %203 = fadd float %202, %197
>  %204 = fmul float %116, %54
>  %205 = fadd float %204, %199
>  %206 = fmul float %116, %55
>  %207 = fadd float %206, %201
>  %208 = fsub float %41, %203
>  %209 = fsub float %42, %205
>  %210 = fsub float %43, %207
>  %211 = fmul float %208, %208
>  %212 = fmul float %209, %209
>  %213 = fadd float %212, %211
>  %214 = fmul float %210, %210
>  %215 = fadd float %213, %214
>  %216 = call float @fabs(float %215)
>  %217 = call float @llvm.AMDGPU.rsq(float %216)
>  %218 = fmul float %208, %217
>  %219 = fmul float %209, %217
>  %220 = fmul float %210, %217
>  %221 = fdiv float 1.000000e+00, %217
>  %222 = fmul float %217, %221
>  %223 = fmul float %221, %221
>  %224 = fmul float %56, %222
>  %225 = fmul float %57, %221
>  %226 = fadd float %225, %224
>  %227 = fmul float %58, %223
>  %228 = fadd float %226, %227
>  %229 = fdiv float 1.000000e+00, %228
>  %230 = fmul float %203, %203
>  %231 = fmul float %205, %205
>  %232 = fadd float %231, %230
>  %233 = fmul float %207, %207
>  %234 = fadd float %232, %233
>  %235 = call float @fabs(float %234)
>  %236 = call float @llvm.AMDGPU.rsq(float %235)
>  %237 = fmul float %203, %236
>  %238 = fmul float %205, %236
>  %239 = fmul float %207, %236
>  %240 = fsub float %218, %237
>  %241 = fsub float %219, %238
>  %242 = fsub float %220, %239
>  %243 = fmul float %240, %240
>  %244 = fmul float %241, %241
>  %245 = fadd float %244, %243
>  %246 = fmul float %242, %242
>  %247 = fadd float %245, %246
>  %248 = call float @fabs(float %247)
>  %249 = call float @llvm.AMDGPU.rsq(float %248)
>  %250 = fmul float %240, %249
>  %251 = fmul float %241, %249
>  %252 = fmul float %242, %249
>  %253 = fmul float %180, %218
>  %254 = fmul float %181, %219
>  %255 = fadd float %254, %253
>  %256 = fmul float %182, %220
>  %257 = fadd float %255, %256
>  %258 = fmul float %180, %250
>  %259 = fmul float %181, %251
>  %260 = fadd float %259, %258
>  %261 = fmul float %182, %252
>  %262 = fadd float %260, %261
>  %263 = fcmp uge float %257, 0.000000e+00
>  %264 = select i1 %263, float %257, float 0.000000e+00
>  %265 = fcmp uge float %262, 0.000000e+00
>  %266 = select i1 %265, float %262, float 0.000000e+00
>  %267 = call float @llvm.pow.f32(float %266, float %36)
>  %268 = call float @llvm.AMDGPU.cndlt(float %257, float 0.000000e+00, float %267)
>  %269 = fmul float 1.000000e+00, %229
>  %270 = fmul float %264, %229
>  %271 = fmul float %268, %229
>  %272 = fmul float %269, %59
>  %273 = fadd float %272, %37
>  %274 = fmul float %269, %60
>  %275 = fadd float %274, %38
>  %276 = fmul float %269, %61
>  %277 = fadd float %276, %39
>  %278 = fmul float %270, %62
>  %279 = fadd float %278, %273
>  %280 = fmul float %270, %63
>  %281 = fadd float %280, %275
>  %282 = fmul float %270, %64
>  %283 = fadd float %282, %277
>  %284 = fmul float %271, %65
>  %285 = fadd float %284, %279
>  %286 = fmul float %271, %66
>  %287 = fadd float %286, %281
>  %288 = fmul float %271, %67
>  %289 = fadd float %288, %283
>  %290 = fsub float %68, %203
>  %291 = fsub float %69, %205
>  %292 = fsub float %70, %207
>  %293 = fmul float %290, %290
>  %294 = fmul float %291, %291
>  %295 = fadd float %294, %293
>  %296 = fmul float %292, %292
>  %297 = fadd float %295, %296
>  %298 = call float @fabs(float %297)
>  %299 = call float @llvm.AMDGPU.rsq(float %298)
>  %300 = fmul float %290, %299
>  %301 = fmul float %291, %299
>  %302 = fmul float %292, %299
>  %303 = fdiv float 1.000000e+00, %299
>  %304 = fmul float %299, %303
>  %305 = fmul float %303, %303
>  %306 = fmul float %71, %304
>  %307 = fmul float %72, %303
>  %308 = fadd float %307, %306
>  %309 = fmul float %73, %305
>  %310 = fadd float %308, %309
>  %311 = fdiv float 1.000000e+00, %310
>  %312 = fsub float %300, %237
>  %313 = fsub float %301, %238
>  %314 = fsub float %302, %239
>  %315 = fmul float %312, %312
>  %316 = fmul float %313, %313
>  %317 = fadd float %316, %315
>  %318 = fmul float %314, %314
>  %319 = fadd float %317, %318
>  %320 = call float @fabs(float %319)
>  %321 = call float @llvm.AMDGPU.rsq(float %320)
>  %322 = fmul float %312, %321
>  %323 = fmul float %313, %321
>  %324 = fmul float %314, %321
>  %325 = fmul float %180, %300
>  %326 = fmul float %181, %301
>  %327 = fadd float %326, %325
>  %328 = fmul float %182, %302
>  %329 = fadd float %327, %328
>  %330 = fmul float %180, %322
>  %331 = fmul float %181, %323
>  %332 = fadd float %331, %330
>  %333 = fmul float %182, %324
>  %334 = fadd float %332, %333
>  %335 = fcmp uge float %329, 0.000000e+00
>  %336 = select i1 %335, float %329, float 0.000000e+00
>  %337 = fcmp uge float %334, 0.000000e+00
>  %338 = select i1 %337, float %334, float 0.000000e+00
>  %339 = call float @llvm.pow.f32(float %338, float %36)
>  %340 = call float @llvm.AMDGPU.cndlt(float %329, float 0.000000e+00, float %339)
>  %341 = fmul float 1.000000e+00, %311
>  %342 = fmul float %336, %311
>  %343 = fmul float %340, %311
>  %344 = fmul float %341, %74
>  %345 = fadd float %344, %285
>  %346 = fmul float %341, %75
>  %347 = fadd float %346, %287
>  %348 = fmul float %341, %76
>  %349 = fadd float %348, %289
>  %350 = fmul float %342, %77
>  %351 = fadd float %350, %345
>  %352 = fmul float %342, %78
>  %353 = fadd float %352, %347
>  %354 = fmul float %342, %79
>  %355 = fadd float %354, %349
>  %356 = fmul float %343, %80
>  %357 = fadd float %356, %351
>  %358 = fmul float %343, %81
>  %359 = fadd float %358, %353
>  %360 = fmul float %343, %82
>  %361 = fadd float %360, %355
>  %362 = fsub float %83, %203
>  %363 = fsub float %84, %205
>  %364 = fsub float %85, %207
>  %365 = fmul float %362, %362
>  %366 = fmul float %363, %363
>  %367 = fadd float %366, %365
>  %368 = fmul float %364, %364
>  %369 = fadd float %367, %368
>  %370 = call float @fabs(float %369)
>  %371 = call float @llvm.AMDGPU.rsq(float %370)
>  %372 = fmul float %362, %371
>  %373 = fmul float %363, %371
>  %374 = fmul float %364, %371
>  %375 = fdiv float 1.000000e+00, %371
>  %376 = fmul float %371, %375
>  %377 = fmul float %375, %375
>  %378 = fmul float %86, %376
>  %379 = fmul float %87, %375
>  %380 = fadd float %379, %378
>  %381 = fmul float %88, %377
>  %382 = fadd float %380, %381
>  %383 = fdiv float 1.000000e+00, %382
>  %384 = fsub float %372, %237
>  %385 = fsub float %373, %238
>  %386 = fsub float %374, %239
>  %387 = fmul float %384, %384
>  %388 = fmul float %385, %385
>  %389 = fadd float %388, %387
>  %390 = fmul float %386, %386
>  %391 = fadd float %389, %390
>  %392 = call float @fabs(float %391)
>  %393 = call float @llvm.AMDGPU.rsq(float %392)
>  %394 = fmul float %384, %393
>  %395 = fmul float %385, %393
>  %396 = fmul float %386, %393
>  %397 = fmul float %180, %372
>  %398 = fmul float %181, %373
>  %399 = fadd float %398, %397
>  %400 = fmul float %182, %374
>  %401 = fadd float %399, %400
>  %402 = fmul float %180, %394
>  %403 = fmul float %181, %395
>  %404 = fadd float %403, %402
>  %405 = fmul float %182, %396
>  %406 = fadd float %404, %405
>  %407 = fcmp uge float %401, 0.000000e+00
>  %408 = select i1 %407, float %401, float 0.000000e+00
>  %409 = fcmp uge float %406, 0.000000e+00
>  %410 = select i1 %409, float %406, float 0.000000e+00
>  %411 = call float @llvm.pow.f32(float %410, float %36)
>  %412 = call float @llvm.AMDGPU.cndlt(float %401, float 0.000000e+00, float %411)
>  %413 = fmul float 1.000000e+00, %383
>  %414 = fmul float %408, %383
>  %415 = fmul float %412, %383
>  %416 = fmul float %413, %89
>  %417 = fadd float %416, %357
>  %418 = fmul float %413, %90
>  %419 = fadd float %418, %359
>  %420 = fmul float %413, %91
>  %421 = fadd float %420, %361
>  %422 = fmul float %414, %92
>  %423 = fadd float %422, %417
>  %424 = fmul float %414, %93
>  %425 = fadd float %424, %419
>  %426 = fmul float %414, %94
>  %427 = fadd float %426, %421
>  %428 = fmul float %415, %95
>  %429 = fadd float %428, %423
>  %430 = fmul float %415, %96
>  %431 = fadd float %430, %425
>  %432 = fmul float %415, %97
>  %433 = fadd float %432, %427
>  %434 = fsub float %98, %237
>  %435 = fsub float %99, %238
>  %436 = fsub float %100, %239
>  %437 = fmul float %434, %434
>  %438 = fmul float %435, %435
>  %439 = fadd float %438, %437
>  %440 = fmul float %436, %436
>  %441 = fadd float %439, %440
>  %442 = call float @fabs(float %441)
>  %443 = call float @llvm.AMDGPU.rsq(float %442)
>  %444 = fmul float %434, %443
>  %445 = fmul float %435, %443
>  %446 = fmul float %436, %443
>  %447 = fmul float %180, %98
>  %448 = fmul float %181, %99
>  %449 = fadd float %448, %447
>  %450 = fmul float %182, %100
>  %451 = fadd float %449, %450
>  %452 = fmul float %180, %444
>  %453 = fmul float %181, %445
>  %454 = fadd float %453, %452
>  %455 = fmul float %182, %446
>  %456 = fadd float %454, %455
>  %457 = fcmp uge float %451, 0.000000e+00
>  %458 = select i1 %457, float %451, float 0.000000e+00
>  %459 = fcmp uge float %456, 0.000000e+00
>  %460 = select i1 %459, float %456, float 0.000000e+00
>  %461 = call float @llvm.pow.f32(float %460, float %36)
>  %462 = call float @llvm.AMDGPU.cndlt(float %451, float 0.000000e+00, float %461)
>  %463 = fadd float %101, %429
>  %464 = fadd float %102, %431
>  %465 = fadd float %103, %433
>  %466 = fmul float %458, %104
>  %467 = fadd float %466, %463
>  %468 = fmul float %458, %105
>  %469 = fadd float %468, %464
>  %470 = fmul float %458, %106
>  %471 = fadd float %470, %465
>  %472 = fmul float %462, %107
>  %473 = fadd float %472, %467
>  %474 = fmul float %462, %108
>  %475 = fadd float %474, %469
>  %476 = fmul float %462, %109
>  %477 = fadd float %476, %471
>  %478 = call float @llvm.AMDIL.clamp.(float %473, float 0.000000e+00, float 1.000000e+00)
>  %479 = call float @llvm.AMDIL.clamp.(float %475, float 0.000000e+00, float 1.000000e+00)
>  %480 = call float @llvm.AMDIL.clamp.(float %477, float 0.000000e+00, float 1.000000e+00)
>  %481 = call float @fabs(float %207)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %478, float %479, float %480, float %186)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %481, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %126, float %127, float %128, float %129)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %151, float %153, float %155, float %157)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020129
>bf8c007f
>100a0204
>c202012d
>bf8c007f
>d2820005
>04140902
>c2020131
>bf8c007f
>d2820005
>04140903
>c2020135
>bf8c007f
>d282000e
>04140904
>c2020128
>bf8c007f
>100a0204
>c202012c
>bf8c007f
>d2820005
>04140902
>c2020130
>bf8c007f
>d2820005
>04140903
>c2020134
>bf8c007f
>d2820010
>04140904
>100a2110
>d2820006
>04161d0e
>c202012a
>bf8c007f
>100a0204
>c202012e
>bf8c007f
>d2820005
>04140902
>c2020132
>bf8c007f
>d2820005
>04140903
>c2020136
>bf8c007f
>d2820005
>04140904
>d2820006
>041a0b05
>d2060106
>02010106
>7e105b06
>100c110e
>c2020125
>bf8c007f
>080e1c04
>c2020124
>bf8c007f
>08162004
>1012170b
>d2820009
>04260f07
>c2020126
>bf8c007f
>08180a04
>d2820009
>0426190c
>d2060109
>02010109
>7e125b09
>10141307
>081a0d0a
>100e1110
>1016130b
>08280f0b
>101e2914
>d2820012
>043e1b0d
>10101105
>1022130c
>081e1111
>d282000c
>044a1f0f
>d206010c
>0201010c
>7e245b0c
>1026250d
>101a2514
>c0840704
>bf8c007f
>e00c2000
>80021400
>c2020114
>bf8c0070
>10182804
>c2020115
>bf8c007f
>d282000c
>04300915
>c2020116
>bf8c007f
>d2820018
>04300916
>c2020110
>bf8c007f
>10182804
>c2020111
>bf8c007f
>d282000c
>04300915
>c2020112
>bf8c007f
>d282000c
>04300916
>1032190c
>d2820019
>04663118
>c2020118
>bf8c007f
>10342804
>c2020119
>bf8c007f
>d282001a
>04680915
>c202011a
>bf8c007f
>d2820014
>04680916
>d2820015
>04662914
>d2060115
>02010115
>7e2a5b15
>10182b0c
>102c1b0c
>101a2b18
>d2820013
>045a270d
>1024250f
>101e2b14
>d2820012
>044e250f
>d00c0004
>02010112
>d2000012
>00122480
>7e244f12
>c202011c
>bf8c007f
>0e242404
>7e244b12
>1016170c
>d282000a
>042e150d
>d282000b
>042a230f
>d0080008
>02021680
>d2000011
>00210112
>7e145509
>10121509
>c2028138
>bf8c007f
>10121205
>c2028139
>bf8c007f
>d2820009
>04261405
>1014150a
>c202813a
>bf8c007f
>d2820009
>04261405
>7e145509
>10121511
>d00c0008
>0201010b
>d200000b
>00221680
>1016150b
>c202813e
>c2040122
>bf8c007f
>7e220208
>d2820011
>04440b0a
>c2028142
>bf8c007f
>d2820011
>04440b0b
>c2028146
>bf8c007f
>d2820013
>04440b09
>c2028149
>bf8c007f
>08241c05
>c2028148
>bf8c007f
>08282005
>10222914
>d2820011
>04462512
>c202814a
>bf8c007f
>082a0a05
>d2820011
>04462b15
>d2060111
>02010111
>7e2c5b11
>7e225516
>102e2316
>c202814c
>bf8c007f
>102e2e05
>c202814d
>bf8c007f
>d2820017
>045e2205
>10222311
>c202814e
>bf8c007f
>d2820011
>045e2205
>7e225511
>c2028152
>bf8c007f
>d2820018
>044c0b11
>102e2d14
>10262f0c
>10322d12
>d2820012
>044e330d
>102a2d15
>d2820013
>044a2b0f
>d00c0008
>02010113
>d2000012
>00222680
>10242312
>c2028156
>bf8c007f
>d2820014
>04600b12
>082c0d19
>082e0f17
>10302f17
>d2820018
>04622d16
>082a1115
>d2820018
>04622b15
>d2060118
>02010118
>7e305b18
>102c3116
>102e3117
>102e2f0c
>d2820016
>045e2d0d
>102a3115
>d2820015
>045a2b0f
>d00c0008
>02010115
>d2000015
>00222a80
>7e2a4f15
>0e2a2a04
>7e2a4b15
>d0080008
>02022680
>d2000013
>00210115
>10262313
>c202815a
>bf8c007f
>d2820015
>04500b13
>c202815d
>bf8c007f
>08281c05
>c202815c
>bf8c007f
>08202005
>101c2110
>d282000e
>043a2914
>c202815e
>bf8c007f
>082c0a05
>d282000e
>043a2d16
>d206010e
>0201010e
>7e2e5b0e
>7e1c5517
>10301d17
>c2028160
>bf8c007f
>10303005
>c2028161
>bf8c007f
>d2820018
>04621c05
>101c1d0e
>c2028162
>bf8c007f
>d282000e
>04621c05
>7e1c550e
>c2028166
>bf8c007f
>d2820015
>04540b0e
>10302f10
>1020310c
>10322f14
>d2820010
>0442330d
>102c2f16
>d2820014
>04422d0f
>d00c0008
>02010114
>d2000010
>00222880
>10201d10
>c202816a
>bf8c007f
>d2820015
>04540b10
>082e0d19
>08300f18
>10323118
>d2820019
>04662f17
>082c1116
>d2820019
>04662d16
>d2060119
>02010119
>7e325b19
>102e3317
>10303318
>1030310c
>d2820017
>04622f0d
>102c3316
>d2820016
>045e2d0f
>d00c0008
>02010116
>d2000016
>00222c80
>7e2c4f16
>0e2c2c04
>7e2c4b16
>d0080008
>02022880
>d2000014
>00210116
>10281d14
>c202816e
>bf8c007f
>d2820015
>04540b14
>c202817a
>bf8c007f
>062e2a05
>c2028170
>bf8c007f
>102a1805
>c2048171
>bf8c007f
>d2820015
>0454130d
>c2040172
>bf8c007f
>d2820016
>0454110f
>d00c000a
>02010116
>d2000015
>002a2c80
>c205017e
>bf8c007f
>d2820017
>045c1515
>080c0c09
>080e0e05
>10300f07
>d2820018
>04620d06
>08101008
>d2820018
>04621108
>d2060118
>02010118
>7e305b18
>100c3106
>100e3107
>100e0f0c
>d2820006
>041e0d0d
>100e3108
>d2820006
>041a0f0f
>d00c0008
>02010106
>d2000006
>00220c80
>7e0c4f06
>0e0c0c04
>7e0c4b06
>d0080004
>02022c80
>d2000007
>00110106
>c2020182
>bf8c007f
>d2820006
>045c0907
>d2060806
>02010106
>c202013d
>c2028121
>bf8c007f
>7e100205
>d2820008
>0420090a
>c2020141
>bf8c007f
>d2820008
>0420090b
>c2020145
>bf8c007f
>d2820008
>04200909
>c2020151
>bf8c007f
>d2820008
>04200911
>c2020155
>bf8c007f
>d2820008
>04200912
>c2020159
>bf8c007f
>d2820008
>04200913
>c2020165
>bf8c007f
>d2820008
>0420090e
>c2020169
>bf8c007f
>d2820008
>04200910
>c202016d
>bf8c007f
>d2820008
>04200914
>c2020179
>bf8c007f
>06101004
>c202017d
>bf8c007f
>d2820008
>04200915
>c2020181
>bf8c007f
>d2820008
>04200907
>d2060808
>02010108
>c202013c
>c2028120
>bf8c007f
>7e180205
>d282000a
>0430090a
>c2020140
>bf8c007f
>d282000a
>0428090b
>c2020144
>bf8c007f
>d2820009
>04280909
>c2020150
>bf8c007f
>d2820009
>04240911
>c2020154
>bf8c007f
>d2820009
>04240912
>c2020158
>bf8c007f
>d2820009
>04240913
>c2020164
>bf8c007f
>d2820009
>0424090e
>c2020168
>bf8c007f
>d2820009
>04240910
>c202016c
>bf8c007f
>d2820009
>04240914
>c2020178
>bf8c007f
>06121204
>c202017c
>bf8c007f
>d2820009
>04240915
>c2020180
>bf8c007f
>d2820007
>04240907
>d2060807
>02010107
>c2020123
>bf8c007f
>d2060809
>02010004
>f800020f
>09060807
>d2060105
>02010105
>bf8c070f
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..36]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD TEMP[3], TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: SUB TEMP[5], CONST[28], TEMP[6]
> 78: DP3 TEMP[7].x, TEMP[5], TEMP[5]
> 79: RSQ TEMP[7].x, |TEMP[7]|
> 80: MUL TEMP[5], TEMP[5], TEMP[7].xxxx
> 81: DP3 TEMP[2].x, TEMP[0], CONST[28]
> 82: DP3 TEMP[2].y, TEMP[0], TEMP[5]
> 83: LIT TEMP[1], TEMP[2]
> 84: ADD TEMP[3], CONST[30], TEMP[3]
> 85: MAD TEMP[3], TEMP[1].yyyy, CONST[31], TEMP[3]
> 86: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[32], TEMP[3]
> 87: MOV OUT[2], IN[2]
> 88: DP3 TEMP[2], TEMP[0], TEMP[6]
> 89: ADD TEMP[2], TEMP[2], TEMP[2]
> 90: MAD TEMP[1].xyz, -TEMP[2], TEMP[0], TEMP[6]
> 91: MOV TEMP[1].w, IN[3]
> 92: MUL TEMP[2], TEMP[1].xxxx, CONST[33]
> 93: MAD TEMP[2], TEMP[1].yyyy, CONST[34], TEMP[2]
> 94: MAD TEMP[2], TEMP[1].zzzz, CONST[35], TEMP[2]
> 95: MAD OUT[3], TEMP[1].wwww, CONST[36], TEMP[2]
> 96: MOV OUT[4], IN[4]
> 97: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 528)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 532)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 536)
>  %113 = call float @llvm.SI.load.const(<16 x i8> %10, i32 540)
>  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 544)
>  %115 = call float @llvm.SI.load.const(<16 x i8> %10, i32 548)
>  %116 = call float @llvm.SI.load.const(<16 x i8> %10, i32 552)
>  %117 = call float @llvm.SI.load.const(<16 x i8> %10, i32 556)
>  %118 = call float @llvm.SI.load.const(<16 x i8> %10, i32 560)
>  %119 = call float @llvm.SI.load.const(<16 x i8> %10, i32 564)
>  %120 = call float @llvm.SI.load.const(<16 x i8> %10, i32 568)
>  %121 = call float @llvm.SI.load.const(<16 x i8> %10, i32 572)
>  %122 = call float @llvm.SI.load.const(<16 x i8> %10, i32 576)
>  %123 = call float @llvm.SI.load.const(<16 x i8> %10, i32 580)
>  %124 = call float @llvm.SI.load.const(<16 x i8> %10, i32 584)
>  %125 = call float @llvm.SI.load.const(<16 x i8> %10, i32 588)
>  %126 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %127 = load <16 x i8> addrspace(2)* %126, !tbaa !0
>  %128 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %127, i32 0, i32 %5)
>  %129 = extractelement <4 x float> %128, i32 0
>  %130 = extractelement <4 x float> %128, i32 1
>  %131 = extractelement <4 x float> %128, i32 2
>  %132 = extractelement <4 x float> %128, i32 3
>  %133 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %134 = load <16 x i8> addrspace(2)* %133, !tbaa !0
>  %135 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %134, i32 0, i32 %5)
>  %136 = extractelement <4 x float> %135, i32 0
>  %137 = extractelement <4 x float> %135, i32 1
>  %138 = extractelement <4 x float> %135, i32 2
>  %139 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %140 = load <16 x i8> addrspace(2)* %139, !tbaa !0
>  %141 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %140, i32 0, i32 %5)
>  %142 = extractelement <4 x float> %141, i32 0
>  %143 = extractelement <4 x float> %141, i32 1
>  %144 = extractelement <4 x float> %141, i32 2
>  %145 = extractelement <4 x float> %141, i32 3
>  %146 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %147 = load <16 x i8> addrspace(2)* %146, !tbaa !0
>  %148 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %147, i32 0, i32 %5)
>  %149 = extractelement <4 x float> %148, i32 3
>  %150 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %151 = load <16 x i8> addrspace(2)* %150, !tbaa !0
>  %152 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %151, i32 0, i32 %5)
>  %153 = extractelement <4 x float> %152, i32 0
>  %154 = extractelement <4 x float> %152, i32 1
>  %155 = extractelement <4 x float> %152, i32 2
>  %156 = extractelement <4 x float> %152, i32 3
>  %157 = fmul float %129, %11
>  %158 = fmul float %129, %12
>  %159 = fmul float %129, %13
>  %160 = fmul float %129, %14
>  %161 = fmul float %130, %15
>  %162 = fadd float %161, %157
>  %163 = fmul float %130, %16
>  %164 = fadd float %163, %158
>  %165 = fmul float %130, %17
>  %166 = fadd float %165, %159
>  %167 = fmul float %130, %18
>  %168 = fadd float %167, %160
>  %169 = fmul float %131, %19
>  %170 = fadd float %169, %162
>  %171 = fmul float %131, %20
>  %172 = fadd float %171, %164
>  %173 = fmul float %131, %21
>  %174 = fadd float %173, %166
>  %175 = fmul float %131, %22
>  %176 = fadd float %175, %168
>  %177 = fmul float %132, %23
>  %178 = fadd float %177, %170
>  %179 = fmul float %132, %24
>  %180 = fadd float %179, %172
>  %181 = fmul float %132, %25
>  %182 = fadd float %181, %174
>  %183 = fmul float %132, %26
>  %184 = fadd float %183, %176
>  %185 = fmul float %136, %27
>  %186 = fmul float %137, %28
>  %187 = fadd float %186, %185
>  %188 = fmul float %138, %29
>  %189 = fadd float %187, %188
>  %190 = fmul float %136, %30
>  %191 = fmul float %137, %31
>  %192 = fadd float %191, %190
>  %193 = fmul float %138, %32
>  %194 = fadd float %192, %193
>  %195 = fmul float %136, %33
>  %196 = fmul float %137, %34
>  %197 = fadd float %196, %195
>  %198 = fmul float %138, %35
>  %199 = fadd float %197, %198
>  %200 = fmul float %189, %189
>  %201 = fmul float %194, %194
>  %202 = fadd float %201, %200
>  %203 = fmul float %199, %199
>  %204 = fadd float %202, %203
>  %205 = call float @fabs(float %204)
>  %206 = call float @llvm.AMDGPU.rsq(float %205)
>  %207 = fmul float %189, %206
>  %208 = fmul float %194, %206
>  %209 = fmul float %199, %206
>  %210 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %211 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %212 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %213 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %214 = fmul float %129, %44
>  %215 = fmul float %129, %45
>  %216 = fmul float %129, %46
>  %217 = fmul float %130, %47
>  %218 = fadd float %217, %214
>  %219 = fmul float %130, %48
>  %220 = fadd float %219, %215
>  %221 = fmul float %130, %49
>  %222 = fadd float %221, %216
>  %223 = fmul float %131, %50
>  %224 = fadd float %223, %218
>  %225 = fmul float %131, %51
>  %226 = fadd float %225, %220
>  %227 = fmul float %131, %52
>  %228 = fadd float %227, %222
>  %229 = fmul float %132, %53
>  %230 = fadd float %229, %224
>  %231 = fmul float %132, %54
>  %232 = fadd float %231, %226
>  %233 = fmul float %132, %55
>  %234 = fadd float %233, %228
>  %235 = fsub float %41, %230
>  %236 = fsub float %42, %232
>  %237 = fsub float %43, %234
>  %238 = fmul float %235, %235
>  %239 = fmul float %236, %236
>  %240 = fadd float %239, %238
>  %241 = fmul float %237, %237
>  %242 = fadd float %240, %241
>  %243 = call float @fabs(float %242)
>  %244 = call float @llvm.AMDGPU.rsq(float %243)
>  %245 = fmul float %235, %244
>  %246 = fmul float %236, %244
>  %247 = fmul float %237, %244
>  %248 = fdiv float 1.000000e+00, %244
>  %249 = fmul float %244, %248
>  %250 = fmul float %248, %248
>  %251 = fmul float %56, %249
>  %252 = fmul float %57, %248
>  %253 = fadd float %252, %251
>  %254 = fmul float %58, %250
>  %255 = fadd float %253, %254
>  %256 = fdiv float 1.000000e+00, %255
>  %257 = fmul float %230, %230
>  %258 = fmul float %232, %232
>  %259 = fadd float %258, %257
>  %260 = fmul float %234, %234
>  %261 = fadd float %259, %260
>  %262 = call float @fabs(float %261)
>  %263 = call float @llvm.AMDGPU.rsq(float %262)
>  %264 = fmul float %230, %263
>  %265 = fmul float %232, %263
>  %266 = fmul float %234, %263
>  %267 = fsub float %245, %264
>  %268 = fsub float %246, %265
>  %269 = fsub float %247, %266
>  %270 = fmul float %267, %267
>  %271 = fmul float %268, %268
>  %272 = fadd float %271, %270
>  %273 = fmul float %269, %269
>  %274 = fadd float %272, %273
>  %275 = call float @fabs(float %274)
>  %276 = call float @llvm.AMDGPU.rsq(float %275)
>  %277 = fmul float %267, %276
>  %278 = fmul float %268, %276
>  %279 = fmul float %269, %276
>  %280 = fmul float %207, %245
>  %281 = fmul float %208, %246
>  %282 = fadd float %281, %280
>  %283 = fmul float %209, %247
>  %284 = fadd float %282, %283
>  %285 = fmul float %207, %277
>  %286 = fmul float %208, %278
>  %287 = fadd float %286, %285
>  %288 = fmul float %209, %279
>  %289 = fadd float %287, %288
>  %290 = fcmp uge float %284, 0.000000e+00
>  %291 = select i1 %290, float %284, float 0.000000e+00
>  %292 = fcmp uge float %289, 0.000000e+00
>  %293 = select i1 %292, float %289, float 0.000000e+00
>  %294 = call float @llvm.pow.f32(float %293, float %36)
>  %295 = call float @llvm.AMDGPU.cndlt(float %284, float 0.000000e+00, float %294)
>  %296 = fmul float 1.000000e+00, %256
>  %297 = fmul float %291, %256
>  %298 = fmul float %295, %256
>  %299 = fmul float %296, %59
>  %300 = fadd float %299, %37
>  %301 = fmul float %296, %60
>  %302 = fadd float %301, %38
>  %303 = fmul float %296, %61
>  %304 = fadd float %303, %39
>  %305 = fmul float %297, %62
>  %306 = fadd float %305, %300
>  %307 = fmul float %297, %63
>  %308 = fadd float %307, %302
>  %309 = fmul float %297, %64
>  %310 = fadd float %309, %304
>  %311 = fmul float %298, %65
>  %312 = fadd float %311, %306
>  %313 = fmul float %298, %66
>  %314 = fadd float %313, %308
>  %315 = fmul float %298, %67
>  %316 = fadd float %315, %310
>  %317 = fsub float %68, %230
>  %318 = fsub float %69, %232
>  %319 = fsub float %70, %234
>  %320 = fmul float %317, %317
>  %321 = fmul float %318, %318
>  %322 = fadd float %321, %320
>  %323 = fmul float %319, %319
>  %324 = fadd float %322, %323
>  %325 = call float @fabs(float %324)
>  %326 = call float @llvm.AMDGPU.rsq(float %325)
>  %327 = fmul float %317, %326
>  %328 = fmul float %318, %326
>  %329 = fmul float %319, %326
>  %330 = fdiv float 1.000000e+00, %326
>  %331 = fmul float %326, %330
>  %332 = fmul float %330, %330
>  %333 = fmul float %71, %331
>  %334 = fmul float %72, %330
>  %335 = fadd float %334, %333
>  %336 = fmul float %73, %332
>  %337 = fadd float %335, %336
>  %338 = fdiv float 1.000000e+00, %337
>  %339 = fsub float %327, %264
>  %340 = fsub float %328, %265
>  %341 = fsub float %329, %266
>  %342 = fmul float %339, %339
>  %343 = fmul float %340, %340
>  %344 = fadd float %343, %342
>  %345 = fmul float %341, %341
>  %346 = fadd float %344, %345
>  %347 = call float @fabs(float %346)
>  %348 = call float @llvm.AMDGPU.rsq(float %347)
>  %349 = fmul float %339, %348
>  %350 = fmul float %340, %348
>  %351 = fmul float %341, %348
>  %352 = fmul float %207, %327
>  %353 = fmul float %208, %328
>  %354 = fadd float %353, %352
>  %355 = fmul float %209, %329
>  %356 = fadd float %354, %355
>  %357 = fmul float %207, %349
>  %358 = fmul float %208, %350
>  %359 = fadd float %358, %357
>  %360 = fmul float %209, %351
>  %361 = fadd float %359, %360
>  %362 = fcmp uge float %356, 0.000000e+00
>  %363 = select i1 %362, float %356, float 0.000000e+00
>  %364 = fcmp uge float %361, 0.000000e+00
>  %365 = select i1 %364, float %361, float 0.000000e+00
>  %366 = call float @llvm.pow.f32(float %365, float %36)
>  %367 = call float @llvm.AMDGPU.cndlt(float %356, float 0.000000e+00, float %366)
>  %368 = fmul float 1.000000e+00, %338
>  %369 = fmul float %363, %338
>  %370 = fmul float %367, %338
>  %371 = fmul float %368, %74
>  %372 = fadd float %371, %312
>  %373 = fmul float %368, %75
>  %374 = fadd float %373, %314
>  %375 = fmul float %368, %76
>  %376 = fadd float %375, %316
>  %377 = fmul float %369, %77
>  %378 = fadd float %377, %372
>  %379 = fmul float %369, %78
>  %380 = fadd float %379, %374
>  %381 = fmul float %369, %79
>  %382 = fadd float %381, %376
>  %383 = fmul float %370, %80
>  %384 = fadd float %383, %378
>  %385 = fmul float %370, %81
>  %386 = fadd float %385, %380
>  %387 = fmul float %370, %82
>  %388 = fadd float %387, %382
>  %389 = fsub float %83, %230
>  %390 = fsub float %84, %232
>  %391 = fsub float %85, %234
>  %392 = fmul float %389, %389
>  %393 = fmul float %390, %390
>  %394 = fadd float %393, %392
>  %395 = fmul float %391, %391
>  %396 = fadd float %394, %395
>  %397 = call float @fabs(float %396)
>  %398 = call float @llvm.AMDGPU.rsq(float %397)
>  %399 = fmul float %389, %398
>  %400 = fmul float %390, %398
>  %401 = fmul float %391, %398
>  %402 = fdiv float 1.000000e+00, %398
>  %403 = fmul float %398, %402
>  %404 = fmul float %402, %402
>  %405 = fmul float %86, %403
>  %406 = fmul float %87, %402
>  %407 = fadd float %406, %405
>  %408 = fmul float %88, %404
>  %409 = fadd float %407, %408
>  %410 = fdiv float 1.000000e+00, %409
>  %411 = fsub float %399, %264
>  %412 = fsub float %400, %265
>  %413 = fsub float %401, %266
>  %414 = fmul float %411, %411
>  %415 = fmul float %412, %412
>  %416 = fadd float %415, %414
>  %417 = fmul float %413, %413
>  %418 = fadd float %416, %417
>  %419 = call float @fabs(float %418)
>  %420 = call float @llvm.AMDGPU.rsq(float %419)
>  %421 = fmul float %411, %420
>  %422 = fmul float %412, %420
>  %423 = fmul float %413, %420
>  %424 = fmul float %207, %399
>  %425 = fmul float %208, %400
>  %426 = fadd float %425, %424
>  %427 = fmul float %209, %401
>  %428 = fadd float %426, %427
>  %429 = fmul float %207, %421
>  %430 = fmul float %208, %422
>  %431 = fadd float %430, %429
>  %432 = fmul float %209, %423
>  %433 = fadd float %431, %432
>  %434 = fcmp uge float %428, 0.000000e+00
>  %435 = select i1 %434, float %428, float 0.000000e+00
>  %436 = fcmp uge float %433, 0.000000e+00
>  %437 = select i1 %436, float %433, float 0.000000e+00
>  %438 = call float @llvm.pow.f32(float %437, float %36)
>  %439 = call float @llvm.AMDGPU.cndlt(float %428, float 0.000000e+00, float %438)
>  %440 = fmul float 1.000000e+00, %410
>  %441 = fmul float %435, %410
>  %442 = fmul float %439, %410
>  %443 = fmul float %440, %89
>  %444 = fadd float %443, %384
>  %445 = fmul float %440, %90
>  %446 = fadd float %445, %386
>  %447 = fmul float %440, %91
>  %448 = fadd float %447, %388
>  %449 = fmul float %441, %92
>  %450 = fadd float %449, %444
>  %451 = fmul float %441, %93
>  %452 = fadd float %451, %446
>  %453 = fmul float %441, %94
>  %454 = fadd float %453, %448
>  %455 = fmul float %442, %95
>  %456 = fadd float %455, %450
>  %457 = fmul float %442, %96
>  %458 = fadd float %457, %452
>  %459 = fmul float %442, %97
>  %460 = fadd float %459, %454
>  %461 = fsub float %98, %264
>  %462 = fsub float %99, %265
>  %463 = fsub float %100, %266
>  %464 = fmul float %461, %461
>  %465 = fmul float %462, %462
>  %466 = fadd float %465, %464
>  %467 = fmul float %463, %463
>  %468 = fadd float %466, %467
>  %469 = call float @fabs(float %468)
>  %470 = call float @llvm.AMDGPU.rsq(float %469)
>  %471 = fmul float %461, %470
>  %472 = fmul float %462, %470
>  %473 = fmul float %463, %470
>  %474 = fmul float %207, %98
>  %475 = fmul float %208, %99
>  %476 = fadd float %475, %474
>  %477 = fmul float %209, %100
>  %478 = fadd float %476, %477
>  %479 = fmul float %207, %471
>  %480 = fmul float %208, %472
>  %481 = fadd float %480, %479
>  %482 = fmul float %209, %473
>  %483 = fadd float %481, %482
>  %484 = fcmp uge float %478, 0.000000e+00
>  %485 = select i1 %484, float %478, float 0.000000e+00
>  %486 = fcmp uge float %483, 0.000000e+00
>  %487 = select i1 %486, float %483, float 0.000000e+00
>  %488 = call float @llvm.pow.f32(float %487, float %36)
>  %489 = call float @llvm.AMDGPU.cndlt(float %478, float 0.000000e+00, float %488)
>  %490 = fadd float %101, %456
>  %491 = fadd float %102, %458
>  %492 = fadd float %103, %460
>  %493 = fmul float %485, %104
>  %494 = fadd float %493, %490
>  %495 = fmul float %485, %105
>  %496 = fadd float %495, %491
>  %497 = fmul float %485, %106
>  %498 = fadd float %497, %492
>  %499 = fmul float %489, %107
>  %500 = fadd float %499, %494
>  %501 = fmul float %489, %108
>  %502 = fadd float %501, %496
>  %503 = fmul float %489, %109
>  %504 = fadd float %503, %498
>  %505 = call float @llvm.AMDIL.clamp.(float %500, float 0.000000e+00, float 1.000000e+00)
>  %506 = call float @llvm.AMDIL.clamp.(float %502, float 0.000000e+00, float 1.000000e+00)
>  %507 = call float @llvm.AMDIL.clamp.(float %504, float 0.000000e+00, float 1.000000e+00)
>  %508 = fmul float %207, %264
>  %509 = fmul float %208, %265
>  %510 = fadd float %509, %508
>  %511 = fmul float %209, %266
>  %512 = fadd float %510, %511
>  %513 = fadd float %512, %512
>  %514 = fadd float %512, %512
>  %515 = fadd float %512, %512
>  %516 = fsub float -0.000000e+00, %513
>  %517 = fmul float %516, %207
>  %518 = fadd float %517, %264
>  %519 = fsub float -0.000000e+00, %514
>  %520 = fmul float %519, %208
>  %521 = fadd float %520, %265
>  %522 = fsub float -0.000000e+00, %515
>  %523 = fmul float %522, %209
>  %524 = fadd float %523, %266
>  %525 = fmul float %518, %110
>  %526 = fmul float %518, %111
>  %527 = fmul float %518, %112
>  %528 = fmul float %518, %113
>  %529 = fmul float %521, %114
>  %530 = fadd float %529, %525
>  %531 = fmul float %521, %115
>  %532 = fadd float %531, %526
>  %533 = fmul float %521, %116
>  %534 = fadd float %533, %527
>  %535 = fmul float %521, %117
>  %536 = fadd float %535, %528
>  %537 = fmul float %524, %118
>  %538 = fadd float %537, %530
>  %539 = fmul float %524, %119
>  %540 = fadd float %539, %532
>  %541 = fmul float %524, %120
>  %542 = fadd float %541, %534
>  %543 = fmul float %524, %121
>  %544 = fadd float %543, %536
>  %545 = fmul float %149, %122
>  %546 = fadd float %545, %538
>  %547 = fmul float %149, %123
>  %548 = fadd float %547, %540
>  %549 = fmul float %149, %124
>  %550 = fadd float %549, %542
>  %551 = fmul float %149, %125
>  %552 = fadd float %551, %544
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %505, float %506, float %507, float %213)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %142, float %143, float %144, float %145)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %546, float %548, float %550, float %552)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %153, float %154, float %155, float %156)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %178, float %180, float %182, float %184)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>082c0d16
>d2820018
>04622d16
>d2060118
>02010118
>7e305b18
>102e3117
>102a3115
>102a2b09
>d2820015
>04562f0a
>102c3116
>d2820015
>04562d08
>d00c0008
>02010115
>d2000015
>00222a80
>7e2a4f15
>0e2a2a04
>7e2a4b15
>d0080008
>02022280
>d2000011
>00210115
>10221d11
>c202816e
>bf8c007f
>d2820014
>04500b11
>c202817a
>bf8c007f
>062c2805
>c2028170
>bf8c007f
>10281205
>c2048171
>bf8c007f
>d2820014
>0450130a
>c2040172
>bf8c007f
>d2820015
>04501108
>d00c000a
>02010115
>d2000014
>002a2a80
>c205017e
>bf8c007f
>d2820017
>04581514
>082c0a09
>08300e05
>10323118
>d282001a
>04662d16
>08320c08
>d282001a
>046a3319
>d206011a
>0201011a
>7e345b1a
>102c3516
>10303518
>10303109
>d2820016
>04622d0a
>10303519
>d2820016
>045a3108
>d00c0008
>02010116
>d2000016
>00222c80
>7e2c4f16
>0e2c2c04
>7e2c4b16
>d0080004
>02022a80
>d2000016
>00110116
>c2020182
>bf8c007f
>d2820015
>045c0916
>d2060815
>02010115
>c202013d
>c2028121
>bf8c007f
>7e2e0205
>d2820017
>045c090c
>c2020141
>bf8c007f
>d2820017
>045c090d
>c2020145
>bf8c007f
>d2820017
>045c090b
>c2020151
>bf8c007f
>d2820017
>045c0910
>c2020155
>bf8c007f
>d2820017
>045c0912
>c2020159
>bf8c007f
>d2820017
>045c0913
>c2020165
>bf8c007f
>d2820017
>045c090e
>c2020169
>bf8c007f
>d2820017
>045c090f
>c202016d
>bf8c007f
>d2820017
>045c0911
>c2020179
>bf8c007f
>062e2e04
>c202017d
>bf8c007f
>d2820017
>045c0914
>c2020181
>bf8c007f
>d2820017
>045c0916
>d2060817
>02010117
>c202013c
>c2028120
>bf8c007f
>7e300205
>d282000c
>0460090c
>c2020140
>bf8c007f
>d282000c
>0430090d
>c2020144
>bf8c007f
>d282000b
>0430090b
>c2020150
>bf8c007f
>d282000b
>042c0910
>c2020154
>bf8c007f
>d282000b
>042c0912
>c2020158
>bf8c007f
>d282000b
>042c0913
>c2020164
>bf8c007f
>d282000b
>042c090e
>c2020168
>bf8c007f
>d282000b
>042c090f
>c202016c
>bf8c007f
>d282000b
>042c0911
>c2020178
>bf8c007f
>06161604
>c202017c
>bf8c007f
>d282000b
>042c0914
>c2020180
>bf8c007f
>d282000b
>042c0916
>d206080b
>0201010b
>c2020123
>bf8c007f
>d206080c
>02010004
>f800020f
>0c15170b
>c0840708
>bf8c000f
>e00c2000
>80020b00
>bf8c0770
>f800021f
>0e0d0c0b
>bf8c070f
>10160f09
>d282000b
>042e0b0a
>d282000b
>042e0d08
>0616170b
>1014150b
>080a1505
>1012130b
>080e1307
>c2020187
>bf8c007f
>10120e04
>c202018b
>bf8c007f
>d2820009
>04240905
>1010110b
>080c1106
>c202018f
>bf8c007f
>d282000c
>04240906
>c084070c
>bf8c007f
>e00c2000
>80020800
>c2020193
>bf8c0070
>d282000c
>0430090b
>c2020186
>bf8c007f
>101a0e04
>c202018a
>bf8c007f
>d282000d
>04340905
>c202018e
>bf8c007f
>d282000d
>04340906
>c2020192
>bf8c007f
>d282000d
>0434090b
>c2020185
>bf8c007f
>101c0e04
>c2020189
>bf8c007f
>d282000e
>04380905
>c202018d
>bf8c007f
>d282000e
>04380906
>c2020191
>bf8c007f
>d282000e
>0438090b
>c2020184
>bf8c007f
>100e0e04
>c2020188
>bf8c007f
>d2820005
>041c0905
>c202018c
>bf8c007f
>d2820005
>04140906
>c2020190
>bf8c007f
>d2820005
>0414090b
>f800022f
>0c0d0e05
>c0820710
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..32]
>DCL TEMP[0..9]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD TEMP[3], TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: SUB TEMP[5], CONST[28], TEMP[6]
> 78: DP3 TEMP[7].x, TEMP[5], TEMP[5]
> 79: RSQ TEMP[7].x, |TEMP[7]|
> 80: MUL TEMP[5], TEMP[5], TEMP[7].xxxx
> 81: DP3 TEMP[2].x, TEMP[0], CONST[28]
> 82: DP3 TEMP[2].y, TEMP[0], TEMP[5]
> 83: LIT TEMP[1], TEMP[2]
> 84: ADD TEMP[3], CONST[30], TEMP[3]
> 85: MAD TEMP[3], TEMP[1].yyyy, CONST[31], TEMP[3]
> 86: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[32], TEMP[3]
> 87: MOV OUT[2], IN[2]
> 88: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %110 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %111 = load <16 x i8> addrspace(2)* %110, !tbaa !0
>  %112 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %111, i32 0, i32 %5)
>  %113 = extractelement <4 x float> %112, i32 0
>  %114 = extractelement <4 x float> %112, i32 1
>  %115 = extractelement <4 x float> %112, i32 2
>  %116 = extractelement <4 x float> %112, i32 3
>  %117 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %118 = load <16 x i8> addrspace(2)* %117, !tbaa !0
>  %119 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %118, i32 0, i32 %5)
>  %120 = extractelement <4 x float> %119, i32 0
>  %121 = extractelement <4 x float> %119, i32 1
>  %122 = extractelement <4 x float> %119, i32 2
>  %123 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %124 = load <16 x i8> addrspace(2)* %123, !tbaa !0
>  %125 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %124, i32 0, i32 %5)
>  %126 = extractelement <4 x float> %125, i32 0
>  %127 = extractelement <4 x float> %125, i32 1
>  %128 = extractelement <4 x float> %125, i32 2
>  %129 = extractelement <4 x float> %125, i32 3
>  %130 = fmul float %113, %11
>  %131 = fmul float %113, %12
>  %132 = fmul float %113, %13
>  %133 = fmul float %113, %14
>  %134 = fmul float %114, %15
>  %135 = fadd float %134, %130
>  %136 = fmul float %114, %16
>  %137 = fadd float %136, %131
>  %138 = fmul float %114, %17
>  %139 = fadd float %138, %132
>  %140 = fmul float %114, %18
>  %141 = fadd float %140, %133
>  %142 = fmul float %115, %19
>  %143 = fadd float %142, %135
>  %144 = fmul float %115, %20
>  %145 = fadd float %144, %137
>  %146 = fmul float %115, %21
>  %147 = fadd float %146, %139
>  %148 = fmul float %115, %22
>  %149 = fadd float %148, %141
>  %150 = fmul float %116, %23
>  %151 = fadd float %150, %143
>  %152 = fmul float %116, %24
>  %153 = fadd float %152, %145
>  %154 = fmul float %116, %25
>  %155 = fadd float %154, %147
>  %156 = fmul float %116, %26
>  %157 = fadd float %156, %149
>  %158 = fmul float %120, %27
>  %159 = fmul float %121, %28
>  %160 = fadd float %159, %158
>  %161 = fmul float %122, %29
>  %162 = fadd float %160, %161
>  %163 = fmul float %120, %30
>  %164 = fmul float %121, %31
>  %165 = fadd float %164, %163
>  %166 = fmul float %122, %32
>  %167 = fadd float %165, %166
>  %168 = fmul float %120, %33
>  %169 = fmul float %121, %34
>  %170 = fadd float %169, %168
>  %171 = fmul float %122, %35
>  %172 = fadd float %170, %171
>  %173 = fmul float %162, %162
>  %174 = fmul float %167, %167
>  %175 = fadd float %174, %173
>  %176 = fmul float %172, %172
>  %177 = fadd float %175, %176
>  %178 = call float @fabs(float %177)
>  %179 = call float @llvm.AMDGPU.rsq(float %178)
>  %180 = fmul float %162, %179
>  %181 = fmul float %167, %179
>  %182 = fmul float %172, %179
>  %183 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %184 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %185 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %186 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %187 = fmul float %113, %44
>  %188 = fmul float %113, %45
>  %189 = fmul float %113, %46
>  %190 = fmul float %114, %47
>  %191 = fadd float %190, %187
>  %192 = fmul float %114, %48
>  %193 = fadd float %192, %188
>  %194 = fmul float %114, %49
>  %195 = fadd float %194, %189
>  %196 = fmul float %115, %50
>  %197 = fadd float %196, %191
>  %198 = fmul float %115, %51
>  %199 = fadd float %198, %193
>  %200 = fmul float %115, %52
>  %201 = fadd float %200, %195
>  %202 = fmul float %116, %53
>  %203 = fadd float %202, %197
>  %204 = fmul float %116, %54
>  %205 = fadd float %204, %199
>  %206 = fmul float %116, %55
>  %207 = fadd float %206, %201
>  %208 = fsub float %41, %203
>  %209 = fsub float %42, %205
>  %210 = fsub float %43, %207
>  %211 = fmul float %208, %208
>  %212 = fmul float %209, %209
>  %213 = fadd float %212, %211
>  %214 = fmul float %210, %210
>  %215 = fadd float %213, %214
>  %216 = call float @fabs(float %215)
>  %217 = call float @llvm.AMDGPU.rsq(float %216)
>  %218 = fmul float %208, %217
>  %219 = fmul float %209, %217
>  %220 = fmul float %210, %217
>  %221 = fdiv float 1.000000e+00, %217
>  %222 = fmul float %217, %221
>  %223 = fmul float %221, %221
>  %224 = fmul float %56, %222
>  %225 = fmul float %57, %221
>  %226 = fadd float %225, %224
>  %227 = fmul float %58, %223
>  %228 = fadd float %226, %227
>  %229 = fdiv float 1.000000e+00, %228
>  %230 = fmul float %203, %203
>  %231 = fmul float %205, %205
>  %232 = fadd float %231, %230
>  %233 = fmul float %207, %207
>  %234 = fadd float %232, %233
>  %235 = call float @fabs(float %234)
>  %236 = call float @llvm.AMDGPU.rsq(float %235)
>  %237 = fmul float %203, %236
>  %238 = fmul float %205, %236
>  %239 = fmul float %207, %236
>  %240 = fsub float %218, %237
>  %241 = fsub float %219, %238
>  %242 = fsub float %220, %239
>  %243 = fmul float %240, %240
>  %244 = fmul float %241, %241
>  %245 = fadd float %244, %243
>  %246 = fmul float %242, %242
>  %247 = fadd float %245, %246
>  %248 = call float @fabs(float %247)
>  %249 = call float @llvm.AMDGPU.rsq(float %248)
>  %250 = fmul float %240, %249
>  %251 = fmul float %241, %249
>  %252 = fmul float %242, %249
>  %253 = fmul float %180, %218
>  %254 = fmul float %181, %219
>  %255 = fadd float %254, %253
>  %256 = fmul float %182, %220
>  %257 = fadd float %255, %256
>  %258 = fmul float %180, %250
>  %259 = fmul float %181, %251
>  %260 = fadd float %259, %258
>  %261 = fmul float %182, %252
>  %262 = fadd float %260, %261
>  %263 = fcmp uge float %257, 0.000000e+00
>  %264 = select i1 %263, float %257, float 0.000000e+00
>  %265 = fcmp uge float %262, 0.000000e+00
>  %266 = select i1 %265, float %262, float 0.000000e+00
>  %267 = call float @llvm.pow.f32(float %266, float %36)
>  %268 = call float @llvm.AMDGPU.cndlt(float %257, float 0.000000e+00, float %267)
>  %269 = fmul float 1.000000e+00, %229
>  %270 = fmul float %264, %229
>  %271 = fmul float %268, %229
>  %272 = fmul float %269, %59
>  %273 = fadd float %272, %37
>  %274 = fmul float %269, %60
>  %275 = fadd float %274, %38
>  %276 = fmul float %269, %61
>  %277 = fadd float %276, %39
>  %278 = fmul float %270, %62
>  %279 = fadd float %278, %273
>  %280 = fmul float %270, %63
>  %281 = fadd float %280, %275
>  %282 = fmul float %270, %64
>  %283 = fadd float %282, %277
>  %284 = fmul float %271, %65
>  %285 = fadd float %284, %279
>  %286 = fmul float %271, %66
>  %287 = fadd float %286, %281
>  %288 = fmul float %271, %67
>  %289 = fadd float %288, %283
>  %290 = fsub float %68, %203
>  %291 = fsub float %69, %205
>  %292 = fsub float %70, %207
>  %293 = fmul float %290, %290
>  %294 = fmul float %291, %291
>  %295 = fadd float %294, %293
>  %296 = fmul float %292, %292
>  %297 = fadd float %295, %296
>  %298 = call float @fabs(float %297)
>  %299 = call float @llvm.AMDGPU.rsq(float %298)
>  %300 = fmul float %290, %299
>  %301 = fmul float %291, %299
>  %302 = fmul float %292, %299
>  %303 = fdiv float 1.000000e+00, %299
>  %304 = fmul float %299, %303
>  %305 = fmul float %303, %303
>  %306 = fmul float %71, %304
>  %307 = fmul float %72, %303
>  %308 = fadd float %307, %306
>  %309 = fmul float %73, %305
>  %310 = fadd float %308, %309
>  %311 = fdiv float 1.000000e+00, %310
>  %312 = fsub float %300, %237
>  %313 = fsub float %301, %238
>  %314 = fsub float %302, %239
>  %315 = fmul float %312, %312
>  %316 = fmul float %313, %313
>  %317 = fadd float %316, %315
>  %318 = fmul float %314, %314
>  %319 = fadd float %317, %318
>  %320 = call float @fabs(float %319)
>  %321 = call float @llvm.AMDGPU.rsq(float %320)
>  %322 = fmul float %312, %321
>  %323 = fmul float %313, %321
>  %324 = fmul float %314, %321
>  %325 = fmul float %180, %300
>  %326 = fmul float %181, %301
>  %327 = fadd float %326, %325
>  %328 = fmul float %182, %302
>  %329 = fadd float %327, %328
>  %330 = fmul float %180, %322
>  %331 = fmul float %181, %323
>  %332 = fadd float %331, %330
>  %333 = fmul float %182, %324
>  %334 = fadd float %332, %333
>  %335 = fcmp uge float %329, 0.000000e+00
>  %336 = select i1 %335, float %329, float 0.000000e+00
>  %337 = fcmp uge float %334, 0.000000e+00
>  %338 = select i1 %337, float %334, float 0.000000e+00
>  %339 = call float @llvm.pow.f32(float %338, float %36)
>  %340 = call float @llvm.AMDGPU.cndlt(float %329, float 0.000000e+00, float %339)
>  %341 = fmul float 1.000000e+00, %311
>  %342 = fmul float %336, %311
>  %343 = fmul float %340, %311
>  %344 = fmul float %341, %74
>  %345 = fadd float %344, %285
>  %346 = fmul float %341, %75
>  %347 = fadd float %346, %287
>  %348 = fmul float %341, %76
>  %349 = fadd float %348, %289
>  %350 = fmul float %342, %77
>  %351 = fadd float %350, %345
>  %352 = fmul float %342, %78
>  %353 = fadd float %352, %347
>  %354 = fmul float %342, %79
>  %355 = fadd float %354, %349
>  %356 = fmul float %343, %80
>  %357 = fadd float %356, %351
>  %358 = fmul float %343, %81
>  %359 = fadd float %358, %353
>  %360 = fmul float %343, %82
>  %361 = fadd float %360, %355
>  %362 = fsub float %83, %203
>  %363 = fsub float %84, %205
>  %364 = fsub float %85, %207
>  %365 = fmul float %362, %362
>  %366 = fmul float %363, %363
>  %367 = fadd float %366, %365
>  %368 = fmul float %364, %364
>  %369 = fadd float %367, %368
>  %370 = call float @fabs(float %369)
>  %371 = call float @llvm.AMDGPU.rsq(float %370)
>  %372 = fmul float %362, %371
>  %373 = fmul float %363, %371
>  %374 = fmul float %364, %371
>  %375 = fdiv float 1.000000e+00, %371
>  %376 = fmul float %371, %375
>  %377 = fmul float %375, %375
>  %378 = fmul float %86, %376
>  %379 = fmul float %87, %375
>  %380 = fadd float %379, %378
>  %381 = fmul float %88, %377
>  %382 = fadd float %380, %381
>  %383 = fdiv float 1.000000e+00, %382
>  %384 = fsub float %372, %237
>  %385 = fsub float %373, %238
>  %386 = fsub float %374, %239
>  %387 = fmul float %384, %384
>  %388 = fmul float %385, %385
>  %389 = fadd float %388, %387
>  %390 = fmul float %386, %386
>  %391 = fadd float %389, %390
>  %392 = call float @fabs(float %391)
>  %393 = call float @llvm.AMDGPU.rsq(float %392)
>  %394 = fmul float %384, %393
>  %395 = fmul float %385, %393
>  %396 = fmul float %386, %393
>  %397 = fmul float %180, %372
>  %398 = fmul float %181, %373
>  %399 = fadd float %398, %397
>  %400 = fmul float %182, %374
>  %401 = fadd float %399, %400
>  %402 = fmul float %180, %394
>  %403 = fmul float %181, %395
>  %404 = fadd float %403, %402
>  %405 = fmul float %182, %396
>  %406 = fadd float %404, %405
>  %407 = fcmp uge float %401, 0.000000e+00
>  %408 = select i1 %407, float %401, float 0.000000e+00
>  %409 = fcmp uge float %406, 0.000000e+00
>  %410 = select i1 %409, float %406, float 0.000000e+00
>  %411 = call float @llvm.pow.f32(float %410, float %36)
>  %412 = call float @llvm.AMDGPU.cndlt(float %401, float 0.000000e+00, float %411)
>  %413 = fmul float 1.000000e+00, %383
>  %414 = fmul float %408, %383
>  %415 = fmul float %412, %383
>  %416 = fmul float %413, %89
>  %417 = fadd float %416, %357
>  %418 = fmul float %413, %90
>  %419 = fadd float %418, %359
>  %420 = fmul float %413, %91
>  %421 = fadd float %420, %361
>  %422 = fmul float %414, %92
>  %423 = fadd float %422, %417
>  %424 = fmul float %414, %93
>  %425 = fadd float %424, %419
>  %426 = fmul float %414, %94
>  %427 = fadd float %426, %421
>  %428 = fmul float %415, %95
>  %429 = fadd float %428, %423
>  %430 = fmul float %415, %96
>  %431 = fadd float %430, %425
>  %432 = fmul float %415, %97
>  %433 = fadd float %432, %427
>  %434 = fsub float %98, %237
>  %435 = fsub float %99, %238
>  %436 = fsub float %100, %239
>  %437 = fmul float %434, %434
>  %438 = fmul float %435, %435
>  %439 = fadd float %438, %437
>  %440 = fmul float %436, %436
>  %441 = fadd float %439, %440
>  %442 = call float @fabs(float %441)
>  %443 = call float @llvm.AMDGPU.rsq(float %442)
>  %444 = fmul float %434, %443
>  %445 = fmul float %435, %443
>  %446 = fmul float %436, %443
>  %447 = fmul float %180, %98
>  %448 = fmul float %181, %99
>  %449 = fadd float %448, %447
>  %450 = fmul float %182, %100
>  %451 = fadd float %449, %450
>  %452 = fmul float %180, %444
>  %453 = fmul float %181, %445
>  %454 = fadd float %453, %452
>  %455 = fmul float %182, %446
>  %456 = fadd float %454, %455
>  %457 = fcmp uge float %451, 0.000000e+00
>  %458 = select i1 %457, float %451, float 0.000000e+00
>  %459 = fcmp uge float %456, 0.000000e+00
>  %460 = select i1 %459, float %456, float 0.000000e+00
>  %461 = call float @llvm.pow.f32(float %460, float %36)
>  %462 = call float @llvm.AMDGPU.cndlt(float %451, float 0.000000e+00, float %461)
>  %463 = fadd float %101, %429
>  %464 = fadd float %102, %431
>  %465 = fadd float %103, %433
>  %466 = fmul float %458, %104
>  %467 = fadd float %466, %463
>  %468 = fmul float %458, %105
>  %469 = fadd float %468, %464
>  %470 = fmul float %458, %106
>  %471 = fadd float %470, %465
>  %472 = fmul float %462, %107
>  %473 = fadd float %472, %467
>  %474 = fmul float %462, %108
>  %475 = fadd float %474, %469
>  %476 = fmul float %462, %109
>  %477 = fadd float %476, %471
>  %478 = call float @llvm.AMDIL.clamp.(float %473, float 0.000000e+00, float 1.000000e+00)
>  %479 = call float @llvm.AMDIL.clamp.(float %475, float 0.000000e+00, float 1.000000e+00)
>  %480 = call float @llvm.AMDIL.clamp.(float %477, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %478, float %479, float %480, float %186)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %126, float %127, float %128, float %129)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %151, float %153, float %155, float %157)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>d2820010
>045e2005
>7e205510
>c2028152
>bf8c007f
>d2820018
>044c0b10
>102e2d14
>10262f0b
>10322d12
>d2820012
>044e330c
>102a2d15
>d2820013
>044a2b0e
>d00c0008
>02010113
>d2000012
>00222680
>10242112
>c2028156
>bf8c007f
>d2820014
>04600b12
>082c0b19
>082e0d17
>10302f17
>d2820018
>04622d16
>082a0f15
>d2820018
>04622b15
>d2060118
>02010118
>7e305b18
>102c3116
>102e3117
>102e2f0b
>d2820016
>045e2d0c
>102a3115
>d2820015
>045a2b0e
>d00c0008
>02010115
>d2000015
>00222a80
>7e2a4f15
>0e2a2a04
>7e2a4b15
>d0080008
>02022680
>d2000013
>00210115
>10262113
>c202815a
>bf8c007f
>d2820015
>04500b13
>c202815d
>bf8c007f
>08281a05
>c202815c
>bf8c007f
>081e1e05
>101a1f0f
>d282000d
>04362914
>c202815e
>bf8c007f
>08222205
>d282000d
>04362311
>d206010d
>0201010d
>7e2c5b0d
>7e1a5516
>102e1b16
>c2028160
>bf8c007f
>102e2e05
>c2028161
>bf8c007f
>d2820017
>045e1a05
>101a1b0d
>c2028162
>bf8c007f
>d282000d
>045e1a05
>7e1a550d
>c2028166
>bf8c007f
>d2820017
>04540b0d
>102a2d0f
>101e2b0b
>10302d14
>d282000f
>043e310c
>102c2d11
>d2820011
>043e2d0e
>d00c0008
>02010111
>d200000f
>00222280
>101e1b0f
>c202816a
>bf8c007f
>d2820014
>045c0b0f
>082e0b18
>082a0d15
>10302b15
>d2820018
>04622f17
>082c0f16
>d2820018
>04622d16
>d2060118
>02010118
>7e305b18
>102e3117
>102a3115
>102a2b0b
>d2820015
>04562f0c
>102c3116
>d2820015
>04562d0e
>d00c0008
>02010115
>d2000015
>00222a80
>7e2a4f15
>0e2a2a04
>7e2a4b15
>d0080008
>02022280
>d2000011
>00210115
>10221b11
>c202816e
>bf8c007f
>d2820014
>04500b11
>c202817a
>bf8c007f
>062c2805
>c2028170
>bf8c007f
>10281605
>c2048171
>bf8c007f
>d2820014
>0450130c
>c2040172
>bf8c007f
>d2820015
>0450110e
>d00c000a
>02010115
>d2000014
>002a2a80
>c205017e
>bf8c007f
>d2820016
>04581514
>080a0a09
>080c0c05
>102e0d06
>d2820017
>045e0b05
>080e0e08
>d2820017
>045e0f07
>d2060117
>02010117
>7e2e5b17
>100a2f05
>100c2f06
>100c0d0b
>d2820005
>041a0b0c
>100c2f07
>d2820005
>04160d0e
>d00c0008
>02010105
>d2000005
>00220a80
>7e0a4f05
>0e0a0a04
>7e0a4b05
>d0080004
>02022a80
>d2000006
>00110105
>c2020182
>bf8c007f
>d2820005
>04580906
>d2060805
>02010105
>c202013d
>c2028121
>bf8c007f
>7e0e0205
>d2820007
>041c0909
>c2020141
>bf8c007f
>d2820007
>041c090a
>c2020145
>bf8c007f
>d2820007
>041c0908
>c2020151
>bf8c007f
>d2820007
>041c0910
>c2020155
>bf8c007f
>d2820007
>041c0912
>c2020159
>bf8c007f
>d2820007
>041c0913
>c2020165
>bf8c007f
>d2820007
>041c090d
>c2020169
>bf8c007f
>d2820007
>041c090f
>c202016d
>bf8c007f
>d2820007
>041c0911
>c2020179
>bf8c007f
>060e0e04
>c202017d
>bf8c007f
>d2820007
>041c0914
>c2020181
>bf8c007f
>d2820007
>041c0906
>d2060807
>02010107
>c202013c
>c2028120
>bf8c007f
>7e160205
>d2820009
>042c0909
>c2020140
>bf8c007f
>d2820009
>0424090a
>c2020144
>bf8c007f
>d2820008
>04240908
>c2020150
>bf8c007f
>d2820008
>04200910
>c2020154
>bf8c007f
>d2820008
>04200912
>c2020158
>bf8c007f
>d2820008
>04200913
>c2020164
>bf8c007f
>d2820008
>0420090d
>c2020168
>bf8c007f
>d2820008
>0420090f
>c202016c
>bf8c007f
>d2820008
>04200911
>c2020178
>bf8c007f
>06101004
>c202017c
>bf8c007f
>d2820008
>04200914
>c2020180
>bf8c007f
>d2820006
>04200906
>d2060806
>02010106
>c2020123
>bf8c007f
>d2060808
>02010004
>f800020f
>08050706
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..8]
>DCL TEMP[0..3]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MOV OUT[2], IN[2]
> 14: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %40 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0
>  %42 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %41, i32 0, i32 %5)
>  %43 = extractelement <4 x float> %42, i32 0
>  %44 = extractelement <4 x float> %42, i32 1
>  %45 = extractelement <4 x float> %42, i32 2
>  %46 = extractelement <4 x float> %42, i32 3
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %54 = load <16 x i8> addrspace(2)* %53, !tbaa !0
>  %55 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %54, i32 0, i32 %5)
>  %56 = extractelement <4 x float> %55, i32 0
>  %57 = extractelement <4 x float> %55, i32 1
>  %58 = extractelement <4 x float> %55, i32 2
>  %59 = extractelement <4 x float> %55, i32 3
>  %60 = fmul float %43, %11
>  %61 = fmul float %43, %12
>  %62 = fmul float %43, %13
>  %63 = fmul float %43, %14
>  %64 = fmul float %44, %15
>  %65 = fadd float %64, %60
>  %66 = fmul float %44, %16
>  %67 = fadd float %66, %61
>  %68 = fmul float %44, %17
>  %69 = fadd float %68, %62
>  %70 = fmul float %44, %18
>  %71 = fadd float %70, %63
>  %72 = fmul float %45, %19
>  %73 = fadd float %72, %65
>  %74 = fmul float %45, %20
>  %75 = fadd float %74, %67
>  %76 = fmul float %45, %21
>  %77 = fadd float %76, %69
>  %78 = fmul float %45, %22
>  %79 = fadd float %78, %71
>  %80 = fmul float %46, %23
>  %81 = fadd float %80, %73
>  %82 = fmul float %46, %24
>  %83 = fadd float %82, %75
>  %84 = fmul float %46, %25
>  %85 = fadd float %84, %77
>  %86 = fmul float %46, %26
>  %87 = fadd float %86, %79
>  %88 = fmul float %50, %27
>  %89 = fmul float %51, %28
>  %90 = fadd float %89, %88
>  %91 = fmul float %52, %29
>  %92 = fadd float %90, %91
>  %93 = fmul float %50, %30
>  %94 = fmul float %51, %31
>  %95 = fadd float %94, %93
>  %96 = fmul float %52, %32
>  %97 = fadd float %95, %96
>  %98 = fmul float %50, %33
>  %99 = fmul float %51, %34
>  %100 = fadd float %99, %98
>  %101 = fmul float %52, %35
>  %102 = fadd float %100, %101
>  %103 = fmul float %92, %92
>  %104 = fmul float %97, %97
>  %105 = fadd float %104, %103
>  %106 = fmul float %102, %102
>  %107 = fadd float %105, %106
>  %108 = call float @fabs(float %107)
>  %109 = call float @llvm.AMDGPU.rsq(float %108)
>  %110 = call float @llvm.AMDIL.clamp.(float %36, float 0.000000e+00, float 1.000000e+00)
>  %111 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %112 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %113 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %110, float %111, float %112, float %113)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %56, float %57, float %58, float %59)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %81, float %83, float %85, float %87)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800100
>bf8c007f
>c2020123
>bf8c007f
>d2060801
>02010004
>c2020122
>bf8c007f
>d2060802
>02010004
>c2020121
>bf8c007f
>d2060803
>02010004
>c2020120
>bf8c007f
>d2060804
>02010004
>f800020f
>01020304
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: MOV OUT[4], IN[3]
> 10: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %53 = load <16 x i8> addrspace(2)* %52, !tbaa !0
>  %54 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %53, i32 0, i32 %5)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %58 = extractelement <4 x float> %54, i32 3
>  %59 = fmul float %34, %11
>  %60 = fmul float %34, %12
>  %61 = fmul float %34, %13
>  %62 = fmul float %34, %14
>  %63 = fmul float %35, %15
>  %64 = fadd float %63, %59
>  %65 = fmul float %35, %16
>  %66 = fadd float %65, %60
>  %67 = fmul float %35, %17
>  %68 = fadd float %67, %61
>  %69 = fmul float %35, %18
>  %70 = fadd float %69, %62
>  %71 = fmul float %36, %19
>  %72 = fadd float %71, %64
>  %73 = fmul float %36, %20
>  %74 = fadd float %73, %66
>  %75 = fmul float %36, %21
>  %76 = fadd float %75, %68
>  %77 = fmul float %36, %22
>  %78 = fadd float %77, %70
>  %79 = fmul float %37, %23
>  %80 = fadd float %79, %72
>  %81 = fmul float %37, %24
>  %82 = fadd float %81, %74
>  %83 = fmul float %37, %25
>  %84 = fadd float %83, %76
>  %85 = fmul float %37, %26
>  %86 = fadd float %85, %78
>  %87 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %88 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %89 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %90 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %91 = fmul float %34, %27
>  %92 = fmul float %35, %28
>  %93 = fadd float %91, %92
>  %94 = fmul float %36, %29
>  %95 = fadd float %93, %94
>  %96 = fmul float %37, %30
>  %97 = fadd float %95, %96
>  %98 = call float @fabs(float %97)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %87, float %88, float %89, float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %98, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %55, float %56, float %57, float %58)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %80, float %82, float %84, float %86)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0840708
>bf8c000f
>e00c2000
>80020500
>bf8c0770
>f800022f
>08070605
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..32]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD TEMP[3], TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: SUB TEMP[5], CONST[28], TEMP[6]
> 78: DP3 TEMP[7].x, TEMP[5], TEMP[5]
> 79: RSQ TEMP[7].x, |TEMP[7]|
> 80: MUL TEMP[5], TEMP[5], TEMP[7].xxxx
> 81: DP3 TEMP[2].x, TEMP[0], CONST[28]
> 82: DP3 TEMP[2].y, TEMP[0], TEMP[5]
> 83: LIT TEMP[1], TEMP[2]
> 84: ADD TEMP[3], CONST[30], TEMP[3]
> 85: MAD TEMP[3], TEMP[1].yyyy, CONST[31], TEMP[3]
> 86: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[32], TEMP[3]
> 87: ABS OUT[2].x, TEMP[4].zzzz
> 88: MOV OUT[2].yzw, IMM[0].xxxy
> 89: MOV OUT[3], IN[2]
> 90: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %110 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %111 = load <16 x i8> addrspace(2)* %110, !tbaa !0
>  %112 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %111, i32 0, i32 %5)
>  %113 = extractelement <4 x float> %112, i32 0
>  %114 = extractelement <4 x float> %112, i32 1
>  %115 = extractelement <4 x float> %112, i32 2
>  %116 = extractelement <4 x float> %112, i32 3
>  %117 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %118 = load <16 x i8> addrspace(2)* %117, !tbaa !0
>  %119 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %118, i32 0, i32 %5)
>  %120 = extractelement <4 x float> %119, i32 0
>  %121 = extractelement <4 x float> %119, i32 1
>  %122 = extractelement <4 x float> %119, i32 2
>  %123 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %124 = load <16 x i8> addrspace(2)* %123, !tbaa !0
>  %125 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %124, i32 0, i32 %5)
>  %126 = extractelement <4 x float> %125, i32 0
>  %127 = extractelement <4 x float> %125, i32 1
>  %128 = extractelement <4 x float> %125, i32 2
>  %129 = extractelement <4 x float> %125, i32 3
>  %130 = fmul float %113, %11
>  %131 = fmul float %113, %12
>  %132 = fmul float %113, %13
>  %133 = fmul float %113, %14
>  %134 = fmul float %114, %15
>  %135 = fadd float %134, %130
>  %136 = fmul float %114, %16
>  %137 = fadd float %136, %131
>  %138 = fmul float %114, %17
>  %139 = fadd float %138, %132
>  %140 = fmul float %114, %18
>  %141 = fadd float %140, %133
>  %142 = fmul float %115, %19
>  %143 = fadd float %142, %135
>  %144 = fmul float %115, %20
>  %145 = fadd float %144, %137
>  %146 = fmul float %115, %21
>  %147 = fadd float %146, %139
>  %148 = fmul float %115, %22
>  %149 = fadd float %148, %141
>  %150 = fmul float %116, %23
>  %151 = fadd float %150, %143
>  %152 = fmul float %116, %24
>  %153 = fadd float %152, %145
>  %154 = fmul float %116, %25
>  %155 = fadd float %154, %147
>  %156 = fmul float %116, %26
>  %157 = fadd float %156, %149
>  %158 = fmul float %120, %27
>  %159 = fmul float %121, %28
>  %160 = fadd float %159, %158
>  %161 = fmul float %122, %29
>  %162 = fadd float %160, %161
>  %163 = fmul float %120, %30
>  %164 = fmul float %121, %31
>  %165 = fadd float %164, %163
>  %166 = fmul float %122, %32
>  %167 = fadd float %165, %166
>  %168 = fmul float %120, %33
>  %169 = fmul float %121, %34
>  %170 = fadd float %169, %168
>  %171 = fmul float %122, %35
>  %172 = fadd float %170, %171
>  %173 = fmul float %162, %162
>  %174 = fmul float %167, %167
>  %175 = fadd float %174, %173
>  %176 = fmul float %172, %172
>  %177 = fadd float %175, %176
>  %178 = call float @fabs(float %177)
>  %179 = call float @llvm.AMDGPU.rsq(float %178)
>  %180 = fmul float %162, %179
>  %181 = fmul float %167, %179
>  %182 = fmul float %172, %179
>  %183 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %184 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %185 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %186 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %187 = fmul float %113, %44
>  %188 = fmul float %113, %45
>  %189 = fmul float %113, %46
>  %190 = fmul float %114, %47
>  %191 = fadd float %190, %187
>  %192 = fmul float %114, %48
>  %193 = fadd float %192, %188
>  %194 = fmul float %114, %49
>  %195 = fadd float %194, %189
>  %196 = fmul float %115, %50
>  %197 = fadd float %196, %191
>  %198 = fmul float %115, %51
>  %199 = fadd float %198, %193
>  %200 = fmul float %115, %52
>  %201 = fadd float %200, %195
>  %202 = fmul float %116, %53
>  %203 = fadd float %202, %197
>  %204 = fmul float %116, %54
>  %205 = fadd float %204, %199
>  %206 = fmul float %116, %55
>  %207 = fadd float %206, %201
>  %208 = fsub float %41, %203
>  %209 = fsub float %42, %205
>  %210 = fsub float %43, %207
>  %211 = fmul float %208, %208
>  %212 = fmul float %209, %209
>  %213 = fadd float %212, %211
>  %214 = fmul float %210, %210
>  %215 = fadd float %213, %214
>  %216 = call float @fabs(float %215)
>  %217 = call float @llvm.AMDGPU.rsq(float %216)
>  %218 = fmul float %208, %217
>  %219 = fmul float %209, %217
>  %220 = fmul float %210, %217
>  %221 = fdiv float 1.000000e+00, %217
>  %222 = fmul float %217, %221
>  %223 = fmul float %221, %221
>  %224 = fmul float %56, %222
>  %225 = fmul float %57, %221
>  %226 = fadd float %225, %224
>  %227 = fmul float %58, %223
>  %228 = fadd float %226, %227
>  %229 = fdiv float 1.000000e+00, %228
>  %230 = fmul float %203, %203
>  %231 = fmul float %205, %205
>  %232 = fadd float %231, %230
>  %233 = fmul float %207, %207
>  %234 = fadd float %232, %233
>  %235 = call float @fabs(float %234)
>  %236 = call float @llvm.AMDGPU.rsq(float %235)
>  %237 = fmul float %203, %236
>  %238 = fmul float %205, %236
>  %239 = fmul float %207, %236
>  %240 = fsub float %218, %237
>  %241 = fsub float %219, %238
>  %242 = fsub float %220, %239
>  %243 = fmul float %240, %240
>  %244 = fmul float %241, %241
>  %245 = fadd float %244, %243
>  %246 = fmul float %242, %242
>  %247 = fadd float %245, %246
>  %248 = call float @fabs(float %247)
>  %249 = call float @llvm.AMDGPU.rsq(float %248)
>  %250 = fmul float %240, %249
>  %251 = fmul float %241, %249
>  %252 = fmul float %242, %249
>  %253 = fmul float %180, %218
>  %254 = fmul float %181, %219
>  %255 = fadd float %254, %253
>  %256 = fmul float %182, %220
>  %257 = fadd float %255, %256
>  %258 = fmul float %180, %250
>  %259 = fmul float %181, %251
>  %260 = fadd float %259, %258
>  %261 = fmul float %182, %252
>  %262 = fadd float %260, %261
>  %263 = fcmp uge float %257, 0.000000e+00
>  %264 = select i1 %263, float %257, float 0.000000e+00
>  %265 = fcmp uge float %262, 0.000000e+00
>  %266 = select i1 %265, float %262, float 0.000000e+00
>  %267 = call float @llvm.pow.f32(float %266, float %36)
>  %268 = call float @llvm.AMDGPU.cndlt(float %257, float 0.000000e+00, float %267)
>  %269 = fmul float 1.000000e+00, %229
>  %270 = fmul float %264, %229
>  %271 = fmul float %268, %229
>  %272 = fmul float %269, %59
>  %273 = fadd float %272, %37
>  %274 = fmul float %269, %60
>  %275 = fadd float %274, %38
>  %276 = fmul float %269, %61
>  %277 = fadd float %276, %39
>  %278 = fmul float %270, %62
>  %279 = fadd float %278, %273
>  %280 = fmul float %270, %63
>  %281 = fadd float %280, %275
>  %282 = fmul float %270, %64
>  %283 = fadd float %282, %277
>  %284 = fmul float %271, %65
>  %285 = fadd float %284, %279
>  %286 = fmul float %271, %66
>  %287 = fadd float %286, %281
>  %288 = fmul float %271, %67
>  %289 = fadd float %288, %283
>  %290 = fsub float %68, %203
>  %291 = fsub float %69, %205
>  %292 = fsub float %70, %207
>  %293 = fmul float %290, %290
>  %294 = fmul float %291, %291
>  %295 = fadd float %294, %293
>  %296 = fmul float %292, %292
>  %297 = fadd float %295, %296
>  %298 = call float @fabs(float %297)
>  %299 = call float @llvm.AMDGPU.rsq(float %298)
>  %300 = fmul float %290, %299
>  %301 = fmul float %291, %299
>  %302 = fmul float %292, %299
>  %303 = fdiv float 1.000000e+00, %299
>  %304 = fmul float %299, %303
>  %305 = fmul float %303, %303
>  %306 = fmul float %71, %304
>  %307 = fmul float %72, %303
>  %308 = fadd float %307, %306
>  %309 = fmul float %73, %305
>  %310 = fadd float %308, %309
>  %311 = fdiv float 1.000000e+00, %310
>  %312 = fsub float %300, %237
>  %313 = fsub float %301, %238
>  %314 = fsub float %302, %239
>  %315 = fmul float %312, %312
>  %316 = fmul float %313, %313
>  %317 = fadd float %316, %315
>  %318 = fmul float %314, %314
>  %319 = fadd float %317, %318
>  %320 = call float @fabs(float %319)
>  %321 = call float @llvm.AMDGPU.rsq(float %320)
>  %322 = fmul float %312, %321
>  %323 = fmul float %313, %321
>  %324 = fmul float %314, %321
>  %325 = fmul float %180, %300
>  %326 = fmul float %181, %301
>  %327 = fadd float %326, %325
>  %328 = fmul float %182, %302
>  %329 = fadd float %327, %328
>  %330 = fmul float %180, %322
>  %331 = fmul float %181, %323
>  %332 = fadd float %331, %330
>  %333 = fmul float %182, %324
>  %334 = fadd float %332, %333
>  %335 = fcmp uge float %329, 0.000000e+00
>  %336 = select i1 %335, float %329, float 0.000000e+00
>  %337 = fcmp uge float %334, 0.000000e+00
>  %338 = select i1 %337, float %334, float 0.000000e+00
>  %339 = call float @llvm.pow.f32(float %338, float %36)
>  %340 = call float @llvm.AMDGPU.cndlt(float %329, float 0.000000e+00, float %339)
>  %341 = fmul float 1.000000e+00, %311
>  %342 = fmul float %336, %311
>  %343 = fmul float %340, %311
>  %344 = fmul float %341, %74
>  %345 = fadd float %344, %285
>  %346 = fmul float %341, %75
>  %347 = fadd float %346, %287
>  %348 = fmul float %341, %76
>  %349 = fadd float %348, %289
>  %350 = fmul float %342, %77
>  %351 = fadd float %350, %345
>  %352 = fmul float %342, %78
>  %353 = fadd float %352, %347
>  %354 = fmul float %342, %79
>  %355 = fadd float %354, %349
>  %356 = fmul float %343, %80
>  %357 = fadd float %356, %351
>  %358 = fmul float %343, %81
>  %359 = fadd float %358, %353
>  %360 = fmul float %343, %82
>  %361 = fadd float %360, %355
>  %362 = fsub float %83, %203
>  %363 = fsub float %84, %205
>  %364 = fsub float %85, %207
>  %365 = fmul float %362, %362
>  %366 = fmul float %363, %363
>  %367 = fadd float %366, %365
>  %368 = fmul float %364, %364
>  %369 = fadd float %367, %368
>  %370 = call float @fabs(float %369)
>  %371 = call float @llvm.AMDGPU.rsq(float %370)
>  %372 = fmul float %362, %371
>  %373 = fmul float %363, %371
>  %374 = fmul float %364, %371
>  %375 = fdiv float 1.000000e+00, %371
>  %376 = fmul float %371, %375
>  %377 = fmul float %375, %375
>  %378 = fmul float %86, %376
>  %379 = fmul float %87, %375
>  %380 = fadd float %379, %378
>  %381 = fmul float %88, %377
>  %382 = fadd float %380, %381
>  %383 = fdiv float 1.000000e+00, %382
>  %384 = fsub float %372, %237
>  %385 = fsub float %373, %238
>  %386 = fsub float %374, %239
>  %387 = fmul float %384, %384
>  %388 = fmul float %385, %385
>  %389 = fadd float %388, %387
>  %390 = fmul float %386, %386
>  %391 = fadd float %389, %390
>  %392 = call float @fabs(float %391)
>  %393 = call float @llvm.AMDGPU.rsq(float %392)
>  %394 = fmul float %384, %393
>  %395 = fmul float %385, %393
>  %396 = fmul float %386, %393
>  %397 = fmul float %180, %372
>  %398 = fmul float %181, %373
>  %399 = fadd float %398, %397
>  %400 = fmul float %182, %374
>  %401 = fadd float %399, %400
>  %402 = fmul float %180, %394
>  %403 = fmul float %181, %395
>  %404 = fadd float %403, %402
>  %405 = fmul float %182, %396
>  %406 = fadd float %404, %405
>  %407 = fcmp uge float %401, 0.000000e+00
>  %408 = select i1 %407, float %401, float 0.000000e+00
>  %409 = fcmp uge float %406, 0.000000e+00
>  %410 = select i1 %409, float %406, float 0.000000e+00
>  %411 = call float @llvm.pow.f32(float %410, float %36)
>  %412 = call float @llvm.AMDGPU.cndlt(float %401, float 0.000000e+00, float %411)
>  %413 = fmul float 1.000000e+00, %383
>  %414 = fmul float %408, %383
>  %415 = fmul float %412, %383
>  %416 = fmul float %413, %89
>  %417 = fadd float %416, %357
>  %418 = fmul float %413, %90
>  %419 = fadd float %418, %359
>  %420 = fmul float %413, %91
>  %421 = fadd float %420, %361
>  %422 = fmul float %414, %92
>  %423 = fadd float %422, %417
>  %424 = fmul float %414, %93
>  %425 = fadd float %424, %419
>  %426 = fmul float %414, %94
>  %427 = fadd float %426, %421
>  %428 = fmul float %415, %95
>  %429 = fadd float %428, %423
>  %430 = fmul float %415, %96
>  %431 = fadd float %430, %425
>  %432 = fmul float %415, %97
>  %433 = fadd float %432, %427
>  %434 = fsub float %98, %237
>  %435 = fsub float %99, %238
>  %436 = fsub float %100, %239
>  %437 = fmul float %434, %434
>  %438 = fmul float %435, %435
>  %439 = fadd float %438, %437
>  %440 = fmul float %436, %436
>  %441 = fadd float %439, %440
>  %442 = call float @fabs(float %441)
>  %443 = call float @llvm.AMDGPU.rsq(float %442)
>  %444 = fmul float %434, %443
>  %445 = fmul float %435, %443
>  %446 = fmul float %436, %443
>  %447 = fmul float %180, %98
>  %448 = fmul float %181, %99
>  %449 = fadd float %448, %447
>  %450 = fmul float %182, %100
>  %451 = fadd float %449, %450
>  %452 = fmul float %180, %444
>  %453 = fmul float %181, %445
>  %454 = fadd float %453, %452
>  %455 = fmul float %182, %446
>  %456 = fadd float %454, %455
>  %457 = fcmp uge float %451, 0.000000e+00
>  %458 = select i1 %457, float %451, float 0.000000e+00
>  %459 = fcmp uge float %456, 0.000000e+00
>  %460 = select i1 %459, float %456, float 0.000000e+00
>  %461 = call float @llvm.pow.f32(float %460, float %36)
>  %462 = call float @llvm.AMDGPU.cndlt(float %451, float 0.000000e+00, float %461)
>  %463 = fadd float %101, %429
>  %464 = fadd float %102, %431
>  %465 = fadd float %103, %433
>  %466 = fmul float %458, %104
>  %467 = fadd float %466, %463
>  %468 = fmul float %458, %105
>  %469 = fadd float %468, %464
>  %470 = fmul float %458, %106
>  %471 = fadd float %470, %465
>  %472 = fmul float %462, %107
>  %473 = fadd float %472, %467
>  %474 = fmul float %462, %108
>  %475 = fadd float %474, %469
>  %476 = fmul float %462, %109
>  %477 = fadd float %476, %471
>  %478 = call float @llvm.AMDIL.clamp.(float %473, float 0.000000e+00, float 1.000000e+00)
>  %479 = call float @llvm.AMDIL.clamp.(float %475, float 0.000000e+00, float 1.000000e+00)
>  %480 = call float @llvm.AMDIL.clamp.(float %477, float 0.000000e+00, float 1.000000e+00)
>  %481 = call float @fabs(float %207)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %478, float %479, float %480, float %186)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %481, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %126, float %127, float %128, float %129)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %151, float %153, float %155, float %157)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020129
>bf8c007f
>100a0204
>c202012d
>bf8c007f
>d2820005
>04140902
>c2020131
>bf8c007f
>d2820005
>04140903
>c2020135
>bf8c007f
>d282000e
>04140904
>c2020128
>bf8c007f
>100a0204
>c202012c
>bf8c007f
>d2820005
>04140902
>c2020130
>bf8c007f
>d2820005
>04140903
>c2020134
>bf8c007f
>d2820010
>04140904
>100a2110
>d2820006
>04161d0e
>c202012a
>bf8c007f
>100a0204
>c202012e
>bf8c007f
>d2820005
>04140902
>c2020132
>bf8c007f
>d2820005
>04140903
>c2020136
>bf8c007f
>d2820005
>04140904
>d2820006
>041a0b05
>d2060106
>02010106
>7e105b06
>100c110e
>c2020125
>bf8c007f
>080e1c04
>c2020124
>bf8c007f
>08162004
>1012170b
>d2820009
>04260f07
>c2020126
>bf8c007f
>08180a04
>d2820009
>0426190c
>d2060109
>02010109
>7e125b09
>10141307
>081a0d0a
>100e1110
>1016130b
>08280f0b
>101e2914
>d2820012
>043e1b0d
>10101105
>1022130c
>081e1111
>d282000c
>044a1f0f
>d206010c
>0201010c
>7e245b0c
>1026250d
>101a2514
>c0840704
>bf8c007f
>e00c2000
>80021400
>c2020114
>bf8c0070
>10182804
>c2020115
>bf8c007f
>d282000c
>04300915
>c2020116
>bf8c007f
>d2820018
>04300916
>c2020110
>bf8c007f
>10182804
>c2020111
>bf8c007f
>d282000c
>04300915
>c2020112
>bf8c007f
>d282000c
>04300916
>1032190c
>d2820019
>04663118
>c2020118
>bf8c007f
>10342804
>c2020119
>bf8c007f
>d282001a
>04680915
>c202011a
>bf8c007f
>d2820014
>04680916
>d2820015
>04662914
>d2060115
>02010115
>7e2a5b15
>10182b0c
>102c1b0c
>101a2b18
>d2820013
>045a270d
>1024250f
>101e2b14
>d2820012
>044e250f
>d00c0004
>02010112
>d2000012
>00122480
>7e244f12
>c202011c
>bf8c007f
>0e242404
>7e244b12
>1016170c
>d282000a
>042e150d
>d282000b
>042a230f
>d0080008
>02021680
>d2000011
>00210112
>7e145509
>10121509
>c2028138
>bf8c007f
>10121205
>c2028139
>bf8c007f
>d2820009
>04261405
>1014150a
>c202813a
>bf8c007f
>d2820009
>04261405
>7e145509
>10121511
>d00c0008
>0201010b
>d200000b
>00221680
>1016150b
>c202813e
>c2040122
>bf8c007f
>7e220208
>d2820011
>04440b0a
>c2028142
>bf8c007f
>d2820011
>04440b0b
>c2028146
>bf8c007f
>d2820013
>04440b09
>c2028149
>bf8c007f
>08241c05
>c2028148
>bf8c007f
>08282005
>10222914
>d2820011
>04462512
>c202814a
>bf8c007f
>082a0a05
>d2820011
>04462b15
>d2060111
>02010111
>7e2c5b11
>7e225516
>102e2316
>c202814c
>bf8c007f
>102e2e05
>c202814d
>bf8c007f
>d2820017
>045e2205
>10222311
>c202814e
>bf8c007f
>d2820011
>045e2205
>7e225511
>c2028152
>bf8c007f
>d2820018
>044c0b11
>102e2d14
>10262f0c
>10322d12
>d2820012
>044e330d
>102a2d15
>d2820013
>044a2b0f
>d00c0008
>02010113
>d2000012
>00222680
>10242312
>c2028156
>bf8c007f
>d2820014
>04600b12
>082c0d19
>082e0f17
>10302f17
>d2820018
>04622d16
>082a1115
>d2820018
>04622b15
>d2060118
>02010118
>7e305b18
>102c3116
>102e3117
>102e2f0c
>d2820016
>045e2d0d
>102a3115
>d2820015
>045a2b0f
>d00c0008
>02010115
>d2000015
>00222a80
>7e2a4f15
>0e2a2a04
>7e2a4b15
>d0080008
>02022680
>d2000013
>00210115
>10262313
>c202815a
>bf8c007f
>d2820015
>04500b13
>c202815d
>bf8c007f
>08281c05
>c202815c
>bf8c007f
>08202005
>101c2110
>d282000e
>043a2914
>c202815e
>bf8c007f
>082c0a05
>d282000e
>043a2d16
>d206010e
>0201010e
>7e2e5b0e
>7e1c5517
>10301d17
>c2028160
>bf8c007f
>10303005
>c2028161
>bf8c007f
>d2820018
>04621c05
>101c1d0e
>c2028162
>bf8c007f
>d282000e
>04621c05
>7e1c550e
>c2028166
>bf8c007f
>d2820015
>04540b0e
>10302f10
>1020310c
>10322f14
>d2820010
>0442330d
>102c2f16
>d2820014
>04422d0f
>d00c0008
>02010114
>d2000010
>00222880
>10201d10
>c202816a
>bf8c007f
>d2820015
>04540b10
>082e0d19
>08300f18
>10323118
>d2820019
>04662f17
>082c1116
>d2820019
>04662d16
>d2060119
>02010119
>7e325b19
>102e3317
>10303318
>1030310c
>d2820017
>04622f0d
>102c3316
>d2820016
>045e2d0f
>d00c0008
>02010116
>d2000016
>00222c80
>7e2c4f16
>0e2c2c04
>7e2c4b16
>d0080008
>02022880
>d2000014
>00210116
>10281d14
>c202816e
>bf8c007f
>d2820015
>04540b14
>c202817a
>bf8c007f
>062e2a05
>c2028170
>bf8c007f
>102a1805
>c2048171
>bf8c007f
>d2820015
>0454130d
>c2040172
>bf8c007f
>d2820016
>0454110f
>d00c000a
>02010116
>d2000015
>002a2c80
>c205017e
>bf8c007f
>d2820017
>045c1515
>080c0c09
>080e0e05
>10300f07
>d2820018
>04620d06
>08101008
>d2820018
>04621108
>d2060118
>02010118
>7e305b18
>100c3106
>100e3107
>100e0f0c
>d2820006
>041e0d0d
>100e3108
>d2820006
>041a0f0f
>d00c0008
>02010106
>d2000006
>00220c80
>7e0c4f06
>0e0c0c04
>7e0c4b06
>d0080004
>02022c80
>d2000007
>00110106
>c2020182
>bf8c007f
>d2820006
>045c0907
>d2060806
>02010106
>c202013d
>c2028121
>bf8c007f
>7e100205
>d2820008
>0420090a
>c2020141
>bf8c007f
>d2820008
>0420090b
>c2020145
>bf8c007f
>d2820008
>04200909
>c2020151
>bf8c007f
>d2820008
>04200911
>c2020155
>bf8c007f
>d2820008
>04200912
>c2020159
>bf8c007f
>d2820008
>04200913
>c2020165
>bf8c007f
>d2820008
>0420090e
>c2020169
>bf8c007f
>d2820008
>04200910
>c202016d
>bf8c007f
>d2820008
>04200914
>c2020179
>bf8c007f
>06101004
>c202017d
>bf8c007f
>d2820008
>04200915
>c2020181
>bf8c007f
>d2820008
>04200907
>d2060808
>02010108
>c202013c
>c2028120
>bf8c007f
>7e180205
>d282000a
>0430090a
>c2020140
>bf8c007f
>d282000a
>0428090b
>c2020144
>bf8c007f
>d2820009
>04280909
>c2020150
>bf8c007f
>d2820009
>04240911
>c2020154
>bf8c007f
>d2820009
>04240912
>c2020158
>bf8c007f
>d2820009
>04240913
>c2020164
>bf8c007f
>d2820009
>0424090e
>c2020168
>bf8c007f
>d2820009
>04240910
>c202016c
>bf8c007f
>d2820009
>04240914
>c2020178
>bf8c007f
>06121204
>c202017c
>bf8c007f
>d2820009
>04240915
>c2020180
>bf8c007f
>d2820007
>04240907
>d2060807
>02010107
>c2020123
>bf8c007f
>d2060809
>02010004
>f800020f
>09060807
>d2060105
>02010105
>bf8c070f
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL OUT[5], GENERIC[2]
>DCL CONST[0..19]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: ABS OUT[2].x, TEMP[4].zzzz
> 41: MOV OUT[2].yzw, IMM[0].xxxy
> 42: MOV OUT[3], IN[3]
> 43: DP3 TEMP[1], TEMP[0], TEMP[6]
> 44: ADD TEMP[1], TEMP[1], TEMP[1]
> 45: MAD OUT[4].xyz, -TEMP[1], TEMP[0], TEMP[6]
> 46: MOV OUT[4].w, IN[4]
> 47: MOV OUT[5], IN[5]
> 48: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = extractelement <4 x float> %73, i32 3
>  %78 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %79 = load <16 x i8> addrspace(2)* %78, !tbaa !0
>  %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %79, i32 0, i32 %5)
>  %81 = extractelement <4 x float> %80, i32 0
>  %82 = extractelement <4 x float> %80, i32 1
>  %83 = extractelement <4 x float> %80, i32 2
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = extractelement <4 x float> %92, i32 3
>  %97 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %98 = load <16 x i8> addrspace(2)* %97, !tbaa !0
>  %99 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %98, i32 0, i32 %5)
>  %100 = extractelement <4 x float> %99, i32 3
>  %101 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %102 = load <16 x i8> addrspace(2)* %101, !tbaa !0
>  %103 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %102, i32 0, i32 %5)
>  %104 = extractelement <4 x float> %103, i32 0
>  %105 = extractelement <4 x float> %103, i32 1
>  %106 = extractelement <4 x float> %103, i32 2
>  %107 = extractelement <4 x float> %103, i32 3
>  %108 = fmul float %74, %11
>  %109 = fmul float %74, %12
>  %110 = fmul float %74, %13
>  %111 = fmul float %74, %14
>  %112 = fmul float %75, %15
>  %113 = fadd float %112, %108
>  %114 = fmul float %75, %16
>  %115 = fadd float %114, %109
>  %116 = fmul float %75, %17
>  %117 = fadd float %116, %110
>  %118 = fmul float %75, %18
>  %119 = fadd float %118, %111
>  %120 = fmul float %76, %19
>  %121 = fadd float %120, %113
>  %122 = fmul float %76, %20
>  %123 = fadd float %122, %115
>  %124 = fmul float %76, %21
>  %125 = fadd float %124, %117
>  %126 = fmul float %76, %22
>  %127 = fadd float %126, %119
>  %128 = fmul float %77, %23
>  %129 = fadd float %128, %121
>  %130 = fmul float %77, %24
>  %131 = fadd float %130, %123
>  %132 = fmul float %77, %25
>  %133 = fadd float %132, %125
>  %134 = fmul float %77, %26
>  %135 = fadd float %134, %127
>  %136 = fmul float %81, %27
>  %137 = fmul float %82, %28
>  %138 = fadd float %137, %136
>  %139 = fmul float %83, %29
>  %140 = fadd float %138, %139
>  %141 = fmul float %81, %30
>  %142 = fmul float %82, %31
>  %143 = fadd float %142, %141
>  %144 = fmul float %83, %32
>  %145 = fadd float %143, %144
>  %146 = fmul float %81, %33
>  %147 = fmul float %82, %34
>  %148 = fadd float %147, %146
>  %149 = fmul float %83, %35
>  %150 = fadd float %148, %149
>  %151 = fmul float %140, %140
>  %152 = fmul float %145, %145
>  %153 = fadd float %152, %151
>  %154 = fmul float %150, %150
>  %155 = fadd float %153, %154
>  %156 = call float @fabs(float %155)
>  %157 = call float @llvm.AMDGPU.rsq(float %156)
>  %158 = fmul float %140, %157
>  %159 = fmul float %145, %157
>  %160 = fmul float %150, %157
>  %161 = fmul float %37, %40
>  %162 = fadd float %161, %87
>  %163 = fmul float %38, %41
>  %164 = fadd float %163, %88
>  %165 = fmul float %39, %42
>  %166 = fadd float %165, %89
>  %167 = call float @llvm.AMDIL.clamp.(float %162, float 0.000000e+00, float 1.000000e+00)
>  %168 = call float @llvm.AMDIL.clamp.(float %164, float 0.000000e+00, float 1.000000e+00)
>  %169 = call float @llvm.AMDIL.clamp.(float %166, float 0.000000e+00, float 1.000000e+00)
>  %170 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %171 = fmul float %74, %47
>  %172 = fmul float %74, %48
>  %173 = fmul float %74, %49
>  %174 = fmul float %75, %50
>  %175 = fadd float %174, %171
>  %176 = fmul float %75, %51
>  %177 = fadd float %176, %172
>  %178 = fmul float %75, %52
>  %179 = fadd float %178, %173
>  %180 = fmul float %76, %53
>  %181 = fadd float %180, %175
>  %182 = fmul float %76, %54
>  %183 = fadd float %182, %177
>  %184 = fmul float %76, %55
>  %185 = fadd float %184, %179
>  %186 = fmul float %77, %56
>  %187 = fadd float %186, %181
>  %188 = fmul float %77, %57
>  %189 = fadd float %188, %183
>  %190 = fmul float %77, %58
>  %191 = fadd float %190, %185
>  %192 = fsub float %44, %187
>  %193 = fsub float %45, %189
>  %194 = fsub float %46, %191
>  %195 = fmul float %192, %192
>  %196 = fmul float %193, %193
>  %197 = fadd float %196, %195
>  %198 = fmul float %194, %194
>  %199 = fadd float %197, %198
>  %200 = call float @fabs(float %199)
>  %201 = call float @llvm.AMDGPU.rsq(float %200)
>  %202 = fmul float %192, %201
>  %203 = fmul float %193, %201
>  %204 = fmul float %194, %201
>  %205 = fdiv float 1.000000e+00, %201
>  %206 = fmul float %201, %205
>  %207 = fmul float %205, %205
>  %208 = fmul float %59, %206
>  %209 = fmul float %60, %205
>  %210 = fadd float %209, %208
>  %211 = fmul float %61, %207
>  %212 = fadd float %210, %211
>  %213 = fdiv float 1.000000e+00, %212
>  %214 = fmul float %187, %187
>  %215 = fmul float %189, %189
>  %216 = fadd float %215, %214
>  %217 = fmul float %191, %191
>  %218 = fadd float %216, %217
>  %219 = call float @fabs(float %218)
>  %220 = call float @llvm.AMDGPU.rsq(float %219)
>  %221 = fmul float %187, %220
>  %222 = fmul float %189, %220
>  %223 = fmul float %191, %220
>  %224 = fsub float %202, %221
>  %225 = fsub float %203, %222
>  %226 = fsub float %204, %223
>  %227 = fmul float %224, %224
>  %228 = fmul float %225, %225
>  %229 = fadd float %228, %227
>  %230 = fmul float %226, %226
>  %231 = fadd float %229, %230
>  %232 = call float @fabs(float %231)
>  %233 = call float @llvm.AMDGPU.rsq(float %232)
>  %234 = fmul float %224, %233
>  %235 = fmul float %225, %233
>  %236 = fmul float %226, %233
>  %237 = fmul float %158, %202
>  %238 = fmul float %159, %203
>  %239 = fadd float %238, %237
>  %240 = fmul float %160, %204
>  %241 = fadd float %239, %240
>  %242 = fmul float %158, %234
>  %243 = fmul float %159, %235
>  %244 = fadd float %243, %242
>  %245 = fmul float %160, %236
>  %246 = fadd float %244, %245
>  %247 = fcmp uge float %241, 0.000000e+00
>  %248 = select i1 %247, float %241, float 0.000000e+00
>  %249 = fcmp uge float %246, 0.000000e+00
>  %250 = select i1 %249, float %246, float 0.000000e+00
>  %251 = call float @llvm.pow.f32(float %250, float %36)
>  %252 = call float @llvm.AMDGPU.cndlt(float %241, float 0.000000e+00, float %251)
>  %253 = fmul float 1.000000e+00, %213
>  %254 = fmul float %248, %213
>  %255 = fmul float %252, %213
>  %256 = fmul float %253, %62
>  %257 = fadd float %256, %162
>  %258 = fmul float %253, %63
>  %259 = fadd float %258, %164
>  %260 = fmul float %253, %64
>  %261 = fadd float %260, %166
>  %262 = fmul float %254, %65
>  %263 = fadd float %262, %257
>  %264 = fmul float %254, %66
>  %265 = fadd float %264, %259
>  %266 = fmul float %254, %67
>  %267 = fadd float %266, %261
>  %268 = fmul float %255, %68
>  %269 = fadd float %268, %263
>  %270 = fmul float %255, %69
>  %271 = fadd float %270, %265
>  %272 = fmul float %255, %70
>  %273 = fadd float %272, %267
>  %274 = call float @llvm.AMDIL.clamp.(float %269, float 0.000000e+00, float 1.000000e+00)
>  %275 = call float @llvm.AMDIL.clamp.(float %271, float 0.000000e+00, float 1.000000e+00)
>  %276 = call float @llvm.AMDIL.clamp.(float %273, float 0.000000e+00, float 1.000000e+00)
>  %277 = call float @fabs(float %191)
>  %278 = fmul float %158, %221
>  %279 = fmul float %159, %222
>  %280 = fadd float %279, %278
>  %281 = fmul float %160, %223
>  %282 = fadd float %280, %281
>  %283 = fadd float %282, %282
>  %284 = fadd float %282, %282
>  %285 = fadd float %282, %282
>  %286 = fsub float -0.000000e+00, %283
>  %287 = fmul float %286, %158
>  %288 = fadd float %287, %221
>  %289 = fsub float -0.000000e+00, %284
>  %290 = fmul float %289, %159
>  %291 = fadd float %290, %222
>  %292 = fsub float -0.000000e+00, %285
>  %293 = fmul float %292, %160
>  %294 = fadd float %293, %223
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %274, float %275, float %276, float %170)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %277, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %93, float %94, float %95, float %96)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %288, float %291, float %294, float %100)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %104, float %105, float %106, float %107)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %129, float %131, float %133, float %135)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..19]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: ABS OUT[2].x, TEMP[4].zzzz
> 41: MOV OUT[2].yzw, IMM[0].xxxy
> 42: MOV OUT[3], IN[3]
> 43: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = extractelement <4 x float> %73, i32 3
>  %78 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %79 = load <16 x i8> addrspace(2)* %78, !tbaa !0
>  %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %79, i32 0, i32 %5)
>  %81 = extractelement <4 x float> %80, i32 0
>  %82 = extractelement <4 x float> %80, i32 1
>  %83 = extractelement <4 x float> %80, i32 2
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = extractelement <4 x float> %92, i32 3
>  %97 = fmul float %74, %11
>  %98 = fmul float %74, %12
>  %99 = fmul float %74, %13
>  %100 = fmul float %74, %14
>  %101 = fmul float %75, %15
>  %102 = fadd float %101, %97
>  %103 = fmul float %75, %16
>  %104 = fadd float %103, %98
>  %105 = fmul float %75, %17
>  %106 = fadd float %105, %99
>  %107 = fmul float %75, %18
>  %108 = fadd float %107, %100
>  %109 = fmul float %76, %19
>  %110 = fadd float %109, %102
>  %111 = fmul float %76, %20
>  %112 = fadd float %111, %104
>  %113 = fmul float %76, %21
>  %114 = fadd float %113, %106
>  %115 = fmul float %76, %22
>  %116 = fadd float %115, %108
>  %117 = fmul float %77, %23
>  %118 = fadd float %117, %110
>  %119 = fmul float %77, %24
>  %120 = fadd float %119, %112
>  %121 = fmul float %77, %25
>  %122 = fadd float %121, %114
>  %123 = fmul float %77, %26
>  %124 = fadd float %123, %116
>  %125 = fmul float %81, %27
>  %126 = fmul float %82, %28
>  %127 = fadd float %126, %125
>  %128 = fmul float %83, %29
>  %129 = fadd float %127, %128
>  %130 = fmul float %81, %30
>  %131 = fmul float %82, %31
>  %132 = fadd float %131, %130
>  %133 = fmul float %83, %32
>  %134 = fadd float %132, %133
>  %135 = fmul float %81, %33
>  %136 = fmul float %82, %34
>  %137 = fadd float %136, %135
>  %138 = fmul float %83, %35
>  %139 = fadd float %137, %138
>  %140 = fmul float %129, %129
>  %141 = fmul float %134, %134
>  %142 = fadd float %141, %140
>  %143 = fmul float %139, %139
>  %144 = fadd float %142, %143
>  %145 = call float @fabs(float %144)
>  %146 = call float @llvm.AMDGPU.rsq(float %145)
>  %147 = fmul float %129, %146
>  %148 = fmul float %134, %146
>  %149 = fmul float %139, %146
>  %150 = fmul float %37, %40
>  %151 = fadd float %150, %87
>  %152 = fmul float %38, %41
>  %153 = fadd float %152, %88
>  %154 = fmul float %39, %42
>  %155 = fadd float %154, %89
>  %156 = call float @llvm.AMDIL.clamp.(float %151, float 0.000000e+00, float 1.000000e+00)
>  %157 = call float @llvm.AMDIL.clamp.(float %153, float 0.000000e+00, float 1.000000e+00)
>  %158 = call float @llvm.AMDIL.clamp.(float %155, float 0.000000e+00, float 1.000000e+00)
>  %159 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %160 = fmul float %74, %47
>  %161 = fmul float %74, %48
>  %162 = fmul float %74, %49
>  %163 = fmul float %75, %50
>  %164 = fadd float %163, %160
>  %165 = fmul float %75, %51
>  %166 = fadd float %165, %161
>  %167 = fmul float %75, %52
>  %168 = fadd float %167, %162
>  %169 = fmul float %76, %53
>  %170 = fadd float %169, %164
>  %171 = fmul float %76, %54
>  %172 = fadd float %171, %166
>  %173 = fmul float %76, %55
>  %174 = fadd float %173, %168
>  %175 = fmul float %77, %56
>  %176 = fadd float %175, %170
>  %177 = fmul float %77, %57
>  %178 = fadd float %177, %172
>  %179 = fmul float %77, %58
>  %180 = fadd float %179, %174
>  %181 = fsub float %44, %176
>  %182 = fsub float %45, %178
>  %183 = fsub float %46, %180
>  %184 = fmul float %181, %181
>  %185 = fmul float %182, %182
>  %186 = fadd float %185, %184
>  %187 = fmul float %183, %183
>  %188 = fadd float %186, %187
>  %189 = call float @fabs(float %188)
>  %190 = call float @llvm.AMDGPU.rsq(float %189)
>  %191 = fmul float %181, %190
>  %192 = fmul float %182, %190
>  %193 = fmul float %183, %190
>  %194 = fdiv float 1.000000e+00, %190
>  %195 = fmul float %190, %194
>  %196 = fmul float %194, %194
>  %197 = fmul float %59, %195
>  %198 = fmul float %60, %194
>  %199 = fadd float %198, %197
>  %200 = fmul float %61, %196
>  %201 = fadd float %199, %200
>  %202 = fdiv float 1.000000e+00, %201
>  %203 = fmul float %176, %176
>  %204 = fmul float %178, %178
>  %205 = fadd float %204, %203
>  %206 = fmul float %180, %180
>  %207 = fadd float %205, %206
>  %208 = call float @fabs(float %207)
>  %209 = call float @llvm.AMDGPU.rsq(float %208)
>  %210 = fmul float %176, %209
>  %211 = fmul float %178, %209
>  %212 = fmul float %180, %209
>  %213 = fsub float %191, %210
>  %214 = fsub float %192, %211
>  %215 = fsub float %193, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fmul float %147, %191
>  %227 = fmul float %148, %192
>  %228 = fadd float %227, %226
>  %229 = fmul float %149, %193
>  %230 = fadd float %228, %229
>  %231 = fmul float %147, %223
>  %232 = fmul float %148, %224
>  %233 = fadd float %232, %231
>  %234 = fmul float %149, %225
>  %235 = fadd float %233, %234
>  %236 = fcmp uge float %230, 0.000000e+00
>  %237 = select i1 %236, float %230, float 0.000000e+00
>  %238 = fcmp uge float %235, 0.000000e+00
>  %239 = select i1 %238, float %235, float 0.000000e+00
>  %240 = call float @llvm.pow.f32(float %239, float %36)
>  %241 = call float @llvm.AMDGPU.cndlt(float %230, float 0.000000e+00, float %240)
>  %242 = fmul float 1.000000e+00, %202
>  %243 = fmul float %237, %202
>  %244 = fmul float %241, %202
>  %245 = fmul float %242, %62
>  %246 = fadd float %245, %151
>  %247 = fmul float %242, %63
>  %248 = fadd float %247, %153
>  %249 = fmul float %242, %64
>  %250 = fadd float %249, %155
>  %251 = fmul float %243, %65
>  %252 = fadd float %251, %246
>  %253 = fmul float %243, %66
>  %254 = fadd float %253, %248
>  %255 = fmul float %243, %67
>  %256 = fadd float %255, %250
>  %257 = fmul float %244, %68
>  %258 = fadd float %257, %252
>  %259 = fmul float %244, %69
>  %260 = fadd float %259, %254
>  %261 = fmul float %244, %70
>  %262 = fadd float %261, %256
>  %263 = call float @llvm.AMDIL.clamp.(float %258, float 0.000000e+00, float 1.000000e+00)
>  %264 = call float @llvm.AMDIL.clamp.(float %260, float 0.000000e+00, float 1.000000e+00)
>  %265 = call float @llvm.AMDIL.clamp.(float %262, float 0.000000e+00, float 1.000000e+00)
>  %266 = call float @fabs(float %180)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %263, float %264, float %265, float %159)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %266, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %93, float %94, float %95, float %96)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %118, float %120, float %122, float %124)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820006
>04140904
>c2020130
>bf8c007f
>100a0204
>c2020134
>bf8c007f
>d2820005
>04140902
>c2020138
>bf8c007f
>d2820005
>04140903
>c202013c
>bf8c007f
>d2820008
>04140904
>100a1108
>d2820007
>04160d06
>c2020132
>bf8c007f
>100a0204
>c2020136
>bf8c007f
>d2820005
>04140902
>c202013a
>bf8c007f
>d2820005
>04140903
>c202013e
>bf8c007f
>d2820005
>04140904
>d2820007
>041e0b05
>d2060107
>02010107
>7e125b07
>10141306
>c202012d
>bf8c007f
>080e0c04
>c202012c
>bf8c007f
>081a1004
>100c1b0d
>d2820006
>041a0f07
>c202012e
>bf8c007f
>08160a04
>d2820006
>041a170b
>d2060106
>02010106
>7e0c5b06
>100e0d07
>08181507
>10141308
>10100d0d
>081a1508
>10141b0d
>d282000e
>042a190c
>10141305
>10120d0b
>08141509
>d282000b
>043a150a
>d206010b
>0201010b
>7e165b0b
>1018170c
>101a170d
>c0840704
>bf8c007f
>e00c2000
>80020e00
>c2020114
>bf8c0070
>10241c04
>c2020115
>bf8c007f
>d2820012
>0448090f
>c2020116
>bf8c007f
>d2820012
>04480910
>c2020110
>bf8c007f
>10261c04
>c2020111
>bf8c007f
>d2820013
>044c090f
>c2020112
>bf8c007f
>d2820013
>044c0910
>10282713
>d2820014
>04522512
>c2020118
>bf8c007f
>102a1c04
>c2020119
>bf8c007f
>d2820015
>0454090f
>c202011a
>bf8c007f
>d282000f
>04540910
>d282000e
>04521f0f
>d206010e
>0201010e
>7e205b0e
>101c2113
>10221b0e
>101a2112
>d282000c
>0446190d
>1016170a
>1014210f
>d282000b
>0432170a
>d00c0004
>0201010b
>d200000b
>00121680
>7e164f0b
>c202011c
>bf8c007f
>0e161604
>7e164b0b
>1010110e
>d2820007
>04220f0d
>d2820008
>041e130a
>d0080004
>02021080
>d2000009
>0011010b
>7e0e5506
>100c0f06
>c2020140
>bf8c007f
>100c0c04
>c2020141
>bf8c007f
>d2820006
>041a0e04
>100e0f07
>c2020142
>bf8c007f
>d2820006
>041a0e04
>7e0e5506
>100c0f09
>d00c0004
>02010108
>d2000008
>00121080
>10100f08
>c0840708
>bf8c007f
>e00c2000
>80020900
>c2020122
>c2028126
>bf8c0070
>7e1a0205
>d282000d
>042e1a04
>c2020146
>bf8c007f
>d282000d
>04340907
>c202014a
>bf8c007f
>d282000d
>04340908
>c202014e
>bf8c007f
>d282000d
>04340906
>d206080d
>0201010d
>c2020121
>c2028125
>bf8c007f
>7e1c0205
>d282000e
>042a1c04
>c2020145
>bf8c007f
>d282000e
>04380907
>c2020149
>bf8c007f
>d282000e
>04380908
>c202014d
>bf8c007f
>d282000e
>04380906
>d206080e
>0201010e
>c2020120
>c2028124
>bf8c007f
>7e1e0205
>d2820009
>04261e04
>c2020144
>bf8c007f
>d2820007
>04240907
>c2020148
>bf8c007f
>d2820007
>041c0908
>c202014c
>bf8c007f
>d2820006
>041c0906
>d2060806
>02010106
>c202012b
>bf8c007f
>d2060807
>02010004
>f800020f
>070d0e06
>d2060105
>02010105
>bf8c070f
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..19]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: ABS OUT[2].x, TEMP[4].zzzz
> 41: MOV OUT[2].yzw, IMM[0].xxxy
> 42: MOV OUT[3], IN[3]
> 43: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
>  %74 = extractelement <4 x float> %73, i32 0
>  %75 = extractelement <4 x float> %73, i32 1
>  %76 = extractelement <4 x float> %73, i32 2
>  %77 = extractelement <4 x float> %73, i32 3
>  %78 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %79 = load <16 x i8> addrspace(2)* %78, !tbaa !0
>  %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %79, i32 0, i32 %5)
>  %81 = extractelement <4 x float> %80, i32 0
>  %82 = extractelement <4 x float> %80, i32 1
>  %83 = extractelement <4 x float> %80, i32 2
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = extractelement <4 x float> %92, i32 3
>  %97 = fmul float %74, %11
>  %98 = fmul float %74, %12
>  %99 = fmul float %74, %13
>  %100 = fmul float %74, %14
>  %101 = fmul float %75, %15
>  %102 = fadd float %101, %97
>  %103 = fmul float %75, %16
>  %104 = fadd float %103, %98
>  %105 = fmul float %75, %17
>  %106 = fadd float %105, %99
>  %107 = fmul float %75, %18
>  %108 = fadd float %107, %100
>  %109 = fmul float %76, %19
>  %110 = fadd float %109, %102
>  %111 = fmul float %76, %20
>  %112 = fadd float %111, %104
>  %113 = fmul float %76, %21
>  %114 = fadd float %113, %106
>  %115 = fmul float %76, %22
>  %116 = fadd float %115, %108
>  %117 = fmul float %77, %23
>  %118 = fadd float %117, %110
>  %119 = fmul float %77, %24
>  %120 = fadd float %119, %112
>  %121 = fmul float %77, %25
>  %122 = fadd float %121, %114
>  %123 = fmul float %77, %26
>  %124 = fadd float %123, %116
>  %125 = fmul float %81, %27
>  %126 = fmul float %82, %28
>  %127 = fadd float %126, %125
>  %128 = fmul float %83, %29
>  %129 = fadd float %127, %128
>  %130 = fmul float %81, %30
>  %131 = fmul float %82, %31
>  %132 = fadd float %131, %130
>  %133 = fmul float %83, %32
>  %134 = fadd float %132, %133
>  %135 = fmul float %81, %33
>  %136 = fmul float %82, %34
>  %137 = fadd float %136, %135
>  %138 = fmul float %83, %35
>  %139 = fadd float %137, %138
>  %140 = fmul float %129, %129
>  %141 = fmul float %134, %134
>  %142 = fadd float %141, %140
>  %143 = fmul float %139, %139
>  %144 = fadd float %142, %143
>  %145 = call float @fabs(float %144)
>  %146 = call float @llvm.AMDGPU.rsq(float %145)
>  %147 = fmul float %129, %146
>  %148 = fmul float %134, %146
>  %149 = fmul float %139, %146
>  %150 = fmul float %37, %40
>  %151 = fadd float %150, %87
>  %152 = fmul float %38, %41
>  %153 = fadd float %152, %88
>  %154 = fmul float %39, %42
>  %155 = fadd float %154, %89
>  %156 = call float @llvm.AMDIL.clamp.(float %151, float 0.000000e+00, float 1.000000e+00)
>  %157 = call float @llvm.AMDIL.clamp.(float %153, float 0.000000e+00, float 1.000000e+00)
>  %158 = call float @llvm.AMDIL.clamp.(float %155, float 0.000000e+00, float 1.000000e+00)
>  %159 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %160 = fmul float %74, %47
>  %161 = fmul float %74, %48
>  %162 = fmul float %74, %49
>  %163 = fmul float %75, %50
>  %164 = fadd float %163, %160
>  %165 = fmul float %75, %51
>  %166 = fadd float %165, %161
>  %167 = fmul float %75, %52
>  %168 = fadd float %167, %162
>  %169 = fmul float %76, %53
>  %170 = fadd float %169, %164
>  %171 = fmul float %76, %54
>  %172 = fadd float %171, %166
>  %173 = fmul float %76, %55
>  %174 = fadd float %173, %168
>  %175 = fmul float %77, %56
>  %176 = fadd float %175, %170
>  %177 = fmul float %77, %57
>  %178 = fadd float %177, %172
>  %179 = fmul float %77, %58
>  %180 = fadd float %179, %174
>  %181 = fsub float %44, %176
>  %182 = fsub float %45, %178
>  %183 = fsub float %46, %180
>  %184 = fmul float %181, %181
>  %185 = fmul float %182, %182
>  %186 = fadd float %185, %184
>  %187 = fmul float %183, %183
>  %188 = fadd float %186, %187
>  %189 = call float @fabs(float %188)
>  %190 = call float @llvm.AMDGPU.rsq(float %189)
>  %191 = fmul float %181, %190
>  %192 = fmul float %182, %190
>  %193 = fmul float %183, %190
>  %194 = fdiv float 1.000000e+00, %190
>  %195 = fmul float %190, %194
>  %196 = fmul float %194, %194
>  %197 = fmul float %59, %195
>  %198 = fmul float %60, %194
>  %199 = fadd float %198, %197
>  %200 = fmul float %61, %196
>  %201 = fadd float %199, %200
>  %202 = fdiv float 1.000000e+00, %201
>  %203 = fmul float %176, %176
>  %204 = fmul float %178, %178
>  %205 = fadd float %204, %203
>  %206 = fmul float %180, %180
>  %207 = fadd float %205, %206
>  %208 = call float @fabs(float %207)
>  %209 = call float @llvm.AMDGPU.rsq(float %208)
>  %210 = fmul float %176, %209
>  %211 = fmul float %178, %209
>  %212 = fmul float %180, %209
>  %213 = fsub float %191, %210
>  %214 = fsub float %192, %211
>  %215 = fsub float %193, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fmul float %147, %191
>  %227 = fmul float %148, %192
>  %228 = fadd float %227, %226
>  %229 = fmul float %149, %193
>  %230 = fadd float %228, %229
>  %231 = fmul float %147, %223
>  %232 = fmul float %148, %224
>  %233 = fadd float %232, %231
>  %234 = fmul float %149, %225
>  %235 = fadd float %233, %234
>  %236 = fcmp uge float %230, 0.000000e+00
>  %237 = select i1 %236, float %230, float 0.000000e+00
>  %238 = fcmp uge float %235, 0.000000e+00
>  %239 = select i1 %238, float %235, float 0.000000e+00
>  %240 = call float @llvm.pow.f32(float %239, float %36)
>  %241 = call float @llvm.AMDGPU.cndlt(float %230, float 0.000000e+00, float %240)
>  %242 = fmul float 1.000000e+00, %202
>  %243 = fmul float %237, %202
>  %244 = fmul float %241, %202
>  %245 = fmul float %242, %62
>  %246 = fadd float %245, %151
>  %247 = fmul float %242, %63
>  %248 = fadd float %247, %153
>  %249 = fmul float %242, %64
>  %250 = fadd float %249, %155
>  %251 = fmul float %243, %65
>  %252 = fadd float %251, %246
>  %253 = fmul float %243, %66
>  %254 = fadd float %253, %248
>  %255 = fmul float %243, %67
>  %256 = fadd float %255, %250
>  %257 = fmul float %244, %68
>  %258 = fadd float %257, %252
>  %259 = fmul float %244, %69
>  %260 = fadd float %259, %254
>  %261 = fmul float %244, %70
>  %262 = fadd float %261, %256
>  %263 = call float @llvm.AMDIL.clamp.(float %258, float 0.000000e+00, float 1.000000e+00)
>  %264 = call float @llvm.AMDIL.clamp.(float %260, float 0.000000e+00, float 1.000000e+00)
>  %265 = call float @llvm.AMDIL.clamp.(float %262, float 0.000000e+00, float 1.000000e+00)
>  %266 = call float @fabs(float %180)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %263, float %264, float %265, float %159)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %266, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %93, float %94, float %95, float %96)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %118, float %120, float %122, float %124)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020131
>bf8c007f
>100a0204
>c2020135
>bf8c007f
>d2820005
>04140902
>c2020139
>bf8c007f
>d2820005
>04140903
>c202013d
>bf8c007f
>d2820006
>04140904
>c2020130
>bf8c007f
>100a0204
>c2020134
>bf8c007f
>d2820005
>04140902
>c2020138
>bf8c007f
>d2820005
>04140903
>c202013c
>bf8c007f
>d2820008
>04140904
>100a1108
>d2820007
>04160d06
>c2020132
>bf8c007f
>100a0204
>c2020136
>bf8c007f
>d2820005
>04140902
>c202013a
>bf8c007f
>d2820005
>04140903
>c202013e
>bf8c007f
>d2820005
>04140904
>d2820007
>041e0b05
>d2060107
>02010107
>7e125b07
>10141306
>c202012d
>bf8c007f
>080e0c04
>c202012c
>bf8c007f
>081a1004
>100c1b0d
>d2820006
>041a0f07
>c202012e
>bf8c007f
>08160a04
>d2820006
>041a170b
>d2060106
>02010106
>7e0c5b06
>100e0d07
>08181507
>10141308
>10100d0d
>081a1508
>10141b0d
>d282000e
>042a190c
>10141305
>10120d0b
>08141509
>d282000b
>043a150a
>d206010b
>0201010b
>7e165b0b
>1018170c
>101a170d
>c0840704
>bf8c007f
>e00c2000
>80020e00
>c2020114
>bf8c0070
>10241c04
>c2020115
>bf8c007f
>d2820012
>0448090f
>c2020116
>bf8c007f
>d2820012
>04480910
>c2020110
>bf8c007f
>10261c04
>c2020111
>bf8c007f
>d2820013
>044c090f
>c2020112
>bf8c007f
>d2820013
>044c0910
>10282713
>d2820014
>04522512
>c2020118
>bf8c007f
>102a1c04
>c2020119
>bf8c007f
>d2820015
>0454090f
>c202011a
>bf8c007f
>d282000f
>04540910
>d282000e
>04521f0f
>d206010e
>0201010e
>7e205b0e
>101c2113
>10221b0e
>101a2112
>d282000c
>0446190d
>1016170a
>1014210f
>d282000b
>0432170a
>d00c0004
>0201010b
>d200000b
>00121680
>7e164f0b
>c202011c
>bf8c007f
>0e161604
>7e164b0b
>1010110e
>d2820007
>04220f0d
>d2820008
>041e130a
>d0080004
>02021080
>d2000009
>0011010b
>7e0e5506
>100c0f06
>c2020140
>bf8c007f
>100c0c04
>c2020141
>bf8c007f
>d2820006
>041a0e04
>100e0f07
>c2020142
>bf8c007f
>d2820006
>041a0e04
>7e0e5506
>100c0f09
>d00c0004
>02010108
>d2000008
>00121080
>10100f08
>c0840708
>bf8c007f
>e00c2000
>80020900
>c2020122
>c2028126
>bf8c0070
>7e1a0205
>d282000d
>042e1a04
>c2020146
>bf8c007f
>d282000d
>04340907
>c202014a
>bf8c007f
>d282000d
>04340908
>c202014e
>bf8c007f
>d282000d
>04340906
>d206080d
>0201010d
>c2020121
>c2028125
>bf8c007f
>7e1c0205
>d282000e
>042a1c04
>c2020145
>bf8c007f
>d282000e
>04380907
>c2020149
>bf8c007f
>d282000e
>04380908
>c202014d
>bf8c007f
>d282000e
>04380906
>d206080e
>0201010e
>c2020120
>c2028124
>bf8c007f
>7e1e0205
>d2820009
>04261e04
>c2020144
>bf8c007f
>d2820007
>04240907
>c2020148
>bf8c007f
>d2820007
>041c0908
>c202014c
>bf8c007f
>d2820006
>041c0906
>d2060806
>02010106
>c202012b
>bf8c007f
>d2060807
>02010004
>f800020f
>070d0e06
>d2060105
>02010105
>bf8c070f
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..7]
>DCL CONST[9..12]
>DCL TEMP[0..1]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MUL TEMP[1], IN[2].xxxx, CONST[9]
>  9: MAD TEMP[1], IN[2].yyyy, CONST[10], TEMP[1]
> 10: MAD TEMP[1], IN[2].zzzz, CONST[11], TEMP[1]
> 11: MAD OUT[3], IN[2].wwww, CONST[12], TEMP[1]
> 12: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = extractelement <4 x float> %56, i32 3
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 0
>  %65 = extractelement <4 x float> %63, i32 1
>  %66 = extractelement <4 x float> %63, i32 2
>  %67 = extractelement <4 x float> %63, i32 3
>  %68 = fmul float %50, %11
>  %69 = fmul float %50, %12
>  %70 = fmul float %50, %13
>  %71 = fmul float %50, %14
>  %72 = fmul float %51, %15
>  %73 = fadd float %72, %68
>  %74 = fmul float %51, %16
>  %75 = fadd float %74, %69
>  %76 = fmul float %51, %17
>  %77 = fadd float %76, %70
>  %78 = fmul float %51, %18
>  %79 = fadd float %78, %71
>  %80 = fmul float %52, %19
>  %81 = fadd float %80, %73
>  %82 = fmul float %52, %20
>  %83 = fadd float %82, %75
>  %84 = fmul float %52, %21
>  %85 = fadd float %84, %77
>  %86 = fmul float %52, %22
>  %87 = fadd float %86, %79
>  %88 = fmul float %53, %23
>  %89 = fadd float %88, %81
>  %90 = fmul float %53, %24
>  %91 = fadd float %90, %83
>  %92 = fmul float %53, %25
>  %93 = fadd float %92, %85
>  %94 = fmul float %53, %26
>  %95 = fadd float %94, %87
>  %96 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %97 = call float @llvm.AMDIL.clamp.(float %58, float 0.000000e+00, float 1.000000e+00)
>  %98 = call float @llvm.AMDIL.clamp.(float %59, float 0.000000e+00, float 1.000000e+00)
>  %99 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %100 = fmul float %50, %27
>  %101 = fmul float %51, %28
>  %102 = fadd float %100, %101
>  %103 = fmul float %52, %29
>  %104 = fadd float %102, %103
>  %105 = fmul float %53, %30
>  %106 = fadd float %104, %105
>  %107 = call float @fabs(float %106)
>  %108 = fmul float %64, %31
>  %109 = fmul float %64, %32
>  %110 = fmul float %64, %33
>  %111 = fmul float %64, %34
>  %112 = fmul float %65, %35
>  %113 = fadd float %112, %108
>  %114 = fmul float %65, %36
>  %115 = fadd float %114, %109
>  %116 = fmul float %65, %37
>  %117 = fadd float %116, %110
>  %118 = fmul float %65, %38
>  %119 = fadd float %118, %111
>  %120 = fmul float %66, %39
>  %121 = fadd float %120, %113
>  %122 = fmul float %66, %40
>  %123 = fadd float %122, %115
>  %124 = fmul float %66, %41
>  %125 = fadd float %124, %117
>  %126 = fmul float %66, %42
>  %127 = fadd float %126, %119
>  %128 = fmul float %67, %43
>  %129 = fadd float %128, %121
>  %130 = fmul float %67, %44
>  %131 = fadd float %130, %123
>  %132 = fmul float %67, %45
>  %133 = fadd float %132, %125
>  %134 = fmul float %67, %46
>  %135 = fadd float %134, %127
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %96, float %97, float %98, float %99)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %107, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %129, float %131, float %133, float %135)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %89, float %91, float %93, float %95)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>c2020127
>bf8c0070
>10000a04
>c202012b
>bf8c007f
>d2820000
>04000906
>c202012f
>bf8c007f
>d2820000
>04000907
>c2020133
>bf8c007f
>d2820000
>04000908
>c2020126
>bf8c007f
>10120a04
>c202012a
>bf8c007f
>d2820009
>04240906
>c202012e
>bf8c007f
>d2820009
>04240907
>c2020132
>bf8c007f
>d2820009
>04240908
>c2020125
>bf8c007f
>10140a04
>c2020129
>bf8c007f
>d282000a
>04280906
>c202012d
>bf8c007f
>d282000a
>04280907
>c2020131
>bf8c007f
>d282000a
>04280908
>c2020124
>bf8c007f
>10160a04
>c2020128
>bf8c007f
>d282000b
>042c0906
>c202012c
>bf8c007f
>d282000b
>042c0907
>c2020130
>bf8c007f
>d2820005
>042c0908
>f800022f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], FOG, PERSPECTIVE
>DCL IN[1], GENERIC[1], PERSPECTIVE
>DCL IN[2], GENERIC[2], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..5]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: TXP TEMP[0], IN[1], SAMP[1], CUBE
>  1: MUL TEMP[0].xyz, TEMP[0], CONST[3]
>  2: MOV TEMP[1].xy, IN[2].xyyy
>  3: MOV TEMP[1].w, IN[2].wwww
>  4: TXP TEMP[1].w, TEMP[1], SAMP[0], 2D
>  5: MOV TEMP[1].w, TEMP[1].wwww
>  6: MAD_SAT TEMP[2].x, IN[0].xxxx, CONST[2].xxxx, CONST[2].yyyy
>  7: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].xxxx
>  8: MUL TEMP[3].xyz, CONST[4].xyzz, TEMP[3].xxxx
>  9: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 10: MOV OUT[0], TEMP[1]
> 11: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %30 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %31 = load <32 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0
>  %34 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %35 = load <32 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
>  %38 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %46 = fdiv float %39, %42
>  %47 = fdiv float %40, %42
>  %48 = fdiv float %41, %42
>  %49 = insertelement <4 x float> undef, float %46, i32 0
>  %50 = insertelement <4 x float> %49, float %47, i32 1
>  %51 = insertelement <4 x float> %50, float %48, i32 2
>  %52 = insertelement <4 x float> %51, float 1.000000e+00, i32 3
>  %53 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %52)
>  %54 = extractelement <4 x float> %53, i32 0
>  %55 = extractelement <4 x float> %53, i32 1
>  %56 = extractelement <4 x float> %53, i32 2
>  %57 = extractelement <4 x float> %53, i32 3
>  %58 = call float @fabs(float %56)
>  %59 = fdiv float 1.000000e+00, %58
>  %60 = fmul float %54, %59
>  %61 = fadd float %60, 1.500000e+00
>  %62 = fmul float %55, %59
>  %63 = fadd float %62, 1.500000e+00
>  %64 = bitcast float %63 to i32
>  %65 = bitcast float %61 to i32
>  %66 = bitcast float %57 to i32
>  %67 = insertelement <4 x i32> undef, i32 %64, i32 0
>  %68 = insertelement <4 x i32> %67, i32 %65, i32 1
>  %69 = insertelement <4 x i32> %68, i32 %66, i32 2
>  %70 = insertelement <4 x i32> %69, i32 undef, i32 3
>  %71 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %70, <32 x i8> %35, <16 x i8> %37, i32 4)
>  %72 = extractelement <4 x float> %71, i32 0
>  %73 = extractelement <4 x float> %71, i32 1
>  %74 = extractelement <4 x float> %71, i32 2
>  %75 = fmul float %72, %24
>  %76 = fmul float %73, %25
>  %77 = fmul float %74, %26
>  %78 = fdiv float %43, %45
>  %79 = fdiv float %44, %45
>  %80 = bitcast float %78 to i32
>  %81 = bitcast float %79 to i32
>  %82 = insertelement <2 x i32> undef, i32 %80, i32 0
>  %83 = insertelement <2 x i32> %82, i32 %81, i32 1
>  %84 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %83, <32 x i8> %31, <16 x i8> %33, i32 2)
>  %85 = extractelement <4 x float> %84, i32 3
>  %86 = fmul float %38, %22
>  %87 = fadd float %86, %23
>  %88 = call float @llvm.AMDIL.clamp.(float %87, float 0.000000e+00, float 1.000000e+00)
>  %89 = fsub float -0.000000e+00, %88
>  %90 = fadd float 1.000000e+00, %89
>  %91 = fmul float %27, %90
>  %92 = fmul float %28, %90
>  %93 = fmul float %29, %90
>  %94 = fmul float %75, %88
>  %95 = fadd float %94, %91
>  %96 = fmul float %76, %88
>  %97 = fadd float %96, %92
>  %98 = fmul float %77, %88
>  %99 = fadd float %98, %93
>  %100 = call i32 @llvm.SI.packf16(float %95, float %97)
>  %101 = bitcast i32 %100 to float
>  %102 = call i32 @llvm.SI.packf16(float %99, float %85)
>  %103 = bitcast i32 %102 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %101, float %103, float %101, float %103)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e0c5503
>10060d02
>c81c0400
>c81d0401
>10040d07
>c81c0600
>c81d0601
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c0840304
>c0c60508
>bf8c007f
>f0800700
>00430307
>c0840100
>bf8c0070
>c200090d
>bf8c007f
>10040800
>c8180000
>c8190001
>c2000908
>c2008909
>bf8c007f
>7e0e0201
>d2820006
>041c0106
>d2060806
>02010106
>080e0cf2
>c2000911
>bf8c007f
>10100e00
>d2820002
>04220d02
>c200090c
>bf8c007f
>10100600
>c2000910
>bf8c007f
>10120e00
>d2820008
>04260d08
>5e040508
>c200090e
>bf8c007f
>10060a00
>c2000912
>bf8c007f
>10080e00
>d2820003
>04120d03
>c8100900
>c8110901
>c8140b00
>c8150b01
>7e0c5505
>100a0d04
>c81c0800
>c81d0801
>10080d07
>c0800300
>c0c20500
>bf8c007f
>f0800800
>00010004
>bf8c0770
>5e000103
>f8001c0f
>00020002
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], FOG
>DCL OUT[2], GENERIC[1]
>DCL OUT[3], GENERIC[2]
>DCL CONST[0..7]
>DCL CONST[9..15]
>DCL TEMP[0..4]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP4 TEMP[0], IN[0], CONST[6]
>  5: ABS OUT[1].x, TEMP[0]
>  6: MOV OUT[1].yzw, IMM[0].xxxy
>  7: DP3 TEMP[1].x, IN[1], CONST[9]
>  8: DP3 TEMP[1].y, IN[1], CONST[10]
>  9: DP3 TEMP[1].z, IN[1], CONST[11]
> 10: DP3 TEMP[2].x, TEMP[1], TEMP[1]
> 11: RSQ TEMP[2].x, |TEMP[2]|
> 12: MUL TEMP[1], TEMP[1], TEMP[2].xxxx
> 13: MUL TEMP[2], IN[0].xxxx, CONST[12]
> 14: MAD TEMP[2], IN[0].yyyy, CONST[13], TEMP[2]
> 15: MAD TEMP[2], IN[0].zzzz, CONST[14], TEMP[2]
> 16: MAD TEMP[2], IN[0].wwww, CONST[15], TEMP[2]
> 17: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 18: RSQ TEMP[3].x, |TEMP[3]|
> 19: MUL TEMP[4], TEMP[2], TEMP[3].xxxx
> 20: DP3 TEMP[3], TEMP[1], TEMP[4]
> 21: ADD TEMP[3], TEMP[3], TEMP[3]
> 22: MAD OUT[2].xyz, -TEMP[3], TEMP[1], TEMP[4]
> 23: MOV OUT[2].w, IN[2]
> 24: MOV OUT[3], IN[3]
> 25: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %52 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %53 = load <16 x i8> addrspace(2)* %52, !tbaa !0
>  %54 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %53, i32 0, i32 %5)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %58 = extractelement <4 x float> %54, i32 3
>  %59 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
>  %61 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %60, i32 0, i32 %5)
>  %62 = extractelement <4 x float> %61, i32 0
>  %63 = extractelement <4 x float> %61, i32 1
>  %64 = extractelement <4 x float> %61, i32 2
>  %65 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %66 = load <16 x i8> addrspace(2)* %65, !tbaa !0
>  %67 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %66, i32 0, i32 %5)
>  %68 = extractelement <4 x float> %67, i32 3
>  %69 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %70 = load <16 x i8> addrspace(2)* %69, !tbaa !0
>  %71 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %70, i32 0, i32 %5)
>  %72 = extractelement <4 x float> %71, i32 0
>  %73 = extractelement <4 x float> %71, i32 1
>  %74 = extractelement <4 x float> %71, i32 2
>  %75 = extractelement <4 x float> %71, i32 3
>  %76 = fmul float %55, %11
>  %77 = fmul float %55, %12
>  %78 = fmul float %55, %13
>  %79 = fmul float %55, %14
>  %80 = fmul float %56, %15
>  %81 = fadd float %80, %76
>  %82 = fmul float %56, %16
>  %83 = fadd float %82, %77
>  %84 = fmul float %56, %17
>  %85 = fadd float %84, %78
>  %86 = fmul float %56, %18
>  %87 = fadd float %86, %79
>  %88 = fmul float %57, %19
>  %89 = fadd float %88, %81
>  %90 = fmul float %57, %20
>  %91 = fadd float %90, %83
>  %92 = fmul float %57, %21
>  %93 = fadd float %92, %85
>  %94 = fmul float %57, %22
>  %95 = fadd float %94, %87
>  %96 = fmul float %58, %23
>  %97 = fadd float %96, %89
>  %98 = fmul float %58, %24
>  %99 = fadd float %98, %91
>  %100 = fmul float %58, %25
>  %101 = fadd float %100, %93
>  %102 = fmul float %58, %26
>  %103 = fadd float %102, %95
>  %104 = fmul float %55, %27
>  %105 = fmul float %56, %28
>  %106 = fadd float %104, %105
>  %107 = fmul float %57, %29
>  %108 = fadd float %106, %107
>  %109 = fmul float %58, %30
>  %110 = fadd float %108, %109
>  %111 = call float @fabs(float %110)
>  %112 = fmul float %62, %31
>  %113 = fmul float %63, %32
>  %114 = fadd float %113, %112
>  %115 = fmul float %64, %33
>  %116 = fadd float %114, %115
>  %117 = fmul float %62, %34
>  %118 = fmul float %63, %35
>  %119 = fadd float %118, %117
>  %120 = fmul float %64, %36
>  %121 = fadd float %119, %120
>  %122 = fmul float %62, %37
>  %123 = fmul float %63, %38
>  %124 = fadd float %123, %122
>  %125 = fmul float %64, %39
>  %126 = fadd float %124, %125
>  %127 = fmul float %116, %116
>  %128 = fmul float %121, %121
>  %129 = fadd float %128, %127
>  %130 = fmul float %126, %126
>  %131 = fadd float %129, %130
>  %132 = call float @fabs(float %131)
>  %133 = call float @llvm.AMDGPU.rsq(float %132)
>  %134 = fmul float %116, %133
>  %135 = fmul float %121, %133
>  %136 = fmul float %126, %133
>  %137 = fmul float %55, %40
>  %138 = fmul float %55, %41
>  %139 = fmul float %55, %42
>  %140 = fmul float %56, %43
>  %141 = fadd float %140, %137
>  %142 = fmul float %56, %44
>  %143 = fadd float %142, %138
>  %144 = fmul float %56, %45
>  %145 = fadd float %144, %139
>  %146 = fmul float %57, %46
>  %147 = fadd float %146, %141
>  %148 = fmul float %57, %47
>  %149 = fadd float %148, %143
>  %150 = fmul float %57, %48
>  %151 = fadd float %150, %145
>  %152 = fmul float %58, %49
>  %153 = fadd float %152, %147
>  %154 = fmul float %58, %50
>  %155 = fadd float %154, %149
>  %156 = fmul float %58, %51
>  %157 = fadd float %156, %151
>  %158 = fmul float %153, %153
>  %159 = fmul float %155, %155
>  %160 = fadd float %159, %158
>  %161 = fmul float %157, %157
>  %162 = fadd float %160, %161
>  %163 = call float @fabs(float %162)
>  %164 = call float @llvm.AMDGPU.rsq(float %163)
>  %165 = fmul float %153, %164
>  %166 = fmul float %155, %164
>  %167 = fmul float %157, %164
>  %168 = fmul float %134, %165
>  %169 = fmul float %135, %166
>  %170 = fadd float %169, %168
>  %171 = fmul float %136, %167
>  %172 = fadd float %170, %171
>  %173 = fadd float %172, %172
>  %174 = fadd float %172, %172
>  %175 = fadd float %172, %172
>  %176 = fsub float -0.000000e+00, %173
>  %177 = fmul float %176, %134
>  %178 = fadd float %177, %165
>  %179 = fsub float -0.000000e+00, %174
>  %180 = fmul float %179, %135
>  %181 = fadd float %180, %166
>  %182 = fsub float -0.000000e+00, %175
>  %183 = fmul float %182, %136
>  %184 = fadd float %183, %167
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %111, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %178, float %181, float %184, float %68)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %72, float %73, float %74, float %75)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %97, float %99, float %101, float %103)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800020f
>06070705
>c0840704
>bf8c000f
>e00c2000
>80020600
>c2020128
>bf8c0070
>100a0c04
>c2020129
>bf8c007f
>d2820005
>04140907
>c202012a
>bf8c007f
>d2820005
>04140908
>c2020124
>bf8c007f
>10140c04
>c2020125
>bf8c007f
>d282000a
>04280907
>c2020126
>bf8c007f
>d282000a
>04280908
>1016150a
>d282000b
>042e0b05
>c202012c
>bf8c007f
>10180c04
>c202012d
>bf8c007f
>d282000c
>04300907
>c202012e
>bf8c007f
>d2820007
>04300908
>d2820006
>042e0f07
>d2060106
>02010106
>7e105b06
>100c110a
>c2020131
>bf8c007f
>10120204
>c2020135
>bf8c007f
>d2820009
>04240902
>c2020139
>bf8c007f
>d2820009
>04240903
>c202013d
>bf8c007f
>d2820009
>04240904
>c2020130
>bf8c007f
>10140204
>c2020134
>bf8c007f
>d282000a
>04280902
>c2020138
>bf8c007f
>d282000a
>04280903
>c202013c
>bf8c007f
>d282000a
>04280904
>1016150a
>d282000c
>042e1309
>c2020132
>bf8c007f
>10160204
>c2020136
>bf8c007f
>d282000b
>042c0902
>c202013a
>bf8c007f
>d282000b
>042c0903
>c202013e
>bf8c007f
>d282000b
>042c0904
>d282000c
>0432170b
>d206010c
>0201010c
>7e185b0c
>1014190a
>101a1506
>100a1105
>10121909
>d282000d
>04361305
>100e1107
>1016190b
>d2820008
>04361707
>06101108
>100e0f08
>080e0f0b
>100a0b08
>080a0b09
>100c0d08
>080c0d0a
>c0840708
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800021f
>0b070506
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..14]
>DCL TEMP[0..3]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: DP4 TEMP[1], IN[0], CONST[13]
> 15: ABS OUT[2].x, TEMP[1]
> 16: MOV OUT[2].yzw, IMM[0].xxxy
> 17: MOV OUT[3], IN[3]
> 18: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
>  %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %5)
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = extractelement <4 x float> %62, i32 1
>  %65 = extractelement <4 x float> %62, i32 2
>  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
>  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
>  %69 = extractelement <4 x float> %68, i32 0
>  %70 = extractelement <4 x float> %68, i32 1
>  %71 = extractelement <4 x float> %68, i32 2
>  %72 = extractelement <4 x float> %68, i32 3
>  %73 = fmul float %50, %11
>  %74 = fmul float %50, %12
>  %75 = fmul float %50, %13
>  %76 = fmul float %50, %14
>  %77 = fmul float %51, %15
>  %78 = fadd float %77, %73
>  %79 = fmul float %51, %16
>  %80 = fadd float %79, %74
>  %81 = fmul float %51, %17
>  %82 = fadd float %81, %75
>  %83 = fmul float %51, %18
>  %84 = fadd float %83, %76
>  %85 = fmul float %52, %19
>  %86 = fadd float %85, %78
>  %87 = fmul float %52, %20
>  %88 = fadd float %87, %80
>  %89 = fmul float %52, %21
>  %90 = fadd float %89, %82
>  %91 = fmul float %52, %22
>  %92 = fadd float %91, %84
>  %93 = fmul float %53, %23
>  %94 = fadd float %93, %86
>  %95 = fmul float %53, %24
>  %96 = fadd float %95, %88
>  %97 = fmul float %53, %25
>  %98 = fadd float %97, %90
>  %99 = fmul float %53, %26
>  %100 = fadd float %99, %92
>  %101 = fmul float %57, %27
>  %102 = fmul float %58, %28
>  %103 = fadd float %102, %101
>  %104 = fmul float %59, %29
>  %105 = fadd float %103, %104
>  %106 = fmul float %57, %30
>  %107 = fmul float %58, %31
>  %108 = fadd float %107, %106
>  %109 = fmul float %59, %32
>  %110 = fadd float %108, %109
>  %111 = fmul float %57, %33
>  %112 = fmul float %58, %34
>  %113 = fadd float %112, %111
>  %114 = fmul float %59, %35
>  %115 = fadd float %113, %114
>  %116 = fmul float %105, %105
>  %117 = fmul float %110, %110
>  %118 = fadd float %117, %116
>  %119 = fmul float %115, %115
>  %120 = fadd float %118, %119
>  %121 = call float @fabs(float %120)
>  %122 = call float @llvm.AMDGPU.rsq(float %121)
>  %123 = fmul float %36, %39
>  %124 = fadd float %123, %63
>  %125 = fmul float %37, %40
>  %126 = fadd float %125, %64
>  %127 = fmul float %38, %41
>  %128 = fadd float %127, %65
>  %129 = call float @llvm.AMDIL.clamp.(float %124, float 0.000000e+00, float 1.000000e+00)
>  %130 = call float @llvm.AMDIL.clamp.(float %126, float 0.000000e+00, float 1.000000e+00)
>  %131 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
>  %132 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %133 = fmul float %50, %43
>  %134 = fmul float %51, %44
>  %135 = fadd float %133, %134
>  %136 = fmul float %52, %45
>  %137 = fadd float %135, %136
>  %138 = fmul float %53, %46
>  %139 = fadd float %137, %138
>  %140 = call float @fabs(float %139)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %129, float %130, float %131, float %132)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %140, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %69, float %70, float %71, float %72)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %94, float %96, float %98, float %100)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c0840700
>bf8c000f
>e00c2000
>80020100
>c2020135
>bf8c0070
>100a0404
>c2020134
>bf8c007f
>d2820005
>04140901
>c2020136
>bf8c007f
>d2820005
>04140903
>c2020137
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL IN[6]
>DCL IN[7]
>DCL IN[8]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL OUT[5], GENERIC[2]
>DCL OUT[6], GENERIC[3]
>DCL OUT[7], GENERIC[4]
>DCL OUT[8], GENERIC[6]
>DCL CONST[0..19]
>DCL CONST[21..36]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: MUL TEMP[4], IN[0].xxxx, CONST[12]
> 15: MAD TEMP[4], IN[0].yyyy, CONST[13], TEMP[4]
> 16: MAD TEMP[4], IN[0].zzzz, CONST[14], TEMP[4]
> 17: MAD TEMP[4], IN[0].wwww, CONST[15], TEMP[4]
> 18: SUB TEMP[5], CONST[11], TEMP[4]
> 19: DP3 TEMP[6], TEMP[5], TEMP[5]
> 20: RSQ TEMP[6], |TEMP[6]|
> 21: MUL TEMP[5], TEMP[5], TEMP[6]
> 22: RCP TEMP[6].yz, TEMP[6]
> 23: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 24: DP3 TEMP[6], CONST[16], TEMP[6]
> 25: RCP TEMP[7], TEMP[6]
> 26: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 27: RSQ TEMP[8].x, |TEMP[8]|
> 28: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 29: SUB TEMP[8], TEMP[5], TEMP[6]
> 30: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 31: RSQ TEMP[9].x, |TEMP[9]|
> 32: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 33: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 34: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 35: LIT TEMP[1], TEMP[2]
> 36: MUL TEMP[1], TEMP[1], TEMP[7]
> 37: MAD TEMP[3], TEMP[1].xxxx, CONST[17], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].yyyy, CONST[18], TEMP[3]
> 39: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[19], TEMP[3]
> 40: ABS OUT[2].x, TEMP[4].zzzz
> 41: MOV OUT[2].yzw, IMM[0].xxxy
> 42: DP3 TEMP[1], TEMP[0], TEMP[6]
> 43: ADD TEMP[1], TEMP[1], TEMP[1]
> 44: MAD OUT[3].xyz, -TEMP[1], TEMP[0], TEMP[6]
> 45: MOV OUT[3].w, IN[3]
> 46: MUL TEMP[1], IN[4].xxxx, CONST[21]
> 47: MAD TEMP[1], IN[4].yyyy, CONST[22], TEMP[1]
> 48: MAD TEMP[1], IN[4].zzzz, CONST[23], TEMP[1]
> 49: MAD OUT[4], IN[4].wwww, CONST[24], TEMP[1]
> 50: MOV OUT[5], IN[5]
> 51: MUL TEMP[1], IN[6].xxxx, CONST[25]
> 52: MAD TEMP[1], IN[6].yyyy, CONST[26], TEMP[1]
> 53: MAD TEMP[1], IN[6].zzzz, CONST[27], TEMP[1]
> 54: MAD OUT[6], IN[6].wwww, CONST[28], TEMP[1]
> 55: DP3 TEMP[2], TEMP[0], TEMP[6]
> 56: ADD TEMP[2], TEMP[2], TEMP[2]
> 57: MAD TEMP[1].xyz, -TEMP[2], TEMP[0], TEMP[6]
> 58: MOV TEMP[1].w, IN[7]
> 59: MUL TEMP[2], TEMP[1].xxxx, CONST[29]
> 60: MAD TEMP[2], TEMP[1].yyyy, CONST[30], TEMP[2]
> 61: MAD TEMP[2], TEMP[1].zzzz, CONST[31], TEMP[2]
> 62: MAD OUT[7], TEMP[1].wwww, CONST[32], TEMP[2]
> 63: MUL TEMP[1], IN[8].xxxx, CONST[33]
> 64: MAD TEMP[1], IN[8].yyyy, CONST[34], TEMP[1]
> 65: MAD TEMP[1], IN[8].zzzz, CONST[35], TEMP[1]
> 66: MAD OUT[8], IN[8].wwww, CONST[36], TEMP[1]
> 67: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 444)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 460)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 476)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 492)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %113 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 508)
>  %115 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %116 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %117 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %118 = call float @llvm.SI.load.const(<16 x i8> %10, i32 524)
>  %119 = call float @llvm.SI.load.const(<16 x i8> %10, i32 528)
>  %120 = call float @llvm.SI.load.const(<16 x i8> %10, i32 532)
>  %121 = call float @llvm.SI.load.const(<16 x i8> %10, i32 536)
>  %122 = call float @llvm.SI.load.const(<16 x i8> %10, i32 540)
>  %123 = call float @llvm.SI.load.const(<16 x i8> %10, i32 544)
>  %124 = call float @llvm.SI.load.const(<16 x i8> %10, i32 548)
>  %125 = call float @llvm.SI.load.const(<16 x i8> %10, i32 552)
>  %126 = call float @llvm.SI.load.const(<16 x i8> %10, i32 556)
>  %127 = call float @llvm.SI.load.const(<16 x i8> %10, i32 560)
>  %128 = call float @llvm.SI.load.const(<16 x i8> %10, i32 564)
>  %129 = call float @llvm.SI.load.const(<16 x i8> %10, i32 568)
>  %130 = call float @llvm.SI.load.const(<16 x i8> %10, i32 572)
>  %131 = call float @llvm.SI.load.const(<16 x i8> %10, i32 576)
>  %132 = call float @llvm.SI.load.const(<16 x i8> %10, i32 580)
>  %133 = call float @llvm.SI.load.const(<16 x i8> %10, i32 584)
>  %134 = call float @llvm.SI.load.const(<16 x i8> %10, i32 588)
>  %135 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %136 = load <16 x i8> addrspace(2)* %135, !tbaa !0
>  %137 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %136, i32 0, i32 %5)
>  %138 = extractelement <4 x float> %137, i32 0
>  %139 = extractelement <4 x float> %137, i32 1
>  %140 = extractelement <4 x float> %137, i32 2
>  %141 = extractelement <4 x float> %137, i32 3
>  %142 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %143 = load <16 x i8> addrspace(2)* %142, !tbaa !0
>  %144 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %143, i32 0, i32 %5)
>  %145 = extractelement <4 x float> %144, i32 0
>  %146 = extractelement <4 x float> %144, i32 1
>  %147 = extractelement <4 x float> %144, i32 2
>  %148 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %149 = load <16 x i8> addrspace(2)* %148, !tbaa !0
>  %150 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %149, i32 0, i32 %5)
>  %151 = extractelement <4 x float> %150, i32 0
>  %152 = extractelement <4 x float> %150, i32 1
>  %153 = extractelement <4 x float> %150, i32 2
>  %154 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %155 = load <16 x i8> addrspace(2)* %154, !tbaa !0
>  %156 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %155, i32 0, i32 %5)
>  %157 = extractelement <4 x float> %156, i32 3
>  %158 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %159 = load <16 x i8> addrspace(2)* %158, !tbaa !0
>  %160 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %159, i32 0, i32 %5)
>  %161 = extractelement <4 x float> %160, i32 0
>  %162 = extractelement <4 x float> %160, i32 1
>  %163 = extractelement <4 x float> %160, i32 2
>  %164 = extractelement <4 x float> %160, i32 3
>  %165 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %166 = load <16 x i8> addrspace(2)* %165, !tbaa !0
>  %167 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %166, i32 0, i32 %5)
>  %168 = extractelement <4 x float> %167, i32 0
>  %169 = extractelement <4 x float> %167, i32 1
>  %170 = extractelement <4 x float> %167, i32 2
>  %171 = extractelement <4 x float> %167, i32 3
>  %172 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
>  %173 = load <16 x i8> addrspace(2)* %172, !tbaa !0
>  %174 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %173, i32 0, i32 %5)
>  %175 = extractelement <4 x float> %174, i32 0
>  %176 = extractelement <4 x float> %174, i32 1
>  %177 = extractelement <4 x float> %174, i32 2
>  %178 = extractelement <4 x float> %174, i32 3
>  %179 = getelementptr <16 x i8> addrspace(2)* %3, i32 7
>  %180 = load <16 x i8> addrspace(2)* %179, !tbaa !0
>  %181 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %180, i32 0, i32 %5)
>  %182 = extractelement <4 x float> %181, i32 3
>  %183 = getelementptr <16 x i8> addrspace(2)* %3, i32 8
>  %184 = load <16 x i8> addrspace(2)* %183, !tbaa !0
>  %185 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %184, i32 0, i32 %5)
>  %186 = extractelement <4 x float> %185, i32 0
>  %187 = extractelement <4 x float> %185, i32 1
>  %188 = extractelement <4 x float> %185, i32 2
>  %189 = extractelement <4 x float> %185, i32 3
>  %190 = fmul float %138, %11
>  %191 = fmul float %138, %12
>  %192 = fmul float %138, %13
>  %193 = fmul float %138, %14
>  %194 = fmul float %139, %15
>  %195 = fadd float %194, %190
>  %196 = fmul float %139, %16
>  %197 = fadd float %196, %191
>  %198 = fmul float %139, %17
>  %199 = fadd float %198, %192
>  %200 = fmul float %139, %18
>  %201 = fadd float %200, %193
>  %202 = fmul float %140, %19
>  %203 = fadd float %202, %195
>  %204 = fmul float %140, %20
>  %205 = fadd float %204, %197
>  %206 = fmul float %140, %21
>  %207 = fadd float %206, %199
>  %208 = fmul float %140, %22
>  %209 = fadd float %208, %201
>  %210 = fmul float %141, %23
>  %211 = fadd float %210, %203
>  %212 = fmul float %141, %24
>  %213 = fadd float %212, %205
>  %214 = fmul float %141, %25
>  %215 = fadd float %214, %207
>  %216 = fmul float %141, %26
>  %217 = fadd float %216, %209
>  %218 = fmul float %145, %27
>  %219 = fmul float %146, %28
>  %220 = fadd float %219, %218
>  %221 = fmul float %147, %29
>  %222 = fadd float %220, %221
>  %223 = fmul float %145, %30
>  %224 = fmul float %146, %31
>  %225 = fadd float %224, %223
>  %226 = fmul float %147, %32
>  %227 = fadd float %225, %226
>  %228 = fmul float %145, %33
>  %229 = fmul float %146, %34
>  %230 = fadd float %229, %228
>  %231 = fmul float %147, %35
>  %232 = fadd float %230, %231
>  %233 = fmul float %222, %222
>  %234 = fmul float %227, %227
>  %235 = fadd float %234, %233
>  %236 = fmul float %232, %232
>  %237 = fadd float %235, %236
>  %238 = call float @fabs(float %237)
>  %239 = call float @llvm.AMDGPU.rsq(float %238)
>  %240 = fmul float %222, %239
>  %241 = fmul float %227, %239
>  %242 = fmul float %232, %239
>  %243 = fmul float %37, %40
>  %244 = fadd float %243, %151
>  %245 = fmul float %38, %41
>  %246 = fadd float %245, %152
>  %247 = fmul float %39, %42
>  %248 = fadd float %247, %153
>  %249 = call float @llvm.AMDIL.clamp.(float %244, float 0.000000e+00, float 1.000000e+00)
>  %250 = call float @llvm.AMDIL.clamp.(float %246, float 0.000000e+00, float 1.000000e+00)
>  %251 = call float @llvm.AMDIL.clamp.(float %248, float 0.000000e+00, float 1.000000e+00)
>  %252 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %253 = fmul float %138, %47
>  %254 = fmul float %138, %48
>  %255 = fmul float %138, %49
>  %256 = fmul float %139, %50
>  %257 = fadd float %256, %253
>  %258 = fmul float %139, %51
>  %259 = fadd float %258, %254
>  %260 = fmul float %139, %52
>  %261 = fadd float %260, %255
>  %262 = fmul float %140, %53
>  %263 = fadd float %262, %257
>  %264 = fmul float %140, %54
>  %265 = fadd float %264, %259
>  %266 = fmul float %140, %55
>  %267 = fadd float %266, %261
>  %268 = fmul float %141, %56
>  %269 = fadd float %268, %263
>  %270 = fmul float %141, %57
>  %271 = fadd float %270, %265
>  %272 = fmul float %141, %58
>  %273 = fadd float %272, %267
>  %274 = fsub float %44, %269
>  %275 = fsub float %45, %271
>  %276 = fsub float %46, %273
>  %277 = fmul float %274, %274
>  %278 = fmul float %275, %275
>  %279 = fadd float %278, %277
>  %280 = fmul float %276, %276
>  %281 = fadd float %279, %280
>  %282 = call float @fabs(float %281)
>  %283 = call float @llvm.AMDGPU.rsq(float %282)
>  %284 = fmul float %274, %283
>  %285 = fmul float %275, %283
>  %286 = fmul float %276, %283
>  %287 = fdiv float 1.000000e+00, %283
>  %288 = fmul float %283, %287
>  %289 = fmul float %287, %287
>  %290 = fmul float %59, %288
>  %291 = fmul float %60, %287
>  %292 = fadd float %291, %290
>  %293 = fmul float %61, %289
>  %294 = fadd float %292, %293
>  %295 = fdiv float 1.000000e+00, %294
>  %296 = fmul float %269, %269
>  %297 = fmul float %271, %271
>  %298 = fadd float %297, %296
>  %299 = fmul float %273, %273
>  %300 = fadd float %298, %299
>  %301 = call float @fabs(float %300)
>  %302 = call float @llvm.AMDGPU.rsq(float %301)
>  %303 = fmul float %269, %302
>  %304 = fmul float %271, %302
>  %305 = fmul float %273, %302
>  %306 = fsub float %284, %303
>  %307 = fsub float %285, %304
>  %308 = fsub float %286, %305
>  %309 = fmul float %306, %306
>  %310 = fmul float %307, %307
>  %311 = fadd float %310, %309
>  %312 = fmul float %308, %308
>  %313 = fadd float %311, %312
>  %314 = call float @fabs(float %313)
>  %315 = call float @llvm.AMDGPU.rsq(float %314)
>  %316 = fmul float %306, %315
>  %317 = fmul float %307, %315
>  %318 = fmul float %308, %315
>  %319 = fmul float %240, %284
>  %320 = fmul float %241, %285
>  %321 = fadd float %320, %319
>  %322 = fmul float %242, %286
>  %323 = fadd float %321, %322
>  %324 = fmul float %240, %316
>  %325 = fmul float %241, %317
>  %326 = fadd float %325, %324
>  %327 = fmul float %242, %318
>  %328 = fadd float %326, %327
>  %329 = fcmp uge float %323, 0.000000e+00
>  %330 = select i1 %329, float %323, float 0.000000e+00
>  %331 = fcmp uge float %328, 0.000000e+00
>  %332 = select i1 %331, float %328, float 0.000000e+00
>  %333 = call float @llvm.pow.f32(float %332, float %36)
>  %334 = call float @llvm.AMDGPU.cndlt(float %323, float 0.000000e+00, float %333)
>  %335 = fmul float 1.000000e+00, %295
>  %336 = fmul float %330, %295
>  %337 = fmul float %334, %295
>  %338 = fmul float %335, %62
>  %339 = fadd float %338, %244
>  %340 = fmul float %335, %63
>  %341 = fadd float %340, %246
>  %342 = fmul float %335, %64
>  %343 = fadd float %342, %248
>  %344 = fmul float %336, %65
>  %345 = fadd float %344, %339
>  %346 = fmul float %336, %66
>  %347 = fadd float %346, %341
>  %348 = fmul float %336, %67
>  %349 = fadd float %348, %343
>  %350 = fmul float %337, %68
>  %351 = fadd float %350, %345
>  %352 = fmul float %337, %69
>  %353 = fadd float %352, %347
>  %354 = fmul float %337, %70
>  %355 = fadd float %354, %349
>  %356 = call float @llvm.AMDIL.clamp.(float %351, float 0.000000e+00, float 1.000000e+00)
>  %357 = call float @llvm.AMDIL.clamp.(float %353, float 0.000000e+00, float 1.000000e+00)
>  %358 = call float @llvm.AMDIL.clamp.(float %355, float 0.000000e+00, float 1.000000e+00)
>  %359 = call float @fabs(float %273)
>  %360 = fmul float %240, %303
>  %361 = fmul float %241, %304
>  %362 = fadd float %361, %360
>  %363 = fmul float %242, %305
>  %364 = fadd float %362, %363
>  %365 = fadd float %364, %364
>  %366 = fadd float %364, %364
>  %367 = fadd float %364, %364
>  %368 = fsub float -0.000000e+00, %365
>  %369 = fmul float %368, %240
>  %370 = fadd float %369, %303
>  %371 = fsub float -0.000000e+00, %366
>  %372 = fmul float %371, %241
>  %373 = fadd float %372, %304
>  %374 = fsub float -0.000000e+00, %367
>  %375 = fmul float %374, %242
>  %376 = fadd float %375, %305
>  %377 = fmul float %161, %71
>  %378 = fmul float %161, %72
>  %379 = fmul float %161, %73
>  %380 = fmul float %161, %74
>  %381 = fmul float %162, %75
>  %382 = fadd float %381, %377
>  %383 = fmul float %162, %76
>  %384 = fadd float %383, %378
>  %385 = fmul float %162, %77
>  %386 = fadd float %385, %379
>  %387 = fmul float %162, %78
>  %388 = fadd float %387, %380
>  %389 = fmul float %163, %79
>  %390 = fadd float %389, %382
>  %391 = fmul float %163, %80
>  %392 = fadd float %391, %384
>  %393 = fmul float %163, %81
>  %394 = fadd float %393, %386
>  %395 = fmul float %163, %82
>  %396 = fadd float %395, %388
>  %397 = fmul float %164, %83
>  %398 = fadd float %397, %390
>  %399 = fmul float %164, %84
>  %400 = fadd float %399, %392
>  %401 = fmul float %164, %85
>  %402 = fadd float %401, %394
>  %403 = fmul float %164, %86
>  %404 = fadd float %403, %396
>  %405 = fmul float %175, %87
>  %406 = fmul float %175, %88
>  %407 = fmul float %175, %89
>  %408 = fmul float %175, %90
>  %409 = fmul float %176, %91
>  %410 = fadd float %409, %405
>  %411 = fmul float %176, %92
>  %412 = fadd float %411, %406
>  %413 = fmul float %176, %93
>  %414 = fadd float %413, %407
>  %415 = fmul float %176, %94
>  %416 = fadd float %415, %408
>  %417 = fmul float %177, %95
>  %418 = fadd float %417, %410
>  %419 = fmul float %177, %96
>  %420 = fadd float %419, %412
>  %421 = fmul float %177, %97
>  %422 = fadd float %421, %414
>  %423 = fmul float %177, %98
>  %424 = fadd float %423, %416
>  %425 = fmul float %178, %99
>  %426 = fadd float %425, %418
>  %427 = fmul float %178, %100
>  %428 = fadd float %427, %420
>  %429 = fmul float %178, %101
>  %430 = fadd float %429, %422
>  %431 = fmul float %178, %102
>  %432 = fadd float %431, %424
>  %433 = fmul float %240, %303
>  %434 = fmul float %241, %304
>  %435 = fadd float %434, %433
>  %436 = fmul float %242, %305
>  %437 = fadd float %435, %436
>  %438 = fadd float %437, %437
>  %439 = fadd float %437, %437
>  %440 = fadd float %437, %437
>  %441 = fsub float -0.000000e+00, %438
>  %442 = fmul float %441, %240
>  %443 = fadd float %442, %303
>  %444 = fsub float -0.000000e+00, %439
>  %445 = fmul float %444, %241
>  %446 = fadd float %445, %304
>  %447 = fsub float -0.000000e+00, %440
>  %448 = fmul float %447, %242
>  %449 = fadd float %448, %305
>  %450 = fmul float %443, %103
>  %451 = fmul float %443, %104
>  %452 = fmul float %443, %105
>  %453 = fmul float %443, %106
>  %454 = fmul float %446, %107
>  %455 = fadd float %454, %450
>  %456 = fmul float %446, %108
>  %457 = fadd float %456, %451
>  %458 = fmul float %446, %109
>  %459 = fadd float %458, %452
>  %460 = fmul float %446, %110
>  %461 = fadd float %460, %453
>  %462 = fmul float %449, %111
>  %463 = fadd float %462, %455
>  %464 = fmul float %449, %112
>  %465 = fadd float %464, %457
>  %466 = fmul float %449, %113
>  %467 = fadd float %466, %459
>  %468 = fmul float %449, %114
>  %469 = fadd float %468, %461
>  %470 = fmul float %182, %115
>  %471 = fadd float %470, %463
>  %472 = fmul float %182, %116
>  %473 = fadd float %472, %465
>  %474 = fmul float %182, %117
>  %475 = fadd float %474, %467
>  %476 = fmul float %182, %118
>  %477 = fadd float %476, %469
>  %478 = fmul float %186, %119
>  %479 = fmul float %186, %120
>  %480 = fmul float %186, %121
>  %481 = fmul float %186, %122
>  %482 = fmul float %187, %123
>  %483 = fadd float %482, %478
>  %484 = fmul float %187, %124
>  %485 = fadd float %484, %479
>  %486 = fmul float %187, %125
>  %487 = fadd float %486, %480
>  %488 = fmul float %187, %126
>  %489 = fadd float %488, %481
>  %490 = fmul float %188, %127
>  %491 = fadd float %490, %483
>  %492 = fmul float %188, %128
>  %493 = fadd float %492, %485
>  %494 = fmul float %188, %129
>  %495 = fadd float %494, %487
>  %496 = fmul float %188, %130
>  %497 = fadd float %496, %489
>  %498 = fmul float %189, %131
>  %499 = fadd float %498, %491
>  %500 = fmul float %189, %132
>  %501 = fadd float %500, %493
>  %502 = fmul float %189, %133
>  %503 = fadd float %502, %495
>  %504 = fmul float %189, %134
>  %505 = fadd float %504, %497
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %356, float %357, float %358, float %252)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %359, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %370, float %373, float %376, float %157)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %398, float %400, float %402, float %404)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %168, float %169, float %170, float %171)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %426, float %428, float %430, float %432)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %471, float %473, float %475, float %477)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %499, float %501, float %503, float %505)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %211, float %213, float %215, float %217)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], FOG
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP4 TEMP[0], IN[0], CONST[6]
>  5: ABS OUT[1].x, TEMP[0]
>  6: MOV OUT[1].yzw, IMM[0].xxxy
>  7: MOV OUT[2], IN[1]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = fmul float %34, %11
>  %46 = fmul float %34, %12
>  %47 = fmul float %34, %13
>  %48 = fmul float %34, %14
>  %49 = fmul float %35, %15
>  %50 = fadd float %49, %45
>  %51 = fmul float %35, %16
>  %52 = fadd float %51, %46
>  %53 = fmul float %35, %17
>  %54 = fadd float %53, %47
>  %55 = fmul float %35, %18
>  %56 = fadd float %55, %48
>  %57 = fmul float %36, %19
>  %58 = fadd float %57, %50
>  %59 = fmul float %36, %20
>  %60 = fadd float %59, %52
>  %61 = fmul float %36, %21
>  %62 = fadd float %61, %54
>  %63 = fmul float %36, %22
>  %64 = fadd float %63, %56
>  %65 = fmul float %37, %23
>  %66 = fadd float %65, %58
>  %67 = fmul float %37, %24
>  %68 = fadd float %67, %60
>  %69 = fmul float %37, %25
>  %70 = fadd float %69, %62
>  %71 = fmul float %37, %26
>  %72 = fadd float %71, %64
>  %73 = fmul float %34, %27
>  %74 = fmul float %35, %28
>  %75 = fadd float %73, %74
>  %76 = fmul float %36, %29
>  %77 = fadd float %75, %76
>  %78 = fmul float %37, %30
>  %79 = fadd float %77, %78
>  %80 = call float @fabs(float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %80, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %41, float %42, float %43, float %44)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %66, float %68, float %70, float %72)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800020f
>06070705
>c0820704
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL OUT[4], GENERIC[2]
>DCL CONST[0..37]
>DCL TEMP[0..10]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: DP3 TEMP[8], -TEMP[5], CONST[25]
> 63: SLT TEMP[9], CONST[25].wwww, TEMP[8]
> 64: POW TEMP[8], TEMP[8], CONST[24].wwww
> 65: MUL TEMP[10], TEMP[9], TEMP[8]
> 66: RCP TEMP[7].yz, TEMP[7]
> 67: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 68: DP3 TEMP[7], CONST[24], TEMP[7]
> 69: RCP TEMP[7], TEMP[7]
> 70: MUL TEMP[10], TEMP[7], TEMP[10]
> 71: SUB TEMP[7], TEMP[5], TEMP[6]
> 72: DP3 TEMP[8].x, TEMP[7], TEMP[7]
> 73: RSQ TEMP[8].x, |TEMP[8]|
> 74: MUL TEMP[7], TEMP[7], TEMP[8].xxxx
> 75: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 76: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 77: LIT TEMP[1], TEMP[2]
> 78: MUL TEMP[1], TEMP[1], TEMP[10]
> 79: MAD TEMP[3], TEMP[1].xxxx, CONST[26], TEMP[3]
> 80: MAD TEMP[3], TEMP[1].yyyy, CONST[27], TEMP[3]
> 81: MAD TEMP[3], TEMP[1].zzzz, CONST[28], TEMP[3]
> 82: SUB TEMP[5], CONST[29], TEMP[6]
> 83: DP3 TEMP[7].x, TEMP[5], TEMP[5]
> 84: RSQ TEMP[7].x, |TEMP[7]|
> 85: MUL TEMP[5], TEMP[5], TEMP[7].xxxx
> 86: DP3 TEMP[2].x, TEMP[0], CONST[29]
> 87: DP3 TEMP[2].y, TEMP[0], TEMP[5]
> 88: LIT TEMP[1], TEMP[2]
> 89: ADD TEMP[3], CONST[31], TEMP[3]
> 90: MAD TEMP[3], TEMP[1].yyyy, CONST[32], TEMP[3]
> 91: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[33], TEMP[3]
> 92: MOV OUT[2], IN[2]
> 93: DP3 TEMP[2], TEMP[0], TEMP[6]
> 94: ADD TEMP[2], TEMP[2], TEMP[2]
> 95: MAD TEMP[1].xyz, -TEMP[2], TEMP[0], TEMP[6]
> 96: MOV TEMP[1].w, IN[3]
> 97: MUL TEMP[2], TEMP[1].xxxx, CONST[34]
> 98: MAD TEMP[2], TEMP[1].yyyy, CONST[35], TEMP[2]
> 99: MAD TEMP[2], TEMP[1].zzzz, CONST[36], TEMP[2]
>100: MAD OUT[3], TEMP[1].wwww, CONST[37], TEMP[2]
>101: MOV OUT[4], IN[4]
>102: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 528)
>  %113 = call float @llvm.SI.load.const(<16 x i8> %10, i32 532)
>  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 536)
>  %115 = call float @llvm.SI.load.const(<16 x i8> %10, i32 544)
>  %116 = call float @llvm.SI.load.const(<16 x i8> %10, i32 548)
>  %117 = call float @llvm.SI.load.const(<16 x i8> %10, i32 552)
>  %118 = call float @llvm.SI.load.const(<16 x i8> %10, i32 556)
>  %119 = call float @llvm.SI.load.const(<16 x i8> %10, i32 560)
>  %120 = call float @llvm.SI.load.const(<16 x i8> %10, i32 564)
>  %121 = call float @llvm.SI.load.const(<16 x i8> %10, i32 568)
>  %122 = call float @llvm.SI.load.const(<16 x i8> %10, i32 572)
>  %123 = call float @llvm.SI.load.const(<16 x i8> %10, i32 576)
>  %124 = call float @llvm.SI.load.const(<16 x i8> %10, i32 580)
>  %125 = call float @llvm.SI.load.const(<16 x i8> %10, i32 584)
>  %126 = call float @llvm.SI.load.const(<16 x i8> %10, i32 588)
>  %127 = call float @llvm.SI.load.const(<16 x i8> %10, i32 592)
>  %128 = call float @llvm.SI.load.const(<16 x i8> %10, i32 596)
>  %129 = call float @llvm.SI.load.const(<16 x i8> %10, i32 600)
>  %130 = call float @llvm.SI.load.const(<16 x i8> %10, i32 604)
>  %131 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %132 = load <16 x i8> addrspace(2)* %131, !tbaa !0
>  %133 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %132, i32 0, i32 %5)
>  %134 = extractelement <4 x float> %133, i32 0
>  %135 = extractelement <4 x float> %133, i32 1
>  %136 = extractelement <4 x float> %133, i32 2
>  %137 = extractelement <4 x float> %133, i32 3
>  %138 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %139 = load <16 x i8> addrspace(2)* %138, !tbaa !0
>  %140 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %139, i32 0, i32 %5)
>  %141 = extractelement <4 x float> %140, i32 0
>  %142 = extractelement <4 x float> %140, i32 1
>  %143 = extractelement <4 x float> %140, i32 2
>  %144 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %145 = load <16 x i8> addrspace(2)* %144, !tbaa !0
>  %146 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %145, i32 0, i32 %5)
>  %147 = extractelement <4 x float> %146, i32 0
>  %148 = extractelement <4 x float> %146, i32 1
>  %149 = extractelement <4 x float> %146, i32 2
>  %150 = extractelement <4 x float> %146, i32 3
>  %151 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %152 = load <16 x i8> addrspace(2)* %151, !tbaa !0
>  %153 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %152, i32 0, i32 %5)
>  %154 = extractelement <4 x float> %153, i32 3
>  %155 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %156 = load <16 x i8> addrspace(2)* %155, !tbaa !0
>  %157 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %156, i32 0, i32 %5)
>  %158 = extractelement <4 x float> %157, i32 0
>  %159 = extractelement <4 x float> %157, i32 1
>  %160 = extractelement <4 x float> %157, i32 2
>  %161 = extractelement <4 x float> %157, i32 3
>  %162 = fmul float %134, %11
>  %163 = fmul float %134, %12
>  %164 = fmul float %134, %13
>  %165 = fmul float %134, %14
>  %166 = fmul float %135, %15
>  %167 = fadd float %166, %162
>  %168 = fmul float %135, %16
>  %169 = fadd float %168, %163
>  %170 = fmul float %135, %17
>  %171 = fadd float %170, %164
>  %172 = fmul float %135, %18
>  %173 = fadd float %172, %165
>  %174 = fmul float %136, %19
>  %175 = fadd float %174, %167
>  %176 = fmul float %136, %20
>  %177 = fadd float %176, %169
>  %178 = fmul float %136, %21
>  %179 = fadd float %178, %171
>  %180 = fmul float %136, %22
>  %181 = fadd float %180, %173
>  %182 = fmul float %137, %23
>  %183 = fadd float %182, %175
>  %184 = fmul float %137, %24
>  %185 = fadd float %184, %177
>  %186 = fmul float %137, %25
>  %187 = fadd float %186, %179
>  %188 = fmul float %137, %26
>  %189 = fadd float %188, %181
>  %190 = fmul float %141, %27
>  %191 = fmul float %142, %28
>  %192 = fadd float %191, %190
>  %193 = fmul float %143, %29
>  %194 = fadd float %192, %193
>  %195 = fmul float %141, %30
>  %196 = fmul float %142, %31
>  %197 = fadd float %196, %195
>  %198 = fmul float %143, %32
>  %199 = fadd float %197, %198
>  %200 = fmul float %141, %33
>  %201 = fmul float %142, %34
>  %202 = fadd float %201, %200
>  %203 = fmul float %143, %35
>  %204 = fadd float %202, %203
>  %205 = fmul float %194, %194
>  %206 = fmul float %199, %199
>  %207 = fadd float %206, %205
>  %208 = fmul float %204, %204
>  %209 = fadd float %207, %208
>  %210 = call float @fabs(float %209)
>  %211 = call float @llvm.AMDGPU.rsq(float %210)
>  %212 = fmul float %194, %211
>  %213 = fmul float %199, %211
>  %214 = fmul float %204, %211
>  %215 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %216 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %217 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %218 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %219 = fmul float %134, %44
>  %220 = fmul float %134, %45
>  %221 = fmul float %134, %46
>  %222 = fmul float %135, %47
>  %223 = fadd float %222, %219
>  %224 = fmul float %135, %48
>  %225 = fadd float %224, %220
>  %226 = fmul float %135, %49
>  %227 = fadd float %226, %221
>  %228 = fmul float %136, %50
>  %229 = fadd float %228, %223
>  %230 = fmul float %136, %51
>  %231 = fadd float %230, %225
>  %232 = fmul float %136, %52
>  %233 = fadd float %232, %227
>  %234 = fmul float %137, %53
>  %235 = fadd float %234, %229
>  %236 = fmul float %137, %54
>  %237 = fadd float %236, %231
>  %238 = fmul float %137, %55
>  %239 = fadd float %238, %233
>  %240 = fsub float %41, %235
>  %241 = fsub float %42, %237
>  %242 = fsub float %43, %239
>  %243 = fmul float %240, %240
>  %244 = fmul float %241, %241
>  %245 = fadd float %244, %243
>  %246 = fmul float %242, %242
>  %247 = fadd float %245, %246
>  %248 = call float @fabs(float %247)
>  %249 = call float @llvm.AMDGPU.rsq(float %248)
>  %250 = fmul float %240, %249
>  %251 = fmul float %241, %249
>  %252 = fmul float %242, %249
>  %253 = fdiv float 1.000000e+00, %249
>  %254 = fmul float %249, %253
>  %255 = fmul float %253, %253
>  %256 = fmul float %56, %254
>  %257 = fmul float %57, %253
>  %258 = fadd float %257, %256
>  %259 = fmul float %58, %255
>  %260 = fadd float %258, %259
>  %261 = fdiv float 1.000000e+00, %260
>  %262 = fmul float %235, %235
>  %263 = fmul float %237, %237
>  %264 = fadd float %263, %262
>  %265 = fmul float %239, %239
>  %266 = fadd float %264, %265
>  %267 = call float @fabs(float %266)
>  %268 = call float @llvm.AMDGPU.rsq(float %267)
>  %269 = fmul float %235, %268
>  %270 = fmul float %237, %268
>  %271 = fmul float %239, %268
>  %272 = fsub float %250, %269
>  %273 = fsub float %251, %270
>  %274 = fsub float %252, %271
>  %275 = fmul float %272, %272
>  %276 = fmul float %273, %273
>  %277 = fadd float %276, %275
>  %278 = fmul float %274, %274
>  %279 = fadd float %277, %278
>  %280 = call float @fabs(float %279)
>  %281 = call float @llvm.AMDGPU.rsq(float %280)
>  %282 = fmul float %272, %281
>  %283 = fmul float %273, %281
>  %284 = fmul float %274, %281
>  %285 = fmul float %212, %250
>  %286 = fmul float %213, %251
>  %287 = fadd float %286, %285
>  %288 = fmul float %214, %252
>  %289 = fadd float %287, %288
>  %290 = fmul float %212, %282
>  %291 = fmul float %213, %283
>  %292 = fadd float %291, %290
>  %293 = fmul float %214, %284
>  %294 = fadd float %292, %293
>  %295 = fcmp uge float %289, 0.000000e+00
>  %296 = select i1 %295, float %289, float 0.000000e+00
>  %297 = fcmp uge float %294, 0.000000e+00
>  %298 = select i1 %297, float %294, float 0.000000e+00
>  %299 = call float @llvm.pow.f32(float %298, float %36)
>  %300 = call float @llvm.AMDGPU.cndlt(float %289, float 0.000000e+00, float %299)
>  %301 = fmul float 1.000000e+00, %261
>  %302 = fmul float %296, %261
>  %303 = fmul float %300, %261
>  %304 = fmul float %301, %59
>  %305 = fadd float %304, %37
>  %306 = fmul float %301, %60
>  %307 = fadd float %306, %38
>  %308 = fmul float %301, %61
>  %309 = fadd float %308, %39
>  %310 = fmul float %302, %62
>  %311 = fadd float %310, %305
>  %312 = fmul float %302, %63
>  %313 = fadd float %312, %307
>  %314 = fmul float %302, %64
>  %315 = fadd float %314, %309
>  %316 = fmul float %303, %65
>  %317 = fadd float %316, %311
>  %318 = fmul float %303, %66
>  %319 = fadd float %318, %313
>  %320 = fmul float %303, %67
>  %321 = fadd float %320, %315
>  %322 = fsub float %68, %235
>  %323 = fsub float %69, %237
>  %324 = fsub float %70, %239
>  %325 = fmul float %322, %322
>  %326 = fmul float %323, %323
>  %327 = fadd float %326, %325
>  %328 = fmul float %324, %324
>  %329 = fadd float %327, %328
>  %330 = call float @fabs(float %329)
>  %331 = call float @llvm.AMDGPU.rsq(float %330)
>  %332 = fmul float %322, %331
>  %333 = fmul float %323, %331
>  %334 = fmul float %324, %331
>  %335 = fdiv float 1.000000e+00, %331
>  %336 = fmul float %331, %335
>  %337 = fmul float %335, %335
>  %338 = fmul float %71, %336
>  %339 = fmul float %72, %335
>  %340 = fadd float %339, %338
>  %341 = fmul float %73, %337
>  %342 = fadd float %340, %341
>  %343 = fdiv float 1.000000e+00, %342
>  %344 = fsub float %332, %269
>  %345 = fsub float %333, %270
>  %346 = fsub float %334, %271
>  %347 = fmul float %344, %344
>  %348 = fmul float %345, %345
>  %349 = fadd float %348, %347
>  %350 = fmul float %346, %346
>  %351 = fadd float %349, %350
>  %352 = call float @fabs(float %351)
>  %353 = call float @llvm.AMDGPU.rsq(float %352)
>  %354 = fmul float %344, %353
>  %355 = fmul float %345, %353
>  %356 = fmul float %346, %353
>  %357 = fmul float %212, %332
>  %358 = fmul float %213, %333
>  %359 = fadd float %358, %357
>  %360 = fmul float %214, %334
>  %361 = fadd float %359, %360
>  %362 = fmul float %212, %354
>  %363 = fmul float %213, %355
>  %364 = fadd float %363, %362
>  %365 = fmul float %214, %356
>  %366 = fadd float %364, %365
>  %367 = fcmp uge float %361, 0.000000e+00
>  %368 = select i1 %367, float %361, float 0.000000e+00
>  %369 = fcmp uge float %366, 0.000000e+00
>  %370 = select i1 %369, float %366, float 0.000000e+00
>  %371 = call float @llvm.pow.f32(float %370, float %36)
>  %372 = call float @llvm.AMDGPU.cndlt(float %361, float 0.000000e+00, float %371)
>  %373 = fmul float 1.000000e+00, %343
>  %374 = fmul float %368, %343
>  %375 = fmul float %372, %343
>  %376 = fmul float %373, %74
>  %377 = fadd float %376, %317
>  %378 = fmul float %373, %75
>  %379 = fadd float %378, %319
>  %380 = fmul float %373, %76
>  %381 = fadd float %380, %321
>  %382 = fmul float %374, %77
>  %383 = fadd float %382, %377
>  %384 = fmul float %374, %78
>  %385 = fadd float %384, %379
>  %386 = fmul float %374, %79
>  %387 = fadd float %386, %381
>  %388 = fmul float %375, %80
>  %389 = fadd float %388, %383
>  %390 = fmul float %375, %81
>  %391 = fadd float %390, %385
>  %392 = fmul float %375, %82
>  %393 = fadd float %392, %387
>  %394 = fsub float %83, %235
>  %395 = fsub float %84, %237
>  %396 = fsub float %85, %239
>  %397 = fmul float %394, %394
>  %398 = fmul float %395, %395
>  %399 = fadd float %398, %397
>  %400 = fmul float %396, %396
>  %401 = fadd float %399, %400
>  %402 = call float @fabs(float %401)
>  %403 = call float @llvm.AMDGPU.rsq(float %402)
>  %404 = fmul float %394, %403
>  %405 = fmul float %395, %403
>  %406 = fmul float %396, %403
>  %407 = fsub float -0.000000e+00, %404
>  %408 = fsub float -0.000000e+00, %405
>  %409 = fsub float -0.000000e+00, %406
>  %410 = fmul float %407, %90
>  %411 = fmul float %408, %91
>  %412 = fadd float %411, %410
>  %413 = fmul float %409, %92
>  %414 = fadd float %412, %413
>  %415 = fcmp olt float %93, %414
>  %416 = select i1 %415, float 1.000000e+00, float 0.000000e+00
>  %417 = fcmp olt float %93, %414
>  %418 = select i1 %417, float 1.000000e+00, float 0.000000e+00
>  %419 = fcmp olt float %93, %414
>  %420 = select i1 %419, float 1.000000e+00, float 0.000000e+00
>  %421 = call float @llvm.pow.f32(float %414, float %89)
>  %422 = fmul float %416, %421
>  %423 = fmul float %418, %421
>  %424 = fmul float %420, %421
>  %425 = fdiv float 1.000000e+00, %403
>  %426 = fmul float %403, %425
>  %427 = fmul float %425, %425
>  %428 = fmul float %86, %426
>  %429 = fmul float %87, %425
>  %430 = fadd float %429, %428
>  %431 = fmul float %88, %427
>  %432 = fadd float %430, %431
>  %433 = fdiv float 1.000000e+00, %432
>  %434 = fmul float %433, %422
>  %435 = fmul float %433, %423
>  %436 = fmul float %433, %424
>  %437 = fsub float %404, %269
>  %438 = fsub float %405, %270
>  %439 = fsub float %406, %271
>  %440 = fmul float %437, %437
>  %441 = fmul float %438, %438
>  %442 = fadd float %441, %440
>  %443 = fmul float %439, %439
>  %444 = fadd float %442, %443
>  %445 = call float @fabs(float %444)
>  %446 = call float @llvm.AMDGPU.rsq(float %445)
>  %447 = fmul float %437, %446
>  %448 = fmul float %438, %446
>  %449 = fmul float %439, %446
>  %450 = fmul float %212, %404
>  %451 = fmul float %213, %405
>  %452 = fadd float %451, %450
>  %453 = fmul float %214, %406
>  %454 = fadd float %452, %453
>  %455 = fmul float %212, %447
>  %456 = fmul float %213, %448
>  %457 = fadd float %456, %455
>  %458 = fmul float %214, %449
>  %459 = fadd float %457, %458
>  %460 = fcmp uge float %454, 0.000000e+00
>  %461 = select i1 %460, float %454, float 0.000000e+00
>  %462 = fcmp uge float %459, 0.000000e+00
>  %463 = select i1 %462, float %459, float 0.000000e+00
>  %464 = call float @llvm.pow.f32(float %463, float %36)
>  %465 = call float @llvm.AMDGPU.cndlt(float %454, float 0.000000e+00, float %464)
>  %466 = fmul float 1.000000e+00, %434
>  %467 = fmul float %461, %435
>  %468 = fmul float %465, %436
>  %469 = fmul float %466, %94
>  %470 = fadd float %469, %389
>  %471 = fmul float %466, %95
>  %472 = fadd float %471, %391
>  %473 = fmul float %466, %96
>  %474 = fadd float %473, %393
>  %475 = fmul float %467, %97
>  %476 = fadd float %475, %470
>  %477 = fmul float %467, %98
>  %478 = fadd float %477, %472
>  %479 = fmul float %467, %99
>  %480 = fadd float %479, %474
>  %481 = fmul float %468, %100
>  %482 = fadd float %481, %476
>  %483 = fmul float %468, %101
>  %484 = fadd float %483, %478
>  %485 = fmul float %468, %102
>  %486 = fadd float %485, %480
>  %487 = fsub float %103, %269
>  %488 = fsub float %104, %270
>  %489 = fsub float %105, %271
>  %490 = fmul float %487, %487
>  %491 = fmul float %488, %488
>  %492 = fadd float %491, %490
>  %493 = fmul float %489, %489
>  %494 = fadd float %492, %493
>  %495 = call float @fabs(float %494)
>  %496 = call float @llvm.AMDGPU.rsq(float %495)
>  %497 = fmul float %487, %496
>  %498 = fmul float %488, %496
>  %499 = fmul float %489, %496
>  %500 = fmul float %212, %103
>  %501 = fmul float %213, %104
>  %502 = fadd float %501, %500
>  %503 = fmul float %214, %105
>  %504 = fadd float %502, %503
>  %505 = fmul float %212, %497
>  %506 = fmul float %213, %498
>  %507 = fadd float %506, %505
>  %508 = fmul float %214, %499
>  %509 = fadd float %507, %508
>  %510 = fcmp uge float %504, 0.000000e+00
>  %511 = select i1 %510, float %504, float 0.000000e+00
>  %512 = fcmp uge float %509, 0.000000e+00
>  %513 = select i1 %512, float %509, float 0.000000e+00
>  %514 = call float @llvm.pow.f32(float %513, float %36)
>  %515 = call float @llvm.AMDGPU.cndlt(float %504, float 0.000000e+00, float %514)
>  %516 = fadd float %106, %482
>  %517 = fadd float %107, %484
>  %518 = fadd float %108, %486
>  %519 = fmul float %511, %109
>  %520 = fadd float %519, %516
>  %521 = fmul float %511, %110
>  %522 = fadd float %521, %517
>  %523 = fmul float %511, %111
>  %524 = fadd float %523, %518
>  %525 = fmul float %515, %112
>  %526 = fadd float %525, %520
>  %527 = fmul float %515, %113
>  %528 = fadd float %527, %522
>  %529 = fmul float %515, %114
>  %530 = fadd float %529, %524
>  %531 = call float @llvm.AMDIL.clamp.(float %526, float 0.000000e+00, float 1.000000e+00)
>  %532 = call float @llvm.AMDIL.clamp.(float %528, float 0.000000e+00, float 1.000000e+00)
>  %533 = call float @llvm.AMDIL.clamp.(float %530, float 0.000000e+00, float 1.000000e+00)
>  %534 = fmul float %212, %269
>  %535 = fmul float %213, %270
>  %536 = fadd float %535, %534
>  %537 = fmul float %214, %271
>  %538 = fadd float %536, %537
>  %539 = fadd float %538, %538
>  %540 = fadd float %538, %538
>  %541 = fadd float %538, %538
>  %542 = fsub float -0.000000e+00, %539
>  %543 = fmul float %542, %212
>  %544 = fadd float %543, %269
>  %545 = fsub float -0.000000e+00, %540
>  %546 = fmul float %545, %213
>  %547 = fadd float %546, %270
>  %548 = fsub float -0.000000e+00, %541
>  %549 = fmul float %548, %214
>  %550 = fadd float %549, %271
>  %551 = fmul float %544, %115
>  %552 = fmul float %544, %116
>  %553 = fmul float %544, %117
>  %554 = fmul float %544, %118
>  %555 = fmul float %547, %119
>  %556 = fadd float %555, %551
>  %557 = fmul float %547, %120
>  %558 = fadd float %557, %552
>  %559 = fmul float %547, %121
>  %560 = fadd float %559, %553
>  %561 = fmul float %547, %122
>  %562 = fadd float %561, %554
>  %563 = fmul float %550, %123
>  %564 = fadd float %563, %556
>  %565 = fmul float %550, %124
>  %566 = fadd float %565, %558
>  %567 = fmul float %550, %125
>  %568 = fadd float %567, %560
>  %569 = fmul float %550, %126
>  %570 = fadd float %569, %562
>  %571 = fmul float %154, %127
>  %572 = fadd float %571, %564
>  %573 = fmul float %154, %128
>  %574 = fadd float %573, %566
>  %575 = fmul float %154, %129
>  %576 = fadd float %575, %568
>  %577 = fmul float %154, %130
>  %578 = fadd float %577, %570
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %531, float %532, float %533, float %218)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %147, float %148, float %149, float %150)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %572, float %574, float %576, float %578)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %158, float %159, float %160, float %161)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %183, float %185, float %187, float %189)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020129
>bf8c007f
>100a0204
>c202012d
>bf8c007f
>d2820005
>04140902
>c2020131
>bf8c007f
>d2820005
>04140903
>c2020135
>bf8c007f
>d2820010
>04140904
>c2020128
>bf8c007f
>100a0204
>c202012c
>bf8c007f
>d2820005
>04140902
>c2020130
>bf8c007f
>d2820005
>04140903
>c2020134
>bf8c007f
>d2820011
>04140904
>100a2311
>d2820005
>04162110
>c202012a
>bf8c007f
>100c0204
>c202012e
>bf8c007f
>d2820006
>04180902
>c2020132
>bf8c007f
>d2820006
>04180903
>c2020136
>bf8c007f
>d2820012
>04180904
>d2820005
>04162512
>d2060105
>02010105
>7e0c5b05
>100a0d10
>c2020125
>bf8c007f
>080e2004
>c2020124
>bf8c007f
>08142204
>1010150a
>d2820009
>04220f07
>c2020126
>bf8c007f
>08102404
>d2820009
>04261108
>d2060109
>02010109
>7e165b09
>10181707
>08120b0c
>100e0d11
>101a170a
>08140f0d
>101c150a
>d282000f
>043a1309
>100c0d12
>101c1708
>08100d0e
>d282000f
>043e1108
>d206010f
>0201010f
>7e1e5b0f
>10261f09
>10141f0a
>c0840704
>bf8c007f
>e00c2000
>80021400
>c2020114
>bf8c0070
>10122804
>c2020115
>bf8c007f
>d2820009
>04240915
>c2020116
>bf8c007f
>d2820018
>04240916
>c2020110
>bf8c007f
>10122804
>c2020111
>bf8c007f
>d2820009
>04240915
>c2020112
>bf8c007f
>d2820009
>04240916
>10321309
>d2820019
>04663118
>c2020118
>bf8c007f
>10342804
>c2020119
>bf8c007f
>d282001a
>04680915
>c202011a
>bf8c007f
>d2820014
>04680916
>d2820015
>04662914
>d2060115
>02010115
>7e2a5b15
>10122b09
>102c1509
>10142b18
>d2820013
>045a270a
>101e1f08
>10102b14
>d282000f
>044e1f08
>d00c0004
>0201010f
>d200000f
>00121e80
>7e1e4f0f
>c202011c
>bf8c007f
>0e1e1e04
>7e1e4b0f
>101a1b09
>d282000c
>0436190a
>d282000d
>04321d08
>d0080008
>02021a80
>d200000e
>0021010f
>7e18550b
>1016190b
>c2028138
>bf8c007f
>10161605
>c2028139
>bf8c007f
>d282000b
>042e1805
>1018190c
>c202813a
>bf8c007f
>d282000b
>042e1805
>7e18550b
>1016190e
>d00c0008
>0201010d
>d200000d
>00221a80
>101a190d
>c202813e
>c2040122
>bf8c007f
>7e1c0208
>d282000e
>04380b0c
>c2028142
>bf8c007f
>d282000e
>04380b0d
>c2028146
>bf8c007f
>d2820013
>04380b0b
>c2028149
>bf8c007f
>081e2005
>c2028148
>bf8c007f
>08282205
>101c2914
>d282000e
>043a1f0f
>c202814a
>bf8c007f
>082a2405
>d282000e
>043a2b15
>d206010e
>0201010e
>7e2c5b0e
>7e1c5516
>102e1d16
>c202814c
>bf8c007f
>102e2e05
>c202814d
>bf8c007f
>d2820017
>045e1c05
>101c1d0e
>c202814e
>bf8c007f
>d282000e
>045e1c05
>7e1c550e
>c2028152
>bf8c007f
>d2820018
>044c0b0e
>102e2d14
>10262f09
>10322d0f
>d282000f
>044e330a
>102a2d15
>d2820013
>043e2b08
>d00c0008
>02010113
>d200000f
>00222680
>101e1d0f
>c2028156
>bf8c007f
>d2820014
>04600b0f
>082c0b19
>082e0f17
>10302f17
>d2820018
>04622d16
>082a0d15
>d2820018
>04622b15
>d2060118
>02010118
>7e305b18
>102c3116
>102e3117
>102e2f09
>d2820016
>045e2d0a
>102a3115
>d2820015
>045a2b08
>d00c0008
>02010115
>d2000015
>00222a80
>7e2a4f15
>0e2a2a04
>7e2a4b15
>d0080008
>02022680
>d2000013
>00210115
>10261d13
>c202815a
>bf8c007f
>d2820014
>04500b13
>c202815d
>bf8c007f
>082a2005
>c202815c
>bf8c007f
>082c2205
>10202d16
>d2820010
>04422b15
>c202815e
>bf8c007f
>08222405
>d2820010
>04422311
>d2060110
>02010110
>7e205b10
>10242116
>c2028164
>bf8c007f
>102c2405
>102a2115
>d2060017
>22010115
>c2028165
>bf8c007f
>102e2e05
>082e2d17
>102c2111
>c2028166
>bf8c007f
>10222c05
>082e2317
>c2028167
>bf8c007f
>d0020008
>02022e05
>d2000011
>0021e480
>7e2e4f17
>c2028163
>bf8c007f
>0e2e2e05
>7e2e4b17
>10222f11
>7e2e5510
>10202f10
>c2028160
>bf8c007f
>10202005
>c2028161
>bf8c007f
>d2820010
>04422e05
>102e2f17
>c2028162
>bf8c007f
>d2820010
>04422e05
>7e205510
>10202310
>c202816a
>bf8c007f
>d2820017
>04500b10
>10222509
>d2820011
>04462b0a
>d2820014
>04462d08
>d00c0008
>02010114
>d2000011
>00222880
>10222111
>c202816e
>bf8c007f
>d2820017
>045c0b11
>082a0b15
>08240f12
>10302512
>d2820018
>04622b15
>082c0d16
>d2820018
>04622d16
>d2060118
>02010118
>7e305b18
>102a3115
>10243112
>10242509
>d2820012
>044a2b0a
>102a3116
>d2820012
>044a2b08
>d00c0008
>02010112
>d2000012
>00222480
>7e244f12
>0e242404
>7e244b12
>d0080008
>02022880
>d2000012
>00210112
>10242112
>c2028172
>bf8c007f
>d2820014
>045c0b12
>c202817e
>bf8c007f
>062c2805
>c2028174
>bf8c007f
>10281205
>c2048175
>bf8c007f
>d2820014
>0450130a
>c2040176
>bf8c007f
>d2820015
>04501108
>d00c000a
>02010115
>d2000014
>002a2a80
>c2050182
>bf8c007f
>d2820017
>04581514
>082c0a09
>08300e05
>10323118
>d282001a
>04662d16
>08320c08
>d282001a
>046a3319
>d206011a
>0201011a
>7e345b1a
>102c3516
>10303518
>10303109
>d2820016
>04622d0a
>10303519
>d2820016
>045a3108
>d00c0008
>02010116
>d2000016
>00222c80
>7e2c4f16
>0e2c2c04
>7e2c4b16
>d0080004
>02022a80
>d2000016
>00110116
>c2020186
>bf8c007f
>d2820015
>045c0916
>d2060815
>02010115
>c202013d
>c2028121
>bf8c007f
>7e2e0205
>d2820017
>045c090c
>c2020141
>bf8c007f
>d2820017
>045c090d
>c2020145
>bf8c007f
>d2820017
>045c090b
>c2020151
>bf8c007f
>d2820017
>045c090e
>c2020155
>bf8c007f
>d2820017
>045c090f
>c2020159
>bf8c007f
>d2820017
>045c0913
>c2020169
>bf8c007f
>d2820017
>045c0910
>c202016d
>bf8c007f
>d2820017
>045c0911
>c2020171
>bf8c007f
>d2820017
>045c0912
>c202017d
>bf8c007f
>062e2e04
>c2020181
>bf8c007f
>d2820017
>045c0914
>c2020185
>bf8c007f
>d2820017
>045c0916
>d2060817
>02010117
>c202013c
>c2028120
>bf8c007f
>7e300205
>d282000c
>0460090c
>c2020140
>bf8c007f
>d282000c
>0430090d
>c2020144
>bf8c007f
>d282000b
>0430090b
>c2020150
>bf8c007f
>d282000b
>042c090e
>c2020154
>bf8c007f
>d282000b
>042c090f
>c2020158
>bf8c007f
>d282000b
>042c0913
>c2020168
>bf8c007f
>d282000b
>042c0910
>c202016c
>bf8c007f
>d282000b
>042c0911
>c2020170
>bf8c007f
>d282000b
>042c0912
>c202017c
>bf8c007f
>06161604
>c2020180
>bf8c007f
>d282000b
>042c0914
>c2020184
>bf8c007f
>d282000b
>042c0916
>d206080b
>0201010b
>c2020123
>bf8c007f
>d206080c
>02010004
>f800020f
>0c15170b
>c0840708
>bf8c000f
>e00c2000
>80020b00
>bf8c0770
>f800021f
>0e0d0c0b
>bf8c070f
>10160f09
>d282000b
>042e0b0a
>d282000b
>042e0d08
>0616170b
>1014150b
>080a1505
>1012130b
>080e1307
>c202018b
>bf8c007f
>10120e04
>c202018f
>bf8c007f
>d2820009
>04240905
>1010110b
>080c1106
>c2020193
>bf8c007f
>d282000c
>04240906
>c084070c
>bf8c007f
>e00c2000
>80020800
>c2020197
>bf8c0070
>d282000c
>0430090b
>c202018a
>bf8c007f
>101a0e04
>c202018e
>bf8c007f
>d282000d
>04340905
>c2020192
>bf8c007f
>d282000d
>04340906
>c2020196
>bf8c007f
>d282000d
>0434090b
>c2020189
>bf8c007f
>101c0e04
>c202018d
>bf8c007f
>d282000e
>04380905
>c2020191
>bf8c007f
>d282000e
>04380906
>c2020195
>bf8c007f
>d282000e
>0438090b
>c2020188
>bf8c007f
>100e0e04
>c202018c
>bf8c007f
>d2820005
>041c0905
>c2020190
>bf8c007f
>d2820005
>04140906
>c2020194
>bf8c007f
>d2820005
>0414090b
>f800022f
>0c0d0e05
>c0820710
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800023f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..33]
>DCL TEMP[0..10]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: DP3 TEMP[8], -TEMP[5], CONST[25]
> 63: SLT TEMP[9], CONST[25].wwww, TEMP[8]
> 64: POW TEMP[8], TEMP[8], CONST[24].wwww
> 65: MUL TEMP[10], TEMP[9], TEMP[8]
> 66: RCP TEMP[7].yz, TEMP[7]
> 67: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 68: DP3 TEMP[7], CONST[24], TEMP[7]
> 69: RCP TEMP[7], TEMP[7]
> 70: MUL TEMP[10], TEMP[7], TEMP[10]
> 71: SUB TEMP[7], TEMP[5], TEMP[6]
> 72: DP3 TEMP[8].x, TEMP[7], TEMP[7]
> 73: RSQ TEMP[8].x, |TEMP[8]|
> 74: MUL TEMP[7], TEMP[7], TEMP[8].xxxx
> 75: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 76: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 77: LIT TEMP[1], TEMP[2]
> 78: MUL TEMP[1], TEMP[1], TEMP[10]
> 79: MAD TEMP[3], TEMP[1].xxxx, CONST[26], TEMP[3]
> 80: MAD TEMP[3], TEMP[1].yyyy, CONST[27], TEMP[3]
> 81: MAD TEMP[3], TEMP[1].zzzz, CONST[28], TEMP[3]
> 82: SUB TEMP[5], CONST[29], TEMP[6]
> 83: DP3 TEMP[7].x, TEMP[5], TEMP[5]
> 84: RSQ TEMP[7].x, |TEMP[7]|
> 85: MUL TEMP[5], TEMP[5], TEMP[7].xxxx
> 86: DP3 TEMP[2].x, TEMP[0], CONST[29]
> 87: DP3 TEMP[2].y, TEMP[0], TEMP[5]
> 88: LIT TEMP[1], TEMP[2]
> 89: ADD TEMP[3], CONST[31], TEMP[3]
> 90: MAD TEMP[3], TEMP[1].yyyy, CONST[32], TEMP[3]
> 91: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[33], TEMP[3]
> 92: MOV OUT[2], IN[2]
> 93: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 528)
>  %113 = call float @llvm.SI.load.const(<16 x i8> %10, i32 532)
>  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 536)
>  %115 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %116 = load <16 x i8> addrspace(2)* %115, !tbaa !0
>  %117 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %116, i32 0, i32 %5)
>  %118 = extractelement <4 x float> %117, i32 0
>  %119 = extractelement <4 x float> %117, i32 1
>  %120 = extractelement <4 x float> %117, i32 2
>  %121 = extractelement <4 x float> %117, i32 3
>  %122 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
>  %124 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %123, i32 0, i32 %5)
>  %125 = extractelement <4 x float> %124, i32 0
>  %126 = extractelement <4 x float> %124, i32 1
>  %127 = extractelement <4 x float> %124, i32 2
>  %128 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %129 = load <16 x i8> addrspace(2)* %128, !tbaa !0
>  %130 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %129, i32 0, i32 %5)
>  %131 = extractelement <4 x float> %130, i32 0
>  %132 = extractelement <4 x float> %130, i32 1
>  %133 = extractelement <4 x float> %130, i32 2
>  %134 = extractelement <4 x float> %130, i32 3
>  %135 = fmul float %118, %11
>  %136 = fmul float %118, %12
>  %137 = fmul float %118, %13
>  %138 = fmul float %118, %14
>  %139 = fmul float %119, %15
>  %140 = fadd float %139, %135
>  %141 = fmul float %119, %16
>  %142 = fadd float %141, %136
>  %143 = fmul float %119, %17
>  %144 = fadd float %143, %137
>  %145 = fmul float %119, %18
>  %146 = fadd float %145, %138
>  %147 = fmul float %120, %19
>  %148 = fadd float %147, %140
>  %149 = fmul float %120, %20
>  %150 = fadd float %149, %142
>  %151 = fmul float %120, %21
>  %152 = fadd float %151, %144
>  %153 = fmul float %120, %22
>  %154 = fadd float %153, %146
>  %155 = fmul float %121, %23
>  %156 = fadd float %155, %148
>  %157 = fmul float %121, %24
>  %158 = fadd float %157, %150
>  %159 = fmul float %121, %25
>  %160 = fadd float %159, %152
>  %161 = fmul float %121, %26
>  %162 = fadd float %161, %154
>  %163 = fmul float %125, %27
>  %164 = fmul float %126, %28
>  %165 = fadd float %164, %163
>  %166 = fmul float %127, %29
>  %167 = fadd float %165, %166
>  %168 = fmul float %125, %30
>  %169 = fmul float %126, %31
>  %170 = fadd float %169, %168
>  %171 = fmul float %127, %32
>  %172 = fadd float %170, %171
>  %173 = fmul float %125, %33
>  %174 = fmul float %126, %34
>  %175 = fadd float %174, %173
>  %176 = fmul float %127, %35
>  %177 = fadd float %175, %176
>  %178 = fmul float %167, %167
>  %179 = fmul float %172, %172
>  %180 = fadd float %179, %178
>  %181 = fmul float %177, %177
>  %182 = fadd float %180, %181
>  %183 = call float @fabs(float %182)
>  %184 = call float @llvm.AMDGPU.rsq(float %183)
>  %185 = fmul float %167, %184
>  %186 = fmul float %172, %184
>  %187 = fmul float %177, %184
>  %188 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %189 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %190 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %191 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %192 = fmul float %118, %44
>  %193 = fmul float %118, %45
>  %194 = fmul float %118, %46
>  %195 = fmul float %119, %47
>  %196 = fadd float %195, %192
>  %197 = fmul float %119, %48
>  %198 = fadd float %197, %193
>  %199 = fmul float %119, %49
>  %200 = fadd float %199, %194
>  %201 = fmul float %120, %50
>  %202 = fadd float %201, %196
>  %203 = fmul float %120, %51
>  %204 = fadd float %203, %198
>  %205 = fmul float %120, %52
>  %206 = fadd float %205, %200
>  %207 = fmul float %121, %53
>  %208 = fadd float %207, %202
>  %209 = fmul float %121, %54
>  %210 = fadd float %209, %204
>  %211 = fmul float %121, %55
>  %212 = fadd float %211, %206
>  %213 = fsub float %41, %208
>  %214 = fsub float %42, %210
>  %215 = fsub float %43, %212
>  %216 = fmul float %213, %213
>  %217 = fmul float %214, %214
>  %218 = fadd float %217, %216
>  %219 = fmul float %215, %215
>  %220 = fadd float %218, %219
>  %221 = call float @fabs(float %220)
>  %222 = call float @llvm.AMDGPU.rsq(float %221)
>  %223 = fmul float %213, %222
>  %224 = fmul float %214, %222
>  %225 = fmul float %215, %222
>  %226 = fdiv float 1.000000e+00, %222
>  %227 = fmul float %222, %226
>  %228 = fmul float %226, %226
>  %229 = fmul float %56, %227
>  %230 = fmul float %57, %226
>  %231 = fadd float %230, %229
>  %232 = fmul float %58, %228
>  %233 = fadd float %231, %232
>  %234 = fdiv float 1.000000e+00, %233
>  %235 = fmul float %208, %208
>  %236 = fmul float %210, %210
>  %237 = fadd float %236, %235
>  %238 = fmul float %212, %212
>  %239 = fadd float %237, %238
>  %240 = call float @fabs(float %239)
>  %241 = call float @llvm.AMDGPU.rsq(float %240)
>  %242 = fmul float %208, %241
>  %243 = fmul float %210, %241
>  %244 = fmul float %212, %241
>  %245 = fsub float %223, %242
>  %246 = fsub float %224, %243
>  %247 = fsub float %225, %244
>  %248 = fmul float %245, %245
>  %249 = fmul float %246, %246
>  %250 = fadd float %249, %248
>  %251 = fmul float %247, %247
>  %252 = fadd float %250, %251
>  %253 = call float @fabs(float %252)
>  %254 = call float @llvm.AMDGPU.rsq(float %253)
>  %255 = fmul float %245, %254
>  %256 = fmul float %246, %254
>  %257 = fmul float %247, %254
>  %258 = fmul float %185, %223
>  %259 = fmul float %186, %224
>  %260 = fadd float %259, %258
>  %261 = fmul float %187, %225
>  %262 = fadd float %260, %261
>  %263 = fmul float %185, %255
>  %264 = fmul float %186, %256
>  %265 = fadd float %264, %263
>  %266 = fmul float %187, %257
>  %267 = fadd float %265, %266
>  %268 = fcmp uge float %262, 0.000000e+00
>  %269 = select i1 %268, float %262, float 0.000000e+00
>  %270 = fcmp uge float %267, 0.000000e+00
>  %271 = select i1 %270, float %267, float 0.000000e+00
>  %272 = call float @llvm.pow.f32(float %271, float %36)
>  %273 = call float @llvm.AMDGPU.cndlt(float %262, float 0.000000e+00, float %272)
>  %274 = fmul float 1.000000e+00, %234
>  %275 = fmul float %269, %234
>  %276 = fmul float %273, %234
>  %277 = fmul float %274, %59
>  %278 = fadd float %277, %37
>  %279 = fmul float %274, %60
>  %280 = fadd float %279, %38
>  %281 = fmul float %274, %61
>  %282 = fadd float %281, %39
>  %283 = fmul float %275, %62
>  %284 = fadd float %283, %278
>  %285 = fmul float %275, %63
>  %286 = fadd float %285, %280
>  %287 = fmul float %275, %64
>  %288 = fadd float %287, %282
>  %289 = fmul float %276, %65
>  %290 = fadd float %289, %284
>  %291 = fmul float %276, %66
>  %292 = fadd float %291, %286
>  %293 = fmul float %276, %67
>  %294 = fadd float %293, %288
>  %295 = fsub float %68, %208
>  %296 = fsub float %69, %210
>  %297 = fsub float %70, %212
>  %298 = fmul float %295, %295
>  %299 = fmul float %296, %296
>  %300 = fadd float %299, %298
>  %301 = fmul float %297, %297
>  %302 = fadd float %300, %301
>  %303 = call float @fabs(float %302)
>  %304 = call float @llvm.AMDGPU.rsq(float %303)
>  %305 = fmul float %295, %304
>  %306 = fmul float %296, %304
>  %307 = fmul float %297, %304
>  %308 = fdiv float 1.000000e+00, %304
>  %309 = fmul float %304, %308
>  %310 = fmul float %308, %308
>  %311 = fmul float %71, %309
>  %312 = fmul float %72, %308
>  %313 = fadd float %312, %311
>  %314 = fmul float %73, %310
>  %315 = fadd float %313, %314
>  %316 = fdiv float 1.000000e+00, %315
>  %317 = fsub float %305, %242
>  %318 = fsub float %306, %243
>  %319 = fsub float %307, %244
>  %320 = fmul float %317, %317
>  %321 = fmul float %318, %318
>  %322 = fadd float %321, %320
>  %323 = fmul float %319, %319
>  %324 = fadd float %322, %323
>  %325 = call float @fabs(float %324)
>  %326 = call float @llvm.AMDGPU.rsq(float %325)
>  %327 = fmul float %317, %326
>  %328 = fmul float %318, %326
>  %329 = fmul float %319, %326
>  %330 = fmul float %185, %305
>  %331 = fmul float %186, %306
>  %332 = fadd float %331, %330
>  %333 = fmul float %187, %307
>  %334 = fadd float %332, %333
>  %335 = fmul float %185, %327
>  %336 = fmul float %186, %328
>  %337 = fadd float %336, %335
>  %338 = fmul float %187, %329
>  %339 = fadd float %337, %338
>  %340 = fcmp uge float %334, 0.000000e+00
>  %341 = select i1 %340, float %334, float 0.000000e+00
>  %342 = fcmp uge float %339, 0.000000e+00
>  %343 = select i1 %342, float %339, float 0.000000e+00
>  %344 = call float @llvm.pow.f32(float %343, float %36)
>  %345 = call float @llvm.AMDGPU.cndlt(float %334, float 0.000000e+00, float %344)
>  %346 = fmul float 1.000000e+00, %316
>  %347 = fmul float %341, %316
>  %348 = fmul float %345, %316
>  %349 = fmul float %346, %74
>  %350 = fadd float %349, %290
>  %351 = fmul float %346, %75
>  %352 = fadd float %351, %292
>  %353 = fmul float %346, %76
>  %354 = fadd float %353, %294
>  %355 = fmul float %347, %77
>  %356 = fadd float %355, %350
>  %357 = fmul float %347, %78
>  %358 = fadd float %357, %352
>  %359 = fmul float %347, %79
>  %360 = fadd float %359, %354
>  %361 = fmul float %348, %80
>  %362 = fadd float %361, %356
>  %363 = fmul float %348, %81
>  %364 = fadd float %363, %358
>  %365 = fmul float %348, %82
>  %366 = fadd float %365, %360
>  %367 = fsub float %83, %208
>  %368 = fsub float %84, %210
>  %369 = fsub float %85, %212
>  %370 = fmul float %367, %367
>  %371 = fmul float %368, %368
>  %372 = fadd float %371, %370
>  %373 = fmul float %369, %369
>  %374 = fadd float %372, %373
>  %375 = call float @fabs(float %374)
>  %376 = call float @llvm.AMDGPU.rsq(float %375)
>  %377 = fmul float %367, %376
>  %378 = fmul float %368, %376
>  %379 = fmul float %369, %376
>  %380 = fsub float -0.000000e+00, %377
>  %381 = fsub float -0.000000e+00, %378
>  %382 = fsub float -0.000000e+00, %379
>  %383 = fmul float %380, %90
>  %384 = fmul float %381, %91
>  %385 = fadd float %384, %383
>  %386 = fmul float %382, %92
>  %387 = fadd float %385, %386
>  %388 = fcmp olt float %93, %387
>  %389 = select i1 %388, float 1.000000e+00, float 0.000000e+00
>  %390 = fcmp olt float %93, %387
>  %391 = select i1 %390, float 1.000000e+00, float 0.000000e+00
>  %392 = fcmp olt float %93, %387
>  %393 = select i1 %392, float 1.000000e+00, float 0.000000e+00
>  %394 = call float @llvm.pow.f32(float %387, float %89)
>  %395 = fmul float %389, %394
>  %396 = fmul float %391, %394
>  %397 = fmul float %393, %394
>  %398 = fdiv float 1.000000e+00, %376
>  %399 = fmul float %376, %398
>  %400 = fmul float %398, %398
>  %401 = fmul float %86, %399
>  %402 = fmul float %87, %398
>  %403 = fadd float %402, %401
>  %404 = fmul float %88, %400
>  %405 = fadd float %403, %404
>  %406 = fdiv float 1.000000e+00, %405
>  %407 = fmul float %406, %395
>  %408 = fmul float %406, %396
>  %409 = fmul float %406, %397
>  %410 = fsub float %377, %242
>  %411 = fsub float %378, %243
>  %412 = fsub float %379, %244
>  %413 = fmul float %410, %410
>  %414 = fmul float %411, %411
>  %415 = fadd float %414, %413
>  %416 = fmul float %412, %412
>  %417 = fadd float %415, %416
>  %418 = call float @fabs(float %417)
>  %419 = call float @llvm.AMDGPU.rsq(float %418)
>  %420 = fmul float %410, %419
>  %421 = fmul float %411, %419
>  %422 = fmul float %412, %419
>  %423 = fmul float %185, %377
>  %424 = fmul float %186, %378
>  %425 = fadd float %424, %423
>  %426 = fmul float %187, %379
>  %427 = fadd float %425, %426
>  %428 = fmul float %185, %420
>  %429 = fmul float %186, %421
>  %430 = fadd float %429, %428
>  %431 = fmul float %187, %422
>  %432 = fadd float %430, %431
>  %433 = fcmp uge float %427, 0.000000e+00
>  %434 = select i1 %433, float %427, float 0.000000e+00
>  %435 = fcmp uge float %432, 0.000000e+00
>  %436 = select i1 %435, float %432, float 0.000000e+00
>  %437 = call float @llvm.pow.f32(float %436, float %36)
>  %438 = call float @llvm.AMDGPU.cndlt(float %427, float 0.000000e+00, float %437)
>  %439 = fmul float 1.000000e+00, %407
>  %440 = fmul float %434, %408
>  %441 = fmul float %438, %409
>  %442 = fmul float %439, %94
>  %443 = fadd float %442, %362
>  %444 = fmul float %439, %95
>  %445 = fadd float %444, %364
>  %446 = fmul float %439, %96
>  %447 = fadd float %446, %366
>  %448 = fmul float %440, %97
>  %449 = fadd float %448, %443
>  %450 = fmul float %440, %98
>  %451 = fadd float %450, %445
>  %452 = fmul float %440, %99
>  %453 = fadd float %452, %447
>  %454 = fmul float %441, %100
>  %455 = fadd float %454, %449
>  %456 = fmul float %441, %101
>  %457 = fadd float %456, %451
>  %458 = fmul float %441, %102
>  %459 = fadd float %458, %453
>  %460 = fsub float %103, %242
>  %461 = fsub float %104, %243
>  %462 = fsub float %105, %244
>  %463 = fmul float %460, %460
>  %464 = fmul float %461, %461
>  %465 = fadd float %464, %463
>  %466 = fmul float %462, %462
>  %467 = fadd float %465, %466
>  %468 = call float @fabs(float %467)
>  %469 = call float @llvm.AMDGPU.rsq(float %468)
>  %470 = fmul float %460, %469
>  %471 = fmul float %461, %469
>  %472 = fmul float %462, %469
>  %473 = fmul float %185, %103
>  %474 = fmul float %186, %104
>  %475 = fadd float %474, %473
>  %476 = fmul float %187, %105
>  %477 = fadd float %475, %476
>  %478 = fmul float %185, %470
>  %479 = fmul float %186, %471
>  %480 = fadd float %479, %478
>  %481 = fmul float %187, %472
>  %482 = fadd float %480, %481
>  %483 = fcmp uge float %477, 0.000000e+00
>  %484 = select i1 %483, float %477, float 0.000000e+00
>  %485 = fcmp uge float %482, 0.000000e+00
>  %486 = select i1 %485, float %482, float 0.000000e+00
>  %487 = call float @llvm.pow.f32(float %486, float %36)
>  %488 = call float @llvm.AMDGPU.cndlt(float %477, float 0.000000e+00, float %487)
>  %489 = fadd float %106, %455
>  %490 = fadd float %107, %457
>  %491 = fadd float %108, %459
>  %492 = fmul float %484, %109
>  %493 = fadd float %492, %489
>  %494 = fmul float %484, %110
>  %495 = fadd float %494, %490
>  %496 = fmul float %484, %111
>  %497 = fadd float %496, %491
>  %498 = fmul float %488, %112
>  %499 = fadd float %498, %493
>  %500 = fmul float %488, %113
>  %501 = fadd float %500, %495
>  %502 = fmul float %488, %114
>  %503 = fadd float %502, %497
>  %504 = call float @llvm.AMDIL.clamp.(float %499, float 0.000000e+00, float 1.000000e+00)
>  %505 = call float @llvm.AMDIL.clamp.(float %501, float 0.000000e+00, float 1.000000e+00)
>  %506 = call float @llvm.AMDIL.clamp.(float %503, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %504, float %505, float %506, float %191)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %131, float %132, float %133, float %134)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %156, float %158, float %160, float %162)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020129
>bf8c007f
>100a0204
>c202012d
>bf8c007f
>d2820005
>04140902
>c2020131
>bf8c007f
>d2820005
>04140903
>c2020135
>bf8c007f
>d2820010
>04140904
>c2020128
>bf8c007f
>100a0204
>c202012c
>bf8c007f
>d2820005
>04140902
>c2020130
>bf8c007f
>d2820005
>04140903
>c2020134
>bf8c007f
>d2820011
>04140904
>100a2311
>d2820005
>04162110
>c202012a
>bf8c007f
>100c0204
>c202012e
>bf8c007f
>d2820006
>04180902
>c2020132
>bf8c007f
>d2820006
>04180903
>c2020136
>bf8c007f
>d2820012
>04180904
>d2820005
>04162512
>d2060105
>02010105
>7e0e5b05
>100a0f10
>c2020125
>bf8c007f
>080c2004
>c2020124
>bf8c007f
>08142204
>1010150a
>d2820008
>04220d06
>c2020126
>bf8c007f
>08162404
>d2820008
>0422170b
>d2060108
>02010108
>7e105b08
>10121106
>08180b09
>100c0f11
>1014110a
>08280d0a
>101a2914
>d282000f
>0436190c
>100e0f12
>101c110b
>081a0f0e
>d282000b
>043e1b0d
>d206010b
>0201010b
>7e1e5b0b
>10261f0c
>10181f14
>c0840704
>bf8c007f
>e00c2000
>80021400
>c2020114
>bf8c0070
>10162804
>c2020115
>bf8c007f
>d282000b
>042c0915
>c2020116
>bf8c007f
>d2820018
>042c0916
>c2020110
>bf8c007f
>10162804
>c2020111
>bf8c007f
>d282000b
>042c0915
>c2020112
>bf8c007f
>d282000b
>042c0916
>1032170b
>d2820019
>04663118
>c2020118
>bf8c007f
>10342804
>c2020119
>bf8c007f
>d282001a
>04680915
>c202011a
>bf8c007f
>d2820014
>04680916
>d2820015
>04662914
>d2060115
>02010115
>7e2a5b15
>10162b0b
>102c190b
>10182b18
>d2820013
>045a270c
>101e1f0d
>101a2b14
>d282000f
>044e1f0d
>d00c0004
>0201010f
>d200000f
>00121e80
>7e1e4f0f
>c202011c
>bf8c007f
>0e1e1e04
>7e1e4b0f
>1014150b
>d2820009
>042a130c
>d282000a
>04261d0d
>d0080008
>02021480
>d200000e
>0021010f
>7e125508
>10101308
>c2028138
>bf8c007f
>10101005
>c2028139
>bf8c007f
>d2820008
>04221205
>10121309
>c202813a
>bf8c007f
>d2820008
>04221205
>7e125508
>1010130e
>d00c0008
>0201010a
>d200000a
>00221480
>1014130a
>c202813e
>c2040122
>bf8c007f
>7e1c0208
>d282000e
>04380b09
>c2028142
>bf8c007f
>d282000e
>04380b0a
>c2028146
>bf8c007f
>d2820013
>04380b08
>c2028149
>bf8c007f
>081e2005
>c2028148
>bf8c007f
>08282205
>101c2914
>d282000e
>043a1f0f
>c202814a
>bf8c007f
>082a2405
>d282000e
>043a2b15
>d206010e
>0201010e
>7e2c5b0e
>7e1c5516
>102e1d16
>c202814c
>bf8c007f
>102e2e05
>c202814d
>bf8c007f
>d2820017
>045e1c05
>101c1d0e
>c202814e
>bf8c007f
>d282000e
>045e1c05
>7e1c550e
>c2028152
>bf8c007f
>d2820018
>044c0b0e
>102e2d14
>10262f0b
>10322d0f
>d282000f
>044e330c
>102a2d15
>d2820013
>043e2b0d
>d00c0008
>02010113
>d200000f
>00222680
>101e1d0f
>c2028156
>bf8c007f
>d2820014
>04600b0f
>082c0b19
>082e0d17
>10302f17
>d2820018
>04622d16
>082a0f15
>d2820018
>04622b15
>d2060118
>02010118
>7e305b18
>102c3116
>102e3117
>102e2f0b
>d2820016
>045e2d0c
>102a3115
>d2820015
>045a2b0d
>d00c0008
>02010115
>d2000015
>00222a80
>7e2a4f15
>0e2a2a04
>7e2a4b15
>d0080008
>02022680
>d2000013
>00210115
>10261d13
>c202815a
>bf8c007f
>d2820014
>04500b13
>c202815d
>bf8c007f
>082a2005
>c202815c
>bf8c007f
>082c2205
>10202d16
>d2820010
>04422b15
>c202815e
>bf8c007f
>08222405
>d2820010
>04422311
>d2060110
>02010110
>7e205b10
>10242116
>c2028164
>bf8c007f
>102c2405
>102a2115
>d2060017
>22010115
>c2028165
>bf8c007f
>102e2e05
>082e2d17
>102c2111
>c2028166
>bf8c007f
>10222c05
>082e2317
>c2028167
>bf8c007f
>d0020008
>02022e05
>d2000011
>0021e480
>7e2e4f17
>c2028163
>bf8c007f
>0e2e2e05
>7e2e4b17
>10222f11
>7e2e5510
>10202f10
>c2028160
>bf8c007f
>10202005
>c2028161
>bf8c007f
>d2820010
>04422e05
>102e2f17
>c2028162
>bf8c007f
>d2820010
>04422e05
>7e205510
>10202310
>c202816a
>bf8c007f
>d2820017
>04500b10
>1022250b
>d2820011
>04462b0c
>d2820014
>04462d0d
>d00c0008
>02010114
>d2000011
>00222880
>10222111
>c202816e
>bf8c007f
>d2820017
>045c0b11
>082a0b15
>08240d12
>10302512
>d2820018
>04622b15
>082c0f16
>d2820018
>04622d16
>d2060118
>02010118
>7e305b18
>102a3115
>10243112
>1024250b
>d2820012
>044a2b0c
>102a3116
>d2820012
>044a2b0d
>d00c0008
>02010112
>d2000012
>00222480
>7e244f12
>0e242404
>7e244b12
>d0080008
>02022880
>d2000012
>00210112
>10242112
>c2028172
>bf8c007f
>d2820014
>045c0b12
>c202817e
>bf8c007f
>062c2805
>c2028174
>bf8c007f
>10281605
>c2048175
>bf8c007f
>d2820014
>0450130c
>c2040176
>bf8c007f
>d2820015
>0450110d
>d00c000a
>02010115
>d2000014
>002a2a80
>c2050182
>bf8c007f
>d2820016
>04581514
>080a0a09
>080c0c05
>102e0d06
>d2820017
>045e0b05
>080e0e08
>d2820017
>045e0f07
>d2060117
>02010117
>7e2e5b17
>100a2f05
>100c2f06
>100c0d0b
>d2820005
>041a0b0c
>100c2f07
>d2820005
>04160d0d
>d00c0008
>02010105
>d2000005
>00220a80
>7e0a4f05
>0e0a0a04
>7e0a4b05
>d0080004
>02022a80
>d2000006
>00110105
>c2020186
>bf8c007f
>d2820005
>04580906
>d2060805
>02010105
>c202013d
>c2028121
>bf8c007f
>7e0e0205
>d2820007
>041c0909
>c2020141
>bf8c007f
>d2820007
>041c090a
>c2020145
>bf8c007f
>d2820007
>041c0908
>c2020151
>bf8c007f
>d2820007
>041c090e
>c2020155
>bf8c007f
>d2820007
>041c090f
>c2020159
>bf8c007f
>d2820007
>041c0913
>c2020169
>bf8c007f
>d2820007
>041c0910
>c202016d
>bf8c007f
>d2820007
>041c0911
>c2020171
>bf8c007f
>d2820007
>041c0912
>c202017d
>bf8c007f
>060e0e04
>c2020181
>bf8c007f
>d2820007
>041c0914
>c2020185
>bf8c007f
>d2820007
>041c0906
>d2060807
>02010107
>c202013c
>c2028120
>bf8c007f
>7e160205
>d2820009
>042c0909
>c2020140
>bf8c007f
>d2820009
>0424090a
>c2020144
>bf8c007f
>d2820008
>04240908
>c2020150
>bf8c007f
>d2820008
>0420090e
>c2020154
>bf8c007f
>d2820008
>0420090f
>c2020158
>bf8c007f
>d2820008
>04200913
>c2020168
>bf8c007f
>d2820008
>04200910
>c202016c
>bf8c007f
>d2820008
>04200911
>c2020170
>bf8c007f
>d2820008
>04200912
>c202017c
>bf8c007f
>06101004
>c2020180
>bf8c007f
>d2820008
>04200914
>c2020184
>bf8c007f
>d2820006
>04200906
>d2060806
>02010106
>c2020123
>bf8c007f
>d2060808
>02010004
>f800020f
>08050706
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800021f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..32]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD TEMP[3], TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: SUB TEMP[5], CONST[28], TEMP[4]
> 78: DP3 TEMP[7], TEMP[5], TEMP[5]
> 79: RSQ TEMP[7], |TEMP[7]|
> 80: MUL TEMP[5], TEMP[5], TEMP[7]
> 81: RCP TEMP[7].yz, TEMP[7]
> 82: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 83: DP3 TEMP[7], CONST[29], TEMP[7]
> 84: RCP TEMP[8], TEMP[7]
> 85: SUB TEMP[7], TEMP[5], TEMP[6]
> 86: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 87: RSQ TEMP[9].x, |TEMP[9]|
> 88: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 89: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 90: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 91: LIT TEMP[1], TEMP[2]
> 92: MUL TEMP[1], TEMP[1], TEMP[8]
> 93: MAD TEMP[3], TEMP[1].xxxx, CONST[30], TEMP[3]
> 94: MAD TEMP[3], TEMP[1].yyyy, CONST[31], TEMP[3]
> 95: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[32], TEMP[3]
> 96: ABS OUT[2].x, TEMP[4].zzzz
> 97: MOV OUT[2].yzw, IMM[0].xxxy
> 98: MOV OUT[3], IN[2]
> 99: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %113 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %114 = load <16 x i8> addrspace(2)* %113, !tbaa !0
>  %115 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %114, i32 0, i32 %5)
>  %116 = extractelement <4 x float> %115, i32 0
>  %117 = extractelement <4 x float> %115, i32 1
>  %118 = extractelement <4 x float> %115, i32 2
>  %119 = extractelement <4 x float> %115, i32 3
>  %120 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
>  %122 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %121, i32 0, i32 %5)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = extractelement <4 x float> %122, i32 1
>  %125 = extractelement <4 x float> %122, i32 2
>  %126 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %127 = load <16 x i8> addrspace(2)* %126, !tbaa !0
>  %128 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %127, i32 0, i32 %5)
>  %129 = extractelement <4 x float> %128, i32 0
>  %130 = extractelement <4 x float> %128, i32 1
>  %131 = extractelement <4 x float> %128, i32 2
>  %132 = extractelement <4 x float> %128, i32 3
>  %133 = fmul float %116, %11
>  %134 = fmul float %116, %12
>  %135 = fmul float %116, %13
>  %136 = fmul float %116, %14
>  %137 = fmul float %117, %15
>  %138 = fadd float %137, %133
>  %139 = fmul float %117, %16
>  %140 = fadd float %139, %134
>  %141 = fmul float %117, %17
>  %142 = fadd float %141, %135
>  %143 = fmul float %117, %18
>  %144 = fadd float %143, %136
>  %145 = fmul float %118, %19
>  %146 = fadd float %145, %138
>  %147 = fmul float %118, %20
>  %148 = fadd float %147, %140
>  %149 = fmul float %118, %21
>  %150 = fadd float %149, %142
>  %151 = fmul float %118, %22
>  %152 = fadd float %151, %144
>  %153 = fmul float %119, %23
>  %154 = fadd float %153, %146
>  %155 = fmul float %119, %24
>  %156 = fadd float %155, %148
>  %157 = fmul float %119, %25
>  %158 = fadd float %157, %150
>  %159 = fmul float %119, %26
>  %160 = fadd float %159, %152
>  %161 = fmul float %123, %27
>  %162 = fmul float %124, %28
>  %163 = fadd float %162, %161
>  %164 = fmul float %125, %29
>  %165 = fadd float %163, %164
>  %166 = fmul float %123, %30
>  %167 = fmul float %124, %31
>  %168 = fadd float %167, %166
>  %169 = fmul float %125, %32
>  %170 = fadd float %168, %169
>  %171 = fmul float %123, %33
>  %172 = fmul float %124, %34
>  %173 = fadd float %172, %171
>  %174 = fmul float %125, %35
>  %175 = fadd float %173, %174
>  %176 = fmul float %165, %165
>  %177 = fmul float %170, %170
>  %178 = fadd float %177, %176
>  %179 = fmul float %175, %175
>  %180 = fadd float %178, %179
>  %181 = call float @fabs(float %180)
>  %182 = call float @llvm.AMDGPU.rsq(float %181)
>  %183 = fmul float %165, %182
>  %184 = fmul float %170, %182
>  %185 = fmul float %175, %182
>  %186 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %187 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %188 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %189 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %190 = fmul float %116, %44
>  %191 = fmul float %116, %45
>  %192 = fmul float %116, %46
>  %193 = fmul float %117, %47
>  %194 = fadd float %193, %190
>  %195 = fmul float %117, %48
>  %196 = fadd float %195, %191
>  %197 = fmul float %117, %49
>  %198 = fadd float %197, %192
>  %199 = fmul float %118, %50
>  %200 = fadd float %199, %194
>  %201 = fmul float %118, %51
>  %202 = fadd float %201, %196
>  %203 = fmul float %118, %52
>  %204 = fadd float %203, %198
>  %205 = fmul float %119, %53
>  %206 = fadd float %205, %200
>  %207 = fmul float %119, %54
>  %208 = fadd float %207, %202
>  %209 = fmul float %119, %55
>  %210 = fadd float %209, %204
>  %211 = fsub float %41, %206
>  %212 = fsub float %42, %208
>  %213 = fsub float %43, %210
>  %214 = fmul float %211, %211
>  %215 = fmul float %212, %212
>  %216 = fadd float %215, %214
>  %217 = fmul float %213, %213
>  %218 = fadd float %216, %217
>  %219 = call float @fabs(float %218)
>  %220 = call float @llvm.AMDGPU.rsq(float %219)
>  %221 = fmul float %211, %220
>  %222 = fmul float %212, %220
>  %223 = fmul float %213, %220
>  %224 = fdiv float 1.000000e+00, %220
>  %225 = fmul float %220, %224
>  %226 = fmul float %224, %224
>  %227 = fmul float %56, %225
>  %228 = fmul float %57, %224
>  %229 = fadd float %228, %227
>  %230 = fmul float %58, %226
>  %231 = fadd float %229, %230
>  %232 = fdiv float 1.000000e+00, %231
>  %233 = fmul float %206, %206
>  %234 = fmul float %208, %208
>  %235 = fadd float %234, %233
>  %236 = fmul float %210, %210
>  %237 = fadd float %235, %236
>  %238 = call float @fabs(float %237)
>  %239 = call float @llvm.AMDGPU.rsq(float %238)
>  %240 = fmul float %206, %239
>  %241 = fmul float %208, %239
>  %242 = fmul float %210, %239
>  %243 = fsub float %221, %240
>  %244 = fsub float %222, %241
>  %245 = fsub float %223, %242
>  %246 = fmul float %243, %243
>  %247 = fmul float %244, %244
>  %248 = fadd float %247, %246
>  %249 = fmul float %245, %245
>  %250 = fadd float %248, %249
>  %251 = call float @fabs(float %250)
>  %252 = call float @llvm.AMDGPU.rsq(float %251)
>  %253 = fmul float %243, %252
>  %254 = fmul float %244, %252
>  %255 = fmul float %245, %252
>  %256 = fmul float %183, %221
>  %257 = fmul float %184, %222
>  %258 = fadd float %257, %256
>  %259 = fmul float %185, %223
>  %260 = fadd float %258, %259
>  %261 = fmul float %183, %253
>  %262 = fmul float %184, %254
>  %263 = fadd float %262, %261
>  %264 = fmul float %185, %255
>  %265 = fadd float %263, %264
>  %266 = fcmp uge float %260, 0.000000e+00
>  %267 = select i1 %266, float %260, float 0.000000e+00
>  %268 = fcmp uge float %265, 0.000000e+00
>  %269 = select i1 %268, float %265, float 0.000000e+00
>  %270 = call float @llvm.pow.f32(float %269, float %36)
>  %271 = call float @llvm.AMDGPU.cndlt(float %260, float 0.000000e+00, float %270)
>  %272 = fmul float 1.000000e+00, %232
>  %273 = fmul float %267, %232
>  %274 = fmul float %271, %232
>  %275 = fmul float %272, %59
>  %276 = fadd float %275, %37
>  %277 = fmul float %272, %60
>  %278 = fadd float %277, %38
>  %279 = fmul float %272, %61
>  %280 = fadd float %279, %39
>  %281 = fmul float %273, %62
>  %282 = fadd float %281, %276
>  %283 = fmul float %273, %63
>  %284 = fadd float %283, %278
>  %285 = fmul float %273, %64
>  %286 = fadd float %285, %280
>  %287 = fmul float %274, %65
>  %288 = fadd float %287, %282
>  %289 = fmul float %274, %66
>  %290 = fadd float %289, %284
>  %291 = fmul float %274, %67
>  %292 = fadd float %291, %286
>  %293 = fsub float %68, %206
>  %294 = fsub float %69, %208
>  %295 = fsub float %70, %210
>  %296 = fmul float %293, %293
>  %297 = fmul float %294, %294
>  %298 = fadd float %297, %296
>  %299 = fmul float %295, %295
>  %300 = fadd float %298, %299
>  %301 = call float @fabs(float %300)
>  %302 = call float @llvm.AMDGPU.rsq(float %301)
>  %303 = fmul float %293, %302
>  %304 = fmul float %294, %302
>  %305 = fmul float %295, %302
>  %306 = fdiv float 1.000000e+00, %302
>  %307 = fmul float %302, %306
>  %308 = fmul float %306, %306
>  %309 = fmul float %71, %307
>  %310 = fmul float %72, %306
>  %311 = fadd float %310, %309
>  %312 = fmul float %73, %308
>  %313 = fadd float %311, %312
>  %314 = fdiv float 1.000000e+00, %313
>  %315 = fsub float %303, %240
>  %316 = fsub float %304, %241
>  %317 = fsub float %305, %242
>  %318 = fmul float %315, %315
>  %319 = fmul float %316, %316
>  %320 = fadd float %319, %318
>  %321 = fmul float %317, %317
>  %322 = fadd float %320, %321
>  %323 = call float @fabs(float %322)
>  %324 = call float @llvm.AMDGPU.rsq(float %323)
>  %325 = fmul float %315, %324
>  %326 = fmul float %316, %324
>  %327 = fmul float %317, %324
>  %328 = fmul float %183, %303
>  %329 = fmul float %184, %304
>  %330 = fadd float %329, %328
>  %331 = fmul float %185, %305
>  %332 = fadd float %330, %331
>  %333 = fmul float %183, %325
>  %334 = fmul float %184, %326
>  %335 = fadd float %334, %333
>  %336 = fmul float %185, %327
>  %337 = fadd float %335, %336
>  %338 = fcmp uge float %332, 0.000000e+00
>  %339 = select i1 %338, float %332, float 0.000000e+00
>  %340 = fcmp uge float %337, 0.000000e+00
>  %341 = select i1 %340, float %337, float 0.000000e+00
>  %342 = call float @llvm.pow.f32(float %341, float %36)
>  %343 = call float @llvm.AMDGPU.cndlt(float %332, float 0.000000e+00, float %342)
>  %344 = fmul float 1.000000e+00, %314
>  %345 = fmul float %339, %314
>  %346 = fmul float %343, %314
>  %347 = fmul float %344, %74
>  %348 = fadd float %347, %288
>  %349 = fmul float %344, %75
>  %350 = fadd float %349, %290
>  %351 = fmul float %344, %76
>  %352 = fadd float %351, %292
>  %353 = fmul float %345, %77
>  %354 = fadd float %353, %348
>  %355 = fmul float %345, %78
>  %356 = fadd float %355, %350
>  %357 = fmul float %345, %79
>  %358 = fadd float %357, %352
>  %359 = fmul float %346, %80
>  %360 = fadd float %359, %354
>  %361 = fmul float %346, %81
>  %362 = fadd float %361, %356
>  %363 = fmul float %346, %82
>  %364 = fadd float %363, %358
>  %365 = fsub float %83, %206
>  %366 = fsub float %84, %208
>  %367 = fsub float %85, %210
>  %368 = fmul float %365, %365
>  %369 = fmul float %366, %366
>  %370 = fadd float %369, %368
>  %371 = fmul float %367, %367
>  %372 = fadd float %370, %371
>  %373 = call float @fabs(float %372)
>  %374 = call float @llvm.AMDGPU.rsq(float %373)
>  %375 = fmul float %365, %374
>  %376 = fmul float %366, %374
>  %377 = fmul float %367, %374
>  %378 = fdiv float 1.000000e+00, %374
>  %379 = fmul float %374, %378
>  %380 = fmul float %378, %378
>  %381 = fmul float %86, %379
>  %382 = fmul float %87, %378
>  %383 = fadd float %382, %381
>  %384 = fmul float %88, %380
>  %385 = fadd float %383, %384
>  %386 = fdiv float 1.000000e+00, %385
>  %387 = fsub float %375, %240
>  %388 = fsub float %376, %241
>  %389 = fsub float %377, %242
>  %390 = fmul float %387, %387
>  %391 = fmul float %388, %388
>  %392 = fadd float %391, %390
>  %393 = fmul float %389, %389
>  %394 = fadd float %392, %393
>  %395 = call float @fabs(float %394)
>  %396 = call float @llvm.AMDGPU.rsq(float %395)
>  %397 = fmul float %387, %396
>  %398 = fmul float %388, %396
>  %399 = fmul float %389, %396
>  %400 = fmul float %183, %375
>  %401 = fmul float %184, %376
>  %402 = fadd float %401, %400
>  %403 = fmul float %185, %377
>  %404 = fadd float %402, %403
>  %405 = fmul float %183, %397
>  %406 = fmul float %184, %398
>  %407 = fadd float %406, %405
>  %408 = fmul float %185, %399
>  %409 = fadd float %407, %408
>  %410 = fcmp uge float %404, 0.000000e+00
>  %411 = select i1 %410, float %404, float 0.000000e+00
>  %412 = fcmp uge float %409, 0.000000e+00
>  %413 = select i1 %412, float %409, float 0.000000e+00
>  %414 = call float @llvm.pow.f32(float %413, float %36)
>  %415 = call float @llvm.AMDGPU.cndlt(float %404, float 0.000000e+00, float %414)
>  %416 = fmul float 1.000000e+00, %386
>  %417 = fmul float %411, %386
>  %418 = fmul float %415, %386
>  %419 = fmul float %416, %89
>  %420 = fadd float %419, %360
>  %421 = fmul float %416, %90
>  %422 = fadd float %421, %362
>  %423 = fmul float %416, %91
>  %424 = fadd float %423, %364
>  %425 = fmul float %417, %92
>  %426 = fadd float %425, %420
>  %427 = fmul float %417, %93
>  %428 = fadd float %427, %422
>  %429 = fmul float %417, %94
>  %430 = fadd float %429, %424
>  %431 = fmul float %418, %95
>  %432 = fadd float %431, %426
>  %433 = fmul float %418, %96
>  %434 = fadd float %433, %428
>  %435 = fmul float %418, %97
>  %436 = fadd float %435, %430
>  %437 = fsub float %98, %206
>  %438 = fsub float %99, %208
>  %439 = fsub float %100, %210
>  %440 = fmul float %437, %437
>  %441 = fmul float %438, %438
>  %442 = fadd float %441, %440
>  %443 = fmul float %439, %439
>  %444 = fadd float %442, %443
>  %445 = call float @fabs(float %444)
>  %446 = call float @llvm.AMDGPU.rsq(float %445)
>  %447 = fmul float %437, %446
>  %448 = fmul float %438, %446
>  %449 = fmul float %439, %446
>  %450 = fdiv float 1.000000e+00, %446
>  %451 = fmul float %446, %450
>  %452 = fmul float %450, %450
>  %453 = fmul float %101, %451
>  %454 = fmul float %102, %450
>  %455 = fadd float %454, %453
>  %456 = fmul float %103, %452
>  %457 = fadd float %455, %456
>  %458 = fdiv float 1.000000e+00, %457
>  %459 = fsub float %447, %240
>  %460 = fsub float %448, %241
>  %461 = fsub float %449, %242
>  %462 = fmul float %459, %459
>  %463 = fmul float %460, %460
>  %464 = fadd float %463, %462
>  %465 = fmul float %461, %461
>  %466 = fadd float %464, %465
>  %467 = call float @fabs(float %466)
>  %468 = call float @llvm.AMDGPU.rsq(float %467)
>  %469 = fmul float %459, %468
>  %470 = fmul float %460, %468
>  %471 = fmul float %461, %468
>  %472 = fmul float %183, %447
>  %473 = fmul float %184, %448
>  %474 = fadd float %473, %472
>  %475 = fmul float %185, %449
>  %476 = fadd float %474, %475
>  %477 = fmul float %183, %469
>  %478 = fmul float %184, %470
>  %479 = fadd float %478, %477
>  %480 = fmul float %185, %471
>  %481 = fadd float %479, %480
>  %482 = fcmp uge float %476, 0.000000e+00
>  %483 = select i1 %482, float %476, float 0.000000e+00
>  %484 = fcmp uge float %481, 0.000000e+00
>  %485 = select i1 %484, float %481, float 0.000000e+00
>  %486 = call float @llvm.pow.f32(float %485, float %36)
>  %487 = call float @llvm.AMDGPU.cndlt(float %476, float 0.000000e+00, float %486)
>  %488 = fmul float 1.000000e+00, %458
>  %489 = fmul float %483, %458
>  %490 = fmul float %487, %458
>  %491 = fmul float %488, %104
>  %492 = fadd float %491, %432
>  %493 = fmul float %488, %105
>  %494 = fadd float %493, %434
>  %495 = fmul float %488, %106
>  %496 = fadd float %495, %436
>  %497 = fmul float %489, %107
>  %498 = fadd float %497, %492
>  %499 = fmul float %489, %108
>  %500 = fadd float %499, %494
>  %501 = fmul float %489, %109
>  %502 = fadd float %501, %496
>  %503 = fmul float %490, %110
>  %504 = fadd float %503, %498
>  %505 = fmul float %490, %111
>  %506 = fadd float %505, %500
>  %507 = fmul float %490, %112
>  %508 = fadd float %507, %502
>  %509 = call float @llvm.AMDIL.clamp.(float %504, float 0.000000e+00, float 1.000000e+00)
>  %510 = call float @llvm.AMDIL.clamp.(float %506, float 0.000000e+00, float 1.000000e+00)
>  %511 = call float @llvm.AMDIL.clamp.(float %508, float 0.000000e+00, float 1.000000e+00)
>  %512 = call float @fabs(float %210)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %509, float %510, float %511, float %189)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %512, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %129, float %130, float %131, float %132)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %154, float %156, float %158, float %160)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>d2060806
>02010106
>c202013d
>c2028121
>bf8c007f
>7e120205
>d2820009
>0424090c
>c2020141
>bf8c007f
>d2820009
>0424090d
>c2020145
>bf8c007f
>d2820009
>0424090b
>c2020151
>bf8c007f
>d2820009
>04240911
>c2020155
>bf8c007f
>d2820009
>04240912
>c2020159
>bf8c007f
>d2820009
>04240913
>c2020165
>bf8c007f
>d2820009
>04240914
>c2020169
>bf8c007f
>d2820009
>04240915
>c202016d
>bf8c007f
>d2820009
>04240916
>c2020179
>bf8c007f
>d2820009
>04240907
>c202017d
>bf8c007f
>d2820009
>0424090a
>c2020181
>bf8c007f
>d2820009
>04240908
>d2060809
>02010109
>c202013c
>c2028120
>bf8c007f
>7e1c0205
>d282000c
>0438090c
>c2020140
>bf8c007f
>d282000c
>0430090d
>c2020144
>bf8c007f
>d282000b
>0430090b
>c2020150
>bf8c007f
>d282000b
>042c0911
>c2020154
>bf8c007f
>d282000b
>042c0912
>c2020158
>bf8c007f
>d282000b
>042c0913
>c2020164
>bf8c007f
>d282000b
>042c0914
>c2020168
>bf8c007f
>d282000b
>042c0915
>c202016c
>bf8c007f
>d282000b
>042c0916
>c2020178
>bf8c007f
>d2820007
>042c0907
>c202017c
>bf8c007f
>d2820007
>041c090a
>c2020180
>bf8c007f
>d2820007
>041c0908
>d2060807
>02010107
>c2020123
>bf8c007f
>d2060808
>02010004
>f800020f
>08060907
>d2060105
>02010105
>bf8c070f
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL OUT[5], GENERIC[2]
>DCL CONST[0..27]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD TEMP[3], TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: SUB TEMP[5], CONST[23], TEMP[4]
> 59: DP3 TEMP[7], TEMP[5], TEMP[5]
> 60: RSQ TEMP[7], |TEMP[7]|
> 61: MUL TEMP[5], TEMP[5], TEMP[7]
> 62: RCP TEMP[7].yz, TEMP[7]
> 63: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 64: DP3 TEMP[7], CONST[24], TEMP[7]
> 65: RCP TEMP[8], TEMP[7]
> 66: SUB TEMP[7], TEMP[5], TEMP[6]
> 67: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 68: RSQ TEMP[9].x, |TEMP[9]|
> 69: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 70: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 71: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 72: LIT TEMP[1], TEMP[2]
> 73: MUL TEMP[1], TEMP[1], TEMP[8]
> 74: MAD TEMP[3], TEMP[1].xxxx, CONST[25], TEMP[3]
> 75: MAD TEMP[3], TEMP[1].yyyy, CONST[26], TEMP[3]
> 76: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[27], TEMP[3]
> 77: ABS OUT[2].x, TEMP[4].zzzz
> 78: MOV OUT[2].yzw, IMM[0].xxxy
> 79: MOV OUT[3], IN[2]
> 80: DP3 TEMP[1], TEMP[0], TEMP[6]
> 81: ADD TEMP[1], TEMP[1], TEMP[1]
> 82: MAD OUT[4].xyz, -TEMP[1], TEMP[0], TEMP[6]
> 83: MOV OUT[4].w, IN[3]
> 84: MOV OUT[5], IN[4]
> 85: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %98 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %99 = load <16 x i8> addrspace(2)* %98, !tbaa !0
>  %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %99, i32 0, i32 %5)
>  %101 = extractelement <4 x float> %100, i32 0
>  %102 = extractelement <4 x float> %100, i32 1
>  %103 = extractelement <4 x float> %100, i32 2
>  %104 = extractelement <4 x float> %100, i32 3
>  %105 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %106 = load <16 x i8> addrspace(2)* %105, !tbaa !0
>  %107 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %106, i32 0, i32 %5)
>  %108 = extractelement <4 x float> %107, i32 0
>  %109 = extractelement <4 x float> %107, i32 1
>  %110 = extractelement <4 x float> %107, i32 2
>  %111 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %112 = load <16 x i8> addrspace(2)* %111, !tbaa !0
>  %113 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %112, i32 0, i32 %5)
>  %114 = extractelement <4 x float> %113, i32 0
>  %115 = extractelement <4 x float> %113, i32 1
>  %116 = extractelement <4 x float> %113, i32 2
>  %117 = extractelement <4 x float> %113, i32 3
>  %118 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %119 = load <16 x i8> addrspace(2)* %118, !tbaa !0
>  %120 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %119, i32 0, i32 %5)
>  %121 = extractelement <4 x float> %120, i32 3
>  %122 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
>  %124 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %123, i32 0, i32 %5)
>  %125 = extractelement <4 x float> %124, i32 0
>  %126 = extractelement <4 x float> %124, i32 1
>  %127 = extractelement <4 x float> %124, i32 2
>  %128 = extractelement <4 x float> %124, i32 3
>  %129 = fmul float %101, %11
>  %130 = fmul float %101, %12
>  %131 = fmul float %101, %13
>  %132 = fmul float %101, %14
>  %133 = fmul float %102, %15
>  %134 = fadd float %133, %129
>  %135 = fmul float %102, %16
>  %136 = fadd float %135, %130
>  %137 = fmul float %102, %17
>  %138 = fadd float %137, %131
>  %139 = fmul float %102, %18
>  %140 = fadd float %139, %132
>  %141 = fmul float %103, %19
>  %142 = fadd float %141, %134
>  %143 = fmul float %103, %20
>  %144 = fadd float %143, %136
>  %145 = fmul float %103, %21
>  %146 = fadd float %145, %138
>  %147 = fmul float %103, %22
>  %148 = fadd float %147, %140
>  %149 = fmul float %104, %23
>  %150 = fadd float %149, %142
>  %151 = fmul float %104, %24
>  %152 = fadd float %151, %144
>  %153 = fmul float %104, %25
>  %154 = fadd float %153, %146
>  %155 = fmul float %104, %26
>  %156 = fadd float %155, %148
>  %157 = fmul float %108, %27
>  %158 = fmul float %109, %28
>  %159 = fadd float %158, %157
>  %160 = fmul float %110, %29
>  %161 = fadd float %159, %160
>  %162 = fmul float %108, %30
>  %163 = fmul float %109, %31
>  %164 = fadd float %163, %162
>  %165 = fmul float %110, %32
>  %166 = fadd float %164, %165
>  %167 = fmul float %108, %33
>  %168 = fmul float %109, %34
>  %169 = fadd float %168, %167
>  %170 = fmul float %110, %35
>  %171 = fadd float %169, %170
>  %172 = fmul float %161, %161
>  %173 = fmul float %166, %166
>  %174 = fadd float %173, %172
>  %175 = fmul float %171, %171
>  %176 = fadd float %174, %175
>  %177 = call float @fabs(float %176)
>  %178 = call float @llvm.AMDGPU.rsq(float %177)
>  %179 = fmul float %161, %178
>  %180 = fmul float %166, %178
>  %181 = fmul float %171, %178
>  %182 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %183 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %184 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %185 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %186 = fmul float %101, %44
>  %187 = fmul float %101, %45
>  %188 = fmul float %101, %46
>  %189 = fmul float %102, %47
>  %190 = fadd float %189, %186
>  %191 = fmul float %102, %48
>  %192 = fadd float %191, %187
>  %193 = fmul float %102, %49
>  %194 = fadd float %193, %188
>  %195 = fmul float %103, %50
>  %196 = fadd float %195, %190
>  %197 = fmul float %103, %51
>  %198 = fadd float %197, %192
>  %199 = fmul float %103, %52
>  %200 = fadd float %199, %194
>  %201 = fmul float %104, %53
>  %202 = fadd float %201, %196
>  %203 = fmul float %104, %54
>  %204 = fadd float %203, %198
>  %205 = fmul float %104, %55
>  %206 = fadd float %205, %200
>  %207 = fsub float %41, %202
>  %208 = fsub float %42, %204
>  %209 = fsub float %43, %206
>  %210 = fmul float %207, %207
>  %211 = fmul float %208, %208
>  %212 = fadd float %211, %210
>  %213 = fmul float %209, %209
>  %214 = fadd float %212, %213
>  %215 = call float @fabs(float %214)
>  %216 = call float @llvm.AMDGPU.rsq(float %215)
>  %217 = fmul float %207, %216
>  %218 = fmul float %208, %216
>  %219 = fmul float %209, %216
>  %220 = fdiv float 1.000000e+00, %216
>  %221 = fmul float %216, %220
>  %222 = fmul float %220, %220
>  %223 = fmul float %56, %221
>  %224 = fmul float %57, %220
>  %225 = fadd float %224, %223
>  %226 = fmul float %58, %222
>  %227 = fadd float %225, %226
>  %228 = fdiv float 1.000000e+00, %227
>  %229 = fmul float %202, %202
>  %230 = fmul float %204, %204
>  %231 = fadd float %230, %229
>  %232 = fmul float %206, %206
>  %233 = fadd float %231, %232
>  %234 = call float @fabs(float %233)
>  %235 = call float @llvm.AMDGPU.rsq(float %234)
>  %236 = fmul float %202, %235
>  %237 = fmul float %204, %235
>  %238 = fmul float %206, %235
>  %239 = fsub float %217, %236
>  %240 = fsub float %218, %237
>  %241 = fsub float %219, %238
>  %242 = fmul float %239, %239
>  %243 = fmul float %240, %240
>  %244 = fadd float %243, %242
>  %245 = fmul float %241, %241
>  %246 = fadd float %244, %245
>  %247 = call float @fabs(float %246)
>  %248 = call float @llvm.AMDGPU.rsq(float %247)
>  %249 = fmul float %239, %248
>  %250 = fmul float %240, %248
>  %251 = fmul float %241, %248
>  %252 = fmul float %179, %217
>  %253 = fmul float %180, %218
>  %254 = fadd float %253, %252
>  %255 = fmul float %181, %219
>  %256 = fadd float %254, %255
>  %257 = fmul float %179, %249
>  %258 = fmul float %180, %250
>  %259 = fadd float %258, %257
>  %260 = fmul float %181, %251
>  %261 = fadd float %259, %260
>  %262 = fcmp uge float %256, 0.000000e+00
>  %263 = select i1 %262, float %256, float 0.000000e+00
>  %264 = fcmp uge float %261, 0.000000e+00
>  %265 = select i1 %264, float %261, float 0.000000e+00
>  %266 = call float @llvm.pow.f32(float %265, float %36)
>  %267 = call float @llvm.AMDGPU.cndlt(float %256, float 0.000000e+00, float %266)
>  %268 = fmul float 1.000000e+00, %228
>  %269 = fmul float %263, %228
>  %270 = fmul float %267, %228
>  %271 = fmul float %268, %59
>  %272 = fadd float %271, %37
>  %273 = fmul float %268, %60
>  %274 = fadd float %273, %38
>  %275 = fmul float %268, %61
>  %276 = fadd float %275, %39
>  %277 = fmul float %269, %62
>  %278 = fadd float %277, %272
>  %279 = fmul float %269, %63
>  %280 = fadd float %279, %274
>  %281 = fmul float %269, %64
>  %282 = fadd float %281, %276
>  %283 = fmul float %270, %65
>  %284 = fadd float %283, %278
>  %285 = fmul float %270, %66
>  %286 = fadd float %285, %280
>  %287 = fmul float %270, %67
>  %288 = fadd float %287, %282
>  %289 = fsub float %68, %202
>  %290 = fsub float %69, %204
>  %291 = fsub float %70, %206
>  %292 = fmul float %289, %289
>  %293 = fmul float %290, %290
>  %294 = fadd float %293, %292
>  %295 = fmul float %291, %291
>  %296 = fadd float %294, %295
>  %297 = call float @fabs(float %296)
>  %298 = call float @llvm.AMDGPU.rsq(float %297)
>  %299 = fmul float %289, %298
>  %300 = fmul float %290, %298
>  %301 = fmul float %291, %298
>  %302 = fdiv float 1.000000e+00, %298
>  %303 = fmul float %298, %302
>  %304 = fmul float %302, %302
>  %305 = fmul float %71, %303
>  %306 = fmul float %72, %302
>  %307 = fadd float %306, %305
>  %308 = fmul float %73, %304
>  %309 = fadd float %307, %308
>  %310 = fdiv float 1.000000e+00, %309
>  %311 = fsub float %299, %236
>  %312 = fsub float %300, %237
>  %313 = fsub float %301, %238
>  %314 = fmul float %311, %311
>  %315 = fmul float %312, %312
>  %316 = fadd float %315, %314
>  %317 = fmul float %313, %313
>  %318 = fadd float %316, %317
>  %319 = call float @fabs(float %318)
>  %320 = call float @llvm.AMDGPU.rsq(float %319)
>  %321 = fmul float %311, %320
>  %322 = fmul float %312, %320
>  %323 = fmul float %313, %320
>  %324 = fmul float %179, %299
>  %325 = fmul float %180, %300
>  %326 = fadd float %325, %324
>  %327 = fmul float %181, %301
>  %328 = fadd float %326, %327
>  %329 = fmul float %179, %321
>  %330 = fmul float %180, %322
>  %331 = fadd float %330, %329
>  %332 = fmul float %181, %323
>  %333 = fadd float %331, %332
>  %334 = fcmp uge float %328, 0.000000e+00
>  %335 = select i1 %334, float %328, float 0.000000e+00
>  %336 = fcmp uge float %333, 0.000000e+00
>  %337 = select i1 %336, float %333, float 0.000000e+00
>  %338 = call float @llvm.pow.f32(float %337, float %36)
>  %339 = call float @llvm.AMDGPU.cndlt(float %328, float 0.000000e+00, float %338)
>  %340 = fmul float 1.000000e+00, %310
>  %341 = fmul float %335, %310
>  %342 = fmul float %339, %310
>  %343 = fmul float %340, %74
>  %344 = fadd float %343, %284
>  %345 = fmul float %340, %75
>  %346 = fadd float %345, %286
>  %347 = fmul float %340, %76
>  %348 = fadd float %347, %288
>  %349 = fmul float %341, %77
>  %350 = fadd float %349, %344
>  %351 = fmul float %341, %78
>  %352 = fadd float %351, %346
>  %353 = fmul float %341, %79
>  %354 = fadd float %353, %348
>  %355 = fmul float %342, %80
>  %356 = fadd float %355, %350
>  %357 = fmul float %342, %81
>  %358 = fadd float %357, %352
>  %359 = fmul float %342, %82
>  %360 = fadd float %359, %354
>  %361 = fsub float %83, %202
>  %362 = fsub float %84, %204
>  %363 = fsub float %85, %206
>  %364 = fmul float %361, %361
>  %365 = fmul float %362, %362
>  %366 = fadd float %365, %364
>  %367 = fmul float %363, %363
>  %368 = fadd float %366, %367
>  %369 = call float @fabs(float %368)
>  %370 = call float @llvm.AMDGPU.rsq(float %369)
>  %371 = fmul float %361, %370
>  %372 = fmul float %362, %370
>  %373 = fmul float %363, %370
>  %374 = fdiv float 1.000000e+00, %370
>  %375 = fmul float %370, %374
>  %376 = fmul float %374, %374
>  %377 = fmul float %86, %375
>  %378 = fmul float %87, %374
>  %379 = fadd float %378, %377
>  %380 = fmul float %88, %376
>  %381 = fadd float %379, %380
>  %382 = fdiv float 1.000000e+00, %381
>  %383 = fsub float %371, %236
>  %384 = fsub float %372, %237
>  %385 = fsub float %373, %238
>  %386 = fmul float %383, %383
>  %387 = fmul float %384, %384
>  %388 = fadd float %387, %386
>  %389 = fmul float %385, %385
>  %390 = fadd float %388, %389
>  %391 = call float @fabs(float %390)
>  %392 = call float @llvm.AMDGPU.rsq(float %391)
>  %393 = fmul float %383, %392
>  %394 = fmul float %384, %392
>  %395 = fmul float %385, %392
>  %396 = fmul float %179, %371
>  %397 = fmul float %180, %372
>  %398 = fadd float %397, %396
>  %399 = fmul float %181, %373
>  %400 = fadd float %398, %399
>  %401 = fmul float %179, %393
>  %402 = fmul float %180, %394
>  %403 = fadd float %402, %401
>  %404 = fmul float %181, %395
>  %405 = fadd float %403, %404
>  %406 = fcmp uge float %400, 0.000000e+00
>  %407 = select i1 %406, float %400, float 0.000000e+00
>  %408 = fcmp uge float %405, 0.000000e+00
>  %409 = select i1 %408, float %405, float 0.000000e+00
>  %410 = call float @llvm.pow.f32(float %409, float %36)
>  %411 = call float @llvm.AMDGPU.cndlt(float %400, float 0.000000e+00, float %410)
>  %412 = fmul float 1.000000e+00, %382
>  %413 = fmul float %407, %382
>  %414 = fmul float %411, %382
>  %415 = fmul float %412, %89
>  %416 = fadd float %415, %356
>  %417 = fmul float %412, %90
>  %418 = fadd float %417, %358
>  %419 = fmul float %412, %91
>  %420 = fadd float %419, %360
>  %421 = fmul float %413, %92
>  %422 = fadd float %421, %416
>  %423 = fmul float %413, %93
>  %424 = fadd float %423, %418
>  %425 = fmul float %413, %94
>  %426 = fadd float %425, %420
>  %427 = fmul float %414, %95
>  %428 = fadd float %427, %422
>  %429 = fmul float %414, %96
>  %430 = fadd float %429, %424
>  %431 = fmul float %414, %97
>  %432 = fadd float %431, %426
>  %433 = call float @llvm.AMDIL.clamp.(float %428, float 0.000000e+00, float 1.000000e+00)
>  %434 = call float @llvm.AMDIL.clamp.(float %430, float 0.000000e+00, float 1.000000e+00)
>  %435 = call float @llvm.AMDIL.clamp.(float %432, float 0.000000e+00, float 1.000000e+00)
>  %436 = call float @fabs(float %206)
>  %437 = fmul float %179, %236
>  %438 = fmul float %180, %237
>  %439 = fadd float %438, %437
>  %440 = fmul float %181, %238
>  %441 = fadd float %439, %440
>  %442 = fadd float %441, %441
>  %443 = fadd float %441, %441
>  %444 = fadd float %441, %441
>  %445 = fsub float -0.000000e+00, %442
>  %446 = fmul float %445, %179
>  %447 = fadd float %446, %236
>  %448 = fsub float -0.000000e+00, %443
>  %449 = fmul float %448, %180
>  %450 = fadd float %449, %237
>  %451 = fsub float -0.000000e+00, %444
>  %452 = fmul float %451, %181
>  %453 = fadd float %452, %238
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %433, float %434, float %435, float %185)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %436, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %114, float %115, float %116, float %117)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %447, float %450, float %453, float %121)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %125, float %126, float %127, float %128)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %150, float %152, float %154, float %156)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>04380913
>c2020164
>bf8c007f
>d282000c
>0438090c
>c2020168
>bf8c007f
>d282000c
>0430090d
>c202016c
>bf8c007f
>d282000c
>04300915
>d206080c
>0201010c
>c2020123
>bf8c007f
>d206080d
>02010004
>f800020f
>0d14160c
>d2060107
>02010107
>bf8c070f
>7e1802f2
>7e1a0280
>f800021f
>0c0d0d07
>c0840708
>bf8c000f
>e00c2000
>80020c00
>bf8c0770
>f800022f
>0f0e0d0c
>100e0d09
>d2820007
>041e0b0a
>d2820007
>041e110b
>bf8c070f
>06180f07
>100e170c
>080e0f08
>1010150c
>080a1105
>1010130c
>080c1106
>c084070c
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800023f
>0b070506
>c0820710
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800024f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..14]
>DCL TEMP[0..3]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: DP4 TEMP[1], IN[0], CONST[13]
> 15: ABS OUT[2].x, TEMP[1]
> 16: MOV OUT[2].yzw, IMM[0].xxxy
> 17: MOV OUT[3], IN[3]
> 18: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
>  %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %5)
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = extractelement <4 x float> %62, i32 1
>  %65 = extractelement <4 x float> %62, i32 2
>  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
>  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
>  %69 = extractelement <4 x float> %68, i32 0
>  %70 = extractelement <4 x float> %68, i32 1
>  %71 = extractelement <4 x float> %68, i32 2
>  %72 = extractelement <4 x float> %68, i32 3
>  %73 = fmul float %50, %11
>  %74 = fmul float %50, %12
>  %75 = fmul float %50, %13
>  %76 = fmul float %50, %14
>  %77 = fmul float %51, %15
>  %78 = fadd float %77, %73
>  %79 = fmul float %51, %16
>  %80 = fadd float %79, %74
>  %81 = fmul float %51, %17
>  %82 = fadd float %81, %75
>  %83 = fmul float %51, %18
>  %84 = fadd float %83, %76
>  %85 = fmul float %52, %19
>  %86 = fadd float %85, %78
>  %87 = fmul float %52, %20
>  %88 = fadd float %87, %80
>  %89 = fmul float %52, %21
>  %90 = fadd float %89, %82
>  %91 = fmul float %52, %22
>  %92 = fadd float %91, %84
>  %93 = fmul float %53, %23
>  %94 = fadd float %93, %86
>  %95 = fmul float %53, %24
>  %96 = fadd float %95, %88
>  %97 = fmul float %53, %25
>  %98 = fadd float %97, %90
>  %99 = fmul float %53, %26
>  %100 = fadd float %99, %92
>  %101 = fmul float %57, %27
>  %102 = fmul float %58, %28
>  %103 = fadd float %102, %101
>  %104 = fmul float %59, %29
>  %105 = fadd float %103, %104
>  %106 = fmul float %57, %30
>  %107 = fmul float %58, %31
>  %108 = fadd float %107, %106
>  %109 = fmul float %59, %32
>  %110 = fadd float %108, %109
>  %111 = fmul float %57, %33
>  %112 = fmul float %58, %34
>  %113 = fadd float %112, %111
>  %114 = fmul float %59, %35
>  %115 = fadd float %113, %114
>  %116 = fmul float %105, %105
>  %117 = fmul float %110, %110
>  %118 = fadd float %117, %116
>  %119 = fmul float %115, %115
>  %120 = fadd float %118, %119
>  %121 = call float @fabs(float %120)
>  %122 = call float @llvm.AMDGPU.rsq(float %121)
>  %123 = fmul float %36, %39
>  %124 = fadd float %123, %63
>  %125 = fmul float %37, %40
>  %126 = fadd float %125, %64
>  %127 = fmul float %38, %41
>  %128 = fadd float %127, %65
>  %129 = call float @llvm.AMDIL.clamp.(float %124, float 0.000000e+00, float 1.000000e+00)
>  %130 = call float @llvm.AMDIL.clamp.(float %126, float 0.000000e+00, float 1.000000e+00)
>  %131 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
>  %132 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %133 = fmul float %50, %43
>  %134 = fmul float %51, %44
>  %135 = fadd float %133, %134
>  %136 = fmul float %52, %45
>  %137 = fadd float %135, %136
>  %138 = fmul float %53, %46
>  %139 = fadd float %137, %138
>  %140 = call float @fabs(float %139)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %129, float %130, float %131, float %132)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %140, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %69, float %70, float %71, float %72)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %94, float %96, float %98, float %100)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c0840700
>bf8c000f
>e00c2000
>80020100
>c2020135
>bf8c0070
>100a0404
>c2020134
>bf8c007f
>d2820005
>04140901
>c2020136
>bf8c007f
>d2820005
>04140903
>c2020137
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], FOG, PERSPECTIVE
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL IN[2], GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[2..6]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[1], 2D
>  3: TXP TEMP[1].w, IN[2], SAMP[0], CUBE
>  4: ADD TEMP[2].x, IMM[0].xxxx, -TEMP[1].wwww
>  5: MUL TEMP[1], TEMP[0], TEMP[1].wwww
>  6: MAD TEMP[1].xyz, CONST[4], TEMP[2].xxxx, TEMP[1]
>  7: MOV TEMP[0].w, TEMP[0].wwww
>  8: MAD_SAT TEMP[2].x, IN[0].xxxx, CONST[2].xxxx, CONST[2].yyyy
>  9: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].xxxx
> 10: MUL TEMP[3].xyz, CONST[5].xyzz, TEMP[3].xxxx
> 11: MAD TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 12: MOV OUT[0], TEMP[0]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88)
>  %30 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %31 = load <32 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0
>  %34 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %35 = load <32 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
>  %38 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %39 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %40 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %46 = fdiv float %39, %41
>  %47 = fdiv float %40, %41
>  %48 = bitcast float %46 to i32
>  %49 = bitcast float %47 to i32
>  %50 = insertelement <2 x i32> undef, i32 %48, i32 0
>  %51 = insertelement <2 x i32> %50, i32 %49, i32 1
>  %52 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %51, <32 x i8> %35, <16 x i8> %37, i32 2)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = fdiv float %42, %45
>  %58 = fdiv float %43, %45
>  %59 = fdiv float %44, %45
>  %60 = insertelement <4 x float> undef, float %57, i32 0
>  %61 = insertelement <4 x float> %60, float %58, i32 1
>  %62 = insertelement <4 x float> %61, float %59, i32 2
>  %63 = insertelement <4 x float> %62, float 1.000000e+00, i32 3
>  %64 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %63)
>  %65 = extractelement <4 x float> %64, i32 0
>  %66 = extractelement <4 x float> %64, i32 1
>  %67 = extractelement <4 x float> %64, i32 2
>  %68 = extractelement <4 x float> %64, i32 3
>  %69 = call float @fabs(float %67)
>  %70 = fdiv float 1.000000e+00, %69
>  %71 = fmul float %65, %70
>  %72 = fadd float %71, 1.500000e+00
>  %73 = fmul float %66, %70
>  %74 = fadd float %73, 1.500000e+00
>  %75 = bitcast float %74 to i32
>  %76 = bitcast float %72 to i32
>  %77 = bitcast float %68 to i32
>  %78 = insertelement <4 x i32> undef, i32 %75, i32 0
>  %79 = insertelement <4 x i32> %78, i32 %76, i32 1
>  %80 = insertelement <4 x i32> %79, i32 %77, i32 2
>  %81 = insertelement <4 x i32> %80, i32 undef, i32 3
>  %82 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %81, <32 x i8> %31, <16 x i8> %33, i32 4)
>  %83 = extractelement <4 x float> %82, i32 3
>  %84 = fsub float -0.000000e+00, %83
>  %85 = fadd float 1.000000e+00, %84
>  %86 = fmul float %53, %83
>  %87 = fmul float %54, %83
>  %88 = fmul float %55, %83
>  %89 = fmul float %24, %85
>  %90 = fadd float %89, %86
>  %91 = fmul float %25, %85
>  %92 = fadd float %91, %87
>  %93 = fmul float %26, %85
>  %94 = fadd float %93, %88
>  %95 = fmul float %38, %22
>  %96 = fadd float %95, %23
>  %97 = call float @llvm.AMDIL.clamp.(float %96, float 0.000000e+00, float 1.000000e+00)
>  %98 = fsub float -0.000000e+00, %97
>  %99 = fadd float 1.000000e+00, %98
>  %100 = fmul float %27, %99
>  %101 = fmul float %28, %99
>  %102 = fmul float %29, %99
>  %103 = fmul float %90, %97
>  %104 = fadd float %103, %100
>  %105 = fmul float %92, %97
>  %106 = fadd float %105, %101
>  %107 = fmul float %94, %97
>  %108 = fadd float %107, %102
>  %109 = call i32 @llvm.SI.packf16(float %104, float %106)
>  %110 = bitcast i32 %109 to float
>  %111 = call i32 @llvm.SI.packf16(float %108, float %56)
>  %112 = bitcast i32 %111 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %110, float %112, float %110, float %112)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: readnone
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e0c5503
>10060d02
>c81c0800
>c81d0801
>10040d07
>c81c0a00
>c81d0a01
>10080d07
>7e0a02f2
>d28a0007
>04120702
>d28c0006
>04120702
>d28e0008
>04120702
>d2880009
>04120702
>d2060102
>02010108
>7e045502
>7e0602ff
>3fc00000
>d2820008
>040e0506
>d2820007
>040e0507
>c0840300
>c0c60500
>bf8c007f
>f0800800
>00430207
>c80c0500
>c80d0501
>c8100700
>c8110701
>7e0a5504
>10080b03
>c8180400
>c8190401
>10060b06
>c0840304
>c0c60508
>bf8c0070
>f0800f00
>00430303
>bf8c0770
>10100504
>080e04f2
>c0800100
>bf8c007f
>c2020111
>bf8c007f
>d2820008
>04220e04
>c8240000
>c8250001
>c2020108
>c2028109
>bf8c007f
>7e000205
>d2820000
>04000909
>d2060800
>02010100
>080200f2
>c2020115
>bf8c007f
>10120204
>d2820008
>04260108
>10120503
>c2020110
>bf8c007f
>d2820009
>04260e04
>c2020114
>bf8c007f
>10140204
>d2820009
>042a0109
>5e101109
>10040505
>c2020112
>bf8c007f
>d2820002
>040a0e04
>c2000116
>bf8c007f
>10020200
>d2820000
>04060102
>5e000d00
>f8001c0f
>00080008
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], FOG
>DCL OUT[2], GENERIC[0]
>DCL OUT[3], GENERIC[1]
>DCL CONST[0..7]
>DCL CONST[9..22]
>DCL TEMP[0..3]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP4 TEMP[0], IN[0], CONST[6]
>  5: ABS OUT[1].x, TEMP[0]
>  6: MOV OUT[1].yzw, IMM[0].xxxy
>  7: DP4 TEMP[1].x, IN[0], CONST[9]
>  8: DP4 TEMP[1].y, IN[0], CONST[10]
>  9: DP4 TEMP[1].z, IN[0], CONST[11]
> 10: MOV TEMP[1].w, IN[2]
> 11: MUL TEMP[2], TEMP[1].xxxx, CONST[12]
> 12: MAD TEMP[2], TEMP[1].yyyy, CONST[13], TEMP[2]
> 13: MAD TEMP[2], TEMP[1].zzzz, CONST[14], TEMP[2]
> 14: MAD OUT[2], TEMP[1].wwww, CONST[15], TEMP[2]
> 15: DP3 TEMP[2].x, IN[1], CONST[16]
> 16: DP3 TEMP[2].y, IN[1], CONST[17]
> 17: DP3 TEMP[2].z, IN[1], CONST[18]
> 18: DP3 TEMP[3].x, TEMP[2], TEMP[2]
> 19: RSQ TEMP[3].x, |TEMP[3]|
> 20: MUL TEMP[2], TEMP[2], TEMP[3].xxxx
> 21: MOV TEMP[1].xyz, TEMP[2]
> 22: MOV TEMP[1].w, IN[3]
> 23: MUL TEMP[3], TEMP[1].xxxx, CONST[19]
> 24: MAD TEMP[3], TEMP[1].yyyy, CONST[20], TEMP[3]
> 25: MAD TEMP[3], TEMP[1].zzzz, CONST[21], TEMP[3]
> 26: MAD OUT[3], TEMP[1].wwww, CONST[22], TEMP[3]
> 27: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 252)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %84 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %85 = load <16 x i8> addrspace(2)* %84, !tbaa !0
>  %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %85, i32 0, i32 %5)
>  %87 = extractelement <4 x float> %86, i32 0
>  %88 = extractelement <4 x float> %86, i32 1
>  %89 = extractelement <4 x float> %86, i32 2
>  %90 = extractelement <4 x float> %86, i32 3
>  %91 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0
>  %93 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %92, i32 0, i32 %5)
>  %94 = extractelement <4 x float> %93, i32 0
>  %95 = extractelement <4 x float> %93, i32 1
>  %96 = extractelement <4 x float> %93, i32 2
>  %97 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %98 = load <16 x i8> addrspace(2)* %97, !tbaa !0
>  %99 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %98, i32 0, i32 %5)
>  %100 = extractelement <4 x float> %99, i32 3
>  %101 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %102 = load <16 x i8> addrspace(2)* %101, !tbaa !0
>  %103 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %102, i32 0, i32 %5)
>  %104 = extractelement <4 x float> %103, i32 3
>  %105 = fmul float %87, %11
>  %106 = fmul float %87, %12
>  %107 = fmul float %87, %13
>  %108 = fmul float %87, %14
>  %109 = fmul float %88, %15
>  %110 = fadd float %109, %105
>  %111 = fmul float %88, %16
>  %112 = fadd float %111, %106
>  %113 = fmul float %88, %17
>  %114 = fadd float %113, %107
>  %115 = fmul float %88, %18
>  %116 = fadd float %115, %108
>  %117 = fmul float %89, %19
>  %118 = fadd float %117, %110
>  %119 = fmul float %89, %20
>  %120 = fadd float %119, %112
>  %121 = fmul float %89, %21
>  %122 = fadd float %121, %114
>  %123 = fmul float %89, %22
>  %124 = fadd float %123, %116
>  %125 = fmul float %90, %23
>  %126 = fadd float %125, %118
>  %127 = fmul float %90, %24
>  %128 = fadd float %127, %120
>  %129 = fmul float %90, %25
>  %130 = fadd float %129, %122
>  %131 = fmul float %90, %26
>  %132 = fadd float %131, %124
>  %133 = fmul float %87, %27
>  %134 = fmul float %88, %28
>  %135 = fadd float %133, %134
>  %136 = fmul float %89, %29
>  %137 = fadd float %135, %136
>  %138 = fmul float %90, %30
>  %139 = fadd float %137, %138
>  %140 = call float @fabs(float %139)
>  %141 = fmul float %87, %31
>  %142 = fmul float %88, %32
>  %143 = fadd float %141, %142
>  %144 = fmul float %89, %33
>  %145 = fadd float %143, %144
>  %146 = fmul float %90, %34
>  %147 = fadd float %145, %146
>  %148 = fmul float %87, %35
>  %149 = fmul float %88, %36
>  %150 = fadd float %148, %149
>  %151 = fmul float %89, %37
>  %152 = fadd float %150, %151
>  %153 = fmul float %90, %38
>  %154 = fadd float %152, %153
>  %155 = fmul float %87, %39
>  %156 = fmul float %88, %40
>  %157 = fadd float %155, %156
>  %158 = fmul float %89, %41
>  %159 = fadd float %157, %158
>  %160 = fmul float %90, %42
>  %161 = fadd float %159, %160
>  %162 = fmul float %147, %43
>  %163 = fmul float %147, %44
>  %164 = fmul float %147, %45
>  %165 = fmul float %147, %46
>  %166 = fmul float %154, %47
>  %167 = fadd float %166, %162
>  %168 = fmul float %154, %48
>  %169 = fadd float %168, %163
>  %170 = fmul float %154, %49
>  %171 = fadd float %170, %164
>  %172 = fmul float %154, %50
>  %173 = fadd float %172, %165
>  %174 = fmul float %161, %51
>  %175 = fadd float %174, %167
>  %176 = fmul float %161, %52
>  %177 = fadd float %176, %169
>  %178 = fmul float %161, %53
>  %179 = fadd float %178, %171
>  %180 = fmul float %161, %54
>  %181 = fadd float %180, %173
>  %182 = fmul float %100, %55
>  %183 = fadd float %182, %175
>  %184 = fmul float %100, %56
>  %185 = fadd float %184, %177
>  %186 = fmul float %100, %57
>  %187 = fadd float %186, %179
>  %188 = fmul float %100, %58
>  %189 = fadd float %188, %181
>  %190 = fmul float %94, %59
>  %191 = fmul float %95, %60
>  %192 = fadd float %191, %190
>  %193 = fmul float %96, %61
>  %194 = fadd float %192, %193
>  %195 = fmul float %94, %62
>  %196 = fmul float %95, %63
>  %197 = fadd float %196, %195
>  %198 = fmul float %96, %64
>  %199 = fadd float %197, %198
>  %200 = fmul float %94, %65
>  %201 = fmul float %95, %66
>  %202 = fadd float %201, %200
>  %203 = fmul float %96, %67
>  %204 = fadd float %202, %203
>  %205 = fmul float %194, %194
>  %206 = fmul float %199, %199
>  %207 = fadd float %206, %205
>  %208 = fmul float %204, %204
>  %209 = fadd float %207, %208
>  %210 = call float @fabs(float %209)
>  %211 = call float @llvm.AMDGPU.rsq(float %210)
>  %212 = fmul float %194, %211
>  %213 = fmul float %199, %211
>  %214 = fmul float %204, %211
>  %215 = fmul float %212, %68
>  %216 = fmul float %212, %69
>  %217 = fmul float %212, %70
>  %218 = fmul float %212, %71
>  %219 = fmul float %213, %72
>  %220 = fadd float %219, %215
>  %221 = fmul float %213, %73
>  %222 = fadd float %221, %216
>  %223 = fmul float %213, %74
>  %224 = fadd float %223, %217
>  %225 = fmul float %213, %75
>  %226 = fadd float %225, %218
>  %227 = fmul float %214, %76
>  %228 = fadd float %227, %220
>  %229 = fmul float %214, %77
>  %230 = fadd float %229, %222
>  %231 = fmul float %214, %78
>  %232 = fadd float %231, %224
>  %233 = fmul float %214, %79
>  %234 = fadd float %233, %226
>  %235 = fmul float %104, %80
>  %236 = fadd float %235, %228
>  %237 = fmul float %104, %81
>  %238 = fadd float %237, %230
>  %239 = fmul float %104, %82
>  %240 = fadd float %239, %232
>  %241 = fmul float %104, %83
>  %242 = fadd float %241, %234
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %140, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %183, float %185, float %187, float %189)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %236, float %238, float %240, float %242)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %126, float %128, float %130, float %132)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800020f
>06070705
>c2020129
>bf8c000f
>100a0404
>c2020128
>bf8c007f
>d2820005
>04140901
>c202012a
>bf8c007f
>d2820005
>04140903
>c202012b
>bf8c007f
>d2820005
>04140904
>c2020125
>bf8c007f
>100c0404
>c2020124
>bf8c007f
>d2820006
>04180901
>c2020126
>bf8c007f
>d2820006
>04180903
>c2020127
>bf8c007f
>d2820006
>04180904
>c2020133
>bf8c007f
>100e0c04
>c2020137
>bf8c007f
>d2820008
>041c0905
>c202012d
>bf8c007f
>100e0404
>c202012c
>bf8c007f
>d2820007
>041c0901
>c202012e
>bf8c007f
>d2820007
>041c0903
>c202012f
>bf8c007f
>d2820007
>041c0904
>c202013b
>bf8c007f
>d282000c
>04200907
>c0840708
>bf8c007f
>e00c2000
>80020800
>c202013f
>bf8c0070
>d282000c
>0430090b
>c2020132
>bf8c007f
>101a0c04
>c2020136
>bf8c007f
>d282000d
>04340905
>c202013a
>bf8c007f
>d282000d
>04340907
>c202013e
>bf8c007f
>d282000d
>0434090b
>c2020131
>bf8c007f
>101c0c04
>c2020135
>bf8c007f
>d282000e
>04380905
>c2020139
>bf8c007f
>d282000e
>04380907
>c202013d
>bf8c007f
>d282000e
>0438090b
>c2020130
>bf8c007f
>100c0c04
>c2020134
>bf8c007f
>d2820005
>04180905
>c2020138
>bf8c007f
>d2820005
>04140907
>c202013c
>bf8c007f
>d2820005
>0414090b
>f800021f
>0c0d0e05
>c0840704
>bf8c000f
>e00c2000
>80020500
>c2020144
>bf8c0070
>10120a04
>c2020145
>bf8c007f
>d2820009
>04240906
>c2020146
>bf8c007f
>d2820009
>04240907
>c2020140
>bf8c007f
>10140a04
>c2020141
>bf8c007f
>d282000a
>04280906
>c2020142
>bf8c007f
>d282000a
>04280907
>1016150a
>d282000b
>042e1309
>c2020148
>bf8c007f
>10180a04
>c2020149
>bf8c007f
>d282000c
>04300906
>c202014a
>bf8c007f
>d2820007
>04300907
>d2820005
>042e0f07
>d2060105
>02010105
>7e105b05
>100a1109
>100c110a
>c202014f
>bf8c007f
>10120c04
>c2020153
>bf8c007f
>d2820009
>04240905
>100e1107
>c2020157
>bf8c007f
>d282000c
>04240907
>c082070c
>bf8c007f
>e00c2000
>80010800
>c202015b
>bf8c0070
>d2820000
>0430090b
>c202014e
>bf8c007f
>10180c04
>c2020152
>bf8c007f
>d282000c
>04300905
>c2020156
>bf8c007f
>d282000c
>04300907
>c202015a
>bf8c007f
>d282000c
>0430090b
>c202014d
>bf8c007f
>101a0c04
>c2020151
>bf8c007f
>d282000d
>04340905
>c2020155
>bf8c007f
>d282000d
>04340907
>c2020159
>bf8c007f
>d282000d
>0434090b
>c202014c
>bf8c007f
>100c0c04
>c2020150
>bf8c007f
>d2820005
>04180905
>c2020154
>bf8c007f
>d2820005
>04140907
>c2020158
>bf8c007f
>d2820005
>0414090b
>f800022f
>000c0d05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MOV OUT[3], IN[2]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %5)
>  %34 = extractelement <4 x float> %33, i32 0
>  %35 = extractelement <4 x float> %33, i32 1
>  %36 = extractelement <4 x float> %33, i32 2
>  %37 = extractelement <4 x float> %33, i32 3
>  %38 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %5)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
>  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %5)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  %52 = fmul float %34, %11
>  %53 = fmul float %34, %12
>  %54 = fmul float %34, %13
>  %55 = fmul float %34, %14
>  %56 = fmul float %35, %15
>  %57 = fadd float %56, %52
>  %58 = fmul float %35, %16
>  %59 = fadd float %58, %53
>  %60 = fmul float %35, %17
>  %61 = fadd float %60, %54
>  %62 = fmul float %35, %18
>  %63 = fadd float %62, %55
>  %64 = fmul float %36, %19
>  %65 = fadd float %64, %57
>  %66 = fmul float %36, %20
>  %67 = fadd float %66, %59
>  %68 = fmul float %36, %21
>  %69 = fadd float %68, %61
>  %70 = fmul float %36, %22
>  %71 = fadd float %70, %63
>  %72 = fmul float %37, %23
>  %73 = fadd float %72, %65
>  %74 = fmul float %37, %24
>  %75 = fadd float %74, %67
>  %76 = fmul float %37, %25
>  %77 = fadd float %76, %69
>  %78 = fmul float %37, %26
>  %79 = fadd float %78, %71
>  %80 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
>  %81 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %82 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %83 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %84 = fmul float %34, %27
>  %85 = fmul float %35, %28
>  %86 = fadd float %84, %85
>  %87 = fmul float %36, %29
>  %88 = fadd float %86, %87
>  %89 = fmul float %37, %30
>  %90 = fadd float %88, %89
>  %91 = call float @fabs(float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %80, float %81, float %82, float %83)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %91, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %48, float %49, float %50, float %51)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %73, float %75, float %77, float %79)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..7]
>DCL CONST[9..12]
>DCL TEMP[0..1]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MUL TEMP[1], IN[2].xxxx, CONST[9]
>  9: MAD TEMP[1], IN[2].yyyy, CONST[10], TEMP[1]
> 10: MAD TEMP[1], IN[2].zzzz, CONST[11], TEMP[1]
> 11: MAD OUT[3], IN[2].wwww, CONST[12], TEMP[1]
> 12: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = extractelement <4 x float> %56, i32 3
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 0
>  %65 = extractelement <4 x float> %63, i32 1
>  %66 = extractelement <4 x float> %63, i32 2
>  %67 = extractelement <4 x float> %63, i32 3
>  %68 = fmul float %50, %11
>  %69 = fmul float %50, %12
>  %70 = fmul float %50, %13
>  %71 = fmul float %50, %14
>  %72 = fmul float %51, %15
>  %73 = fadd float %72, %68
>  %74 = fmul float %51, %16
>  %75 = fadd float %74, %69
>  %76 = fmul float %51, %17
>  %77 = fadd float %76, %70
>  %78 = fmul float %51, %18
>  %79 = fadd float %78, %71
>  %80 = fmul float %52, %19
>  %81 = fadd float %80, %73
>  %82 = fmul float %52, %20
>  %83 = fadd float %82, %75
>  %84 = fmul float %52, %21
>  %85 = fadd float %84, %77
>  %86 = fmul float %52, %22
>  %87 = fadd float %86, %79
>  %88 = fmul float %53, %23
>  %89 = fadd float %88, %81
>  %90 = fmul float %53, %24
>  %91 = fadd float %90, %83
>  %92 = fmul float %53, %25
>  %93 = fadd float %92, %85
>  %94 = fmul float %53, %26
>  %95 = fadd float %94, %87
>  %96 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %97 = call float @llvm.AMDIL.clamp.(float %58, float 0.000000e+00, float 1.000000e+00)
>  %98 = call float @llvm.AMDIL.clamp.(float %59, float 0.000000e+00, float 1.000000e+00)
>  %99 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %100 = fmul float %50, %27
>  %101 = fmul float %51, %28
>  %102 = fadd float %100, %101
>  %103 = fmul float %52, %29
>  %104 = fadd float %102, %103
>  %105 = fmul float %53, %30
>  %106 = fadd float %104, %105
>  %107 = call float @fabs(float %106)
>  %108 = fmul float %64, %31
>  %109 = fmul float %64, %32
>  %110 = fmul float %64, %33
>  %111 = fmul float %64, %34
>  %112 = fmul float %65, %35
>  %113 = fadd float %112, %108
>  %114 = fmul float %65, %36
>  %115 = fadd float %114, %109
>  %116 = fmul float %65, %37
>  %117 = fadd float %116, %110
>  %118 = fmul float %65, %38
>  %119 = fadd float %118, %111
>  %120 = fmul float %66, %39
>  %121 = fadd float %120, %113
>  %122 = fmul float %66, %40
>  %123 = fadd float %122, %115
>  %124 = fmul float %66, %41
>  %125 = fadd float %124, %117
>  %126 = fmul float %66, %42
>  %127 = fadd float %126, %119
>  %128 = fmul float %67, %43
>  %129 = fadd float %128, %121
>  %130 = fmul float %67, %44
>  %131 = fadd float %130, %123
>  %132 = fmul float %67, %45
>  %133 = fadd float %132, %125
>  %134 = fmul float %67, %46
>  %135 = fadd float %134, %127
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %96, float %97, float %98, float %99)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %107, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %129, float %131, float %133, float %135)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %89, float %91, float %93, float %95)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>c2020127
>bf8c0070
>10000a04
>c202012b
>bf8c007f
>d2820000
>04000906
>c202012f
>bf8c007f
>d2820000
>04000907
>c2020133
>bf8c007f
>d2820000
>04000908
>c2020126
>bf8c007f
>10120a04
>c202012a
>bf8c007f
>d2820009
>04240906
>c202012e
>bf8c007f
>d2820009
>04240907
>c2020132
>bf8c007f
>d2820009
>04240908
>c2020125
>bf8c007f
>10140a04
>c2020129
>bf8c007f
>d282000a
>04280906
>c202012d
>bf8c007f
>d282000a
>04280907
>c2020131
>bf8c007f
>d282000a
>04280908
>c2020124
>bf8c007f
>10160a04
>c2020128
>bf8c007f
>d282000b
>042c0906
>c202012c
>bf8c007f
>d282000b
>042c0907
>c2020130
>bf8c007f
>d2820005
>042c0908
>f800022f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..14]
>DCL TEMP[0..3]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[10]
> 12: MAD TEMP[3].xyz, CONST[8], CONST[9], IN[2]
> 13: MOV_SAT OUT[1], TEMP[3]
> 14: DP4 TEMP[1], IN[0], CONST[13]
> 15: ABS OUT[2].x, TEMP[1]
> 16: MOV OUT[2].yzw, IMM[0].xxxy
> 17: MOV OUT[3], IN[3]
> 18: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
>  %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %5)
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = extractelement <4 x float> %62, i32 1
>  %65 = extractelement <4 x float> %62, i32 2
>  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
>  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
>  %69 = extractelement <4 x float> %68, i32 0
>  %70 = extractelement <4 x float> %68, i32 1
>  %71 = extractelement <4 x float> %68, i32 2
>  %72 = extractelement <4 x float> %68, i32 3
>  %73 = fmul float %50, %11
>  %74 = fmul float %50, %12
>  %75 = fmul float %50, %13
>  %76 = fmul float %50, %14
>  %77 = fmul float %51, %15
>  %78 = fadd float %77, %73
>  %79 = fmul float %51, %16
>  %80 = fadd float %79, %74
>  %81 = fmul float %51, %17
>  %82 = fadd float %81, %75
>  %83 = fmul float %51, %18
>  %84 = fadd float %83, %76
>  %85 = fmul float %52, %19
>  %86 = fadd float %85, %78
>  %87 = fmul float %52, %20
>  %88 = fadd float %87, %80
>  %89 = fmul float %52, %21
>  %90 = fadd float %89, %82
>  %91 = fmul float %52, %22
>  %92 = fadd float %91, %84
>  %93 = fmul float %53, %23
>  %94 = fadd float %93, %86
>  %95 = fmul float %53, %24
>  %96 = fadd float %95, %88
>  %97 = fmul float %53, %25
>  %98 = fadd float %97, %90
>  %99 = fmul float %53, %26
>  %100 = fadd float %99, %92
>  %101 = fmul float %57, %27
>  %102 = fmul float %58, %28
>  %103 = fadd float %102, %101
>  %104 = fmul float %59, %29
>  %105 = fadd float %103, %104
>  %106 = fmul float %57, %30
>  %107 = fmul float %58, %31
>  %108 = fadd float %107, %106
>  %109 = fmul float %59, %32
>  %110 = fadd float %108, %109
>  %111 = fmul float %57, %33
>  %112 = fmul float %58, %34
>  %113 = fadd float %112, %111
>  %114 = fmul float %59, %35
>  %115 = fadd float %113, %114
>  %116 = fmul float %105, %105
>  %117 = fmul float %110, %110
>  %118 = fadd float %117, %116
>  %119 = fmul float %115, %115
>  %120 = fadd float %118, %119
>  %121 = call float @fabs(float %120)
>  %122 = call float @llvm.AMDGPU.rsq(float %121)
>  %123 = fmul float %36, %39
>  %124 = fadd float %123, %63
>  %125 = fmul float %37, %40
>  %126 = fadd float %125, %64
>  %127 = fmul float %38, %41
>  %128 = fadd float %127, %65
>  %129 = call float @llvm.AMDIL.clamp.(float %124, float 0.000000e+00, float 1.000000e+00)
>  %130 = call float @llvm.AMDIL.clamp.(float %126, float 0.000000e+00, float 1.000000e+00)
>  %131 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
>  %132 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
>  %133 = fmul float %50, %43
>  %134 = fmul float %51, %44
>  %135 = fadd float %133, %134
>  %136 = fmul float %52, %45
>  %137 = fadd float %135, %136
>  %138 = fmul float %53, %46
>  %139 = fadd float %137, %138
>  %140 = call float @fabs(float %139)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %129, float %130, float %131, float %132)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %140, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %69, float %70, float %71, float %72)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %94, float %96, float %98, float %100)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840708
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020122
>c2028126
>bf8c007f
>7e0a0205
>d2820005
>040e0a04
>d2060805
>02010105
>c2020121
>c2028125
>bf8c007f
>7e0c0205
>d2820006
>040a0c04
>d2060806
>02010106
>c2020120
>c2028124
>bf8c007f
>7e0e0205
>d2820001
>04060e04
>d2060801
>02010101
>c202012b
>bf8c007f
>d2060802
>02010004
>f800020f
>02050601
>c0840700
>bf8c000f
>e00c2000
>80020100
>c2020135
>bf8c0070
>100a0404
>c2020134
>bf8c007f
>d2820005
>04140901
>c2020136
>bf8c007f
>d2820005
>04140903
>c2020137
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c082070c
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800022f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], FOG, PERSPECTIVE
>DCL IN[2], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[2].xyyy
>  1: MOV TEMP[0].w, IN[2].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: ADD TEMP[1].x, IMM[0].xxxx, -IN[0].wwww
>  4: MUL TEMP[2], TEMP[0], IN[0].wwww
>  5: MAD TEMP[1].xyz, CONST[2], TEMP[1].xxxx, TEMP[2]
>  6: MOV TEMP[0].w, TEMP[0].wwww
>  7: MAD_SAT TEMP[2].x, IN[1].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  8: ADD TEMP[3].x, IMM[0].xxxx, -TEMP[2].xxxx
>  9: MUL TEMP[3].xyz, CONST[3].xyzz, TEMP[3].xxxx
> 10: MAD TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xxxx, TEMP[3].xyzz
> 11: MOV OUT[0], TEMP[0]
> 12: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %30 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %31 = load <32 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %38 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %39 = fdiv float %36, %38
>  %40 = fdiv float %37, %38
>  %41 = bitcast float %39 to i32
>  %42 = bitcast float %40 to i32
>  %43 = insertelement <2 x i32> undef, i32 %41, i32 0
>  %44 = insertelement <2 x i32> %43, i32 %42, i32 1
>  %45 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %44, <32 x i8> %31, <16 x i8> %33, i32 2)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = fsub float -0.000000e+00, %34
>  %51 = fadd float 1.000000e+00, %50
>  %52 = fmul float %46, %34
>  %53 = fmul float %47, %34
>  %54 = fmul float %48, %34
>  %55 = fmul float %24, %51
>  %56 = fadd float %55, %52
>  %57 = fmul float %25, %51
>  %58 = fadd float %57, %53
>  %59 = fmul float %26, %51
>  %60 = fadd float %59, %54
>  %61 = fmul float %35, %22
>  %62 = fadd float %61, %23
>  %63 = call float @llvm.AMDIL.clamp.(float %62, float 0.000000e+00, float 1.000000e+00)
>  %64 = fsub float -0.000000e+00, %63
>  %65 = fadd float 1.000000e+00, %64
>  %66 = fmul float %27, %65
>  %67 = fmul float %28, %65
>  %68 = fmul float %29, %65
>  %69 = fmul float %56, %63
>  %70 = fadd float %69, %66
>  %71 = fmul float %58, %63
>  %72 = fadd float %71, %67
>  %73 = fmul float %60, %63
>  %74 = fadd float %73, %68
>  %75 = call i32 @llvm.SI.packf16(float %70, float %72)
>  %76 = bitcast i32 %75 to float
>  %77 = call i32 @llvm.SI.packf16(float %74, float %49)
>  %78 = bitcast i32 %77 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %76, float %78, float %76, float %78)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080900
>c8090901
>c80c0b00
>c80d0b01
>7e085503
>10060902
>c8140800
>c8150801
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>c8180300
>c8190301
>bf8c0770
>10100d04
>080e0cf2
>c0800100
>bf8c007f
>c202010a
>bf8c007f
>d2820008
>04220e04
>c8240400
>c8250401
>c2020104
>c2028105
>bf8c007f
>7e000205
>d2820000
>04000909
>d2060800
>02010100
>080200f2
>c202010e
>bf8c007f
>10120204
>d2820008
>04260108
>5e100b08
>10120d03
>c2020109
>bf8c007f
>d2820009
>04260e04
>c202010d
>bf8c007f
>10140204
>d2820009
>042a0109
>10040d02
>c2020108
>bf8c007f
>d2820002
>040a0e04
>c200010c
>bf8c007f
>10020200
>d2820000
>04060102
>5e001300
>f8001c0f
>08000800
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL CONST[0..7]
>DCL CONST[9..12]
>DCL TEMP[0..1]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: DP4 TEMP[0], IN[0], CONST[6]
>  6: ABS OUT[2].x, TEMP[0]
>  7: MOV OUT[2].yzw, IMM[0].xxxy
>  8: MUL TEMP[1], IN[2].xxxx, CONST[9]
>  9: MAD TEMP[1], IN[2].yyyy, CONST[10], TEMP[1]
> 10: MAD TEMP[1], IN[2].zzzz, CONST[11], TEMP[1]
> 11: MAD OUT[3], IN[2].wwww, CONST[12], TEMP[1]
> 12: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = extractelement <4 x float> %56, i32 3
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 0
>  %65 = extractelement <4 x float> %63, i32 1
>  %66 = extractelement <4 x float> %63, i32 2
>  %67 = extractelement <4 x float> %63, i32 3
>  %68 = fmul float %50, %11
>  %69 = fmul float %50, %12
>  %70 = fmul float %50, %13
>  %71 = fmul float %50, %14
>  %72 = fmul float %51, %15
>  %73 = fadd float %72, %68
>  %74 = fmul float %51, %16
>  %75 = fadd float %74, %69
>  %76 = fmul float %51, %17
>  %77 = fadd float %76, %70
>  %78 = fmul float %51, %18
>  %79 = fadd float %78, %71
>  %80 = fmul float %52, %19
>  %81 = fadd float %80, %73
>  %82 = fmul float %52, %20
>  %83 = fadd float %82, %75
>  %84 = fmul float %52, %21
>  %85 = fadd float %84, %77
>  %86 = fmul float %52, %22
>  %87 = fadd float %86, %79
>  %88 = fmul float %53, %23
>  %89 = fadd float %88, %81
>  %90 = fmul float %53, %24
>  %91 = fadd float %90, %83
>  %92 = fmul float %53, %25
>  %93 = fadd float %92, %85
>  %94 = fmul float %53, %26
>  %95 = fadd float %94, %87
>  %96 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
>  %97 = call float @llvm.AMDIL.clamp.(float %58, float 0.000000e+00, float 1.000000e+00)
>  %98 = call float @llvm.AMDIL.clamp.(float %59, float 0.000000e+00, float 1.000000e+00)
>  %99 = call float @llvm.AMDIL.clamp.(float %60, float 0.000000e+00, float 1.000000e+00)
>  %100 = fmul float %50, %27
>  %101 = fmul float %51, %28
>  %102 = fadd float %100, %101
>  %103 = fmul float %52, %29
>  %104 = fadd float %102, %103
>  %105 = fmul float %53, %30
>  %106 = fadd float %104, %105
>  %107 = call float @fabs(float %106)
>  %108 = fmul float %64, %31
>  %109 = fmul float %64, %32
>  %110 = fmul float %64, %33
>  %111 = fmul float %64, %34
>  %112 = fmul float %65, %35
>  %113 = fadd float %112, %108
>  %114 = fmul float %65, %36
>  %115 = fadd float %114, %109
>  %116 = fmul float %65, %37
>  %117 = fadd float %116, %110
>  %118 = fmul float %65, %38
>  %119 = fadd float %118, %111
>  %120 = fmul float %66, %39
>  %121 = fadd float %120, %113
>  %122 = fmul float %66, %40
>  %123 = fadd float %122, %115
>  %124 = fmul float %66, %41
>  %125 = fadd float %124, %117
>  %126 = fmul float %66, %42
>  %127 = fadd float %126, %119
>  %128 = fmul float %67, %43
>  %129 = fadd float %128, %121
>  %130 = fmul float %67, %44
>  %131 = fadd float %130, %123
>  %132 = fmul float %67, %45
>  %133 = fadd float %132, %125
>  %134 = fmul float %67, %46
>  %135 = fadd float %134, %127
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %96, float %97, float %98, float %99)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %107, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %129, float %131, float %133, float %135)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %89, float %91, float %93, float %95)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840700
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020119
>bf8c007f
>100a0404
>c2020118
>bf8c007f
>d2820005
>04140901
>c202011a
>bf8c007f
>d2820005
>04140903
>c202011b
>bf8c007f
>d2820005
>04140904
>d2060105
>02010105
>7e0c02f2
>7e0e0280
>f800021f
>06070705
>c0820708
>bf8c000f
>e00c2000
>80010500
>c2020127
>bf8c0070
>10000a04
>c202012b
>bf8c007f
>d2820000
>04000906
>c202012f
>bf8c007f
>d2820000
>04000907
>c2020133
>bf8c007f
>d2820000
>04000908
>c2020126
>bf8c007f
>10120a04
>c202012a
>bf8c007f
>d2820009
>04240906
>c202012e
>bf8c007f
>d2820009
>04240907
>c2020132
>bf8c007f
>d2820009
>04240908
>c2020125
>bf8c007f
>10140a04
>c2020129
>bf8c007f
>d282000a
>04280906
>c202012d
>bf8c007f
>d282000a
>04280907
>c2020131
>bf8c007f
>d282000a
>04280908
>c2020124
>bf8c007f
>10160a04
>c2020128
>bf8c007f
>d282000b
>042c0906
>c202012c
>bf8c007f
>d282000b
>042c0907
>c2020130
>bf8c007f
>d2820005
>042c0908
>f800022f
>00090a05
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], FOG
>DCL OUT[3], GENERIC[0]
>DCL OUT[4], GENERIC[1]
>DCL OUT[5], GENERIC[2]
>DCL CONST[0..22]
>DCL TEMP[0..9]
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: DP3 TEMP[0].x, IN[1], CONST[4]
>  5: DP3 TEMP[0].y, IN[1], CONST[5]
>  6: DP3 TEMP[0].z, IN[1], CONST[6]
>  7: DP3 TEMP[1].x, TEMP[0], TEMP[0]
>  8: RSQ TEMP[1].x, |TEMP[1]|
>  9: MUL TEMP[0], TEMP[0], TEMP[1].xxxx
> 10: MOV TEMP[2].w, CONST[7].xxxx
> 11: MOV TEMP[3], CONST[8]
> 12: MOV_SAT OUT[1], TEMP[3]
> 13: MUL TEMP[4], IN[0].xxxx, CONST[10]
> 14: MAD TEMP[4], IN[0].yyyy, CONST[11], TEMP[4]
> 15: MAD TEMP[4], IN[0].zzzz, CONST[12], TEMP[4]
> 16: MAD TEMP[4], IN[0].wwww, CONST[13], TEMP[4]
> 17: SUB TEMP[5], CONST[9], TEMP[4]
> 18: DP3 TEMP[6], TEMP[5], TEMP[5]
> 19: RSQ TEMP[6], |TEMP[6]|
> 20: MUL TEMP[5], TEMP[5], TEMP[6]
> 21: RCP TEMP[6].yz, TEMP[6]
> 22: MUL TEMP[6].xz, TEMP[6], TEMP[6].yyyy
> 23: DP3 TEMP[6], CONST[14], TEMP[6]
> 24: RCP TEMP[7], TEMP[6]
> 25: DP3 TEMP[8].x, TEMP[4], TEMP[4]
> 26: RSQ TEMP[8].x, |TEMP[8]|
> 27: MUL TEMP[6], TEMP[4], TEMP[8].xxxx
> 28: SUB TEMP[8], TEMP[5], TEMP[6]
> 29: DP3 TEMP[9].x, TEMP[8], TEMP[8]
> 30: RSQ TEMP[9].x, |TEMP[9]|
> 31: MUL TEMP[8], TEMP[8], TEMP[9].xxxx
> 32: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 33: DP3 TEMP[2].y, TEMP[0], TEMP[8]
> 34: LIT TEMP[1], TEMP[2]
> 35: MUL TEMP[1], TEMP[1], TEMP[7]
> 36: MAD TEMP[3], TEMP[1].xxxx, CONST[15], TEMP[3]
> 37: MAD TEMP[3], TEMP[1].yyyy, CONST[16], TEMP[3]
> 38: MAD TEMP[3], TEMP[1].zzzz, CONST[17], TEMP[3]
> 39: SUB TEMP[5], CONST[18], TEMP[4]
> 40: DP3 TEMP[7], TEMP[5], TEMP[5]
> 41: RSQ TEMP[7], |TEMP[7]|
> 42: MUL TEMP[5], TEMP[5], TEMP[7]
> 43: RCP TEMP[7].yz, TEMP[7]
> 44: MUL TEMP[7].xz, TEMP[7], TEMP[7].yyyy
> 45: DP3 TEMP[7], CONST[19], TEMP[7]
> 46: RCP TEMP[8], TEMP[7]
> 47: SUB TEMP[7], TEMP[5], TEMP[6]
> 48: DP3 TEMP[9].x, TEMP[7], TEMP[7]
> 49: RSQ TEMP[9].x, |TEMP[9]|
> 50: MUL TEMP[7], TEMP[7], TEMP[9].xxxx
> 51: DP3 TEMP[2].x, TEMP[0], TEMP[5]
> 52: DP3 TEMP[2].y, TEMP[0], TEMP[7]
> 53: LIT TEMP[1], TEMP[2]
> 54: MUL TEMP[1], TEMP[1], TEMP[8]
> 55: MAD TEMP[3], TEMP[1].xxxx, CONST[20], TEMP[3]
> 56: MAD TEMP[3], TEMP[1].yyyy, CONST[21], TEMP[3]
> 57: MAD_SAT OUT[1].xyz, TEMP[1].zzzz, CONST[22], TEMP[3]
> 58: ABS OUT[2].x, TEMP[4].zzzz
> 59: MOV OUT[2].yzw, IMM[0].xxxy
> 60: MOV OUT[3], IN[2]
> 61: DP3 TEMP[1], TEMP[0], TEMP[6]
> 62: ADD TEMP[1], TEMP[1], TEMP[1]
> 63: MAD OUT[4].xyz, -TEMP[1], TEMP[0], TEMP[6]
> 64: MOV OUT[4].w, IN[3]
> 65: MOV OUT[5], IN[4]
> 66: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %83 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %84 = load <16 x i8> addrspace(2)* %83, !tbaa !0
>  %85 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %84, i32 0, i32 %5)
>  %86 = extractelement <4 x float> %85, i32 0
>  %87 = extractelement <4 x float> %85, i32 1
>  %88 = extractelement <4 x float> %85, i32 2
>  %89 = extractelement <4 x float> %85, i32 3
>  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
>  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
>  %93 = extractelement <4 x float> %92, i32 0
>  %94 = extractelement <4 x float> %92, i32 1
>  %95 = extractelement <4 x float> %92, i32 2
>  %96 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %97 = load <16 x i8> addrspace(2)* %96, !tbaa !0
>  %98 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %97, i32 0, i32 %5)
>  %99 = extractelement <4 x float> %98, i32 0
>  %100 = extractelement <4 x float> %98, i32 1
>  %101 = extractelement <4 x float> %98, i32 2
>  %102 = extractelement <4 x float> %98, i32 3
>  %103 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %104 = load <16 x i8> addrspace(2)* %103, !tbaa !0
>  %105 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %104, i32 0, i32 %5)
>  %106 = extractelement <4 x float> %105, i32 3
>  %107 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %108 = load <16 x i8> addrspace(2)* %107, !tbaa !0
>  %109 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %108, i32 0, i32 %5)
>  %110 = extractelement <4 x float> %109, i32 0
>  %111 = extractelement <4 x float> %109, i32 1
>  %112 = extractelement <4 x float> %109, i32 2
>  %113 = extractelement <4 x float> %109, i32 3
>  %114 = fmul float %86, %11
>  %115 = fmul float %86, %12
>  %116 = fmul float %86, %13
>  %117 = fmul float %86, %14
>  %118 = fmul float %87, %15
>  %119 = fadd float %118, %114
>  %120 = fmul float %87, %16
>  %121 = fadd float %120, %115
>  %122 = fmul float %87, %17
>  %123 = fadd float %122, %116
>  %124 = fmul float %87, %18
>  %125 = fadd float %124, %117
>  %126 = fmul float %88, %19
>  %127 = fadd float %126, %119
>  %128 = fmul float %88, %20
>  %129 = fadd float %128, %121
>  %130 = fmul float %88, %21
>  %131 = fadd float %130, %123
>  %132 = fmul float %88, %22
>  %133 = fadd float %132, %125
>  %134 = fmul float %89, %23
>  %135 = fadd float %134, %127
>  %136 = fmul float %89, %24
>  %137 = fadd float %136, %129
>  %138 = fmul float %89, %25
>  %139 = fadd float %138, %131
>  %140 = fmul float %89, %26
>  %141 = fadd float %140, %133
>  %142 = fmul float %93, %27
>  %143 = fmul float %94, %28
>  %144 = fadd float %143, %142
>  %145 = fmul float %95, %29
>  %146 = fadd float %144, %145
>  %147 = fmul float %93, %30
>  %148 = fmul float %94, %31
>  %149 = fadd float %148, %147
>  %150 = fmul float %95, %32
>  %151 = fadd float %149, %150
>  %152 = fmul float %93, %33
>  %153 = fmul float %94, %34
>  %154 = fadd float %153, %152
>  %155 = fmul float %95, %35
>  %156 = fadd float %154, %155
>  %157 = fmul float %146, %146
>  %158 = fmul float %151, %151
>  %159 = fadd float %158, %157
>  %160 = fmul float %156, %156
>  %161 = fadd float %159, %160
>  %162 = call float @fabs(float %161)
>  %163 = call float @llvm.AMDGPU.rsq(float %162)
>  %164 = fmul float %146, %163
>  %165 = fmul float %151, %163
>  %166 = fmul float %156, %163
>  %167 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
>  %168 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
>  %169 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
>  %170 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
>  %171 = fmul float %86, %44
>  %172 = fmul float %86, %45
>  %173 = fmul float %86, %46
>  %174 = fmul float %87, %47
>  %175 = fadd float %174, %171
>  %176 = fmul float %87, %48
>  %177 = fadd float %176, %172
>  %178 = fmul float %87, %49
>  %179 = fadd float %178, %173
>  %180 = fmul float %88, %50
>  %181 = fadd float %180, %175
>  %182 = fmul float %88, %51
>  %183 = fadd float %182, %177
>  %184 = fmul float %88, %52
>  %185 = fadd float %184, %179
>  %186 = fmul float %89, %53
>  %187 = fadd float %186, %181
>  %188 = fmul float %89, %54
>  %189 = fadd float %188, %183
>  %190 = fmul float %89, %55
>  %191 = fadd float %190, %185
>  %192 = fsub float %41, %187
>  %193 = fsub float %42, %189
>  %194 = fsub float %43, %191
>  %195 = fmul float %192, %192
>  %196 = fmul float %193, %193
>  %197 = fadd float %196, %195
>  %198 = fmul float %194, %194
>  %199 = fadd float %197, %198
>  %200 = call float @fabs(float %199)
>  %201 = call float @llvm.AMDGPU.rsq(float %200)
>  %202 = fmul float %192, %201
>  %203 = fmul float %193, %201
>  %204 = fmul float %194, %201
>  %205 = fdiv float 1.000000e+00, %201
>  %206 = fmul float %201, %205
>  %207 = fmul float %205, %205
>  %208 = fmul float %56, %206
>  %209 = fmul float %57, %205
>  %210 = fadd float %209, %208
>  %211 = fmul float %58, %207
>  %212 = fadd float %210, %211
>  %213 = fdiv float 1.000000e+00, %212
>  %214 = fmul float %187, %187
>  %215 = fmul float %189, %189
>  %216 = fadd float %215, %214
>  %217 = fmul float %191, %191
>  %218 = fadd float %216, %217
>  %219 = call float @fabs(float %218)
>  %220 = call float @llvm.AMDGPU.rsq(float %219)
>  %221 = fmul float %187, %220
>  %222 = fmul float %189, %220
>  %223 = fmul float %191, %220
>  %224 = fsub float %202, %221
>  %225 = fsub float %203, %222
>  %226 = fsub float %204, %223
>  %227 = fmul float %224, %224
>  %228 = fmul float %225, %225
>  %229 = fadd float %228, %227
>  %230 = fmul float %226, %226
>  %231 = fadd float %229, %230
>  %232 = call float @fabs(float %231)
>  %233 = call float @llvm.AMDGPU.rsq(float %232)
>  %234 = fmul float %224, %233
>  %235 = fmul float %225, %233
>  %236 = fmul float %226, %233
>  %237 = fmul float %164, %202
>  %238 = fmul float %165, %203
>  %239 = fadd float %238, %237
>  %240 = fmul float %166, %204
>  %241 = fadd float %239, %240
>  %242 = fmul float %164, %234
>  %243 = fmul float %165, %235
>  %244 = fadd float %243, %242
>  %245 = fmul float %166, %236
>  %246 = fadd float %244, %245
>  %247 = fcmp uge float %241, 0.000000e+00
>  %248 = select i1 %247, float %241, float 0.000000e+00
>  %249 = fcmp uge float %246, 0.000000e+00
>  %250 = select i1 %249, float %246, float 0.000000e+00
>  %251 = call float @llvm.pow.f32(float %250, float %36)
>  %252 = call float @llvm.AMDGPU.cndlt(float %241, float 0.000000e+00, float %251)
>  %253 = fmul float 1.000000e+00, %213
>  %254 = fmul float %248, %213
>  %255 = fmul float %252, %213
>  %256 = fmul float %253, %59
>  %257 = fadd float %256, %37
>  %258 = fmul float %253, %60
>  %259 = fadd float %258, %38
>  %260 = fmul float %253, %61
>  %261 = fadd float %260, %39
>  %262 = fmul float %254, %62
>  %263 = fadd float %262, %257
>  %264 = fmul float %254, %63
>  %265 = fadd float %264, %259
>  %266 = fmul float %254, %64
>  %267 = fadd float %266, %261
>  %268 = fmul float %255, %65
>  %269 = fadd float %268, %263
>  %270 = fmul float %255, %66
>  %271 = fadd float %270, %265
>  %272 = fmul float %255, %67
>  %273 = fadd float %272, %267
>  %274 = fsub float %68, %187
>  %275 = fsub float %69, %189
>  %276 = fsub float %70, %191
>  %277 = fmul float %274, %274
>  %278 = fmul float %275, %275
>  %279 = fadd float %278, %277
>  %280 = fmul float %276, %276
>  %281 = fadd float %279, %280
>  %282 = call float @fabs(float %281)
>  %283 = call float @llvm.AMDGPU.rsq(float %282)
>  %284 = fmul float %274, %283
>  %285 = fmul float %275, %283
>  %286 = fmul float %276, %283
>  %287 = fdiv float 1.000000e+00, %283
>  %288 = fmul float %283, %287
>  %289 = fmul float %287, %287
>  %290 = fmul float %71, %288
>  %291 = fmul float %72, %287
>  %292 = fadd float %291, %290
>  %293 = fmul float %73, %289
>  %294 = fadd float %292, %293
>  %295 = fdiv float 1.000000e+00, %294
>  %296 = fsub float %284, %221
>  %297 = fsub float %285, %222
>  %298 = fsub float %286, %223
>  %299 = fmul float %296, %296
>  %300 = fmul float %297, %297
>  %301 = fadd float %300, %299
>  %302 = fmul float %298, %298
>  %303 = fadd float %301, %302
>  %304 = call float @fabs(float %303)
>  %305 = call float @llvm.AMDGPU.rsq(float %304)
>  %306 = fmul float %296, %305
>  %307 = fmul float %297, %305
>  %308 = fmul float %298, %305
>  %309 = fmul float %164, %284
>  %310 = fmul float %165, %285
>  %311 = fadd float %310, %309
>  %312 = fmul float %166, %286
>  %313 = fadd float %311, %312
>  %314 = fmul float %164, %306
>  %315 = fmul float %165, %307
>  %316 = fadd float %315, %314
>  %317 = fmul float %166, %308
>  %318 = fadd float %316, %317
>  %319 = fcmp uge float %313, 0.000000e+00
>  %320 = select i1 %319, float %313, float 0.000000e+00
>  %321 = fcmp uge float %318, 0.000000e+00
>  %322 = select i1 %321, float %318, float 0.000000e+00
>  %323 = call float @llvm.pow.f32(float %322, float %36)
>  %324 = call float @llvm.AMDGPU.cndlt(float %313, float 0.000000e+00, float %323)
>  %325 = fmul float 1.000000e+00, %295
>  %326 = fmul float %320, %295
>  %327 = fmul float %324, %295
>  %328 = fmul float %325, %74
>  %329 = fadd float %328, %269
>  %330 = fmul float %325, %75
>  %331 = fadd float %330, %271
>  %332 = fmul float %325, %76
>  %333 = fadd float %332, %273
>  %334 = fmul float %326, %77
>  %335 = fadd float %334, %329
>  %336 = fmul float %326, %78
>  %337 = fadd float %336, %331
>  %338 = fmul float %326, %79
>  %339 = fadd float %338, %333
>  %340 = fmul float %327, %80
>  %341 = fadd float %340, %335
>  %342 = fmul float %327, %81
>  %343 = fadd float %342, %337
>  %344 = fmul float %327, %82
>  %345 = fadd float %344, %339
>  %346 = call float @llvm.AMDIL.clamp.(float %341, float 0.000000e+00, float 1.000000e+00)
>  %347 = call float @llvm.AMDIL.clamp.(float %343, float 0.000000e+00, float 1.000000e+00)
>  %348 = call float @llvm.AMDIL.clamp.(float %345, float 0.000000e+00, float 1.000000e+00)
>  %349 = call float @fabs(float %191)
>  %350 = fmul float %164, %221
>  %351 = fmul float %165, %222
>  %352 = fadd float %351, %350
>  %353 = fmul float %166, %223
>  %354 = fadd float %352, %353
>  %355 = fadd float %354, %354
>  %356 = fadd float %354, %354
>  %357 = fadd float %354, %354
>  %358 = fsub float -0.000000e+00, %355
>  %359 = fmul float %358, %164
>  %360 = fadd float %359, %221
>  %361 = fsub float -0.000000e+00, %356
>  %362 = fmul float %361, %165
>  %363 = fadd float %362, %222
>  %364 = fsub float -0.000000e+00, %357
>  %365 = fmul float %364, %166
>  %366 = fadd float %365, %223
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %346, float %347, float %348, float %170)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %349, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %99, float %100, float %101, float %102)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %360, float %363, float %366, float %106)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %110, float %111, float %112, float %113)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %135, float %137, float %139, float %141)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020129
>bf8c007f
>100a0204
>c202012d
>bf8c007f
>d2820005
>04140902
>c2020131
>bf8c007f
>d2820005
>04140903
>c2020135
>bf8c007f
>d282000c
>04140904
>c2020128
>bf8c007f
>100a0204
>c202012c
>bf8c007f
>d2820005
>04140902
>c2020130
>bf8c007f
>d2820005
>04140903
>c2020134
>bf8c007f
>d282000d
>04140904
>100a1b0d
>d2820005
>0416190c
>c202012a
>bf8c007f
>100c0204
>c202012e
>bf8c007f
>d2820006
>04180902
>c2020132
>bf8c007f
>d2820006
>04180903
>c2020136
>bf8c007f
>d2820007
>04180904
>d2820005
>04160f07
>d2060105
>02010105
>7e105b05
>100a110c
>c2020125
>bf8c007f
>080c1804
>c2020124
>bf8c007f
>08161a04
>1012170b
>d282000a
>04260d06
>c2020126
>bf8c007f
>08120e04
>d282000a
>042a1309
>d206010a
>0201010a
>7e1c5b0a
>101e1d06
>08140b0f
>100c110d
>10201d0b
>08280d10
>10162914
>d2820012
>042e150a
>10101107
>10221d09
>08161111
>d2820009
>044a170b
>d2060109
>02010109
>7e245b09
>1026250a
>10142514
>c0840704
>bf8c007f
>e00c2000
>80021400
>c2020114
>bf8c0070
>10122804
>c2020115
>bf8c007f
>d2820009
>04240915
>c2020116
>bf8c007f
>d2820018
>04240916
>c2020110
>bf8c007f
>10122804
>c2020111
>bf8c007f
>d2820009
>04240915
>c2020112
>bf8c007f
>d2820009
>04240916
>10321309
>d2820019
>04663118
>c2020118
>bf8c007f
>10342804
>c2020119
>bf8c007f
>d282001a
>04680915
>c202011a
>bf8c007f
>d2820014
>04680916
>d2820015
>04662914
>d2060115
>02010115
>7e2a5b15
>10122b09
>102c1509
>10142b18
>d2820013
>045a270a
>1024250b
>10162b14
>d2820012
>044e250b
>d00c0004
>02010112
>d2000012
>00122480
>7e244f12
>c202011c
>bf8c007f
>0e242404
>7e244b12
>10202109
>d282000f
>04421f0a
>d2820010
>043e230b
>d0080008
>02022080
>d2000011
>00210112
>7e1e550e
>101c1f0e
>c2028138
>bf8c007f
>101c1c05
>c2028139
>bf8c007f
>d282000e
>043a1e05
>101e1f0f
>c202813a
>bf8c007f
>d282000e
>043a1e05
>7e1e550e
>101c1f11
>d00c0008
>02010110
>d2000010
>00222080
>10201f10
>c202813e
>c2040122
>bf8c007f
>7e220208
>d2820011
>04440b0f
>c2028142
>bf8c007f
>d2820011
>04440b10
>c2028146
>bf8c007f
>d2820012
>04440b0e
>c2028149
>bf8c007f
>08221805
>c2028148
>bf8c007f
>081a1a05
>10181b0d
>d282000c
>04322311
>c202814a
>bf8c007f
>08260e05
>d282000c
>04322713
>d206010c
>0201010c
>7e285b0c
>7e185514
>102a1914
>c202814c
>bf8c007f
>102a2a05
>c202814d
>bf8c007f
>d2820015
>04561805
>1018190c
>c202814e
>bf8c007f
>d282000c
>04561805
>7e18550c
>c2028152
>bf8c007f
>d2820015
>04480b0c
>1024290d
>101a2509
>102c2911
>d282000d
>04362d0a
>10282913
>d2820011
>0436290b
>d00c0008
>02010111
>d200000d
>00222280
>101a190d
>c2028156
>bf8c007f
>d2820013
>04540b0d
>082a0b16
>08240d12
>102c2512
>d2820016
>045a2b15
>08281114
>d2820016
>045a2914
>d2060116
>02010116
>7e2c5b16
>102a2d15
>10242d12
>10242509
>d2820012
>044a2b0a
>10282d14
>d2820012
>044a290b
>d00c0008
>02010112
>d2000012
>00222480
>7e244f12
>0e242404
>7e244b12
>d0080004
>02022280
>d2000011
>00110112
>10241911
>c202015a
>bf8c007f
>d2820011
>044c0912
>d2060811
>02010111
>c202013d
>c2028121
>bf8c007f
>7e260205
>d2820013
>044c090f
>c2020141
>bf8c007f
>d2820013
>044c0910
>c2020145
>bf8c007f
>d2820013
>044c090e
>c2020151
>bf8c007f
>d2820013
>044c090c
>c2020155
>bf8c007f
>d2820013
>044c090d
>c2020159
>bf8c007f
>d2820013
>044c0912
>d2060813
>02010113
>c202013c
>c2028120
>bf8c007f
>7e280205
>d282000f
>0450090f
>c2020140
>bf8c007f
>d282000f
>043c0910
>c2020144
>bf8c007f
>d282000e
>043c090e
>c2020150
>bf8c007f
>d282000c
>0438090c
>c2020154
>bf8c007f
>d282000c
>0430090d
>c2020158
>bf8c007f
>d282000c
>04300912
>d206080c
>0201010c
>c2020123
>bf8c007f
>d206080d
>02010004
>f800020f
>0d11130c
>d2060107
>02010107
>bf8c070f
>7e1802f2
>7e1a0280
>f800021f
>0c0d0d07
>c0840708
>bf8c000f
>e00c2000
>80020c00
>bf8c0770
>f800022f
>0f0e0d0c
>100e0d09
>d2820007
>041e0b0a
>d2820007
>041e110b
>bf8c070f
>06180f07
>100e170c
>080e0f08
>1010150c
>080a1105
>1010130c
>080c1106
>c084070c
>bf8c007f
>e00c2000
>80020800
>bf8c0770
>f800023f
>0b070506
>c0820710
>bf8c000f
>e00c2000
>80010500
>bf8c0770
>f800024f
>08070605
>c2020103
>bf8c000f
>10000204
>c2020107
>bf8c007f
>d2820000
>04000902
>c202010b
>bf8c007f
>d2820000
>04000903
>c202010f
>bf8c007f
>d2820000
>04000904
>c2020102
>bf8c007f
>100a0204
>c2020106
>bf8c007f
>d2820005
>04140902
>c202010a
>bf8c007f
>d2820005
>04140903
>c202010e
>bf8c007f
>d2820005
>04140904
>c2020101
>bf8c007f
>100c0204
>c2020105
>bf8c007f
>d2820006
>04180902
>c2020109
>bf8c007f
>d2820006
>04180903
>c202010d
>bf8c007f
>d2820006
>04180904
>c2020100
>bf8c007f
>100e0204
>c2020104
>bf8c007f
>d2820007
>041c0902
>c2020108
>bf8c007f
>d2820007
>041c0903
>c200010c
>bf8c007f
>d2820001
>041c0104
>f80008cf
>00050601
>bf810000
>Game removed: AppID 1250 "Killing Floor", ProcID 4486 
>Generating new string page texture 161: 128x256, total string texture memory is 393,22 KB
>unlinked 2 orphaned pipes
>CAsyncIOManager: 0 threads terminating.  0 reads, 0 writes, 0 deferrals.
>CAsyncIOManager: 15866 single object sleeps, 0 multi object sleeps
>CAsyncIOManager: 0 single object alertable sleeps, 2 multi object alertable sleeps
>Shutting down. . .
>[2013-09-08 03:59:07] Shutdown

Actions: View

Attachments on bug 69081: 85409 | 85410 | 85411 | 85412 | 85413 | 85414 | 86100 | 86101 | 86102 | 86105 | 86106

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