Attachment 86613 Details for Bug 69693 – dmesg nightly(24c8329416)

dmesg nightly(24c8329416)

dmesg_kms_flip_byt04_0926.txt (text/plain), 126.83 KB, created by lu hua on 2013-09-26 05:47:52 UTC

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Description:

Filename:

MIME Type:

Creator: lu hua

Created: 2013-09-26 05:47:52 UTC

Size: 126.83 KB

patch

obsolete

>[  103.436962] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.453625] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.470290] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.486956] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.492686] [drm:valleyview_set_rps], GPU freq request from 551 MHz (208) to 573 MHz (209)
>[  103.503622] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.520291] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.536953] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.553599] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.570286] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.577292] [drm:valleyview_set_rps], GPU freq request from 573 MHz (209) to 595 MHz (210)
>[  103.586953] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.603621] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.620288] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.636985] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.653626] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.662013] [drm:valleyview_set_rps], GPU freq request from 595 MHz (210) to 617 MHz (211)
>[  103.670288] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.686951] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.703619] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.720282] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.736952] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.746740] [drm:valleyview_set_rps], GPU freq request from 617 MHz (211) to 639 MHz (212)
>[  103.753623] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.770289] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.786950] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.803619] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.820286] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.831406] [drm:valleyview_set_rps], GPU freq request from 639 MHz (212) to 661 MHz (213)
>[  103.836999] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.853617] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.870282] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.886950] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.903616] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.916114] [drm:valleyview_set_rps], GPU freq request from 661 MHz (213) to 683 MHz (214)
>[  103.920282] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.936949] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.953617] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.970281] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  103.986946] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.000830] [drm:valleyview_set_rps], GPU freq request from 683 MHz (214) to 705 MHz (215)
>[  104.003615] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.020282] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.036946] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.053613] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.070276] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.085539] [drm:valleyview_set_rps], GPU freq request from 705 MHz (215) to 727 MHz (216)
>[  104.086943] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.103613] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.120277] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.136862] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.153660] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.170229] [drm:valleyview_set_rps], GPU freq request from 727 MHz (216) to 749 MHz (217)
>[  104.170308] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.186938] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.203594] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.220256] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.236920] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.253589] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.270249] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.286920] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.303586] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.320254] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.336919] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.353581] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.370251] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.386917] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.403584] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.420257] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.436914] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.453586] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.470253] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.486915] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.503581] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.520248] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.536915] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.553581] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.570246] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.586914] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.603577] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.620247] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.636913] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.653585] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.670247] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.686910] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.703583] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.720245] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.736912] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.753578] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.770240] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.786917] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.803579] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.820243] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.836909] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.853574] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.870244] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.886919] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.903576] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.920245] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.936905] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.953575] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.970238] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  104.986907] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.003573] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.020241] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.036907] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.053573] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.070238] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.086904] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.103569] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.120237] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.136903] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.153572] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.170237] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.186899] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.203571] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.220235] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.236902] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.253576] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.270232] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.286901] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.303567] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.320235] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.336902] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.353560] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.370236] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.386899] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.403569] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.420232] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.436899] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.453568] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.470244] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.486909] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.503568] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.520233] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.536835] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.553605] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.570264] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.586902] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.603564] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.620228] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.636897] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.653562] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.670231] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.686894] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.703558] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.720238] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.736897] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.753560] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.770230] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.786890] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.803559] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.820229] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.836894] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.853560] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.870228] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.886891] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.903558] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.920225] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.936896] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.953559] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.970226] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  105.986888] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.003569] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.020224] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.036888] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.053555] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.070220] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.086885] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.103555] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.120223] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.136888] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.153553] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.170227] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.186887] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.203549] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.220221] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.236884] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.253550] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.270219] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.286881] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.303551] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.320220] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.336886] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.353550] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.370214] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.386882] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.403552] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.420221] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.436883] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.453546] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.470219] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.486879] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.503545] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.520213] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.536876] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.553546] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.570215] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.586878] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.603544] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.620214] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.636884] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.653545] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.670213] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.686875] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.703544] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.720209] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.736877] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.753544] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.770211] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.786876] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.803544] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.820211] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.836877] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.853540] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.870216] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.886874] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.903570] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.920215] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.936875] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.953540] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.970203] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  106.986871] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.003539] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.020205] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.036873] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.053534] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.070205] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.086868] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.103542] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.120207] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.136866] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.153477] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.170132] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.186816] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.203486] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.220137] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.236797] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.253472] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.270143] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.286802] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.303471] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.320166] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.336813] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.353569] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.370212] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.386874] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.403534] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.420202] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.436865] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.453532] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.470195] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.486866] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.503529] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.520200] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.536863] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.553528] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.570195] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.586862] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.603575] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.620227] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.636884] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.653549] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.670217] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.686882] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.703548] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.720212] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.736884] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.753548] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.770216] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.786881] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.803560] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.820221] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.836883] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.853554] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.870216] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.886882] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.903548] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.920215] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.936879] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.953543] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.970211] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  107.986879] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.003544] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.020220] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.036881] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.053543] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.070206] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.086880] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.103542] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.120209] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.136877] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.153536] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.170205] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.186876] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.203551] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.220215] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.236875] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.253541] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.270208] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.286873] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.303549] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.320211] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.336875] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.353538] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.370206] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.386872] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.403534] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.420213] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.436873] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.453538] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.470203] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.486867] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.503534] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.520203] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.536867] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.553536] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.570200] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.586867] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.603533] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.620115] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.636778] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.653458] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.670154] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.686876] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.703514] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.720176] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.736841] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.753541] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.770194] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.786845] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.803508] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.820172] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.836841] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.853505] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.870173] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.886836] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.903501] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.920173] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.936840] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.953527] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.970199] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  108.986853] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.003537] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.020197] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.036860] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.053537] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.070193] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.086859] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.103525] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.120194] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.136890] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.153525] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.170189] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.186852] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.203524] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.220190] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.236864] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.253522] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.270189] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.286854] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.303522] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.320187] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.336854] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.353520] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.370189] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.386852] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.403518] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.420186] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.436853] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.453517] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.470194] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.486849] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.503516] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.520187] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.536849] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.553516] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.570185] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.586845] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.603515] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.620186] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.636846] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.653526] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.670180] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.686846] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.703519] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.720184] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.736847] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.753512] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.770183] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.786844] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.803513] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.820180] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.836842] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.853509] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.870178] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.886843] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.903511] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.920186] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.936854] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.953538] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.970181] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  109.986842] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.003505] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.020178] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.036844] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.053506] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.070173] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.086839] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.103506] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.120174] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.136838] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.153513] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.170178] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.186840] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.203510] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.220173] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.236838] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.253498] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.270175] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.286837] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.303503] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.320172] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.336836] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.353505] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.370170] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.386843] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.403509] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.420175] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.436832] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.453502] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.470166] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.486831] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.503500] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.520164] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.536831] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.553501] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.570167] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.586832] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.603498] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.620172] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.636832] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.653498] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.670166] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.686828] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.703497] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.720167] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.736829] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.753497] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.770161] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.786829] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.803498] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.820164] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.836830] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.853497] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.870166] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.886828] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.903494] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.920165] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.936828] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.953493] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.970161] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  110.986833] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.003495] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.020160] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.036828] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.053492] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.070156] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.086831] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.103488] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.120158] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.136824] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.153491] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.170159] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.186819] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.203489] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.220157] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.236819] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.253488] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.270151] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.286818] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.303487] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.320159] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.336822] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.353483] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.370151] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.386818] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.403486] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.420150] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.436889] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.453493] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.470152] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.486818] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.503486] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.520150] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.536823] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.553484] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.570151] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.586815] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.603482] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.620145] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.636815] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.653481] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.670126] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.686815] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.703453] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.720126] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.736807] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.753456] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.770131] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.786804] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.803456] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.820124] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.836805] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.853455] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.870121] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.886802] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.903454] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.920122] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.936802] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.953450] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.970123] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  111.986801] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.003456] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.020122] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.036799] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.053452] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.070118] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.086800] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.103450] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.120116] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.136800] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.153449] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.170118] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.186798] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.203470] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.220121] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.236806] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.253450] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.270116] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.286797] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.303446] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.320116] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.336798] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.353446] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.370110] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.386794] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.403446] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.420115] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.436795] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.453441] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.470120] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.486795] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.503443] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.520110] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.536789] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.553442] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.570109] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.586794] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.603442] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.620106] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.636792] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.653440] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.670107] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.686793] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.703439] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.720110] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.736790] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.753439] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.770104] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.786790] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.803439] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.820014] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.836790] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.853437] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.870105] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.886785] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.903439] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.920110] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.936792] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.953436] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.970101] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  112.986788] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.003436] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.020101] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.036787] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.053431] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.070100] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.086787] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.103433] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.120101] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.136783] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.153463] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.170101] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.186786] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.203430] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.220096] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.236786] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.253431] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.270098] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.286783] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.303426] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.320099] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.336782] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.353430] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.370097] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.386785] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.403431] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.420095] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.436783] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.453428] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.470091] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.486781] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.503426] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.520093] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.536778] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.553421] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.570094] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.586778] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.603425] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.620098] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.636776] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.653424] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.670088] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.686774] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.703423] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.720086] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.736776] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.753423] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.770089] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.786775] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.803418] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.820088] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  113.836829] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  113.836836] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  113.836841] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:eDP-1] to [NOCRTC]
>[  113.836844] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  113.836848] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:6]
>[  113.836852] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  113.836855] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  113.836861] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  113.836865] [drm:ironlake_edp_panel_vdd_on], eDP VDD already on
>[  113.836868] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  113.836873] [drm:ironlake_edp_backlight_off], 
>[  113.900779] [drm:valleyview_set_rps], GPU freq request from 749 MHz (217) to 397 MHz (201)
>[  114.037927] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  114.037933] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  114.037937] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  114.197430] [drm:valleyview_irq_handler], hotplug event received, stat 0x00100000
>[  114.197449] [drm:intel_hpd_irq_handler], Received HPD interrupt on PIN 5 - cnt: 0
>[  114.536740] [drm:intel_dp_link_down], 
>[  114.588738] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  114.639768] [drm:g4x_check_srwm], SR watermark: display plane 107, cursor 6
>[  114.639786] [drm:g4x_check_srwm], SR watermark: display plane 212, cursor 10
>[  114.639799] [drm:valleyview_update_wm], Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=93, cursor=6, SR: plane=107, cursor=10
>[  114.639835] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
>[  114.639854] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[  114.639869] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[  114.639882] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[  114.639899] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[  114.639902] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[  114.639906] [drm:check_crtc_state], [CRTC:3]
>[  114.639910] [drm:check_crtc_state], [CRTC:6]
>[  114.641809] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[5] ENCODERS[5]
>[  114.641839] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[5] ENCODERS[5]
>[  114.641865] [drm:drm_mode_getconnector], [CONNECTOR:16:?]
>[  114.641882] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:eDP-1]
>[  114.641896] [drm:intel_dp_detect], [CONNECTOR:16:eDP-1]
>[  114.641908] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  114.641926] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  114.641931] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  114.641938] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  114.641942] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  114.671238] [drm:valleyview_irq_handler], hotplug event received, stat 0x10100000
>[  114.671257] [drm:intel_hpd_irq_handler], Received HPD interrupt on PIN 5 - cnt: 1
>[  114.842942] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  114.843097] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  114.843101] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  114.843117] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  114.843124] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:eDP-1] probed modes :
>[  114.843127] [drm:drm_mode_debug_printmodeline], Modeline 17:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  114.843141] [drm:i915_hotplug_work_func], 
>[  114.843145] [drm:drm_mode_getconnector], 
>[  114.843149] [CONNECTOR:16:?]
>[  114.843153] running encoder hotplug functions
>[  114.843157] [drm:i915_hotplug_work_func], Connector eDP-1 (pin 5) received hotplug event.
>[  114.843161] [drm:i915_hotplug_work_func], Connector HDMI-A-1 (pin 5) received hotplug event.
>[  114.843165] [drm:intel_dp_detect], [CONNECTOR:16:eDP-1]
>[  114.843169] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  114.843173] [drm:ironlake_edp_panel_vdd_on], eDP VDD already on
>[  114.843328] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  114.843481] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  114.843484] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  114.843489] [drm:intel_hdmi_detect], [CONNECTOR:12:HDMI-A-1]
>[  114.843670] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  114.843689] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
>[  114.843754] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  114.843852] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[5] ENCODERS[5]
>[  114.843879] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[5] ENCODERS[5]
>[  114.843966] [drm:drm_mode_addfb], [FB:40]
>[  114.843978] [drm:drm_mode_addfb], [FB:41]
>[  114.844002] [drm:drm_mode_addfb], [FB:42]
>[  114.937402] [drm:drm_mode_setcrtc], [CRTC:6]
>[  114.937415] [drm:drm_mode_setcrtc], [CONNECTOR:16:eDP-1]
>[  114.937419] [drm:intel_crtc_set_config], [CRTC:6] [FB:40] #connectors=1 (x y) (0 0)
>[  114.937426] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  114.937429] [drm:drm_mode_debug_printmodeline], Modeline 38:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0x6
>[  114.937435] [drm:drm_mode_debug_printmodeline], Modeline 43:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  114.937440] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:6], mode_changed=1, fb_changed=1
>[  114.937444] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  114.937447] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [NOCRTC]
>[  114.937450] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  114.937454] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:eDP-1] to [CRTC:6]
>[  114.937457] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  114.937460] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  114.937464] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  114.937470] [drm:connected_sink_compute_bpp], [CONNECTOR:16:eDP-1] checking for sink bpp constrains
>[  114.937475] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  114.937479] [drm:intel_dp_compute_config], clamping bpp for eDP panel to BIOS-provided 18
>[  114.937483] [drm:intel_dp_compute_config], DP link bw 06 lane count 2 clock 162000 bpp 18
>[  114.937487] [drm:intel_dp_compute_config], DP link bw required 249804 available 259200
>[  114.937491] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  114.937495] [drm:intel_dump_pipe_config], [CRTC:6][modeset] config for pipe B
>[  114.937498] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[  114.937501] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  114.937504] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  114.937508] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 4042260, gmch_n: 4194304, link_m: 224570, link_n: 262144, tu: 64
>[  114.937513] [drm:intel_dump_pipe_config], requested mode:
>[  114.937515] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  114.937520] [drm:intel_dump_pipe_config], adjusted mode:
>[  114.937523] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  114.937528] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  114.937533] [drm:intel_dump_pipe_config], port clock: 162000
>[  114.937535] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
>[  114.937538] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  114.937542] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  114.937545] [drm:intel_dump_pipe_config], ips: 0
>[  114.937548] [drm:intel_dump_pipe_config], double wide: 0
>[  114.970745] [drm:valleyview_update_wm], Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=2, cursor=2, SR: plane=0, cursor=0
>[  114.978739] [drm:vlv_sideband_rw], IOSF sideband finish wait (read) timed out
>[  114.986739] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  114.994738] [drm:vlv_sideband_rw], IOSF sideband idle wait (read) timed out
>[  115.002738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.010738] [drm:vlv_sideband_rw], IOSF sideband idle wait (read) timed out
>[  115.018737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.026738] [drm:vlv_sideband_rw], IOSF sideband idle wait (read) timed out
>[  115.034737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.042738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.050737] [drm:vlv_sideband_rw], IOSF sideband idle wait (read) timed out
>[  115.058737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.066737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.074738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.082738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.090738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.098738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.106738] [drm:vlv_sideband_rw], IOSF sideband idle wait (read) timed out
>[  115.114738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.122738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.122775] [drm:i9xx_update_plane], Writing base 0282F000 00000000 0 0 7680
>[  115.122798] [drm:intel_edp_psr_match_conditions], PSR not supported on this platform
>[  115.122813] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:0:1920x1080]
>[  115.130738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.138739] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.146739] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.154737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.162738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  115.170744] [drm:intel_dp_init_panel_power_sequencer], cur t1_t3 0 t8 0 t9 0 t10 0 t11_t12 4000
>[  115.170764] [drm:intel_dp_init_panel_power_sequencer], vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[  115.170779] [drm:intel_dp_init_panel_power_sequencer], panel power up delay 200, power down delay 50, power cycle delay 500
>[  115.170792] [drm:intel_dp_init_panel_power_sequencer], backlight on delay 1, off delay 200
>[  115.170809] [drm:intel_dp_init_panel_power_sequencer_registers], panel power sequencer register settings: PP_ON 0x87d0000a, PP_OFF 0x1f407d0, PP_DIV 0x270f05
>[  115.170825] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  115.170838] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  115.170849] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  115.170868] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  115.170881] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  115.385739] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  115.399747] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  115.413738] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  115.427745] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  115.441738] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  115.455746] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  115.456331] [drm:intel_dp_start_link_train], clock recovery OK
>[  115.456335] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  115.456338] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  115.456341] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  115.456347] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  115.456350] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 9000000a control abcd000b
>[  115.587747] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  115.587769] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0xabcd000b PP_CONTROL: 0x80000008
>[  115.652738] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  115.653628] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  115.653815] [drm:g4x_check_srwm], SR watermark: display plane 107, cursor 6
>[  115.653823] [drm:g4x_check_srwm], SR watermark: display plane 211, cursor 10
>[  115.653826] [drm:valleyview_update_wm], Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=61, cursor=6, SR: plane=107, cursor=10
>[  115.673741] [drm:ironlake_edp_backlight_on], 
>[  115.675748] [drm:intel_panel_get_max_backlight], max backlight PWM = 0
>[  115.675767] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  115.675789] [drm:intel_connector_check_state], [CONNECTOR:16:eDP-1]
>[  115.675809] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[  115.675823] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[  115.675837] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[  115.675850] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[  115.675863] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[  115.675876] [drm:check_crtc_state], [CRTC:3]
>[  115.675888] [drm:check_crtc_state], [CRTC:6]
>[  115.679801] [drm:vlv_update_rps_cur_delay], Punit overrode GPU freq: 397 MHz (201) requested, but got 749 Mhz (217)
>[  115.679822] [drm:valleyview_set_rps], GPU freq request from 749 MHz (217) to 375 MHz (200)
>[  115.681744] [drm:vlv_update_rps_cur_delay], Punit overrode GPU freq: 375 MHz (200) requested, but got 397 Mhz (201)
>[  115.681764] [drm:valleyview_set_rps], GPU freq request from 397 MHz (201) to 397 MHz (201)
>[  115.690648] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.708940] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.727233] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.745546] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.763842] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.764383] [drm:vlv_update_rps_cur_delay], Punit overrode GPU freq: 397 MHz (201) requested, but got 375 Mhz (200)
>[  115.764403] [drm:valleyview_set_rps], GPU freq request from 375 MHz (200) to 419 MHz (202)
>[  115.782150] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.800448] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.818786] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.837060] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.849006] [drm:valleyview_set_rps], GPU freq request from 419 MHz (202) to 441 MHz (203)
>[  115.855369] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.873671] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.891978] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.910279] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.928591] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.933614] [drm:valleyview_set_rps], GPU freq request from 441 MHz (203) to 463 MHz (204)
>[  115.946892] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.965194] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  115.983496] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  116.001822] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  116.018284] [drm:valleyview_set_rps], GPU freq request from 463 MHz (204) to 485 MHz (205)
>[  116.019999] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  116.038412] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  116.056735] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  116.075018] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  116.093326] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  116.102888] [drm:valleyview_set_rps], GPU freq request from 485 MHz (205) to 507 MHz (206)
>[  116.111637] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  116.129882] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  116.148167] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  116.166588] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  116.188874] [drm:valleyview_set_rps], GPU freq request from 507 MHz (206) to 529 MHz (207)
>[  116.190113] [drm:intel_crtc_set_config], [CRTC:3] [FB:39] #connectors=1 (x y) (0 0)
>[  116.190116] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
>[  116.190119] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  116.190123] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:eDP-1] to [CRTC:3]
>[  116.190125] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  116.190129] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  116.190133] [drm:connected_sink_compute_bpp], [CONNECTOR:16:eDP-1] checking for sink bpp constrains
>[  116.190138] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  116.190140] [drm:intel_dp_compute_config], clamping bpp for eDP panel to BIOS-provided 18
>[  116.190143] [drm:intel_dp_compute_config], DP link bw 06 lane count 2 clock 162000 bpp 18
>[  116.190145] [drm:intel_dp_compute_config], DP link bw required 249804 available 259200
>[  116.190148] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  116.190151] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  116.190152] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  116.190154] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  116.190157] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  116.190160] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 4042260, gmch_n: 4194304, link_m: 224570, link_n: 262144, tu: 64
>[  116.190161] [drm:intel_dump_pipe_config], requested mode:
>[  116.190166] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  116.190167] [drm:intel_dump_pipe_config], adjusted mode:
>[  116.190171] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  116.190175] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  116.190176] [drm:intel_dump_pipe_config], port clock: 162000
>[  116.190178] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
>[  116.190181] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  116.190183] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  116.190184] [drm:intel_dump_pipe_config], ips: 0
>[  116.190186] [drm:intel_dump_pipe_config], double wide: 0
>[  116.190188] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  116.190191] [drm:ironlake_edp_panel_vdd_on], eDP VDD already on
>[  116.190194] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  116.190197] [drm:ironlake_edp_backlight_off], 
>[  116.290779] [drm:valleyview_set_rps], GPU freq request from 529 MHz (207) to 397 MHz (201)
>[  116.390924] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  116.390926] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  116.390930] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  116.550433] [drm:valleyview_irq_handler], hotplug event received, stat 0x00100000
>[  116.550442] [drm:intel_hpd_irq_handler], Received HPD interrupt on PIN 5 - cnt: 0
>[  116.843747] [drm:intel_dp_link_down], 
>[  116.895757] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  116.946776] [drm:valleyview_update_wm], Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=2, cursor=2, SR: plane=0, cursor=0
>[  116.954749] [drm:vlv_sideband_rw], IOSF sideband finish wait (write) timed out
>[  116.962748] [drm:vlv_sideband_rw], IOSF sideband idle wait (read) timed out
>[  116.970747] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  116.978746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  116.986747] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  116.994754] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.002747] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.010746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.018747] [drm:vlv_sideband_rw], IOSF sideband idle wait (read) timed out
>[  117.026746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.034747] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.034778] [drm:i9xx_update_plane], Writing base 00073000 00000000 0 0 7680
>[  117.034804] [drm:intel_edp_psr_match_conditions], PSR not supported on this platform
>[  117.034817] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:0:1920x1080]
>[  117.042747] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.050747] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.058747] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.066747] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.074747] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.078747] [drm:vlv_enable_pll] *ERROR* DPLL 0 failed to lock
>[  117.086748] [drm:vlv_sideband_rw], IOSF sideband idle wait (read) timed out
>[  117.094746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.102747] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.110747] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.110764] [drm:intel_dp_init_panel_power_sequencer], cur t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[  117.110774] [drm:intel_dp_init_panel_power_sequencer], vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[  117.110783] [drm:intel_dp_init_panel_power_sequencer], panel power up delay 200, power down delay 50, power cycle delay 500
>[  117.110790] [drm:intel_dp_init_panel_power_sequencer], backlight on delay 1, off delay 200
>[  117.110805] [drm:intel_dp_init_panel_power_sequencer_registers], panel power sequencer register settings: PP_ON 0x87d0000a, PP_OFF 0x1f407d0, PP_DIV 0x270f05
>[  117.110812] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  117.110818] [drm:ironlake_edp_panel_vdd_on], eDP VDD already on
>[  117.113266] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x50150064
>[  117.117186] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x50150064
>[  117.121185] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x50150064
>[  117.125512] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x50150064
>[  117.132741] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.140742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.148741] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.156747] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.164744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.172743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.180743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  117.180752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  117.183202] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x50150064
>[  117.185679] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x50150064
>[  117.185684] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  117.185686] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  117.185690] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  117.185693] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  117.185696] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 00000000 control abcd000b
>[  117.210604] [drm:valleyview_irq_handler], hotplug event received, stat 0x10100000
>[  117.210613] [drm:intel_hpd_irq_handler], Received HPD interrupt on PIN 5 - cnt: 1
>[  122.189751] [drm:ironlake_wait_panel_status] *ERROR* Panel status timeout: status 00000000 control abcd000b
>[  122.189762] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  122.189777] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0xabcd000b PP_CONTROL: 0x00000000
>[  122.248745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.256744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.264745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.272744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.280744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.288744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.296744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.296753] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  122.304745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.312745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.320744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.328745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.336746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.344745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.352745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.352754] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  122.360745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.368744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.376745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.384743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.392745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.400744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.408745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.408753] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  122.416746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.424745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.432745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.440745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.448744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.456744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.464745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.464753] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  122.472745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.480744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.488744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.496744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.504744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.512744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.520744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.520752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  122.528744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.536744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.544744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.552745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.560752] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.568744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.576743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.576751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  122.584745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.592745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.600744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.608744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.616744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.624744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.632744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.632753] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  122.633618] [drm:intel_dp_link_down], 
>[  122.684744] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  122.743746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.751744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.759744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.767743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.775744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.783744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.791743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.791751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  122.799744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.807744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.815744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.823744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.831744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.839744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.847744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.847752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  122.855745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.863744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.871744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.879743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.887744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.895743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.903744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.903752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  122.911743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.919744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.927744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.935744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.943744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.951744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.959745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.959752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  122.967745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.975744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.983744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.991743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  122.999744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.007744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.015743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.015752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.023745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.031744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.039744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.047744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.055743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.063745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.071744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.071753] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.072320] [drm:intel_dp_start_link_train], too many voltage retries, give up
>[  123.079744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.087744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.095744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.103744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.111744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.119744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.127744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.127752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.135744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.143745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.151744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.159743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.167744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.175744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.183744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.183752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.191744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.199743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.207744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.215744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.223744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.231744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.239743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.239751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.247745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.255744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.263744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.271744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.279744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.287744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.295743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.295751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.303745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.311744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.319744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.327744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.335744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.343744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.351744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.351752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.359744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.367744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.375744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.383743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.391744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.399744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.407744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.407752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.415745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.423744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.431744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.439745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.447745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.455744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.463744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.463752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.464618] [drm:intel_dp_link_down], 
>[  123.515743] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  123.574745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.582744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.590744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.598744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.606744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.614743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.622745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.622753] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.630745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.638744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.646744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.654744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.662744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.670744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.678744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.678752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.686744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.694744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.702743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.710739] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.718738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.726738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.734738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.734746] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.735319] [drm:intel_dp_start_link_train], clock recovery OK
>[  123.742738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.750738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.758738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.766738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.774738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.782737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.790737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.790745] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.798738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.806737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.814737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.822737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.830737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.838738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.846737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.846745] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.854739] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.862738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.870739] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.878738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.886738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.894738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.902738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.902746] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.910739] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.918738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.926737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.934737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.942737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.950736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.958737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.958745] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  123.966738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.974738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.982737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.990737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  123.998738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.006736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.014738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.014746] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.022738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.030738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.038737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.046737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.054738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.062738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.070738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.070745] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.078738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.086737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.094738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.102737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.110737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.118737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.126737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.126745] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.127609] [drm:intel_dp_link_down], 
>[  124.178737] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  124.237743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.245744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.253743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.261744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.269743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.277742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.285742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.285751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.293745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.301744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.309744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.317743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.325744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.333744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.341743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.341751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.349744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.357743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.365744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.373743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.381743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.389744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.397742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.397750] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.405745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.413743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.421743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.429743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.437743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.445744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.453743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.453752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.461743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.469743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.477744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.485743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.493744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.501743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.509744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.509752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.517743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.525743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.533743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.541743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.549743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.557743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.565744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.565752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.566319] [drm:intel_dp_start_link_train], too many voltage retries, give up
>[  124.573744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.581743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.589743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.597743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.605743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.613743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.621744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.621752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.629745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.637743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.645744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.653744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.661743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.669744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.677745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.677753] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.685743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.693744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.701744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.709748] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.717744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.725743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.733743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.733752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.741744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.749744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.757742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.765743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.773744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.781744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.789742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.789750] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.797744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.805743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.813744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.821744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.829744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.837744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.845743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.845751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.853744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.861743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.869743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.877743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.885744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.893743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.901743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.901751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.909744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.917743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.925749] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.933743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.941743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.949743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.957743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  124.957751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  124.958617] [drm:intel_dp_link_down], 
>[  125.009742] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  125.068744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.076742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.084743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.092743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.100743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.108742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.116743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.116751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.124744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.132743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.140743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.148744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.156743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.164743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.172743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.172751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.180744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.188743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.196744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.204743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.212743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.220743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.228743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.228751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.236744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.244744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.252742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.260743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.268743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.276744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.284743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.284751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.292744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.300741] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.308743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.316743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.324742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.332742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.340742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.340751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.348744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.356742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.364743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.372743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.380742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.388743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.396742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.396751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.397320] [drm:intel_dp_start_link_train], too many voltage retries, give up
>[  125.404743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.412744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.420743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.428742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.436743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.444743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.452743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.452751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.460743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.468742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.476742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.484742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.492743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.500742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.508744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.508751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.516744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.524748] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.532738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.540736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.548737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.556736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.564738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.564747] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.572739] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.580740] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.588737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.596737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.604736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.612737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.620736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.620744] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.628738] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.636737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.644736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.652736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.660737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.668737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.676736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.676744] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.684737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.692736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.700739] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.708758] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.716736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.724736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.732736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.732744] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.740737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.748737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.756736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.764737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.772737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.780736] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.788737] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.788745] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.789609] [drm:intel_dp_link_down], 
>[  125.840737] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  125.899743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.907753] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.915742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.923743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.931743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.939743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.947743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.947751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  125.955746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.963743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.971744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.979742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.987743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  125.995743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.003744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.003752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.011743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.019742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.027741] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.035742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.043743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.051744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.059743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.059751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.067743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.075742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.083745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.091744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.099741] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.107743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.115743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.115751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.123742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.131744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.139743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.147742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.155742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.163744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.171743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.171751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.179744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.187742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.195746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.203743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.211745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.219743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.227743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.227751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.228314] [drm:intel_dp_start_link_train], too many voltage retries, give up
>[  126.235743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.243743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.251742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.259743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.267742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.275743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.283746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.283754] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.291744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.299743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.307743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.315743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.323743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.331742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.339746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.339755] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.347744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.355742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.363743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.371743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.379752] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.387743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.395742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.395750] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.403743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.411746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.419745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.427745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.435744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.443744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.451743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.451751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.459746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.467746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.475742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.483742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.491742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.499742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.507742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.507750] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.515814] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.523744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.531742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.539742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.547742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.555743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.563743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.563751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.571743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.579743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.587742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.595745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.603744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.611743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.619742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.619750] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.620620] [drm:intel_dp_link_down], 
>[  126.671743] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  126.730743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.738743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.746742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.754744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.762742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.770742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.778742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.778751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.786743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.794742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.802743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.810746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.818742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.826742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.834743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.834751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.842742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.850750] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.858743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.866743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.874743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.882744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.890744] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.890752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.898742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.906752] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.914742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.922743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.930742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.938742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.946745] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.946753] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.954743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.962742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.970742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.978749] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.986746] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  126.994743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  127.002743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  127.002751] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  127.010743] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  127.018742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  127.026742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  127.034742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  127.042742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  127.050742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  127.058742] [drm:vlv_sideband_rw], IOSF sideband idle wait (write) timed out
>[  127.058750] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  127.059314] [drm:intel_dp_start_link_train], too many voltage retries, give up
>[  127.059316] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  127.059318] [drm:intel_dp_link_down], 
>[  127.110743] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  128.163737] ------------[ cut here ]------------
>[  128.163817] WARNING: CPU: 0 PID: 3474 at drivers/gpu/drm/i915/intel_display.c:1479 vlv_pre_enable_dp+0x112/0x121 [i915]()
>[  128.163822] timed out waiting for port C ready: 0xf00020ff
>[  128.163882] Modules linked in: ip6table_filter ip6_tables ipv6 iptable_filter ip_tables ebtable_nat ebtables x_tables dm_mod snd_hda_codec_realtek serio_raw pcspkr snd_hda_intel snd_hda_codec snd_hwdep snd_pcm snd_page_alloc snd_timer snd soundcore battery ac acpi_cpufreq i915 video button drm_kms_helper drm freq_table
>[  128.163886] CPU: 0 PID: 3474 Comm: kms_flip Not tainted 3.12.0-rc2_nightlytop_24c832_20130926_+ #286
>[  128.163890]  0000000000000000 0000000000000009 ffffffff817041c4 ffff880073d85848
>[  128.163893]  ffffffff8103319e 0000000000000282 ffffffffa009b1ff dead000000200200
>[  128.163895]  ffff88006ff44000 0000000000000000 0000000000000001 ffff880004d11800
>[  128.163896] Call Trace:
>[  128.163904]  [<ffffffff817041c4>] ? dump_stack+0x41/0x51
>[  128.163910]  [<ffffffff8103319e>] ? warn_slowpath_common+0x73/0x8b
>[  128.163926]  [<ffffffffa009b1ff>] ? vlv_pre_enable_dp+0x112/0x121 [i915]
>[  128.163930]  [<ffffffff8103324e>] ? warn_slowpath_fmt+0x45/0x4a
>[  128.163946]  [<ffffffffa0084d45>] ? vlv_wait_port_ready+0xc9/0xfc [i915]
>[  128.163962]  [<ffffffffa009b1ff>] ? vlv_pre_enable_dp+0x112/0x121 [i915]
>[  128.163977]  [<ffffffffa00854ac>] ? valleyview_crtc_enable+0x2b8/0x395 [i915]
>[  128.163993]  [<ffffffffa008b0f5>] ? __intel_set_mode+0xfbc/0x10c7 [i915]
>[  128.163998]  [<ffffffff810635b9>] ? console_trylock+0xf/0x47
>[  128.164014]  [<ffffffffa008ca94>] ? intel_set_mode+0xd/0x27 [i915]
>[  128.164029]  [<ffffffffa008d0df>] ? intel_crtc_set_config+0x631/0x838 [i915]
>[  128.164034]  [<ffffffff812c719b>] ? cpumask_next_and+0x2b/0x3b
>[  128.164045]  [<ffffffffa000f4a8>] ? drm_mode_set_config_internal+0x44/0xac [drm]
>[  128.164050]  [<ffffffffa0048c6e>] ? drm_fb_helper_set_par+0x55/0x9a [drm_kms_helper]
>[  128.164055]  [<ffffffff812f94f6>] ? fb_set_var+0x246/0x32c
>[  128.164059]  [<ffffffff8130333d>] ? fbcon_blank+0x71/0x230
>[  128.164064]  [<ffffffff81352368>] ? do_unblank_screen+0xef/0x169
>[  128.164068]  [<ffffffff8134a798>] ? vt_ioctl+0x4af/0xf87
>[  128.164072]  [<ffffffff810e68ce>] ? path_openat+0x22d/0x5b9
>[  128.164075]  [<ffffffff81342f1d>] ? tty_ioctl+0x8b4/0x923
>[  128.164078]  [<ffffffff810e6f26>] ? do_filp_open+0x2b/0x6f
>[  128.164080]  [<ffffffff810e81f2>] ? vfs_ioctl+0x1e/0x31
>[  128.164083]  [<ffffffff810e89c8>] ? do_vfs_ioctl+0x3ad/0x3ef
>[  128.164087]  [<ffffffff810f0382>] ? __fd_install+0x15/0x39
>[  128.164090]  [<ffffffff810e8a58>] ? SyS_ioctl+0x4e/0x7e
>[  128.164093]  [<ffffffff8170e722>] ? system_call_fastpath+0x16/0x1b
>[  128.164095] ---[ end trace d48407b80d740924 ]---
>[  128.164145] [drm:g4x_check_srwm], SR watermark: display plane 107, cursor 6
>[  128.164148] [drm:g4x_check_srwm], SR watermark: display plane 211, cursor 10
>[  128.164151] [drm:valleyview_update_wm], Setting FIFO watermarks - A: plane=61, cursor=6, B: plane=2, cursor=2, SR: plane=107, cursor=10
>[  128.215740] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  128.267741] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  128.267750] [drm:ironlake_edp_backlight_on], 
>[  128.269743] [drm:intel_panel_get_max_backlight], max backlight PWM = 0
>[  128.269753] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  128.269772] [drm:intel_connector_check_state], [CONNECTOR:16:eDP-1]
>[  128.269787] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[  128.269797] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[  128.269806] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[  128.269815] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[  128.269824] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[  128.269831] [drm:check_crtc_state], [CRTC:3]
>[  128.277736] [drm:vlv_sideband_rw], IOSF sideband idle wait (read) timed out
>[  128.277759] divide error: 0000 [#1] SMP 
>[  128.277816] Modules linked in: ip6table_filter ip6_tables ipv6 iptable_filter ip_tables ebtable_nat ebtables x_tables dm_mod snd_hda_codec_realtek serio_raw pcspkr snd_hda_intel snd_hda_codec snd_hwdep snd_pcm snd_page_alloc snd_timer snd soundcore battery ac acpi_cpufreq i915 video button drm_kms_helper drm freq_table
>[  128.277827] CPU: 0 PID: 3474 Comm: kms_flip Tainted: G        W    3.12.0-rc2_nightlytop_24c832_20130926_+ #286
>[  128.277834] task: ffff880004ebd340 ti: ffff880073d84000 task.ti: ffff880073d84000
>[  128.277885] RIP: 0010:[<ffffffffa0082a5d>]  [<ffffffffa0082a5d>] i9xx_get_pipe_config+0x31e/0x362 [i915]
>[  128.277887] RSP: 0018:ffff880073d856c8  EFLAGS: 00010246
>[  128.277888] RAX: 0000000000000000 RBX: ffff880073d85738 RCX: 0000000000000000
>[  128.277890] RDX: 0000000000000000 RSI: 0000000000000046 RDI: ffff88006ff45988
>[  128.277891] RBP: 0000000000000000 R08: 0000000000000000 R09: ffffffff8587dec0
>[  128.277892] R10: 0000000000000001 R11: 0000000000000626 R12: ffff88006ff45988
>[  128.277894] R13: 0000000000000000 R14: ffff88006ff44000 R15: ffff880004d11800
>[  128.277896] FS:  00007f0aff7768c0(0000) GS:ffff880077c00000(0000) knlGS:0000000000000000
>[  128.277897] CS:  0010 DS: 0000 ES: 0000 CR0: 000000008005003b
>[  128.277898] CR2: 00007fff75021eb0 CR3: 0000000070585000 CR4: 00000000001007f0
>[  128.277899] Stack:
>[  128.277902]  ffff880073d85738 ffff8800742f1000 ffff880004d11800 ffff880073d85738
>[  128.277904]  0000000000000001 ffff88006ff44000 ffff88006fe9d700 ffffffffa0081f5a
>[  128.277907]  0000000000000000 0000000000000046 ffff880004d11c08 ffff880004d11c38
>[  128.277908] Call Trace:
>[  128.277923]  [<ffffffffa0081f5a>] ? check_crtc_state+0x121/0x84e [i915]
>[  128.277942]  [<ffffffffa008c7d3>] ? intel_modeset_check_state+0x36f/0x623 [i915]
>[  128.277957]  [<ffffffffa008caa4>] ? intel_set_mode+0x1d/0x27 [i915]
>[  128.277973]  [<ffffffffa008d0df>] ? intel_crtc_set_config+0x631/0x838 [i915]
>[  128.277976]  [<ffffffff812c719b>] ? cpumask_next_and+0x2b/0x3b
>[  128.277986]  [<ffffffffa000f4a8>] ? drm_mode_set_config_internal+0x44/0xac [drm]
>[  128.277991]  [<ffffffffa0048c6e>] ? drm_fb_helper_set_par+0x55/0x9a [drm_kms_helper]
>[  128.277995]  [<ffffffff812f94f6>] ? fb_set_var+0x246/0x32c
>[  128.277999]  [<ffffffff8130333d>] ? fbcon_blank+0x71/0x230
>[  128.278002]  [<ffffffff81352368>] ? do_unblank_screen+0xef/0x169
>[  128.278005]  [<ffffffff8134a798>] ? vt_ioctl+0x4af/0xf87
>[  128.278008]  [<ffffffff810e68ce>] ? path_openat+0x22d/0x5b9
>[  128.278011]  [<ffffffff81342f1d>] ? tty_ioctl+0x8b4/0x923
>[  128.278013]  [<ffffffff810e6f26>] ? do_filp_open+0x2b/0x6f
>[  128.278016]  [<ffffffff810e81f2>] ? vfs_ioctl+0x1e/0x31
>[  128.278019]  [<ffffffff810e89c8>] ? do_vfs_ioctl+0x3ad/0x3ef
>[  128.278022]  [<ffffffff810f0382>] ? __fd_install+0x15/0x39
>[  128.278025]  [<ffffffff810e8a58>] ? SyS_ioctl+0x4e/0x7e
>[  128.278027]  [<ffffffff8170e722>] ? system_call_fastpath+0x16/0x1b
>[  128.278058] Code: 34 03 00 4c 89 e7 89 c5 e8 b1 48 68 e1 89 e8 40 0f b6 d5 89 e9 c1 e8 08 c1 e9 0c 83 e0 07 83 e1 0f 69 c0 a0 86 01 00 0f af c2 99 <f7> f9 89 e9 c1 ed 10 c1 e9 15 83 e5 1f 83 e1 07 0f af cd 01 c0 
>[  128.278072] RIP  [<ffffffffa0082a5d>] i9xx_get_pipe_config+0x31e/0x362 [i915]
>[  128.278073]  RSP <ffff880073d856c8>
>[  128.278076] ---[ end trace d48407b80d740925 ]---

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Attachments on bug 69693: 86333 | 86613 | 87641 | 88873

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