Attachment 87534 Details for Bug 66331 – Dump with R600_DEBUG=ps,vs,fs

Dump with R600_DEBUG=ps,vs,fs

webgl-water.log (text/plain), 297.17 KB, created by Dieter Nützel on 2013-10-12 21:25:20 UTC

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Filename:

MIME Type:

Creator: Dieter Nützel

Created: 2013-10-12 21:25:20 UTC

Size: 297.17 KB

patch

obsolete

>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
>   {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
>
>===== SHADER #1 ========================================= FETCH/RV730/R700 =====
>===== 12 dw ===== 3 gprs ===== 0 stack =========================================
>0000  00000002 81000400 VTX 2 @4
> 0004  7c00a000 88cd1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
> 0008  7c00a000 88cd1002 00080010 VFETCH              R2.xyzw, R0.x + 16b ,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, }
>
>===== SHADER #2 ========================================= FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 93564001 00080000 VFETCH              R1.x001, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, }
>
>===== SHADER #3 ========================================= FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 97561001 00080000 VFETCH              R1.xy01, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, }
>
>===== SHADER #4 ========================================= FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 9bd51001 00080000 VFETCH              R1.xyz1, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, }
>
>===== SHADER #5 ========================================= FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 988d1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  call void @llvm.R600.store.dummy(i32 0)
>  ret void
>}
>
>declare void @llvm.R600.store.dummy(i32)
>
>attributes #0 = { "ShaderType"="0" }
>
>===== SHADER #6 ============================================ PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600fff EXPORT_DONE        PIXEL 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #6 OPT ======================================== PS/RV730/R700 =====
>===== 2 dw ===== 0 gprs ===== 0 stack ==========================================
>0000  c0000000 94600fff EXPORT_DONE        PIXEL 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #7 ============================================ PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #7 OPT ======================================== PS/RV730/R700 =====
>===== 2 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #8 ============================================ PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #8 OPT ======================================== PS/RV730/R700 =====
>===== 2 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = insertelement <4 x float> undef, float %0, i32 0
>  %9 = insertelement <4 x float> %8, float %1, i32 1
>  %10 = insertelement <4 x float> %9, float %2, i32 2
>  %11 = insertelement <4 x float> %10, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1)
>  %12 = insertelement <4 x float> undef, float %4, i32 0
>  %13 = insertelement <4 x float> %12, float %5, i32 1
>  %14 = insertelement <4 x float> %13, float %6, i32 2
>  %15 = insertelement <4 x float> %14, float %7, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #9 ============================================ VS/RV730/R700 =====
>===== 8 dw ===== 3 gprs ===== 1 stack ==========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0004  c0014000 94600688 EXPORT_DONE        PARAM 0     R2.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #9 OPT ======================================== VS/RV730/R700 =====
>===== 12 dw ===== 3 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c0014000 94400688 EXPORT_DONE        PARAM 0     R2.xyzw  VPM
>0004  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0006  00000005 a0000000 ALU 1 @10
> 0010  80000000 00000d00     1      x: ALU_NOP            __.x
>0008  00000000 80200000 NOP @0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>  0: MOV OUT[0], IN[0]
>  1: END
>STREAMOUT
>  0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.stream.output(<4 x float> %7, i32 0, i32 0, i32 1)
>  %8 = insertelement <4 x float> undef, float %0, i32 0
>  %9 = insertelement <4 x float> %8, float %1, i32 1
>  %10 = insertelement <4 x float> %9, float %2, i32 2
>  %11 = insertelement <4 x float> %10, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1)
>  call void @llvm.R600.store.dummy(i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32)
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>declare void @llvm.R600.store.dummy(i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #10 =========================================== VS/RV730/R700 =====
>===== 12 dw ===== 2 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  00008000 90401fff MEM_STREAM0        WRITE 0     R1.x___  ES:0  VPM
>0004  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0006  c0004000 94600fff EXPORT_DONE        PARAM 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #10 OPT ======================================= VS/RV730/R700 =====
>===== 14 dw ===== 2 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0004  00008000 90401fff MEM_STREAM0        WRITE 0     R1.x___  ES:0  VPM
>0006  c0004000 94400fff EXPORT_DONE        PARAM 0     R0.____  VPM
>0008  00000006 a0000000 ALU 1 @12
> 0012  80000000 00000d00     1      x: ALU_NOP            __.x
>0010  00000000 80200000 NOP @0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  call void @llvm.R600.store.dummy(i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.dummy(i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #11 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600fff EXPORT_DONE        PIXEL 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #11 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 0 gprs ===== 0 stack ==========================================
>0000  c0000000 94600fff EXPORT_DONE        PIXEL 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>ATTENTION: default value of option vblank_mode overridden by environment.
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
>   {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
>
>===== SHADER #12 ======================================== FETCH/RV730/R700 =====
>===== 12 dw ===== 3 gprs ===== 0 stack =========================================
>0000  00000002 81000400 VTX 2 @4
> 0004  7c00a000 88cd1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
> 0008  7c00a000 88cd1002 00080010 VFETCH              R2.xyzw, R0.x + 16b ,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, }
>
>===== SHADER #13 ======================================== FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 93564001 00080000 VFETCH              R1.x001, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, }
>
>===== SHADER #14 ======================================== FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 97561001 00080000 VFETCH              R1.xy01, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, }
>
>===== SHADER #15 ======================================== FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 9bd51001 00080000 VFETCH              R1.xyz1, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, }
>
>===== SHADER #16 ======================================== FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 988d1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  call void @llvm.R600.store.dummy(i32 0)
>  ret void
>}
>
>declare void @llvm.R600.store.dummy(i32)
>
>attributes #0 = { "ShaderType"="0" }
>
>===== SHADER #17 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600fff EXPORT_DONE        PIXEL 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #17 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 0 gprs ===== 0 stack ==========================================
>0000  c0000000 94600fff EXPORT_DONE        PIXEL 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #18 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #18 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #19 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #19 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = insertelement <4 x float> undef, float %0, i32 0
>  %9 = insertelement <4 x float> %8, float %1, i32 1
>  %10 = insertelement <4 x float> %9, float %2, i32 2
>  %11 = insertelement <4 x float> %10, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1)
>  %12 = insertelement <4 x float> undef, float %4, i32 0
>  %13 = insertelement <4 x float> %12, float %5, i32 1
>  %14 = insertelement <4 x float> %13, float %6, i32 2
>  %15 = insertelement <4 x float> %14, float %7, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #20 =========================================== VS/RV730/R700 =====
>===== 8 dw ===== 3 gprs ===== 1 stack ==========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0004  c0014000 94600688 EXPORT_DONE        PARAM 0     R2.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #20 OPT ======================================= VS/RV730/R700 =====
>===== 12 dw ===== 3 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c0014000 94400688 EXPORT_DONE        PARAM 0     R2.xyzw  VPM
>0004  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0006  00000005 a0000000 ALU 1 @10
> 0010  80000000 00000d00     1      x: ALU_NOP            __.x
>0008  00000000 80200000 NOP @0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>  0: MOV OUT[0], IN[0]
>  1: END
>STREAMOUT
>  0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.stream.output(<4 x float> %7, i32 0, i32 0, i32 1)
>  %8 = insertelement <4 x float> undef, float %0, i32 0
>  %9 = insertelement <4 x float> %8, float %1, i32 1
>  %10 = insertelement <4 x float> %9, float %2, i32 2
>  %11 = insertelement <4 x float> %10, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1)
>  call void @llvm.R600.store.dummy(i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32)
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>declare void @llvm.R600.store.dummy(i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #21 =========================================== VS/RV730/R700 =====
>===== 12 dw ===== 2 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  00008000 90401fff MEM_STREAM0        WRITE 0     R1.x___  ES:0  VPM
>0004  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0006  c0004000 94600fff EXPORT_DONE        PARAM 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #21 OPT ======================================= VS/RV730/R700 =====
>===== 14 dw ===== 2 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0004  00008000 90401fff MEM_STREAM0        WRITE 0     R1.x___  ES:0  VPM
>0006  c0004000 94400fff EXPORT_DONE        PARAM 0     R0.____  VPM
>0008  00000006 a0000000 ALU 1 @12
> 0012  80000000 00000d00     1      x: ALU_NOP            __.x
>0010  00000000 80200000 NOP @0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  call void @llvm.R600.store.dummy(i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.dummy(i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #22 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600fff EXPORT_DONE        PIXEL 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #22 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 0 gprs ===== 0 stack ==========================================
>0000  c0000000 94600fff EXPORT_DONE        PIXEL 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #23 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #23 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = load <4 x float> addrspace(8)* null
>  %9 = extractelement <4 x float> %8, i32 0
>  %10 = fmul float %0, %9
>  %11 = load <4 x float> addrspace(8)* null
>  %12 = extractelement <4 x float> %11, i32 1
>  %13 = fmul float %0, %12
>  %14 = load <4 x float> addrspace(8)* null
>  %15 = extractelement <4 x float> %14, i32 2
>  %16 = fmul float %0, %15
>  %17 = load <4 x float> addrspace(8)* null
>  %18 = extractelement <4 x float> %17, i32 3
>  %19 = fmul float %0, %18
>  %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %21 = extractelement <4 x float> %20, i32 0
>  %22 = fmul float %1, %21
>  %23 = fadd float %22, %10
>  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %25 = extractelement <4 x float> %24, i32 1
>  %26 = fmul float %1, %25
>  %27 = fadd float %26, %13
>  %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %29 = extractelement <4 x float> %28, i32 2
>  %30 = fmul float %1, %29
>  %31 = fadd float %30, %16
>  %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %33 = extractelement <4 x float> %32, i32 3
>  %34 = fmul float %1, %33
>  %35 = fadd float %34, %19
>  %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = fmul float %2, %37
>  %39 = fadd float %38, %23
>  %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %41 = extractelement <4 x float> %40, i32 1
>  %42 = fmul float %2, %41
>  %43 = fadd float %42, %27
>  %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %45 = extractelement <4 x float> %44, i32 2
>  %46 = fmul float %2, %45
>  %47 = fadd float %46, %31
>  %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %49 = extractelement <4 x float> %48, i32 3
>  %50 = fmul float %2, %49
>  %51 = fadd float %50, %35
>  %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = fmul float %3, %53
>  %55 = fadd float %54, %39
>  %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %57 = extractelement <4 x float> %56, i32 1
>  %58 = fmul float %3, %57
>  %59 = fadd float %58, %43
>  %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %61 = extractelement <4 x float> %60, i32 2
>  %62 = fmul float %3, %61
>  %63 = fadd float %62, %47
>  %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %65 = extractelement <4 x float> %64, i32 3
>  %66 = fmul float %3, %65
>  %67 = fadd float %66, %51
>  %68 = call float @llvm.AMDIL.clamp.(float %4, float 0,000000e+00, float 0x3FF0000000000000)
>  %69 = call float @llvm.AMDIL.clamp.(float %5, float 0,000000e+00, float 0x3FF0000000000000)
>  %70 = call float @llvm.AMDIL.clamp.(float %6, float 0,000000e+00, float 0x3FF0000000000000)
>  %71 = call float @llvm.AMDIL.clamp.(float %7, float 0,000000e+00, float 0x3FF0000000000000)
>  %72 = insertelement <4 x float> undef, float %55, i32 0
>  %73 = insertelement <4 x float> %72, float %59, i32 1
>  %74 = insertelement <4 x float> %73, float %63, i32 2
>  %75 = insertelement <4 x float> %74, float %67, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %75, i32 60, i32 1)
>  %76 = insertelement <4 x float> undef, float %68, i32 0
>  %77 = insertelement <4 x float> %76, float %69, i32 1
>  %78 = insertelement <4 x float> %77, float %70, i32 2
>  %79 = insertelement <4 x float> %78, float %71, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %79, i32 0, i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #24 =========================================== VS/RV730/R700 =====
>===== 52 dw ===== 5 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  80000006 a04c0000 ALU 20 @12 KC0[CB0:0-31]
> 0012  00100001 00000110     1      x: MUL_IEEE           R0.x,  R1.x, KC0[0].x
> 0014  00900001 20000110            y: MUL_IEEE           R0.y,  R1.x, KC0[0].y
> 0016  01100001 40000110            z: MUL_IEEE           R0.z,  R1.x, KC0[0].z
> 0018  81900001 60000110            w: MUL_IEEE           R0.w,  R1.x, KC0[0].w
> 0020  00102401 000280fe     2      x: MULADD_IEEE        R0.x,  R1.y, KC0[1].x, PV.x
> 0022  00902401 200284fe            y: MULADD_IEEE        R0.y,  R1.y, KC0[1].y, PV.y
> 0024  01102401 400288fe            z: MULADD_IEEE        R0.z,  R1.y, KC0[1].z, PV.z
> 0026  81902401 60028cfe            w: MULADD_IEEE        R0.w,  R1.y, KC0[1].w, PV.w
> 0028  00104801 00228000     3      x: MULADD_IEEE        R1.x,  R1.z, KC0[2].x, R0.x
> 0030  00904801 20228400            y: MULADD_IEEE        R1.y,  R1.z, KC0[2].y, R0.y
> 0032  01104801 40828800            z: MULADD_IEEE        R4.z,  R1.z, KC0[2].z, R0.z
> 0034  81904801 60628c00            w: MULADD_IEEE        R3.w,  R1.z, KC0[2].w, R0.w
> 0036  00000002 80000c90     4      x: MOV_sat            R0.x,  R2.x
> 0038  81906c01 60628c03            w: MULADD_IEEE        R3.w,  R1.w, KC0[3].w, R3.w
> 0040  80906c01 20628401     5      y: MULADD_IEEE        R3.y,  R1.w, KC0[3].y, R1.y
> 0042  00106c01 00628001     6      x: MULADD_IEEE        R3.x,  R1.w, KC0[3].x, R1.x
> 0044  00000402 a0000c90            y: MOV_sat            R0.y,  R2.y
> 0046  01106c01 40628804            z: MULADD_IEEE        R3.z,  R1.w, KC0[3].z, R4.z
> 0048  80000c02 e0080c90            w: MOV_sat            R0.w,  R2.w                   VEC_120
> 0050  80000802 c0000c90     7      z: MOV_sat            R0.z,  R2.z
>0004  c001a03c 94400688 EXPORT_DONE        POS   60    R3.xyzw  VPM
>0006  c0004000 94600688 EXPORT_DONE        PARAM 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #24 OPT ======================================= VS/RV730/R700 =====
>===== 56 dw ===== 3 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  40000006 a0500000 ALU 21 @12 KC0[CB0:0-15]
> 0012  01900001 0f800110     1      x: MUL_IEEE           T0.x,  R1.x, KC0[0].w
> 0014  81100001 2f800110            y: MUL_IEEE           T0.y,  R1.x, KC0[0].z
> 0016  01902401 0f82807c     2      x: MULADD_IEEE        T0.x,  R1.y, KC0[1].w, T0.x
> 0018  01102401 2f82847c            y: MULADD_IEEE        T0.y,  R1.y, KC0[1].z, T0.y
> 0020  00900001 4f800110            z: MUL_IEEE           T0.z,  R1.x, KC0[0].y
> 0022  80100001 6f800110            w: MUL_IEEE           T0.w,  R1.x, KC0[0].x
> 0024  01104801 2fa2847c     3      y: MULADD_IEEE        T1.y,  R1.z, KC0[2].z, T0.y
> 0026  00902401 4f82887c            z: MULADD_IEEE        T0.z,  R1.y, KC0[1].y, T0.z
> 0028  80102401 6f828c7c            w: MULADD_IEEE        T0.w,  R1.y, KC0[1].x, T0.w
> 0030  01904801 0fa2807c     4      x: MULADD_IEEE        T1.x,  R1.z, KC0[2].w, T0.x
> 0032  80104801 2f828c7c            y: MULADD_IEEE        T0.y,  R1.z, KC0[2].x, T0.w
> 0034  00904801 0f8e887c     5      x: MULADD_IEEE        T0.x,  R1.z, KC0[2].y, T0.z   VEC_102
> 0036  00000402 a0000c90            y: MOV_sat            R0.y,  R2.y
> 0038  00000802 c0000c90            z: MOV_sat            R0.z,  R2.z
> 0040  00000c02 e0000c90            w: MOV_sat            R0.w,  R2.w
> 0042  80000c01 6f800c90            t: MOV                T0.w,  R1.w
> 0044  00106c7c 0022847c     6      x: MULADD_IEEE        R1.x,  T0.w, KC0[3].x, T0.y
> 0046  00906c7c 2022807c            y: MULADD_IEEE        R1.y,  T0.w, KC0[3].y, T0.x
> 0048  01106c7c 4026847d            z: MULADD_IEEE        R1.z,  T0.w, KC0[3].z, T1.y   VEC_021
> 0050  01906c7c 602a807d            w: MULADD_IEEE        R1.w,  T0.w, KC0[3].w, T1.x   VEC_120
> 0052  80000002 80040c90            t: MOV_sat            R0.x,  R2.x                   SCL_122
>0004  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0006  c0004000 94400688 EXPORT_DONE        PARAM 0     R0.xyzw  VPM
>0008  0000001b a0000000 ALU 1 @54
> 0054  80000000 00000d00     7      x: ALU_NOP            __.x
>0010  00000000 80200000 NOP @0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #25 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #25 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>IMM[0] FLT32 {    0,5000,     0,0000,     0,0000,     0,0000}
>  0: MOV TEMP[0].xy, IMM[0].xxxx
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MOV OUT[0], TEMP[0]
>  3: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = insertelement <4 x float> undef, float 0x3FE0000000000000, i32 0
>  %1 = insertelement <4 x float> %0, float 0x3FE0000000000000, i32 1
>  %2 = insertelement <4 x float> %1, float 0,000000e+00, i32 2
>  %3 = insertelement <4 x float> %2, float 0,000000e+00, i32 3
>  %4 = extractelement <4 x float> %3, i32 0
>  %5 = extractelement <4 x float> %3, i32 1
>  %6 = insertelement <4 x float> undef, float %4, i32 0
>  %7 = insertelement <4 x float> %6, float %5, i32 1
>  %8 = insertelement <4 x float> %7, float undef, i32 2
>  %9 = insertelement <4 x float> %8, float undef, i32 3
>  %10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %9, i32 16, i32 0, i32 2)
>  %11 = extractelement <4 x float> %10, i32 0
>  %12 = extractelement <4 x float> %10, i32 1
>  %13 = extractelement <4 x float> %10, i32 2
>  %14 = extractelement <4 x float> %10, i32 3
>  %15 = insertelement <4 x float> undef, float %11, i32 0
>  %16 = insertelement <4 x float> %15, float %12, i32 1
>  %17 = insertelement <4 x float> %16, float %13, i32 2
>  %18 = insertelement <4 x float> %17, float %14, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #26 =========================================== PS/RV730/R700 =====
>===== 18 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000006 a0080000 ALU 3 @12
> 0012  800000fd 00000c90     1      x: MOV                R0.x,  [0x3f000000 0,5].x
> 0014  3f000000 
> 0016  800000fe 20000c90     2      y: MOV                R0.y,  PV.x
>0002  00000004 80800000 TEX 1 @8
> 0008  00001010 f00d1000 68800000 SAMPLE              R0.xyzw, R0.xyzw,   RID:16, SID:0 CT:NNNN
>0004  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #26 OPT ======================================= PS/RV730/R700 =====
>===== 12 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000003 a0000000 ALU 1 @6
> 0006  800000fc 00000c90     1      x: MOV                R0.x,  0.5
>0002  00000004 80800000 TEX 1 @8
> 0008  00001010 f00d1000 fc000000 SAMPLE              R0.xyzw, R0.xx__,   RID:16, SID:0 CT:NNNN
>0004  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL TEMP[0], LOCAL
>IMM[0] FLT32 {    0,0000,     1,0000,     0,0000,     0,0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MOV OUT[0], TEMP[0]
>  3: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float 0,000000e+00, i32 2
>  %7 = insertelement <4 x float> %6, float 0x3FF0000000000000, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 60, i32 1)
>  call void @llvm.R600.store.dummy(i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>declare void @llvm.R600.store.dummy(i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #27 =========================================== VS/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 1 stack ==========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c000a03c 94400b08 EXPORT_DONE        POS   60    R1.xy01  VPM
>0004  c0004000 94600fff EXPORT_DONE        PARAM 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #27 OPT ======================================= VS/RV730/R700 =====
>===== 12 dw ===== 2 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c000a03c 94400b08 EXPORT_DONE        POS   60    R1.xy01  VPM
>0004  c0004000 94400fff EXPORT_DONE        PARAM 0     R0.____  VPM
>0006  00000005 a0000000 ALU 1 @10
> 0010  80000000 00000d00     1      x: ALU_NOP            __.x
>0008  00000000 80200000 NOP @0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_FLOAT, }
>
>===== SHADER #28 ======================================== FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 87961001 00080000 VFETCH              R1.xy01, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:30 NUM:0 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
>   {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
>
>===== SHADER #29 ======================================== FETCH/RV730/R700 =====
>===== 12 dw ===== 3 gprs ===== 0 stack =========================================
>0000  00000002 81000400 VTX 2 @4
> 0004  7c00a000 88cd1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
> 0008  7c00a000 88cd1002 00080010 VFETCH              R2.xyzw, R0.x + 16b ,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, }
>
>===== SHADER #30 ======================================== FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 93564001 00080000 VFETCH              R1.x001, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, }
>
>===== SHADER #31 ======================================== FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 97561001 00080000 VFETCH              R1.xy01, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, }
>
>===== SHADER #32 ======================================== FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 9bd51001 00080000 VFETCH              R1.xyz1, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, }
>
>===== SHADER #33 ======================================== FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 988d1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  call void @llvm.R600.store.dummy(i32 0)
>  ret void
>}
>
>declare void @llvm.R600.store.dummy(i32)
>
>attributes #0 = { "ShaderType"="0" }
>
>===== SHADER #34 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600fff EXPORT_DONE        PIXEL 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #34 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 0 gprs ===== 0 stack ==========================================
>0000  c0000000 94600fff EXPORT_DONE        PIXEL 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #35 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #35 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #36 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #36 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = insertelement <4 x float> undef, float %0, i32 0
>  %9 = insertelement <4 x float> %8, float %1, i32 1
>  %10 = insertelement <4 x float> %9, float %2, i32 2
>  %11 = insertelement <4 x float> %10, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1)
>  %12 = insertelement <4 x float> undef, float %4, i32 0
>  %13 = insertelement <4 x float> %12, float %5, i32 1
>  %14 = insertelement <4 x float> %13, float %6, i32 2
>  %15 = insertelement <4 x float> %14, float %7, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #37 =========================================== VS/RV730/R700 =====
>===== 8 dw ===== 3 gprs ===== 1 stack ==========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0004  c0014000 94600688 EXPORT_DONE        PARAM 0     R2.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #37 OPT ======================================= VS/RV730/R700 =====
>===== 12 dw ===== 3 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c0014000 94400688 EXPORT_DONE        PARAM 0     R2.xyzw  VPM
>0004  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0006  00000005 a0000000 ALU 1 @10
> 0010  80000000 00000d00     1      x: ALU_NOP            __.x
>0008  00000000 80200000 NOP @0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>  0: MOV OUT[0], IN[0]
>  1: END
>STREAMOUT
>  0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.stream.output(<4 x float> %7, i32 0, i32 0, i32 1)
>  %8 = insertelement <4 x float> undef, float %0, i32 0
>  %9 = insertelement <4 x float> %8, float %1, i32 1
>  %10 = insertelement <4 x float> %9, float %2, i32 2
>  %11 = insertelement <4 x float> %10, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1)
>  call void @llvm.R600.store.dummy(i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32)
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>declare void @llvm.R600.store.dummy(i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #38 =========================================== VS/RV730/R700 =====
>===== 12 dw ===== 2 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  00008000 90401fff MEM_STREAM0        WRITE 0     R1.x___  ES:0  VPM
>0004  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0006  c0004000 94600fff EXPORT_DONE        PARAM 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #38 OPT ======================================= VS/RV730/R700 =====
>===== 14 dw ===== 2 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0004  00008000 90401fff MEM_STREAM0        WRITE 0     R1.x___  ES:0  VPM
>0006  c0004000 94400fff EXPORT_DONE        PARAM 0     R0.____  VPM
>0008  00000006 a0000000 ALU 1 @12
> 0012  80000000 00000d00     1      x: ALU_NOP            __.x
>0010  00000000 80200000 NOP @0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  call void @llvm.R600.store.dummy(i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.dummy(i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #39 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600fff EXPORT_DONE        PIXEL 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #39 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 0 gprs ===== 0 stack ==========================================
>0000  c0000000 94600fff EXPORT_DONE        PIXEL 0     R0.____  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #40 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #40 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = load <4 x float> addrspace(8)* null
>  %9 = extractelement <4 x float> %8, i32 0
>  %10 = fmul float %0, %9
>  %11 = load <4 x float> addrspace(8)* null
>  %12 = extractelement <4 x float> %11, i32 1
>  %13 = fmul float %0, %12
>  %14 = load <4 x float> addrspace(8)* null
>  %15 = extractelement <4 x float> %14, i32 2
>  %16 = fmul float %0, %15
>  %17 = load <4 x float> addrspace(8)* null
>  %18 = extractelement <4 x float> %17, i32 3
>  %19 = fmul float %0, %18
>  %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %21 = extractelement <4 x float> %20, i32 0
>  %22 = fmul float %1, %21
>  %23 = fadd float %22, %10
>  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %25 = extractelement <4 x float> %24, i32 1
>  %26 = fmul float %1, %25
>  %27 = fadd float %26, %13
>  %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %29 = extractelement <4 x float> %28, i32 2
>  %30 = fmul float %1, %29
>  %31 = fadd float %30, %16
>  %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %33 = extractelement <4 x float> %32, i32 3
>  %34 = fmul float %1, %33
>  %35 = fadd float %34, %19
>  %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = fmul float %2, %37
>  %39 = fadd float %38, %23
>  %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %41 = extractelement <4 x float> %40, i32 1
>  %42 = fmul float %2, %41
>  %43 = fadd float %42, %27
>  %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %45 = extractelement <4 x float> %44, i32 2
>  %46 = fmul float %2, %45
>  %47 = fadd float %46, %31
>  %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %49 = extractelement <4 x float> %48, i32 3
>  %50 = fmul float %2, %49
>  %51 = fadd float %50, %35
>  %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = fmul float %3, %53
>  %55 = fadd float %54, %39
>  %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %57 = extractelement <4 x float> %56, i32 1
>  %58 = fmul float %3, %57
>  %59 = fadd float %58, %43
>  %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %61 = extractelement <4 x float> %60, i32 2
>  %62 = fmul float %3, %61
>  %63 = fadd float %62, %47
>  %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %65 = extractelement <4 x float> %64, i32 3
>  %66 = fmul float %3, %65
>  %67 = fadd float %66, %51
>  %68 = call float @llvm.AMDIL.clamp.(float %4, float 0,000000e+00, float 0x3FF0000000000000)
>  %69 = call float @llvm.AMDIL.clamp.(float %5, float 0,000000e+00, float 0x3FF0000000000000)
>  %70 = call float @llvm.AMDIL.clamp.(float %6, float 0,000000e+00, float 0x3FF0000000000000)
>  %71 = call float @llvm.AMDIL.clamp.(float %7, float 0,000000e+00, float 0x3FF0000000000000)
>  %72 = insertelement <4 x float> undef, float %55, i32 0
>  %73 = insertelement <4 x float> %72, float %59, i32 1
>  %74 = insertelement <4 x float> %73, float %63, i32 2
>  %75 = insertelement <4 x float> %74, float %67, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %75, i32 60, i32 1)
>  %76 = insertelement <4 x float> undef, float %68, i32 0
>  %77 = insertelement <4 x float> %76, float %69, i32 1
>  %78 = insertelement <4 x float> %77, float %70, i32 2
>  %79 = insertelement <4 x float> %78, float %71, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %79, i32 0, i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #41 =========================================== VS/RV730/R700 =====
>===== 52 dw ===== 5 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  80000006 a04c0000 ALU 20 @12 KC0[CB0:0-31]
> 0012  00100001 00000110     1      x: MUL_IEEE           R0.x,  R1.x, KC0[0].x
> 0014  00900001 20000110            y: MUL_IEEE           R0.y,  R1.x, KC0[0].y
> 0016  01100001 40000110            z: MUL_IEEE           R0.z,  R1.x, KC0[0].z
> 0018  81900001 60000110            w: MUL_IEEE           R0.w,  R1.x, KC0[0].w
> 0020  00102401 000280fe     2      x: MULADD_IEEE        R0.x,  R1.y, KC0[1].x, PV.x
> 0022  00902401 200284fe            y: MULADD_IEEE        R0.y,  R1.y, KC0[1].y, PV.y
> 0024  01102401 400288fe            z: MULADD_IEEE        R0.z,  R1.y, KC0[1].z, PV.z
> 0026  81902401 60028cfe            w: MULADD_IEEE        R0.w,  R1.y, KC0[1].w, PV.w
> 0028  00104801 00228000     3      x: MULADD_IEEE        R1.x,  R1.z, KC0[2].x, R0.x
> 0030  00904801 20228400            y: MULADD_IEEE        R1.y,  R1.z, KC0[2].y, R0.y
> 0032  01104801 40828800            z: MULADD_IEEE        R4.z,  R1.z, KC0[2].z, R0.z
> 0034  81904801 60628c00            w: MULADD_IEEE        R3.w,  R1.z, KC0[2].w, R0.w
> 0036  00000002 80000c90     4      x: MOV_sat            R0.x,  R2.x
> 0038  81906c01 60628c03            w: MULADD_IEEE        R3.w,  R1.w, KC0[3].w, R3.w
> 0040  80906c01 20628401     5      y: MULADD_IEEE        R3.y,  R1.w, KC0[3].y, R1.y
> 0042  00106c01 00628001     6      x: MULADD_IEEE        R3.x,  R1.w, KC0[3].x, R1.x
> 0044  00000402 a0000c90            y: MOV_sat            R0.y,  R2.y
> 0046  01106c01 40628804            z: MULADD_IEEE        R3.z,  R1.w, KC0[3].z, R4.z
> 0048  80000c02 e0080c90            w: MOV_sat            R0.w,  R2.w                   VEC_120
> 0050  80000802 c0000c90     7      z: MOV_sat            R0.z,  R2.z
>0004  c001a03c 94400688 EXPORT_DONE        POS   60    R3.xyzw  VPM
>0006  c0004000 94600688 EXPORT_DONE        PARAM 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #41 OPT ======================================= VS/RV730/R700 =====
>===== 56 dw ===== 3 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  40000006 a0500000 ALU 21 @12 KC0[CB0:0-15]
> 0012  01900001 0f800110     1      x: MUL_IEEE           T0.x,  R1.x, KC0[0].w
> 0014  81100001 2f800110            y: MUL_IEEE           T0.y,  R1.x, KC0[0].z
> 0016  01902401 0f82807c     2      x: MULADD_IEEE        T0.x,  R1.y, KC0[1].w, T0.x
> 0018  01102401 2f82847c            y: MULADD_IEEE        T0.y,  R1.y, KC0[1].z, T0.y
> 0020  00900001 4f800110            z: MUL_IEEE           T0.z,  R1.x, KC0[0].y
> 0022  80100001 6f800110            w: MUL_IEEE           T0.w,  R1.x, KC0[0].x
> 0024  01104801 2fa2847c     3      y: MULADD_IEEE        T1.y,  R1.z, KC0[2].z, T0.y
> 0026  00902401 4f82887c            z: MULADD_IEEE        T0.z,  R1.y, KC0[1].y, T0.z
> 0028  80102401 6f828c7c            w: MULADD_IEEE        T0.w,  R1.y, KC0[1].x, T0.w
> 0030  01904801 0fa2807c     4      x: MULADD_IEEE        T1.x,  R1.z, KC0[2].w, T0.x
> 0032  80104801 2f828c7c            y: MULADD_IEEE        T0.y,  R1.z, KC0[2].x, T0.w
> 0034  00904801 0f8e887c     5      x: MULADD_IEEE        T0.x,  R1.z, KC0[2].y, T0.z   VEC_102
> 0036  00000402 a0000c90            y: MOV_sat            R0.y,  R2.y
> 0038  00000802 c0000c90            z: MOV_sat            R0.z,  R2.z
> 0040  00000c02 e0000c90            w: MOV_sat            R0.w,  R2.w
> 0042  80000c01 6f800c90            t: MOV                T0.w,  R1.w
> 0044  00106c7c 0022847c     6      x: MULADD_IEEE        R1.x,  T0.w, KC0[3].x, T0.y
> 0046  00906c7c 2022807c            y: MULADD_IEEE        R1.y,  T0.w, KC0[3].y, T0.x
> 0048  01106c7c 4026847d            z: MULADD_IEEE        R1.z,  T0.w, KC0[3].z, T1.y   VEC_021
> 0050  01906c7c 602a807d            w: MULADD_IEEE        R1.w,  T0.w, KC0[3].w, T1.x   VEC_120
> 0052  80000002 80040c90            t: MOV_sat            R0.x,  R2.x                   SCL_122
>0004  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0006  c0004000 94400688 EXPORT_DONE        PARAM 0     R0.xyzw  VPM
>0008  0000001b a0000000 ALU 1 @54
> 0054  80000000 00000d00     7      x: ALU_NOP            __.x
>0010  00000000 80200000 NOP @0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #42 =========================================== PS/RV730/R700 =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #42 OPT ======================================= PS/RV730/R700 =====
>===== 2 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>java version "1.7.0_40"
>OpenJDK Runtime Environment (IcedTea 2.4.1) (suse-8.18.1-i386)
>OpenJDK Client VM (build 24.0-b50, mixed mode)
>konqueror(17086) KMimeTypePrivate::ensureXmlDataLoaded: Missing <comment> field in "application/x-msdownload.xml" 
>konqueror(17086) KMimeTypePrivate::ensureXmlDataLoaded: Missing <comment> field in "text/x-component.xml" 
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
>   {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
>
>===== SHADER #43 ======================================== FETCH/RV730/R700 =====
>===== 12 dw ===== 3 gprs ===== 0 stack =========================================
>0000  00000002 81000400 VTX 2 @4
> 0004  7c00a000 88cd1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
> 0008  7c00a000 88cd1002 00080010 VFETCH              R2.xyzw, R0.x + 16b ,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float %2, i32 2
>  %7 = insertelement <4 x float> %6, float %3, i32 3
>  %8 = extractelement <4 x float> %7, i32 0
>  %9 = extractelement <4 x float> %7, i32 1
>  %10 = insertelement <4 x float> undef, float %8, i32 0
>  %11 = insertelement <4 x float> %10, float %9, i32 1
>  %12 = insertelement <4 x float> %11, float undef, i32 2
>  %13 = insertelement <4 x float> %12, float undef, i32 3
>  %14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %13, i32 16, i32 0, i32 2)
>  %15 = extractelement <4 x float> %14, i32 0
>  %16 = extractelement <4 x float> %14, i32 1
>  %17 = extractelement <4 x float> %14, i32 2
>  %18 = extractelement <4 x float> %14, i32 3
>  %19 = insertelement <4 x float> undef, float %15, i32 0
>  %20 = insertelement <4 x float> %19, float %16, i32 1
>  %21 = insertelement <4 x float> %20, float %17, i32 2
>  %22 = insertelement <4 x float> %21, float %18, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %22, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #44 =========================================== PS/RV730/R700 =====
>===== 12 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000004 80800000 TEX 1 @8
> 0008  00001010 f00d1000 68800000 SAMPLE              R0.xyzw, R0.xyzw,   RID:16, SID:0 CT:NNNN
>0002  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #44 OPT ======================================= PS/RV730/R700 =====
>===== 8 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  00000002 80800000 TEX 1 @4
> 0004  00001010 f00d1000 68800000 SAMPLE              R0.xyzw, R0.xyzw,   RID:16, SID:0 CT:NNNN
>0002  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = call float @llvm.R600.load.input(i32 8)
>  %5 = call float @llvm.R600.load.input(i32 9)
>  %6 = call float @llvm.R600.load.input(i32 10)
>  %7 = call float @llvm.R600.load.input(i32 11)
>  %8 = insertelement <4 x float> undef, float %0, i32 0
>  %9 = insertelement <4 x float> %8, float %1, i32 1
>  %10 = insertelement <4 x float> %9, float %2, i32 2
>  %11 = insertelement <4 x float> %10, float %3, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1)
>  %12 = insertelement <4 x float> undef, float %4, i32 0
>  %13 = insertelement <4 x float> %12, float %5, i32 1
>  %14 = insertelement <4 x float> %13, float %6, i32 2
>  %15 = insertelement <4 x float> %14, float %7, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #45 =========================================== VS/RV730/R700 =====
>===== 8 dw ===== 3 gprs ===== 1 stack ==========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0004  c0014000 94600688 EXPORT_DONE        PARAM 0     R2.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #45 OPT ======================================= VS/RV730/R700 =====
>===== 12 dw ===== 3 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  c0014000 94400688 EXPORT_DONE        PARAM 0     R2.xyzw  VPM
>0004  c000a03c 94400688 EXPORT_DONE        POS   60    R1.xyzw  VPM
>0006  00000005 a0000000 ALU 1 @10
> 0010  80000000 00000d00     1      x: ALU_NOP            __.x
>0008  00000000 80200000 NOP @0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..3]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    0,5000,     0,0000,     1,0000,     3,1416}
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MAD TEMP[1].xy, CONST[1].xyyy, IMM[0].xxxx, IMM[0].xxxx
>  3: ADD TEMP[1].xy, TEMP[1].xyyy, -IN[0].xyyy
>  4: MOV TEMP[2].yzw, TEMP[0].zyzw
>  5: DP2 TEMP[1].x, TEMP[1].xyyy, TEMP[1].xyyy
>  6: RSQ TEMP[3].x, TEMP[1].xxxx
>  7: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[1].xxxx
>  8: CMP TEMP[3].x, -TEMP[1].xxxx, TEMP[3].xxxx, IMM[0].yyyy
>  9: RCP TEMP[1].x, CONST[2].xxxx
> 10: MUL TEMP[1].x, TEMP[3].xxxx, TEMP[1].xxxx
> 11: ADD TEMP[1].x, IMM[0].zzzz, -TEMP[1].xxxx
> 12: MAX TEMP[1].x, IMM[0].yyyy, TEMP[1].xxxx
> 13: MUL TEMP[1].x, TEMP[1].xxxx, IMM[0].wwww
> 14: COS TEMP[1].x, TEMP[1].xxxx
> 15: MUL TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx
> 16: ADD TEMP[1].x, IMM[0].xxxx, -TEMP[1].xxxx
> 17: MAD TEMP[2].x, TEMP[1].xxxx, CONST[3].xxxx, TEMP[0].xxxx
> 18: MOV OUT[0], TEMP[2]
> 19: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = insertelement <4 x float> undef, float %0, i32 0
>  %5 = insertelement <4 x float> %4, float %1, i32 1
>  %6 = insertelement <4 x float> %5, float 0,000000e+00, i32 2
>  %7 = insertelement <4 x float> %6, float 0,000000e+00, i32 3
>  %8 = extractelement <4 x float> %7, i32 0
>  %9 = extractelement <4 x float> %7, i32 1
>  %10 = insertelement <4 x float> undef, float %8, i32 0
>  %11 = insertelement <4 x float> %10, float %9, i32 1
>  %12 = insertelement <4 x float> %11, float undef, i32 2
>  %13 = insertelement <4 x float> %12, float undef, i32 3
>  %14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %13, i32 16, i32 0, i32 2)
>  %15 = extractelement <4 x float> %14, i32 0
>  %16 = extractelement <4 x float> %14, i32 1
>  %17 = extractelement <4 x float> %14, i32 2
>  %18 = extractelement <4 x float> %14, i32 3
>  %19 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %20 = extractelement <4 x float> %19, i32 0
>  %21 = fmul float %20, 0x3FE0000000000000
>  %22 = fadd float %21, 0x3FE0000000000000
>  %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %24 = extractelement <4 x float> %23, i32 1
>  %25 = fmul float %24, 0x3FE0000000000000
>  %26 = fadd float %25, 0x3FE0000000000000
>  %27 = fsub float -0,000000e+00, %0
>  %28 = fadd float %22, %27
>  %29 = fsub float -0,000000e+00, %1
>  %30 = fadd float %26, %29
>  %31 = insertelement <4 x float> undef, float %28, i32 0
>  %32 = insertelement <4 x float> %31, float %30, i32 1
>  %33 = insertelement <4 x float> %32, float 0,000000e+00, i32 2
>  %34 = insertelement <4 x float> %33, float 0,000000e+00, i32 3
>  %35 = insertelement <4 x float> undef, float %28, i32 0
>  %36 = insertelement <4 x float> %35, float %30, i32 1
>  %37 = insertelement <4 x float> %36, float 0,000000e+00, i32 2
>  %38 = insertelement <4 x float> %37, float 0,000000e+00, i32 3
>  %39 = call float @llvm.AMDGPU.dp4(<4 x float> %34, <4 x float> %38)
>  %40 = call float @llvm.AMDGPU.rsq(float %39)
>  %41 = fmul float %40, %39
>  %42 = fsub float -0,000000e+00, %39
>  %43 = fcmp ult float %42, 0,000000e+00
>  %44 = select i1 %43, float %41, float 0,000000e+00
>  %45 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = fdiv float 0x3FF0000000000000, %46
>  %48 = fmul float %44, %47
>  %49 = fsub float -0,000000e+00, %48
>  %50 = fadd float 0x3FF0000000000000, %49
>  %51 = fcmp uge float 0,000000e+00, %50
>  %52 = select i1 %51, float 0,000000e+00, float %50
>  %53 = fmul float %52, 0x400921FB60000000
>  %54 = call float @llvm.cos.f32(float %53)
>  %55 = fmul float %54, 0x3FE0000000000000
>  %56 = fsub float -0,000000e+00, %55
>  %57 = fadd float 0x3FE0000000000000, %56
>  %58 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %59 = extractelement <4 x float> %58, i32 0
>  %60 = fmul float %57, %59
>  %61 = fadd float %60, %15
>  %62 = insertelement <4 x float> undef, float %61, i32 0
>  %63 = insertelement <4 x float> %62, float %16, i32 1
>  %64 = insertelement <4 x float> %63, float %17, i32 2
>  %65 = insertelement <4 x float> %64, float %18, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %65, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #1
>
>; Function Attrs: nounwind readonly
>declare float @llvm.cos.f32(float) #2
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>attributes #2 = { nounwind readonly }
>
>===== SHADER #46 =========================================== PS/RV730/R700 =====
>===== 70 dw ===== 3 gprs ===== 0 stack =========================================
>0000  80000008 a0640000 ALU 26 @16 KC0[CB0:0-31]
> 0016  001f8481 002280fc     1      x: MULADD_IEEE        R1.x,  KC0[1].y, 0.5, 0.5
> 0018  801f8081 202280fc            y: MULADD_IEEE        R1.y,  KC0[1].x, 0.5, 0.5
> 0020  80000082 40203310     2      t: RECIP_IEEE         R1.z,  KC0[2].x
> 0022  800000fd 60200c90     3      w: MOV                R1.w,  [0x3e22f983 0,159155].x
> 0024  3e22f983 
> 0026  82800001 20400010     4      y: ADD                R2.y,  R1.x, -R0.y
> 0028  02000401 00400010     5      x: ADD                R2.x,  R1.y, -R0.x
> 0030  800000fd 40400c90            z: MOV                R2.z,  [0x00000000 0].x
> 0032  00000000 
> 0034  800008fe 60400c90     6      w: MOV                R2.w,  PV.z
> 0036  00004002 00202810     7      x: DOT4               R1.x,  R2.x, R2.x
> 0038  00804402 20202800            y: DOT4               __.y,  R2.y, R2.y
> 0040  01004802 40202800            z: DOT4               __.z,  R2.z, R2.z
> 0042  81804c02 60202800            w: DOT4               __.w,  R2.w, R2.w
> 0044  80000001 00403390     8      t: RECIPSQRT_CLAMPED  R2.x,  R1.x
> 0046  80002002 00400110     9      x: MUL_IEEE           R2.x,  R2.x, R1.x
> 0048  801f1001 002340fe    10      x: CNDGE              R1.x,  -R1.x, 0, PV.x
> 0050  81002001 00200110    11      x: MUL_IEEE           R1.x,  R1.x, R1.z
> 0052  801f30fe 00200010    12      x: ADD                R1.x,  -PV.x, 1.0
> 0054  801fc0fe 002320f8    13      x: CNDGT              R1.x,  PV.x, PV.x, 0
> 0056  801fa001 00200110    14      x: MUL_IEEE           R1.x,  R1.x, [0x40490fdb 3,14159].x
> 0058  40490fdb 
> 0060  801fcc01 00200110    15      x: MUL_IEEE           R1.x,  R1.w, PV.x
> 0062  80000001 00203790    16      t: COS                R1.x,  R1.x
> 0064  801fa001 002280fc    17      x: MULADD_IEEE        R1.x,  R1.x, [0xbf000000 -0,5].x, 0.5
> 0066  bf000000 
>0002  00000006 80800000 TEX 1 @12
> 0012  00001010 f00d1000 68800000 SAMPLE              R0.xyzw, R0.xyzw,   RID:16, SID:0 CT:NNNN
>0004  80000022 a0000000 ALU 1 @68 KC0[CB0:0-31]
> 0068  80106001 00028000    18      x: MULADD_IEEE        R0.x,  R1.x, KC0[3].x, R0.x
>0006  c0000000 94600688 EXPORT_DONE        PIXEL 0     R0.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #46 OPT ======================================= PS/RV730/R700 =====
>===== 50 dw ===== 2 gprs ===== 0 stack =========================================
>0000  00000004 80800000 TEX 1 @8
> 0008  00001010 f00d1001 68800000 SAMPLE              R1.xyzw, R0.xyzw,   RID:16, SID:0 CT:NNNN
>0002  40000006 a0480000 ALU 19 @12 KC0[CB0:0-15]
> 0012  001f8481 4f8280fc     1      z: MULADD_IEEE        T0.z,  KC0[1].y, 0.5, 0.5
> 0014  801f8081 6f8280fc            w: MULADD_IEEE        T0.w,  KC0[1].x, 0.5, 0.5
> 0016  02000c7c 0f800010     2      x: ADD                T0.x,  T0.w, -R0.x
> 0018  8280087c 2f800010            y: ADD                T0.y,  T0.z, -R0.y
> 0020  000f807c 0f802810     3      x: DOT4               T0.x,  T0.x, T0.x
> 0022  008f847c 20002800            y: DOT4               __.y,  T0.y, T0.y
> 0024  001f00f8 40002800            z: DOT4               __.z,  0, 0
> 0026  801f00f8 60002800            w: DOT4               __.w,  0, 0
> 0028  8000007c 2f803390     4      t: RECIPSQRT_CLAMPED  T0.y,  T0.x
> 0030  800f847c 2f800110     5      y: MUL_IEEE           T0.y,  T0.y, T0.x
> 0032  001f107c 0f83447c     6      x: CNDGE              T0.x,  -T0.x, 0, T0.y
> 0034  80000082 2f803310            t: RECIP_IEEE         T0.y,  KC0[2].x
> 0036  808f907c 0f8280f9     7      x: MULADD_IEEE        T0.x,  -T0.x, T0.y, 1.0
> 0038  800f807c 0f8320f8     8      x: CNDGT              T0.x,  T0.x, T0.x, 0
> 0040  801f807c 0f800110     9      x: MUL_IEEE           T0.x,  T0.x, 0.5
> 0042  8000007c 0f803790    10      t: COS                T0.x,  T0.x
> 0044  801fa07c 0f8280fc    11      x: MULADD_IEEE        T0.x,  T0.x, [0xbf000000 -0,5].x, 0.5
> 0046  bf000000 
> 0048  8010607c 00228001    12      x: MULADD_IEEE        R1.x,  T0.x, KC0[3].x, R1.x
>0004  c0008000 94600688 EXPORT_DONE        PIXEL 0     R1.xyzw  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    1,0000,     0,5000,     0,0000,     0,0000}
>  0: MOV TEMP[0].w, IMM[0].xxxx
>  1: MOV TEMP[0].xyz, IN[0].xyzx
>  2: MAD TEMP[1].xy, IN[0].xyyy, IMM[0].yyyy, IMM[0].yyyy
>  3: MOV OUT[0], TEMP[0]
>  4: MOV OUT[1], TEMP[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = fmul float %0, 0x3FE0000000000000
>  %5 = fadd float %4, 0x3FE0000000000000
>  %6 = fmul float %1, 0x3FE0000000000000
>  %7 = fadd float %6, 0x3FE0000000000000
>  %8 = insertelement <4 x float> undef, float %0, i32 0
>  %9 = insertelement <4 x float> %8, float %1, i32 1
>  %10 = insertelement <4 x float> %9, float %2, i32 2
>  %11 = insertelement <4 x float> %10, float 0x3FF0000000000000, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1)
>  %12 = insertelement <4 x float> undef, float %5, i32 0
>  %13 = insertelement <4 x float> %12, float %7, i32 1
>  %14 = insertelement <4 x float> %13, float 0,000000e+00, i32 2
>  %15 = insertelement <4 x float> %14, float 0,000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #47 =========================================== VS/RV730/R700 =====
>===== 16 dw ===== 2 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  00000006 a0040000 ALU 2 @12
> 0012  801f8401 200280fc     1      y: MULADD_IEEE        R0.y,  R1.y, 0.5, 0.5
> 0014  801f8001 000280fc     2      x: MULADD_IEEE        R0.x,  R1.x, 0.5, 0.5
>0004  c000a03c 94400a88 EXPORT_DONE        POS   60    R1.xyz1  VPM
>0006  c0004000 94600908 EXPORT_DONE        PARAM 0     R0.xy00  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #47 OPT ======================================= VS/RV730/R700 =====
>===== 18 dw ===== 2 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  00000006 a0040000 ALU 2 @12
> 0012  001f8001 000280fc     1      x: MULADD_IEEE        R0.x,  R1.x, 0.5, 0.5
> 0014  801f8401 200280fc            y: MULADD_IEEE        R0.y,  R1.y, 0.5, 0.5
>0004  c0004000 94400908 EXPORT_DONE        PARAM 0     R0.xy00  VPM
>0006  c000a03c 94400a88 EXPORT_DONE        POS   60    R1.xyz1  VPM
>0008  00000008 a0000000 ALU 1 @16
> 0016  80000000 00000d00     2      x: ALU_NOP            __.x
>0010  00000000 80200000 NOP @0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>Vertex elements state:
>   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_FLOAT, }
>
>===== SHADER #48 ======================================== FETCH/RV730/R700 =====
>===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
>0000  00000002 81000000 VTX 1 @4
> 0004  7c00a000 8c151001 00080000 VFETCH              R1.xyz1, R0.x,   RID:160  VERTEX MFC:31 UCF:0 FMT(DTA:48 NUM:0 COMP:0 MODE:1)
>0002  00000000 8a000000 RET @0
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL CONST[0..2]
>DCL TEMP[0..6], LOCAL
>IMM[0] FLT32 {    0,5000,     0,9990,     1,0000,     0,0000}
>IMM[1] FLT32 {    0,9000,     4,0000,     0,5628,     0,7502}
>IMM[2] FLT32 {    0,3750,     2,0000,    -1,0000,     1,0000}
>IMM[3] FLT32 { -288,5390,    -0,1667,    10,0000,     0,4800}
>IMM[4] FLT32 {    0,4800,     1,0800,     1,2000,     0,0000}
>  0: ABS TEMP[0].x, IN[0].xxxx
>  1: FSLT TEMP[1].x, IMM[0].yyyy, TEMP[0].xxxx
>  2: UIF TEMP[1].xxxx :0
>  3:   MAD TEMP[1].xy, IN[0].yzzz, IMM[0].xxxx, IMM[0].zxxx
>  4:   MOV TEMP[1].xy, TEMP[1].xyyy
>  5:   TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D
>  6:   MOV TEMP[1].xyz, TEMP[1].xyzx
>  7:   MOV TEMP[2].yz, IMM[0].wwww
>  8:   MOV TEMP[2].x, -IN[0].xxxx
>  9:   MOV TEMP[2].xyz, TEMP[2].xyzx
> 10: ELSE :0
> 11:   ABS TEMP[3].x, IN[0].zzzz
> 12:   FSLT TEMP[3].x, IMM[0].yyyy, TEMP[3].xxxx
> 13:   UIF TEMP[3].xxxx :0
> 14:     MAD TEMP[3].xy, IN[0].yxxx, IMM[0].xxxx, IMM[0].zxxx
> 15:     MOV TEMP[3].xy, TEMP[3].xyyy
> 16:     TEX TEMP[3].xyz, TEMP[3], SAMP[0], 2D
> 17:     MOV TEMP[1].xyz, TEMP[3].xyzx
> 18:     MOV TEMP[3].xy, IMM[0].wwww
> 19:     MOV TEMP[3].z, -IN[0].zzzz
> 20:     MOV TEMP[2].xyz, TEMP[3].xyzx
> 21:   ELSE :0
> 22:     MAD TEMP[3].xy, IN[0].xzzz, IMM[0].xxxx, IMM[0].xxxx
> 23:     MOV TEMP[3].xy, TEMP[3].xyyy
> 24:     TEX TEMP[3].xyz, TEMP[3], SAMP[0], 2D
> 25:     MOV TEMP[1].xyz, TEMP[3].xyzx
> 26:     MOV TEMP[2].xyz, IMM[0].wzww
> 27:   ENDIF
> 28: ENDIF
> 29: DP3 TEMP[3].x, IN[0].xyzz, IN[0].xyzz
> 30: RSQ TEMP[3].x, TEMP[3].xxxx
> 31: MUL TEMP[0].x, IMM[0].xxxx, TEMP[3].xxxx
> 32: ADD TEMP[3].xyz, IN[0].xyzz, -CONST[1].xyzz
> 33: DP3 TEMP[3].x, TEMP[3].xyzz, TEMP[3].xyzz
> 34: RSQ TEMP[4].x, TEMP[3].xxxx
> 35: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[3].xxxx
> 36: CMP TEMP[4].x, -TEMP[3].xxxx, TEMP[4].xxxx, IMM[0].wwww
> 37: RCP TEMP[3].x, CONST[2].xxxx
> 38: MUL TEMP[3].x, TEMP[4].xxxx, TEMP[3].xxxx
> 39: POW TEMP[3].x, TEMP[3].xxxx, IMM[1].yyyy
> 40: RCP TEMP[3].x, TEMP[3].xxxx
> 41: MUL TEMP[3].x, IMM[1].xxxx, TEMP[3].xxxx
> 42: ADD TEMP[3].x, IMM[0].zzzz, -TEMP[3].xxxx
> 43: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[3].xxxx
> 44: MOV TEMP[3].xyz, -CONST[0].xyzx
> 45: MUL TEMP[4].x, TEMP[3].yyyy, TEMP[3].yyyy
> 46: ADD TEMP[4].x, IMM[0].zzzz, -TEMP[4].xxxx
> 47: MUL TEMP[4].x, TEMP[4].xxxx, IMM[1].zzzz
> 48: ADD TEMP[4].x, IMM[0].zzzz, -TEMP[4].xxxx
> 49: FSLT TEMP[5].x, TEMP[4].xxxx, IMM[0].wwww
> 50: UIF TEMP[5].xxxx :0
> 51:   MOV TEMP[5].xyz, IMM[0].wwww
> 52: ELSE :0
> 53:   RSQ TEMP[6].x, TEMP[4].xxxx
> 54:   MUL TEMP[6].x, TEMP[6].xxxx, TEMP[4].xxxx
> 55:   CMP TEMP[6].x, -TEMP[4].xxxx, TEMP[6].xxxx, IMM[0].wwww
> 56:   MAD TEMP[4].x, IMM[1].wwww, TEMP[3].yyyy, TEMP[6].xxxx
> 57:   MUL TEMP[4].xyz, TEMP[4].xxxx, IMM[0].wzww
> 58:   MAD TEMP[5].xyz, IMM[1].wwww, TEMP[3].xyzz, -TEMP[4].xyzz
> 59: ENDIF
> 60: MOV TEMP[3].xyz, -TEMP[5].xyzx
> 61: DP3 TEMP[2].x, TEMP[3].xyzz, TEMP[2].xyzz
> 62: MAX TEMP[2].x, IMM[0].wwww, TEMP[2].xxxx
> 63: MAD TEMP[4].xy, IN[0].xzzz, IMM[0].xxxx, IMM[0].xxxx
> 64: MOV TEMP[4].xy, TEMP[4].xyyy
> 65: TEX TEMP[4].x, TEMP[4], SAMP[2], 2D
> 66: FSLT TEMP[4].x, IN[0].yyyy, TEMP[4].xxxx
> 67: UIF TEMP[4].xxxx :0
> 68:   MUL TEMP[4].xy, IN[0].yyyy, TEMP[3].xzzz
> 69:   RCP TEMP[5].x, TEMP[3].yyyy
> 70:   MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[5].xxxx
> 71:   ADD TEMP[4].xy, IN[0].xzzz, -TEMP[4].xyyy
> 72:   MAD TEMP[4].xy, IMM[2].xxxx, TEMP[4].xyyy, IMM[0].xxxx
> 73:   MOV TEMP[4].xy, TEMP[4].xyyy
> 74:   TEX TEMP[4].xy, TEMP[4], SAMP[1], 2D
> 75:   MUL TEMP[5].x, TEMP[2].xxxx, TEMP[4].xxxx
> 76:   MUL TEMP[5].x, TEMP[5].xxxx, IMM[2].yyyy
> 77:   MAD TEMP[0].x, TEMP[5].xxxx, TEMP[4].yyyy, TEMP[0].xxxx
> 78: ELSE :0
> 79:   ADD TEMP[4].xyz, IMM[2].zzzz, -IN[0].xyzz
> 80:   RCP TEMP[5].x, TEMP[3].xxxx
> 81:   RCP TEMP[5].y, TEMP[3].yyyy
> 82:   RCP TEMP[5].z, TEMP[3].zzzz
> 83:   MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xyzz
> 84:   ADD TEMP[5].xyz, IMM[2].wyww, -IN[0].xyzz
> 85:   RCP TEMP[6].x, TEMP[3].xxxx
> 86:   RCP TEMP[6].y, TEMP[3].yyyy
> 87:   RCP TEMP[6].z, TEMP[3].zzzz
> 88:   MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xyzz
> 89:   MIN TEMP[6].xyz, TEMP[4].xyzz, TEMP[5].xyzz
> 90:   MAX TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xyzz
> 91:   MIN TEMP[5].x, TEMP[4].xxxx, TEMP[4].yyyy
> 92:   MIN TEMP[4].x, TEMP[5].xxxx, TEMP[4].zzzz
> 93:   MAD TEMP[3].x, TEMP[3].yyyy, TEMP[4].xxxx, IN[0].yyyy
> 94:   ADD TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 95:   MUL TEMP[3].x, IMM[3].xxxx, TEMP[3].xxxx
> 96:   MAX TEMP[5].x, TEMP[6].xxxx, TEMP[6].yyyy
> 97:   MAX TEMP[5].x, TEMP[5].xxxx, TEMP[6].zzzz
> 98:   ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[5].xxxx
> 99:   MAD TEMP[4].x, IMM[3].zzzz, TEMP[4].xxxx, IMM[0].zzzz
>100:   RCP TEMP[4].x, TEMP[4].xxxx
>101:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>102:   EX2 TEMP[3].x, TEMP[3].xxxx
>103:   ADD TEMP[3].x, IMM[0].zzzz, TEMP[3].xxxx
>104:   RCP TEMP[3].x, TEMP[3].xxxx
>105:   MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
>106:   MAD TEMP[0].x, TEMP[2].xxxx, IMM[0].xxxx, TEMP[0].xxxx
>107: ENDIF
>108: MUL TEMP[0].xyz, TEMP[1].xyzz, TEMP[0].xxxx
>109: MOV TEMP[1].w, IMM[0].zzzz
>110: MOV TEMP[1].xyz, TEMP[0].xyzx
>111: MOV TEMP[1], TEMP[1]
>112: MAD TEMP[2].xy, IN[0].xzzz, IMM[0].xxxx, IMM[0].xxxx
>113: MOV TEMP[2].xy, TEMP[2].xyyy
>114: TEX TEMP[2].x, TEMP[2], SAMP[2], 2D
>115: FSLT TEMP[2].x, IN[0].yyyy, TEMP[2].xxxx
>116: UIF TEMP[2].xxxx :0
>117:   MUL TEMP[1].xyz, TEMP[0].xyzz, IMM[4].xyzz
>118: ENDIF
>119: MOV OUT[0], TEMP[1]
>120: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = call float @fabs(float %0)
>  %5 = fcmp olt float 0x3FEFF7CEE0000000, %4
>  %6 = sext i1 %5 to i32
>  %7 = bitcast i32 %6 to float
>  %8 = bitcast float %7 to i32
>  %9 = icmp ne i32 %8, 0
>  br i1 %9, label %IF, label %ELSE
>
>IF:                                               ; preds = %main_body
>  %10 = fmul float %1, 0x3FE0000000000000
>  %11 = fadd float %10, 0x3FF0000000000000
>  %12 = fmul float %2, 0x3FE0000000000000
>  %13 = fadd float %12, 0x3FE0000000000000
>  %14 = insertelement <4 x float> undef, float %11, i32 0
>  %15 = insertelement <4 x float> %14, float %13, i32 1
>  %16 = insertelement <4 x float> %15, float 0,000000e+00, i32 2
>  %17 = insertelement <4 x float> %16, float 0,000000e+00, i32 3
>  %18 = extractelement <4 x float> %17, i32 0
>  %19 = extractelement <4 x float> %17, i32 1
>  %20 = insertelement <4 x float> undef, float %18, i32 0
>  %21 = insertelement <4 x float> %20, float %19, i32 1
>  %22 = insertelement <4 x float> %21, float undef, i32 2
>  %23 = insertelement <4 x float> %22, float undef, i32 3
>  %24 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %23, i32 16, i32 0, i32 2)
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = extractelement <4 x float> %24, i32 1
>  %27 = extractelement <4 x float> %24, i32 2
>  %28 = fsub float -0,000000e+00, %0
>  br label %ENDIF
>
>ELSE:                                             ; preds = %main_body
>  %29 = call float @fabs(float %2)
>  %30 = fcmp olt float 0x3FEFF7CEE0000000, %29
>  %31 = sext i1 %30 to i32
>  %32 = bitcast i32 %31 to float
>  %33 = bitcast float %32 to i32
>  %34 = icmp ne i32 %33, 0
>  br i1 %34, label %IF29, label %ELSE30
>
>ENDIF:                                            ; preds = %IF29, %ELSE30, %IF
>  %temp4.0 = phi float [ %25, %IF ], [ %117, %IF29 ], [ %136, %ELSE30 ]
>  %temp5.0 = phi float [ %26, %IF ], [ %118, %IF29 ], [ %137, %ELSE30 ]
>  %temp6.0 = phi float [ %27, %IF ], [ %119, %IF29 ], [ %138, %ELSE30 ]
>  %temp8.0 = phi float [ %28, %IF ], [ 0,000000e+00, %ELSE30 ], [ 0,000000e+00, %IF29 ]
>  %temp9.0 = phi float [ 0,000000e+00, %IF ], [ 0,000000e+00, %IF29 ], [ 0x3FF0000000000000, %ELSE30 ]
>  %temp10.0 = phi float [ 0,000000e+00, %IF ], [ %120, %IF29 ], [ 0,000000e+00, %ELSE30 ]
>  %35 = insertelement <4 x float> undef, float %0, i32 0
>  %36 = insertelement <4 x float> %35, float %1, i32 1
>  %37 = insertelement <4 x float> %36, float %2, i32 2
>  %38 = insertelement <4 x float> %37, float 0,000000e+00, i32 3
>  %39 = insertelement <4 x float> undef, float %0, i32 0
>  %40 = insertelement <4 x float> %39, float %1, i32 1
>  %41 = insertelement <4 x float> %40, float %2, i32 2
>  %42 = insertelement <4 x float> %41, float 0,000000e+00, i32 3
>  %43 = call float @llvm.AMDGPU.dp4(<4 x float> %38, <4 x float> %42)
>  %44 = call float @llvm.AMDGPU.rsq(float %43)
>  %45 = fmul float 0x3FE0000000000000, %44
>  %46 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %47 = extractelement <4 x float> %46, i32 0
>  %48 = fsub float -0,000000e+00, %47
>  %49 = fadd float %0, %48
>  %50 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %51 = extractelement <4 x float> %50, i32 1
>  %52 = fsub float -0,000000e+00, %51
>  %53 = fadd float %1, %52
>  %54 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %55 = extractelement <4 x float> %54, i32 2
>  %56 = fsub float -0,000000e+00, %55
>  %57 = fadd float %2, %56
>  %58 = insertelement <4 x float> undef, float %49, i32 0
>  %59 = insertelement <4 x float> %58, float %53, i32 1
>  %60 = insertelement <4 x float> %59, float %57, i32 2
>  %61 = insertelement <4 x float> %60, float 0,000000e+00, i32 3
>  %62 = insertelement <4 x float> undef, float %49, i32 0
>  %63 = insertelement <4 x float> %62, float %53, i32 1
>  %64 = insertelement <4 x float> %63, float %57, i32 2
>  %65 = insertelement <4 x float> %64, float 0,000000e+00, i32 3
>  %66 = call float @llvm.AMDGPU.dp4(<4 x float> %61, <4 x float> %65)
>  %67 = call float @llvm.AMDGPU.rsq(float %66)
>  %68 = fmul float %67, %66
>  %69 = fsub float -0,000000e+00, %66
>  %70 = fcmp ult float %69, 0,000000e+00
>  %71 = select i1 %70, float %68, float 0,000000e+00
>  %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %73 = extractelement <4 x float> %72, i32 0
>  %74 = fdiv float 0x3FF0000000000000, %73
>  %75 = fmul float %71, %74
>  %76 = call float @llvm.pow.f32(float %75, float 0x4010000000000000)
>  %77 = fdiv float 0x3FF0000000000000, %76
>  %78 = fmul float 0x3FECCCCCC0000000, %77
>  %79 = fsub float -0,000000e+00, %78
>  %80 = fadd float 0x3FF0000000000000, %79
>  %81 = fmul float %45, %80
>  %82 = load <4 x float> addrspace(8)* null
>  %83 = extractelement <4 x float> %82, i32 0
>  %84 = fsub float -0,000000e+00, %83
>  %85 = load <4 x float> addrspace(8)* null
>  %86 = extractelement <4 x float> %85, i32 1
>  %87 = fsub float -0,000000e+00, %86
>  %88 = load <4 x float> addrspace(8)* null
>  %89 = extractelement <4 x float> %88, i32 2
>  %90 = fsub float -0,000000e+00, %89
>  %91 = fmul float %87, %87
>  %92 = fsub float -0,000000e+00, %91
>  %93 = fadd float 0x3FF0000000000000, %92
>  %94 = fmul float %93, 0x3FE2024E20000000
>  %95 = fsub float -0,000000e+00, %94
>  %96 = fadd float 0x3FF0000000000000, %95
>  %97 = fcmp olt float %96, 0,000000e+00
>  %98 = sext i1 %97 to i32
>  %99 = bitcast i32 %98 to float
>  %100 = bitcast float %99 to i32
>  %101 = icmp ne i32 %100, 0
>  br i1 %101, label %ENDIF31, label %ELSE33
>
>IF29:                                             ; preds = %ELSE
>  %102 = fmul float %1, 0x3FE0000000000000
>  %103 = fadd float %102, 0x3FF0000000000000
>  %104 = fmul float %0, 0x3FE0000000000000
>  %105 = fadd float %104, 0x3FE0000000000000
>  %106 = insertelement <4 x float> undef, float %103, i32 0
>  %107 = insertelement <4 x float> %106, float %105, i32 1
>  %108 = insertelement <4 x float> %107, float 0,000000e+00, i32 2
>  %109 = insertelement <4 x float> %108, float 0,000000e+00, i32 3
>  %110 = extractelement <4 x float> %109, i32 0
>  %111 = extractelement <4 x float> %109, i32 1
>  %112 = insertelement <4 x float> undef, float %110, i32 0
>  %113 = insertelement <4 x float> %112, float %111, i32 1
>  %114 = insertelement <4 x float> %113, float undef, i32 2
>  %115 = insertelement <4 x float> %114, float undef, i32 3
>  %116 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %115, i32 16, i32 0, i32 2)
>  %117 = extractelement <4 x float> %116, i32 0
>  %118 = extractelement <4 x float> %116, i32 1
>  %119 = extractelement <4 x float> %116, i32 2
>  %120 = fsub float -0,000000e+00, %2
>  br label %ENDIF
>
>ELSE30:                                           ; preds = %ELSE
>  %121 = fmul float %0, 0x3FE0000000000000
>  %122 = fadd float %121, 0x3FE0000000000000
>  %123 = fmul float %2, 0x3FE0000000000000
>  %124 = fadd float %123, 0x3FE0000000000000
>  %125 = insertelement <4 x float> undef, float %122, i32 0
>  %126 = insertelement <4 x float> %125, float %124, i32 1
>  %127 = insertelement <4 x float> %126, float 0,000000e+00, i32 2
>  %128 = insertelement <4 x float> %127, float 0,000000e+00, i32 3
>  %129 = extractelement <4 x float> %128, i32 0
>  %130 = extractelement <4 x float> %128, i32 1
>  %131 = insertelement <4 x float> undef, float %129, i32 0
>  %132 = insertelement <4 x float> %131, float %130, i32 1
>  %133 = insertelement <4 x float> %132, float undef, i32 2
>  %134 = insertelement <4 x float> %133, float undef, i32 3
>  %135 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %134, i32 16, i32 0, i32 2)
>  %136 = extractelement <4 x float> %135, i32 0
>  %137 = extractelement <4 x float> %135, i32 1
>  %138 = extractelement <4 x float> %135, i32 2
>  br label %ENDIF
>
>ELSE33:                                           ; preds = %ENDIF
>  %139 = call float @llvm.AMDGPU.rsq(float %96)
>  %140 = fmul float %139, %96
>  %141 = fsub float -0,000000e+00, %96
>  %142 = fcmp ult float %141, 0,000000e+00
>  %143 = select i1 %142, float %140, float 0,000000e+00
>  %144 = fmul float 0x3FE8018960000000, %87
>  %145 = fadd float %144, %143
>  %146 = fmul float %145, 0,000000e+00
>  %147 = fmul float %145, 0x3FF0000000000000
>  %148 = fmul float %145, 0,000000e+00
>  %149 = fsub float -0,000000e+00, %146
>  %150 = fmul float 0x3FE8018960000000, %84
>  %151 = fadd float %150, %149
>  %152 = fsub float -0,000000e+00, %147
>  %153 = fmul float 0x3FE8018960000000, %87
>  %154 = fadd float %153, %152
>  %155 = fsub float -0,000000e+00, %148
>  %156 = fmul float 0x3FE8018960000000, %90
>  %157 = fadd float %156, %155
>  br label %ENDIF31
>
>ENDIF31:                                          ; preds = %ENDIF, %ELSE33
>  %temp18.0 = phi float [ %148, %ELSE33 ], [ 0,000000e+00, %ENDIF ]
>  %temp20.0 = phi float [ %151, %ELSE33 ], [ 0,000000e+00, %ENDIF ]
>  %temp21.0 = phi float [ %154, %ELSE33 ], [ 0,000000e+00, %ENDIF ]
>  %temp22.0 = phi float [ %157, %ELSE33 ], [ 0,000000e+00, %ENDIF ]
>  %158 = fsub float -0,000000e+00, %temp20.0
>  %159 = fsub float -0,000000e+00, %temp21.0
>  %160 = fsub float -0,000000e+00, %temp22.0
>  %161 = insertelement <4 x float> undef, float %158, i32 0
>  %162 = insertelement <4 x float> %161, float %159, i32 1
>  %163 = insertelement <4 x float> %162, float %160, i32 2
>  %164 = insertelement <4 x float> %163, float 0,000000e+00, i32 3
>  %165 = insertelement <4 x float> undef, float %temp8.0, i32 0
>  %166 = insertelement <4 x float> %165, float %temp9.0, i32 1
>  %167 = insertelement <4 x float> %166, float %temp10.0, i32 2
>  %168 = insertelement <4 x float> %167, float 0,000000e+00, i32 3
>  %169 = call float @llvm.AMDGPU.dp4(<4 x float> %164, <4 x float> %168)
>  %170 = fcmp uge float 0,000000e+00, %169
>  %171 = select i1 %170, float 0,000000e+00, float %169
>  %172 = fmul float %0, 0x3FE0000000000000
>  %173 = fadd float %172, 0x3FE0000000000000
>  %174 = fmul float %2, 0x3FE0000000000000
>  %175 = fadd float %174, 0x3FE0000000000000
>  %176 = insertelement <4 x float> undef, float %173, i32 0
>  %177 = insertelement <4 x float> %176, float %175, i32 1
>  %178 = insertelement <4 x float> %177, float %temp18.0, i32 2
>  %179 = insertelement <4 x float> %178, float 0,000000e+00, i32 3
>  %180 = extractelement <4 x float> %179, i32 0
>  %181 = extractelement <4 x float> %179, i32 1
>  %182 = insertelement <4 x float> undef, float %180, i32 0
>  %183 = insertelement <4 x float> %182, float %181, i32 1
>  %184 = insertelement <4 x float> %183, float undef, i32 2
>  %185 = insertelement <4 x float> %184, float undef, i32 3
>  %186 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %185, i32 18, i32 2, i32 2)
>  %187 = extractelement <4 x float> %186, i32 0
>  %188 = fcmp olt float %1, %187
>  %189 = sext i1 %188 to i32
>  %190 = bitcast i32 %189 to float
>  %191 = bitcast float %190 to i32
>  %192 = icmp ne i32 %191, 0
>  br i1 %192, label %IF35, label %ELSE36
>
>IF35:                                             ; preds = %ENDIF31
>  %193 = fmul float %1, %158
>  %194 = fmul float %1, %160
>  %195 = fdiv float 0x3FF0000000000000, %159
>  %196 = fmul float %193, %195
>  %197 = fmul float %194, %195
>  %198 = fsub float -0,000000e+00, %196
>  %199 = fadd float %0, %198
>  %200 = fsub float -0,000000e+00, %197
>  %201 = fadd float %2, %200
>  %202 = fmul float 0x3FD8000000000000, %199
>  %203 = fadd float %202, 0x3FE0000000000000
>  %204 = fmul float 0x3FD8000000000000, %201
>  %205 = fadd float %204, 0x3FE0000000000000
>  %206 = insertelement <4 x float> undef, float %203, i32 0
>  %207 = insertelement <4 x float> %206, float %205, i32 1
>  %208 = insertelement <4 x float> %207, float %temp18.0, i32 2
>  %209 = insertelement <4 x float> %208, float 0,000000e+00, i32 3
>  %210 = extractelement <4 x float> %209, i32 0
>  %211 = extractelement <4 x float> %209, i32 1
>  %212 = insertelement <4 x float> undef, float %210, i32 0
>  %213 = insertelement <4 x float> %212, float %211, i32 1
>  %214 = insertelement <4 x float> %213, float undef, i32 2
>  %215 = insertelement <4 x float> %214, float undef, i32 3
>  %216 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %215, i32 17, i32 1, i32 2)
>  %217 = extractelement <4 x float> %216, i32 0
>  %218 = extractelement <4 x float> %216, i32 1
>  %219 = fmul float %171, %217
>  %220 = fmul float %219, 0x4000000000000000
>  %221 = fmul float %220, %218
>  br label %ENDIF34
>
>ELSE36:                                           ; preds = %ENDIF31
>  %222 = fsub float -0,000000e+00, %0
>  %223 = fadd float 0xBFF0000000000000, %222
>  %224 = fsub float -0,000000e+00, %1
>  %225 = fadd float 0xBFF0000000000000, %224
>  %226 = fsub float -0,000000e+00, %2
>  %227 = fadd float 0xBFF0000000000000, %226
>  %228 = fdiv float 0x3FF0000000000000, %158
>  %229 = fdiv float 0x3FF0000000000000, %159
>  %230 = fdiv float 0x3FF0000000000000, %160
>  %231 = fmul float %223, %228
>  %232 = fmul float %225, %229
>  %233 = fmul float %227, %230
>  %234 = fsub float -0,000000e+00, %0
>  %235 = fadd float 0x3FF0000000000000, %234
>  %236 = fsub float -0,000000e+00, %1
>  %237 = fadd float 0x4000000000000000, %236
>  %238 = fsub float -0,000000e+00, %2
>  %239 = fadd float 0x3FF0000000000000, %238
>  %240 = fdiv float 0x3FF0000000000000, %158
>  %241 = fdiv float 0x3FF0000000000000, %159
>  %242 = fdiv float 0x3FF0000000000000, %160
>  %243 = fmul float %235, %240
>  %244 = fmul float %237, %241
>  %245 = fmul float %239, %242
>  %246 = fcmp uge float %231, %243
>  %247 = select i1 %246, float %243, float %231
>  %248 = fcmp uge float %232, %244
>  %249 = select i1 %248, float %244, float %232
>  %250 = fcmp uge float %233, %245
>  %251 = select i1 %250, float %245, float %233
>  %252 = fcmp uge float %231, %243
>  %253 = select i1 %252, float %231, float %243
>  %254 = fcmp uge float %232, %244
>  %255 = select i1 %254, float %232, float %244
>  %256 = fcmp uge float %233, %245
>  %257 = select i1 %256, float %233, float %245
>  %258 = fcmp uge float %253, %255
>  %259 = select i1 %258, float %255, float %253
>  %260 = fcmp uge float %259, %257
>  %261 = select i1 %260, float %257, float %259
>  %262 = fmul float %159, %261
>  %263 = fadd float %262, %1
>  %264 = fadd float %263, 0xBFC5555560000000
>  %265 = fmul float 0xC072089FC0000000, %264
>  %266 = fcmp uge float %247, %249
>  %267 = select i1 %266, float %247, float %249
>  %268 = fcmp uge float %267, %251
>  %269 = select i1 %268, float %267, float %251
>  %270 = fsub float -0,000000e+00, %269
>  %271 = fadd float %261, %270
>  %272 = fmul float 0x4024000000000000, %271
>  %273 = fadd float %272, 0x3FF0000000000000
>  %274 = fdiv float 0x3FF0000000000000, %273
>  %275 = fmul float %265, %274
>  %276 = call float @llvm.AMDIL.exp.(float %275)
>  %277 = fadd float 0x3FF0000000000000, %276
>  %278 = fdiv float 0x3FF0000000000000, %277
>  %279 = fmul float %171, %278
>  %280 = fmul float %279, 0x3FE0000000000000
>  br label %ENDIF34
>
>ENDIF34:                                          ; preds = %ELSE36, %IF35
>  %.sink = phi float [ %221, %IF35 ], [ %280, %ELSE36 ]
>  %281 = fadd float %.sink, %81
>  %282 = fmul float %temp4.0, %281
>  %283 = fmul float %temp5.0, %281
>  %284 = fmul float %temp6.0, %281
>  %285 = fmul float %0, 0x3FE0000000000000
>  %286 = fadd float %285, 0x3FE0000000000000
>  %287 = fmul float %2, 0x3FE0000000000000
>  %288 = fadd float %287, 0x3FE0000000000000
>  %289 = insertelement <4 x float> undef, float %286, i32 0
>  %290 = insertelement <4 x float> %289, float %288, i32 1
>  %291 = insertelement <4 x float> %290, float %temp10.0, i32 2
>  %292 = insertelement <4 x float> %291, float 0,000000e+00, i32 3
>  %293 = extractelement <4 x float> %292, i32 0
>  %294 = extractelement <4 x float> %292, i32 1
>  %295 = insertelement <4 x float> undef, float %293, i32 0
>  %296 = insertelement <4 x float> %295, float %294, i32 1
>  %297 = insertelement <4 x float> %296, float undef, i32 2
>  %298 = insertelement <4 x float> %297, float undef, i32 3
>  %299 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %298, i32 18, i32 2, i32 2)
>  %300 = extractelement <4 x float> %299, i32 0
>  %301 = fcmp olt float %1, %300
>  %302 = sext i1 %301 to i32
>  %303 = bitcast i32 %302 to float
>  %304 = bitcast float %303 to i32
>  %305 = icmp ne i32 %304, 0
>  br i1 %305, label %IF38, label %ENDIF37
>
>IF38:                                             ; preds = %ENDIF34
>  %306 = fmul float %282, 0x3FDEB85200000000
>  %307 = fmul float %283, 0x3FF147AE20000000
>  %308 = fmul float %284, 0x3FF3333340000000
>  br label %ENDIF37
>
>ENDIF37:                                          ; preds = %ENDIF34, %IF38
>  %temp4.2 = phi float [ %306, %IF38 ], [ %282, %ENDIF34 ]
>  %temp5.2 = phi float [ %307, %IF38 ], [ %283, %ENDIF34 ]
>  %temp6.2 = phi float [ %308, %IF38 ], [ %284, %ENDIF34 ]
>  %309 = insertelement <4 x float> undef, float %temp4.2, i32 0
>  %310 = insertelement <4 x float> %309, float %temp5.2, i32 1
>  %311 = insertelement <4 x float> %310, float %temp6.2, i32 2
>  %312 = insertelement <4 x float> %311, float 0x3FF0000000000000, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %312, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #1
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>attributes #2 = { readonly }
>attributes #3 = { nounwind readonly }
>
>===== SHADER #49 =========================================== PS/RV730/R700 =====
>===== 390 dw ===== 9 gprs ===== 1 stack ========================================
>0000  00000024 a4080000 ALU_PUSH_BEFORE 3 @72
> 0072  800000fd 00200712     1      x: SETGE_DX10         R1.x,  [0x3f7fbe77 0,999].x, |R0.x|
> 0074  3f7fbe77 
> 0076  801f00fe 00002284     2 M    x: PRED_SETNE_INT     __.x,  PV.x, 0
>0002  00000008 85000000 JUMP @16
>0004  00000027 a4080000 ALU_PUSH_BEFORE 3 @78
> 0078  801fa800 00200691     3      x: SETGT_DX10         R1.x,  |R0.z|, [0x3f7fbe77 0,999].x
> 0080  3f7fbe77 
> 0082  801f00fe 00002104     4 M    x: PRED_SETE_INT      __.x,  PV.x, 0
>0006  00000005 85000000 JUMP @10
>0008  0000002a a0100000 ALU 5 @84
> 0084  000000f8 00400c90     5      x: MOV                R2.x,  0
> 0086  000000f9 20400c90            y: MOV                R2.y,  1.0
> 0088  800000f8 40400c90            z: MOV                R2.z,  0
> 0090  801f8800 202280fc     6      y: MULADD_IEEE        R1.y,  R0.z, 0.5, 0.5
> 0092  801f8000 002280fc     7      x: MULADD_IEEE        R1.x,  R0.x, 0.5, 0.5
>0010  00000008 86800001 ELSE @16 POP:1
>0012  0000002f a0100000 ALU 5 @94
> 0094  001f8000 202280fc     8      y: MULADD_IEEE        R1.y,  R0.x, 0.5, 0.5
> 0096  80001800 40400c90            z: MOV                R2.z,  -R0.z
> 0098  000000f8 00400c90     9      x: MOV                R2.x,  0
> 0100  800000f8 20400c90            y: MOV                R2.y,  0
> 0102  801f8400 002280f9    10      x: MULADD_IEEE        R1.x,  R0.y, 0.5, 1.0
>0014  00000008 87000001 POP @16 POP:1
>0016  0000000b 86800001 ELSE @22 POP:1
>0018  00000034 a0100000 ALU 5 @104
> 0104  00001000 00400c90    11      x: MOV                R2.x,  -R0.x
> 0106  801f8800 202280fc            y: MULADD_IEEE        R1.y,  R0.z, 0.5, 0.5
> 0108  000000f8 20400c90    12      y: MOV                R2.y,  0
> 0110  800000f8 40400c90            z: MOV                R2.z,  0
> 0112  801f8400 002280f9    13      x: MULADD_IEEE        R1.x,  R0.y, 0.5, 1.0
>0020  0000000b 87000001 POP @22 POP:1
>0022  0000001c 80800000 TEX 1 @56
> 0056  00011010 f00d1001 68800000 SAMPLE              R1.xyzw, R1.xyzw,   RID:16, SID:0 CT:NNNN
>0024  80000039 a1100000 ALU 69 @114 KC0[CB0:0-31]
> 0114  000000f8 00c00c90    14      x: MOV                R6.x,  0
> 0116  800000f8 20a00c90            y: MOV                R5.y,  0
> 0118  800000f8 20800c90    15      y: MOV                R4.y,  0
> 0120  001fa881 00601910    16      x: XOR_INT            R3.x,  KC0[1].z, [0x80000000 -0].x
> 0122  001fa081 20c01910            y: XOR_INT            R6.y,  KC0[1].x, [0x80000000 -0].x
> 0124  801fa481 40801910            z: XOR_INT            R4.z,  KC0[1].y, [0x80000000 -0].x
> 0126  80000000 
> 0128  80000082 00a03310    17      t: RECIP_IEEE         R5.x,  KC0[2].x
> 0130  00900480 20e00110    18      y: MUL_IEEE           R7.y,  KC0[0].y, KC0[0].y
> 0132  80006800 40600010            z: ADD                R3.z,  R0.z, R3.x
> 0134  0080c000 00600010    19      x: ADD                R3.x,  R0.x, R6.y
> 0136  801f34fe 20c00010            y: ADD                R6.y,  -PV.y, 1.0
> 0138  001fa4fe 008280f9    20      x: MULADD_IEEE        R4.x,  PV.y, [0xbf101271 -0,562781].x, 1.0
> 0140  81008400 20600010            y: ADD                R3.y,  R0.y, R4.z
> 0142  bf101271 
> 0144  000080f8 00e00690    21      x: SETGT_DX10         R7.x,  0, R4.x
> 0146  800000fd 60600c90            w: MOV                R3.w,  [0x00000000 0].x
> 0148  00000000 
> 0150  00006003 00802800    22      x: DOT4               __.x,  R3.x, R3.x
> 0152  00806403 20802800            y: DOT4               __.y,  R3.y, R3.y
> 0154  01006803 40802810            z: DOT4               R4.z,  R3.z, R3.z
> 0156  81806c03 60802800            w: DOT4               __.w,  R3.w, R3.w
> 0158  80000804 01003390    23      t: RECIPSQRT_CLAMPED  R8.x,  R4.z
> 0160  80000c03 60000c90    24      w: MOV                R0.w,  R3.w
> 0162  00000000 00802800    25      x: DOT4               __.x,  R0.x, R0.x
> 0164  00800400 20802800            y: DOT4               __.y,  R0.y, R0.y
> 0166  01000800 40802800            z: DOT4               __.z,  R0.z, R0.z
> 0168  81800c00 60802810            w: DOT4               R4.w,  R0.w, R0.w
> 0170  81008008 01000110    26      x: MUL_IEEE           R8.x,  R8.x, R4.z
> 0172  80000c04 20c03390    27      t: RECIPSQRT_CLAMPED  R6.y,  R4.w
> 0174  001f1804 01034008    28      x: CNDGE              R8.x,  -R4.z, 0, R8.x
> 0176  801f8406 20c00110            y: MUL_IEEE           R6.y,  R6.y, 0.5
> 0178  8000a008 00a00110    29      x: MUL_IEEE           R5.x,  R8.x, R5.x
> 0180  80000005 00a03190    30      t: LOG_IEEE           R5.x,  R5.x
> 0182  8000a0fd 00a00090    31      x: MUL                R5.x,  [0x40800000 4].x, R5.x
> 0184  40800000 
> 0186  80000005 00a03090    32      t: EXP_IEEE           R5.x,  R5.x
> 0188  80000005 00a03310    33      t: RECIP_IEEE         R5.x,  R5.x
> 0190  801fa005 00a280f9    34      x: MULADD_IEEE        R5.x,  R5.x, [0xbf666666 -0,9].x, 1.0
> 0192  bf666666 
> 0194  801f0007 00002288    35  P   x: PRED_SETNE_INT     __.x,  R7.x, 0
> 0196  40000480 00c00c90    36    0 x: MOV                R6.x,  KC0[0].y
> 0198  401fa880 20801910          0 y: XOR_INT            R4.y,  KC0[0].z, [0x80000000 -0].x
> 0200  c01fa080 40801910          0 z: XOR_INT            R4.z,  KC0[0].x, [0x80000000 -0].x
> 0202  80000000 
> 0204  c0000004 60803390    37    0 t: RECIPSQRT_CLAMPED  R4.w,  R4.x
> 0206  40001006 00c00c90    38    0 x: MOV                R6.x,  -R6.x
> 0208  c0008c04 20a00110          0 y: MUL_IEEE           R5.y,  R4.w, R4.x
> 0210  c01f1004 00834405    39    0 x: CNDGE              R4.x,  -R4.x, 0, R5.y
> 0212  c01fa006 00e28004    40    0 x: MULADD_IEEE        R7.x,  R6.x, [0x3f400c4b 0,750188].x, R4.x
> 0214  3f400c4b 
> 0216  401f0007 00800110    41    0 x: MUL_IEEE           R4.x,  R7.x, 0
> 0218  c01fa006 20aa9007          0 y: MULADD_IEEE        R5.y,  R6.x, [0x3f400c4b 0,750188].x, -R7.x  VEC_120
> 0220  3f400c4b 
> 0222  401fa804 00c28004    42    0 x: MULADD_IEEE        R6.x,  R4.z, [0x3f400c4b 0,750188].x, R4.x
> 0224  c01fa404 20828004          0 y: MULADD_IEEE        R4.y,  R4.y, [0x3f400c4b 0,750188].x, R4.x
> 0226  3f400c4b 
> 0228  0000a406 00a00110    43      x: MUL_IEEE           R5.x,  R6.y, R5.x
> 0230  80001404 40680c90            z: MOV                R3.z,  -R4.y                  VEC_120
> 0232  001f8000 008280fc    44      x: MULADD_IEEE        R4.x,  R0.x, 0.5, 0.5
> 0234  80001405 20600c90            y: MOV                R3.y,  -R5.y
> 0236  00001006 00600c90    45      x: MOV                R3.x,  -R6.x
> 0238  801f8800 208280fc            y: MULADD_IEEE        R4.y,  R0.z, 0.5, 0.5
> 0240  80000c03 60400c90    46      w: MOV                R2.w,  R3.w
> 0242  00004003 00402810    47      x: DOT4               R2.x,  R3.x, R2.x
> 0244  00804403 20402800            y: DOT4               __.y,  R3.y, R2.y
> 0246  01004803 40402800            z: DOT4               __.z,  R3.z, R2.z
> 0248  81804c03 60402800            w: DOT4               __.w,  R3.w, R2.w
> 0250  801fc0fe 004320f8    48      x: CNDGT              R2.x,  PV.x, PV.x, 0
>0026  0000001e 80800000 TEX 1 @60
> 0060  00041210 f00d1006 68810000 SAMPLE              R6.xyzw, R4.xyzw,   RID:18, SID:2 CT:NNNN
>0028  0000007e a4040000 ALU_PUSH_BEFORE 2 @252
> 0252  8000c400 00c00710    49      x: SETGE_DX10         R6.x,  R0.y, R6.x
> 0254  801f00fe 00002284    50 M    x: PRED_SETNE_INT     __.x,  PV.x, 0
>0030  00000011 85000000 JUMP @34
>0032  00000080 a0a00000 ALU 41 @256
> 0256  001fb000 00e00010    51      x: ADD                R7.x,  -R0.x, [0xbf800000 -1].x
> 0258  001fb400 20400010            y: ADD                R2.y,  -R0.y, [0xbf800000 -1].x
> 0260  009fb400 40400010            z: ADD                R2.z,  -R0.y, [0x40000000 2].y
> 0262  801f3000 60a00010            w: ADD                R5.w,  -R0.x, 1.0
> 0264  bf800000 
> 0265  40000000 
> 0266  801fb800 00c00010    52      x: ADD                R6.x,  -R0.z, [0xbf800000 -1].x
> 0268  bf800000 
> 0270  80000003 20a03310    53      t: RECIP_IEEE         R5.y,  R3.x
> 0272  80000403 40c03310    54      t: RECIP_IEEE         R6.z,  R3.y
> 0274  801f3800 60400010    55      w: ADD                R2.w,  -R0.z, 1.0
> 0276  0080a007 01000110    56      x: MUL_IEEE           R8.x,  R7.x, R5.y
> 0278  0080ac05 20a00110            y: MUL_IEEE           R5.y,  R5.w, R5.y
> 0280  0100c402 40a00110            z: MUL_IEEE           R5.z,  R2.y, R6.z
> 0282  8100c802 60a00110            w: MUL_IEEE           R5.w,  R2.z, R6.z
> 0284  009fc0fe 00e00190    57      x: MAX                R7.x,  PV.x, PV.y
> 0286  009fc0fe 20400210            y: MIN                R2.y,  PV.x, PV.y
> 0288  019fc8fe 40400190            z: MAX                R2.z,  PV.z, PV.w
> 0290  819fc8fe 60a00210            w: MIN                R5.w,  PV.z, PV.w
> 0292  011fc0fe 00e00210    58      x: MIN                R7.x,  PV.x, PV.z
> 0294  819fc4fe 20400190            y: MAX                R2.y,  PV.y, PV.w
> 0296  80000803 40403310    59      t: RECIP_IEEE         R2.z,  R3.z
> 0298  01004006 00c00110    60      x: MUL_IEEE           R6.x,  R6.x, R2.z
> 0300  81004c02 20a00110            y: MUL_IEEE           R5.y,  R2.w, R2.z
> 0302  009fc0fe 01000190    61      x: MAX                R8.x,  PV.x, PV.y
> 0304  809fc0fe 20a00210            y: MIN                R5.y,  PV.x, PV.y
> 0306  001fc007 00c00210    62      x: MIN                R6.x,  R7.x, PV.x
> 0308  809fc402 20400190            y: MAX                R2.y,  R2.y, PV.y
> 0310  001fc403 00628400    63      x: MULADD_IEEE        R3.x,  R3.y, PV.x, R0.y
> 0312  829fc0fe 20400010            y: ADD                R2.y,  PV.x, -PV.y
> 0314  001fa003 00600010    64      x: ADD                R3.x,  R3.x, [0xbe2aaaab -0,166667].x
> 0316  809fa4fe 204280f9            y: MULADD_IEEE        R2.y,  PV.y, [0x41200000 10].y, 1.0
> 0318  be2aaaab 
> 0319  41200000 
> 0320  801fa0fe 00600110    65      x: MUL_IEEE           R3.x,  PV.x, [0xc39044fe -288,539].x
> 0322  c39044fe 
> 0324  80000402 20403310    66      t: RECIP_IEEE         R2.y,  R2.y
> 0326  80804003 00600110    67      x: MUL_IEEE           R3.x,  R3.x, R2.y
> 0328  80000003 00603090    68      t: EXP_IEEE           R3.x,  R3.x
> 0330  801f2003 00600010    69      x: ADD                R3.x,  R3.x, 1.0
> 0332  80000003 00603310    70      t: RECIP_IEEE         R3.x,  R3.x
> 0334  80006002 00400110    71      x: MUL_IEEE           R2.x,  R2.x, R3.x
> 0336  801f80fe 00400110    72      x: MUL_IEEE           R2.x,  PV.x, 0.5
>0034  00000016 86800001 ELSE @44 POP:1
>0036  000000a9 a0280000 ALU 11 @338
> 0338  01006400 00c00110    73      x: MUL_IEEE           R6.x,  R0.y, R3.z
> 0340  80006400 20400110            y: MUL_IEEE           R2.y,  R0.y, R3.x
> 0342  80000403 40403310    74      t: RECIP_IEEE         R2.z,  R3.y
> 0344  01004402 00600110    75      x: MUL_IEEE           R3.x,  R2.y, R2.z
> 0346  81004006 20400110            y: MUL_IEEE           R2.y,  R6.x, R2.z
> 0348  021fc000 00600010    76      x: ADD                R3.x,  R0.x, -PV.x
> 0350  829fc800 20400010            y: ADD                R2.y,  R0.z, -PV.y
> 0352  801fa4fe 20c280fc    77      y: MULADD_IEEE        R6.y,  PV.y, [0x3ec00000 0,375].x, 0.5
> 0354  3ec00000 
> 0356  801fa003 00c280fc    78      x: MULADD_IEEE        R6.x,  R3.x, [0x3ec00000 0,375].x, 0.5
> 0358  3ec00000 
>0038  00000020 80800000 TEX 1 @64
> 0064  00061110 f00d1003 68808000 SAMPLE              R3.xyzw, R6.xyzw,   RID:17, SID:1 CT:NNNN
>0040  000000b4 a0080000 ALU 3 @360
> 0360  80006002 00c00110    79      x: MUL_IEEE           R6.x,  R2.x, R3.x
> 0362  80006002 004280fe    80      x: MULADD_IEEE        R2.x,  R2.x, R3.x, PV.x
> 0364  80806002 00400110    81      x: MUL_IEEE           R2.x,  R2.x, R3.y
>0042  00000016 87000001 POP @44 POP:1
>0044  000000b7 a00c0000 ALU 4 @366
> 0366  8000a002 00600010    82      x: ADD                R3.x,  R2.x, R5.x
> 0368  801fc401 20400110    83      y: MUL_IEEE           R2.y,  R1.y, PV.x
> 0370  00006001 00400110    84      x: MUL_IEEE           R2.x,  R1.x, R3.x
> 0372  80006801 40400110            z: MUL_IEEE           R2.z,  R1.z, R3.x
>0046  00000022 80800000 TEX 1 @68
> 0068  00041210 f00d1001 68810000 SAMPLE              R1.xyzw, R4.xyzw,   RID:18, SID:2 CT:NNNN
>0048  000000bb a01c0000 ALU 8 @374
> 0374  80002400 00000710    85      x: SETGE_DX10         R0.x,  R0.y, R1.x
> 0376  801f00fe 00002288    86  P   x: PRED_SETNE_INT     __.x,  PV.x, 0
> 0378  c01fa802 40400110    87    0 z: MUL_IEEE           R2.z,  R2.z, [0x3f99999a 1,2].x
> 0380  3f99999a 
> 0382  c01fa002 00400110    88    0 x: MUL_IEEE           R2.x,  R2.x, [0x3ef5c290 0,48].x
> 0384  3ef5c290 
> 0386  c01fa402 20400110    89    0 y: MUL_IEEE           R2.y,  R2.y, [0x3f8a3d71 1,08].x
> 0388  3f8a3d71 
>0050  c0010000 94600a88 EXPORT_DONE        PIXEL 0     R2.xyz1  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #49 OPT ======================================= PS/RV730/R700 =====
>===== 338 dw ===== 6 gprs ===== 1 stack ========================================
>0000  4000000d a0640000 ALU 26 @26 KC0[CB0:0-15]
> 0026  801fa881 0f801910     1      x: XOR_INT            T0.x,  KC0[1].z, [0x80000000 -0].x
> 0028  80000000 
> 0030  001fa481 4f801910     2      z: XOR_INT            T0.z,  KC0[1].y, [0x80000000 -0].x
> 0032  80901480 6f8280f9            w: MULADD_IEEE        T0.w,  -KC0[0].y, KC0[0].y, 1.0
> 0034  80000000 
> 0036  010f8400 0f800010     3      x: ADD                T0.x,  R0.y, T0.z
> 0038  001fac7c 206280f9            y: MULADD_IEEE        R3.y,  T0.w, [0xbf101271 -0,562781].x, 1.0
> 0040  009fa081 6f801910            w: XOR_INT            T0.w,  KC0[1].x, [0x80000000 -0].y
> 0042  800f8800 2f800010            t: ADD                T0.y,  R0.z, T0.x
> 0044  bf101271 
> 0045  80000000 
> 0046  00000000 00a02810     4      x: DOT4               R5.x,  R0.x, R0.x
> 0048  00800400 20002800            y: DOT4               __.y,  R0.y, R0.y
> 0050  01000800 40002800            z: DOT4               __.z,  R0.z, R0.z
> 0052  001f00f8 60002800            w: DOT4               __.w,  0, 0
> 0054  818f8000 6f800010            t: ADD                T0.w,  R0.x, T0.w
> 0056  018f8c7c 00002800     5      x: DOT4               __.x,  T0.w, T0.w
> 0058  000f807c 20802810            y: DOT4               R4.y,  T0.x, T0.x
> 0060  008f847c 40002800            z: DOT4               __.z,  T0.y, T0.y
> 0062  801f00f8 60002800            w: DOT4               __.w,  0, 0
> 0064  001fa080 20401910     6      y: XOR_INT            R2.y,  KC0[0].x, [0x80000000 -0].x
> 0066  80000403 00603390            t: RECIPSQRT_CLAMPED  R3.x,  R3.y
> 0068  80000000 
> 0070  001f8000 002280fc     7      x: MULADD_IEEE        R1.x,  R0.x, 0.5, 0.5
> 0072  001f8800 202280fc            y: MULADD_IEEE        R1.y,  R0.z, 0.5, 0.5
> 0074  00804403 40234404            z: CNDGE              R1.z,  R3.y, R2.y, R4.y
> 0076  80006403 60234005            w: CNDGE              R1.w,  R3.y, R3.x, R5.x
>0002  00000028 80800000 TEX 1 @80
> 0080  00011210 f00d7002 68810000 SAMPLE              R2.x_zw, R1.xyzw,   RID:18, SID:2 CT:NNNN
>0004  4000002a a4880000 ALU_PUSH_BEFORE 35 @84 KC0[CB0:0-15]
> 0084  80806003 6f800110     8      w: MUL_IEEE           T0.w,  R3.x, R3.y
> 0086  00001480 0f800c90     9      x: MOV                T0.x,  -KC0[0].y
> 0088  801f1403 6f834c7c            w: CNDGE              T0.w,  -R3.y, 0, T0.w
> 0090  801fa07c 6fa28c7c    10      w: MULADD_IEEE        T1.w,  T0.x, [0x3f400c4b 0,750188].x, T0.w
> 0092  3f400c4b 
> 0094  001fa800 40800691    11      z: SETGT_DX10         R4.z,  |R0.z|, [0x3f7fbe77 0,999].x
> 0096  001f0c7d 6f800110            w: MUL_IEEE           T0.w,  T1.w, 0
> 0098  809fa880 4f801910            t: XOR_INT            T0.z,  KC0[0].z, [0x80000000 -0].y
> 0100  3f7fbe77 
> 0101  80000000 
> 0102  001fa402 0f828c7c    12      x: MULADD_IEEE        T0.x,  R2.y, [0x3f400c4b 0,750188].x, T0.w
> 0104  001fa87c 4f828c7c            z: MULADD_IEEE        T0.z,  T0.z, [0x3f400c4b 0,750188].x, T0.w
> 0106  001fa07c 6f869c7d            w: MULADD_IEEE        T0.w,  T0.x, [0x3f400c4b 0,750188].x, -T1.w  VEC_021
> 0108  80001800 6fa00c90            t: MOV                T1.w,  -R0.z
> 0110  3f400c4b 
> 0112  001fa000 00800691    13      x: SETGT_DX10         R4.x,  |R0.x|, [0x3f7fbe77 0,999].x
> 0114  001f0804 2f838c7d            y: CNDE_INT           T0.y,  R4.z, 0, T1.w
> 0116  000f8403 4fa340f8            z: CNDGE              T1.z,  R3.y, T0.x, 0
> 0118  801f2804 6fc380f8            w: CNDE_INT           T2.w,  R4.z, 1.0, 0
> 0120  3f7fbe77 
> 0122  00001000 2f880c90    14      y: MOV                T0.y,  -R0.x                  VEC_120
> 0124  010f8403 4f8340f8            z: CNDGE              T0.z,  R3.y, T0.z, 0
> 0126  008f8004 6f8380f8            w: CNDE_INT           T0.w,  R4.x, T0.y, 0
> 0128  818f8403 6fa340f8            t: CNDGE              T1.w,  R3.y, T0.w, 0
> 0130  00001c7d 00600c90    15      x: MOV                R3.x,  -T1.w
> 0132  001f0004 2f83847c            y: CNDE_INT           T0.y,  R4.x, 0, T0.y
> 0134  0000187c 40680c90            z: MOV                R3.z,  -T0.z                  VEC_120
> 0136  0000187d 60000c90            w: MOV                R0.w,  -T1.z
> 0138  818fc004 2fa380f8            t: CNDE_INT           T1.y,  R4.x, T2.w, 0
> 0140  008f8c00 00002800    16      x: DOT4               __.x,  R0.w, T0.y
> 0142  008fa003 2f842810            y: DOT4               T0.y,  R3.x, T1.y             VEC_021
> 0144  018f8803 40002800            z: DOT4               __.z,  R3.z, T0.w
> 0146  801f00f8 60002800            w: DOT4               __.w,  0, 0
> 0148  00004400 00001104    17 M    x: PRED_SETGE         __.x,  R0.y, R2.x
> 0150  008f847c 206b20f8            y: CNDGT              R3.y,  T0.y, T0.y, 0          VEC_120
> 0152  80000003 00403310            t: RECIP_IEEE         R2.x,  R3.x
>0006  00000005 85000000 JUMP @10
>0008  0000004d a0a00000 ALU 41 @154
> 0154  001fb400 6f800010    18      w: ADD                T0.w,  -R0.y, [0x40000000 2].x
> 0156  80000c00 6fa03310            t: RECIP_IEEE         T1.w,  R0.w
> 0158  40000000 
> 0160  00004c7c 0fa00110    19      x: MUL_IEEE           T1.x,  T0.w, R2.x
> 0162  001fb000 2f800010            y: ADD                T0.y,  -R0.x, [0xbf800000 -1].x
> 0164  001fb400 4f800010            z: ADD                T0.z,  -R0.y, [0xbf800000 -1].x
> 0166  801f3000 0f800010            t: ADD                T0.x,  -R0.x, 1.0
> 0168  bf800000 
> 0170  018fa07c 0f800110    20      x: MUL_IEEE           T0.x,  T0.x, T1.w
> 0172  018fa47c 2f800110            y: MUL_IEEE           T0.y,  T0.y, T1.w
> 0174  001f3800 4fa00010            z: ADD                T1.z,  -R0.z, 1.0
> 0176  0000487c 6f880110            w: MUL_IEEE           T0.w,  T0.z, R2.x             VEC_120
> 0178  80000803 6fc03310            t: RECIP_IEEE         T2.w,  R3.z
> 0180  000f847c 4fc00190    21      z: MAX                T2.z,  T0.y, T0.x
> 0182  000fac7c 6fa40190            w: MAX                T1.w,  T0.w, T1.x             VEC_021
> 0184  801fb800 4f800010            t: ADD                T0.z,  -R0.z, [0xbf800000 -1].x
> 0186  bf800000 
> 0188  000f847c 0f800210    22      x: MIN                T0.x,  T0.y, T0.x
> 0190  018fc87c 4f800110            z: MUL_IEEE           T0.z,  T0.z, T2.w
> 0192  000fac7c 6f840210            w: MIN                T0.w,  T0.w, T1.x             VEC_021
> 0194  818fc87d 4fa00110            t: MUL_IEEE           T1.z,  T1.z, T2.w
> 0196  018f807c 0f800190    23      x: MAX                T0.x,  T0.x, T0.w
> 0198  010fa87c 2f800190            y: MAX                T0.y,  T0.z, T1.z
> 0200  010fa87c 4f800210            z: MIN                T0.z,  T0.z, T1.z
> 0202  818fa87e 0fac0210            t: MIN                T1.x,  T2.z, T1.w             SCL_221
> 0204  010f807c 0f800190    24      x: MAX                T0.x,  T0.x, T0.z
> 0206  808f807d 6f880210            w: MIN                T0.w,  T1.x, T0.y             VEC_120
> 0208  020f8c7c 0f800010    25      x: ADD                T0.x,  T0.w, -T0.x
> 0210  818f8003 4f828400            z: MULADD_IEEE        T0.z,  R3.x, T0.w, R0.y
> 0212  009fa07c 0f8280f9    26      x: MULADD_IEEE        T0.x,  T0.x, [0x41200000 10].y, 1.0
> 0214  801fa87c 4f800010            z: ADD                T0.z,  T0.z, [0xbe2aaaab -0,166667].x
> 0216  be2aaaab 
> 0217  41200000 
> 0218  001fa87c 4f800110    27      z: MUL_IEEE           T0.z,  T0.z, [0xc39044fe -288,539].x
> 0220  8000007c 0f803310            t: RECIP_IEEE         T0.x,  T0.x
> 0222  c39044fe 
> 0224  800f887c 0f800110    28      x: MUL_IEEE           T0.x,  T0.z, T0.x
> 0226  8000007c 0f803090    29      t: EXP_IEEE           T0.x,  T0.x
> 0228  801f207c 0f800010    30      x: ADD                T0.x,  T0.x, 1.0
> 0230  8000007c 0f803310    31      t: RECIP_IEEE         T0.x,  T0.x
> 0232  800f8403 0f800110    32      x: MUL_IEEE           T0.x,  R3.y, T0.x
> 0234  801f807c 00400110    33      x: MUL_IEEE           R2.x,  T0.x, 0.5
>0010  00000009 86800001 ELSE @18 POP:1
>0012  00000076 a0180000 ALU 7 @236
> 0236  01006400 2f800110    34      y: MUL_IEEE           T0.y,  R0.y, R3.z
> 0238  81800400 6f800110            w: MUL_IEEE           T0.w,  R0.y, R0.w
> 0240  02004c7c 0f828000    35      x: MULADD_IEEE        T0.x,  T0.w, -R2.x, R0.x
> 0242  8200447c 4f828800            z: MULADD_IEEE        T0.z,  T0.y, -R2.x, R0.z
> 0244  001fa07c 004280fc    36      x: MULADD_IEEE        R2.x,  T0.x, [0x3ec00000 0,375].x, 0.5
> 0246  801fa87c 204280fc            y: MULADD_IEEE        R2.y,  T0.z, [0x3ec00000 0,375].x, 0.5
> 0248  3ec00000 
>0014  0000007e 80800000 TEX 1 @252
> 0252  00021110 f01cf000 68808000 SAMPLE              R0.x_y_, R2.xyzw,   RID:17, SID:1 CT:NNNN
>0016  00000080 a80c0000 ALU_POP_AFTER 4 @256
> 0256  801fa000 0f800090    37      x: MUL                T0.x,  R0.x, [0x40000000 2].x
> 0258  40000000 
> 0260  800f8403 0f800110    38      x: MUL_IEEE           T0.x,  R3.y, T0.x
> 0262  8100007c 00400110    39      x: MUL_IEEE           R2.x,  T0.x, R0.z
>0018  00000084 a0100000 ALU 5 @264
> 0264  801f8400 0f8280f9    40      x: MULADD_IEEE        T0.x,  R0.y, 0.5, 1.0
> 0266  00802804 4f878001    41      z: CNDE_INT           T0.z,  R4.z, R1.y, R1.x       VEC_021
> 0268  80002804 6f83807c            w: CNDE_INT           T0.w,  R4.z, R1.x, T0.x
> 0270  018f8004 0003807c    42      x: CNDE_INT           R0.x,  R4.x, T0.w, T0.x
> 0272  810f8004 40038401            z: CNDE_INT           R0.z,  R4.x, T0.z, R1.y
>0020  0000008a 80800400 TEX 2 @276
> 0276  00001010 f008f000 fd000000 SAMPLE              R0.x_yz, R0.xz__,   RID:16, SID:0 CT:NNNN
> 0280  00011210 f01ff001 68810000 SAMPLE              R1.x___, R1.xyzw,   RID:18, SID:2 CT:NNNN
>0022  4000008e a0680000 ALU 27 @284 KC0[CB0:0-15]
> 0284  80000404 2f803390    43      t: RECIPSQRT_CLAMPED  T0.y,  R4.y
> 0286  8080847c 2f800110    44      y: MUL_IEEE           T0.y,  T0.y, R4.y
> 0288  001f1404 2f83447c    45      y: CNDGE              T0.y,  -R4.y, 0, T0.y
> 0290  80000082 4f803310            t: RECIP_IEEE         T0.z,  KC0[2].x
> 0292  810f847c 2f800110    46      y: MUL_IEEE           T0.y,  T0.y, T0.z
> 0294  8000047c 2f803190    47      t: LOG_IEEE           T0.y,  T0.y
> 0296  801fa47c 2f800090    48      y: MUL                T0.y,  T0.y, [0x40800000 4].x
> 0298  40800000 
> 0300  8000047c 2f803090    49      t: EXP_IEEE           T0.y,  T0.y
> 0302  80000005 4f803390    50      t: RECIPSQRT_CLAMPED  T0.z,  R5.x
> 0304  8000047c 2f803310    51      t: RECIP_IEEE         T0.y,  T0.y
> 0306  001fa47c 2f8280f9    52      y: MULADD_IEEE        T0.y,  T0.y, [0xbf666666 -0,9].x, 1.0
> 0308  801f887c 4f800110            z: MUL_IEEE           T0.z,  T0.z, 0.5
> 0310  bf666666 
> 0312  808f887c 2f828002    53      y: MULADD_IEEE        T0.y,  T0.z, T0.y, R2.x
> 0314  008f8000 0fa00110    54      x: MUL_IEEE           T1.x,  R0.x, T0.y
> 0316  008f8800 4f800110            z: MUL_IEEE           T0.z,  R0.z, T0.y
> 0318  808f8c00 6fa00110            w: MUL_IEEE           T1.w,  R0.w, T0.y
> 0320  00800001 0f880690    55      x: SETGT_DX10         T0.x,  R1.x, R0.y             VEC_120
> 0322  009fa87c 2f800110            y: MUL_IEEE           T0.y,  T0.z, [0x3f8a3d71 1,08].y
> 0324  001fa07d 6f800110            w: MUL_IEEE           T0.w,  T1.x, [0x3ef5c290 0,48].x
> 0326  811fac7d 2fa00110            t: MUL_IEEE           T1.y,  T1.w, [0x3f99999a 1,2].z
> 0328  3ef5c290 
> 0329  3f8a3d71 
> 0330  3f99999a 
> 0332  000fa07c 00038c7c    56      x: CNDE_INT           R0.x,  T0.x, T1.x, T0.w
> 0334  010f807c 2003847c            y: CNDE_INT           R0.y,  T0.x, T0.z, T0.y
> 0336  818fa07c 4013847d            z: CNDE_INT           R0.z,  T0.x, T1.w, T1.y       VEC_201
>0024  c0000000 94600a88 EXPORT_DONE        PIXEL 0     R0.xyz1  VPM  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..3]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    1,0000,     0,5833,    -1,0000,     0,0000}
>  0: MOV TEMP[0].xz, IN[0].xxzx
>  1: ADD TEMP[1].x, IMM[0].xxxx, -IN[0].yyyy
>  2: MAD TEMP[1].x, TEMP[1].xxxx, IMM[0].yyyy, IMM[0].zzzz
>  3: MOV TEMP[0].y, TEMP[1].xxxx
>  4: MUL TEMP[2], CONST[0], IN[0].xxxx
>  5: MAD TEMP[1], CONST[1], TEMP[1].xxxx, TEMP[2]
>  6: MAD TEMP[1], CONST[2], IN[0].zzzz, TEMP[1]
>  7: ADD TEMP[1], TEMP[1], CONST[3]
>  8: MOV TEMP[0].xyz, TEMP[0].xyzx
>  9: MOV OUT[1], TEMP[0]
> 10: MOV OUT[0], TEMP[1]
> 11: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 4)
>  %1 = call float @llvm.R600.load.input(i32 5)
>  %2 = call float @llvm.R600.load.input(i32 6)
>  %3 = call float @llvm.R600.load.input(i32 7)
>  %4 = fsub float -0,000000e+00, %1
>  %5 = fadd float 0x3FF0000000000000, %4
>  %6 = fmul float %5, 0x3FE2AAAAA0000000
>  %7 = fadd float %6, 0xBFF0000000000000
>  %8 = load <4 x float> addrspace(8)* null
>  %9 = extractelement <4 x float> %8, i32 0
>  %10 = fmul float %9, %0
>  %11 = load <4 x float> addrspace(8)* null
>  %12 = extractelement <4 x float> %11, i32 1
>  %13 = fmul float %12, %0
>  %14 = load <4 x float> addrspace(8)* null
>  %15 = extractelement <4 x float> %14, i32 2
>  %16 = fmul float %15, %0
>  %17 = load <4 x float> addrspace(8)* null
>  %18 = extractelement <4 x float> %17, i32 3
>  %19 = fmul float %18, %0
>  %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %21 = extractelement <4 x float> %20, i32 0
>  %22 = fmul float %21, %7
>  %23 = fadd float %22, %10
>  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %25 = extractelement <4 x float> %24, i32 1
>  %26 = fmul float %25, %7
>  %27 = fadd float %26, %13
>  %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %29 = extractelement <4 x float> %28, i32 2
>  %30 = fmul float %29, %7
>  %31 = fadd float %30, %16
>  %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %33 = extractelement <4 x float> %32, i32 3
>  %34 = fmul float %33, %7
>  %35 = fadd float %34, %19
>  %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = fmul float %37, %2
>  %39 = fadd float %38, %23
>  %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %41 = extractelement <4 x float> %40, i32 1
>  %42 = fmul float %41, %2
>  %43 = fadd float %42, %27
>  %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %45 = extractelement <4 x float> %44, i32 2
>  %46 = fmul float %45, %2
>  %47 = fadd float %46, %31
>  %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %49 = extractelement <4 x float> %48, i32 3
>  %50 = fmul float %49, %2
>  %51 = fadd float %50, %35
>  %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = fadd float %39, %53
>  %55 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %56 = extractelement <4 x float> %55, i32 1
>  %57 = fadd float %43, %56
>  %58 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %59 = extractelement <4 x float> %58, i32 2
>  %60 = fadd float %47, %59
>  %61 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %62 = extractelement <4 x float> %61, i32 3
>  %63 = fadd float %51, %62
>  %64 = insertelement <4 x float> undef, float %54, i32 0
>  %65 = insertelement <4 x float> %64, float %57, i32 1
>  %66 = insertelement <4 x float> %65, float %60, i32 2
>  %67 = insertelement <4 x float> %66, float %63, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %67, i32 60, i32 1)
>  %68 = insertelement <4 x float> undef, float %0, i32 0
>  %69 = insertelement <4 x float> %68, float %7, i32 1
>  %70 = insertelement <4 x float> %69, float %2, i32 2
>  %71 = insertelement <4 x float> %70, float 0,000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %71, i32 0, i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #50 =========================================== VS/RV730/R700 =====
>===== 56 dw ===== 3 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  80000006 a0540000 ALU 22 @12 KC0[CB0:0-31]
> 0012  80000401 00000c90     1      x: MOV                R0.x,  R1.y
> 0014  001f30fe 00000010     2      x: ADD                R0.x,  -PV.x, 1.0
> 0016  800000fd 20000c90            y: MOV                R0.y,  [0x3f155555 0,583333].x
> 0018  3f155555 
> 0020  809fc0fe 202280fd     3      y: MULADD_IEEE        R1.y,  PV.x, PV.y, [0xbf800000 -1].x
> 0022  bf800000 
> 0024  00002880 00000110     4      x: MUL_IEEE           R0.x,  KC0[0].z, R1.x
> 0026  00002c80 20000110            y: MUL_IEEE           R0.y,  KC0[0].w, R1.x
> 0028  00002080 40000110            z: MUL_IEEE           R0.z,  KC0[0].x, R1.x
> 0030  80002480 60000110            w: MUL_IEEE           R0.w,  KC0[0].y, R1.x
> 0032  00802881 000280fe     5      x: MULADD_IEEE        R0.x,  KC0[1].z, R1.y, PV.x
> 0034  00802c81 200284fe            y: MULADD_IEEE        R0.y,  KC0[1].w, R1.y, PV.y
> 0036  00802081 400288fe            z: MULADD_IEEE        R0.z,  KC0[1].x, R1.y, PV.z
> 0038  80802481 60028cfe            w: MULADD_IEEE        R0.w,  KC0[1].y, R1.y, PV.w
> 0040  01002882 00028000     6      x: MULADD_IEEE        R0.x,  KC0[2].z, R1.z, R0.x
> 0042  01002c82 20028400            y: MULADD_IEEE        R0.y,  KC0[2].w, R1.z, R0.y
> 0044  01002082 40028800            z: MULADD_IEEE        R0.z,  KC0[2].x, R1.z, R0.z
> 0046  81002482 60028c00            w: MULADD_IEEE        R0.w,  KC0[2].y, R1.z, R0.w
> 0048  00906c00 20400010     7      y: ADD                R2.y,  R0.w, KC0[3].y
> 0050  81906400 60400010            w: ADD                R2.w,  R0.y, KC0[3].w
> 0052  00106800 00400010     8      x: ADD                R2.x,  R0.z, KC0[3].x
> 0054  81106000 40400010            z: ADD                R2.z,  R0.x, KC0[3].z
>0004  c001203c 94400688 EXPORT_DONE        POS   60    R2.xyzw  VPM
>0006  c000c000 94600888 EXPORT_DONE        PARAM 0     R1.xyz0  VPM  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #50 OPT ======================================= VS/RV730/R700 =====
>===== 52 dw ===== 2 gprs ===== 1 stack =========================================
>0000  00000000 89800000 CALL_FS @0
>0002  40000006 a0480000 ALU 19 @12 KC0[CB0:0-15]
> 0012  801f3401 0f800010     1      x: ADD                T0.x,  -R1.y, 1.0
> 0014  00002c80 0f800110     2      x: MUL_IEEE           T0.x,  KC0[0].w, R1.x
> 0016  001fa07c 202284fd            y: MULADD_IEEE        R1.y,  T0.x, [0x3f155555 0,583333].x, [0xbf800000 -1].y
> 0018  80002880 2f800110            t: MUL_IEEE           T0.y,  KC0[0].z, R1.x
> 0020  3f155555 
> 0021  bf800000 
> 0022  00802c81 0f82807c     3      x: MULADD_IEEE        T0.x,  KC0[1].w, R1.y, T0.x
> 0024  00802881 2f82847c            y: MULADD_IEEE        T0.y,  KC0[1].z, R1.y, T0.y
> 0026  00002480 4f800110            z: MUL_IEEE           T0.z,  KC0[0].y, R1.x
> 0028  80002080 6f800110            w: MUL_IEEE           T0.w,  KC0[0].x, R1.x
> 0030  01002c82 0fa2807c     4      x: MULADD_IEEE        T1.x,  KC0[2].w, R1.z, T0.x
> 0032  00802481 4f82887c            z: MULADD_IEEE        T0.z,  KC0[1].y, R1.y, T0.z
> 0034  80802081 6f828c7c            w: MULADD_IEEE        T0.w,  KC0[1].x, R1.y, T0.w
> 0036  01002082 0f828c7c     5      x: MULADD_IEEE        T0.x,  KC0[2].x, R1.z, T0.w
> 0038  01002882 2f82847c            y: MULADD_IEEE        T0.y,  KC0[2].z, R1.z, T0.y
> 0040  81002482 6f82887c            w: MULADD_IEEE        T0.w,  KC0[2].y, R1.z, T0.z
> 0042  0010607c 00000010     6      x: ADD                R0.x,  T0.x, KC0[3].x
> 0044  00906c7c 20000010            y: ADD                R0.y,  T0.w, KC0[3].y
> 0046  0110647c 40000010            z: ADD                R0.z,  T0.y, KC0[3].z
> 0048  8190607d 60080010            w: ADD                R0.w,  T1.x, KC0[3].w         VEC_120
>0004  c000203c 94400688 EXPORT_DONE        POS   60    R0.xyzw  VPM
>0006  c000c000 94400888 EXPORT_DONE        PARAM 0     R1.xyz0  VPM
>0008  00000019 a0000000 ALU 1 @50
> 0050  80000000 00000d00     7      x: ALU_NOP            __.x
>0010  00000000 80200000 NOP @0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL CONST[0..2]
>DCL CONST[6]
>DCL TEMP[0..11], LOCAL
>IMM[0] FLT32 {    0,5000,     0,0050,     1,0000,     0,0000}
>IMM[1] FLT32 {    2,0000,     0,5628,     0,7502,     0,2500}
>IMM[2] FLT32 {    3,0000,     4,0000, 1000000,0000,     0,9000}
>IMM[3] UINT32 {4294967295, 0, 0, 0}
>IMM[4] FLT32 {    0,3750,    -1,0000,     1,0000,     2,0000}
>IMM[5] FLT32 {    0,9990,  -288,5390,    -0,1667,    10,0000}
>IMM[6] FLT32 {    0,1667,  5000,0000,     0,2500,     1,0000}
>IMM[7] FLT32 {   10,0000,     8,0000,     6,0000,     0,2500}
>IMM[8] FLT32 {    0,2500,     1,0000,     1,2500,     0,0000}
>  0: MAD TEMP[0].xy, IN[0].xzzz, IMM[0].xxxx, IMM[0].xxxx
>  1: MOV TEMP[1].xy, TEMP[0].xyyy
>  2: TEX TEMP[1].zw, TEMP[1], SAMP[2], 2D
>  3: MAD TEMP[0].xy, TEMP[1].zwww, IMM[0].yyyy, TEMP[0].xyyy
>  4: MOV TEMP[1].xy, TEMP[0].xyyy
>  5: TEX TEMP[1].zw, TEMP[1], SAMP[2], 2D
>  6: MAD TEMP[0].xy, TEMP[1].zwww, IMM[0].yyyy, TEMP[0].xyyy
>  7: MOV TEMP[1].xy, TEMP[0].xyyy
>  8: TEX TEMP[1].zw, TEMP[1], SAMP[2], 2D
>  9: MAD TEMP[0].xy, TEMP[1].zwww, IMM[0].yyyy, TEMP[0].xyyy
> 10: MOV TEMP[1].xy, TEMP[0].xyyy
> 11: TEX TEMP[1].zw, TEMP[1], SAMP[2], 2D
> 12: MAD TEMP[0].xy, TEMP[1].zwww, IMM[0].yyyy, TEMP[0].xyyy
> 13: MOV TEMP[1].xy, TEMP[0].xyyy
> 14: TEX TEMP[1].zw, TEMP[1], SAMP[2], 2D
> 15: MAD TEMP[0].xy, TEMP[1].zwww, IMM[0].yyyy, TEMP[0].xyyy
> 16: MOV TEMP[0].xy, TEMP[0].xyyy
> 17: TEX TEMP[0].zw, TEMP[0], SAMP[2], 2D
> 18: MOV TEMP[1].x, TEMP[0].zzzz
> 19: DP2 TEMP[2].x, TEMP[0].zwww, TEMP[0].zwww
> 20: ADD TEMP[2].x, IMM[0].zzzz, -TEMP[2].xxxx
> 21: RSQ TEMP[3].x, TEMP[2].xxxx
> 22: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[2].xxxx
> 23: CMP TEMP[3].x, -TEMP[2].xxxx, TEMP[3].xxxx, IMM[0].wwww
> 24: MOV TEMP[1].y, TEMP[3].xxxx
> 25: MOV TEMP[1].z, TEMP[0].wwww
> 26: ADD TEMP[0].xyz, IN[0].xyzz, -CONST[6].xyzz
> 27: DP3 TEMP[2].x, TEMP[0].xyzz, TEMP[0].xyzz
> 28: RSQ TEMP[2].x, TEMP[2].xxxx
> 29: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
> 30: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[0].xyzz
> 31: MUL TEMP[2].xyz, TEMP[2].xxxx, TEMP[1].xyzz
> 32: MUL TEMP[2].xyz, IMM[1].xxxx, TEMP[2].xyzz
> 33: ADD TEMP[2].xyz, TEMP[0].xyzz, -TEMP[2].xyzz
> 34: DP3 TEMP[3].x, TEMP[1].xyzz, TEMP[0].xyzz
> 35: MUL TEMP[4].x, TEMP[3].xxxx, TEMP[3].xxxx
> 36: ADD TEMP[4].x, IMM[0].zzzz, -TEMP[4].xxxx
> 37: MUL TEMP[4].x, TEMP[4].xxxx, IMM[1].yyyy
> 38: ADD TEMP[4].x, IMM[0].zzzz, -TEMP[4].xxxx
> 39: FSLT TEMP[5].x, TEMP[4].xxxx, IMM[0].wwww
> 40: UIF TEMP[5].xxxx :0
> 41:   MOV TEMP[5].xyz, IMM[0].wwww
> 42: ELSE :0
> 43:   RSQ TEMP[6].x, TEMP[4].xxxx
> 44:   MUL TEMP[6].x, TEMP[6].xxxx, TEMP[4].xxxx
> 45:   CMP TEMP[6].x, -TEMP[4].xxxx, TEMP[6].xxxx, IMM[0].wwww
> 46:   MAD TEMP[3].x, IMM[1].zzzz, TEMP[3].xxxx, TEMP[6].xxxx
> 47:   MUL TEMP[3].xyz, TEMP[3].xxxx, TEMP[1].xyzz
> 48:   MAD TEMP[5].xyz, IMM[1].zzzz, TEMP[0].xyzz, -TEMP[3].xyzz
> 49: ENDIF
> 50: DP3 TEMP[0].x, TEMP[1].xyzz, -TEMP[0].xyzz
> 51: ADD TEMP[0].x, IMM[0].zzzz, -TEMP[0].xxxx
> 52: POW TEMP[0].x, TEMP[0].xxxx, IMM[2].xxxx
> 53: LRP TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz, IMM[1].wwww
> 54: MOV TEMP[1].x, IMM[3].xxxx
> 55: ADD TEMP[3].xyz, IN[0].xyzz, -CONST[1].xyzz
> 56: DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[2].xyzz
> 57: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[2].xyzz
> 58: MUL TEMP[6].x, IMM[1].xxxx, TEMP[6].xxxx
> 59: MUL TEMP[7].x, IMM[2].yyyy, TEMP[4].xxxx
> 60: DP3 TEMP[3].x, TEMP[3].xyzz, TEMP[3].xyzz
> 61: MUL TEMP[8].x, CONST[2].xxxx, CONST[2].xxxx
> 62: ADD TEMP[3].x, TEMP[3].xxxx, -TEMP[8].xxxx
> 63: MUL TEMP[3].x, TEMP[7].xxxx, TEMP[3].xxxx
> 64: MAD TEMP[3].x, TEMP[6].xxxx, TEMP[6].xxxx, -TEMP[3].xxxx
> 65: FSLT TEMP[7].x, IMM[0].wwww, TEMP[3].xxxx
> 66: UIF TEMP[7].xxxx :0
> 67:   RSQ TEMP[7].x, TEMP[3].xxxx
> 68:   MUL TEMP[7].x, TEMP[7].xxxx, TEMP[3].xxxx
> 69:   CMP TEMP[7].x, -TEMP[3].xxxx, TEMP[7].xxxx, IMM[0].wwww
> 70:   ADD TEMP[3].x, -TEMP[6].xxxx, -TEMP[7].xxxx
> 71:   MUL TEMP[4].x, IMM[1].xxxx, TEMP[4].xxxx
> 72:   RCP TEMP[4].x, TEMP[4].xxxx
> 73:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
> 74:   FSLT TEMP[4].x, IMM[0].wwww, TEMP[3].xxxx
> 75:   UIF TEMP[4].xxxx :0
> 76:     MOV TEMP[3].x, TEMP[3].xxxx
> 77:     MOV TEMP[1].x, IMM[3].yyyy
> 78:   ENDIF
> 79: ENDIF
> 80: UIF TEMP[1].xxxx :0
> 81:   MOV TEMP[3].x, IMM[2].zzzz
> 82: ENDIF
> 83: FSLT TEMP[1].x, TEMP[3].xxxx, IMM[2].zzzz
> 84: UIF TEMP[1].xxxx :0
> 85:   MAD TEMP[1].xyz, TEMP[2].xyzz, TEMP[3].xxxx, IN[0].xyzz
> 86:   ADD TEMP[3].x, IMM[0].zzzz, CONST[2].xxxx
> 87:   ABS TEMP[4].x, TEMP[1].xxxx
> 88:   ADD TEMP[3].x, TEMP[3].xxxx, -TEMP[4].xxxx
> 89:   RCP TEMP[4].x, CONST[2].xxxx
> 90:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
> 91:   POW TEMP[3].x, TEMP[3].xxxx, IMM[2].xxxx
> 92:   RCP TEMP[3].x, TEMP[3].xxxx
> 93:   MUL TEMP[3].x, IMM[2].wwww, TEMP[3].xxxx
> 94:   ADD TEMP[3].x, IMM[0].zzzz, -TEMP[3].xxxx
> 95:   MUL TEMP[3].xyz, IMM[0].xxxx, TEMP[3].xxxx
> 96:   ADD TEMP[4].x, IMM[0].zzzz, CONST[2].xxxx
> 97:   ABS TEMP[6].x, TEMP[1].zzzz
> 98:   ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[6].xxxx
> 99:   RCP TEMP[6].x, CONST[2].xxxx
>100:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[6].xxxx
>101:   POW TEMP[4].x, TEMP[4].xxxx, IMM[2].xxxx
>102:   RCP TEMP[4].x, TEMP[4].xxxx
>103:   MUL TEMP[4].x, IMM[2].wwww, TEMP[4].xxxx
>104:   ADD TEMP[4].x, IMM[0].zzzz, -TEMP[4].xxxx
>105:   MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
>106:   ADD TEMP[4].x, TEMP[1].yyyy, IMM[0].zzzz
>107:   ADD TEMP[4].x, TEMP[4].xxxx, CONST[2].xxxx
>108:   RCP TEMP[6].x, CONST[2].xxxx
>109:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[6].xxxx
>110:   POW TEMP[4].x, TEMP[4].xxxx, IMM[2].xxxx
>111:   RCP TEMP[4].x, TEMP[4].xxxx
>112:   MUL TEMP[4].x, IMM[2].wwww, TEMP[4].xxxx
>113:   ADD TEMP[4].x, IMM[0].zzzz, -TEMP[4].xxxx
>114:   MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
>115:   ADD TEMP[4].xyz, TEMP[1].xyzz, -CONST[1].xyzz
>116:   RCP TEMP[6].x, CONST[2].xxxx
>117:   MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[6].xxxx
>118:   MOV TEMP[6].xyz, -CONST[0].xyzx
>119:   MUL TEMP[7].x, TEMP[6].yyyy, TEMP[6].yyyy
>120:   ADD TEMP[7].x, IMM[0].zzzz, -TEMP[7].xxxx
>121:   MUL TEMP[7].x, TEMP[7].xxxx, IMM[1].yyyy
>122:   ADD TEMP[7].x, IMM[0].zzzz, -TEMP[7].xxxx
>123:   FSLT TEMP[8].x, TEMP[7].xxxx, IMM[0].wwww
>124:   UIF TEMP[8].xxxx :0
>125:     MOV TEMP[8].xyz, IMM[0].wwww
>126:   ELSE :0
>127:     RSQ TEMP[9].x, TEMP[7].xxxx
>128:     MUL TEMP[9].x, TEMP[9].xxxx, TEMP[7].xxxx
>129:     CMP TEMP[9].x, -TEMP[7].xxxx, TEMP[9].xxxx, IMM[0].wwww
>130:     MAD TEMP[7].x, IMM[1].zzzz, TEMP[6].yyyy, TEMP[9].xxxx
>131:     MUL TEMP[7].xyz, TEMP[7].xxxx, IMM[0].wzww
>132:     MAD TEMP[8].xyz, IMM[1].zzzz, TEMP[6].xyzz, -TEMP[7].xyzz
>133:   ENDIF
>134:   DP3 TEMP[4].x, -TEMP[8].xyzz, TEMP[4].xyzz
>135:   MAX TEMP[4].x, IMM[0].wwww, TEMP[4].xxxx
>136:   MUL TEMP[4].x, TEMP[4].xxxx, IMM[0].xxxx
>137:   MAD TEMP[6].xy, TEMP[1].xzzz, IMM[0].xxxx, IMM[0].xxxx
>138:   MOV TEMP[6].xy, TEMP[6].xyyy
>139:   TEX TEMP[6].x, TEMP[6], SAMP[2], 2D
>140:   FSLT TEMP[6].x, TEMP[1].yyyy, TEMP[6].xxxx
>141:   UIF TEMP[6].xxxx :0
>142:     MUL TEMP[6].xy, TEMP[1].yyyy, TEMP[8].xzzz
>143:     RCP TEMP[7].x, TEMP[8].yyyy
>144:     MUL TEMP[6].xy, TEMP[6].xyyy, TEMP[7].xxxx
>145:     ADD TEMP[1].xy, TEMP[1].xzzz, -TEMP[6].xyyy
>146:     MAD TEMP[1].xy, IMM[4].xxxx, TEMP[1].xyyy, IMM[0].xxxx
>147:     MOV TEMP[1].xy, TEMP[1].xyyy
>148:     TEX TEMP[1].x, TEMP[1], SAMP[1], 2D
>149:     MUL TEMP[1].x, TEMP[1].xxxx, IMM[2].yyyy
>150:     MUL TEMP[4].x, TEMP[4].xxxx, TEMP[1].xxxx
>151:   ENDIF
>152:   ADD TEMP[1].xyz, TEMP[3].xyzz, TEMP[4].xxxx
>153:   MOV TEMP[1].xyz, TEMP[1].xyzx
>154: ELSE :0
>155:   FSLT TEMP[3].x, TEMP[2].yyyy, IMM[0].wwww
>156:   UIF TEMP[3].xxxx :0
>157:     ADD TEMP[3].xyz, IMM[4].yyyy, -IN[0].xyzz
>158:     RCP TEMP[4].x, TEMP[2].xxxx
>159:     RCP TEMP[4].y, TEMP[2].yyyy
>160:     RCP TEMP[4].z, TEMP[2].zzzz
>161:     MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xyzz
>162:     ADD TEMP[4].xyz, IMM[4].zwzz, -IN[0].xyzz
>163:     RCP TEMP[6].x, TEMP[2].xxxx
>164:     RCP TEMP[6].y, TEMP[2].yyyy
>165:     RCP TEMP[6].z, TEMP[2].zzzz
>166:     MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[6].xyzz
>167:     MAX TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xyzz
>168:     MIN TEMP[4].x, TEMP[3].xxxx, TEMP[3].yyyy
>169:     MIN TEMP[3].x, TEMP[4].xxxx, TEMP[3].zzzz
>170:     MAD TEMP[3].xyz, TEMP[2].xyzz, TEMP[3].xxxx, IN[0].xyzz
>171:     ABS TEMP[6].x, TEMP[3].xxxx
>172:     FSLT TEMP[6].x, IMM[5].xxxx, TEMP[6].xxxx
>173:     UIF TEMP[6].xxxx :0
>174:       MAD TEMP[6].xy, TEMP[3].yzzz, IMM[0].xxxx, IMM[0].zxxx
>175:       MOV TEMP[6].xy, TEMP[6].xyyy
>176:       TEX TEMP[6].xyz, TEMP[6], SAMP[0], 2D
>177:       MOV TEMP[6].xyz, TEMP[6].xyzx
>178:       MOV TEMP[7].yz, IMM[0].wwww
>179:       MOV TEMP[7].x, -TEMP[3].xxxx
>180:       MOV TEMP[7].xyz, TEMP[7].xyzx
>181:     ELSE :0
>182:       ABS TEMP[8].x, TEMP[3].zzzz
>183:       FSLT TEMP[8].x, IMM[5].xxxx, TEMP[8].xxxx
>184:       UIF TEMP[8].xxxx :0
>185:         MAD TEMP[8].xy, TEMP[3].yxxx, IMM[0].xxxx, IMM[0].zxxx
>186:         MOV TEMP[8].xy, TEMP[8].xyyy
>187:         TEX TEMP[8].xyz, TEMP[8], SAMP[0], 2D
>188:         MOV TEMP[6].xyz, TEMP[8].xyzx
>189:         MOV TEMP[8].xy, IMM[0].wwww
>190:         MOV TEMP[8].z, -TEMP[3].zzzz
>191:         MOV TEMP[7].xyz, TEMP[8].xyzx
>192:       ELSE :0
>193:         MAD TEMP[8].xy, TEMP[3].xzzz, IMM[0].xxxx, IMM[0].xxxx
>194:         MOV TEMP[8].xy, TEMP[8].xyyy
>195:         TEX TEMP[8].xyz, TEMP[8], SAMP[0], 2D
>196:         MOV TEMP[6].xyz, TEMP[8].xyzx
>197:         MOV TEMP[7].xyz, IMM[0].wzww
>198:       ENDIF
>199:     ENDIF
>200:     DP3 TEMP[8].x, TEMP[3].xyzz, TEMP[3].xyzz
>201:     RSQ TEMP[8].x, TEMP[8].xxxx
>202:     MUL TEMP[4].x, IMM[0].xxxx, TEMP[8].xxxx
>203:     ADD TEMP[8].xyz, TEMP[3].xyzz, -CONST[1].xyzz
>204:     DP3 TEMP[8].x, TEMP[8].xyzz, TEMP[8].xyzz
>205:     RSQ TEMP[9].x, TEMP[8].xxxx
>206:     MUL TEMP[9].x, TEMP[9].xxxx, TEMP[8].xxxx
>207:     CMP TEMP[9].x, -TEMP[8].xxxx, TEMP[9].xxxx, IMM[0].wwww
>208:     RCP TEMP[8].x, CONST[2].xxxx
>209:     MUL TEMP[8].x, TEMP[9].xxxx, TEMP[8].xxxx
>210:     POW TEMP[8].x, TEMP[8].xxxx, IMM[2].yyyy
>211:     RCP TEMP[8].x, TEMP[8].xxxx
>212:     MUL TEMP[8].x, IMM[2].wwww, TEMP[8].xxxx
>213:     ADD TEMP[8].x, IMM[0].zzzz, -TEMP[8].xxxx
>214:     MUL TEMP[4].x, TEMP[4].xxxx, TEMP[8].xxxx
>215:     MOV TEMP[8].xyz, -CONST[0].xyzx
>216:     MUL TEMP[9].x, TEMP[8].yyyy, TEMP[8].yyyy
>217:     ADD TEMP[9].x, IMM[0].zzzz, -TEMP[9].xxxx
>218:     MUL TEMP[9].x, TEMP[9].xxxx, IMM[1].yyyy
>219:     ADD TEMP[9].x, IMM[0].zzzz, -TEMP[9].xxxx
>220:     FSLT TEMP[10].x, TEMP[9].xxxx, IMM[0].wwww
>221:     UIF TEMP[10].xxxx :0
>222:       MOV TEMP[10].xyz, IMM[0].wwww
>223:     ELSE :0
>224:       RSQ TEMP[11].x, TEMP[9].xxxx
>225:       MUL TEMP[11].x, TEMP[11].xxxx, TEMP[9].xxxx
>226:       CMP TEMP[11].x, -TEMP[9].xxxx, TEMP[11].xxxx, IMM[0].wwww
>227:       MAD TEMP[9].x, IMM[1].zzzz, TEMP[8].yyyy, TEMP[11].xxxx
>228:       MUL TEMP[9].xyz, TEMP[9].xxxx, IMM[0].wzww
>229:       MAD TEMP[10].xyz, IMM[1].zzzz, TEMP[8].xyzz, -TEMP[9].xyzz
>230:     ENDIF
>231:     MOV TEMP[8].xyz, -TEMP[10].xyzx
>232:     DP3 TEMP[7].x, TEMP[8].xyzz, TEMP[7].xyzz
>233:     MAX TEMP[7].x, IMM[0].wwww, TEMP[7].xxxx
>234:     MAD TEMP[9].xy, TEMP[3].xzzz, IMM[0].xxxx, IMM[0].xxxx
>235:     MOV TEMP[9].xy, TEMP[9].xyyy
>236:     TEX TEMP[9].x, TEMP[9], SAMP[2], 2D
>237:     FSLT TEMP[9].x, TEMP[3].yyyy, TEMP[9].xxxx
>238:     UIF TEMP[9].xxxx :0
>239:       MUL TEMP[9].xy, TEMP[3].yyyy, TEMP[8].xzzz
>240:       RCP TEMP[10].x, TEMP[8].yyyy
>241:       MUL TEMP[9].xy, TEMP[9].xyyy, TEMP[10].xxxx
>242:       ADD TEMP[9].xy, TEMP[3].xzzz, -TEMP[9].xyyy
>243:       MAD TEMP[9].xy, IMM[4].xxxx, TEMP[9].xyyy, IMM[0].xxxx
>244:       MOV TEMP[9].xy, TEMP[9].xyyy
>245:       TEX TEMP[9].xy, TEMP[9], SAMP[1], 2D
>246:       MUL TEMP[10].x, TEMP[7].xxxx, TEMP[9].xxxx
>247:       MUL TEMP[10].x, TEMP[10].xxxx, IMM[1].xxxx
>248:       MAD TEMP[4].x, TEMP[10].xxxx, TEMP[9].yyyy, TEMP[4].xxxx
>249:     ELSE :0
>250:       ADD TEMP[9].xyz, IMM[4].yyyy, -TEMP[3].xyzz
>251:       RCP TEMP[10].x, TEMP[8].xxxx
>252:       RCP TEMP[10].y, TEMP[8].yyyy
>253:       RCP TEMP[10].z, TEMP[8].zzzz
>254:       MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[10].xyzz
>255:       ADD TEMP[10].xyz, IMM[4].zwzz, -TEMP[3].xyzz
>256:       RCP TEMP[11].x, TEMP[8].xxxx
>257:       RCP TEMP[11].y, TEMP[8].yyyy
>258:       RCP TEMP[11].z, TEMP[8].zzzz
>259:       MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[11].xyzz
>260:       MIN TEMP[11].xyz, TEMP[9].xyzz, TEMP[10].xyzz
>261:       MAX TEMP[9].xyz, TEMP[9].xyzz, TEMP[10].xyzz
>262:       MIN TEMP[10].x, TEMP[9].xxxx, TEMP[9].yyyy
>263:       MIN TEMP[9].x, TEMP[10].xxxx, TEMP[9].zzzz
>264:       MAD TEMP[3].x, TEMP[8].yyyy, TEMP[9].xxxx, TEMP[3].yyyy
>265:       ADD TEMP[3].x, TEMP[3].xxxx, IMM[5].zzzz
>266:       MUL TEMP[3].x, IMM[5].yyyy, TEMP[3].xxxx
>267:       MAX TEMP[8].x, TEMP[11].xxxx, TEMP[11].yyyy
>268:       MAX TEMP[8].x, TEMP[8].xxxx, TEMP[11].zzzz
>269:       ADD TEMP[8].x, TEMP[9].xxxx, -TEMP[8].xxxx
>270:       MAD TEMP[8].x, IMM[5].wwww, TEMP[8].xxxx, IMM[0].zzzz
>271:       RCP TEMP[8].x, TEMP[8].xxxx
>272:       MUL TEMP[3].x, TEMP[3].xxxx, TEMP[8].xxxx
>273:       EX2 TEMP[3].x, TEMP[3].xxxx
>274:       ADD TEMP[3].x, IMM[0].zzzz, TEMP[3].xxxx
>275:       RCP TEMP[3].x, TEMP[3].xxxx
>276:       MUL TEMP[3].x, TEMP[7].xxxx, TEMP[3].xxxx
>277:       MAD TEMP[4].x, TEMP[3].xxxx, IMM[0].xxxx, TEMP[4].xxxx
>278:     ENDIF
>279:     MUL TEMP[1].xyz, TEMP[6].xyzz, TEMP[4].xxxx
>280:   ELSE :0
>281:     ADD TEMP[3].xyz, IMM[4].yyyy, -IN[0].xyzz
>282:     RCP TEMP[4].x, TEMP[2].xxxx
>283:     RCP TEMP[4].y, TEMP[2].yyyy
>284:     RCP TEMP[4].z, TEMP[2].zzzz
>285:     MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xyzz
>286:     ADD TEMP[4].xyz, IMM[4].zwzz, -IN[0].xyzz
>287:     RCP TEMP[6].x, TEMP[2].xxxx
>288:     RCP TEMP[6].y, TEMP[2].yyyy
>289:     RCP TEMP[6].z, TEMP[2].zzzz
>290:     MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[6].xyzz
>291:     MAX TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xyzz
>292:     MIN TEMP[4].x, TEMP[3].xxxx, TEMP[3].yyyy
>293:     MIN TEMP[3].x, TEMP[4].xxxx, TEMP[3].zzzz
>294:     MAD TEMP[3].xyz, TEMP[2].xyzz, TEMP[3].xxxx, IN[0].xyzz
>295:     FSLT TEMP[4].x, TEMP[3].yyyy, IMM[6].xxxx
>296:     UIF TEMP[4].xxxx :0
>297:       ABS TEMP[6].x, TEMP[3].xxxx
>298:       FSLT TEMP[6].x, IMM[5].xxxx, TEMP[6].xxxx
>299:       UIF TEMP[6].xxxx :0
>300:         MAD TEMP[6].xy, TEMP[3].yzzz, IMM[0].xxxx, IMM[0].zxxx
>301:         MOV TEMP[6].xy, TEMP[6].xyyy
>302:         TEX TEMP[6].xyz, TEMP[6], SAMP[0], 2D
>303:         MOV TEMP[6].xyz, TEMP[6].xyzx
>304:         MOV TEMP[7].yz, IMM[0].wwww
>305:         MOV TEMP[7].x, -TEMP[3].xxxx
>306:         MOV TEMP[7].xyz, TEMP[7].xyzx
>307:       ELSE :0
>308:         ABS TEMP[8].x, TEMP[3].zzzz
>309:         FSLT TEMP[8].x, IMM[5].xxxx, TEMP[8].xxxx
>310:         UIF TEMP[8].xxxx :0
>311:           MAD TEMP[8].xy, TEMP[3].yxxx, IMM[0].xxxx, IMM[0].zxxx
>312:           MOV TEMP[8].xy, TEMP[8].xyyy
>313:           TEX TEMP[8].xyz, TEMP[8], SAMP[0], 2D
>314:           MOV TEMP[6].xyz, TEMP[8].xyzx
>315:           MOV TEMP[8].xy, IMM[0].wwww
>316:           MOV TEMP[8].z, -TEMP[3].zzzz
>317:           MOV TEMP[7].xyz, TEMP[8].xyzx
>318:         ELSE :0
>319:           MAD TEMP[8].xy, TEMP[3].xzzz, IMM[0].xxxx, IMM[0].xxxx
>320:           MOV TEMP[8].xy, TEMP[8].xyyy
>321:           TEX TEMP[8].xyz, TEMP[8], SAMP[0], 2D
>322:           MOV TEMP[6].xyz, TEMP[8].xyzx
>323:           MOV TEMP[7].xyz, IMM[0].wzww
>324:         ENDIF
>325:       ENDIF
>326:       DP3 TEMP[8].x, TEMP[3].xyzz, TEMP[3].xyzz
>327:       RSQ TEMP[8].x, TEMP[8].xxxx
>328:       MUL TEMP[4].x, IMM[0].xxxx, TEMP[8].xxxx
>329:       ADD TEMP[8].xyz, TEMP[3].xyzz, -CONST[1].xyzz
>330:       DP3 TEMP[8].x, TEMP[8].xyzz, TEMP[8].xyzz
>331:       RSQ TEMP[9].x, TEMP[8].xxxx
>332:       MUL TEMP[9].x, TEMP[9].xxxx, TEMP[8].xxxx
>333:       CMP TEMP[9].x, -TEMP[8].xxxx, TEMP[9].xxxx, IMM[0].wwww
>334:       RCP TEMP[8].x, CONST[2].xxxx
>335:       MUL TEMP[8].x, TEMP[9].xxxx, TEMP[8].xxxx
>336:       POW TEMP[8].x, TEMP[8].xxxx, IMM[2].yyyy
>337:       RCP TEMP[8].x, TEMP[8].xxxx
>338:       MUL TEMP[8].x, IMM[2].wwww, TEMP[8].xxxx
>339:       ADD TEMP[8].x, IMM[0].zzzz, -TEMP[8].xxxx
>340:       MUL TEMP[4].x, TEMP[4].xxxx, TEMP[8].xxxx
>341:       MOV TEMP[8].xyz, -CONST[0].xyzx
>342:       MUL TEMP[9].x, TEMP[8].yyyy, TEMP[8].yyyy
>343:       ADD TEMP[9].x, IMM[0].zzzz, -TEMP[9].xxxx
>344:       MUL TEMP[9].x, TEMP[9].xxxx, IMM[1].yyyy
>345:       ADD TEMP[9].x, IMM[0].zzzz, -TEMP[9].xxxx
>346:       FSLT TEMP[10].x, TEMP[9].xxxx, IMM[0].wwww
>347:       UIF TEMP[10].xxxx :0
>348:         MOV TEMP[10].xyz, IMM[0].wwww
>349:       ELSE :0
>350:         RSQ TEMP[11].x, TEMP[9].xxxx
>351:         MUL TEMP[11].x, TEMP[11].xxxx, TEMP[9].xxxx
>352:         CMP TEMP[11].x, -TEMP[9].xxxx, TEMP[11].xxxx, IMM[0].wwww
>353:         MAD TEMP[9].x, IMM[1].zzzz, TEMP[8].yyyy, TEMP[11].xxxx
>354:         MUL TEMP[9].xyz, TEMP[9].xxxx, IMM[0].wzww
>355:         MAD TEMP[10].xyz, IMM[1].zzzz, TEMP[8].xyzz, -TEMP[9].xyzz
>356:       ENDIF
>357:       MOV TEMP[8].xyz, -TEMP[10].xyzx
>358:       DP3 TEMP[7].x, TEMP[8].xyzz, TEMP[7].xyzz
>359:       MAX TEMP[7].x, IMM[0].wwww, TEMP[7].xxxx
>360:       MAD TEMP[9].xy, TEMP[3].xzzz, IMM[0].xxxx, IMM[0].xxxx
>361:       MOV TEMP[9].xy, TEMP[9].xyyy
>362:       TEX TEMP[9].x, TEMP[9], SAMP[2], 2D
>363:       FSLT TEMP[9].x, TEMP[3].yyyy, TEMP[9].xxxx
>364:       UIF TEMP[9].xxxx :0
>365:         MUL TEMP[9].xy, TEMP[3].yyyy, TEMP[8].xzzz
>366:         RCP TEMP[10].x, TEMP[8].yyyy
>367:         MUL TEMP[9].xy, TEMP[9].xyyy, TEMP[10].xxxx
>368:         ADD TEMP[9].xy, TEMP[3].xzzz, -TEMP[9].xyyy
>369:         MAD TEMP[9].xy, IMM[4].xxxx, TEMP[9].xyyy, IMM[0].xxxx
>370:         MOV TEMP[9].xy, TEMP[9].xyyy
>371:         TEX TEMP[9].xy, TEMP[9], SAMP[1], 2D
>372:         MUL TEMP[10].x, TEMP[7].xxxx, TEMP[9].xxxx
>373:         MUL TEMP[10].x, TEMP[10].xxxx, IMM[1].xxxx
>374:         MAD TEMP[4].x, TEMP[10].xxxx, TEMP[9].yyyy, TEMP[4].xxxx
>375:       ELSE :0
>376:         ADD TEMP[9].xyz, IMM[4].yyyy, -TEMP[3].xyzz
>377:         RCP TEMP[10].x, TEMP[8].xxxx
>378:         RCP TEMP[10].y, TEMP[8].yyyy
>379:         RCP TEMP[10].z, TEMP[8].zzzz
>380:         MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[10].xyzz
>381:         ADD TEMP[10].xyz, IMM[4].zwzz, -TEMP[3].xyzz
>382:         RCP TEMP[11].x, TEMP[8].xxxx
>383:         RCP TEMP[11].y, TEMP[8].yyyy
>384:         RCP TEMP[11].z, TEMP[8].zzzz
>385:         MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[11].xyzz
>386:         MIN TEMP[11].xyz, TEMP[9].xyzz, TEMP[10].xyzz
>387:         MAX TEMP[9].xyz, TEMP[9].xyzz, TEMP[10].xyzz
>388:         MIN TEMP[10].x, TEMP[9].xxxx, TEMP[9].yyyy
>389:         MIN TEMP[9].x, TEMP[10].xxxx, TEMP[9].zzzz
>390:         MAD TEMP[3].x, TEMP[8].yyyy, TEMP[9].xxxx, TEMP[3].yyyy
>391:         ADD TEMP[3].x, TEMP[3].xxxx, IMM[5].zzzz
>392:         MUL TEMP[3].x, IMM[5].yyyy, TEMP[3].xxxx
>393:         MAX TEMP[8].x, TEMP[11].xxxx, TEMP[11].yyyy
>394:         MAX TEMP[8].x, TEMP[8].xxxx, TEMP[11].zzzz
>395:         ADD TEMP[8].x, TEMP[9].xxxx, -TEMP[8].xxxx
>396:         MAD TEMP[8].x, IMM[5].wwww, TEMP[8].xxxx, IMM[0].zzzz
>397:         RCP TEMP[8].x, TEMP[8].xxxx
>398:         MUL TEMP[3].x, TEMP[3].xxxx, TEMP[8].xxxx
>399:         EX2 TEMP[3].x, TEMP[3].xxxx
>400:         ADD TEMP[3].x, IMM[0].zzzz, TEMP[3].xxxx
>401:         RCP TEMP[3].x, TEMP[3].xxxx
>402:         MUL TEMP[3].x, TEMP[7].xxxx, TEMP[3].xxxx
>403:         MAD TEMP[4].x, TEMP[3].xxxx, IMM[0].xxxx, TEMP[4].xxxx
>404:       ENDIF
>405:       MUL TEMP[1].xyz, TEMP[6].xyzz, TEMP[4].xxxx
>406:     ELSE :0
>407:       DP3 TEMP[3].x, CONST[0].xyzz, TEMP[2].xyzz
>408:       MAX TEMP[3].x, IMM[0].wwww, TEMP[3].xxxx
>409:       POW TEMP[3].x, TEMP[3].xxxx, IMM[6].yyyy
>410:       MOV TEMP[4].xyz, TEMP[2].xyzz
>411:       TEX TEMP[4].xyz, TEMP[4], SAMP[3], CUBE
>412:       MAD TEMP[1].xyz, TEMP[3].xxxx, IMM[7].xyzz, TEMP[4].xyzz
>413:     ENDIF
>414:   ENDIF
>415: ENDIF
>416: FSLT TEMP[2].x, TEMP[2].yyyy, IMM[0].wwww
>417: UIF TEMP[2].xxxx :0
>418:   MUL TEMP[1].xyz, TEMP[1].xyzz, IMM[8].xyzz
>419: ENDIF
>420: MOV TEMP[2].x, IMM[3].xxxx
>421: ADD TEMP[3].xyz, IN[0].xyzz, -CONST[1].xyzz
>422: DP3 TEMP[4].x, TEMP[5].xyzz, TEMP[5].xyzz
>423: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[5].xyzz
>424: MUL TEMP[6].x, IMM[1].xxxx, TEMP[6].xxxx
>425: MUL TEMP[7].x, IMM[2].yyyy, TEMP[4].xxxx
>426: DP3 TEMP[3].x, TEMP[3].xyzz, TEMP[3].xyzz
>427: MUL TEMP[8].x, CONST[2].xxxx, CONST[2].xxxx
>428: ADD TEMP[3].x, TEMP[3].xxxx, -TEMP[8].xxxx
>429: MUL TEMP[3].x, TEMP[7].xxxx, TEMP[3].xxxx
>430: MAD TEMP[3].x, TEMP[6].xxxx, TEMP[6].xxxx, -TEMP[3].xxxx
>431: FSLT TEMP[7].x, IMM[0].wwww, TEMP[3].xxxx
>432: UIF TEMP[7].xxxx :0
>433:   RSQ TEMP[7].x, TEMP[3].xxxx
>434:   MUL TEMP[7].x, TEMP[7].xxxx, TEMP[3].xxxx
>435:   CMP TEMP[7].x, -TEMP[3].xxxx, TEMP[7].xxxx, IMM[0].wwww
>436:   ADD TEMP[3].x, -TEMP[6].xxxx, -TEMP[7].xxxx
>437:   MUL TEMP[4].x, IMM[1].xxxx, TEMP[4].xxxx
>438:   RCP TEMP[4].x, TEMP[4].xxxx
>439:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>440:   FSLT TEMP[4].x, IMM[0].wwww, TEMP[3].xxxx
>441:   UIF TEMP[4].xxxx :0
>442:     MOV TEMP[3].x, TEMP[3].xxxx
>443:     MOV TEMP[2].x, IMM[3].yyyy
>444:   ENDIF
>445: ENDIF
>446: UIF TEMP[2].xxxx :0
>447:   MOV TEMP[3].x, IMM[2].zzzz
>448: ENDIF
>449: FSLT TEMP[2].x, TEMP[3].xxxx, IMM[2].zzzz
>450: UIF TEMP[2].xxxx :0
>451:   MAD TEMP[2].xyz, TEMP[5].xyzz, TEMP[3].xxxx, IN[0].xyzz
>452:   ADD TEMP[3].x, IMM[0].zzzz, CONST[2].xxxx
>453:   ABS TEMP[4].x, TEMP[2].xxxx
>454:   ADD TEMP[3].x, TEMP[3].xxxx, -TEMP[4].xxxx
>455:   RCP TEMP[4].x, CONST[2].xxxx
>456:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>457:   POW TEMP[3].x, TEMP[3].xxxx, IMM[2].xxxx
>458:   RCP TEMP[3].x, TEMP[3].xxxx
>459:   MUL TEMP[3].x, IMM[2].wwww, TEMP[3].xxxx
>460:   ADD TEMP[3].x, IMM[0].zzzz, -TEMP[3].xxxx
>461:   MUL TEMP[3].xyz, IMM[0].xxxx, TEMP[3].xxxx
>462:   ADD TEMP[4].x, IMM[0].zzzz, CONST[2].xxxx
>463:   ABS TEMP[6].x, TEMP[2].zzzz
>464:   ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[6].xxxx
>465:   RCP TEMP[6].x, CONST[2].xxxx
>466:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[6].xxxx
>467:   POW TEMP[4].x, TEMP[4].xxxx, IMM[2].xxxx
>468:   RCP TEMP[4].x, TEMP[4].xxxx
>469:   MUL TEMP[4].x, IMM[2].wwww, TEMP[4].xxxx
>470:   ADD TEMP[4].x, IMM[0].zzzz, -TEMP[4].xxxx
>471:   MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
>472:   ADD TEMP[4].x, TEMP[2].yyyy, IMM[0].zzzz
>473:   ADD TEMP[4].x, TEMP[4].xxxx, CONST[2].xxxx
>474:   RCP TEMP[6].x, CONST[2].xxxx
>475:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[6].xxxx
>476:   POW TEMP[4].x, TEMP[4].xxxx, IMM[2].xxxx
>477:   RCP TEMP[4].x, TEMP[4].xxxx
>478:   MUL TEMP[4].x, IMM[2].wwww, TEMP[4].xxxx
>479:   ADD TEMP[4].x, IMM[0].zzzz, -TEMP[4].xxxx
>480:   MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
>481:   ADD TEMP[4].xyz, TEMP[2].xyzz, -CONST[1].xyzz
>482:   RCP TEMP[6].x, CONST[2].xxxx
>483:   MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[6].xxxx
>484:   MOV TEMP[6].xyz, -CONST[0].xyzx
>485:   MUL TEMP[7].x, TEMP[6].yyyy, TEMP[6].yyyy
>486:   ADD TEMP[7].x, IMM[0].zzzz, -TEMP[7].xxxx
>487:   MUL TEMP[7].x, TEMP[7].xxxx, IMM[1].yyyy
>488:   ADD TEMP[7].x, IMM[0].zzzz, -TEMP[7].xxxx
>489:   FSLT TEMP[8].x, TEMP[7].xxxx, IMM[0].wwww
>490:   UIF TEMP[8].xxxx :0
>491:     MOV TEMP[8].xyz, IMM[0].wwww
>492:   ELSE :0
>493:     RSQ TEMP[9].x, TEMP[7].xxxx
>494:     MUL TEMP[9].x, TEMP[9].xxxx, TEMP[7].xxxx
>495:     CMP TEMP[9].x, -TEMP[7].xxxx, TEMP[9].xxxx, IMM[0].wwww
>496:     MAD TEMP[7].x, IMM[1].zzzz, TEMP[6].yyyy, TEMP[9].xxxx
>497:     MUL TEMP[7].xyz, TEMP[7].xxxx, IMM[0].wzww
>498:     MAD TEMP[8].xyz, IMM[1].zzzz, TEMP[6].xyzz, -TEMP[7].xyzz
>499:   ENDIF
>500:   DP3 TEMP[4].x, -TEMP[8].xyzz, TEMP[4].xyzz
>501:   MAX TEMP[4].x, IMM[0].wwww, TEMP[4].xxxx
>502:   MUL TEMP[4].x, TEMP[4].xxxx, IMM[0].xxxx
>503:   MAD TEMP[6].xy, TEMP[2].xzzz, IMM[0].xxxx, IMM[0].xxxx
>504:   MOV TEMP[6].xy, TEMP[6].xyyy
>505:   TEX TEMP[6].x, TEMP[6], SAMP[2], 2D
>506:   FSLT TEMP[6].x, TEMP[2].yyyy, TEMP[6].xxxx
>507:   UIF TEMP[6].xxxx :0
>508:     MUL TEMP[6].xy, TEMP[2].yyyy, TEMP[8].xzzz
>509:     RCP TEMP[7].x, TEMP[8].yyyy
>510:     MUL TEMP[6].xy, TEMP[6].xyyy, TEMP[7].xxxx
>511:     ADD TEMP[2].xy, TEMP[2].xzzz, -TEMP[6].xyyy
>512:     MAD TEMP[2].xy, IMM[4].xxxx, TEMP[2].xyyy, IMM[0].xxxx
>513:     MOV TEMP[2].xy, TEMP[2].xyyy
>514:     TEX TEMP[2].x, TEMP[2], SAMP[1], 2D
>515:     MUL TEMP[2].x, TEMP[2].xxxx, IMM[2].yyyy
>516:     MUL TEMP[4].x, TEMP[4].xxxx, TEMP[2].xxxx
>517:   ENDIF
>518:   ADD TEMP[2].xyz, TEMP[3].xyzz, TEMP[4].xxxx
>519:   MOV TEMP[2].xyz, TEMP[2].xyzx
>520: ELSE :0
>521:   FSLT TEMP[3].x, TEMP[5].yyyy, IMM[0].wwww
>522:   UIF TEMP[3].xxxx :0
>523:     ADD TEMP[3].xyz, IMM[4].yyyy, -IN[0].xyzz
>524:     RCP TEMP[4].x, TEMP[5].xxxx
>525:     RCP TEMP[4].y, TEMP[5].yyyy
>526:     RCP TEMP[4].z, TEMP[5].zzzz
>527:     MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xyzz
>528:     ADD TEMP[4].xyz, IMM[4].zwzz, -IN[0].xyzz
>529:     RCP TEMP[6].x, TEMP[5].xxxx
>530:     RCP TEMP[6].y, TEMP[5].yyyy
>531:     RCP TEMP[6].z, TEMP[5].zzzz
>532:     MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[6].xyzz
>533:     MAX TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xyzz
>534:     MIN TEMP[4].x, TEMP[3].xxxx, TEMP[3].yyyy
>535:     MIN TEMP[3].x, TEMP[4].xxxx, TEMP[3].zzzz
>536:     MAD TEMP[3].xyz, TEMP[5].xyzz, TEMP[3].xxxx, IN[0].xyzz
>537:     ABS TEMP[6].x, TEMP[3].xxxx
>538:     FSLT TEMP[6].x, IMM[5].xxxx, TEMP[6].xxxx
>539:     UIF TEMP[6].xxxx :0
>540:       MAD TEMP[6].xy, TEMP[3].yzzz, IMM[0].xxxx, IMM[0].zxxx
>541:       MOV TEMP[6].xy, TEMP[6].xyyy
>542:       TEX TEMP[6].xyz, TEMP[6], SAMP[0], 2D
>543:       MOV TEMP[6].xyz, TEMP[6].xyzx
>544:       MOV TEMP[7].yz, IMM[0].wwww
>545:       MOV TEMP[7].x, -TEMP[3].xxxx
>546:       MOV TEMP[7].xyz, TEMP[7].xyzx
>547:     ELSE :0
>548:       ABS TEMP[8].x, TEMP[3].zzzz
>549:       FSLT TEMP[8].x, IMM[5].xxxx, TEMP[8].xxxx
>550:       UIF TEMP[8].xxxx :0
>551:         MAD TEMP[8].xy, TEMP[3].yxxx, IMM[0].xxxx, IMM[0].zxxx
>552:         MOV TEMP[8].xy, TEMP[8].xyyy
>553:         TEX TEMP[8].xyz, TEMP[8], SAMP[0], 2D
>554:         MOV TEMP[6].xyz, TEMP[8].xyzx
>555:         MOV TEMP[8].xy, IMM[0].wwww
>556:         MOV TEMP[8].z, -TEMP[3].zzzz
>557:         MOV TEMP[7].xyz, TEMP[8].xyzx
>558:       ELSE :0
>559:         MAD TEMP[8].xy, TEMP[3].xzzz, IMM[0].xxxx, IMM[0].xxxx
>560:         MOV TEMP[8].xy, TEMP[8].xyyy
>561:         TEX TEMP[8].xyz, TEMP[8], SAMP[0], 2D
>562:         MOV TEMP[6].xyz, TEMP[8].xyzx
>563:         MOV TEMP[7].xyz, IMM[0].wzww
>564:       ENDIF
>565:     ENDIF
>566:     DP3 TEMP[8].x, TEMP[3].xyzz, TEMP[3].xyzz
>567:     RSQ TEMP[8].x, TEMP[8].xxxx
>568:     MUL TEMP[4].x, IMM[0].xxxx, TEMP[8].xxxx
>569:     ADD TEMP[8].xyz, TEMP[3].xyzz, -CONST[1].xyzz
>570:     DP3 TEMP[8].x, TEMP[8].xyzz, TEMP[8].xyzz
>571:     RSQ TEMP[9].x, TEMP[8].xxxx
>572:     MUL TEMP[9].x, TEMP[9].xxxx, TEMP[8].xxxx
>573:     CMP TEMP[9].x, -TEMP[8].xxxx, TEMP[9].xxxx, IMM[0].wwww
>574:     RCP TEMP[8].x, CONST[2].xxxx
>575:     MUL TEMP[8].x, TEMP[9].xxxx, TEMP[8].xxxx
>576:     POW TEMP[8].x, TEMP[8].xxxx, IMM[2].yyyy
>577:     RCP TEMP[8].x, TEMP[8].xxxx
>578:     MUL TEMP[8].x, IMM[2].wwww, TEMP[8].xxxx
>579:     ADD TEMP[8].x, IMM[0].zzzz, -TEMP[8].xxxx
>580:     MUL TEMP[4].x, TEMP[4].xxxx, TEMP[8].xxxx
>581:     MOV TEMP[8].xyz, -CONST[0].xyzx
>582:     MUL TEMP[9].x, TEMP[8].yyyy, TEMP[8].yyyy
>583:     ADD TEMP[9].x, IMM[0].zzzz, -TEMP[9].xxxx
>584:     MUL TEMP[9].x, TEMP[9].xxxx, IMM[1].yyyy
>585:     ADD TEMP[9].x, IMM[0].zzzz, -TEMP[9].xxxx
>586:     FSLT TEMP[10].x, TEMP[9].xxxx, IMM[0].wwww
>587:     UIF TEMP[10].xxxx :0
>588:       MOV TEMP[10].xyz, IMM[0].wwww
>589:     ELSE :0
>590:       RSQ TEMP[11].x, TEMP[9].xxxx
>591:       MUL TEMP[11].x, TEMP[11].xxxx, TEMP[9].xxxx
>592:       CMP TEMP[11].x, -TEMP[9].xxxx, TEMP[11].xxxx, IMM[0].wwww
>593:       MAD TEMP[9].x, IMM[1].zzzz, TEMP[8].yyyy, TEMP[11].xxxx
>594:       MUL TEMP[9].xyz, TEMP[9].xxxx, IMM[0].wzww
>595:       MAD TEMP[10].xyz, IMM[1].zzzz, TEMP[8].xyzz, -TEMP[9].xyzz
>596:     ENDIF
>597:     MOV TEMP[8].xyz, -TEMP[10].xyzx
>598:     DP3 TEMP[7].x, TEMP[8].xyzz, TEMP[7].xyzz
>599:     MAX TEMP[7].x, IMM[0].wwww, TEMP[7].xxxx
>600:     MAD TEMP[9].xy, TEMP[3].xzzz, IMM[0].xxxx, IMM[0].xxxx
>601:     MOV TEMP[9].xy, TEMP[9].xyyy
>602:     TEX TEMP[9].x, TEMP[9], SAMP[2], 2D
>603:     FSLT TEMP[9].x, TEMP[3].yyyy, TEMP[9].xxxx
>604:     UIF TEMP[9].xxxx :0
>605:       MUL TEMP[9].xy, TEMP[3].yyyy, TEMP[8].xzzz
>606:       RCP TEMP[10].x, TEMP[8].yyyy
>607:       MUL TEMP[9].xy, TEMP[9].xyyy, TEMP[10].xxxx
>608:       ADD TEMP[9].xy, TEMP[3].xzzz, -TEMP[9].xyyy
>609:       MAD TEMP[9].xy, IMM[4].xxxx, TEMP[9].xyyy, IMM[0].xxxx
>610:       MOV TEMP[9].xy, TEMP[9].xyyy
>611:       TEX TEMP[9].xy, TEMP[9], SAMP[1], 2D
>612:       MUL TEMP[10].x, TEMP[7].xxxx, TEMP[9].xxxx
>613:       MUL TEMP[10].x, TEMP[10].xxxx, IMM[1].xxxx
>614:       MAD TEMP[4].x, TEMP[10].xxxx, TEMP[9].yyyy, TEMP[4].xxxx
>615:     ELSE :0
>616:       ADD TEMP[9].xyz, IMM[4].yyyy, -TEMP[3].xyzz
>617:       RCP TEMP[10].x, TEMP[8].xxxx
>618:       RCP TEMP[10].y, TEMP[8].yyyy
>619:       RCP TEMP[10].z, TEMP[8].zzzz
>620:       MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[10].xyzz
>621:       ADD TEMP[10].xyz, IMM[4].zwzz, -TEMP[3].xyzz
>622:       RCP TEMP[11].x, TEMP[8].xxxx
>623:       RCP TEMP[11].y, TEMP[8].yyyy
>624:       RCP TEMP[11].z, TEMP[8].zzzz
>625:       MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[11].xyzz
>626:       MIN TEMP[11].xyz, TEMP[9].xyzz, TEMP[10].xyzz
>627:       MAX TEMP[9].xyz, TEMP[9].xyzz, TEMP[10].xyzz
>628:       MIN TEMP[10].x, TEMP[9].xxxx, TEMP[9].yyyy
>629:       MIN TEMP[9].x, TEMP[10].xxxx, TEMP[9].zzzz
>630:       MAD TEMP[3].x, TEMP[8].yyyy, TEMP[9].xxxx, TEMP[3].yyyy
>631:       ADD TEMP[3].x, TEMP[3].xxxx, IMM[5].zzzz
>632:       MUL TEMP[3].x, IMM[5].yyyy, TEMP[3].xxxx
>633:       MAX TEMP[8].x, TEMP[11].xxxx, TEMP[11].yyyy
>634:       MAX TEMP[8].x, TEMP[8].xxxx, TEMP[11].zzzz
>635:       ADD TEMP[8].x, TEMP[9].xxxx, -TEMP[8].xxxx
>636:       MAD TEMP[8].x, IMM[5].wwww, TEMP[8].xxxx, IMM[0].zzzz
>637:       RCP TEMP[8].x, TEMP[8].xxxx
>638:       MUL TEMP[3].x, TEMP[3].xxxx, TEMP[8].xxxx
>639:       EX2 TEMP[3].x, TEMP[3].xxxx
>640:       ADD TEMP[3].x, IMM[0].zzzz, TEMP[3].xxxx
>641:       RCP TEMP[3].x, TEMP[3].xxxx
>642:       MUL TEMP[3].x, TEMP[7].xxxx, TEMP[3].xxxx
>643:       MAD TEMP[4].x, TEMP[3].xxxx, IMM[0].xxxx, TEMP[4].xxxx
>644:     ENDIF
>645:     MUL TEMP[2].xyz, TEMP[6].xyzz, TEMP[4].xxxx
>646:   ELSE :0
>647:     ADD TEMP[3].xyz, IMM[4].yyyy, -IN[0].xyzz
>648:     RCP TEMP[4].x, TEMP[5].xxxx
>649:     RCP TEMP[4].y, TEMP[5].yyyy
>650:     RCP TEMP[4].z, TEMP[5].zzzz
>651:     MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xyzz
>652:     ADD TEMP[4].xyz, IMM[4].zwzz, -IN[0].xyzz
>653:     RCP TEMP[6].x, TEMP[5].xxxx
>654:     RCP TEMP[6].y, TEMP[5].yyyy
>655:     RCP TEMP[6].z, TEMP[5].zzzz
>656:     MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[6].xyzz
>657:     MAX TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xyzz
>658:     MIN TEMP[4].x, TEMP[3].xxxx, TEMP[3].yyyy
>659:     MIN TEMP[3].x, TEMP[4].xxxx, TEMP[3].zzzz
>660:     MAD TEMP[3].xyz, TEMP[5].xyzz, TEMP[3].xxxx, IN[0].xyzz
>661:     FSLT TEMP[4].x, TEMP[3].yyyy, IMM[6].xxxx
>662:     UIF TEMP[4].xxxx :0
>663:       ABS TEMP[6].x, TEMP[3].xxxx
>664:       FSLT TEMP[6].x, IMM[5].xxxx, TEMP[6].xxxx
>665:       UIF TEMP[6].xxxx :0
>666:         MAD TEMP[6].xy, TEMP[3].yzzz, IMM[0].xxxx, IMM[0].zxxx
>667:         MOV TEMP[6].xy, TEMP[6].xyyy
>668:         TEX TEMP[6].xyz, TEMP[6], SAMP[0], 2D
>669:         MOV TEMP[6].xyz, TEMP[6].xyzx
>670:         MOV TEMP[7].yz, IMM[0].wwww
>671:         MOV TEMP[7].x, -TEMP[3].xxxx
>672:         MOV TEMP[7].xyz, TEMP[7].xyzx
>673:       ELSE :0
>674:         ABS TEMP[8].x, TEMP[3].zzzz
>675:         FSLT TEMP[8].x, IMM[5].xxxx, TEMP[8].xxxx
>676:         UIF TEMP[8].xxxx :0
>677:           MAD TEMP[8].xy, TEMP[3].yxxx, IMM[0].xxxx, IMM[0].zxxx
>678:           MOV TEMP[8].xy, TEMP[8].xyyy
>679:           TEX TEMP[8].xyz, TEMP[8], SAMP[0], 2D
>680:           MOV TEMP[6].xyz, TEMP[8].xyzx
>681:           MOV TEMP[8].xy, IMM[0].wwww
>682:           MOV TEMP[8].z, -TEMP[3].zzzz
>683:           MOV TEMP[7].xyz, TEMP[8].xyzx
>684:         ELSE :0
>685:           MAD TEMP[8].xy, TEMP[3].xzzz, IMM[0].xxxx, IMM[0].xxxx
>686:           MOV TEMP[8].xy, TEMP[8].xyyy
>687:           TEX TEMP[8].xyz, TEMP[8], SAMP[0], 2D
>688:           MOV TEMP[6].xyz, TEMP[8].xyzx
>689:           MOV TEMP[7].xyz, IMM[0].wzww
>690:         ENDIF
>691:       ENDIF
>692:       DP3 TEMP[8].x, TEMP[3].xyzz, TEMP[3].xyzz
>693:       RSQ TEMP[8].x, TEMP[8].xxxx
>694:       MUL TEMP[4].x, IMM[0].xxxx, TEMP[8].xxxx
>695:       ADD TEMP[8].xyz, TEMP[3].xyzz, -CONST[1].xyzz
>696:       DP3 TEMP[8].x, TEMP[8].xyzz, TEMP[8].xyzz
>697:       RSQ TEMP[9].x, TEMP[8].xxxx
>698:       MUL TEMP[9].x, TEMP[9].xxxx, TEMP[8].xxxx
>699:       CMP TEMP[9].x, -TEMP[8].xxxx, TEMP[9].xxxx, IMM[0].wwww
>700:       RCP TEMP[8].x, CONST[2].xxxx
>701:       MUL TEMP[8].x, TEMP[9].xxxx, TEMP[8].xxxx
>702:       POW TEMP[8].x, TEMP[8].xxxx, IMM[2].yyyy
>703:       RCP TEMP[8].x, TEMP[8].xxxx
>704:       MUL TEMP[8].x, IMM[2].wwww, TEMP[8].xxxx
>705:       ADD TEMP[8].x, IMM[0].zzzz, -TEMP[8].xxxx
>706:       MUL TEMP[4].x, TEMP[4].xxxx, TEMP[8].xxxx
>707:       MOV TEMP[8].xyz, -CONST[0].xyzx
>708:       MUL TEMP[9].x, TEMP[8].yyyy, TEMP[8].yyyy
>709:       ADD TEMP[9].x, IMM[0].zzzz, -TEMP[9].xxxx
>710:       MUL TEMP[9].x, TEMP[9].xxxx, IMM[1].yyyy
>711:       ADD TEMP[9].x, IMM[0].zzzz, -TEMP[9].xxxx
>712:       FSLT TEMP[10].x, TEMP[9].xxxx, IMM[0].wwww
>713:       UIF TEMP[10].xxxx :0
>714:         MOV TEMP[10].xyz, IMM[0].wwww
>715:       ELSE :0
>716:         RSQ TEMP[11].x, TEMP[9].xxxx
>717:         MUL TEMP[11].x, TEMP[11].xxxx, TEMP[9].xxxx
>718:         CMP TEMP[11].x, -TEMP[9].xxxx, TEMP[11].xxxx, IMM[0].wwww
>719:         MAD TEMP[9].x, IMM[1].zzzz, TEMP[8].yyyy, TEMP[11].xxxx
>720:         MUL TEMP[9].xyz, TEMP[9].xxxx, IMM[0].wzww
>721:         MAD TEMP[10].xyz, IMM[1].zzzz, TEMP[8].xyzz, -TEMP[9].xyzz
>722:       ENDIF
>723:       MOV TEMP[8].xyz, -TEMP[10].xyzx
>724:       DP3 TEMP[7].x, TEMP[8].xyzz, TEMP[7].xyzz
>725:       MAX TEMP[7].x, IMM[0].wwww, TEMP[7].xxxx
>726:       MAD TEMP[9].xy, TEMP[3].xzzz, IMM[0].xxxx, IMM[0].xxxx
>727:       MOV TEMP[9].xy, TEMP[9].xyyy
>728:       TEX TEMP[9].x, TEMP[9], SAMP[2], 2D
>729:       FSLT TEMP[9].x, TEMP[3].yyyy, TEMP[9].xxxx
>730:       UIF TEMP[9].xxxx :0
>731:         MUL TEMP[9].xy, TEMP[3].yyyy, TEMP[8].xzzz
>732:         RCP TEMP[10].x, TEMP[8].yyyy
>733:         MUL TEMP[9].xy, TEMP[9].xyyy, TEMP[10].xxxx
>734:         ADD TEMP[9].xy, TEMP[3].xzzz, -TEMP[9].xyyy
>735:         MAD TEMP[9].xy, IMM[4].xxxx, TEMP[9].xyyy, IMM[0].xxxx
>736:         MOV TEMP[9].xy, TEMP[9].xyyy
>737:         TEX TEMP[9].xy, TEMP[9], SAMP[1], 2D
>738:         MUL TEMP[10].x, TEMP[7].xxxx, TEMP[9].xxxx
>739:         MUL TEMP[10].x, TEMP[10].xxxx, IMM[1].xxxx
>740:         MAD TEMP[4].x, TEMP[10].xxxx, TEMP[9].yyyy, TEMP[4].xxxx
>741:       ELSE :0
>742:         ADD TEMP[9].xyz, IMM[4].yyyy, -TEMP[3].xyzz
>743:         RCP TEMP[10].x, TEMP[8].xxxx
>744:         RCP TEMP[10].y, TEMP[8].yyyy
>745:         RCP TEMP[10].z, TEMP[8].zzzz
>746:         MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[10].xyzz
>747:         ADD TEMP[10].xyz, IMM[4].zwzz, -TEMP[3].xyzz
>748:         RCP TEMP[11].x, TEMP[8].xxxx
>749:         RCP TEMP[11].y, TEMP[8].yyyy
>750:         RCP TEMP[11].z, TEMP[8].zzzz
>751:         MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[11].xyzz
>752:         MIN TEMP[11].xyz, TEMP[9].xyzz, TEMP[10].xyzz
>753:         MAX TEMP[9].xyz, TEMP[9].xyzz, TEMP[10].xyzz
>754:         MIN TEMP[10].x, TEMP[9].xxxx, TEMP[9].yyyy
>755:         MIN TEMP[9].x, TEMP[10].xxxx, TEMP[9].zzzz
>756:         MAD TEMP[3].x, TEMP[8].yyyy, TEMP[9].xxxx, TEMP[3].yyyy
>757:         ADD TEMP[3].x, TEMP[3].xxxx, IMM[5].zzzz
>758:         MUL TEMP[3].x, IMM[5].yyyy, TEMP[3].xxxx
>759:         MAX TEMP[8].x, TEMP[11].xxxx, TEMP[11].yyyy
>760:         MAX TEMP[8].x, TEMP[8].xxxx, TEMP[11].zzzz
>761:         ADD TEMP[8].x, TEMP[9].xxxx, -TEMP[8].xxxx
>762:         MAD TEMP[8].x, IMM[5].wwww, TEMP[8].xxxx, IMM[0].zzzz
>763:         RCP TEMP[8].x, TEMP[8].xxxx
>764:         MUL TEMP[3].x, TEMP[3].xxxx, TEMP[8].xxxx
>765:         EX2 TEMP[3].x, TEMP[3].xxxx
>766:         ADD TEMP[3].x, IMM[0].zzzz, TEMP[3].xxxx
>767:         RCP TEMP[3].x, TEMP[3].xxxx
>768:         MUL TEMP[3].x, TEMP[7].xxxx, TEMP[3].xxxx
>769:         MAD TEMP[4].x, TEMP[3].xxxx, IMM[0].xxxx, TEMP[4].xxxx
>770:       ENDIF
>771:       MUL TEMP[2].xyz, TEMP[6].xyzz, TEMP[4].xxxx
>772:     ELSE :0
>773:       DP3 TEMP[3].x, CONST[0].xyzz, TEMP[5].xyzz
>774:       MAX TEMP[3].x, IMM[0].wwww, TEMP[3].xxxx
>775:       POW TEMP[3].x, TEMP[3].xxxx, IMM[6].yyyy
>776:       MOV TEMP[4].xyz, TEMP[5].xyzz
>777:       TEX TEMP[4].xyz, TEMP[4], SAMP[3], CUBE
>778:       MAD TEMP[2].xyz, TEMP[3].xxxx, IMM[7].xyzz, TEMP[4].xyzz
>779:     ENDIF
>780:   ENDIF
>781: ENDIF
>782: FSLT TEMP[3].x, TEMP[5].yyyy, IMM[0].wwww
>783: UIF TEMP[3].xxxx :0
>784:   MUL TEMP[2].xyz, TEMP[2].xyzz, IMM[8].xyzz
>785: ENDIF
>786: MOV TEMP[3].w, IMM[0].zzzz
>787: LRP TEMP[3].xyz, TEMP[0].xxxx, TEMP[1].xyzz, TEMP[2].xyzz
>788: MOV OUT[0], TEMP[3]
>789: END
>; ModuleID = 'tgsi'
>
>define void @main() #0 {
>main_body:
>  %0 = call float @llvm.R600.load.input(i32 0)
>  %1 = call float @llvm.R600.load.input(i32 1)
>  %2 = call float @llvm.R600.load.input(i32 2)
>  %3 = call float @llvm.R600.load.input(i32 3)
>  %4 = fmul float %0, 0x3FE0000000000000
>  %5 = fadd float %4, 0x3FE0000000000000
>  %6 = fmul float %2, 0x3FE0000000000000
>  %7 = fadd float %6, 0x3FE0000000000000
>  %8 = insertelement <4 x float> undef, float %5, i32 0
>  %9 = insertelement <4 x float> %8, float %7, i32 1
>  %10 = insertelement <4 x float> %9, float 0,000000e+00, i32 2
>  %11 = insertelement <4 x float> %10, float 0,000000e+00, i32 3
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = insertelement <4 x float> undef, float %12, i32 0
>  %15 = insertelement <4 x float> %14, float %13, i32 1
>  %16 = insertelement <4 x float> %15, float undef, i32 2
>  %17 = insertelement <4 x float> %16, float undef, i32 3
>  %18 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %17, i32 18, i32 2, i32 2)
>  %19 = extractelement <4 x float> %18, i32 2
>  %20 = extractelement <4 x float> %18, i32 3
>  %21 = fmul float %19, 0x3F747AE140000000
>  %22 = fadd float %21, %5
>  %23 = fmul float %20, 0x3F747AE140000000
>  %24 = fadd float %23, %7
>  %25 = insertelement <4 x float> undef, float %22, i32 0
>  %26 = insertelement <4 x float> %25, float %24, i32 1
>  %27 = insertelement <4 x float> %26, float %19, i32 2
>  %28 = insertelement <4 x float> %27, float %20, i32 3
>  %29 = extractelement <4 x float> %28, i32 0
>  %30 = extractelement <4 x float> %28, i32 1
>  %31 = insertelement <4 x float> undef, float %29, i32 0
>  %32 = insertelement <4 x float> %31, float %30, i32 1
>  %33 = insertelement <4 x float> %32, float undef, i32 2
>  %34 = insertelement <4 x float> %33, float undef, i32 3
>  %35 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %34, i32 18, i32 2, i32 2)
>  %36 = extractelement <4 x float> %35, i32 2
>  %37 = extractelement <4 x float> %35, i32 3
>  %38 = fmul float %36, 0x3F747AE140000000
>  %39 = fadd float %38, %22
>  %40 = fmul float %37, 0x3F747AE140000000
>  %41 = fadd float %40, %24
>  %42 = insertelement <4 x float> undef, float %39, i32 0
>  %43 = insertelement <4 x float> %42, float %41, i32 1
>  %44 = insertelement <4 x float> %43, float %36, i32 2
>  %45 = insertelement <4 x float> %44, float %37, i32 3
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = insertelement <4 x float> undef, float %46, i32 0
>  %49 = insertelement <4 x float> %48, float %47, i32 1
>  %50 = insertelement <4 x float> %49, float undef, i32 2
>  %51 = insertelement <4 x float> %50, float undef, i32 3
>  %52 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %51, i32 18, i32 2, i32 2)
>  %53 = extractelement <4 x float> %52, i32 2
>  %54 = extractelement <4 x float> %52, i32 3
>  %55 = fmul float %53, 0x3F747AE140000000
>  %56 = fadd float %55, %39
>  %57 = fmul float %54, 0x3F747AE140000000
>  %58 = fadd float %57, %41
>  %59 = insertelement <4 x float> undef, float %56, i32 0
>  %60 = insertelement <4 x float> %59, float %58, i32 1
>  %61 = insertelement <4 x float> %60, float %53, i32 2
>  %62 = insertelement <4 x float> %61, float %54, i32 3
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = extractelement <4 x float> %62, i32 1
>  %65 = insertelement <4 x float> undef, float %63, i32 0
>  %66 = insertelement <4 x float> %65, float %64, i32 1
>  %67 = insertelement <4 x float> %66, float undef, i32 2
>  %68 = insertelement <4 x float> %67, float undef, i32 3
>  %69 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %68, i32 18, i32 2, i32 2)
>  %70 = extractelement <4 x float> %69, i32 2
>  %71 = extractelement <4 x float> %69, i32 3
>  %72 = fmul float %70, 0x3F747AE140000000
>  %73 = fadd float %72, %56
>  %74 = fmul float %71, 0x3F747AE140000000
>  %75 = fadd float %74, %58
>  %76 = insertelement <4 x float> undef, float %73, i32 0
>  %77 = insertelement <4 x float> %76, float %75, i32 1
>  %78 = insertelement <4 x float> %77, float %70, i32 2
>  %79 = insertelement <4 x float> %78, float %71, i32 3
>  %80 = extractelement <4 x float> %79, i32 0
>  %81 = extractelement <4 x float> %79, i32 1
>  %82 = insertelement <4 x float> undef, float %80, i32 0
>  %83 = insertelement <4 x float> %82, float %81, i32 1
>  %84 = insertelement <4 x float> %83, float undef, i32 2
>  %85 = insertelement <4 x float> %84, float undef, i32 3
>  %86 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %85, i32 18, i32 2, i32 2)
>  %87 = extractelement <4 x float> %86, i32 2
>  %88 = extractelement <4 x float> %86, i32 3
>  %89 = fmul float %87, 0x3F747AE140000000
>  %90 = fadd float %89, %73
>  %91 = fmul float %88, 0x3F747AE140000000
>  %92 = fadd float %91, %75
>  %93 = insertelement <4 x float> undef, float %90, i32 0
>  %94 = insertelement <4 x float> %93, float %92, i32 1
>  %95 = insertelement <4 x float> %94, float 0,000000e+00, i32 2
>  %96 = insertelement <4 x float> %95, float 0,000000e+00, i32 3
>  %97 = extractelement <4 x float> %96, i32 0
>  %98 = extractelement <4 x float> %96, i32 1
>  %99 = insertelement <4 x float> undef, float %97, i32 0
>  %100 = insertelement <4 x float> %99, float %98, i32 1
>  %101 = insertelement <4 x float> %100, float undef, i32 2
>  %102 = insertelement <4 x float> %101, float undef, i32 3
>  %103 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %102, i32 18, i32 2, i32 2)
>  %104 = extractelement <4 x float> %103, i32 2
>  %105 = extractelement <4 x float> %103, i32 3
>  %106 = insertelement <4 x float> undef, float %104, i32 0
>  %107 = insertelement <4 x float> %106, float %105, i32 1
>  %108 = insertelement <4 x float> %107, float 0,000000e+00, i32 2
>  %109 = insertelement <4 x float> %108, float 0,000000e+00, i32 3
>  %110 = insertelement <4 x float> undef, float %104, i32 0
>  %111 = insertelement <4 x float> %110, float %105, i32 1
>  %112 = insertelement <4 x float> %111, float 0,000000e+00, i32 2
>  %113 = insertelement <4 x float> %112, float 0,000000e+00, i32 3
>  %114 = call float @llvm.AMDGPU.dp4(<4 x float> %109, <4 x float> %113)
>  %115 = fsub float -0,000000e+00, %114
>  %116 = fadd float 0x3FF0000000000000, %115
>  %117 = call float @llvm.AMDGPU.rsq(float %116)
>  %118 = fmul float %117, %116
>  %119 = fsub float -0,000000e+00, %116
>  %120 = fcmp ult float %119, 0,000000e+00
>  %121 = select i1 %120, float %118, float 0,000000e+00
>  %122 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = fsub float -0,000000e+00, %123
>  %125 = fadd float %0, %124
>  %126 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %127 = extractelement <4 x float> %126, i32 1
>  %128 = fsub float -0,000000e+00, %127
>  %129 = fadd float %1, %128
>  %130 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %131 = extractelement <4 x float> %130, i32 2
>  %132 = fsub float -0,000000e+00, %131
>  %133 = fadd float %2, %132
>  %134 = insertelement <4 x float> undef, float %125, i32 0
>  %135 = insertelement <4 x float> %134, float %129, i32 1
>  %136 = insertelement <4 x float> %135, float %133, i32 2
>  %137 = insertelement <4 x float> %136, float 0,000000e+00, i32 3
>  %138 = insertelement <4 x float> undef, float %125, i32 0
>  %139 = insertelement <4 x float> %138, float %129, i32 1
>  %140 = insertelement <4 x float> %139, float %133, i32 2
>  %141 = insertelement <4 x float> %140, float 0,000000e+00, i32 3
>  %142 = call float @llvm.AMDGPU.dp4(<4 x float> %137, <4 x float> %141)
>  %143 = call float @llvm.AMDGPU.rsq(float %142)
>  %144 = fmul float %125, %143
>  %145 = fmul float %129, %143
>  %146 = fmul float %133, %143
>  %147 = insertelement <4 x float> undef, float %104, i32 0
>  %148 = insertelement <4 x float> %147, float %121, i32 1
>  %149 = insertelement <4 x float> %148, float %105, i32 2
>  %150 = insertelement <4 x float> %149, float 0,000000e+00, i32 3
>  %151 = insertelement <4 x float> undef, float %144, i32 0
>  %152 = insertelement <4 x float> %151, float %145, i32 1
>  %153 = insertelement <4 x float> %152, float %146, i32 2
>  %154 = insertelement <4 x float> %153, float 0,000000e+00, i32 3
>  %155 = call float @llvm.AMDGPU.dp4(<4 x float> %150, <4 x float> %154)
>  %156 = fmul float %155, %104
>  %157 = fmul float %155, %121
>  %158 = fmul float %155, %105
>  %159 = fmul float 0x4000000000000000, %156
>  %160 = fmul float 0x4000000000000000, %157
>  %161 = fmul float 0x4000000000000000, %158
>  %162 = fsub float -0,000000e+00, %159
>  %163 = fadd float %144, %162
>  %164 = fsub float -0,000000e+00, %160
>  %165 = fadd float %145, %164
>  %166 = fsub float -0,000000e+00, %161
>  %167 = fadd float %146, %166
>  %168 = insertelement <4 x float> undef, float %104, i32 0
>  %169 = insertelement <4 x float> %168, float %121, i32 1
>  %170 = insertelement <4 x float> %169, float %105, i32 2
>  %171 = insertelement <4 x float> %170, float 0,000000e+00, i32 3
>  %172 = insertelement <4 x float> undef, float %144, i32 0
>  %173 = insertelement <4 x float> %172, float %145, i32 1
>  %174 = insertelement <4 x float> %173, float %146, i32 2
>  %175 = insertelement <4 x float> %174, float 0,000000e+00, i32 3
>  %176 = call float @llvm.AMDGPU.dp4(<4 x float> %171, <4 x float> %175)
>  %177 = fmul float %176, %176
>  %178 = fsub float -0,000000e+00, %177
>  %179 = fadd float 0x3FF0000000000000, %178
>  %180 = fmul float %179, 0x3FE2024E20000000
>  %181 = fsub float -0,000000e+00, %180
>  %182 = fadd float 0x3FF0000000000000, %181
>  %183 = fcmp olt float %182, 0,000000e+00
>  %184 = sext i1 %183 to i32
>  %185 = bitcast i32 %184 to float
>  %186 = bitcast float %185 to i32
>  %187 = icmp ne i32 %186, 0
>  br i1 %187, label %ENDIF, label %ELSE
>
>ELSE:                                             ; preds = %main_body
>  %188 = call float @llvm.AMDGPU.rsq(float %182)
>  %189 = fmul float %188, %182
>  %190 = fsub float -0,000000e+00, %182
>  %191 = fcmp ult float %190, 0,000000e+00
>  %192 = select i1 %191, float %189, float 0,000000e+00
>  %193 = fmul float 0x3FE8018960000000, %176
>  %194 = fadd float %193, %192
>  %195 = fmul float %194, %104
>  %196 = fmul float %194, %121
>  %197 = fmul float %194, %105
>  %198 = fsub float -0,000000e+00, %195
>  %199 = fmul float 0x3FE8018960000000, %144
>  %200 = fadd float %199, %198
>  %201 = fsub float -0,000000e+00, %196
>  %202 = fmul float 0x3FE8018960000000, %145
>  %203 = fadd float %202, %201
>  %204 = fsub float -0,000000e+00, %197
>  %205 = fmul float 0x3FE8018960000000, %146
>  %206 = fadd float %205, %204
>  br label %ENDIF
>
>ENDIF:                                            ; preds = %main_body, %ELSE
>  %temp20.0 = phi float [ %200, %ELSE ], [ 0,000000e+00, %main_body ]
>  %temp21.0 = phi float [ %203, %ELSE ], [ 0,000000e+00, %main_body ]
>  %temp22.0 = phi float [ %206, %ELSE ], [ 0,000000e+00, %main_body ]
>  %207 = fsub float -0,000000e+00, %144
>  %208 = fsub float -0,000000e+00, %145
>  %209 = fsub float -0,000000e+00, %146
>  %210 = insertelement <4 x float> undef, float %104, i32 0
>  %211 = insertelement <4 x float> %210, float %121, i32 1
>  %212 = insertelement <4 x float> %211, float %105, i32 2
>  %213 = insertelement <4 x float> %212, float 0,000000e+00, i32 3
>  %214 = insertelement <4 x float> undef, float %207, i32 0
>  %215 = insertelement <4 x float> %214, float %208, i32 1
>  %216 = insertelement <4 x float> %215, float %209, i32 2
>  %217 = insertelement <4 x float> %216, float 0,000000e+00, i32 3
>  %218 = call float @llvm.AMDGPU.dp4(<4 x float> %213, <4 x float> %217)
>  %219 = fsub float -0,000000e+00, %218
>  %220 = fadd float 0x3FF0000000000000, %219
>  %221 = call float @llvm.pow.f32(float %220, float 0x4008000000000000)
>  %222 = call float @llvm.AMDGPU.lrp(float %221, float 0x3FF0000000000000, float 0x3FD0000000000000)
>  %223 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %224 = extractelement <4 x float> %223, i32 0
>  %225 = fsub float -0,000000e+00, %224
>  %226 = fadd float %0, %225
>  %227 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %228 = extractelement <4 x float> %227, i32 1
>  %229 = fsub float -0,000000e+00, %228
>  %230 = fadd float %1, %229
>  %231 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %232 = extractelement <4 x float> %231, i32 2
>  %233 = fsub float -0,000000e+00, %232
>  %234 = fadd float %2, %233
>  %235 = insertelement <4 x float> undef, float %163, i32 0
>  %236 = insertelement <4 x float> %235, float %165, i32 1
>  %237 = insertelement <4 x float> %236, float %167, i32 2
>  %238 = insertelement <4 x float> %237, float 0,000000e+00, i32 3
>  %239 = insertelement <4 x float> undef, float %163, i32 0
>  %240 = insertelement <4 x float> %239, float %165, i32 1
>  %241 = insertelement <4 x float> %240, float %167, i32 2
>  %242 = insertelement <4 x float> %241, float 0,000000e+00, i32 3
>  %243 = call float @llvm.AMDGPU.dp4(<4 x float> %238, <4 x float> %242)
>  %244 = insertelement <4 x float> undef, float %226, i32 0
>  %245 = insertelement <4 x float> %244, float %230, i32 1
>  %246 = insertelement <4 x float> %245, float %234, i32 2
>  %247 = insertelement <4 x float> %246, float 0,000000e+00, i32 3
>  %248 = insertelement <4 x float> undef, float %163, i32 0
>  %249 = insertelement <4 x float> %248, float %165, i32 1
>  %250 = insertelement <4 x float> %249, float %167, i32 2
>  %251 = insertelement <4 x float> %250, float 0,000000e+00, i32 3
>  %252 = call float @llvm.AMDGPU.dp4(<4 x float> %247, <4 x float> %251)
>  %253 = fmul float 0x4000000000000000, %252
>  %254 = fmul float 0x4010000000000000, %243
>  %255 = insertelement <4 x float> undef, float %226, i32 0
>  %256 = insertelement <4 x float> %255, float %230, i32 1
>  %257 = insertelement <4 x float> %256, float %234, i32 2
>  %258 = insertelement <4 x float> %257, float 0,000000e+00, i32 3
>  %259 = insertelement <4 x float> undef, float %226, i32 0
>  %260 = insertelement <4 x float> %259, float %230, i32 1
>  %261 = insertelement <4 x float> %260, float %234, i32 2
>  %262 = insertelement <4 x float> %261, float 0,000000e+00, i32 3
>  %263 = call float @llvm.AMDGPU.dp4(<4 x float> %258, <4 x float> %262)
>  %264 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %265 = extractelement <4 x float> %264, i32 0
>  %266 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %267 = extractelement <4 x float> %266, i32 0
>  %268 = fmul float %265, %267
>  %269 = fsub float -0,000000e+00, %268
>  %270 = fadd float %263, %269
>  %271 = fmul float %254, %270
>  %272 = fsub float -0,000000e+00, %271
>  %273 = fmul float %253, %253
>  %274 = fadd float %273, %272
>  %275 = fcmp olt float 0,000000e+00, %274
>  %276 = sext i1 %275 to i32
>  %277 = bitcast i32 %276 to float
>  %278 = bitcast float %277 to i32
>  %279 = icmp ne i32 %278, 0
>  br i1 %279, label %IF49, label %ENDIF48
>
>IF49:                                             ; preds = %ENDIF
>  %280 = call float @llvm.AMDGPU.rsq(float %274)
>  %281 = fmul float %280, %274
>  %282 = fsub float -0,000000e+00, %274
>  %283 = fcmp ult float %282, 0,000000e+00
>  %284 = select i1 %283, float %281, float 0,000000e+00
>  %285 = fsub float -0,000000e+00, %253
>  %286 = fsub float -0,000000e+00, %284
>  %287 = fadd float %285, %286
>  %288 = fmul float 0x4000000000000000, %243
>  %289 = fdiv float 0x3FF0000000000000, %288
>  %290 = fmul float %287, %289
>  %291 = fcmp olt float 0,000000e+00, %290
>  %292 = sext i1 %291 to i32
>  %293 = bitcast i32 %292 to float
>  %294 = bitcast float %293 to i32
>  %295 = icmp ne i32 %294, 0
>  %. = select i1 %295, float 0,000000e+00, float 0xFFFFFFFFE0000000
>  br label %ENDIF48
>
>ENDIF48:                                          ; preds = %ENDIF, %IF49
>  %temp12.0 = phi float [ %290, %IF49 ], [ %274, %ENDIF ]
>  %temp4.0 = phi float [ %., %IF49 ], [ 0xFFFFFFFFE0000000, %ENDIF ]
>  %296 = bitcast float %temp4.0 to i32
>  %297 = icmp ne i32 %296, 0
>  %.temp12.0 = select i1 %297, float 0x412E848000000000, float %temp12.0
>  %298 = fcmp olt float %.temp12.0, 0x412E848000000000
>  %299 = sext i1 %298 to i32
>  %300 = bitcast i32 %299 to float
>  %301 = bitcast float %300 to i32
>  %302 = icmp ne i32 %301, 0
>  br i1 %302, label %IF58, label %ELSE59
>
>IF58:                                             ; preds = %ENDIF48
>  %303 = fmul float %163, %.temp12.0
>  %304 = fadd float %303, %0
>  %305 = fmul float %165, %.temp12.0
>  %306 = fadd float %305, %1
>  %307 = fmul float %167, %.temp12.0
>  %308 = fadd float %307, %2
>  %309 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %310 = extractelement <4 x float> %309, i32 0
>  %311 = fadd float 0x3FF0000000000000, %310
>  %312 = call float @fabs(float %304)
>  %313 = fsub float -0,000000e+00, %312
>  %314 = fadd float %311, %313
>  %315 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %316 = extractelement <4 x float> %315, i32 0
>  %317 = fdiv float 0x3FF0000000000000, %316
>  %318 = fmul float %314, %317
>  %319 = call float @llvm.pow.f32(float %318, float 0x4008000000000000)
>  %320 = fdiv float 0x3FF0000000000000, %319
>  %321 = fmul float 0x3FECCCCCC0000000, %320
>  %322 = fsub float -0,000000e+00, %321
>  %323 = fadd float 0x3FF0000000000000, %322
>  %324 = fmul float 0x3FE0000000000000, %323
>  %325 = fmul float 0x3FE0000000000000, %323
>  %326 = fmul float 0x3FE0000000000000, %323
>  %327 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %328 = extractelement <4 x float> %327, i32 0
>  %329 = fadd float 0x3FF0000000000000, %328
>  %330 = call float @fabs(float %308)
>  %331 = fsub float -0,000000e+00, %330
>  %332 = fadd float %329, %331
>  %333 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %334 = extractelement <4 x float> %333, i32 0
>  %335 = fdiv float 0x3FF0000000000000, %334
>  %336 = fmul float %332, %335
>  %337 = call float @llvm.pow.f32(float %336, float 0x4008000000000000)
>  %338 = fdiv float 0x3FF0000000000000, %337
>  %339 = fmul float 0x3FECCCCCC0000000, %338
>  %340 = fsub float -0,000000e+00, %339
>  %341 = fadd float 0x3FF0000000000000, %340
>  %342 = fmul float %324, %341
>  %343 = fmul float %325, %341
>  %344 = fmul float %326, %341
>  %345 = fadd float %306, 0x3FF0000000000000
>  %346 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %347 = extractelement <4 x float> %346, i32 0
>  %348 = fadd float %345, %347
>  %349 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %350 = extractelement <4 x float> %349, i32 0
>  %351 = fdiv float 0x3FF0000000000000, %350
>  %352 = fmul float %348, %351
>  %353 = call float @llvm.pow.f32(float %352, float 0x4008000000000000)
>  %354 = fdiv float 0x3FF0000000000000, %353
>  %355 = fmul float 0x3FECCCCCC0000000, %354
>  %356 = fsub float -0,000000e+00, %355
>  %357 = fadd float 0x3FF0000000000000, %356
>  %358 = fmul float %342, %357
>  %359 = fmul float %343, %357
>  %360 = fmul float %344, %357
>  %361 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %362 = extractelement <4 x float> %361, i32 0
>  %363 = fsub float -0,000000e+00, %362
>  %364 = fadd float %304, %363
>  %365 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %366 = extractelement <4 x float> %365, i32 1
>  %367 = fsub float -0,000000e+00, %366
>  %368 = fadd float %306, %367
>  %369 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %370 = extractelement <4 x float> %369, i32 2
>  %371 = fsub float -0,000000e+00, %370
>  %372 = fadd float %308, %371
>  %373 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %374 = extractelement <4 x float> %373, i32 0
>  %375 = fdiv float 0x3FF0000000000000, %374
>  %376 = fmul float %364, %375
>  %377 = fmul float %368, %375
>  %378 = fmul float %372, %375
>  %379 = load <4 x float> addrspace(8)* null
>  %380 = extractelement <4 x float> %379, i32 0
>  %381 = fsub float -0,000000e+00, %380
>  %382 = load <4 x float> addrspace(8)* null
>  %383 = extractelement <4 x float> %382, i32 1
>  %384 = fsub float -0,000000e+00, %383
>  %385 = load <4 x float> addrspace(8)* null
>  %386 = extractelement <4 x float> %385, i32 2
>  %387 = fsub float -0,000000e+00, %386
>  %388 = fmul float %384, %384
>  %389 = fsub float -0,000000e+00, %388
>  %390 = fadd float 0x3FF0000000000000, %389
>  %391 = fmul float %390, 0x3FE2024E20000000
>  %392 = fsub float -0,000000e+00, %391
>  %393 = fadd float 0x3FF0000000000000, %392
>  %394 = fcmp olt float %393, 0,000000e+00
>  %395 = sext i1 %394 to i32
>  %396 = bitcast i32 %395 to float
>  %397 = bitcast float %396 to i32
>  %398 = icmp ne i32 %397, 0
>  br i1 %398, label %ENDIF60, label %ELSE62
>
>ELSE59:                                           ; preds = %ENDIF48
>  %399 = fcmp olt float %165, 0,000000e+00
>  %400 = sext i1 %399 to i32
>  %401 = bitcast i32 %400 to float
>  %402 = bitcast float %401 to i32
>  %403 = icmp ne i32 %402, 0
>  %404 = fsub float -0,000000e+00, %0
>  %405 = fadd float 0xBFF0000000000000, %404
>  %406 = fsub float -0,000000e+00, %1
>  %407 = fadd float 0xBFF0000000000000, %406
>  %408 = fsub float -0,000000e+00, %2
>  %409 = fadd float 0xBFF0000000000000, %408
>  %410 = fdiv float 0x3FF0000000000000, %163
>  %411 = fdiv float 0x3FF0000000000000, %165
>  %412 = fdiv float 0x3FF0000000000000, %167
>  %413 = fmul float %405, %410
>  %414 = fmul float %407, %411
>  %415 = fmul float %409, %412
>  %416 = fsub float -0,000000e+00, %0
>  %417 = fadd float 0x3FF0000000000000, %416
>  %418 = fsub float -0,000000e+00, %1
>  %419 = fadd float 0x4000000000000000, %418
>  %420 = fsub float -0,000000e+00, %2
>  %421 = fadd float 0x3FF0000000000000, %420
>  %422 = fdiv float 0x3FF0000000000000, %163
>  %423 = fdiv float 0x3FF0000000000000, %165
>  %424 = fdiv float 0x3FF0000000000000, %167
>  %425 = fmul float %417, %422
>  %426 = fmul float %419, %423
>  %427 = fmul float %421, %424
>  %428 = fcmp uge float %413, %425
>  %429 = select i1 %428, float %413, float %425
>  %430 = fcmp uge float %414, %426
>  %431 = select i1 %430, float %414, float %426
>  %432 = fcmp uge float %415, %427
>  %433 = select i1 %432, float %415, float %427
>  %434 = fcmp uge float %429, %431
>  %435 = select i1 %434, float %431, float %429
>  %436 = fcmp uge float %435, %433
>  %437 = select i1 %436, float %433, float %435
>  %438 = fmul float %163, %437
>  %439 = fadd float %438, %0
>  %440 = fmul float %165, %437
>  %441 = fadd float %440, %1
>  %442 = fmul float %167, %437
>  %443 = fadd float %442, %2
>  br i1 %403, label %IF67, label %ELSE68
>
>ENDIF57:                                          ; preds = %ENDIF93, %ELSE83, %ENDIF78, %ENDIF63
>  %temp6.0 = phi float [ %533, %ENDIF63 ], [ %819, %ENDIF78 ], [ %1155, %ENDIF93 ], [ %880, %ELSE83 ]
>  %temp5.0 = phi float [ %532, %ENDIF63 ], [ %818, %ENDIF78 ], [ %1154, %ENDIF93 ], [ %878, %ELSE83 ]
>  %temp4.2 = phi float [ %531, %ENDIF63 ], [ %817, %ENDIF78 ], [ %1153, %ENDIF93 ], [ %876, %ELSE83 ]
>  %temp34.0 = phi float [ %temp34.1, %ENDIF63 ], [ %695, %ENDIF78 ], [ %1031, %ENDIF93 ], [ 0,000000e+00, %ELSE83 ]
>  %temp38.0 = phi float [ 0,000000e+00, %ENDIF63 ], [ %temp38.3, %ENDIF78 ], [ %temp38.6, %ENDIF93 ], [ 0,000000e+00, %ELSE83 ]
>  %444 = fcmp olt float %165, 0,000000e+00
>  %445 = sext i1 %444 to i32
>  %446 = bitcast i32 %445 to float
>  %447 = bitcast float %446 to i32
>  %448 = icmp ne i32 %447, 0
>  br i1 %448, label %IF97, label %ENDIF96
>
>ELSE62:                                           ; preds = %IF58
>  %449 = call float @llvm.AMDGPU.rsq(float %393)
>  %450 = fmul float %449, %393
>  %451 = fsub float -0,000000e+00, %393
>  %452 = fcmp ult float %451, 0,000000e+00
>  %453 = select i1 %452, float %450, float 0,000000e+00
>  %454 = fmul float 0x3FE8018960000000, %384
>  %455 = fadd float %454, %453
>  %456 = fmul float %455, 0,000000e+00
>  %457 = fmul float %455, 0x3FF0000000000000
>  %458 = fmul float %455, 0,000000e+00
>  %459 = fsub float -0,000000e+00, %456
>  %460 = fmul float 0x3FE8018960000000, %381
>  %461 = fadd float %460, %459
>  %462 = fsub float -0,000000e+00, %457
>  %463 = fmul float 0x3FE8018960000000, %384
>  %464 = fadd float %463, %462
>  %465 = fsub float -0,000000e+00, %458
>  %466 = fmul float 0x3FE8018960000000, %387
>  %467 = fadd float %466, %465
>  br label %ENDIF60
>
>ENDIF60:                                          ; preds = %IF58, %ELSE62
>  %temp32.0 = phi float [ %461, %ELSE62 ], [ 0,000000e+00, %IF58 ]
>  %temp33.0 = phi float [ %464, %ELSE62 ], [ 0,000000e+00, %IF58 ]
>  %temp34.1 = phi float [ %467, %ELSE62 ], [ 0,000000e+00, %IF58 ]
>  %468 = fsub float -0,000000e+00, %temp32.0
>  %469 = fsub float -0,000000e+00, %temp33.0
>  %470 = fsub float -0,000000e+00, %temp34.1
>  %471 = insertelement <4 x float> undef, float %468, i32 0
>  %472 = insertelement <4 x float> %471, float %469, i32 1
>  %473 = insertelement <4 x float> %472, float %470, i32 2
>  %474 = insertelement <4 x float> %473, float 0,000000e+00, i32 3
>  %475 = insertelement <4 x float> undef, float %376, i32 0
>  %476 = insertelement <4 x float> %475, float %377, i32 1
>  %477 = insertelement <4 x float> %476, float %378, i32 2
>  %478 = insertelement <4 x float> %477, float 0,000000e+00, i32 3
>  %479 = call float @llvm.AMDGPU.dp4(<4 x float> %474, <4 x float> %478)
>  %480 = fcmp uge float 0,000000e+00, %479
>  %481 = select i1 %480, float 0,000000e+00, float %479
>  %482 = fmul float %481, 0x3FE0000000000000
>  %483 = fmul float %304, 0x3FE0000000000000
>  %484 = fadd float %483, 0x3FE0000000000000
>  %485 = fmul float %308, 0x3FE0000000000000
>  %486 = fadd float %485, 0x3FE0000000000000
>  %487 = insertelement <4 x float> undef, float %484, i32 0
>  %488 = insertelement <4 x float> %487, float %486, i32 1
>  %489 = insertelement <4 x float> %488, float %387, i32 2
>  %490 = insertelement <4 x float> %489, float 0,000000e+00, i32 3
>  %491 = extractelement <4 x float> %490, i32 0
>  %492 = extractelement <4 x float> %490, i32 1
>  %493 = insertelement <4 x float> undef, float %491, i32 0
>  %494 = insertelement <4 x float> %493, float %492, i32 1
>  %495 = insertelement <4 x float> %494, float undef, i32 2
>  %496 = insertelement <4 x float> %495, float undef, i32 3
>  %497 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %496, i32 18, i32 2, i32 2)
>  %498 = extractelement <4 x float> %497, i32 0
>  %499 = fcmp olt float %306, %498
>  %500 = sext i1 %499 to i32
>  %501 = bitcast i32 %500 to float
>  %502 = bitcast float %501 to i32
>  %503 = icmp ne i32 %502, 0
>  br i1 %503, label %IF64, label %ENDIF63
>
>IF64:                                             ; preds = %ENDIF60
>  %504 = fmul float %306, %temp32.0
>  %505 = fmul float %306, %temp34.1
>  %506 = fdiv float 0x3FF0000000000000, %temp33.0
>  %507 = fmul float %504, %506
>  %508 = fmul float %505, %506
>  %509 = fsub float -0,000000e+00, %507
>  %510 = fadd float %304, %509
>  %511 = fsub float -0,000000e+00, %508
>  %512 = fadd float %308, %511
>  %513 = fmul float 0x3FD8000000000000, %510
>  %514 = fadd float %513, 0x3FE0000000000000
>  %515 = fmul float 0x3FD8000000000000, %512
>  %516 = fadd float %515, 0x3FE0000000000000
>  %517 = insertelement <4 x float> undef, float %514, i32 0
>  %518 = insertelement <4 x float> %517, float %516, i32 1
>  %519 = insertelement <4 x float> %518, float %308, i32 2
>  %520 = insertelement <4 x float> %519, float %88, i32 3
>  %521 = extractelement <4 x float> %520, i32 0
>  %522 = extractelement <4 x float> %520, i32 1
>  %523 = insertelement <4 x float> undef, float %521, i32 0
>  %524 = insertelement <4 x float> %523, float %522, i32 1
>  %525 = insertelement <4 x float> %524, float undef, i32 2
>  %526 = insertelement <4 x float> %525, float undef, i32 3
>  %527 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %526, i32 17, i32 1, i32 2)
>  %528 = extractelement <4 x float> %527, i32 0
>  %529 = fmul float %528, 0x4010000000000000
>  %530 = fmul float %482, %529
>  br label %ENDIF63
>
>ENDIF63:                                          ; preds = %ENDIF60, %IF64
>  %temp16.0 = phi float [ %530, %IF64 ], [ %482, %ENDIF60 ]
>  %531 = fadd float %358, %temp16.0
>  %532 = fadd float %359, %temp16.0
>  %533 = fadd float %360, %temp16.0
>  br label %ENDIF57
>
>IF67:                                             ; preds = %ELSE59
>  %534 = call float @fabs(float %439)
>  %535 = fcmp olt float 0x3FEFF7CEE0000000, %534
>  %536 = sext i1 %535 to i32
>  %537 = bitcast i32 %536 to float
>  %538 = bitcast float %537 to i32
>  %539 = icmp ne i32 %538, 0
>  br i1 %539, label %IF70, label %ELSE71
>
>ELSE68:                                           ; preds = %ELSE59
>  %540 = fcmp olt float %441, 0x3FC5555560000000
>  %541 = sext i1 %540 to i32
>  %542 = bitcast i32 %541 to float
>  %543 = bitcast float %542 to i32
>  %544 = icmp ne i32 %543, 0
>  br i1 %544, label %IF82, label %ELSE83
>
>IF70:                                             ; preds = %IF67
>  %545 = fmul float %441, 0x3FE0000000000000
>  %546 = fadd float %545, 0x3FF0000000000000
>  %547 = fmul float %443, 0x3FE0000000000000
>  %548 = fadd float %547, 0x3FE0000000000000
>  %549 = insertelement <4 x float> undef, float %546, i32 0
>  %550 = insertelement <4 x float> %549, float %548, i32 1
>  %551 = insertelement <4 x float> %550, float %424, i32 2
>  %552 = insertelement <4 x float> %551, float 0,000000e+00, i32 3
>  %553 = extractelement <4 x float> %552, i32 0
>  %554 = extractelement <4 x float> %552, i32 1
>  %555 = insertelement <4 x float> undef, float %553, i32 0
>  %556 = insertelement <4 x float> %555, float %554, i32 1
>  %557 = insertelement <4 x float> %556, float undef, i32 2
>  %558 = insertelement <4 x float> %557, float undef, i32 3
>  %559 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %558, i32 16, i32 0, i32 2)
>  %560 = extractelement <4 x float> %559, i32 0
>  %561 = extractelement <4 x float> %559, i32 1
>  %562 = extractelement <4 x float> %559, i32 2
>  %563 = fsub float -0,000000e+00, %439
>  br label %ENDIF69
>
>ELSE71:                                           ; preds = %IF67
>  %564 = call float @fabs(float %443)
>  %565 = fcmp olt float 0x3FEFF7CEE0000000, %564
>  %566 = sext i1 %565 to i32
>  %567 = bitcast i32 %566 to float
>  %568 = bitcast float %567 to i32
>  %569 = icmp ne i32 %568, 0
>  br i1 %569, label %IF73, label %ELSE74
>
>ENDIF69:                                          ; preds = %IF73, %ELSE74, %IF70
>  %temp24.0 = phi float [ %560, %IF70 ], [ %652, %IF73 ], [ %671, %ELSE74 ]
>  %temp25.0 = phi float [ %561, %IF70 ], [ %653, %IF73 ], [ %672, %ELSE74 ]
>  %temp26.0 = phi float [ %562, %IF70 ], [ %654, %IF73 ], [ %673, %ELSE74 ]
>  %temp28.0 = phi float [ %563, %IF70 ], [ 0,000000e+00, %ELSE74 ], [ 0,000000e+00, %IF73 ]
>  %temp29.0 = phi float [ 0,000000e+00, %IF70 ], [ 0,000000e+00, %IF73 ], [ 0x3FF0000000000000, %ELSE74 ]
>  %temp30.0 = phi float [ 0,000000e+00, %IF70 ], [ %655, %IF73 ], [ 0,000000e+00, %ELSE74 ]
>  %570 = insertelement <4 x float> undef, float %439, i32 0
>  %571 = insertelement <4 x float> %570, float %441, i32 1
>  %572 = insertelement <4 x float> %571, float %443, i32 2
>  %573 = insertelement <4 x float> %572, float 0,000000e+00, i32 3
>  %574 = insertelement <4 x float> undef, float %439, i32 0
>  %575 = insertelement <4 x float> %574, float %441, i32 1
>  %576 = insertelement <4 x float> %575, float %443, i32 2
>  %577 = insertelement <4 x float> %576, float 0,000000e+00, i32 3
>  %578 = call float @llvm.AMDGPU.dp4(<4 x float> %573, <4 x float> %577)
>  %579 = call float @llvm.AMDGPU.rsq(float %578)
>  %580 = fmul float 0x3FE0000000000000, %579
>  %581 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %582 = extractelement <4 x float> %581, i32 0
>  %583 = fsub float -0,000000e+00, %582
>  %584 = fadd float %439, %583
>  %585 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %586 = extractelement <4 x float> %585, i32 1
>  %587 = fsub float -0,000000e+00, %586
>  %588 = fadd float %441, %587
>  %589 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %590 = extractelement <4 x float> %589, i32 2
>  %591 = fsub float -0,000000e+00, %590
>  %592 = fadd float %443, %591
>  %593 = insertelement <4 x float> undef, float %584, i32 0
>  %594 = insertelement <4 x float> %593, float %588, i32 1
>  %595 = insertelement <4 x float> %594, float %592, i32 2
>  %596 = insertelement <4 x float> %595, float 0,000000e+00, i32 3
>  %597 = insertelement <4 x float> undef, float %584, i32 0
>  %598 = insertelement <4 x float> %597, float %588, i32 1
>  %599 = insertelement <4 x float> %598, float %592, i32 2
>  %600 = insertelement <4 x float> %599, float 0,000000e+00, i32 3
>  %601 = call float @llvm.AMDGPU.dp4(<4 x float> %596, <4 x float> %600)
>  %602 = call float @llvm.AMDGPU.rsq(float %601)
>  %603 = fmul float %602, %601
>  %604 = fsub float -0,000000e+00, %601
>  %605 = fcmp ult float %604, 0,000000e+00
>  %606 = select i1 %605, float %603, float 0,000000e+00
>  %607 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %608 = extractelement <4 x float> %607, i32 0
>  %609 = fdiv float 0x3FF0000000000000, %608
>  %610 = fmul float %606, %609
>  %611 = call float @llvm.pow.f32(float %610, float 0x4010000000000000)
>  %612 = fdiv float 0x3FF0000000000000, %611
>  %613 = fmul float 0x3FECCCCCC0000000, %612
>  %614 = fsub float -0,000000e+00, %613
>  %615 = fadd float 0x3FF0000000000000, %614
>  %616 = fmul float %580, %615
>  %617 = load <4 x float> addrspace(8)* null
>  %618 = extractelement <4 x float> %617, i32 0
>  %619 = fsub float -0,000000e+00, %618
>  %620 = load <4 x float> addrspace(8)* null
>  %621 = extractelement <4 x float> %620, i32 1
>  %622 = fsub float -0,000000e+00, %621
>  %623 = load <4 x float> addrspace(8)* null
>  %624 = extractelement <4 x float> %623, i32 2
>  %625 = fsub float -0,000000e+00, %624
>  %626 = fmul float %622, %622
>  %627 = fsub float -0,000000e+00, %626
>  %628 = fadd float 0x3FF0000000000000, %627
>  %629 = fmul float %628, 0x3FE2024E20000000
>  %630 = fsub float -0,000000e+00, %629
>  %631 = fadd float 0x3FF0000000000000, %630
>  %632 = fcmp olt float %631, 0,000000e+00
>  %633 = sext i1 %632 to i32
>  %634 = bitcast i32 %633 to float
>  %635 = bitcast float %634 to i32
>  %636 = icmp ne i32 %635, 0
>  br i1 %636, label %ENDIF75, label %ELSE77
>
>IF73:                                             ; preds = %ELSE71
>  %637 = fmul float %441, 0x3FE0000000000000
>  %638 = fadd float %637, 0x3FF0000000000000
>  %639 = fmul float %439, 0x3FE0000000000000
>  %640 = fadd float %639, 0x3FE0000000000000
>  %641 = insertelement <4 x float> undef, float %638, i32 0
>  %642 = insertelement <4 x float> %641, float %640, i32 1
>  %643 = insertelement <4 x float> %642, float 0,000000e+00, i32 2
>  %644 = insertelement <4 x float> %643, float 0,000000e+00, i32 3
>  %645 = extractelement <4 x float> %644, i32 0
>  %646 = extractelement <4 x float> %644, i32 1
>  %647 = insertelement <4 x float> undef, float %645, i32 0
>  %648 = insertelement <4 x float> %647, float %646, i32 1
>  %649 = insertelement <4 x float> %648, float undef, i32 2
>  %650 = insertelement <4 x float> %649, float undef, i32 3
>  %651 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %650, i32 16, i32 0, i32 2)
>  %652 = extractelement <4 x float> %651, i32 0
>  %653 = extractelement <4 x float> %651, i32 1
>  %654 = extractelement <4 x float> %651, i32 2
>  %655 = fsub float -0,000000e+00, %443
>  br label %ENDIF69
>
>ELSE74:                                           ; preds = %ELSE71
>  %656 = fmul float %439, 0x3FE0000000000000
>  %657 = fadd float %656, 0x3FE0000000000000
>  %658 = fmul float %443, 0x3FE0000000000000
>  %659 = fadd float %658, 0x3FE0000000000000
>  %660 = insertelement <4 x float> undef, float %657, i32 0
>  %661 = insertelement <4 x float> %660, float %659, i32 1
>  %662 = insertelement <4 x float> %661, float 0,000000e+00, i32 2
>  %663 = insertelement <4 x float> %662, float 0,000000e+00, i32 3
>  %664 = extractelement <4 x float> %663, i32 0
>  %665 = extractelement <4 x float> %663, i32 1
>  %666 = insertelement <4 x float> undef, float %664, i32 0
>  %667 = insertelement <4 x float> %666, float %665, i32 1
>  %668 = insertelement <4 x float> %667, float undef, i32 2
>  %669 = insertelement <4 x float> %668, float undef, i32 3
>  %670 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %669, i32 16, i32 0, i32 2)
>  %671 = extractelement <4 x float> %670, i32 0
>  %672 = extractelement <4 x float> %670, i32 1
>  %673 = extractelement <4 x float> %670, i32 2
>  br label %ENDIF69
>
>ELSE77:                                           ; preds = %ENDIF69
>  %674 = call float @llvm.AMDGPU.rsq(float %631)
>  %675 = fmul float %674, %631
>  %676 = fsub float -0,000000e+00, %631
>  %677 = fcmp ult float %676, 0,000000e+00
>  %678 = select i1 %677, float %675, float 0,000000e+00
>  %679 = fmul float 0x3FE8018960000000, %622
>  %680 = fadd float %679, %678
>  %681 = fmul float %680, 0,000000e+00
>  %682 = fmul float %680, 0x3FF0000000000000
>  %683 = fmul float %680, 0,000000e+00
>  %684 = fsub float -0,000000e+00, %681
>  %685 = fmul float 0x3FE8018960000000, %619
>  %686 = fadd float %685, %684
>  %687 = fsub float -0,000000e+00, %682
>  %688 = fmul float 0x3FE8018960000000, %622
>  %689 = fadd float %688, %687
>  %690 = fsub float -0,000000e+00, %683
>  %691 = fmul float 0x3FE8018960000000, %625
>  %692 = fadd float %691, %690
>  br label %ENDIF75
>
>ENDIF75:                                          ; preds = %ENDIF69, %ELSE77
>  %temp38.2 = phi float [ %683, %ELSE77 ], [ 0,000000e+00, %ENDIF69 ]
>  %temp40.0 = phi float [ %686, %ELSE77 ], [ 0,000000e+00, %ENDIF69 ]
>  %temp41.0 = phi float [ %689, %ELSE77 ], [ 0,000000e+00, %ENDIF69 ]
>  %temp42.0 = phi float [ %692, %ELSE77 ], [ 0,000000e+00, %ENDIF69 ]
>  %693 = fsub float -0,000000e+00, %temp40.0
>  %694 = fsub float -0,000000e+00, %temp41.0
>  %695 = fsub float -0,000000e+00, %temp42.0
>  %696 = insertelement <4 x float> undef, float %693, i32 0
>  %697 = insertelement <4 x float> %696, float %694, i32 1
>  %698 = insertelement <4 x float> %697, float %695, i32 2
>  %699 = insertelement <4 x float> %698, float 0,000000e+00, i32 3
>  %700 = insertelement <4 x float> undef, float %temp28.0, i32 0
>  %701 = insertelement <4 x float> %700, float %temp29.0, i32 1
>  %702 = insertelement <4 x float> %701, float %temp30.0, i32 2
>  %703 = insertelement <4 x float> %702, float 0,000000e+00, i32 3
>  %704 = call float @llvm.AMDGPU.dp4(<4 x float> %699, <4 x float> %703)
>  %705 = fcmp uge float 0,000000e+00, %704
>  %706 = select i1 %705, float 0,000000e+00, float %704
>  %707 = fmul float %439, 0x3FE0000000000000
>  %708 = fadd float %707, 0x3FE0000000000000
>  %709 = fmul float %443, 0x3FE0000000000000
>  %710 = fadd float %709, 0x3FE0000000000000
>  %711 = insertelement <4 x float> undef, float %708, i32 0
>  %712 = insertelement <4 x float> %711, float %710, i32 1
>  %713 = insertelement <4 x float> %712, float %temp38.2, i32 2
>  %714 = insertelement <4 x float> %713, float 0,000000e+00, i32 3
>  %715 = extractelement <4 x float> %714, i32 0
>  %716 = extractelement <4 x float> %714, i32 1
>  %717 = insertelement <4 x float> undef, float %715, i32 0
>  %718 = insertelement <4 x float> %717, float %716, i32 1
>  %719 = insertelement <4 x float> %718, float undef, i32 2
>  %720 = insertelement <4 x float> %719, float undef, i32 3
>  %721 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %720, i32 18, i32 2, i32 2)
>  %722 = extractelement <4 x float> %721, i32 0
>  %723 = fcmp olt float %441, %722
>  %724 = sext i1 %723 to i32
>  %725 = bitcast i32 %724 to float
>  %726 = bitcast float %725 to i32
>  %727 = icmp ne i32 %726, 0
>  br i1 %727, label %IF79, label %ELSE80
>
>IF79:                                             ; preds = %ENDIF75
>  %728 = fmul float %441, %693
>  %729 = fmul float %441, %695
>  %730 = fdiv float 0x3FF0000000000000, %694
>  %731 = fmul float %728, %730
>  %732 = fmul float %729, %730
>  %733 = fsub float -0,000000e+00, %731
>  %734 = fadd float %439, %733
>  %735 = fsub float -0,000000e+00, %732
>  %736 = fadd float %443, %735
>  %737 = fmul float 0x3FD8000000000000, %734
>  %738 = fadd float %737, 0x3FE0000000000000
>  %739 = fmul float 0x3FD8000000000000, %736
>  %740 = fadd float %739, 0x3FE0000000000000
>  %741 = insertelement <4 x float> undef, float %738, i32 0
>  %742 = insertelement <4 x float> %741, float %740, i32 1
>  %743 = insertelement <4 x float> %742, float %temp38.2, i32 2
>  %744 = insertelement <4 x float> %743, float 0,000000e+00, i32 3
>  %745 = extractelement <4 x float> %744, i32 0
>  %746 = extractelement <4 x float> %744, i32 1
>  %747 = insertelement <4 x float> undef, float %745, i32 0
>  %748 = insertelement <4 x float> %747, float %746, i32 1
>  %749 = insertelement <4 x float> %748, float undef, i32 2
>  %750 = insertelement <4 x float> %749, float undef, i32 3
>  %751 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %750, i32 17, i32 1, i32 2)
>  %752 = extractelement <4 x float> %751, i32 0
>  %753 = extractelement <4 x float> %751, i32 1
>  %754 = fmul float %706, %752
>  %755 = fmul float %754, 0x4000000000000000
>  %756 = fmul float %755, %753
>  br label %ENDIF78
>
>ELSE80:                                           ; preds = %ENDIF75
>  %757 = fsub float -0,000000e+00, %439
>  %758 = fadd float 0xBFF0000000000000, %757
>  %759 = fsub float -0,000000e+00, %441
>  %760 = fadd float 0xBFF0000000000000, %759
>  %761 = fsub float -0,000000e+00, %443
>  %762 = fadd float 0xBFF0000000000000, %761
>  %763 = fdiv float 0x3FF0000000000000, %693
>  %764 = fdiv float 0x3FF0000000000000, %694
>  %765 = fdiv float 0x3FF0000000000000, %695
>  %766 = fmul float %758, %763
>  %767 = fmul float %760, %764
>  %768 = fmul float %762, %765
>  %769 = fsub float -0,000000e+00, %439
>  %770 = fadd float 0x3FF0000000000000, %769
>  %771 = fsub float -0,000000e+00, %441
>  %772 = fadd float 0x4000000000000000, %771
>  %773 = fsub float -0,000000e+00, %443
>  %774 = fadd float 0x3FF0000000000000, %773
>  %775 = fdiv float 0x3FF0000000000000, %693
>  %776 = fdiv float 0x3FF0000000000000, %694
>  %777 = fdiv float 0x3FF0000000000000, %695
>  %778 = fmul float %770, %775
>  %779 = fmul float %772, %776
>  %780 = fmul float %774, %777
>  %781 = fcmp uge float %766, %778
>  %782 = select i1 %781, float %778, float %766
>  %783 = fcmp uge float %767, %779
>  %784 = select i1 %783, float %779, float %767
>  %785 = fcmp uge float %768, %780
>  %786 = select i1 %785, float %780, float %768
>  %787 = fcmp uge float %766, %778
>  %788 = select i1 %787, float %766, float %778
>  %789 = fcmp uge float %767, %779
>  %790 = select i1 %789, float %767, float %779
>  %791 = fcmp uge float %768, %780
>  %792 = select i1 %791, float %768, float %780
>  %793 = fcmp uge float %788, %790
>  %794 = select i1 %793, float %790, float %788
>  %795 = fcmp uge float %794, %792
>  %796 = select i1 %795, float %792, float %794
>  %797 = fmul float %694, %796
>  %798 = fadd float %797, %441
>  %799 = fadd float %798, 0xBFC5555560000000
>  %800 = fmul float 0xC072089FC0000000, %799
>  %801 = fcmp uge float %782, %784
>  %802 = select i1 %801, float %782, float %784
>  %803 = fcmp uge float %802, %786
>  %804 = select i1 %803, float %802, float %786
>  %805 = fsub float -0,000000e+00, %804
>  %806 = fadd float %796, %805
>  %807 = fmul float 0x4024000000000000, %806
>  %808 = fadd float %807, 0x3FF0000000000000
>  %809 = fdiv float 0x3FF0000000000000, %808
>  %810 = fmul float %800, %809
>  %811 = call float @llvm.AMDIL.exp.(float %810)
>  %812 = fadd float 0x3FF0000000000000, %811
>  %813 = fdiv float 0x3FF0000000000000, %812
>  %814 = fmul float %706, %813
>  %815 = fmul float %814, 0x3FE0000000000000
>  br label %ENDIF78
>
>ENDIF78:                                          ; preds = %ELSE80, %IF79
>  %.sink = phi float [ %756, %IF79 ], [ %815, %ELSE80 ]
>  %temp38.3 = phi float [ %temp38.2, %IF79 ], [ %792, %ELSE80 ]
>  %816 = fadd float %.sink, %616
>  %817 = fmul float %temp24.0, %816
>  %818 = fmul float %temp25.0, %816
>  %819 = fmul float %temp26.0, %816
>  br label %ENDIF57
>
>IF82:                                             ; preds = %ELSE68
>  %820 = call float @fabs(float %439)
>  %821 = fcmp olt float 0x3FEFF7CEE0000000, %820
>  %822 = sext i1 %821 to i32
>  %823 = bitcast i32 %822 to float
>  %824 = bitcast float %823 to i32
>  %825 = icmp ne i32 %824, 0
>  br i1 %825, label %IF85, label %ELSE86
>
>ELSE83:                                           ; preds = %ELSE68
>  %826 = load <4 x float> addrspace(8)* null
>  %827 = extractelement <4 x float> %826, i32 0
>  %828 = load <4 x float> addrspace(8)* null
>  %829 = extractelement <4 x float> %828, i32 1
>  %830 = load <4 x float> addrspace(8)* null
>  %831 = extractelement <4 x float> %830, i32 2
>  %832 = insertelement <4 x float> undef, float %827, i32 0
>  %833 = insertelement <4 x float> %832, float %829, i32 1
>  %834 = insertelement <4 x float> %833, float %831, i32 2
>  %835 = insertelement <4 x float> %834, float 0,000000e+00, i32 3
>  %836 = insertelement <4 x float> undef, float %163, i32 0
>  %837 = insertelement <4 x float> %836, float %165, i32 1
>  %838 = insertelement <4 x float> %837, float %167, i32 2
>  %839 = insertelement <4 x float> %838, float 0,000000e+00, i32 3
>  %840 = call float @llvm.AMDGPU.dp4(<4 x float> %835, <4 x float> %839)
>  %841 = fcmp uge float 0,000000e+00, %840
>  %842 = select i1 %841, float 0,000000e+00, float %840
>  %843 = call float @llvm.pow.f32(float %842, float 0x40B3880000000000)
>  %844 = insertelement <4 x float> undef, float %163, i32 0
>  %845 = insertelement <4 x float> %844, float %165, i32 1
>  %846 = insertelement <4 x float> %845, float %167, i32 2
>  %847 = insertelement <4 x float> %846, float 0,000000e+00, i32 3
>  %848 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %847)
>  %849 = extractelement <4 x float> %848, i32 0
>  %850 = extractelement <4 x float> %848, i32 1
>  %851 = extractelement <4 x float> %848, i32 2
>  %852 = extractelement <4 x float> %848, i32 3
>  %853 = call float @fabs(float %851)
>  %854 = fdiv float 0x3FF0000000000000, %853
>  %855 = fmul float %849, %854
>  %856 = fadd float %855, 0x3FF8000000000000
>  %857 = fmul float %850, %854
>  %858 = fadd float %857, 0x3FF8000000000000
>  %859 = insertelement <4 x float> undef, float %858, i32 0
>  %860 = insertelement <4 x float> %859, float %856, i32 1
>  %861 = insertelement <4 x float> %860, float %852, i32 2
>  %862 = insertelement <4 x float> %861, float %858, i32 3
>  %863 = extractelement <4 x float> %862, i32 0
>  %864 = extractelement <4 x float> %862, i32 1
>  %865 = extractelement <4 x float> %862, i32 2
>  %866 = extractelement <4 x float> %862, i32 3
>  %867 = insertelement <4 x float> undef, float %863, i32 0
>  %868 = insertelement <4 x float> %867, float %864, i32 1
>  %869 = insertelement <4 x float> %868, float %865, i32 2
>  %870 = insertelement <4 x float> %869, float %866, i32 3
>  %871 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %870, i32 19, i32 3, i32 4)
>  %872 = extractelement <4 x float> %871, i32 0
>  %873 = extractelement <4 x float> %871, i32 1
>  %874 = extractelement <4 x float> %871, i32 2
>  %875 = fmul float %843, 0x4024000000000000
>  %876 = fadd float %875, %872
>  %877 = fmul float %843, 0x4020000000000000
>  %878 = fadd float %877, %873
>  %879 = fmul float %843, 0x4018000000000000
>  %880 = fadd float %879, %874
>  br label %ENDIF57
>
>IF85:                                             ; preds = %IF82
>  %881 = fmul float %441, 0x3FE0000000000000
>  %882 = fadd float %881, 0x3FF0000000000000
>  %883 = fmul float %443, 0x3FE0000000000000
>  %884 = fadd float %883, 0x3FE0000000000000
>  %885 = insertelement <4 x float> undef, float %882, i32 0
>  %886 = insertelement <4 x float> %885, float %884, i32 1
>  %887 = insertelement <4 x float> %886, float %424, i32 2
>  %888 = insertelement <4 x float> %887, float 0,000000e+00, i32 3
>  %889 = extractelement <4 x float> %888, i32 0
>  %890 = extractelement <4 x float> %888, i32 1
>  %891 = insertelement <4 x float> undef, float %889, i32 0
>  %892 = insertelement <4 x float> %891, float %890, i32 1
>  %893 = insertelement <4 x float> %892, float undef, i32 2
>  %894 = insertelement <4 x float> %893, float undef, i32 3
>  %895 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %894, i32 16, i32 0, i32 2)
>  %896 = extractelement <4 x float> %895, i32 0
>  %897 = extractelement <4 x float> %895, i32 1
>  %898 = extractelement <4 x float> %895, i32 2
>  %899 = fsub float -0,000000e+00, %439
>  br label %ENDIF84
>
>ELSE86:                                           ; preds = %IF82
>  %900 = call float @fabs(float %443)
>  %901 = fcmp olt float 0x3FEFF7CEE0000000, %900
>  %902 = sext i1 %901 to i32
>  %903 = bitcast i32 %902 to float
>  %904 = bitcast float %903 to i32
>  %905 = icmp ne i32 %904, 0
>  br i1 %905, label %IF88, label %ELSE89
>
>ENDIF84:                                          ; preds = %IF88, %ELSE89, %IF85
>  %temp24.2 = phi float [ %896, %IF85 ], [ %988, %IF88 ], [ %1007, %ELSE89 ]
>  %temp25.2 = phi float [ %897, %IF85 ], [ %989, %IF88 ], [ %1008, %ELSE89 ]
>  %temp26.2 = phi float [ %898, %IF85 ], [ %990, %IF88 ], [ %1009, %ELSE89 ]
>  %temp28.2 = phi float [ %899, %IF85 ], [ 0,000000e+00, %ELSE89 ], [ 0,000000e+00, %IF88 ]
>  %temp29.2 = phi float [ 0,000000e+00, %IF85 ], [ 0,000000e+00, %IF88 ], [ 0x3FF0000000000000, %ELSE89 ]
>  %temp30.2 = phi float [ 0,000000e+00, %IF85 ], [ %991, %IF88 ], [ 0,000000e+00, %ELSE89 ]
>  %906 = insertelement <4 x float> undef, float %439, i32 0
>  %907 = insertelement <4 x float> %906, float %441, i32 1
>  %908 = insertelement <4 x float> %907, float %443, i32 2
>  %909 = insertelement <4 x float> %908, float 0,000000e+00, i32 3
>  %910 = insertelement <4 x float> undef, float %439, i32 0
>  %911 = insertelement <4 x float> %910, float %441, i32 1
>  %912 = insertelement <4 x float> %911, float %443, i32 2
>  %913 = insertelement <4 x float> %912, float 0,000000e+00, i32 3
>  %914 = call float @llvm.AMDGPU.dp4(<4 x float> %909, <4 x float> %913)
>  %915 = call float @llvm.AMDGPU.rsq(float %914)
>  %916 = fmul float 0x3FE0000000000000, %915
>  %917 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %918 = extractelement <4 x float> %917, i32 0
>  %919 = fsub float -0,000000e+00, %918
>  %920 = fadd float %439, %919
>  %921 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %922 = extractelement <4 x float> %921, i32 1
>  %923 = fsub float -0,000000e+00, %922
>  %924 = fadd float %441, %923
>  %925 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %926 = extractelement <4 x float> %925, i32 2
>  %927 = fsub float -0,000000e+00, %926
>  %928 = fadd float %443, %927
>  %929 = insertelement <4 x float> undef, float %920, i32 0
>  %930 = insertelement <4 x float> %929, float %924, i32 1
>  %931 = insertelement <4 x float> %930, float %928, i32 2
>  %932 = insertelement <4 x float> %931, float 0,000000e+00, i32 3
>  %933 = insertelement <4 x float> undef, float %920, i32 0
>  %934 = insertelement <4 x float> %933, float %924, i32 1
>  %935 = insertelement <4 x float> %934, float %928, i32 2
>  %936 = insertelement <4 x float> %935, float 0,000000e+00, i32 3
>  %937 = call float @llvm.AMDGPU.dp4(<4 x float> %932, <4 x float> %936)
>  %938 = call float @llvm.AMDGPU.rsq(float %937)
>  %939 = fmul float %938, %937
>  %940 = fsub float -0,000000e+00, %937
>  %941 = fcmp ult float %940, 0,000000e+00
>  %942 = select i1 %941, float %939, float 0,000000e+00
>  %943 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %944 = extractelement <4 x float> %943, i32 0
>  %945 = fdiv float 0x3FF0000000000000, %944
>  %946 = fmul float %942, %945
>  %947 = call float @llvm.pow.f32(float %946, float 0x4010000000000000)
>  %948 = fdiv float 0x3FF0000000000000, %947
>  %949 = fmul float 0x3FECCCCCC0000000, %948
>  %950 = fsub float -0,000000e+00, %949
>  %951 = fadd float 0x3FF0000000000000, %950
>  %952 = fmul float %916, %951
>  %953 = load <4 x float> addrspace(8)* null
>  %954 = extractelement <4 x float> %953, i32 0
>  %955 = fsub float -0,000000e+00, %954
>  %956 = load <4 x float> addrspace(8)* null
>  %957 = extractelement <4 x float> %956, i32 1
>  %958 = fsub float -0,000000e+00, %957
>  %959 = load <4 x float> addrspace(8)* null
>  %960 = extractelement <4 x float> %959, i32 2
>  %961 = fsub float -0,000000e+00, %960
>  %962 = fmul float %958, %958
>  %963 = fsub float -0,000000e+00, %962
>  %964 = fadd float 0x3FF0000000000000, %963
>  %965 = fmul float %964, 0x3FE2024E20000000
>  %966 = fsub float -0,000000e+00, %965
>  %967 = fadd float 0x3FF0000000000000, %966
>  %968 = fcmp olt float %967, 0,000000e+00
>  %969 = sext i1 %968 to i32
>  %970 = bitcast i32 %969 to float
>  %971 = bitcast float %970 to i32
>  %972 = icmp ne i32 %971, 0
>  br i1 %972, label %ENDIF90, label %ELSE92
>
>IF88:                                             ; preds = %ELSE86
>  %973 = fmul float %441, 0x3FE0000000000000
>  %974 = fadd float %973, 0x3FF0000000000000
>  %975 = fmul float %439, 0x3FE0000000000000
>  %976 = fadd float %975, 0x3FE0000000000000
>  %977 = insertelement <4 x float> undef, float %974, i32 0
>  %978 = insertelement <4 x float> %977, float %976, i32 1
>  %979 = insertelement <4 x float> %978, float 0,000000e+00, i32 2
>  %980 = insertelement <4 x float> %979, float 0,000000e+00, i32 3
>  %981 = extractelement <4 x float> %980, i32 0
>  %982 = extractelement <4 x float> %980, i32 1
>  %983 = insertelement <4 x float> undef, float %981, i32 0
>  %984 = insertelement <4 x float> %983, float %982, i32 1
>  %985 = insertelement <4 x float> %984, float undef, i32 2
>  %986 = insertelement <4 x float> %985, float undef, i32 3
>  %987 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %986, i32 16, i32 0, i32 2)
>  %988 = extractelement <4 x float> %987, i32 0
>  %989 = extractelement <4 x float> %987, i32 1
>  %990 = extractelement <4 x float> %987, i32 2
>  %991 = fsub float -0,000000e+00, %443
>  br label %ENDIF84
>
>ELSE89:                                           ; preds = %ELSE86
>  %992 = fmul float %439, 0x3FE0000000000000
>  %993 = fadd float %992, 0x3FE0000000000000
>  %994 = fmul float %443, 0x3FE0000000000000
>  %995 = fadd float %994, 0x3FE0000000000000
>  %996 = insertelement <4 x float> undef, float %993, i32 0
>  %997 = insertelement <4 x float> %996, float %995, i32 1
>  %998 = insertelement <4 x float> %997, float 0,000000e+00, i32 2
>  %999 = insertelement <4 x float> %998, float 0,000000e+00, i32 3
>  %1000 = extractelement <4 x float> %999, i32 0
>  %1001 = extractelement <4 x float> %999, i32 1
>  %1002 = insertelement <4 x float> undef, float %1000, i32 0
>  %1003 = insertelement <4 x float> %1002, float %1001, i32 1
>  %1004 = insertelement <4 x float> %1003, float undef, i32 2
>  %1005 = insertelement <4 x float> %1004, float undef, i32 3
>  %1006 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1005, i32 16, i32 0, i32 2)
>  %1007 = extractelement <4 x float> %1006, i32 0
>  %1008 = extractelement <4 x float> %1006, i32 1
>  %1009 = extractelement <4 x float> %1006, i32 2
>  br label %ENDIF84
>
>ELSE92:                                           ; preds = %ENDIF84
>  %1010 = call float @llvm.AMDGPU.rsq(float %967)
>  %1011 = fmul float %1010, %967
>  %1012 = fsub float -0,000000e+00, %967
>  %1013 = fcmp ult float %1012, 0,000000e+00
>  %1014 = select i1 %1013, float %1011, float 0,000000e+00
>  %1015 = fmul float 0x3FE8018960000000, %958
>  %1016 = fadd float %1015, %1014
>  %1017 = fmul float %1016, 0,000000e+00
>  %1018 = fmul float %1016, 0x3FF0000000000000
>  %1019 = fmul float %1016, 0,000000e+00
>  %1020 = fsub float -0,000000e+00, %1017
>  %1021 = fmul float 0x3FE8018960000000, %955
>  %1022 = fadd float %1021, %1020
>  %1023 = fsub float -0,000000e+00, %1018
>  %1024 = fmul float 0x3FE8018960000000, %958
>  %1025 = fadd float %1024, %1023
>  %1026 = fsub float -0,000000e+00, %1019
>  %1027 = fmul float 0x3FE8018960000000, %961
>  %1028 = fadd float %1027, %1026
>  br label %ENDIF90
>
>ENDIF90:                                          ; preds = %ENDIF84, %ELSE92
>  %temp38.5 = phi float [ %1019, %ELSE92 ], [ 0,000000e+00, %ENDIF84 ]
>  %temp40.1 = phi float [ %1022, %ELSE92 ], [ 0,000000e+00, %ENDIF84 ]
>  %temp41.1 = phi float [ %1025, %ELSE92 ], [ 0,000000e+00, %ENDIF84 ]
>  %temp42.1 = phi float [ %1028, %ELSE92 ], [ 0,000000e+00, %ENDIF84 ]
>  %1029 = fsub float -0,000000e+00, %temp40.1
>  %1030 = fsub float -0,000000e+00, %temp41.1
>  %1031 = fsub float -0,000000e+00, %temp42.1
>  %1032 = insertelement <4 x float> undef, float %1029, i32 0
>  %1033 = insertelement <4 x float> %1032, float %1030, i32 1
>  %1034 = insertelement <4 x float> %1033, float %1031, i32 2
>  %1035 = insertelement <4 x float> %1034, float 0,000000e+00, i32 3
>  %1036 = insertelement <4 x float> undef, float %temp28.2, i32 0
>  %1037 = insertelement <4 x float> %1036, float %temp29.2, i32 1
>  %1038 = insertelement <4 x float> %1037, float %temp30.2, i32 2
>  %1039 = insertelement <4 x float> %1038, float 0,000000e+00, i32 3
>  %1040 = call float @llvm.AMDGPU.dp4(<4 x float> %1035, <4 x float> %1039)
>  %1041 = fcmp uge float 0,000000e+00, %1040
>  %1042 = select i1 %1041, float 0,000000e+00, float %1040
>  %1043 = fmul float %439, 0x3FE0000000000000
>  %1044 = fadd float %1043, 0x3FE0000000000000
>  %1045 = fmul float %443, 0x3FE0000000000000
>  %1046 = fadd float %1045, 0x3FE0000000000000
>  %1047 = insertelement <4 x float> undef, float %1044, i32 0
>  %1048 = insertelement <4 x float> %1047, float %1046, i32 1
>  %1049 = insertelement <4 x float> %1048, float %temp38.5, i32 2
>  %1050 = insertelement <4 x float> %1049, float 0,000000e+00, i32 3
>  %1051 = extractelement <4 x float> %1050, i32 0
>  %1052 = extractelement <4 x float> %1050, i32 1
>  %1053 = insertelement <4 x float> undef, float %1051, i32 0
>  %1054 = insertelement <4 x float> %1053, float %1052, i32 1
>  %1055 = insertelement <4 x float> %1054, float undef, i32 2
>  %1056 = insertelement <4 x float> %1055, float undef, i32 3
>  %1057 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1056, i32 18, i32 2, i32 2)
>  %1058 = extractelement <4 x float> %1057, i32 0
>  %1059 = fcmp olt float %441, %1058
>  %1060 = sext i1 %1059 to i32
>  %1061 = bitcast i32 %1060 to float
>  %1062 = bitcast float %1061 to i32
>  %1063 = icmp ne i32 %1062, 0
>  br i1 %1063, label %IF94, label %ELSE95
>
>IF94:                                             ; preds = %ENDIF90
>  %1064 = fmul float %441, %1029
>  %1065 = fmul float %441, %1031
>  %1066 = fdiv float 0x3FF0000000000000, %1030
>  %1067 = fmul float %1064, %1066
>  %1068 = fmul float %1065, %1066
>  %1069 = fsub float -0,000000e+00, %1067
>  %1070 = fadd float %439, %1069
>  %1071 = fsub float -0,000000e+00, %1068
>  %1072 = fadd float %443, %1071
>  %1073 = fmul float 0x3FD8000000000000, %1070
>  %1074 = fadd float %1073, 0x3FE0000000000000
>  %1075 = fmul float 0x3FD8000000000000, %1072
>  %1076 = fadd float %1075, 0x3FE0000000000000
>  %1077 = insertelement <4 x float> undef, float %1074, i32 0
>  %1078 = insertelement <4 x float> %1077, float %1076, i32 1
>  %1079 = insertelement <4 x float> %1078, float %temp38.5, i32 2
>  %1080 = insertelement <4 x float> %1079, float 0,000000e+00, i32 3
>  %1081 = extractelement <4 x float> %1080, i32 0
>  %1082 = extractelement <4 x float> %1080, i32 1
>  %1083 = insertelement <4 x float> undef, float %1081, i32 0
>  %1084 = insertelement <4 x float> %1083, float %1082, i32 1
>  %1085 = insertelement <4 x float> %1084, float undef, i32 2
>  %1086 = insertelement <4 x float> %1085, float undef, i32 3
>  %1087 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1086, i32 17, i32 1, i32 2)
>  %1088 = extractelement <4 x float> %1087, i32 0
>  %1089 = extractelement <4 x float> %1087, i32 1
>  %1090 = fmul float %1042, %1088
>  %1091 = fmul float %1090, 0x4000000000000000
>  %1092 = fmul float %1091, %1089
>  br label %ENDIF93
>
>ELSE95:                                           ; preds = %ENDIF90
>  %1093 = fsub float -0,000000e+00, %439
>  %1094 = fadd float 0xBFF0000000000000, %1093
>  %1095 = fsub float -0,000000e+00, %441
>  %1096 = fadd float 0xBFF0000000000000, %1095
>  %1097 = fsub float -0,000000e+00, %443
>  %1098 = fadd float 0xBFF0000000000000, %1097
>  %1099 = fdiv float 0x3FF0000000000000, %1029
>  %1100 = fdiv float 0x3FF0000000000000, %1030
>  %1101 = fdiv float 0x3FF0000000000000, %1031
>  %1102 = fmul float %1094, %1099
>  %1103 = fmul float %1096, %1100
>  %1104 = fmul float %1098, %1101
>  %1105 = fsub float -0,000000e+00, %439
>  %1106 = fadd float 0x3FF0000000000000, %1105
>  %1107 = fsub float -0,000000e+00, %441
>  %1108 = fadd float 0x4000000000000000, %1107
>  %1109 = fsub float -0,000000e+00, %443
>  %1110 = fadd float 0x3FF0000000000000, %1109
>  %1111 = fdiv float 0x3FF0000000000000, %1029
>  %1112 = fdiv float 0x3FF0000000000000, %1030
>  %1113 = fdiv float 0x3FF0000000000000, %1031
>  %1114 = fmul float %1106, %1111
>  %1115 = fmul float %1108, %1112
>  %1116 = fmul float %1110, %1113
>  %1117 = fcmp uge float %1102, %1114
>  %1118 = select i1 %1117, float %1114, float %1102
>  %1119 = fcmp uge float %1103, %1115
>  %1120 = select i1 %1119, float %1115, float %1103
>  %1121 = fcmp uge float %1104, %1116
>  %1122 = select i1 %1121, float %1116, float %1104
>  %1123 = fcmp uge float %1102, %1114
>  %1124 = select i1 %1123, float %1102, float %1114
>  %1125 = fcmp uge float %1103, %1115
>  %1126 = select i1 %1125, float %1103, float %1115
>  %1127 = fcmp uge float %1104, %1116
>  %1128 = select i1 %1127, float %1104, float %1116
>  %1129 = fcmp uge float %1124, %1126
>  %1130 = select i1 %1129, float %1126, float %1124
>  %1131 = fcmp uge float %1130, %1128
>  %1132 = select i1 %1131, float %1128, float %1130
>  %1133 = fmul float %1030, %1132
>  %1134 = fadd float %1133, %441
>  %1135 = fadd float %1134, 0xBFC5555560000000
>  %1136 = fmul float 0xC072089FC0000000, %1135
>  %1137 = fcmp uge float %1118, %1120
>  %1138 = select i1 %1137, float %1118, float %1120
>  %1139 = fcmp uge float %1138, %1122
>  %1140 = select i1 %1139, float %1138, float %1122
>  %1141 = fsub float -0,000000e+00, %1140
>  %1142 = fadd float %1132, %1141
>  %1143 = fmul float 0x4024000000000000, %1142
>  %1144 = fadd float %1143, 0x3FF0000000000000
>  %1145 = fdiv float 0x3FF0000000000000, %1144
>  %1146 = fmul float %1136, %1145
>  %1147 = call float @llvm.AMDIL.exp.(float %1146)
>  %1148 = fadd float 0x3FF0000000000000, %1147
>  %1149 = fdiv float 0x3FF0000000000000, %1148
>  %1150 = fmul float %1042, %1149
>  %1151 = fmul float %1150, 0x3FE0000000000000
>  br label %ENDIF93
>
>ENDIF93:                                          ; preds = %ELSE95, %IF94
>  %.sink150 = phi float [ %1092, %IF94 ], [ %1151, %ELSE95 ]
>  %temp38.6 = phi float [ %temp38.5, %IF94 ], [ %1128, %ELSE95 ]
>  %1152 = fadd float %.sink150, %952
>  %1153 = fmul float %temp24.2, %1152
>  %1154 = fmul float %temp25.2, %1152
>  %1155 = fmul float %temp26.2, %1152
>  br label %ENDIF57
>
>IF97:                                             ; preds = %ENDIF57
>  %1156 = fmul float %temp4.2, 0x3FD0000000000000
>  %1157 = fmul float %temp5.0, 0x3FF0000000000000
>  %1158 = fmul float %temp6.0, 0x3FF4000000000000
>  br label %ENDIF96
>
>ENDIF96:                                          ; preds = %ENDIF57, %IF97
>  %temp6.3 = phi float [ %1158, %IF97 ], [ %temp6.0, %ENDIF57 ]
>  %temp5.3 = phi float [ %1157, %IF97 ], [ %temp5.0, %ENDIF57 ]
>  %temp4.5 = phi float [ %1156, %IF97 ], [ %temp4.2, %ENDIF57 ]
>  %1159 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %1160 = extractelement <4 x float> %1159, i32 0
>  %1161 = fsub float -0,000000e+00, %1160
>  %1162 = fadd float %0, %1161
>  %1163 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %1164 = extractelement <4 x float> %1163, i32 1
>  %1165 = fsub float -0,000000e+00, %1164
>  %1166 = fadd float %1, %1165
>  %1167 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %1168 = extractelement <4 x float> %1167, i32 2
>  %1169 = fsub float -0,000000e+00, %1168
>  %1170 = fadd float %2, %1169
>  %1171 = insertelement <4 x float> undef, float %temp20.0, i32 0
>  %1172 = insertelement <4 x float> %1171, float %temp21.0, i32 1
>  %1173 = insertelement <4 x float> %1172, float %temp22.0, i32 2
>  %1174 = insertelement <4 x float> %1173, float 0,000000e+00, i32 3
>  %1175 = insertelement <4 x float> undef, float %temp20.0, i32 0
>  %1176 = insertelement <4 x float> %1175, float %temp21.0, i32 1
>  %1177 = insertelement <4 x float> %1176, float %temp22.0, i32 2
>  %1178 = insertelement <4 x float> %1177, float 0,000000e+00, i32 3
>  %1179 = call float @llvm.AMDGPU.dp4(<4 x float> %1174, <4 x float> %1178)
>  %1180 = insertelement <4 x float> undef, float %1162, i32 0
>  %1181 = insertelement <4 x float> %1180, float %1166, i32 1
>  %1182 = insertelement <4 x float> %1181, float %1170, i32 2
>  %1183 = insertelement <4 x float> %1182, float 0,000000e+00, i32 3
>  %1184 = insertelement <4 x float> undef, float %temp20.0, i32 0
>  %1185 = insertelement <4 x float> %1184, float %temp21.0, i32 1
>  %1186 = insertelement <4 x float> %1185, float %temp22.0, i32 2
>  %1187 = insertelement <4 x float> %1186, float 0,000000e+00, i32 3
>  %1188 = call float @llvm.AMDGPU.dp4(<4 x float> %1183, <4 x float> %1187)
>  %1189 = fmul float 0x4000000000000000, %1188
>  %1190 = fmul float 0x4010000000000000, %1179
>  %1191 = insertelement <4 x float> undef, float %1162, i32 0
>  %1192 = insertelement <4 x float> %1191, float %1166, i32 1
>  %1193 = insertelement <4 x float> %1192, float %1170, i32 2
>  %1194 = insertelement <4 x float> %1193, float 0,000000e+00, i32 3
>  %1195 = insertelement <4 x float> undef, float %1162, i32 0
>  %1196 = insertelement <4 x float> %1195, float %1166, i32 1
>  %1197 = insertelement <4 x float> %1196, float %1170, i32 2
>  %1198 = insertelement <4 x float> %1197, float 0,000000e+00, i32 3
>  %1199 = call float @llvm.AMDGPU.dp4(<4 x float> %1194, <4 x float> %1198)
>  %1200 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %1201 = extractelement <4 x float> %1200, i32 0
>  %1202 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %1203 = extractelement <4 x float> %1202, i32 0
>  %1204 = fmul float %1201, %1203
>  %1205 = fsub float -0,000000e+00, %1204
>  %1206 = fadd float %1199, %1205
>  %1207 = fmul float %1190, %1206
>  %1208 = fsub float -0,000000e+00, %1207
>  %1209 = fmul float %1189, %1189
>  %1210 = fadd float %1209, %1208
>  %1211 = fcmp olt float 0,000000e+00, %1210
>  %1212 = sext i1 %1211 to i32
>  %1213 = bitcast i32 %1212 to float
>  %1214 = bitcast float %1213 to i32
>  %1215 = icmp ne i32 %1214, 0
>  br i1 %1215, label %IF100, label %ENDIF99
>
>IF100:                                            ; preds = %ENDIF96
>  %1216 = call float @llvm.AMDGPU.rsq(float %1210)
>  %1217 = fmul float %1216, %1210
>  %1218 = fsub float -0,000000e+00, %1210
>  %1219 = fcmp ult float %1218, 0,000000e+00
>  %1220 = select i1 %1219, float %1217, float 0,000000e+00
>  %1221 = fsub float -0,000000e+00, %1189
>  %1222 = fsub float -0,000000e+00, %1220
>  %1223 = fadd float %1221, %1222
>  %1224 = fmul float 0x4000000000000000, %1179
>  %1225 = fdiv float 0x3FF0000000000000, %1224
>  %1226 = fmul float %1223, %1225
>  %1227 = fcmp olt float 0,000000e+00, %1226
>  %1228 = sext i1 %1227 to i32
>  %1229 = bitcast i32 %1228 to float
>  %1230 = bitcast float %1229 to i32
>  %1231 = icmp ne i32 %1230, 0
>  %.151 = select i1 %1231, float 0,000000e+00, float 0xFFFFFFFFE0000000
>  br label %ENDIF99
>
>ENDIF99:                                          ; preds = %ENDIF96, %IF100
>  %temp8.0 = phi float [ %.151, %IF100 ], [ 0xFFFFFFFFE0000000, %ENDIF96 ]
>  %temp12.3 = phi float [ %1226, %IF100 ], [ %1210, %ENDIF96 ]
>  %1232 = bitcast float %temp8.0 to i32
>  %1233 = icmp ne i32 %1232, 0
>  %.temp12.3 = select i1 %1233, float 0x412E848000000000, float %temp12.3
>  %1234 = fcmp olt float %.temp12.3, 0x412E848000000000
>  %1235 = sext i1 %1234 to i32
>  %1236 = bitcast i32 %1235 to float
>  %1237 = bitcast float %1236 to i32
>  %1238 = icmp ne i32 %1237, 0
>  br i1 %1238, label %IF109, label %ELSE110
>
>IF109:                                            ; preds = %ENDIF99
>  %1239 = fmul float %temp20.0, %.temp12.3
>  %1240 = fadd float %1239, %0
>  %1241 = fmul float %temp21.0, %.temp12.3
>  %1242 = fadd float %1241, %1
>  %1243 = fmul float %temp22.0, %.temp12.3
>  %1244 = fadd float %1243, %2
>  %1245 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %1246 = extractelement <4 x float> %1245, i32 0
>  %1247 = fadd float 0x3FF0000000000000, %1246
>  %1248 = call float @fabs(float %1240)
>  %1249 = fsub float -0,000000e+00, %1248
>  %1250 = fadd float %1247, %1249
>  %1251 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %1252 = extractelement <4 x float> %1251, i32 0
>  %1253 = fdiv float 0x3FF0000000000000, %1252
>  %1254 = fmul float %1250, %1253
>  %1255 = call float @llvm.pow.f32(float %1254, float 0x4008000000000000)
>  %1256 = fdiv float 0x3FF0000000000000, %1255
>  %1257 = fmul float 0x3FECCCCCC0000000, %1256
>  %1258 = fsub float -0,000000e+00, %1257
>  %1259 = fadd float 0x3FF0000000000000, %1258
>  %1260 = fmul float 0x3FE0000000000000, %1259
>  %1261 = fmul float 0x3FE0000000000000, %1259
>  %1262 = fmul float 0x3FE0000000000000, %1259
>  %1263 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %1264 = extractelement <4 x float> %1263, i32 0
>  %1265 = fadd float 0x3FF0000000000000, %1264
>  %1266 = call float @fabs(float %1244)
>  %1267 = fsub float -0,000000e+00, %1266
>  %1268 = fadd float %1265, %1267
>  %1269 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %1270 = extractelement <4 x float> %1269, i32 0
>  %1271 = fdiv float 0x3FF0000000000000, %1270
>  %1272 = fmul float %1268, %1271
>  %1273 = call float @llvm.pow.f32(float %1272, float 0x4008000000000000)
>  %1274 = fdiv float 0x3FF0000000000000, %1273
>  %1275 = fmul float 0x3FECCCCCC0000000, %1274
>  %1276 = fsub float -0,000000e+00, %1275
>  %1277 = fadd float 0x3FF0000000000000, %1276
>  %1278 = fmul float %1260, %1277
>  %1279 = fmul float %1261, %1277
>  %1280 = fmul float %1262, %1277
>  %1281 = fadd float %1242, 0x3FF0000000000000
>  %1282 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %1283 = extractelement <4 x float> %1282, i32 0
>  %1284 = fadd float %1281, %1283
>  %1285 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %1286 = extractelement <4 x float> %1285, i32 0
>  %1287 = fdiv float 0x3FF0000000000000, %1286
>  %1288 = fmul float %1284, %1287
>  %1289 = call float @llvm.pow.f32(float %1288, float 0x4008000000000000)
>  %1290 = fdiv float 0x3FF0000000000000, %1289
>  %1291 = fmul float 0x3FECCCCCC0000000, %1290
>  %1292 = fsub float -0,000000e+00, %1291
>  %1293 = fadd float 0x3FF0000000000000, %1292
>  %1294 = fmul float %1278, %1293
>  %1295 = fmul float %1279, %1293
>  %1296 = fmul float %1280, %1293
>  %1297 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %1298 = extractelement <4 x float> %1297, i32 0
>  %1299 = fsub float -0,000000e+00, %1298
>  %1300 = fadd float %1240, %1299
>  %1301 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %1302 = extractelement <4 x float> %1301, i32 1
>  %1303 = fsub float -0,000000e+00, %1302
>  %1304 = fadd float %1242, %1303
>  %1305 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %1306 = extractelement <4 x float> %1305, i32 2
>  %1307 = fsub float -0,000000e+00, %1306
>  %1308 = fadd float %1244, %1307
>  %1309 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %1310 = extractelement <4 x float> %1309, i32 0
>  %1311 = fdiv float 0x3FF0000000000000, %1310
>  %1312 = fmul float %1300, %1311
>  %1313 = fmul float %1304, %1311
>  %1314 = fmul float %1308, %1311
>  %1315 = load <4 x float> addrspace(8)* null
>  %1316 = extractelement <4 x float> %1315, i32 0
>  %1317 = fsub float -0,000000e+00, %1316
>  %1318 = load <4 x float> addrspace(8)* null
>  %1319 = extractelement <4 x float> %1318, i32 1
>  %1320 = fsub float -0,000000e+00, %1319
>  %1321 = load <4 x float> addrspace(8)* null
>  %1322 = extractelement <4 x float> %1321, i32 2
>  %1323 = fsub float -0,000000e+00, %1322
>  %1324 = fmul float %1320, %1320
>  %1325 = fsub float -0,000000e+00, %1324
>  %1326 = fadd float 0x3FF0000000000000, %1325
>  %1327 = fmul float %1326, 0x3FE2024E20000000
>  %1328 = fsub float -0,000000e+00, %1327
>  %1329 = fadd float 0x3FF0000000000000, %1328
>  %1330 = fcmp olt float %1329, 0,000000e+00
>  %1331 = sext i1 %1330 to i32
>  %1332 = bitcast i32 %1331 to float
>  %1333 = bitcast float %1332 to i32
>  %1334 = icmp ne i32 %1333, 0
>  br i1 %1334, label %ENDIF111, label %ELSE113
>
>ELSE110:                                          ; preds = %ENDIF99
>  %1335 = fcmp olt float %temp21.0, 0,000000e+00
>  %1336 = sext i1 %1335 to i32
>  %1337 = bitcast i32 %1336 to float
>  %1338 = bitcast float %1337 to i32
>  %1339 = icmp ne i32 %1338, 0
>  %1340 = fsub float -0,000000e+00, %0
>  %1341 = fadd float 0xBFF0000000000000, %1340
>  %1342 = fsub float -0,000000e+00, %1
>  %1343 = fadd float 0xBFF0000000000000, %1342
>  %1344 = fsub float -0,000000e+00, %2
>  %1345 = fadd float 0xBFF0000000000000, %1344
>  %1346 = fdiv float 0x3FF0000000000000, %temp20.0
>  %1347 = fdiv float 0x3FF0000000000000, %temp21.0
>  %1348 = fdiv float 0x3FF0000000000000, %temp22.0
>  %1349 = fmul float %1341, %1346
>  %1350 = fmul float %1343, %1347
>  %1351 = fmul float %1345, %1348
>  %1352 = fsub float -0,000000e+00, %0
>  %1353 = fadd float 0x3FF0000000000000, %1352
>  %1354 = fsub float -0,000000e+00, %1
>  %1355 = fadd float 0x4000000000000000, %1354
>  %1356 = fsub float -0,000000e+00, %2
>  %1357 = fadd float 0x3FF0000000000000, %1356
>  %1358 = fdiv float 0x3FF0000000000000, %temp20.0
>  %1359 = fdiv float 0x3FF0000000000000, %temp21.0
>  %1360 = fdiv float 0x3FF0000000000000, %temp22.0
>  %1361 = fmul float %1353, %1358
>  %1362 = fmul float %1355, %1359
>  %1363 = fmul float %1357, %1360
>  %1364 = fcmp uge float %1349, %1361
>  %1365 = select i1 %1364, float %1349, float %1361
>  %1366 = fcmp uge float %1350, %1362
>  %1367 = select i1 %1366, float %1350, float %1362
>  %1368 = fcmp uge float %1351, %1363
>  %1369 = select i1 %1368, float %1351, float %1363
>  %1370 = fcmp uge float %1365, %1367
>  %1371 = select i1 %1370, float %1367, float %1365
>  %1372 = fcmp uge float %1371, %1369
>  %1373 = select i1 %1372, float %1369, float %1371
>  %1374 = fmul float %temp20.0, %1373
>  %1375 = fadd float %1374, %0
>  %1376 = fmul float %temp21.0, %1373
>  %1377 = fadd float %1376, %1
>  %1378 = fmul float %temp22.0, %1373
>  %1379 = fadd float %1378, %2
>  br i1 %1339, label %IF118, label %ELSE119
>
>ENDIF108:                                         ; preds = %ENDIF144, %ELSE134, %ENDIF129, %ENDIF114
>  %temp8.2 = phi float [ %1467, %ENDIF114 ], [ %1753, %ENDIF129 ], [ %2089, %ENDIF144 ], [ %1812, %ELSE134 ]
>  %temp9.0 = phi float [ %1468, %ENDIF114 ], [ %1754, %ENDIF129 ], [ %2090, %ENDIF144 ], [ %1814, %ELSE134 ]
>  %temp10.0 = phi float [ %1469, %ENDIF114 ], [ %1755, %ENDIF129 ], [ %2091, %ENDIF144 ], [ %1816, %ELSE134 ]
>  %1380 = fcmp olt float %temp21.0, 0,000000e+00
>  %1381 = sext i1 %1380 to i32
>  %1382 = bitcast i32 %1381 to float
>  %1383 = bitcast float %1382 to i32
>  %1384 = icmp ne i32 %1383, 0
>  br i1 %1384, label %IF148, label %ENDIF147
>
>ELSE113:                                          ; preds = %IF109
>  %1385 = call float @llvm.AMDGPU.rsq(float %1329)
>  %1386 = fmul float %1385, %1329
>  %1387 = fsub float -0,000000e+00, %1329
>  %1388 = fcmp ult float %1387, 0,000000e+00
>  %1389 = select i1 %1388, float %1386, float 0,000000e+00
>  %1390 = fmul float 0x3FE8018960000000, %1320
>  %1391 = fadd float %1390, %1389
>  %1392 = fmul float %1391, 0,000000e+00
>  %1393 = fmul float %1391, 0x3FF0000000000000
>  %1394 = fmul float %1391, 0,000000e+00
>  %1395 = fsub float -0,000000e+00, %1392
>  %1396 = fmul float 0x3FE8018960000000, %1317
>  %1397 = fadd float %1396, %1395
>  %1398 = fsub float -0,000000e+00, %1393
>  %1399 = fmul float 0x3FE8018960000000, %1320
>  %1400 = fadd float %1399, %1398
>  %1401 = fsub float -0,000000e+00, %1394
>  %1402 = fmul float 0x3FE8018960000000, %1323
>  %1403 = fadd float %1402, %1401
>  br label %ENDIF111
>
>ENDIF111:                                         ; preds = %IF109, %ELSE113
>  %temp32.1 = phi float [ %1397, %ELSE113 ], [ 0,000000e+00, %IF109 ]
>  %temp33.1 = phi float [ %1400, %ELSE113 ], [ 0,000000e+00, %IF109 ]
>  %temp34.4 = phi float [ %1403, %ELSE113 ], [ 0,000000e+00, %IF109 ]
>  %1404 = fsub float -0,000000e+00, %temp32.1
>  %1405 = fsub float -0,000000e+00, %temp33.1
>  %1406 = fsub float -0,000000e+00, %temp34.4
>  %1407 = insertelement <4 x float> undef, float %1404, i32 0
>  %1408 = insertelement <4 x float> %1407, float %1405, i32 1
>  %1409 = insertelement <4 x float> %1408, float %1406, i32 2
>  %1410 = insertelement <4 x float> %1409, float 0,000000e+00, i32 3
>  %1411 = insertelement <4 x float> undef, float %1312, i32 0
>  %1412 = insertelement <4 x float> %1411, float %1313, i32 1
>  %1413 = insertelement <4 x float> %1412, float %1314, i32 2
>  %1414 = insertelement <4 x float> %1413, float 0,000000e+00, i32 3
>  %1415 = call float @llvm.AMDGPU.dp4(<4 x float> %1410, <4 x float> %1414)
>  %1416 = fcmp uge float 0,000000e+00, %1415
>  %1417 = select i1 %1416, float 0,000000e+00, float %1415
>  %1418 = fmul float %1417, 0x3FE0000000000000
>  %1419 = fmul float %1240, 0x3FE0000000000000
>  %1420 = fadd float %1419, 0x3FE0000000000000
>  %1421 = fmul float %1244, 0x3FE0000000000000
>  %1422 = fadd float %1421, 0x3FE0000000000000
>  %1423 = insertelement <4 x float> undef, float %1420, i32 0
>  %1424 = insertelement <4 x float> %1423, float %1422, i32 1
>  %1425 = insertelement <4 x float> %1424, float %1323, i32 2
>  %1426 = insertelement <4 x float> %1425, float 0,000000e+00, i32 3
>  %1427 = extractelement <4 x float> %1426, i32 0
>  %1428 = extractelement <4 x float> %1426, i32 1
>  %1429 = insertelement <4 x float> undef, float %1427, i32 0
>  %1430 = insertelement <4 x float> %1429, float %1428, i32 1
>  %1431 = insertelement <4 x float> %1430, float undef, i32 2
>  %1432 = insertelement <4 x float> %1431, float undef, i32 3
>  %1433 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1432, i32 18, i32 2, i32 2)
>  %1434 = extractelement <4 x float> %1433, i32 0
>  %1435 = fcmp olt float %1242, %1434
>  %1436 = sext i1 %1435 to i32
>  %1437 = bitcast i32 %1436 to float
>  %1438 = bitcast float %1437 to i32
>  %1439 = icmp ne i32 %1438, 0
>  br i1 %1439, label %IF115, label %ENDIF114
>
>IF115:                                            ; preds = %ENDIF111
>  %1440 = fmul float %1242, %temp32.1
>  %1441 = fmul float %1242, %temp34.4
>  %1442 = fdiv float 0x3FF0000000000000, %temp33.1
>  %1443 = fmul float %1440, %1442
>  %1444 = fmul float %1441, %1442
>  %1445 = fsub float -0,000000e+00, %1443
>  %1446 = fadd float %1240, %1445
>  %1447 = fsub float -0,000000e+00, %1444
>  %1448 = fadd float %1244, %1447
>  %1449 = fmul float 0x3FD8000000000000, %1446
>  %1450 = fadd float %1449, 0x3FE0000000000000
>  %1451 = fmul float 0x3FD8000000000000, %1448
>  %1452 = fadd float %1451, 0x3FE0000000000000
>  %1453 = insertelement <4 x float> undef, float %1450, i32 0
>  %1454 = insertelement <4 x float> %1453, float %1452, i32 1
>  %1455 = insertelement <4 x float> %1454, float %1244, i32 2
>  %1456 = insertelement <4 x float> %1455, float 0,000000e+00, i32 3
>  %1457 = extractelement <4 x float> %1456, i32 0
>  %1458 = extractelement <4 x float> %1456, i32 1
>  %1459 = insertelement <4 x float> undef, float %1457, i32 0
>  %1460 = insertelement <4 x float> %1459, float %1458, i32 1
>  %1461 = insertelement <4 x float> %1460, float undef, i32 2
>  %1462 = insertelement <4 x float> %1461, float undef, i32 3
>  %1463 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1462, i32 17, i32 1, i32 2)
>  %1464 = extractelement <4 x float> %1463, i32 0
>  %1465 = fmul float %1464, 0x4010000000000000
>  %1466 = fmul float %1418, %1465
>  br label %ENDIF114
>
>ENDIF114:                                         ; preds = %ENDIF111, %IF115
>  %temp16.3 = phi float [ %1466, %IF115 ], [ %1418, %ENDIF111 ]
>  %1467 = fadd float %1294, %temp16.3
>  %1468 = fadd float %1295, %temp16.3
>  %1469 = fadd float %1296, %temp16.3
>  br label %ENDIF108
>
>IF118:                                            ; preds = %ELSE110
>  %1470 = call float @fabs(float %1375)
>  %1471 = fcmp olt float 0x3FEFF7CEE0000000, %1470
>  %1472 = sext i1 %1471 to i32
>  %1473 = bitcast i32 %1472 to float
>  %1474 = bitcast float %1473 to i32
>  %1475 = icmp ne i32 %1474, 0
>  br i1 %1475, label %IF121, label %ELSE122
>
>ELSE119:                                          ; preds = %ELSE110
>  %1476 = fcmp olt float %1377, 0x3FC5555560000000
>  %1477 = sext i1 %1476 to i32
>  %1478 = bitcast i32 %1477 to float
>  %1479 = bitcast float %1478 to i32
>  %1480 = icmp ne i32 %1479, 0
>  br i1 %1480, label %IF133, label %ELSE134
>
>IF121:                                            ; preds = %IF118
>  %1481 = fmul float %1377, 0x3FE0000000000000
>  %1482 = fadd float %1481, 0x3FF0000000000000
>  %1483 = fmul float %1379, 0x3FE0000000000000
>  %1484 = fadd float %1483, 0x3FE0000000000000
>  %1485 = insertelement <4 x float> undef, float %1482, i32 0
>  %1486 = insertelement <4 x float> %1485, float %1484, i32 1
>  %1487 = insertelement <4 x float> %1486, float %1360, i32 2
>  %1488 = insertelement <4 x float> %1487, float 0,000000e+00, i32 3
>  %1489 = extractelement <4 x float> %1488, i32 0
>  %1490 = extractelement <4 x float> %1488, i32 1
>  %1491 = insertelement <4 x float> undef, float %1489, i32 0
>  %1492 = insertelement <4 x float> %1491, float %1490, i32 1
>  %1493 = insertelement <4 x float> %1492, float undef, i32 2
>  %1494 = insertelement <4 x float> %1493, float undef, i32 3
>  %1495 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1494, i32 16, i32 0, i32 2)
>  %1496 = extractelement <4 x float> %1495, i32 0
>  %1497 = extractelement <4 x float> %1495, i32 1
>  %1498 = extractelement <4 x float> %1495, i32 2
>  %1499 = fsub float -0,000000e+00, %1375
>  br label %ENDIF120
>
>ELSE122:                                          ; preds = %IF118
>  %1500 = call float @fabs(float %1379)
>  %1501 = fcmp olt float 0x3FEFF7CEE0000000, %1500
>  %1502 = sext i1 %1501 to i32
>  %1503 = bitcast i32 %1502 to float
>  %1504 = bitcast float %1503 to i32
>  %1505 = icmp ne i32 %1504, 0
>  br i1 %1505, label %IF124, label %ELSE125
>
>ENDIF120:                                         ; preds = %IF124, %ELSE125, %IF121
>  %temp24.4 = phi float [ %1496, %IF121 ], [ %1588, %IF124 ], [ %1607, %ELSE125 ]
>  %temp25.4 = phi float [ %1497, %IF121 ], [ %1589, %IF124 ], [ %1608, %ELSE125 ]
>  %temp26.4 = phi float [ %1498, %IF121 ], [ %1590, %IF124 ], [ %1609, %ELSE125 ]
>  %temp28.4 = phi float [ %1499, %IF121 ], [ 0,000000e+00, %ELSE125 ], [ 0,000000e+00, %IF124 ]
>  %temp29.4 = phi float [ 0,000000e+00, %IF121 ], [ 0,000000e+00, %IF124 ], [ 0x3FF0000000000000, %ELSE125 ]
>  %temp30.4 = phi float [ 0,000000e+00, %IF121 ], [ %1591, %IF124 ], [ 0,000000e+00, %ELSE125 ]
>  %1506 = insertelement <4 x float> undef, float %1375, i32 0
>  %1507 = insertelement <4 x float> %1506, float %1377, i32 1
>  %1508 = insertelement <4 x float> %1507, float %1379, i32 2
>  %1509 = insertelement <4 x float> %1508, float 0,000000e+00, i32 3
>  %1510 = insertelement <4 x float> undef, float %1375, i32 0
>  %1511 = insertelement <4 x float> %1510, float %1377, i32 1
>  %1512 = insertelement <4 x float> %1511, float %1379, i32 2
>  %1513 = insertelement <4 x float> %1512, float 0,000000e+00, i32 3
>  %1514 = call float @llvm.AMDGPU.dp4(<4 x float> %1509, <4 x float> %1513)
>  %1515 = call float @llvm.AMDGPU.rsq(float %1514)
>  %1516 = fmul float 0x3FE0000000000000, %1515
>  %1517 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %1518 = extractelement <4 x float> %1517, i32 0
>  %1519 = fsub float -0,000000e+00, %1518
>  %1520 = fadd float %1375, %1519
>  %1521 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %1522 = extractelement <4 x float> %1521, i32 1
>  %1523 = fsub float -0,000000e+00, %1522
>  %1524 = fadd float %1377, %1523
>  %1525 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %1526 = extractelement <4 x float> %1525, i32 2
>  %1527 = fsub float -0,000000e+00, %1526
>  %1528 = fadd float %1379, %1527
>  %1529 = insertelement <4 x float> undef, float %1520, i32 0
>  %1530 = insertelement <4 x float> %1529, float %1524, i32 1
>  %1531 = insertelement <4 x float> %1530, float %1528, i32 2
>  %1532 = insertelement <4 x float> %1531, float 0,000000e+00, i32 3
>  %1533 = insertelement <4 x float> undef, float %1520, i32 0
>  %1534 = insertelement <4 x float> %1533, float %1524, i32 1
>  %1535 = insertelement <4 x float> %1534, float %1528, i32 2
>  %1536 = insertelement <4 x float> %1535, float 0,000000e+00, i32 3
>  %1537 = call float @llvm.AMDGPU.dp4(<4 x float> %1532, <4 x float> %1536)
>  %1538 = call float @llvm.AMDGPU.rsq(float %1537)
>  %1539 = fmul float %1538, %1537
>  %1540 = fsub float -0,000000e+00, %1537
>  %1541 = fcmp ult float %1540, 0,000000e+00
>  %1542 = select i1 %1541, float %1539, float 0,000000e+00
>  %1543 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %1544 = extractelement <4 x float> %1543, i32 0
>  %1545 = fdiv float 0x3FF0000000000000, %1544
>  %1546 = fmul float %1542, %1545
>  %1547 = call float @llvm.pow.f32(float %1546, float 0x4010000000000000)
>  %1548 = fdiv float 0x3FF0000000000000, %1547
>  %1549 = fmul float 0x3FECCCCCC0000000, %1548
>  %1550 = fsub float -0,000000e+00, %1549
>  %1551 = fadd float 0x3FF0000000000000, %1550
>  %1552 = fmul float %1516, %1551
>  %1553 = load <4 x float> addrspace(8)* null
>  %1554 = extractelement <4 x float> %1553, i32 0
>  %1555 = fsub float -0,000000e+00, %1554
>  %1556 = load <4 x float> addrspace(8)* null
>  %1557 = extractelement <4 x float> %1556, i32 1
>  %1558 = fsub float -0,000000e+00, %1557
>  %1559 = load <4 x float> addrspace(8)* null
>  %1560 = extractelement <4 x float> %1559, i32 2
>  %1561 = fsub float -0,000000e+00, %1560
>  %1562 = fmul float %1558, %1558
>  %1563 = fsub float -0,000000e+00, %1562
>  %1564 = fadd float 0x3FF0000000000000, %1563
>  %1565 = fmul float %1564, 0x3FE2024E20000000
>  %1566 = fsub float -0,000000e+00, %1565
>  %1567 = fadd float 0x3FF0000000000000, %1566
>  %1568 = fcmp olt float %1567, 0,000000e+00
>  %1569 = sext i1 %1568 to i32
>  %1570 = bitcast i32 %1569 to float
>  %1571 = bitcast float %1570 to i32
>  %1572 = icmp ne i32 %1571, 0
>  br i1 %1572, label %ENDIF126, label %ELSE128
>
>IF124:                                            ; preds = %ELSE122
>  %1573 = fmul float %1377, 0x3FE0000000000000
>  %1574 = fadd float %1573, 0x3FF0000000000000
>  %1575 = fmul float %1375, 0x3FE0000000000000
>  %1576 = fadd float %1575, 0x3FE0000000000000
>  %1577 = insertelement <4 x float> undef, float %1574, i32 0
>  %1578 = insertelement <4 x float> %1577, float %1576, i32 1
>  %1579 = insertelement <4 x float> %1578, float %temp34.0, i32 2
>  %1580 = insertelement <4 x float> %1579, float 0,000000e+00, i32 3
>  %1581 = extractelement <4 x float> %1580, i32 0
>  %1582 = extractelement <4 x float> %1580, i32 1
>  %1583 = insertelement <4 x float> undef, float %1581, i32 0
>  %1584 = insertelement <4 x float> %1583, float %1582, i32 1
>  %1585 = insertelement <4 x float> %1584, float undef, i32 2
>  %1586 = insertelement <4 x float> %1585, float undef, i32 3
>  %1587 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1586, i32 16, i32 0, i32 2)
>  %1588 = extractelement <4 x float> %1587, i32 0
>  %1589 = extractelement <4 x float> %1587, i32 1
>  %1590 = extractelement <4 x float> %1587, i32 2
>  %1591 = fsub float -0,000000e+00, %1379
>  br label %ENDIF120
>
>ELSE125:                                          ; preds = %ELSE122
>  %1592 = fmul float %1375, 0x3FE0000000000000
>  %1593 = fadd float %1592, 0x3FE0000000000000
>  %1594 = fmul float %1379, 0x3FE0000000000000
>  %1595 = fadd float %1594, 0x3FE0000000000000
>  %1596 = insertelement <4 x float> undef, float %1593, i32 0
>  %1597 = insertelement <4 x float> %1596, float %1595, i32 1
>  %1598 = insertelement <4 x float> %1597, float %temp34.0, i32 2
>  %1599 = insertelement <4 x float> %1598, float 0,000000e+00, i32 3
>  %1600 = extractelement <4 x float> %1599, i32 0
>  %1601 = extractelement <4 x float> %1599, i32 1
>  %1602 = insertelement <4 x float> undef, float %1600, i32 0
>  %1603 = insertelement <4 x float> %1602, float %1601, i32 1
>  %1604 = insertelement <4 x float> %1603, float undef, i32 2
>  %1605 = insertelement <4 x float> %1604, float undef, i32 3
>  %1606 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1605, i32 16, i32 0, i32 2)
>  %1607 = extractelement <4 x float> %1606, i32 0
>  %1608 = extractelement <4 x float> %1606, i32 1
>  %1609 = extractelement <4 x float> %1606, i32 2
>  br label %ENDIF120
>
>ELSE128:                                          ; preds = %ENDIF120
>  %1610 = call float @llvm.AMDGPU.rsq(float %1567)
>  %1611 = fmul float %1610, %1567
>  %1612 = fsub float -0,000000e+00, %1567
>  %1613 = fcmp ult float %1612, 0,000000e+00
>  %1614 = select i1 %1613, float %1611, float 0,000000e+00
>  %1615 = fmul float 0x3FE8018960000000, %1558
>  %1616 = fadd float %1615, %1614
>  %1617 = fmul float %1616, 0,000000e+00
>  %1618 = fmul float %1616, 0x3FF0000000000000
>  %1619 = fmul float %1616, 0,000000e+00
>  %1620 = fsub float -0,000000e+00, %1617
>  %1621 = fmul float 0x3FE8018960000000, %1555
>  %1622 = fadd float %1621, %1620
>  %1623 = fsub float -0,000000e+00, %1618
>  %1624 = fmul float 0x3FE8018960000000, %1558
>  %1625 = fadd float %1624, %1623
>  %1626 = fsub float -0,000000e+00, %1619
>  %1627 = fmul float 0x3FE8018960000000, %1561
>  %1628 = fadd float %1627, %1626
>  br label %ENDIF126
>
>ENDIF126:                                         ; preds = %ENDIF120, %ELSE128
>  %temp38.7 = phi float [ %1619, %ELSE128 ], [ %temp38.0, %ENDIF120 ]
>  %temp40.2 = phi float [ %1622, %ELSE128 ], [ 0,000000e+00, %ENDIF120 ]
>  %temp41.2 = phi float [ %1625, %ELSE128 ], [ 0,000000e+00, %ENDIF120 ]
>  %temp42.2 = phi float [ %1628, %ELSE128 ], [ 0,000000e+00, %ENDIF120 ]
>  %1629 = fsub float -0,000000e+00, %temp40.2
>  %1630 = fsub float -0,000000e+00, %temp41.2
>  %1631 = fsub float -0,000000e+00, %temp42.2
>  %1632 = insertelement <4 x float> undef, float %1629, i32 0
>  %1633 = insertelement <4 x float> %1632, float %1630, i32 1
>  %1634 = insertelement <4 x float> %1633, float %1631, i32 2
>  %1635 = insertelement <4 x float> %1634, float 0,000000e+00, i32 3
>  %1636 = insertelement <4 x float> undef, float %temp28.4, i32 0
>  %1637 = insertelement <4 x float> %1636, float %temp29.4, i32 1
>  %1638 = insertelement <4 x float> %1637, float %temp30.4, i32 2
>  %1639 = insertelement <4 x float> %1638, float 0,000000e+00, i32 3
>  %1640 = call float @llvm.AMDGPU.dp4(<4 x float> %1635, <4 x float> %1639)
>  %1641 = fcmp uge float 0,000000e+00, %1640
>  %1642 = select i1 %1641, float 0,000000e+00, float %1640
>  %1643 = fmul float %1375, 0x3FE0000000000000
>  %1644 = fadd float %1643, 0x3FE0000000000000
>  %1645 = fmul float %1379, 0x3FE0000000000000
>  %1646 = fadd float %1645, 0x3FE0000000000000
>  %1647 = insertelement <4 x float> undef, float %1644, i32 0
>  %1648 = insertelement <4 x float> %1647, float %1646, i32 1
>  %1649 = insertelement <4 x float> %1648, float %temp38.7, i32 2
>  %1650 = insertelement <4 x float> %1649, float 0,000000e+00, i32 3
>  %1651 = extractelement <4 x float> %1650, i32 0
>  %1652 = extractelement <4 x float> %1650, i32 1
>  %1653 = insertelement <4 x float> undef, float %1651, i32 0
>  %1654 = insertelement <4 x float> %1653, float %1652, i32 1
>  %1655 = insertelement <4 x float> %1654, float undef, i32 2
>  %1656 = insertelement <4 x float> %1655, float undef, i32 3
>  %1657 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1656, i32 18, i32 2, i32 2)
>  %1658 = extractelement <4 x float> %1657, i32 0
>  %1659 = fcmp olt float %1377, %1658
>  %1660 = sext i1 %1659 to i32
>  %1661 = bitcast i32 %1660 to float
>  %1662 = bitcast float %1661 to i32
>  %1663 = icmp ne i32 %1662, 0
>  br i1 %1663, label %IF130, label %ELSE131
>
>IF130:                                            ; preds = %ENDIF126
>  %1664 = fmul float %1377, %1629
>  %1665 = fmul float %1377, %1631
>  %1666 = fdiv float 0x3FF0000000000000, %1630
>  %1667 = fmul float %1664, %1666
>  %1668 = fmul float %1665, %1666
>  %1669 = fsub float -0,000000e+00, %1667
>  %1670 = fadd float %1375, %1669
>  %1671 = fsub float -0,000000e+00, %1668
>  %1672 = fadd float %1379, %1671
>  %1673 = fmul float 0x3FD8000000000000, %1670
>  %1674 = fadd float %1673, 0x3FE0000000000000
>  %1675 = fmul float 0x3FD8000000000000, %1672
>  %1676 = fadd float %1675, 0x3FE0000000000000
>  %1677 = insertelement <4 x float> undef, float %1674, i32 0
>  %1678 = insertelement <4 x float> %1677, float %1676, i32 1
>  %1679 = insertelement <4 x float> %1678, float %temp38.7, i32 2
>  %1680 = insertelement <4 x float> %1679, float 0,000000e+00, i32 3
>  %1681 = extractelement <4 x float> %1680, i32 0
>  %1682 = extractelement <4 x float> %1680, i32 1
>  %1683 = insertelement <4 x float> undef, float %1681, i32 0
>  %1684 = insertelement <4 x float> %1683, float %1682, i32 1
>  %1685 = insertelement <4 x float> %1684, float undef, i32 2
>  %1686 = insertelement <4 x float> %1685, float undef, i32 3
>  %1687 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1686, i32 17, i32 1, i32 2)
>  %1688 = extractelement <4 x float> %1687, i32 0
>  %1689 = extractelement <4 x float> %1687, i32 1
>  %1690 = fmul float %1642, %1688
>  %1691 = fmul float %1690, 0x4000000000000000
>  %1692 = fmul float %1691, %1689
>  br label %ENDIF129
>
>ELSE131:                                          ; preds = %ENDIF126
>  %1693 = fsub float -0,000000e+00, %1375
>  %1694 = fadd float 0xBFF0000000000000, %1693
>  %1695 = fsub float -0,000000e+00, %1377
>  %1696 = fadd float 0xBFF0000000000000, %1695
>  %1697 = fsub float -0,000000e+00, %1379
>  %1698 = fadd float 0xBFF0000000000000, %1697
>  %1699 = fdiv float 0x3FF0000000000000, %1629
>  %1700 = fdiv float 0x3FF0000000000000, %1630
>  %1701 = fdiv float 0x3FF0000000000000, %1631
>  %1702 = fmul float %1694, %1699
>  %1703 = fmul float %1696, %1700
>  %1704 = fmul float %1698, %1701
>  %1705 = fsub float -0,000000e+00, %1375
>  %1706 = fadd float 0x3FF0000000000000, %1705
>  %1707 = fsub float -0,000000e+00, %1377
>  %1708 = fadd float 0x4000000000000000, %1707
>  %1709 = fsub float -0,000000e+00, %1379
>  %1710 = fadd float 0x3FF0000000000000, %1709
>  %1711 = fdiv float 0x3FF0000000000000, %1629
>  %1712 = fdiv float 0x3FF0000000000000, %1630
>  %1713 = fdiv float 0x3FF0000000000000, %1631
>  %1714 = fmul float %1706, %1711
>  %1715 = fmul float %1708, %1712
>  %1716 = fmul float %1710, %1713
>  %1717 = fcmp uge float %1702, %1714
>  %1718 = select i1 %1717, float %1714, float %1702
>  %1719 = fcmp uge float %1703, %1715
>  %1720 = select i1 %1719, float %1715, float %1703
>  %1721 = fcmp uge float %1704, %1716
>  %1722 = select i1 %1721, float %1716, float %1704
>  %1723 = fcmp uge float %1702, %1714
>  %1724 = select i1 %1723, float %1702, float %1714
>  %1725 = fcmp uge float %1703, %1715
>  %1726 = select i1 %1725, float %1703, float %1715
>  %1727 = fcmp uge float %1704, %1716
>  %1728 = select i1 %1727, float %1704, float %1716
>  %1729 = fcmp uge float %1724, %1726
>  %1730 = select i1 %1729, float %1726, float %1724
>  %1731 = fcmp uge float %1730, %1728
>  %1732 = select i1 %1731, float %1728, float %1730
>  %1733 = fmul float %1630, %1732
>  %1734 = fadd float %1733, %1377
>  %1735 = fadd float %1734, 0xBFC5555560000000
>  %1736 = fmul float 0xC072089FC0000000, %1735
>  %1737 = fcmp uge float %1718, %1720
>  %1738 = select i1 %1737, float %1718, float %1720
>  %1739 = fcmp uge float %1738, %1722
>  %1740 = select i1 %1739, float %1738, float %1722
>  %1741 = fsub float -0,000000e+00, %1740
>  %1742 = fadd float %1732, %1741
>  %1743 = fmul float 0x4024000000000000, %1742
>  %1744 = fadd float %1743, 0x3FF0000000000000
>  %1745 = fdiv float 0x3FF0000000000000, %1744
>  %1746 = fmul float %1736, %1745
>  %1747 = call float @llvm.AMDIL.exp.(float %1746)
>  %1748 = fadd float 0x3FF0000000000000, %1747
>  %1749 = fdiv float 0x3FF0000000000000, %1748
>  %1750 = fmul float %1642, %1749
>  %1751 = fmul float %1750, 0x3FE0000000000000
>  br label %ENDIF129
>
>ENDIF129:                                         ; preds = %ELSE131, %IF130
>  %.sink152 = phi float [ %1692, %IF130 ], [ %1751, %ELSE131 ]
>  %1752 = fadd float %.sink152, %1552
>  %1753 = fmul float %temp24.4, %1752
>  %1754 = fmul float %temp25.4, %1752
>  %1755 = fmul float %temp26.4, %1752
>  br label %ENDIF108
>
>IF133:                                            ; preds = %ELSE119
>  %1756 = call float @fabs(float %1375)
>  %1757 = fcmp olt float 0x3FEFF7CEE0000000, %1756
>  %1758 = sext i1 %1757 to i32
>  %1759 = bitcast i32 %1758 to float
>  %1760 = bitcast float %1759 to i32
>  %1761 = icmp ne i32 %1760, 0
>  br i1 %1761, label %IF136, label %ELSE137
>
>ELSE134:                                          ; preds = %ELSE119
>  %1762 = load <4 x float> addrspace(8)* null
>  %1763 = extractelement <4 x float> %1762, i32 0
>  %1764 = load <4 x float> addrspace(8)* null
>  %1765 = extractelement <4 x float> %1764, i32 1
>  %1766 = load <4 x float> addrspace(8)* null
>  %1767 = extractelement <4 x float> %1766, i32 2
>  %1768 = insertelement <4 x float> undef, float %1763, i32 0
>  %1769 = insertelement <4 x float> %1768, float %1765, i32 1
>  %1770 = insertelement <4 x float> %1769, float %1767, i32 2
>  %1771 = insertelement <4 x float> %1770, float 0,000000e+00, i32 3
>  %1772 = insertelement <4 x float> undef, float %temp20.0, i32 0
>  %1773 = insertelement <4 x float> %1772, float %temp21.0, i32 1
>  %1774 = insertelement <4 x float> %1773, float %temp22.0, i32 2
>  %1775 = insertelement <4 x float> %1774, float 0,000000e+00, i32 3
>  %1776 = call float @llvm.AMDGPU.dp4(<4 x float> %1771, <4 x float> %1775)
>  %1777 = fcmp uge float 0,000000e+00, %1776
>  %1778 = select i1 %1777, float 0,000000e+00, float %1776
>  %1779 = call float @llvm.pow.f32(float %1778, float 0x40B3880000000000)
>  %1780 = insertelement <4 x float> undef, float %temp20.0, i32 0
>  %1781 = insertelement <4 x float> %1780, float %temp21.0, i32 1
>  %1782 = insertelement <4 x float> %1781, float %temp22.0, i32 2
>  %1783 = insertelement <4 x float> %1782, float 0,000000e+00, i32 3
>  %1784 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %1783)
>  %1785 = extractelement <4 x float> %1784, i32 0
>  %1786 = extractelement <4 x float> %1784, i32 1
>  %1787 = extractelement <4 x float> %1784, i32 2
>  %1788 = extractelement <4 x float> %1784, i32 3
>  %1789 = call float @fabs(float %1787)
>  %1790 = fdiv float 0x3FF0000000000000, %1789
>  %1791 = fmul float %1785, %1790
>  %1792 = fadd float %1791, 0x3FF8000000000000
>  %1793 = fmul float %1786, %1790
>  %1794 = fadd float %1793, 0x3FF8000000000000
>  %1795 = insertelement <4 x float> undef, float %1794, i32 0
>  %1796 = insertelement <4 x float> %1795, float %1792, i32 1
>  %1797 = insertelement <4 x float> %1796, float %1788, i32 2
>  %1798 = insertelement <4 x float> %1797, float %1794, i32 3
>  %1799 = extractelement <4 x float> %1798, i32 0
>  %1800 = extractelement <4 x float> %1798, i32 1
>  %1801 = extractelement <4 x float> %1798, i32 2
>  %1802 = extractelement <4 x float> %1798, i32 3
>  %1803 = insertelement <4 x float> undef, float %1799, i32 0
>  %1804 = insertelement <4 x float> %1803, float %1800, i32 1
>  %1805 = insertelement <4 x float> %1804, float %1801, i32 2
>  %1806 = insertelement <4 x float> %1805, float %1802, i32 3
>  %1807 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1806, i32 19, i32 3, i32 4)
>  %1808 = extractelement <4 x float> %1807, i32 0
>  %1809 = extractelement <4 x float> %1807, i32 1
>  %1810 = extractelement <4 x float> %1807, i32 2
>  %1811 = fmul float %1779, 0x4024000000000000
>  %1812 = fadd float %1811, %1808
>  %1813 = fmul float %1779, 0x4020000000000000
>  %1814 = fadd float %1813, %1809
>  %1815 = fmul float %1779, 0x4018000000000000
>  %1816 = fadd float %1815, %1810
>  br label %ENDIF108
>
>IF136:                                            ; preds = %IF133
>  %1817 = fmul float %1377, 0x3FE0000000000000
>  %1818 = fadd float %1817, 0x3FF0000000000000
>  %1819 = fmul float %1379, 0x3FE0000000000000
>  %1820 = fadd float %1819, 0x3FE0000000000000
>  %1821 = insertelement <4 x float> undef, float %1818, i32 0
>  %1822 = insertelement <4 x float> %1821, float %1820, i32 1
>  %1823 = insertelement <4 x float> %1822, float %1360, i32 2
>  %1824 = insertelement <4 x float> %1823, float 0,000000e+00, i32 3
>  %1825 = extractelement <4 x float> %1824, i32 0
>  %1826 = extractelement <4 x float> %1824, i32 1
>  %1827 = insertelement <4 x float> undef, float %1825, i32 0
>  %1828 = insertelement <4 x float> %1827, float %1826, i32 1
>  %1829 = insertelement <4 x float> %1828, float undef, i32 2
>  %1830 = insertelement <4 x float> %1829, float undef, i32 3
>  %1831 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1830, i32 16, i32 0, i32 2)
>  %1832 = extractelement <4 x float> %1831, i32 0
>  %1833 = extractelement <4 x float> %1831, i32 1
>  %1834 = extractelement <4 x float> %1831, i32 2
>  %1835 = fsub float -0,000000e+00, %1375
>  br label %ENDIF135
>
>ELSE137:                                          ; preds = %IF133
>  %1836 = call float @fabs(float %1379)
>  %1837 = fcmp olt float 0x3FEFF7CEE0000000, %1836
>  %1838 = sext i1 %1837 to i32
>  %1839 = bitcast i32 %1838 to float
>  %1840 = bitcast float %1839 to i32
>  %1841 = icmp ne i32 %1840, 0
>  br i1 %1841, label %IF139, label %ELSE140
>
>ENDIF135:                                         ; preds = %IF139, %ELSE140, %IF136
>  %temp24.6 = phi float [ %1832, %IF136 ], [ %1924, %IF139 ], [ %1943, %ELSE140 ]
>  %temp25.6 = phi float [ %1833, %IF136 ], [ %1925, %IF139 ], [ %1944, %ELSE140 ]
>  %temp26.6 = phi float [ %1834, %IF136 ], [ %1926, %IF139 ], [ %1945, %ELSE140 ]
>  %temp28.6 = phi float [ %1835, %IF136 ], [ 0,000000e+00, %ELSE140 ], [ 0,000000e+00, %IF139 ]
>  %temp29.6 = phi float [ 0,000000e+00, %IF136 ], [ 0,000000e+00, %IF139 ], [ 0x3FF0000000000000, %ELSE140 ]
>  %temp30.6 = phi float [ 0,000000e+00, %IF136 ], [ %1927, %IF139 ], [ 0,000000e+00, %ELSE140 ]
>  %1842 = insertelement <4 x float> undef, float %1375, i32 0
>  %1843 = insertelement <4 x float> %1842, float %1377, i32 1
>  %1844 = insertelement <4 x float> %1843, float %1379, i32 2
>  %1845 = insertelement <4 x float> %1844, float 0,000000e+00, i32 3
>  %1846 = insertelement <4 x float> undef, float %1375, i32 0
>  %1847 = insertelement <4 x float> %1846, float %1377, i32 1
>  %1848 = insertelement <4 x float> %1847, float %1379, i32 2
>  %1849 = insertelement <4 x float> %1848, float 0,000000e+00, i32 3
>  %1850 = call float @llvm.AMDGPU.dp4(<4 x float> %1845, <4 x float> %1849)
>  %1851 = call float @llvm.AMDGPU.rsq(float %1850)
>  %1852 = fmul float 0x3FE0000000000000, %1851
>  %1853 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %1854 = extractelement <4 x float> %1853, i32 0
>  %1855 = fsub float -0,000000e+00, %1854
>  %1856 = fadd float %1375, %1855
>  %1857 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %1858 = extractelement <4 x float> %1857, i32 1
>  %1859 = fsub float -0,000000e+00, %1858
>  %1860 = fadd float %1377, %1859
>  %1861 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %1862 = extractelement <4 x float> %1861, i32 2
>  %1863 = fsub float -0,000000e+00, %1862
>  %1864 = fadd float %1379, %1863
>  %1865 = insertelement <4 x float> undef, float %1856, i32 0
>  %1866 = insertelement <4 x float> %1865, float %1860, i32 1
>  %1867 = insertelement <4 x float> %1866, float %1864, i32 2
>  %1868 = insertelement <4 x float> %1867, float 0,000000e+00, i32 3
>  %1869 = insertelement <4 x float> undef, float %1856, i32 0
>  %1870 = insertelement <4 x float> %1869, float %1860, i32 1
>  %1871 = insertelement <4 x float> %1870, float %1864, i32 2
>  %1872 = insertelement <4 x float> %1871, float 0,000000e+00, i32 3
>  %1873 = call float @llvm.AMDGPU.dp4(<4 x float> %1868, <4 x float> %1872)
>  %1874 = call float @llvm.AMDGPU.rsq(float %1873)
>  %1875 = fmul float %1874, %1873
>  %1876 = fsub float -0,000000e+00, %1873
>  %1877 = fcmp ult float %1876, 0,000000e+00
>  %1878 = select i1 %1877, float %1875, float 0,000000e+00
>  %1879 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %1880 = extractelement <4 x float> %1879, i32 0
>  %1881 = fdiv float 0x3FF0000000000000, %1880
>  %1882 = fmul float %1878, %1881
>  %1883 = call float @llvm.pow.f32(float %1882, float 0x4010000000000000)
>  %1884 = fdiv float 0x3FF0000000000000, %1883
>  %1885 = fmul float 0x3FECCCCCC0000000, %1884
>  %1886 = fsub float -0,000000e+00, %1885
>  %1887 = fadd float 0x3FF0000000000000, %1886
>  %1888 = fmul float %1852, %1887
>  %1889 = load <4 x float> addrspace(8)* null
>  %1890 = extractelement <4 x float> %1889, i32 0
>  %1891 = fsub float -0,000000e+00, %1890
>  %1892 = load <4 x float> addrspace(8)* null
>  %1893 = extractelement <4 x float> %1892, i32 1
>  %1894 = fsub float -0,000000e+00, %1893
>  %1895 = load <4 x float> addrspace(8)* null
>  %1896 = extractelement <4 x float> %1895, i32 2
>  %1897 = fsub float -0,000000e+00, %1896
>  %1898 = fmul float %1894, %1894
>  %1899 = fsub float -0,000000e+00, %1898
>  %1900 = fadd float 0x3FF0000000000000, %1899
>  %1901 = fmul float %1900, 0x3FE2024E20000000
>  %1902 = fsub float -0,000000e+00, %1901
>  %1903 = fadd float 0x3FF0000000000000, %1902
>  %1904 = fcmp olt float %1903, 0,000000e+00
>  %1905 = sext i1 %1904 to i32
>  %1906 = bitcast i32 %1905 to float
>  %1907 = bitcast float %1906 to i32
>  %1908 = icmp ne i32 %1907, 0
>  br i1 %1908, label %ENDIF141, label %ELSE143
>
>IF139:                                            ; preds = %ELSE137
>  %1909 = fmul float %1377, 0x3FE0000000000000
>  %1910 = fadd float %1909, 0x3FF0000000000000
>  %1911 = fmul float %1375, 0x3FE0000000000000
>  %1912 = fadd float %1911, 0x3FE0000000000000
>  %1913 = insertelement <4 x float> undef, float %1910, i32 0
>  %1914 = insertelement <4 x float> %1913, float %1912, i32 1
>  %1915 = insertelement <4 x float> %1914, float %temp34.0, i32 2
>  %1916 = insertelement <4 x float> %1915, float 0,000000e+00, i32 3
>  %1917 = extractelement <4 x float> %1916, i32 0
>  %1918 = extractelement <4 x float> %1916, i32 1
>  %1919 = insertelement <4 x float> undef, float %1917, i32 0
>  %1920 = insertelement <4 x float> %1919, float %1918, i32 1
>  %1921 = insertelement <4 x float> %1920, float undef, i32 2
>  %1922 = insertelement <4 x float> %1921, float undef, i32 3
>  %1923 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1922, i32 16, i32 0, i32 2)
>  %1924 = extractelement <4 x float> %1923, i32 0
>  %1925 = extractelement <4 x float> %1923, i32 1
>  %1926 = extractelement <4 x float> %1923, i32 2
>  %1927 = fsub float -0,000000e+00, %1379
>  br label %ENDIF135
>
>ELSE140:                                          ; preds = %ELSE137
>  %1928 = fmul float %1375, 0x3FE0000000000000
>  %1929 = fadd float %1928, 0x3FE0000000000000
>  %1930 = fmul float %1379, 0x3FE0000000000000
>  %1931 = fadd float %1930, 0x3FE0000000000000
>  %1932 = insertelement <4 x float> undef, float %1929, i32 0
>  %1933 = insertelement <4 x float> %1932, float %1931, i32 1
>  %1934 = insertelement <4 x float> %1933, float %temp34.0, i32 2
>  %1935 = insertelement <4 x float> %1934, float 0,000000e+00, i32 3
>  %1936 = extractelement <4 x float> %1935, i32 0
>  %1937 = extractelement <4 x float> %1935, i32 1
>  %1938 = insertelement <4 x float> undef, float %1936, i32 0
>  %1939 = insertelement <4 x float> %1938, float %1937, i32 1
>  %1940 = insertelement <4 x float> %1939, float undef, i32 2
>  %1941 = insertelement <4 x float> %1940, float undef, i32 3
>  %1942 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1941, i32 16, i32 0, i32 2)
>  %1943 = extractelement <4 x float> %1942, i32 0
>  %1944 = extractelement <4 x float> %1942, i32 1
>  %1945 = extractelement <4 x float> %1942, i32 2
>  br label %ENDIF135
>
>ELSE143:                                          ; preds = %ENDIF135
>  %1946 = call float @llvm.AMDGPU.rsq(float %1903)
>  %1947 = fmul float %1946, %1903
>  %1948 = fsub float -0,000000e+00, %1903
>  %1949 = fcmp ult float %1948, 0,000000e+00
>  %1950 = select i1 %1949, float %1947, float 0,000000e+00
>  %1951 = fmul float 0x3FE8018960000000, %1894
>  %1952 = fadd float %1951, %1950
>  %1953 = fmul float %1952, 0,000000e+00
>  %1954 = fmul float %1952, 0x3FF0000000000000
>  %1955 = fmul float %1952, 0,000000e+00
>  %1956 = fsub float -0,000000e+00, %1953
>  %1957 = fmul float 0x3FE8018960000000, %1891
>  %1958 = fadd float %1957, %1956
>  %1959 = fsub float -0,000000e+00, %1954
>  %1960 = fmul float 0x3FE8018960000000, %1894
>  %1961 = fadd float %1960, %1959
>  %1962 = fsub float -0,000000e+00, %1955
>  %1963 = fmul float 0x3FE8018960000000, %1897
>  %1964 = fadd float %1963, %1962
>  br label %ENDIF141
>
>ENDIF141:                                         ; preds = %ENDIF135, %ELSE143
>  %temp38.8 = phi float [ %1955, %ELSE143 ], [ %temp38.0, %ENDIF135 ]
>  %temp40.3 = phi float [ %1958, %ELSE143 ], [ 0,000000e+00, %ENDIF135 ]
>  %temp41.3 = phi float [ %1961, %ELSE143 ], [ 0,000000e+00, %ENDIF135 ]
>  %temp42.3 = phi float [ %1964, %ELSE143 ], [ 0,000000e+00, %ENDIF135 ]
>  %1965 = fsub float -0,000000e+00, %temp40.3
>  %1966 = fsub float -0,000000e+00, %temp41.3
>  %1967 = fsub float -0,000000e+00, %temp42.3
>  %1968 = insertelement <4 x float> undef, float %1965, i32 0
>  %1969 = insertelement <4 x float> %1968, float %1966, i32 1
>  %1970 = insertelement <4 x float> %1969, float %1967, i32 2
>  %1971 = insertelement <4 x float> %1970, float 0,000000e+00, i32 3
>  %1972 = insertelement <4 x float> undef, float %temp28.6, i32 0
>  %1973 = insertelement <4 x float> %1972, float %temp29.6, i32 1
>  %1974 = insertelement <4 x float> %1973, float %temp30.6, i32 2
>  %1975 = insertelement <4 x float> %1974, float 0,000000e+00, i32 3
>  %1976 = call float @llvm.AMDGPU.dp4(<4 x float> %1971, <4 x float> %1975)
>  %1977 = fcmp uge float 0,000000e+00, %1976
>  %1978 = select i1 %1977, float 0,000000e+00, float %1976
>  %1979 = fmul float %1375, 0x3FE0000000000000
>  %1980 = fadd float %1979, 0x3FE0000000000000
>  %1981 = fmul float %1379, 0x3FE0000000000000
>  %1982 = fadd float %1981, 0x3FE0000000000000
>  %1983 = insertelement <4 x float> undef, float %1980, i32 0
>  %1984 = insertelement <4 x float> %1983, float %1982, i32 1
>  %1985 = insertelement <4 x float> %1984, float %temp38.8, i32 2
>  %1986 = insertelement <4 x float> %1985, float 0,000000e+00, i32 3
>  %1987 = extractelement <4 x float> %1986, i32 0
>  %1988 = extractelement <4 x float> %1986, i32 1
>  %1989 = insertelement <4 x float> undef, float %1987, i32 0
>  %1990 = insertelement <4 x float> %1989, float %1988, i32 1
>  %1991 = insertelement <4 x float> %1990, float undef, i32 2
>  %1992 = insertelement <4 x float> %1991, float undef, i32 3
>  %1993 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1992, i32 18, i32 2, i32 2)
>  %1994 = extractelement <4 x float> %1993, i32 0
>  %1995 = fcmp olt float %1377, %1994
>  %1996 = sext i1 %1995 to i32
>  %1997 = bitcast i32 %1996 to float
>  %1998 = bitcast float %1997 to i32
>  %1999 = icmp ne i32 %1998, 0
>  br i1 %1999, label %IF145, label %ELSE146
>
>IF145:                                            ; preds = %ENDIF141
>  %2000 = fmul float %1377, %1965
>  %2001 = fmul float %1377, %1967
>  %2002 = fdiv float 0x3FF0000000000000, %1966
>  %2003 = fmul float %2000, %2002
>  %2004 = fmul float %2001, %2002
>  %2005 = fsub float -0,000000e+00, %2003
>  %2006 = fadd float %1375, %2005
>  %2007 = fsub float -0,000000e+00, %2004
>  %2008 = fadd float %1379, %2007
>  %2009 = fmul float 0x3FD8000000000000, %2006
>  %2010 = fadd float %2009, 0x3FE0000000000000
>  %2011 = fmul float 0x3FD8000000000000, %2008
>  %2012 = fadd float %2011, 0x3FE0000000000000
>  %2013 = insertelement <4 x float> undef, float %2010, i32 0
>  %2014 = insertelement <4 x float> %2013, float %2012, i32 1
>  %2015 = insertelement <4 x float> %2014, float %temp38.8, i32 2
>  %2016 = insertelement <4 x float> %2015, float 0,000000e+00, i32 3
>  %2017 = extractelement <4 x float> %2016, i32 0
>  %2018 = extractelement <4 x float> %2016, i32 1
>  %2019 = insertelement <4 x float> undef, float %2017, i32 0
>  %2020 = insertelement <4 x float> %2019, float %2018, i32 1
>  %2021 = insertelement <4 x float> %2020, float undef, i32 2
>  %2022 = insertelement <4 x float> %2021, float undef, i32 3
>  %2023 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2022, i32 17, i32 1, i32 2)
>  %2024 = extractelement <4 x float> %2023, i32 0
>  %2025 = extractelement <4 x float> %2023, i32 1
>  %2026 = fmul float %1978, %2024
>  %2027 = fmul float %2026, 0x4000000000000000
>  %2028 = fmul float %2027, %2025
>  br label %ENDIF144
>
>ELSE146:                                          ; preds = %ENDIF141
>  %2029 = fsub float -0,000000e+00, %1375
>  %2030 = fadd float 0xBFF0000000000000, %2029
>  %2031 = fsub float -0,000000e+00, %1377
>  %2032 = fadd float 0xBFF0000000000000, %2031
>  %2033 = fsub float -0,000000e+00, %1379
>  %2034 = fadd float 0xBFF0000000000000, %2033
>  %2035 = fdiv float 0x3FF0000000000000, %1965
>  %2036 = fdiv float 0x3FF0000000000000, %1966
>  %2037 = fdiv float 0x3FF0000000000000, %1967
>  %2038 = fmul float %2030, %2035
>  %2039 = fmul float %2032, %2036
>  %2040 = fmul float %2034, %2037
>  %2041 = fsub float -0,000000e+00, %1375
>  %2042 = fadd float 0x3FF0000000000000, %2041
>  %2043 = fsub float -0,000000e+00, %1377
>  %2044 = fadd float 0x4000000000000000, %2043
>  %2045 = fsub float -0,000000e+00, %1379
>  %2046 = fadd float 0x3FF0000000000000, %2045
>  %2047 = fdiv float 0x3FF0000000000000, %1965
>  %2048 = fdiv float 0x3FF0000000000000, %1966
>  %2049 = fdiv float 0x3FF0000000000000, %1967
>  %2050 = fmul float %2042, %2047
>  %2051 = fmul float %2044, %2048
>  %2052 = fmul float %2046, %2049
>  %2053 = fcmp uge float %2038, %2050
>  %2054 = select i1 %2053, float %2050, float %2038
>  %2055 = fcmp uge float %2039, %2051
>  %2056 = select i1 %2055, float %2051, float %2039
>  %2057 = fcmp uge float %2040, %2052
>  %2058 = select i1 %2057, float %2052, float %2040
>  %2059 = fcmp uge float %2038, %2050
>  %2060 = select i1 %2059, float %2038, float %2050
>  %2061 = fcmp uge float %2039, %2051
>  %2062 = select i1 %2061, float %2039, float %2051
>  %2063 = fcmp uge float %2040, %2052
>  %2064 = select i1 %2063, float %2040, float %2052
>  %2065 = fcmp uge float %2060, %2062
>  %2066 = select i1 %2065, float %2062, float %2060
>  %2067 = fcmp uge float %2066, %2064
>  %2068 = select i1 %2067, float %2064, float %2066
>  %2069 = fmul float %1966, %2068
>  %2070 = fadd float %2069, %1377
>  %2071 = fadd float %2070, 0xBFC5555560000000
>  %2072 = fmul float 0xC072089FC0000000, %2071
>  %2073 = fcmp uge float %2054, %2056
>  %2074 = select i1 %2073, float %2054, float %2056
>  %2075 = fcmp uge float %2074, %2058
>  %2076 = select i1 %2075, float %2074, float %2058
>  %2077 = fsub float -0,000000e+00, %2076
>  %2078 = fadd float %2068, %2077
>  %2079 = fmul float 0x4024000000000000, %2078
>  %2080 = fadd float %2079, 0x3FF0000000000000
>  %2081 = fdiv float 0x3FF0000000000000, %2080
>  %2082 = fmul float %2072, %2081
>  %2083 = call float @llvm.AMDIL.exp.(float %2082)
>  %2084 = fadd float 0x3FF0000000000000, %2083
>  %2085 = fdiv float 0x3FF0000000000000, %2084
>  %2086 = fmul float %1978, %2085
>  %2087 = fmul float %2086, 0x3FE0000000000000
>  br label %ENDIF144
>
>ENDIF144:                                         ; preds = %ELSE146, %IF145
>  %.sink153 = phi float [ %2028, %IF145 ], [ %2087, %ELSE146 ]
>  %2088 = fadd float %.sink153, %1888
>  %2089 = fmul float %temp24.6, %2088
>  %2090 = fmul float %temp25.6, %2088
>  %2091 = fmul float %temp26.6, %2088
>  br label %ENDIF108
>
>IF148:                                            ; preds = %ENDIF108
>  %2092 = fmul float %temp8.2, 0x3FD0000000000000
>  %2093 = fmul float %temp9.0, 0x3FF0000000000000
>  %2094 = fmul float %temp10.0, 0x3FF4000000000000
>  br label %ENDIF147
>
>ENDIF147:                                         ; preds = %ENDIF108, %IF148
>  %temp8.5 = phi float [ %2092, %IF148 ], [ %temp8.2, %ENDIF108 ]
>  %temp9.3 = phi float [ %2093, %IF148 ], [ %temp9.0, %ENDIF108 ]
>  %temp10.3 = phi float [ %2094, %IF148 ], [ %temp10.0, %ENDIF108 ]
>  %2095 = call float @llvm.AMDGPU.lrp(float %222, float %temp4.5, float %temp8.5)
>  %2096 = call float @llvm.AMDGPU.lrp(float %222, float %temp5.3, float %temp9.3)
>  %2097 = call float @llvm.AMDGPU.lrp(float %222, float %temp6.3, float %temp10.3)
>  %2098 = insertelement <4 x float> undef, float %2095, i32 0
>  %2099 = insertelement <4 x float> %2098, float %2096, i32 1
>  %2100 = insertelement <4 x float> %2099, float %2097, i32 2
>  %2101 = insertelement <4 x float> %2100, float 0x3FF0000000000000, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %2101, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.R600.load.input(i32) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #1
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.lrp(float, float, float) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>attributes #2 = { nounwind readonly }
>attributes #3 = { readonly }
>KCrash: Application 'konqueror' crashing...
>KCrash: Attempting to start /usr/lib/kde4/libexec/drkonqi from kdeinit

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Attachments on bug 66331: 81647 | 87534 | 93202

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