Attachment 8885 Details for Bug 6942 – log of X session that involved suspend/resume

log of X session that involved suspend/resume

Xorg.0.log.old (text/plain), 106.09 KB, created by Chris Ball on 2007-02-27 07:45:18 UTC

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Creator: Chris Ball

Created: 2007-02-27 07:45:18 UTC

Size: 106.09 KB

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obsolete

>
>X Window System Version 7.2.0
>Release Date: 24 December 2006
>X Protocol Version 11, Revision 0, Release 7.2
>Build Operating System: Fedora Core 7 Red Hat, Inc.
>Current Operating System: Linux unity.printf.net 2.6.19-1.2917.fc7 #1 SMP Wed Jan 31 19:19:14 EST 2007 i686
>Build Date: 20 February 2007
>Build ID: xorg-x11-server 1.2.0-6.fc7 
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Module Loader present
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/var/log/Xorg.0.log", Time: Tue Feb 27 10:43:11 2007
>(==) Using config file: "/etc/X11/xorg.conf"
>(==) ServerLayout "Multihead layout"
>(**) |-->Screen "Screen0" (0)
>(**) |   |-->Monitor "Monitor0"
>(**) |   |-->Device "Videocard0"
>(**) |-->Input Device "Keyboard0"
>(**) |-->Input Device "Synaptics"
>(**) |-->Input Device "Mouse0"
>(**) FontPath set to:
>	unix/:7100
>(==) RgbPath set to "/usr/share/X11/rgb"
>(==) ModulePath set to "/usr/lib/xorg/modules"
>(**) Extension "Composite" is enabled
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) Loader magic: 0x81ee2e0
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.3
>	X.Org Video Driver: 1.0
>	X.Org XInput driver : 0.6
>	X.Org Server Extension : 0.3
>	X.Org Font Renderer : 0.5
>(II) Loader running on linux
>(II) LoadModule: "pcidata"
>(II) Loading /usr/lib/xorg/modules//libpcidata.so
>(II) Module pcidata: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.0
>(++) using VT number 7
>
>(II) PCI: PCI scan (all values are in hex)
>(II) PCI: 00:00:0: chip 8086,2590 card 1584,9800 rev 04 class 06,00,00 hdr 00
>(II) PCI: 00:02:0: chip 8086,2592 card 1584,9800 rev 04 class 03,00,00 hdr 80
>(II) PCI: 00:02:1: chip 8086,2792 card 1584,9800 rev 04 class 03,80,00 hdr 80
>(II) PCI: 00:1b:0: chip 8086,2668 card 1584,9050 rev 04 class 04,03,00 hdr 00
>(II) PCI: 00:1d:0: chip 8086,2658 card 1584,9050 rev 04 class 0c,03,00 hdr 80
>(II) PCI: 00:1d:1: chip 8086,2659 card 1584,9050 rev 04 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:2: chip 8086,265a card 1584,9050 rev 04 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:3: chip 8086,265b card 1584,9050 rev 04 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:7: chip 8086,265c card 1584,9051 rev 04 class 0c,03,20 hdr 00
>(II) PCI: 00:1e:0: chip 8086,2448 card 0000,0000 rev d4 class 06,04,01 hdr 01
>(II) PCI: 00:1f:0: chip 8086,2641 card 1584,9050 rev 04 class 06,01,00 hdr 80
>(II) PCI: 00:1f:2: chip 8086,2653 card 1584,9050 rev 04 class 01,01,80 hdr 00
>(II) PCI: 00:1f:3: chip 8086,266a card 1584,9050 rev 04 class 0c,05,00 hdr 00
>(II) PCI: 01:03:0: chip 104c,ac50 card c000,0000 rev 02 class 06,07,00 hdr 02
>(II) PCI: 01:07:0: chip 8086,4220 card 8086,2701 rev 05 class 02,80,00 hdr 00
>(II) PCI: 01:0a:0: chip 104c,8023 card 1584,7000 rev 00 class 0c,00,10 hdr 00
>(II) PCI: 01:0c:0: chip 10ec,8169 card 1584,9710 rev 10 class 02,00,00 hdr 00
>(II) PCI: End of PCI scan
>(II) Intel Bridge workaround enabled
>(II) Host-to-PCI bridge:
>(II) Bus 0: bridge is at (0:0:0), (0,0,2), BCTRL: 0x0008 (VGA_EN is set)
>(II) Bus 0 I/O range:
>	[0] -1	0	0x00000000 - 0x0000ffff (0x10000) IX[B]
>(II) Bus 0 non-prefetchable memory range:
>	[0] -1	0	0x00000000 - 0xffffffff (0x0) MX[B]
>(II) Bus 0 prefetchable memory range:
>	[0] -1	0	0x00000000 - 0xffffffff (0x0) MX[B]
>(II) Subtractive PCI-to-PCI bridge:
>(II) Bus 1: bridge is at (0:30:0), (0,1,5), BCTRL: 0x0006 (VGA_EN is cleared)
>(II) Bus 1 I/O range:
>	[0] -1	0	0x0000c000 - 0x0000c0ff (0x100) IX[B]
>	[1] -1	0	0x0000c400 - 0x0000c4ff (0x100) IX[B]
>	[2] -1	0	0x0000c800 - 0x0000c8ff (0x100) IX[B]
>	[3] -1	0	0x0000cc00 - 0x0000ccff (0x100) IX[B]
>	[4] -1	0	0x0000d000 - 0x0000d0ff (0x100) IX[B]
>	[5] -1	0	0x0000d400 - 0x0000d4ff (0x100) IX[B]
>	[6] -1	0	0x0000d800 - 0x0000d8ff (0x100) IX[B]
>	[7] -1	0	0x0000dc00 - 0x0000dcff (0x100) IX[B]
>(II) Bus 1 non-prefetchable memory range:
>	[0] -1	0	0xff400000 - 0xffcfffff (0x900000) MX[B]
>(II) Bus 1 prefetchable memory range:
>	[0] -1	0	0xbdf00000 - 0xbfefffff (0x2000000) MX[B]
>(II) PCI-to-ISA bridge:
>(II) Bus -1: bridge is at (0:31:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set)
>(II) PCI-to-CardBus bridge:
>(II) Bus 2: bridge is at (1:3:0), (1,2,5), BCTRL: 0x05c0 (VGA_EN is cleared)
>(II) Bus 2 I/O range:
>	[0] -1	0	0x0000c000 - 0x0000c0ff (0x100) IX[B]
>	[1] -1	0	0x0000c400 - 0x0000c4ff (0x100) IX[B]
>(--) PCI:*(0:2:0) Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller rev 4, Mem @ 0xffe80000/19, 0xd0000000/28, 0xffe40000/18, I/O @ 0xec00/3
>(--) PCI: (0:2:1) Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller rev 4, Mem @ 0x20000000/19
>(II) Addressable bus resource ranges are
>	[0] -1	0	0x00000000 - 0xffffffff (0x0) MX[B]
>	[1] -1	0	0x00000000 - 0x0000ffff (0x10000) IX[B]
>(II) OS-reported resource ranges:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>(II) Active PCI resource ranges:
>	[0] -1	0	0xffcffc00 - 0xffcffcff (0x100) MX[B]
>	[1] -1	0	0xffcf8000 - 0xffcfbfff (0x4000) MX[B]
>	[2] -1	0	0xffcff000 - 0xffcff7ff (0x800) MX[B]
>	[3] -1	0	0xffcfe000 - 0xffcfefff (0x1000) MX[B]
>	[4] -1	0	0xffe3fc00 - 0xffe3ffff (0x400) MX[B]
>	[5] -1	0	0xffe38000 - 0xffe3bfff (0x4000) MX[B]
>	[6] -1	0	0xffe40000 - 0xffe7ffff (0x40000) MX[B](B)
>	[7] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[8] -1	0	0xffe80000 - 0xffefffff (0x80000) MX[B](B)
>	[9] -1	0	0x0000d800 - 0x0000d8ff (0x100) IX[B]
>	[10] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[11] -1	0	0x0000ffa0 - 0x0000ffaf (0x10) IX[B]
>	[12] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[13] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[14] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[15] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[16] -1	0	0x0000e880 - 0x0000e89f (0x20) IX[B]
>	[17] -1	0	0x0000e800 - 0x0000e81f (0x20) IX[B]
>	[18] -1	0	0x0000e480 - 0x0000e49f (0x20) IX[B]
>	[19] -1	0	0x0000e400 - 0x0000e41f (0x20) IX[B]
>	[20] -1	0	0x0000ec00 - 0x0000ec07 (0x8) IX[B](B)
>(II) Inactive PCI resource ranges:
>	[0] -1	0	0x20000000 - 0x2007ffff (0x80000) MX[B](B)
>(II) Active PCI resource ranges after removing overlaps:
>	[0] -1	0	0xffcffc00 - 0xffcffcff (0x100) MX[B]
>	[1] -1	0	0xffcf8000 - 0xffcfbfff (0x4000) MX[B]
>	[2] -1	0	0xffcff000 - 0xffcff7ff (0x800) MX[B]
>	[3] -1	0	0xffcfe000 - 0xffcfefff (0x1000) MX[B]
>	[4] -1	0	0xffe3fc00 - 0xffe3ffff (0x400) MX[B]
>	[5] -1	0	0xffe38000 - 0xffe3bfff (0x4000) MX[B]
>	[6] -1	0	0xffe40000 - 0xffe7ffff (0x40000) MX[B](B)
>	[7] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[8] -1	0	0xffe80000 - 0xffefffff (0x80000) MX[B](B)
>	[9] -1	0	0x0000d800 - 0x0000d8ff (0x100) IX[B]
>	[10] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[11] -1	0	0x0000ffa0 - 0x0000ffaf (0x10) IX[B]
>	[12] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[13] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[14] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[15] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[16] -1	0	0x0000e880 - 0x0000e89f (0x20) IX[B]
>	[17] -1	0	0x0000e800 - 0x0000e81f (0x20) IX[B]
>	[18] -1	0	0x0000e480 - 0x0000e49f (0x20) IX[B]
>	[19] -1	0	0x0000e400 - 0x0000e41f (0x20) IX[B]
>	[20] -1	0	0x0000ec00 - 0x0000ec07 (0x8) IX[B](B)
>(II) Inactive PCI resource ranges after removing overlaps:
>	[0] -1	0	0x20000000 - 0x2007ffff (0x80000) MX[B](B)
>(II) OS-reported resource ranges after removing overlaps with PCI:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>(II) All system resource ranges:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xffcffc00 - 0xffcffcff (0x100) MX[B]
>	[5] -1	0	0xffcf8000 - 0xffcfbfff (0x4000) MX[B]
>	[6] -1	0	0xffcff000 - 0xffcff7ff (0x800) MX[B]
>	[7] -1	0	0xffcfe000 - 0xffcfefff (0x1000) MX[B]
>	[8] -1	0	0xffe3fc00 - 0xffe3ffff (0x400) MX[B]
>	[9] -1	0	0xffe38000 - 0xffe3bfff (0x4000) MX[B]
>	[10] -1	0	0xffe40000 - 0xffe7ffff (0x40000) MX[B](B)
>	[11] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[12] -1	0	0xffe80000 - 0xffefffff (0x80000) MX[B](B)
>	[13] -1	0	0x20000000 - 0x2007ffff (0x80000) MX[B](B)
>	[14] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[15] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[16] -1	0	0x0000d800 - 0x0000d8ff (0x100) IX[B]
>	[17] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[18] -1	0	0x0000ffa0 - 0x0000ffaf (0x10) IX[B]
>	[19] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[20] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[21] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[22] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[23] -1	0	0x0000e880 - 0x0000e89f (0x20) IX[B]
>	[24] -1	0	0x0000e800 - 0x0000e81f (0x20) IX[B]
>	[25] -1	0	0x0000e480 - 0x0000e49f (0x20) IX[B]
>	[26] -1	0	0x0000e400 - 0x0000e41f (0x20) IX[B]
>	[27] -1	0	0x0000ec00 - 0x0000ec07 (0x8) IX[B](B)
>(II) LoadModule: "dbe"
>(II) Loading /usr/lib/xorg/modules/extensions//libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "extmod"
>(II) Loading /usr/lib/xorg/modules/extensions//libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension SHAPE
>(II) Loading extension MIT-SUNDRY-NONSTANDARD
>(II) Loading extension BIG-REQUESTS
>(II) Loading extension SYNC
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XC-MISC
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-Misc
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension TOG-CUP
>(II) Loading extension Extended-Visual-Information
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "fbdevhw"
>(II) Loading /usr/lib/xorg/modules/linux//libfbdevhw.so
>(II) Module fbdevhw: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 0.0.2
>	ABI class: X.Org Video Driver, version 1.0
>(II) LoadModule: "glx"
>(II) Loading /usr/lib/xorg/modules/extensions//libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(==) AIGLX enabled
>(II) Loading extension GLX
>(II) LoadModule: "record"
>(II) Loading /usr/lib/xorg/modules/extensions//librecord.so
>(II) Module record: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.13.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension RECORD
>(II) LoadModule: "freetype"
>(II) Loading /usr/lib/xorg/modules/fonts//libfreetype.so
>(II) Module freetype: vendor="X.Org Foundation & the After X-TT Project"
>	compiled for 7.2.0, module version = 2.1.0
>	Module class: X.Org Font Renderer
>	ABI class: X.Org Font Renderer, version 0.5
>(II) Loading font FreeType
>(II) LoadModule: "type1"
>(II) Loading /usr/lib/xorg/modules/fonts//libtype1.so
>(II) Module type1: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.2
>	Module class: X.Org Font Renderer
>	ABI class: X.Org Font Renderer, version 0.5
>(II) Loading font Type1
>(II) LoadModule: "dri"
>(II) Loading /usr/lib/xorg/modules/extensions//libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "synaptics"
>(II) Loading /usr/lib/xorg/modules/input//synaptics_drv.so
>(II) Module synaptics: vendor="X.Org Foundation"
>	compiled for 4.3.99.902, module version = 1.0.0
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 0.6
>(II) LoadModule: "intel"
>(II) Loading /usr/lib/xorg/modules/drivers//intel_drv.so
>(II) Module i810: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.7.2
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 1.0
>(II) LoadModule: "kbd"
>(II) Loading /usr/lib/xorg/modules/input//kbd_drv.so
>(II) Module kbd: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.1.0
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 0.6
>(II) LoadModule: "synaptics"
>(II) Reloading /usr/lib/xorg/modules/input//synaptics_drv.so
>(II) LoadModule: "mouse"
>(II) Loading /usr/lib/xorg/modules/input//mouse_drv.so
>(II) Module mouse: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.1.1
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 0.6
>(II) INTEL: Driver for Intel Integrated Graphics Chipsets: i810,
>	i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G,
>	E7221 (i915), 915GM, 945G, 945GM, 965G, 965G, 965Q, 946GZ
>(II) Primary Device is: PCI 00:02:0
>(WW) INTEL: No matching Device section for instance (BusID PCI:0:2:1) found
>(--) Chipset 915GM found
>(II) resource ranges after xf86ClaimFixedResources() call:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xffcffc00 - 0xffcffcff (0x100) MX[B]
>	[5] -1	0	0xffcf8000 - 0xffcfbfff (0x4000) MX[B]
>	[6] -1	0	0xffcff000 - 0xffcff7ff (0x800) MX[B]
>	[7] -1	0	0xffcfe000 - 0xffcfefff (0x1000) MX[B]
>	[8] -1	0	0xffe3fc00 - 0xffe3ffff (0x400) MX[B]
>	[9] -1	0	0xffe38000 - 0xffe3bfff (0x4000) MX[B]
>	[10] -1	0	0xffe40000 - 0xffe7ffff (0x40000) MX[B](B)
>	[11] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[12] -1	0	0xffe80000 - 0xffefffff (0x80000) MX[B](B)
>	[13] -1	0	0x20000000 - 0x2007ffff (0x80000) MX[B](B)
>	[14] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[15] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[16] -1	0	0x0000d800 - 0x0000d8ff (0x100) IX[B]
>	[17] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[18] -1	0	0x0000ffa0 - 0x0000ffaf (0x10) IX[B]
>	[19] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[20] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[21] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[22] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[23] -1	0	0x0000e880 - 0x0000e89f (0x20) IX[B]
>	[24] -1	0	0x0000e800 - 0x0000e81f (0x20) IX[B]
>	[25] -1	0	0x0000e480 - 0x0000e49f (0x20) IX[B]
>	[26] -1	0	0x0000e400 - 0x0000e41f (0x20) IX[B]
>	[27] -1	0	0x0000ec00 - 0x0000ec07 (0x8) IX[B](B)
>(II) resource ranges after probing:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xffcffc00 - 0xffcffcff (0x100) MX[B]
>	[5] -1	0	0xffcf8000 - 0xffcfbfff (0x4000) MX[B]
>	[6] -1	0	0xffcff000 - 0xffcff7ff (0x800) MX[B]
>	[7] -1	0	0xffcfe000 - 0xffcfefff (0x1000) MX[B]
>	[8] -1	0	0xffe3fc00 - 0xffe3ffff (0x400) MX[B]
>	[9] -1	0	0xffe38000 - 0xffe3bfff (0x4000) MX[B]
>	[10] -1	0	0xffe40000 - 0xffe7ffff (0x40000) MX[B](B)
>	[11] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[12] -1	0	0xffe80000 - 0xffefffff (0x80000) MX[B](B)
>	[13] -1	0	0x20000000 - 0x2007ffff (0x80000) MX[B](B)
>	[14] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B]
>	[15] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B]
>	[16] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B]
>	[17] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[18] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[19] -1	0	0x0000d800 - 0x0000d8ff (0x100) IX[B]
>	[20] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[21] -1	0	0x0000ffa0 - 0x0000ffaf (0x10) IX[B]
>	[22] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[23] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[24] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[25] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[26] -1	0	0x0000e880 - 0x0000e89f (0x20) IX[B]
>	[27] -1	0	0x0000e800 - 0x0000e81f (0x20) IX[B]
>	[28] -1	0	0x0000e480 - 0x0000e49f (0x20) IX[B]
>	[29] -1	0	0x0000e400 - 0x0000e41f (0x20) IX[B]
>	[30] -1	0	0x0000ec00 - 0x0000ec07 (0x8) IX[B](B)
>	[31] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B]
>	[32] 0	0	0x000003c0 - 0x000003df (0x20) IS[B]
>(II) Setting vga for screen 0.
>(II) Loading sub module "int10"
>(II) LoadModule: "int10"
>(II) Loading /usr/lib/xorg/modules//libint10.so
>(II) Module int10: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) Loading sub module "vbe"
>(II) LoadModule: "vbe"
>(II) Loading /usr/lib/xorg/modules//libvbe.so
>(II) Module vbe: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.1.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>(II) Loading /usr/lib/xorg/modules//libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 1.0
>(**) INTEL(0): Depth 24, (--) framebuffer bpp 32
>(==) INTEL(0): RGB weight 888
>(==) INTEL(0): Default visual is TrueColor
>(**) INTEL(0): Option "accel" "On"
>(II) INTEL(0): Integrated Graphics Chipset: Intel(R) 915GM
>(--) INTEL(0): Chipset: "915GM"
>(--) INTEL(0): Linear framebuffer at 0xD0000000
>(--) INTEL(0): IO registers at addr 0xFFE80000
>(II) INTEL(0): Hardware state on X startup:
>(II) INTEL(0): DumpRegsBegin
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):            DPLL_TEST: 0x00010001 ()
>(II) INTEL(0):              D_STATE: 0x00000000
>(II) INTEL(0):        DSPCLK_GATE_D: 0x00001000
>(II) INTEL(0):       RENCLK_GATE_D1: 0x00000000
>(II) INTEL(0):       RENCLK_GATE_D2: 0x00000000
>(II) INTEL(0):                SDVOB: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):              SDVOUDI: 0x00000002
>(II) INTEL(0):               DSPARB: 0x00001d9c
>(II) INTEL(0):               DSPFW1: 0x00000000
>(II) INTEL(0):               DSPFW2: 0x00000000
>(II) INTEL(0):               DSPFW3: 0x00000000
>(II) INTEL(0):                 ADPA: 0x40008c18
>(II) INTEL(0):                 LVDS: 0xc000033c (enabled, pipe B)
>(II) INTEL(0):                 DVOA: 0x00000000
>(II) INTEL(0):                 DVOB: 0x00480000
>(II) INTEL(0):                 DVOC: 0x00480000
>(II) INTEL(0):          DVOA_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOB_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOC_SRCDIM: 0x00000000
>(II) INTEL(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) INTEL(0):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II) INTEL(0):         PFIT_CONTROL: 0x80006668
>(II) INTEL(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) INTEL(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) INTEL(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) INTEL(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) INTEL(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) INTEL(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPABASE: 0x00000000
>(II) INTEL(0):             DSPASURF: 0x00000000
>(II) INTEL(0):          DSPATILEOFF: 0x00000000
>(II) INTEL(0):            PIPEACONF: 0x00000000 (disabled, single-wide)
>(II) INTEL(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) INTEL(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_A: 0x04800000 (disabled, non-dvo, VGA, dac/serial mode, default clock, p1 = 8, p2 = 10)
>(II) INTEL(0):            DPLL_A_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) INTEL(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) INTEL(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) INTEL(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) INTEL(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) INTEL(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) INTEL(0):            BCLRPAT_A: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_A: 0x00000000
>(II) INTEL(0):             DSPBCNTR: 0x19000000 (disabled, pipe B)
>(II) INTEL(0):           DSPBSTRIDE: 0x00000a00 (2560 bytes)
>(II) INTEL(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPBSIZE: 0x018f02cf (720, 400)
>(II) INTEL(0):             DSPBBASE: 0x00000000
>(II) INTEL(0):             DSPBSURF: 0x00000000
>(II) INTEL(0):          DSPBTILEOFF: 0x00000000
>(II) INTEL(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) INTEL(0):             PIPEBSRC: 0x027f018f (640, 400)
>(II) INTEL(0):                 FPB0: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
>(II) INTEL(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_B: 0x99026000 (enabled, non-dvo, LVDS mode, unknown clock, p1 = 2, p2 = 7)
>(II) INTEL(0):            DPLL_B_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_B: 0x081f077f (1920 active, 2080 total)
>(II) INTEL(0):             HBLANK_B: 0x081f077f (1920 start, 2080 end)
>(II) INTEL(0):              HSYNC_B: 0x07cf07af (1968 start, 2000 end)
>(II) INTEL(0):             VTOTAL_B: 0x04d204af (1200 active, 1235 total)
>(II) INTEL(0):             VBLANK_B: 0x04d204af (1200 start, 1235 end)
>(II) INTEL(0):              VSYNC_B: 0x04bb04b1 (1202 start, 1212 end)
>(II) INTEL(0):            BCLRPAT_B: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_B: 0x00000000
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):             VGACNTRL: 0x22c4008e (enabled)
>(II) INTEL(0):               TV_CTL: 0x30000000
>(II) INTEL(0):               TV_DAC: 0x70000000
>(II) INTEL(0):             TV_CSC_Y: 0x00000000
>(II) INTEL(0):            TV_CSC_Y2: 0x00000000
>(II) INTEL(0):             TV_CSC_U: 0x00000000
>(II) INTEL(0):            TV_CSC_U2: 0x00000000
>(II) INTEL(0):             TV_CSC_V: 0x00000000
>(II) INTEL(0):            TV_CSC_V2: 0x00000000
>(II) INTEL(0):         TV_CLR_KNOBS: 0x00000000
>(II) INTEL(0):         TV_CLR_LEVEL: 0x00000000
>(II) INTEL(0):           TV_H_CTL_1: 0x00000000
>(II) INTEL(0):           TV_H_CTL_2: 0x00000000
>(II) INTEL(0):           TV_H_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_1: 0x00000000
>(II) INTEL(0):           TV_V_CTL_2: 0x00000000
>(II) INTEL(0):           TV_V_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_4: 0x00000000
>(II) INTEL(0):           TV_V_CTL_5: 0x00000000
>(II) INTEL(0):           TV_V_CTL_6: 0x00000000
>(II) INTEL(0):           TV_V_CTL_7: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_1: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_2: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_3: 0x00000000
>(II) INTEL(0):           TV_WIN_POS: 0x00000000
>(II) INTEL(0):          TV_WIN_SIZE: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_1: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_2: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_3: 0x00000000
>(II) INTEL(0):        TV_CC_CONTROL: 0x00000000
>(II) INTEL(0):           TV_CC_DATA: 0x00000000
>(II) INTEL(0):          TV_H_LUMA_0: 0x00000000
>(II) INTEL(0):         TV_H_LUMA_59: 0x00000000
>(II) INTEL(0):        TV_H_CHROMA_0: 0x00000000
>(II) INTEL(0):       TV_H_CHROMA_59: 0x00000000
>(II) INTEL(0):                 SR00: 0x03
>(II) INTEL(0):                 SR01: 0x00
>(II) INTEL(0):                 SR02: 0x03
>(II) INTEL(0):                 SR03: 0x00
>(II) INTEL(0):                 SR04: 0x02
>(II) INTEL(0):                 SR05: 0x00
>(II) INTEL(0):                 SR06: 0x00
>(II) INTEL(0):                 SR07: 0x00
>(II) INTEL(0):                  MSR: 0x67
>(II) INTEL(0):                 CR00: 0x5f
>(II) INTEL(0):                 CR01: 0x4f
>(II) INTEL(0):                 CR02: 0x50
>(II) INTEL(0):                 CR03: 0x82
>(II) INTEL(0):                 CR04: 0x55
>(II) INTEL(0):                 CR05: 0x81
>(II) INTEL(0):                 CR06: 0xbf
>(II) INTEL(0):                 CR07: 0x1f
>(II) INTEL(0):                 CR08: 0x00
>(II) INTEL(0):                 CR09: 0x4f
>(II) INTEL(0):                 CR0a: 0x1f
>(II) INTEL(0):                 CR0b: 0x1e
>(II) INTEL(0):                 CR0c: 0x00
>(II) INTEL(0):                 CR0d: 0x00
>(II) INTEL(0):                 CR0e: 0x07
>(II) INTEL(0):                 CR0f: 0x80
>(II) INTEL(0):                 CR10: 0x9c
>(II) INTEL(0):                 CR11: 0x8e
>(II) INTEL(0):                 CR12: 0x8f
>(II) INTEL(0):                 CR13: 0x28
>(II) INTEL(0):                 CR14: 0x1f
>(II) INTEL(0):                 CR15: 0x96
>(II) INTEL(0):                 CR16: 0xb9
>(II) INTEL(0):                 CR17: 0xa3
>(II) INTEL(0):                 CR18: 0xff
>(II) INTEL(0):                 CR19: 0x00
>(II) INTEL(0):                 CR1a: 0x00
>(II) INTEL(0):                 CR1b: 0x00
>(II) INTEL(0):                 CR1c: 0x00
>(II) INTEL(0):                 CR1d: 0x00
>(II) INTEL(0):                 CR1e: 0x00
>(II) INTEL(0):                 CR1f: 0x00
>(II) INTEL(0):                 CR20: 0x00
>(II) INTEL(0):                 CR21: 0x00
>(II) INTEL(0):                 CR22: 0x20
>(II) INTEL(0):                 CR23: 0x00
>(II) INTEL(0):                 CR24: 0x00
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(EE) INTEL(0): ref out of range
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe B dot 0 n 2 m1 14 m2 8 p1 2 p2 5
>(II) INTEL(0): DumpRegsEnd
>(II) INTEL(0): 2 display pipes available.
>(II) INTEL(0): detected 256 kB GTT.
>(II) INTEL(0): detected 7932 kB stolen memory.
>(II) INTEL(0): Kernel reported 110336 total, 1 used
>(II) INTEL(0): I830CheckAvailableMemory: 441340 kB available
>(==) INTEL(0): Using XAA for acceleration
>(II) INTEL(0): Will try to reserve 32768 kiB of AGP aperture space
>	for the DRM memory manager.
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"
>(II) Loading /usr/lib/xorg/modules//libddc.so
>(II) Module ddc: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"
>(II) Loading /usr/lib/xorg/modules//libi2c.so
>(II) Module i2c: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.2.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) INTEL(0): I2C bus "CRTDDC_A" initialized.
>(II) Loading sub module "int10"
>(II) LoadModule: "int10"
>(II) Reloading /usr/lib/xorg/modules//libint10.so
>(II) INTEL(0): initializing int10
>(WW) INTEL(0): Bad V_BIOS checksum
>(II) INTEL(0): Primary V_BIOS segment is: 0xc000
>(II) INTEL(0): VESA BIOS detected
>(II) INTEL(0): VESA VBE Version 3.0
>(II) INTEL(0): VESA VBE Total Mem: 7872 kB
>(II) INTEL(0): VESA VBE OEM: Intel(r)915GM/910ML/915MS Graphics Chip Accelerated VGA BIOS
>(II) INTEL(0): VESA VBE OEM Software Rev: 1.0
>(II) INTEL(0): VESA VBE OEM Vendor: Intel Corporation
>(II) INTEL(0): VESA VBE OEM Product: Intel(r)915GM/910ML/915MS Graphics Controller
>(II) INTEL(0): VESA VBE OEM Product Rev: Hardware Version 0.0
>(II) INTEL(0): Found BDB block type 254
>(II) INTEL(0): Found BDB block type 1
>(II) INTEL(0): Found BDB block type 254
>(II) INTEL(0): Found BDB block type 2
>(II) INTEL(0): Found BDB block type 3
>(II) INTEL(0): Found BDB block type 4
>(II) INTEL(0): Found BDB block type 254
>(II) INTEL(0): Found BDB block type 6
>(II) INTEL(0): Found BDB block type 7
>(II) INTEL(0): Found BDB block type 8
>(II) INTEL(0): Found BDB block type 10
>(II) INTEL(0): Found BDB block type 11
>(II) INTEL(0): Found BDB block type 12
>(II) INTEL(0): Found BDB block type 13
>(II) INTEL(0): Found BDB block type 14
>(II) INTEL(0): Found BDB block type 15
>(II) INTEL(0): Found BDB block type 16
>(II) INTEL(0): Found BDB block type 17
>(II) INTEL(0): Found BDB block type 18
>(II) INTEL(0): Found BDB block type 19
>(II) INTEL(0): Found BDB block type 20
>(II) INTEL(0): Found BDB block type 21
>(II) INTEL(0): Found BDB block type 22
>(II) INTEL(0): Found BDB block type 23
>(II) INTEL(0): Found BDB block type 24
>(II) INTEL(0): Found BDB block type 25
>(II) INTEL(0): Found BDB block type 26
>(II) INTEL(0): Found BDB block type 40
>(II) INTEL(0): Found BDB block type 41
>(II) INTEL(0): Found panel mode in BIOS VBT tables:
>(II) INTEL(0): Modeline "1920x1200"x0.0  154.00  1920 1968 2000 2080  1200 1202 1212 1235 (74.0 kHz)
>(II) INTEL(0): Found BDB block type 42
>(II) INTEL(0): Found BDB block type 43
>(II) INTEL(0): Found BDB block type 44
>(II) INTEL(0): I2C bus "LVDSDDC_C" initialized.
>(II) INTEL(0): I2C bus "SDVOCTRL_E for SDVOB" initialized.
>(II) INTEL(0): I2C device "SDVOCTRL_E for SDVOB:SDVO Controller B" registered at address 0x70.
>(II) INTEL(0): No SDVO device found on SDVOB
>(II) INTEL(0): I2C device "SDVOCTRL_E for SDVOB:SDVO Controller B" removed.
>(II) INTEL(0): I2C bus "SDVOCTRL_E for SDVOB" removed.
>(II) INTEL(0): I2C bus "SDVOCTRL_E for SDVOC" initialized.
>(II) INTEL(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" registered at address 0x72.
>(II) INTEL(0): No SDVO device found on SDVOC
>(II) INTEL(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" removed.
>(II) INTEL(0): I2C bus "SDVOCTRL_E for SDVOC" removed.
>chosen: dotclock 31488 vco 1574400 ((m 82, m1 13, m2 5), n 3, (p 50, p1 5, p2 10))
>clock regs: 0x94100000, 0x00030d05
>chosen: dotclock 107520 vco 2150400 ((m 112, m1 19, m2 5), n 3, (p 20, p1 2, p2 10))
>clock regs: 0x94020003, 0x00031305
>(II) INTEL(0): No TV connection detected
>chosen: dotclock 31488 vco 1574400 ((m 82, m1 13, m2 5), n 3, (p 50, p1 5, p2 10))
>clock regs: 0x94100000, 0x00030d05
>(II) INTEL(0): I2C device "LVDSDDC_C:ddc2" registered at address 0xA0.
>(II) INTEL(0): I2C device "LVDSDDC_C:ddc2" removed.
>(II) INTEL(0): EDID for output LVDS
>(II) INTEL(0): Manufacturer: LCD  Model: 5000  Serial#: 16843009
>(II) INTEL(0): Year: 2006  Week: 4
>(II) INTEL(0): EDID Version: 1.3
>(II) INTEL(0): Digital Display Input
>(II) INTEL(0): Max H-Image Size [cm]: horiz.: 33  vert.: 21
>(II) INTEL(0): Gamma: 2.20
>(II) INTEL(0): No DPMS capabilities specified; RGB/Color Display
>(II) INTEL(0): First detailed timing is preferred mode
>(II) INTEL(0): redX: 0.610 redY: 0.340   greenX: 0.296 greenY: 0.550
>(II) INTEL(0): blueX: 0.155 blueY: 0.122   whiteX: 0.313 whiteY: 0.329
>(II) INTEL(0): Manufacturer's mask: 0
>(II) INTEL(0): Supported Future Video Modes:
>(II) INTEL(0): #0: hsize: 1920  vsize 1200  refresh: 60  vid: 209
>(II) INTEL(0): Supported additional Video Mode:
>(II) INTEL(0): clock: 151.8 MHz   Image Size:  332 x 208 mm
>(II) INTEL(0): h_active: 1920  h_sync: 2020  h_sync_end 2052 h_blank_end 2184 h_border: 0
>(II) INTEL(0): v_active: 1200  v_sync: 1202  v_sync_end 1208 v_blanking: 1235 v_border: 0
>(II) INTEL(0):  LTD154EZ0S
>(II) INTEL(0):  10R6A001490
>(II) INTEL(0): EDID (in hex):
>(II) INTEL(0): 	00ffffffffffff003064005001010101
>(II) INTEL(0): 	04100103802115780a4fd59c574b8c27
>(II) INTEL(0): 	1f5054000000d1000101010101010101
>(II) INTEL(0): 	010101010101473b800871b023406420
>(II) INTEL(0): 	26004cd0100000180000000f00082810
>(II) INTEL(0): 	38011102111e20081200000000fe004c
>(II) INTEL(0): 	5444313534455a30530a2020000000fe
>(II) INTEL(0): 	0031305236413030313439300a20002f
>(II) INTEL(0): EDID vendor "LCD", prod id 20480
>(II) INTEL(0): Not using default mode "640x350" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "640x400" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "720x400" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "640x480" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "640x480" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "640x480" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "800x600" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "800x600" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "800x600" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "800x600" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1024x768" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1152x864" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1280x960" (hsync out of range)
>(II) INTEL(0): Not using default mode "1280x960" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1280x1024" (hsync out of range)
>(II) INTEL(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1280x1024" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1600x1200" (hsync out of range)
>(II) INTEL(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1600x1200" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1792x1344" (hsync out of range)
>(II) INTEL(0): Not using default mode "1792x1344" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1856x1392" (hsync out of range)
>(II) INTEL(0): Not using default mode "1856x1392" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1920x1440" (hsync out of range)
>(II) INTEL(0): Not using default mode "1920x1440" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "832x624" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1152x768" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1152x864" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1152x864" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1152x864" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1152x864" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1152x864" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1280x720" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1280x720" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1280x720" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1280x800" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1280x800" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1280x800" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1280x768" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1280x768" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1280x768" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1400x1050" (hsync out of range)
>(II) INTEL(0): Not using default mode "1400x1050" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1400x1050" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1400x1050" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1400x1050" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1400x1050" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1440x900" (hsync out of range)
>(II) INTEL(0): Not using default mode "1600x1024" (hsync out of range)
>(II) INTEL(0): Not using default mode "1680x1050" (hsync out of range)
>(II) INTEL(0): Not using default mode "1680x1050" (hsync out of range)
>(II) INTEL(0): Not using default mode "1680x1050" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1680x1050" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1680x1050" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1920x1080" (hsync out of range)
>(II) INTEL(0): Not using default mode "1920x1080" (hsync out of range)
>(II) INTEL(0): Not using default mode "1920x1080" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1920x1080" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1920x1080" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1920x1200" (hsync out of range)
>(II) INTEL(0): Not using default mode "1920x1200" (hsync out of range)
>(II) INTEL(0): Not using default mode "1920x1200" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1920x1200" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1920x1200" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1920x1200" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "1920x1440" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "2048x1536" (hsync out of range)
>(II) INTEL(0): Not using default mode "2048x1536" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "2048x1536" (vrefresh out of range)
>(II) INTEL(0): Not using default mode "2560x1600" (width too large for virtual size)
>(II) INTEL(0): Printing probed modes for output LVDS
>(II) INTEL(0): Modeline "1920x1200"x56.3  151.75  1920 2020 2052 2184  1200 1202 1208 1235 -hsync -vsync (69.5 kHz)
>(II) INTEL(0): Modeline "1920x1200"x59.9  193.25  1920 2056 2256 2592  1200 1203 1209 1245 -hsync +vsync (74.6 kHz)
>(II) INTEL(0): Modeline "1360x768"x59.8   84.75  1360 1432 1568 1776  768 771 781 798 -hsync +vsync (47.7 kHz)
>(II) INTEL(0): Modeline "1360x768"x60.0   72.00  1360 1408 1440 1520  768 771 781 790 +hsync -vsync (47.4 kHz)
>(II) INTEL(0): Modeline "1280x800"x60.0   83.46  1280 1344 1480 1680  800 801 804 828 -hsync +vsync (49.7 kHz)
>(II) INTEL(0): Modeline "1152x864"x60.0   81.62  1152 1216 1336 1520  864 865 868 895 -hsync +vsync (53.7 kHz)
>(II) INTEL(0): Modeline "1280x768"x60.0   80.14  1280 1344 1480 1680  768 769 772 795 -hsync +vsync (47.7 kHz)
>(II) INTEL(0): Modeline "1280x720"x60.0   74.48  1280 1336 1472 1664  720 721 724 746 -hsync +vsync (44.8 kHz)
>(II) INTEL(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) INTEL(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) INTEL(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>chosen: dotclock 107520 vco 2150400 ((m 112, m1 19, m2 5), n 3, (p 20, p1 2, p2 10))
>clock regs: 0x94020003, 0x00031305
>(II) INTEL(0): No TV connection detected
>(II) INTEL(0): Monitoring connected displays enabled
>(--) INTEL(0): Pre-allocated VideoRam: 7932 kByte
>(==) INTEL(0): Potential VideoRam: 262144 kByte
>(==) INTEL(0): video overlay key set to 0x101fe
>(**) INTEL(0): page flipping disabled
>(==) INTEL(0): Using gamma correction (1.0, 1.0, 1.0)
>(WW) INTEL(0): DRM memory manager will be disabled
>	to make room for video memory
>(II) INTEL(0): Increasing the scanline pitch to allow tiling mode (1920 -> 2048).
>(==) INTEL(0): VideoRam: 72704 KB
>(==) INTEL(0): DPI set to (75, 75)
>(II) Loading sub module "fb"
>(II) LoadModule: "fb"
>(II) Loading /usr/lib/xorg/modules//libfb.so
>(II) Module fb: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.0.0
>	ABI class: X.Org ANSI C Emulation, version 0.3
>(II) Loading sub module "xaa"
>(II) LoadModule: "xaa"
>(II) Loading /usr/lib/xorg/modules//libxaa.so
>(II) Module xaa: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.2.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) Loading sub module "ramdac"
>(II) LoadModule: "ramdac"
>(II) Loading /usr/lib/xorg/modules//libramdac.so
>(II) Module ramdac: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 1.0
>(II) INTEL(0): Comparing regs from server start up to After PreInit
>(WW) INTEL(0): Register 0x61200 (PP_STATUS) changed from 0xc0000008 to 0xd0000009
>(WW) INTEL(0): PP_STATUS before: on, ready, sequencing idle
>(WW) INTEL(0): PP_STATUS after: on, ready, sequencing on
>(II) Loading sub module "shadow"
>(II) LoadModule: "shadow"
>(II) Loading /usr/lib/xorg/modules//libshadow.so
>(II) Module shadow: vendor="X.Org Foundation"
>	compiled for 7.2.0, module version = 1.1.0
>	ABI class: X.Org ANSI C Emulation, version 0.3
>(==) Depth 24 pixmap format is 32 bpp
>(II) do I need RAC?  No, I don't.
>(II) resource ranges after preInit:
>	[0] 0	0	0xffe40000 - 0xffe7ffff (0x40000) MS[B]
>	[1] 0	0	0xd0000000 - 0xdfffffff (0x10000000) MS[B]
>	[2] 0	0	0xffe80000 - 0xffefffff (0x80000) MS[B]
>	[3] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[4] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[5] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[6] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[7] -1	0	0xffcffc00 - 0xffcffcff (0x100) MX[B]
>	[8] -1	0	0xffcf8000 - 0xffcfbfff (0x4000) MX[B]
>	[9] -1	0	0xffcff000 - 0xffcff7ff (0x800) MX[B]
>	[10] -1	0	0xffcfe000 - 0xffcfefff (0x1000) MX[B]
>	[11] -1	0	0xffe3fc00 - 0xffe3ffff (0x400) MX[B]
>	[12] -1	0	0xffe38000 - 0xffe3bfff (0x4000) MX[B]
>	[13] -1	0	0xffe40000 - 0xffe7ffff (0x40000) MX[B](B)
>	[14] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[15] -1	0	0xffe80000 - 0xffefffff (0x80000) MX[B](B)
>	[16] -1	0	0x20000000 - 0x2007ffff (0x80000) MX[B](B)
>	[17] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B](OprD)
>	[18] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD)
>	[19] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B](OprD)
>	[20] 0	0	0x0000ec00 - 0x0000ec07 (0x8) IS[B]
>	[21] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[22] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[23] -1	0	0x0000d800 - 0x0000d8ff (0x100) IX[B]
>	[24] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[25] -1	0	0x0000ffa0 - 0x0000ffaf (0x10) IX[B]
>	[26] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[27] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[28] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[29] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[30] -1	0	0x0000e880 - 0x0000e89f (0x20) IX[B]
>	[31] -1	0	0x0000e800 - 0x0000e81f (0x20) IX[B]
>	[32] -1	0	0x0000e480 - 0x0000e49f (0x20) IX[B]
>	[33] -1	0	0x0000e400 - 0x0000e41f (0x20) IX[B]
>	[34] -1	0	0x0000ec00 - 0x0000ec07 (0x8) IX[B](B)
>	[35] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B](OprU)
>	[36] 0	0	0x000003c0 - 0x000003df (0x20) IS[B](OprU)
>(II) INTEL(0): Allocated 128 kB for the ring buffer at 0x0
>(II) INTEL(0): Allocating at least 4620 scanlines for pixmap cache
>(II) INTEL(0): Initial framebuffer allocation size: 52320 kByte
>(II) INTEL(0): Allocated 4 kB for HW cursor at 0xffff000 (0x0c4a6000)
>(II) INTEL(0): Allocated 16 kB for HW (ARGB) cursor at 0xfffb000 (0x1762c000)
>(II) INTEL(0): Allocated 4 kB for HW cursor at 0xfffa000 (0x10bcc000)
>(II) INTEL(0): Allocated 16 kB for HW (ARGB) cursor at 0xfff6000 (0x10ba8000)
>(II) INTEL(0): Allocated 4 kB for Overlay registers at 0xfff5000 (0x106c9000).
>(II) INTEL(0): Allocated 64 kB for the scratch buffer at 0xffe5000
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 8, (OK)
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 8, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 8, (OK)
>drmOpenByBusid: drmOpenMinor returns 8
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(II) INTEL(0): [drm] DRM interface version 1.3
>(II) INTEL(0): [drm] created "i915" driver at busid "pci:0000:00:02.0"
>(II) INTEL(0): [drm] added 8192 byte SAREA at 0xe04f8000
>(II) INTEL(0): [drm] mapped SAREA 0xe04f8000 to 0xb7ef3000
>(II) INTEL(0): [drm] framebuffer handle = 0xd0020000
>(II) INTEL(0): [drm] added 1 reserved context for kernel
>(II) INTEL(0): Allocated 32 kB for the logical context at 0xffdd000.
>(II) INTEL(0): Allocated 9600 kB for the back buffer at 0xe000000.
>(II) INTEL(0): Allocated 9600 kB for the depth buffer at 0xd000000.
>(II) INTEL(0): Allocated 912 kB for textures at 0xcf1c000
>(II) INTEL(0): 0x9180410: Memory at offset 0x00020000, size 52320 kBytes
>(II) INTEL(0): 0x9182fb4: Memory at offset 0x0ffff000, size 4 kBytes
>(II) INTEL(0): 0x9182fd4: Memory at offset 0x0fffb000, size 16 kBytes
>(II) INTEL(0): 0x918347c: Memory at offset 0x0fffa000, size 4 kBytes
>(II) INTEL(0): 0x918349c: Memory at offset 0x0fff6000, size 16 kBytes
>(II) INTEL(0): 0x918222c: Memory at offset 0x00000000, size 128 kBytes
>(II) INTEL(0): 0x9180450: Memory at offset 0x0ffe5000, size 64 kBytes
>(II) INTEL(0): 0x9181e38: Memory at offset 0x0fff5000, size 4 kBytes
>(II) INTEL(0): 0x9180584: Memory at offset 0x0ffdd000, size 32 kBytes
>(II) INTEL(0): 0x91805a4: Memory at offset 0x0e000000, size 9600 kBytes
>(II) INTEL(0): 0x91805c4: Memory at offset 0x0d000000, size 9600 kBytes
>(II) INTEL(0): 0x91805e4: Memory at offset 0x0cf1c000, size 912 kBytes
>(II) INTEL(0): Activating tiled memory for the back buffer.
>(II) INTEL(0): Activating tiled memory for the depth buffer.
>(II) INTEL(0): [drm] Registers = 0xffe80000
>(II) INTEL(0): [drm] ring buffer = 0xd0000000
>(II) INTEL(0): [drm] init sarea width,height = 1920 x 1200 (pitch 2048)
>(II) INTEL(0): [drm] Mapping front buffer
>(II) INTEL(0): [drm] Front Buffer = 0x2a004000
>(II) INTEL(0): [drm] Back Buffer = 0xde000000
>(II) INTEL(0): [drm] Depth Buffer = 0xdd000000
>(II) INTEL(0): [drm] textures = 0xdcf1c000
>(II) INTEL(0): [drm] Initialized kernel agp heap manager, 933888
>(II) INTEL(0): [dri] visual configs initialized
>(==) INTEL(0): Write-combining range (0xd0000000,0x10000000)
>(II) INTEL(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000
>(II) INTEL(0): xf86BindGARTMemory: bind key 10 at 0x007bf000 (pgoffset 1983)
>(II) INTEL(0): xf86BindGARTMemory: bind key 0 at 0x0ffff000 (pgoffset 65535)
>(II) INTEL(0): xf86BindGARTMemory: bind key 1 at 0x0fffb000 (pgoffset 65531)
>(II) INTEL(0): xf86BindGARTMemory: bind key 2 at 0x0fffa000 (pgoffset 65530)
>(II) INTEL(0): xf86BindGARTMemory: bind key 3 at 0x0fff6000 (pgoffset 65526)
>(II) INTEL(0): xf86BindGARTMemory: bind key 5 at 0x0ffe5000 (pgoffset 65509)
>(II) INTEL(0): xf86BindGARTMemory: bind key 4 at 0x0fff5000 (pgoffset 65525)
>(II) INTEL(0): xf86BindGARTMemory: bind key 6 at 0x0ffdd000 (pgoffset 65501)
>(II) INTEL(0): xf86BindGARTMemory: bind key 7 at 0x0e000000 (pgoffset 57344)
>(II) INTEL(0): xf86BindGARTMemory: bind key 8 at 0x0d000000 (pgoffset 53248)
>(II) INTEL(0): xf86BindGARTMemory: bind key 9 at 0x0cf1c000 (pgoffset 53020)
>(WW) INTEL(0): No pipe mode list for pipe 0,continuing with desired mode
>chosen: dotclock 153600 vco 2150400 ((m 112, m1 19, m2 5), n 3, (p 14, p1 2, p2 7))
>clock regs: 0x99020000, 0x00031305
>(II) INTEL(0): DumpRegsBegin
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):            DPLL_TEST: 0x00010001 ()
>(II) INTEL(0):              D_STATE: 0x00000000
>(II) INTEL(0):        DSPCLK_GATE_D: 0x00001000
>(II) INTEL(0):       RENCLK_GATE_D1: 0x00000000
>(II) INTEL(0):       RENCLK_GATE_D2: 0x00000000
>(II) INTEL(0):                SDVOB: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):              SDVOUDI: 0x00000002
>(II) INTEL(0):               DSPARB: 0x00001d9c
>(II) INTEL(0):               DSPFW1: 0x00000000
>(II) INTEL(0):               DSPFW2: 0x00000000
>(II) INTEL(0):               DSPFW3: 0x00000000
>(II) INTEL(0):                 ADPA: 0x40008c18
>(II) INTEL(0):                 LVDS: 0xc000033c (enabled, pipe B)
>(II) INTEL(0):                 DVOA: 0x00000000
>(II) INTEL(0):                 DVOB: 0x00480000
>(II) INTEL(0):                 DVOC: 0x00480000
>(II) INTEL(0):          DVOA_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOB_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOC_SRCDIM: 0x00000000
>(II) INTEL(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) INTEL(0):            PP_STATUS: 0xd0000009 (on, ready, sequencing on)
>(II) INTEL(0):         PFIT_CONTROL: 0x80000668
>(II) INTEL(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) INTEL(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) INTEL(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) INTEL(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) INTEL(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) INTEL(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPABASE: 0x00000000
>(II) INTEL(0):             DSPASURF: 0x00000000
>(II) INTEL(0):          DSPATILEOFF: 0x00000000
>(II) INTEL(0):            PIPEACONF: 0x00000000 (disabled, single-wide)
>(II) INTEL(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) INTEL(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_A: 0x04800000 (disabled, non-dvo, VGA, dac/serial mode, default clock, p1 = 8, p2 = 10)
>(II) INTEL(0):            DPLL_A_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) INTEL(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) INTEL(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) INTEL(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) INTEL(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) INTEL(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) INTEL(0):            BCLRPAT_A: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_A: 0x00000000
>(II) INTEL(0):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II) INTEL(0):           DSPBSTRIDE: 0x00002000 (8192 bytes)
>(II) INTEL(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPBSIZE: 0x04af077f (1920, 1200)
>(II) INTEL(0):             DSPBBASE: 0x00020000
>(II) INTEL(0):             DSPBSURF: 0x00000000
>(II) INTEL(0):          DSPBTILEOFF: 0x00000000
>(II) INTEL(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) INTEL(0):             PIPEBSRC: 0x077f04af (1920, 1200)
>(II) INTEL(0):                 FPB0: 0x00031305 (n = 3, m1 = 19, m2 = 5)
>(II) INTEL(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_B: 0x99020000 (enabled, non-dvo, LVDS mode, default clock, p1 = 2, p2 = 7)
>(II) INTEL(0):            DPLL_B_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_B: 0x081f077f (1920 active, 2080 total)
>(II) INTEL(0):             HBLANK_B: 0x081f077f (1920 start, 2080 end)
>(II) INTEL(0):              HSYNC_B: 0x07cf07af (1968 start, 2000 end)
>(II) INTEL(0):             VTOTAL_B: 0x04d204af (1200 active, 1235 total)
>(II) INTEL(0):             VBLANK_B: 0x04d204af (1200 start, 1235 end)
>(II) INTEL(0):              VSYNC_B: 0x04bb04b1 (1202 start, 1212 end)
>(II) INTEL(0):            BCLRPAT_B: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_B: 0x00000000
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):             VGACNTRL: 0x80000000 (disabled)
>(II) INTEL(0):               TV_CTL: 0x30000000
>(II) INTEL(0):               TV_DAC: 0x70000000
>(II) INTEL(0):             TV_CSC_Y: 0x00000000
>(II) INTEL(0):            TV_CSC_Y2: 0x00000000
>(II) INTEL(0):             TV_CSC_U: 0x00000000
>(II) INTEL(0):            TV_CSC_U2: 0x00000000
>(II) INTEL(0):             TV_CSC_V: 0x00000000
>(II) INTEL(0):            TV_CSC_V2: 0x00000000
>(II) INTEL(0):         TV_CLR_KNOBS: 0x00000000
>(II) INTEL(0):         TV_CLR_LEVEL: 0x00000000
>(II) INTEL(0):           TV_H_CTL_1: 0x00000000
>(II) INTEL(0):           TV_H_CTL_2: 0x00000000
>(II) INTEL(0):           TV_H_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_1: 0x00000000
>(II) INTEL(0):           TV_V_CTL_2: 0x00000000
>(II) INTEL(0):           TV_V_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_4: 0x00000000
>(II) INTEL(0):           TV_V_CTL_5: 0x00000000
>(II) INTEL(0):           TV_V_CTL_6: 0x00000000
>(II) INTEL(0):           TV_V_CTL_7: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_1: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_2: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_3: 0x00000000
>(II) INTEL(0):           TV_WIN_POS: 0x00000000
>(II) INTEL(0):          TV_WIN_SIZE: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_1: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_2: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_3: 0x00000000
>(II) INTEL(0):        TV_CC_CONTROL: 0x00000000
>(II) INTEL(0):           TV_CC_DATA: 0x00000000
>(II) INTEL(0):          TV_H_LUMA_0: 0x00000000
>(II) INTEL(0):         TV_H_LUMA_59: 0x00000000
>(II) INTEL(0):        TV_H_CHROMA_0: 0x00000000
>(II) INTEL(0):       TV_H_CHROMA_59: 0x00000000
>(II) INTEL(0):                 SR00: 0x03
>(II) INTEL(0):                 SR01: 0x00
>(II) INTEL(0):                 SR02: 0x03
>(II) INTEL(0):                 SR03: 0x00
>(II) INTEL(0):                 SR04: 0x02
>(II) INTEL(0):                 SR05: 0x00
>(II) INTEL(0):                 SR06: 0x00
>(II) INTEL(0):                 SR07: 0x00
>(II) INTEL(0):                  MSR: 0x67
>(II) INTEL(0):                 CR00: 0x5f
>(II) INTEL(0):                 CR01: 0x4f
>(II) INTEL(0):                 CR02: 0x50
>(II) INTEL(0):                 CR03: 0x82
>(II) INTEL(0):                 CR04: 0x55
>(II) INTEL(0):                 CR05: 0x81
>(II) INTEL(0):                 CR06: 0xbf
>(II) INTEL(0):                 CR07: 0x1f
>(II) INTEL(0):                 CR08: 0x00
>(II) INTEL(0):                 CR09: 0x4f
>(II) INTEL(0):                 CR0a: 0x1f
>(II) INTEL(0):                 CR0b: 0x1e
>(II) INTEL(0):                 CR0c: 0x00
>(II) INTEL(0):                 CR0d: 0x00
>(II) INTEL(0):                 CR0e: 0x07
>(II) INTEL(0):                 CR0f: 0x80
>(II) INTEL(0):                 CR10: 0x9c
>(II) INTEL(0):                 CR11: 0x0e
>(II) INTEL(0):                 CR12: 0x8f
>(II) INTEL(0):                 CR13: 0x28
>(II) INTEL(0):                 CR14: 0x1f
>(II) INTEL(0):                 CR15: 0x96
>(II) INTEL(0):                 CR16: 0xb9
>(II) INTEL(0):                 CR17: 0xa3
>(II) INTEL(0):                 CR18: 0xff
>(II) INTEL(0):                 CR19: 0x00
>(II) INTEL(0):                 CR1a: 0x00
>(II) INTEL(0):                 CR1b: 0x00
>(II) INTEL(0):                 CR1c: 0x00
>(II) INTEL(0):                 CR1d: 0x00
>(II) INTEL(0):                 CR1e: 0x00
>(II) INTEL(0):                 CR1f: 0x00
>(II) INTEL(0):                 CR20: 0x00
>(II) INTEL(0):                 CR21: 0x00
>(II) INTEL(0):                 CR22: 0x00
>(II) INTEL(0):                 CR23: 0x00
>(II) INTEL(0):                 CR24: 0x00
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe B dot 215040 n 3 m1 19 m2 5 p1 2 p2 5
>(II) INTEL(0): DumpRegsEnd
>(II) INTEL(0): Output configuration:
>(II) INTEL(0):   Pipe A is off
>(II) INTEL(0):   Display plane A is now disabled and connected to pipe A.
>(II) INTEL(0):   Pipe B is on
>(II) INTEL(0):   Display plane B is now enabled and connected to pipe B.
>(II) INTEL(0):   Output VGA is connected to pipe none
>(II) INTEL(0):   Output LVDS is connected to pipe B
>(II) INTEL(0):   Output TV is connected to pipe none
>(**) INTEL(0): Option "XaaNoOffscreenPixmaps" "True"
>(II) INTEL(0): Using XFree86 Acceleration Architecture (XAA)
>	Screen to screen bit blits
>	Solid filled rectangles
>	8x8 mono pattern filled rectangles
>	Indirect CPU to Screen color expansion
>	Solid Horizontal and Vertical Lines
>	Setting up tile and stipple cache:
>		32 128x128 slots
>		32 256x256 slots
>		16 512x512 slots
>(==) INTEL(0): Backing store disabled
>(==) INTEL(0): Silken mouse enabled
>(II) INTEL(0): Initializing HW Cursor
>(**) Option "dpms"
>(**) INTEL(0): DPMS enabled
>(II) INTEL(0): Set up textured video
>(II) INTEL(0): Set up overlay video
>(II) INTEL(0): X context handle = 0x1
>(II) INTEL(0): [drm] installed DRM signal handler
>(II) INTEL(0): [DRI] installation complete
>(II) INTEL(0): [drm] dma control initialized, using IRQ 20
>(II) INTEL(0): direct rendering: Enabled
>(II) INTEL(0): RandR enabled, ignore the following RandR disabled message.
>(II) INTEL(0): Rotating to 0 degrees
>(--) RandR disabled
>(II) Initializing built-in extension MIT-SHM
>(II) Initializing built-in extension XInputExtension
>(II) Initializing built-in extension XTEST
>(II) Initializing built-in extension XKEYBOARD
>(II) Initializing built-in extension XC-APPGROUP
>(II) Initializing built-in extension XAccessControlExtension
>(II) Initializing built-in extension SECURITY
>(II) Initializing built-in extension XINERAMA
>(II) Initializing built-in extension XFIXES
>(II) Initializing built-in extension XFree86-Bigfont
>(II) Initializing built-in extension RENDER
>(II) Initializing built-in extension RANDR
>(II) Initializing built-in extension COMPOSITE
>(II) Initializing built-in extension DAMAGE
>(II) Initializing built-in extension XEVIE
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 9, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 9, (OK)
>drmOpenByBusid: drmOpenMinor returns 9
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(WW) AIGLX: 3D driver claims to not support visual 0x23
>(WW) AIGLX: 3D driver claims to not support visual 0x24
>(WW) AIGLX: 3D driver claims to not support visual 0x25
>(WW) AIGLX: 3D driver claims to not support visual 0x26
>(WW) AIGLX: 3D driver claims to not support visual 0x27
>(WW) AIGLX: 3D driver claims to not support visual 0x28
>(WW) AIGLX: 3D driver claims to not support visual 0x29
>(WW) AIGLX: 3D driver claims to not support visual 0x2a
>(WW) AIGLX: 3D driver claims to not support visual 0x2b
>(WW) AIGLX: 3D driver claims to not support visual 0x2c
>(WW) AIGLX: 3D driver claims to not support visual 0x2d
>(WW) AIGLX: 3D driver claims to not support visual 0x2e
>(WW) AIGLX: 3D driver claims to not support visual 0x2f
>(WW) AIGLX: 3D driver claims to not support visual 0x30
>(WW) AIGLX: 3D driver claims to not support visual 0x31
>(WW) AIGLX: 3D driver claims to not support visual 0x32
>(II) AIGLX: Loaded and initialized /usr/lib/dri/i915_dri.so
>(II) GLX: Initialized DRI GL provider for screen 0
>(II) INTEL(0): Setting screen physical size to 650 x 406
>(**) Option "CoreKeyboard"
>(**) Keyboard0: Core Keyboard
>(**) Option "Protocol" "standard"
>(**) Keyboard0: Protocol: standard
>(**) Option "AutoRepeat" "500 30"
>(**) Option "XkbRules" "xorg"
>(**) Keyboard0: XkbRules: "xorg"
>(**) Option "XkbModel" "pc105"
>(**) Keyboard0: XkbModel: "pc105"
>(**) Option "XkbLayout" "us"
>(**) Keyboard0: XkbLayout: "us"
>(**) Option "CustomKeycodes" "off"
>(**) Keyboard0: CustomKeycodes disabled
>(II) Synaptics touchpad driver version 0.14.4 (1404)
>(--) Synaptics auto-dev sets device to /dev/input/event0
>(**) Option "Device" "/dev/input/event0"
>(**) Option "MaxTapTime" "0"
>(**) Option "MaxTapMove" "0"
>(**) Option "VertScrollDelta" "0"
>(**) Option "HorizScrollDelta" "0"
>(--) Synaptics touchpad found
>(**) Option "CorePointer"
>(**) Synaptics: Core Pointer
>(**) Option "Protocol" "IMPS/2"
>(**) Mouse0: Device: "/dev/input/mice"
>(**) Mouse0: Protocol: "IMPS/2"
>(**) Option "AlwaysCore"
>(**) Mouse0: always reports core events
>(**) Option "Device" "/dev/input/mice"
>(**) Option "Emulate3Buttons" "yes"
>(**) Mouse0: Emulate3Buttons, Emulate3Timeout: 50
>(**) Option "ZAxisMapping" "4 5"
>(**) Mouse0: ZAxisMapping: buttons 4 and 5
>(**) Mouse0: Buttons: 9
>(II) XINPUT: Adding extended input device "Mouse0" (type: MOUSE)
>(II) XINPUT: Adding extended input device "Synaptics" (type: MOUSE)
>(II) XINPUT: Adding extended input device "Keyboard0" (type: KEYBOARD)
>Synaptics DeviceInit called
>SynapticsCtrl called.
>Synaptics DeviceOn called
>(--) Synaptics auto-dev sets device to /dev/input/event0
>(**) Option "Device" "/dev/input/event0"
>(--) Synaptics touchpad found
>(II) Mouse0: ps2EnableDataReporting: succeeded
>Synaptics DeviceOff called
>(II) AIGLX: Suspending AIGLX clients for VT switch
>(II) INTEL(0): Comparing regs from server start up to After LeaveVT
>(II) INTEL(0): DumpRegsBegin
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):            DPLL_TEST: 0x00010001 ()
>(II) INTEL(0):              D_STATE: 0x00000000
>(II) INTEL(0):        DSPCLK_GATE_D: 0x00001000
>(II) INTEL(0):       RENCLK_GATE_D1: 0x00000000
>(II) INTEL(0):       RENCLK_GATE_D2: 0x00000000
>(II) INTEL(0):                SDVOB: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):              SDVOUDI: 0x00000002
>(II) INTEL(0):               DSPARB: 0x00001d9c
>(II) INTEL(0):               DSPFW1: 0x00000000
>(II) INTEL(0):               DSPFW2: 0x00000000
>(II) INTEL(0):               DSPFW3: 0x00000000
>(II) INTEL(0):                 ADPA: 0x40008c18
>(II) INTEL(0):                 LVDS: 0xc000033c (enabled, pipe B)
>(II) INTEL(0):                 DVOA: 0x00000000
>(II) INTEL(0):                 DVOB: 0x00480000
>(II) INTEL(0):                 DVOC: 0x00480000
>(II) INTEL(0):          DVOA_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOB_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOC_SRCDIM: 0x00000000
>(II) INTEL(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) INTEL(0):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II) INTEL(0):         PFIT_CONTROL: 0x80006668
>(II) INTEL(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) INTEL(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) INTEL(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) INTEL(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) INTEL(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) INTEL(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPABASE: 0x00000000
>(II) INTEL(0):             DSPASURF: 0x00000000
>(II) INTEL(0):          DSPATILEOFF: 0x00000000
>(II) INTEL(0):            PIPEACONF: 0x00000000 (disabled, single-wide)
>(II) INTEL(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) INTEL(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_A: 0x04800000 (disabled, non-dvo, VGA, dac/serial mode, default clock, p1 = 8, p2 = 10)
>(II) INTEL(0):            DPLL_A_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) INTEL(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) INTEL(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) INTEL(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) INTEL(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) INTEL(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) INTEL(0):            BCLRPAT_A: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_A: 0x00000000
>(II) INTEL(0):             DSPBCNTR: 0x19000000 (disabled, pipe B)
>(II) INTEL(0):           DSPBSTRIDE: 0x00000a00 (2560 bytes)
>(II) INTEL(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPBSIZE: 0x018f02cf (720, 400)
>(II) INTEL(0):             DSPBBASE: 0x00000000
>(II) INTEL(0):             DSPBSURF: 0x00000000
>(II) INTEL(0):          DSPBTILEOFF: 0x00000000
>(II) INTEL(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) INTEL(0):             PIPEBSRC: 0x027f018f (640, 400)
>(II) INTEL(0):                 FPB0: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
>(II) INTEL(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_B: 0x99026000 (enabled, non-dvo, LVDS mode, unknown clock, p1 = 2, p2 = 7)
>(II) INTEL(0):            DPLL_B_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_B: 0x081f077f (1920 active, 2080 total)
>(II) INTEL(0):             HBLANK_B: 0x081f077f (1920 start, 2080 end)
>(II) INTEL(0):              HSYNC_B: 0x07cf07af (1968 start, 2000 end)
>(II) INTEL(0):             VTOTAL_B: 0x04d204af (1200 active, 1235 total)
>(II) INTEL(0):             VBLANK_B: 0x04d204af (1200 start, 1235 end)
>(II) INTEL(0):              VSYNC_B: 0x04bb04b1 (1202 start, 1212 end)
>(II) INTEL(0):            BCLRPAT_B: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_B: 0x00000000
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):             VGACNTRL: 0x22c4008e (enabled)
>(II) INTEL(0):               TV_CTL: 0x30000000
>(II) INTEL(0):               TV_DAC: 0x70000000
>(II) INTEL(0):             TV_CSC_Y: 0x00000000
>(II) INTEL(0):            TV_CSC_Y2: 0x00000000
>(II) INTEL(0):             TV_CSC_U: 0x00000000
>(II) INTEL(0):            TV_CSC_U2: 0x00000000
>(II) INTEL(0):             TV_CSC_V: 0x00000000
>(II) INTEL(0):            TV_CSC_V2: 0x00000000
>(II) INTEL(0):         TV_CLR_KNOBS: 0x00000000
>(II) INTEL(0):         TV_CLR_LEVEL: 0x00000000
>(II) INTEL(0):           TV_H_CTL_1: 0x00000000
>(II) INTEL(0):           TV_H_CTL_2: 0x00000000
>(II) INTEL(0):           TV_H_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_1: 0x00000000
>(II) INTEL(0):           TV_V_CTL_2: 0x00000000
>(II) INTEL(0):           TV_V_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_4: 0x00000000
>(II) INTEL(0):           TV_V_CTL_5: 0x00000000
>(II) INTEL(0):           TV_V_CTL_6: 0x00000000
>(II) INTEL(0):           TV_V_CTL_7: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_1: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_2: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_3: 0x00000000
>(II) INTEL(0):           TV_WIN_POS: 0x00000000
>(II) INTEL(0):          TV_WIN_SIZE: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_1: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_2: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_3: 0x00000000
>(II) INTEL(0):        TV_CC_CONTROL: 0x00000000
>(II) INTEL(0):           TV_CC_DATA: 0x00000000
>(II) INTEL(0):          TV_H_LUMA_0: 0x00000000
>(II) INTEL(0):         TV_H_LUMA_59: 0x00000000
>(II) INTEL(0):        TV_H_CHROMA_0: 0x00000000
>(II) INTEL(0):       TV_H_CHROMA_59: 0x00000000
>(II) INTEL(0):                 SR00: 0x03
>(II) INTEL(0):                 SR01: 0x00
>(II) INTEL(0):                 SR02: 0x03
>(II) INTEL(0):                 SR03: 0x00
>(II) INTEL(0):                 SR04: 0x02
>(II) INTEL(0):                 SR05: 0x00
>(II) INTEL(0):                 SR06: 0x00
>(II) INTEL(0):                 SR07: 0x00
>(II) INTEL(0):                  MSR: 0x67
>(II) INTEL(0):                 CR00: 0x5f
>(II) INTEL(0):                 CR01: 0x4f
>(II) INTEL(0):                 CR02: 0x50
>(II) INTEL(0):                 CR03: 0x82
>(II) INTEL(0):                 CR04: 0x55
>(II) INTEL(0):                 CR05: 0x81
>(II) INTEL(0):                 CR06: 0xbf
>(II) INTEL(0):                 CR07: 0x1f
>(II) INTEL(0):                 CR08: 0x00
>(II) INTEL(0):                 CR09: 0x4f
>(II) INTEL(0):                 CR0a: 0x1f
>(II) INTEL(0):                 CR0b: 0x1e
>(II) INTEL(0):                 CR0c: 0x00
>(II) INTEL(0):                 CR0d: 0x00
>(II) INTEL(0):                 CR0e: 0x77
>(II) INTEL(0):                 CR0f: 0x80
>(II) INTEL(0):                 CR10: 0x9c
>(II) INTEL(0):                 CR11: 0x8e
>(II) INTEL(0):                 CR12: 0x8f
>(II) INTEL(0):                 CR13: 0x28
>(II) INTEL(0):                 CR14: 0x1f
>(II) INTEL(0):                 CR15: 0x96
>(II) INTEL(0):                 CR16: 0xb9
>(II) INTEL(0):                 CR17: 0xa3
>(II) INTEL(0):                 CR18: 0xff
>(II) INTEL(0):                 CR19: 0x00
>(II) INTEL(0):                 CR1a: 0x00
>(II) INTEL(0):                 CR1b: 0x00
>(II) INTEL(0):                 CR1c: 0x00
>(II) INTEL(0):                 CR1d: 0x00
>(II) INTEL(0):                 CR1e: 0x00
>(II) INTEL(0):                 CR1f: 0x00
>(II) INTEL(0):                 CR20: 0x00
>(II) INTEL(0):                 CR21: 0x00
>(II) INTEL(0):                 CR22: 0x00
>(II) INTEL(0):                 CR23: 0x00
>(II) INTEL(0):                 CR24: 0x00
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(EE) INTEL(0): ref out of range
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe B dot 0 n 2 m1 14 m2 8 p1 2 p2 5
>(II) INTEL(0): DumpRegsEnd
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 10
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 0
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 1
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 2
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 3
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 5
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 4
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 6
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 7
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 8
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 9
>(II) Mouse0: ps2EnableDataReporting: succeeded
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) AIGLX: Resuming AIGLX clients after VT switch
>(II) INTEL(0): xf86BindGARTMemory: bind key 10 at 0x007bf000 (pgoffset 1983)
>(II) INTEL(0): xf86BindGARTMemory: bind key 0 at 0x0ffff000 (pgoffset 65535)
>(II) INTEL(0): xf86BindGARTMemory: bind key 1 at 0x0fffb000 (pgoffset 65531)
>(II) INTEL(0): xf86BindGARTMemory: bind key 2 at 0x0fffa000 (pgoffset 65530)
>(II) INTEL(0): xf86BindGARTMemory: bind key 3 at 0x0fff6000 (pgoffset 65526)
>(II) INTEL(0): xf86BindGARTMemory: bind key 5 at 0x0ffe5000 (pgoffset 65509)
>(II) INTEL(0): xf86BindGARTMemory: bind key 4 at 0x0fff5000 (pgoffset 65525)
>(II) INTEL(0): xf86BindGARTMemory: bind key 6 at 0x0ffdd000 (pgoffset 65501)
>(II) INTEL(0): xf86BindGARTMemory: bind key 7 at 0x0e000000 (pgoffset 57344)
>(II) INTEL(0): xf86BindGARTMemory: bind key 8 at 0x0d000000 (pgoffset 53248)
>(II) INTEL(0): xf86BindGARTMemory: bind key 9 at 0x0cf1c000 (pgoffset 53020)
>chosen: dotclock 153600 vco 2150400 ((m 112, m1 19, m2 5), n 3, (p 14, p1 2, p2 7))
>clock regs: 0x99020000, 0x00031305
>(II) INTEL(0): DumpRegsBegin
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):            DPLL_TEST: 0x00010001 ()
>(II) INTEL(0):              D_STATE: 0x00000000
>(II) INTEL(0):        DSPCLK_GATE_D: 0x00001000
>(II) INTEL(0):       RENCLK_GATE_D1: 0x00000000
>(II) INTEL(0):       RENCLK_GATE_D2: 0x00000000
>(II) INTEL(0):                SDVOB: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):              SDVOUDI: 0x00000002
>(II) INTEL(0):               DSPARB: 0x00001d9c
>(II) INTEL(0):               DSPFW1: 0x00000000
>(II) INTEL(0):               DSPFW2: 0x00000000
>(II) INTEL(0):               DSPFW3: 0x00000000
>(II) INTEL(0):                 ADPA: 0x40008c18
>(II) INTEL(0):                 LVDS: 0xc000033c (enabled, pipe B)
>(II) INTEL(0):                 DVOA: 0x00000000
>(II) INTEL(0):                 DVOB: 0x00480000
>(II) INTEL(0):                 DVOC: 0x00480000
>(II) INTEL(0):          DVOA_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOB_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOC_SRCDIM: 0x00000000
>(II) INTEL(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) INTEL(0):            PP_STATUS: 0xd000000a (on, ready, sequencing on)
>(II) INTEL(0):         PFIT_CONTROL: 0x80000668
>(II) INTEL(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) INTEL(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) INTEL(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) INTEL(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) INTEL(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) INTEL(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPABASE: 0x00000000
>(II) INTEL(0):             DSPASURF: 0x00000000
>(II) INTEL(0):          DSPATILEOFF: 0x00000000
>(II) INTEL(0):            PIPEACONF: 0x00000000 (disabled, single-wide)
>(II) INTEL(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) INTEL(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_A: 0x04800000 (disabled, non-dvo, VGA, dac/serial mode, default clock, p1 = 8, p2 = 10)
>(II) INTEL(0):            DPLL_A_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) INTEL(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) INTEL(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) INTEL(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) INTEL(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) INTEL(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) INTEL(0):            BCLRPAT_A: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_A: 0x00000000
>(II) INTEL(0):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II) INTEL(0):           DSPBSTRIDE: 0x00002000 (8192 bytes)
>(II) INTEL(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPBSIZE: 0x04af077f (1920, 1200)
>(II) INTEL(0):             DSPBBASE: 0x00020000
>(II) INTEL(0):             DSPBSURF: 0x00000000
>(II) INTEL(0):          DSPBTILEOFF: 0x00000000
>(II) INTEL(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) INTEL(0):             PIPEBSRC: 0x077f04af (1920, 1200)
>(II) INTEL(0):                 FPB0: 0x00031305 (n = 3, m1 = 19, m2 = 5)
>(II) INTEL(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_B: 0x99020000 (enabled, non-dvo, LVDS mode, default clock, p1 = 2, p2 = 7)
>(II) INTEL(0):            DPLL_B_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_B: 0x081f077f (1920 active, 2080 total)
>(II) INTEL(0):             HBLANK_B: 0x081f077f (1920 start, 2080 end)
>(II) INTEL(0):              HSYNC_B: 0x07cf07af (1968 start, 2000 end)
>(II) INTEL(0):             VTOTAL_B: 0x04d204af (1200 active, 1235 total)
>(II) INTEL(0):             VBLANK_B: 0x04d204af (1200 start, 1235 end)
>(II) INTEL(0):              VSYNC_B: 0x04bb04b1 (1202 start, 1212 end)
>(II) INTEL(0):            BCLRPAT_B: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_B: 0x00000000
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):             VGACNTRL: 0x80000000 (disabled)
>(II) INTEL(0):               TV_CTL: 0x30000000
>(II) INTEL(0):               TV_DAC: 0x70000000
>(II) INTEL(0):             TV_CSC_Y: 0x00000000
>(II) INTEL(0):            TV_CSC_Y2: 0x00000000
>(II) INTEL(0):             TV_CSC_U: 0x00000000
>(II) INTEL(0):            TV_CSC_U2: 0x00000000
>(II) INTEL(0):             TV_CSC_V: 0x00000000
>(II) INTEL(0):            TV_CSC_V2: 0x00000000
>(II) INTEL(0):         TV_CLR_KNOBS: 0x00000000
>(II) INTEL(0):         TV_CLR_LEVEL: 0x00000000
>(II) INTEL(0):           TV_H_CTL_1: 0x00000000
>(II) INTEL(0):           TV_H_CTL_2: 0x00000000
>(II) INTEL(0):           TV_H_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_1: 0x00000000
>(II) INTEL(0):           TV_V_CTL_2: 0x00000000
>(II) INTEL(0):           TV_V_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_4: 0x00000000
>(II) INTEL(0):           TV_V_CTL_5: 0x00000000
>(II) INTEL(0):           TV_V_CTL_6: 0x00000000
>(II) INTEL(0):           TV_V_CTL_7: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_1: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_2: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_3: 0x00000000
>(II) INTEL(0):           TV_WIN_POS: 0x00000000
>(II) INTEL(0):          TV_WIN_SIZE: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_1: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_2: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_3: 0x00000000
>(II) INTEL(0):        TV_CC_CONTROL: 0x00000000
>(II) INTEL(0):           TV_CC_DATA: 0x00000000
>(II) INTEL(0):          TV_H_LUMA_0: 0x00000000
>(II) INTEL(0):         TV_H_LUMA_59: 0x00000000
>(II) INTEL(0):        TV_H_CHROMA_0: 0x00000000
>(II) INTEL(0):       TV_H_CHROMA_59: 0x00000000
>(II) INTEL(0):                 SR00: 0x03
>(II) INTEL(0):                 SR01: 0x00
>(II) INTEL(0):                 SR02: 0x03
>(II) INTEL(0):                 SR03: 0x00
>(II) INTEL(0):                 SR04: 0x02
>(II) INTEL(0):                 SR05: 0x00
>(II) INTEL(0):                 SR06: 0x00
>(II) INTEL(0):                 SR07: 0x00
>(II) INTEL(0):                  MSR: 0x67
>(II) INTEL(0):                 CR00: 0x5f
>(II) INTEL(0):                 CR01: 0x4f
>(II) INTEL(0):                 CR02: 0x50
>(II) INTEL(0):                 CR03: 0x82
>(II) INTEL(0):                 CR04: 0x55
>(II) INTEL(0):                 CR05: 0x81
>(II) INTEL(0):                 CR06: 0xbf
>(II) INTEL(0):                 CR07: 0x1f
>(II) INTEL(0):                 CR08: 0x00
>(II) INTEL(0):                 CR09: 0x4f
>(II) INTEL(0):                 CR0a: 0x1f
>(II) INTEL(0):                 CR0b: 0x1e
>(II) INTEL(0):                 CR0c: 0x00
>(II) INTEL(0):                 CR0d: 0x00
>(II) INTEL(0):                 CR0e: 0x07
>(II) INTEL(0):                 CR0f: 0x80
>(II) INTEL(0):                 CR10: 0x9c
>(II) INTEL(0):                 CR11: 0x8e
>(II) INTEL(0):                 CR12: 0x8f
>(II) INTEL(0):                 CR13: 0x28
>(II) INTEL(0):                 CR14: 0x1f
>(II) INTEL(0):                 CR15: 0x96
>(II) INTEL(0):                 CR16: 0xb9
>(II) INTEL(0):                 CR17: 0xa3
>(II) INTEL(0):                 CR18: 0xff
>(II) INTEL(0):                 CR19: 0x00
>(II) INTEL(0):                 CR1a: 0x00
>(II) INTEL(0):                 CR1b: 0x00
>(II) INTEL(0):                 CR1c: 0x00
>(II) INTEL(0):                 CR1d: 0x00
>(II) INTEL(0):                 CR1e: 0x00
>(II) INTEL(0):                 CR1f: 0x00
>(II) INTEL(0):                 CR20: 0x00
>(II) INTEL(0):                 CR21: 0x00
>(II) INTEL(0):                 CR22: 0x20
>(II) INTEL(0):                 CR23: 0x00
>(II) INTEL(0):                 CR24: 0x00
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe B dot 215040 n 3 m1 19 m2 5 p1 2 p2 5
>(II) INTEL(0): DumpRegsEnd
>(II) INTEL(0): Output configuration:
>(II) INTEL(0):   Pipe A is off
>(II) INTEL(0):   Display plane A is now disabled and connected to pipe A.
>(II) INTEL(0):   Pipe B is on
>(II) INTEL(0):   Display plane B is now enabled and connected to pipe B.
>(II) INTEL(0):   Output VGA is connected to pipe none
>(II) INTEL(0):   Output LVDS is connected to pipe B
>(II) INTEL(0):   Output TV is connected to pipe none
>(II) INTEL(0): [drm] dma control initialized, using IRQ 20
>Synaptics DeviceOn called
>(--) Synaptics auto-dev sets device to /dev/input/event0
>(**) Option "Device" "/dev/input/event0"
>(--) Synaptics touchpad found
>ProcXCloseDevice to close or not ?
>SynapticsCtrl called.
>SynapticsCtrl called.
>Synaptics DeviceOff called
>(II) AIGLX: Suspending AIGLX clients for VT switch
>(II) INTEL(0): Comparing regs from server start up to After LeaveVT
>(II) INTEL(0): DumpRegsBegin
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):            DPLL_TEST: 0x00010001 ()
>(II) INTEL(0):              D_STATE: 0x00000000
>(II) INTEL(0):        DSPCLK_GATE_D: 0x00001000
>(II) INTEL(0):       RENCLK_GATE_D1: 0x00000000
>(II) INTEL(0):       RENCLK_GATE_D2: 0x00000000
>(II) INTEL(0):                SDVOB: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):              SDVOUDI: 0x00000002
>(II) INTEL(0):               DSPARB: 0x00001d9c
>(II) INTEL(0):               DSPFW1: 0x00000000
>(II) INTEL(0):               DSPFW2: 0x00000000
>(II) INTEL(0):               DSPFW3: 0x00000000
>(II) INTEL(0):                 ADPA: 0x40008c18
>(II) INTEL(0):                 LVDS: 0xc000033c (enabled, pipe B)
>(II) INTEL(0):                 DVOA: 0x00000000
>(II) INTEL(0):                 DVOB: 0x00480000
>(II) INTEL(0):                 DVOC: 0x00480000
>(II) INTEL(0):          DVOA_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOB_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOC_SRCDIM: 0x00000000
>(II) INTEL(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) INTEL(0):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II) INTEL(0):         PFIT_CONTROL: 0x80006668
>(II) INTEL(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) INTEL(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) INTEL(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) INTEL(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) INTEL(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) INTEL(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPABASE: 0x00000000
>(II) INTEL(0):             DSPASURF: 0x00000000
>(II) INTEL(0):          DSPATILEOFF: 0x00000000
>(II) INTEL(0):            PIPEACONF: 0x00000000 (disabled, single-wide)
>(II) INTEL(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) INTEL(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_A: 0x04800000 (disabled, non-dvo, VGA, dac/serial mode, default clock, p1 = 8, p2 = 10)
>(II) INTEL(0):            DPLL_A_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) INTEL(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) INTEL(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) INTEL(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) INTEL(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) INTEL(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) INTEL(0):            BCLRPAT_A: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_A: 0x00000000
>(II) INTEL(0):             DSPBCNTR: 0x19000000 (disabled, pipe B)
>(II) INTEL(0):           DSPBSTRIDE: 0x00000a00 (2560 bytes)
>(II) INTEL(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPBSIZE: 0x018f02cf (720, 400)
>(II) INTEL(0):             DSPBBASE: 0x00000000
>(II) INTEL(0):             DSPBSURF: 0x00000000
>(II) INTEL(0):          DSPBTILEOFF: 0x00000000
>(II) INTEL(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) INTEL(0):             PIPEBSRC: 0x027f018f (640, 400)
>(II) INTEL(0):                 FPB0: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
>(II) INTEL(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_B: 0x99026000 (enabled, non-dvo, LVDS mode, unknown clock, p1 = 2, p2 = 7)
>(II) INTEL(0):            DPLL_B_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_B: 0x081f077f (1920 active, 2080 total)
>(II) INTEL(0):             HBLANK_B: 0x081f077f (1920 start, 2080 end)
>(II) INTEL(0):              HSYNC_B: 0x07cf07af (1968 start, 2000 end)
>(II) INTEL(0):             VTOTAL_B: 0x04d204af (1200 active, 1235 total)
>(II) INTEL(0):             VBLANK_B: 0x04d204af (1200 start, 1235 end)
>(II) INTEL(0):              VSYNC_B: 0x04bb04b1 (1202 start, 1212 end)
>(II) INTEL(0):            BCLRPAT_B: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_B: 0x00000000
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):             VGACNTRL: 0x22c4008e (enabled)
>(II) INTEL(0):               TV_CTL: 0x30000000
>(II) INTEL(0):               TV_DAC: 0x70000000
>(II) INTEL(0):             TV_CSC_Y: 0x00000000
>(II) INTEL(0):            TV_CSC_Y2: 0x00000000
>(II) INTEL(0):             TV_CSC_U: 0x00000000
>(II) INTEL(0):            TV_CSC_U2: 0x00000000
>(II) INTEL(0):             TV_CSC_V: 0x00000000
>(II) INTEL(0):            TV_CSC_V2: 0x00000000
>(II) INTEL(0):         TV_CLR_KNOBS: 0x00000000
>(II) INTEL(0):         TV_CLR_LEVEL: 0x00000000
>(II) INTEL(0):           TV_H_CTL_1: 0x00000000
>(II) INTEL(0):           TV_H_CTL_2: 0x00000000
>(II) INTEL(0):           TV_H_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_1: 0x00000000
>(II) INTEL(0):           TV_V_CTL_2: 0x00000000
>(II) INTEL(0):           TV_V_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_4: 0x00000000
>(II) INTEL(0):           TV_V_CTL_5: 0x00000000
>(II) INTEL(0):           TV_V_CTL_6: 0x00000000
>(II) INTEL(0):           TV_V_CTL_7: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_1: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_2: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_3: 0x00000000
>(II) INTEL(0):           TV_WIN_POS: 0x00000000
>(II) INTEL(0):          TV_WIN_SIZE: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_1: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_2: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_3: 0x00000000
>(II) INTEL(0):        TV_CC_CONTROL: 0x00000000
>(II) INTEL(0):           TV_CC_DATA: 0x00000000
>(II) INTEL(0):          TV_H_LUMA_0: 0x00000000
>(II) INTEL(0):         TV_H_LUMA_59: 0x00000000
>(II) INTEL(0):        TV_H_CHROMA_0: 0x00000000
>(II) INTEL(0):       TV_H_CHROMA_59: 0x00000000
>(II) INTEL(0):                 SR00: 0x03
>(II) INTEL(0):                 SR01: 0x00
>(II) INTEL(0):                 SR02: 0x03
>(II) INTEL(0):                 SR03: 0x00
>(II) INTEL(0):                 SR04: 0x02
>(II) INTEL(0):                 SR05: 0x00
>(II) INTEL(0):                 SR06: 0x00
>(II) INTEL(0):                 SR07: 0x00
>(II) INTEL(0):                  MSR: 0x67
>(II) INTEL(0):                 CR00: 0x5f
>(II) INTEL(0):                 CR01: 0x4f
>(II) INTEL(0):                 CR02: 0x50
>(II) INTEL(0):                 CR03: 0x82
>(II) INTEL(0):                 CR04: 0x55
>(II) INTEL(0):                 CR05: 0x81
>(II) INTEL(0):                 CR06: 0xbf
>(II) INTEL(0):                 CR07: 0x1f
>(II) INTEL(0):                 CR08: 0x00
>(II) INTEL(0):                 CR09: 0x4f
>(II) INTEL(0):                 CR0a: 0x1f
>(II) INTEL(0):                 CR0b: 0x1e
>(II) INTEL(0):                 CR0c: 0x00
>(II) INTEL(0):                 CR0d: 0x00
>(II) INTEL(0):                 CR0e: 0x77
>(II) INTEL(0):                 CR0f: 0x80
>(II) INTEL(0):                 CR10: 0x9c
>(II) INTEL(0):                 CR11: 0x8e
>(II) INTEL(0):                 CR12: 0x8f
>(II) INTEL(0):                 CR13: 0x28
>(II) INTEL(0):                 CR14: 0x1f
>(II) INTEL(0):                 CR15: 0x96
>(II) INTEL(0):                 CR16: 0xb9
>(II) INTEL(0):                 CR17: 0xa3
>(II) INTEL(0):                 CR18: 0xff
>(II) INTEL(0):                 CR19: 0x00
>(II) INTEL(0):                 CR1a: 0x00
>(II) INTEL(0):                 CR1b: 0x00
>(II) INTEL(0):                 CR1c: 0x00
>(II) INTEL(0):                 CR1d: 0x00
>(II) INTEL(0):                 CR1e: 0x00
>(II) INTEL(0):                 CR1f: 0x00
>(II) INTEL(0):                 CR20: 0x00
>(II) INTEL(0):                 CR21: 0x00
>(II) INTEL(0):                 CR22: 0x20
>(II) INTEL(0):                 CR23: 0x00
>(II) INTEL(0):                 CR24: 0x00
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(EE) INTEL(0): ref out of range
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe B dot 0 n 2 m1 14 m2 8 p1 2 p2 5
>(II) INTEL(0): DumpRegsEnd
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 10
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 0
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 1
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 2
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 3
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 5
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 4
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 6
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 7
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 8
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 9
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) AIGLX: Resuming AIGLX clients after VT switch
>(II) INTEL(0): xf86BindGARTMemory: bind key 10 at 0x007bf000 (pgoffset 1983)
>(II) INTEL(0): xf86BindGARTMemory: bind key 0 at 0x0ffff000 (pgoffset 65535)
>(II) INTEL(0): xf86BindGARTMemory: bind key 1 at 0x0fffb000 (pgoffset 65531)
>(II) INTEL(0): xf86BindGARTMemory: bind key 2 at 0x0fffa000 (pgoffset 65530)
>(II) INTEL(0): xf86BindGARTMemory: bind key 3 at 0x0fff6000 (pgoffset 65526)
>(II) INTEL(0): xf86BindGARTMemory: bind key 5 at 0x0ffe5000 (pgoffset 65509)
>(II) INTEL(0): xf86BindGARTMemory: bind key 4 at 0x0fff5000 (pgoffset 65525)
>(II) INTEL(0): xf86BindGARTMemory: bind key 6 at 0x0ffdd000 (pgoffset 65501)
>(II) INTEL(0): xf86BindGARTMemory: bind key 7 at 0x0e000000 (pgoffset 57344)
>(II) INTEL(0): xf86BindGARTMemory: bind key 8 at 0x0d000000 (pgoffset 53248)
>(II) INTEL(0): xf86BindGARTMemory: bind key 9 at 0x0cf1c000 (pgoffset 53020)
>chosen: dotclock 153600 vco 2150400 ((m 112, m1 19, m2 5), n 3, (p 14, p1 2, p2 7))
>clock regs: 0x99020000, 0x00031305
>(II) INTEL(0): DumpRegsBegin
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):            DPLL_TEST: 0x00010001 ()
>(II) INTEL(0):              D_STATE: 0x00000000
>(II) INTEL(0):        DSPCLK_GATE_D: 0x00000000
>(II) INTEL(0):       RENCLK_GATE_D1: 0x00000000
>(II) INTEL(0):       RENCLK_GATE_D2: 0x00000000
>(II) INTEL(0):                SDVOB: 0x00300000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):                SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):              SDVOUDI: 0x00000069
>(II) INTEL(0):               DSPARB: 0x00001d9c
>(II) INTEL(0):               DSPFW1: 0x00000000
>(II) INTEL(0):               DSPFW2: 0x00000000
>(II) INTEL(0):               DSPFW3: 0x00000000
>(II) INTEL(0):                 ADPA: 0x00000c00
>(II) INTEL(0):                 LVDS: 0xc0000000 (enabled, pipe B)
>(II) INTEL(0):                 DVOA: 0x00000000
>(II) INTEL(0):                 DVOB: 0x00300000
>(II) INTEL(0):                 DVOC: 0x00300000
>(II) INTEL(0):          DVOA_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOB_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOC_SRCDIM: 0x00000000
>(II) INTEL(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) INTEL(0):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II) INTEL(0):         PFIT_CONTROL: 0x80000668
>(II) INTEL(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) INTEL(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) INTEL(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) INTEL(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) INTEL(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) INTEL(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPABASE: 0x00000000
>(II) INTEL(0):             DSPASURF: 0x00000000
>(II) INTEL(0):          DSPATILEOFF: 0x00000000
>(II) INTEL(0):            PIPEACONF: 0x00000000 (disabled, single-wide)
>(II) INTEL(0):             PIPEASRC: 0x00000000 (1, 1)
>(II) INTEL(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_A: 0x04800000 (disabled, non-dvo, VGA, dac/serial mode, default clock, p1 = 8, p2 = 10)
>(II) INTEL(0):            DPLL_A_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_A: 0x00000000 (1 active, 1 total)
>(II) INTEL(0):             HBLANK_A: 0x00000000 (1 start, 1 end)
>(II) INTEL(0):              HSYNC_A: 0x00000000 (1 start, 1 end)
>(II) INTEL(0):             VTOTAL_A: 0x00000000 (1 active, 1 total)
>(II) INTEL(0):             VBLANK_A: 0x00000000 (1 start, 1 end)
>(II) INTEL(0):              VSYNC_A: 0x00000000 (1 start, 1 end)
>(II) INTEL(0):            BCLRPAT_A: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_A: 0x00000000
>(II) INTEL(0):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II) INTEL(0):           DSPBSTRIDE: 0x00002000 (8192 bytes)
>(II) INTEL(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPBSIZE: 0x04af077f (1920, 1200)
>(II) INTEL(0):             DSPBBASE: 0x00020000
>(II) INTEL(0):             DSPBSURF: 0x00000000
>(II) INTEL(0):          DSPBTILEOFF: 0x00000000
>(II) INTEL(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) INTEL(0):             PIPEBSRC: 0x077f04af (1920, 1200)
>(II) INTEL(0):                 FPB0: 0x00031305 (n = 3, m1 = 19, m2 = 5)
>(II) INTEL(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_B: 0x99020000 (enabled, non-dvo, LVDS mode, default clock, p1 = 2, p2 = 7)
>(II) INTEL(0):            DPLL_B_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_B: 0x081f077f (1920 active, 2080 total)
>(II) INTEL(0):             HBLANK_B: 0x081f077f (1920 start, 2080 end)
>(II) INTEL(0):              HSYNC_B: 0x07cf07af (1968 start, 2000 end)
>(II) INTEL(0):             VTOTAL_B: 0x04d204af (1200 active, 1235 total)
>(II) INTEL(0):             VBLANK_B: 0x04d204af (1200 start, 1235 end)
>(II) INTEL(0):              VSYNC_B: 0x04bb04b1 (1202 start, 1212 end)
>(II) INTEL(0):            BCLRPAT_B: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_B: 0x00000000
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):             VGACNTRL: 0x80000000 (disabled)
>(II) INTEL(0):               TV_CTL: 0x00000000
>(II) INTEL(0):               TV_DAC: 0x00000000
>(II) INTEL(0):             TV_CSC_Y: 0x00000000
>(II) INTEL(0):            TV_CSC_Y2: 0x00000000
>(II) INTEL(0):             TV_CSC_U: 0x00000000
>(II) INTEL(0):            TV_CSC_U2: 0x00000000
>(II) INTEL(0):             TV_CSC_V: 0x00000000
>(II) INTEL(0):            TV_CSC_V2: 0x00000000
>(II) INTEL(0):         TV_CLR_KNOBS: 0x00000000
>(II) INTEL(0):         TV_CLR_LEVEL: 0x00000000
>(II) INTEL(0):           TV_H_CTL_1: 0x00000000
>(II) INTEL(0):           TV_H_CTL_2: 0x00000000
>(II) INTEL(0):           TV_H_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_1: 0x00000000
>(II) INTEL(0):           TV_V_CTL_2: 0x00000000
>(II) INTEL(0):           TV_V_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_4: 0x00000000
>(II) INTEL(0):           TV_V_CTL_5: 0x00000000
>(II) INTEL(0):           TV_V_CTL_6: 0x00000000
>(II) INTEL(0):           TV_V_CTL_7: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_1: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_2: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_3: 0x00000000
>(II) INTEL(0):           TV_WIN_POS: 0x00000000
>(II) INTEL(0):          TV_WIN_SIZE: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_1: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_2: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_3: 0x00000000
>(II) INTEL(0):        TV_CC_CONTROL: 0x00000000
>(II) INTEL(0):           TV_CC_DATA: 0x00000000
>(II) INTEL(0):          TV_H_LUMA_0: 0x00000000
>(II) INTEL(0):         TV_H_LUMA_59: 0x00000000
>(II) INTEL(0):        TV_H_CHROMA_0: 0x00000000
>(II) INTEL(0):       TV_H_CHROMA_59: 0x00000000
>(II) INTEL(0):                 SR00: 0x03
>(II) INTEL(0):                 SR01: 0x00
>(II) INTEL(0):                 SR02: 0x03
>(II) INTEL(0):                 SR03: 0x04
>(II) INTEL(0):                 SR04: 0x02
>(II) INTEL(0):                 SR05: 0x00
>(II) INTEL(0):                 SR06: 0x00
>(II) INTEL(0):                 SR07: 0x00
>(II) INTEL(0):                  MSR: 0x00
>(II) INTEL(0):                 CR00: 0x00
>(II) INTEL(0):                 CR01: 0x00
>(II) INTEL(0):                 CR02: 0x00
>(II) INTEL(0):                 CR03: 0x80
>(II) INTEL(0):                 CR04: 0x00
>(II) INTEL(0):                 CR05: 0x00
>(II) INTEL(0):                 CR06: 0x00
>(II) INTEL(0):                 CR07: 0x00
>(II) INTEL(0):                 CR08: 0x00
>(II) INTEL(0):                 CR09: 0x00
>(II) INTEL(0):                 CR0a: 0x00
>(II) INTEL(0):                 CR0b: 0x00
>(II) INTEL(0):                 CR0c: 0x00
>(II) INTEL(0):                 CR0d: 0x00
>(II) INTEL(0):                 CR0e: 0x00
>(II) INTEL(0):                 CR0f: 0x00
>(II) INTEL(0):                 CR10: 0x00
>(II) INTEL(0):                 CR11: 0x00
>(II) INTEL(0):                 CR12: 0x00
>(II) INTEL(0):                 CR13: 0x00
>(II) INTEL(0):                 CR14: 0x00
>(II) INTEL(0):                 CR15: 0x00
>(II) INTEL(0):                 CR16: 0x00
>(II) INTEL(0):                 CR17: 0x00
>(II) INTEL(0):                 CR18: 0x00
>(II) INTEL(0):                 CR19: 0x00
>(II) INTEL(0):                 CR1a: 0x00
>(II) INTEL(0):                 CR1b: 0x00
>(II) INTEL(0):                 CR1c: 0x00
>(II) INTEL(0):                 CR1d: 0x00
>(II) INTEL(0):                 CR1e: 0x00
>(II) INTEL(0):                 CR1f: 0x00
>(II) INTEL(0):                 CR20: 0x00
>(II) INTEL(0):                 CR21: 0x00
>(II) INTEL(0):                 CR22: 0x00
>(II) INTEL(0):                 CR23: 0x00
>(II) INTEL(0):                 CR24: 0x00
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe B dot 215040 n 3 m1 19 m2 5 p1 2 p2 5
>(II) INTEL(0): DumpRegsEnd
>(II) INTEL(0): Output configuration:
>(II) INTEL(0):   Pipe A is off
>(II) INTEL(0):   Display plane A is now disabled and connected to pipe A.
>(II) INTEL(0):   Pipe B is on
>(II) INTEL(0):   Display plane B is now enabled and connected to pipe B.
>(II) INTEL(0):   Output VGA is connected to pipe none
>(II) INTEL(0):   Output LVDS is connected to pipe B
>(II) INTEL(0):   Output TV is connected to pipe none
>(II) INTEL(0): [drm] dma control initialized, using IRQ 20
>(II) Mouse0: ps2EnableDataReporting: succeeded
>Synaptics DeviceOn called
>(--) Synaptics auto-dev sets device to /dev/input/event0
>(**) Option "Device" "/dev/input/event0"
>(--) Synaptics touchpad found
>Synaptics DeviceOff called
>(II) INTEL(0): [drm] removed 1 reserved context for kernel
>(II) INTEL(0): [drm] unmapping 8192 bytes of SAREA 0xe04f8000 at 0xb7ef3000
>(EE) INTEL(0): I830 Vblank Pipe Setup Failed 0
>(II) INTEL(0): Comparing regs from server start up to After LeaveVT
>(WW) INTEL(0): Register 0x6200 (DSPCLK_GATE_D) changed from 0x00001000 to 0x00000000
>(WW) INTEL(0): Register 0x61140 (SDVOB) changed from 0x00480000 to 0x00300000
>(WW) INTEL(0): SDVOB before: disabled, pipe A, stall disabled, not detected, SDVO mult 1
>(WW) INTEL(0): SDVOB after: disabled, pipe A, stall disabled, not detected, SDVO mult 1
>(WW) INTEL(0): Register 0x61160 (SDVOC) changed from 0x00480000 to 0x00300000
>(WW) INTEL(0): SDVOC before: disabled, pipe A, stall disabled, not detected, SDVO mult 1
>(WW) INTEL(0): SDVOC after: disabled, pipe A, stall disabled, not detected, SDVO mult 1
>(WW) INTEL(0): Register 0x61150 (SDVOUDI) changed from 0x00000002 to 0x00000069
>(WW) INTEL(0): Register 0x61140 (DVOB) changed from 0x00480000 to 0x00300000
>(WW) INTEL(0): Register 0x61160 (DVOC) changed from 0x00480000 to 0x00300000
>(WW) INTEL(0): Register 0x68004 (TV_DAC) changed from 0x70000000 to 0x00000000
>(II) INTEL(0): DumpRegsBegin
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):            DPLL_TEST: 0x00010001 ()
>(II) INTEL(0):              D_STATE: 0x00000000
>(II) INTEL(0):        DSPCLK_GATE_D: 0x00000000
>(II) INTEL(0):       RENCLK_GATE_D1: 0x00000000
>(II) INTEL(0):       RENCLK_GATE_D2: 0x00000000
>(II) INTEL(0):                SDVOB: 0x00300000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):                SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II) INTEL(0):              SDVOUDI: 0x00000069
>(II) INTEL(0):               DSPARB: 0x00001d9c
>(II) INTEL(0):               DSPFW1: 0x00000000
>(II) INTEL(0):               DSPFW2: 0x00000000
>(II) INTEL(0):               DSPFW3: 0x00000000
>(II) INTEL(0):                 ADPA: 0x40008c18
>(II) INTEL(0):                 LVDS: 0xc000033c (enabled, pipe B)
>(II) INTEL(0):                 DVOA: 0x00000000
>(II) INTEL(0):                 DVOB: 0x00300000
>(II) INTEL(0):                 DVOC: 0x00300000
>(II) INTEL(0):          DVOA_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOB_SRCDIM: 0x00000000
>(II) INTEL(0):          DVOC_SRCDIM: 0x00000000
>(II) INTEL(0):           PP_CONTROL: 0x00000001 (power target: on)
>(II) INTEL(0):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II) INTEL(0):         PFIT_CONTROL: 0x80006668
>(II) INTEL(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) INTEL(0):      PORT_HOTPLUG_EN: 0x00000000
>(II) INTEL(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) INTEL(0):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II) INTEL(0):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II) INTEL(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) INTEL(0):             DSPABASE: 0x00000000
>(II) INTEL(0):             DSPASURF: 0x00000000
>(II) INTEL(0):          DSPATILEOFF: 0x00000000
>(II) INTEL(0):            PIPEACONF: 0x00000000 (disabled, single-wide)
>(II) INTEL(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) INTEL(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_A: 0x04800000 (disabled, non-dvo, VGA, dac/serial mode, default clock, p1 = 8, p2 = 10)
>(II) INTEL(0):            DPLL_A_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) INTEL(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) INTEL(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) INTEL(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) INTEL(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) INTEL(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) INTEL(0):            BCLRPAT_A: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_A: 0x00000000
>(II) INTEL(0):             DSPBCNTR: 0x19000000 (disabled, pipe B)
>(II) INTEL(0):           DSPBSTRIDE: 0x00000a00 (2560 bytes)
>(II) INTEL(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) INTEL(0):             DSPBSIZE: 0x018f02cf (720, 400)
>(II) INTEL(0):             DSPBBASE: 0x00000000
>(II) INTEL(0):             DSPBSURF: 0x00000000
>(II) INTEL(0):          DSPBTILEOFF: 0x00000000
>(II) INTEL(0):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II) INTEL(0):             PIPEBSRC: 0x027f018f (640, 400)
>(II) INTEL(0):                 FPB0: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
>(II) INTEL(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) INTEL(0):               DPLL_B: 0x99026000 (enabled, non-dvo, LVDS mode, unknown clock, p1 = 2, p2 = 7)
>(II) INTEL(0):            DPLL_B_MD: 0x00000000
>(II) INTEL(0):             HTOTAL_B: 0x081f077f (1920 active, 2080 total)
>(II) INTEL(0):             HBLANK_B: 0x081f077f (1920 start, 2080 end)
>(II) INTEL(0):              HSYNC_B: 0x07cf07af (1968 start, 2000 end)
>(II) INTEL(0):             VTOTAL_B: 0x04d204af (1200 active, 1235 total)
>(II) INTEL(0):             VBLANK_B: 0x04d204af (1200 start, 1235 end)
>(II) INTEL(0):              VSYNC_B: 0x04bb04b1 (1202 start, 1212 end)
>(II) INTEL(0):            BCLRPAT_B: 0x00000000
>(II) INTEL(0):         VSYNCSHIFT_B: 0x00000000
>(II) INTEL(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) INTEL(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) INTEL(0):        VCLK_POST_DIV: 0x00800080
>(II) INTEL(0):             VGACNTRL: 0x22c4008e (enabled)
>(II) INTEL(0):               TV_CTL: 0x30000000
>(II) INTEL(0):               TV_DAC: 0x00000000
>(II) INTEL(0):             TV_CSC_Y: 0x00000000
>(II) INTEL(0):            TV_CSC_Y2: 0x00000000
>(II) INTEL(0):             TV_CSC_U: 0x00000000
>(II) INTEL(0):            TV_CSC_U2: 0x00000000
>(II) INTEL(0):             TV_CSC_V: 0x00000000
>(II) INTEL(0):            TV_CSC_V2: 0x00000000
>(II) INTEL(0):         TV_CLR_KNOBS: 0x00000000
>(II) INTEL(0):         TV_CLR_LEVEL: 0x00000000
>(II) INTEL(0):           TV_H_CTL_1: 0x00000000
>(II) INTEL(0):           TV_H_CTL_2: 0x00000000
>(II) INTEL(0):           TV_H_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_1: 0x00000000
>(II) INTEL(0):           TV_V_CTL_2: 0x00000000
>(II) INTEL(0):           TV_V_CTL_3: 0x00000000
>(II) INTEL(0):           TV_V_CTL_4: 0x00000000
>(II) INTEL(0):           TV_V_CTL_5: 0x00000000
>(II) INTEL(0):           TV_V_CTL_6: 0x00000000
>(II) INTEL(0):           TV_V_CTL_7: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_1: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_2: 0x00000000
>(II) INTEL(0):          TV_SC_CTL_3: 0x00000000
>(II) INTEL(0):           TV_WIN_POS: 0x00000000
>(II) INTEL(0):          TV_WIN_SIZE: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_1: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_2: 0x00000000
>(II) INTEL(0):      TV_FILTER_CTL_3: 0x00000000
>(II) INTEL(0):        TV_CC_CONTROL: 0x00000000
>(II) INTEL(0):           TV_CC_DATA: 0x00000000
>(II) INTEL(0):          TV_H_LUMA_0: 0x00000000
>(II) INTEL(0):         TV_H_LUMA_59: 0x00000000
>(II) INTEL(0):        TV_H_CHROMA_0: 0x00000000
>(II) INTEL(0):       TV_H_CHROMA_59: 0x00000000
>(II) INTEL(0):                 SR00: 0x03
>(II) INTEL(0):                 SR01: 0x00
>(II) INTEL(0):                 SR02: 0x03
>(II) INTEL(0):                 SR03: 0x04
>(II) INTEL(0):                 SR04: 0x02
>(II) INTEL(0):                 SR05: 0x00
>(II) INTEL(0):                 SR06: 0x00
>(II) INTEL(0):                 SR07: 0x00
>(II) INTEL(0):                  MSR: 0x00
>(II) INTEL(0):                 CR00: 0x00
>(II) INTEL(0):                 CR01: 0x00
>(II) INTEL(0):                 CR02: 0x00
>(II) INTEL(0):                 CR03: 0x80
>(II) INTEL(0):                 CR04: 0x00
>(II) INTEL(0):                 CR05: 0x00
>(II) INTEL(0):                 CR06: 0x00
>(II) INTEL(0):                 CR07: 0x00
>(II) INTEL(0):                 CR08: 0x00
>(II) INTEL(0):                 CR09: 0x00
>(II) INTEL(0):                 CR0a: 0x00
>(II) INTEL(0):                 CR0b: 0x00
>(II) INTEL(0):                 CR0c: 0x00
>(II) INTEL(0):                 CR0d: 0x00
>(II) INTEL(0):                 CR0e: 0x00
>(II) INTEL(0):                 CR0f: 0x00
>(II) INTEL(0):                 CR10: 0x00
>(II) INTEL(0):                 CR11: 0x00
>(II) INTEL(0):                 CR12: 0x00
>(II) INTEL(0):                 CR13: 0x00
>(II) INTEL(0):                 CR14: 0x00
>(II) INTEL(0):                 CR15: 0x00
>(II) INTEL(0):                 CR16: 0x00
>(II) INTEL(0):                 CR17: 0x00
>(II) INTEL(0):                 CR18: 0x00
>(II) INTEL(0):                 CR19: 0x00
>(II) INTEL(0):                 CR1a: 0x00
>(II) INTEL(0):                 CR1b: 0x00
>(II) INTEL(0):                 CR1c: 0x00
>(II) INTEL(0):                 CR1d: 0x00
>(II) INTEL(0):                 CR1e: 0x00
>(II) INTEL(0):                 CR1f: 0x00
>(II) INTEL(0):                 CR20: 0x00
>(II) INTEL(0):                 CR21: 0x00
>(II) INTEL(0):                 CR22: 0x00
>(II) INTEL(0):                 CR23: 0x00
>(II) INTEL(0):                 CR24: 0x80
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(EE) INTEL(0): ref out of range
>(II) INTEL(0): SDVO phase shift 0 out of range -- probobly not an issue.
>(II) INTEL(0): pipe B dot 0 n 2 m1 14 m2 8 p1 2 p2 5
>(II) INTEL(0): DumpRegsEnd
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 10
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 0
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 1
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 2
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 3
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 5
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 4
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 6
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 7
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 8
>(II) INTEL(0): xf86UnbindGARTMemory: unbind key 9

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Attachments on bug 6942: 5645 | 7738 | 7739 | 8635 | 8636 | 8885

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