Attachment 89615 Details for Bug 71285 – Work Around

[patch] Work Around

0001-XXX-WIP-Register-spilling-v3.patch (text/plain), 13.58 KB, created by Tom Stellard on 2013-11-22 04:42:22 UTC

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Creator: Tom Stellard

Created: 2013-11-22 04:42:22 UTC

Size: 13.58 KB

patch

obsolete

>From 8b02910abc4a18fb4670e8bc678357d7f1f4998d Mon Sep 17 00:00:00 2001
>From: Tom Stellard <thomas.stellard@amd.com>
>Date: Thu, 29 Aug 2013 11:43:01 -0700
>Subject: [PATCH] XXX: WIP Register spilling v3
>
>v2:
>  - Fix encoding of Lane Mask
>  - Use correct register flags, so we don't overwrite the low dword
>    when restoring multi-dword registers.
>
>v3:
>  - Register spilling seems to hang the GPU, so replace all shaders
>    that need spilling with a dummy shader.
>---
> lib/Target/R600/AMDGPUInstrInfo.h         | 20 ++++-----
> lib/Target/R600/SIInstrInfo.cpp           | 75 +++++++++++++++++++++++++++++++
> lib/Target/R600/SIInstrInfo.h             | 12 +++++
> lib/Target/R600/SILowerControlFlow.cpp    | 24 ++++++++++
> lib/Target/R600/SIMachineFunctionInfo.cpp | 35 ++++++++++++++-
> lib/Target/R600/SIMachineFunctionInfo.h   | 28 ++++++++++++
> lib/Target/R600/SIRegisterInfo.cpp        | 20 +++++++++
> lib/Target/R600/SIRegisterInfo.h          |  1 +
> 8 files changed, 204 insertions(+), 11 deletions(-)
>
>diff --git a/lib/Target/R600/AMDGPUInstrInfo.h b/lib/Target/R600/AMDGPUInstrInfo.h
>index ce5b58c..426910c 100644
>--- a/lib/Target/R600/AMDGPUInstrInfo.h
>+++ b/lib/Target/R600/AMDGPUInstrInfo.h
>@@ -78,18 +78,18 @@ public:
>                            unsigned DestReg, unsigned SrcReg,
>                            bool KillSrc) const = 0;
> 
>-  void storeRegToStackSlot(MachineBasicBlock &MBB,
>-                           MachineBasicBlock::iterator MI,
>-                           unsigned SrcReg, bool isKill, int FrameIndex,
>-                           const TargetRegisterClass *RC,
>-                           const TargetRegisterInfo *TRI) const;
>-  void loadRegFromStackSlot(MachineBasicBlock &MBB,
>-                            MachineBasicBlock::iterator MI,
>-                            unsigned DestReg, int FrameIndex,
>-                            const TargetRegisterClass *RC,
>-                            const TargetRegisterInfo *TRI) const;
>   virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
> 
>+  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
>+                                   MachineBasicBlock::iterator MI,
>+                                   unsigned SrcReg, bool isKill, int FrameIndex,
>+                                   const TargetRegisterClass *RC,
>+                                   const TargetRegisterInfo *TRI) const;
>+  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
>+                                    MachineBasicBlock::iterator MI,
>+                                    unsigned DestReg, int FrameIndex,
>+                                    const TargetRegisterClass *RC,
>+                                    const TargetRegisterInfo *TRI) const;
> 
> protected:
>   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
>diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
>index ab55c1b..61220ae 100644
>--- a/lib/Target/R600/SIInstrInfo.cpp
>+++ b/lib/Target/R600/SIInstrInfo.cpp
>@@ -16,6 +16,7 @@
> #include "SIInstrInfo.h"
> #include "AMDGPUTargetMachine.h"
> #include "SIDefines.h"
>+#include "SIMachineFunctionInfo.h"
> #include "llvm/CodeGen/MachineInstrBuilder.h"
> #include "llvm/CodeGen/MachineRegisterInfo.h"
> #include "llvm/MC/MCInstrDesc.h"
>@@ -185,6 +186,80 @@ unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
>   return Opcode;
> }
> 
>+void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
>+                                      MachineBasicBlock::iterator MI,
>+                                      unsigned SrcReg, bool isKill,
>+                                      int FrameIndex,
>+                                      const TargetRegisterClass *RC,
>+                                      const TargetRegisterInfo *TRI) const {
>+  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
>+  SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
>+  DebugLoc DL = MBB.findDebugLoc(MI);
>+  unsigned KillFlag = isKill ? RegState::Kill : 0;
>+
>+  if (RC == &AMDGPU::SReg_32RegClass) {
>+    if (RI.allUsesCanBeCopiedToVGPR(MRI, MI->getOperand(0).getReg())) {
>+      unsigned VReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
>+      BuildMI(MBB, MI, DL, get(AMDGPU::COPY), VReg)
>+             .addReg(SrcReg, KillFlag);
>+      MFI->SpillTracker.addSpilledReg(FrameIndex, VReg);
>+    } else {
>+      unsigned Lane = MFI->SpillTracker.getNextLane(MRI);
>+      BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32_e32),
>+              MFI->SpillTracker.LaneVGPR)
>+              .addReg(SrcReg, KillFlag)
>+              .addImm(Lane + 0x80);
>+      MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
>+                                      Lane);
>+    }
>+  } else {
>+    for (unsigned i = 0, e = RC->getSize() / 4; i != e; ++i) {
>+      unsigned SubReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
>+      BuildMI(MBB, MI, MBB.findDebugLoc(MI), get(AMDGPU::COPY), SubReg)
>+              .addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
>+      storeRegToStackSlot(MBB, MI, SubReg, isKill, FrameIndex + i,
>+                          &AMDGPU::SReg_32RegClass, TRI);
>+    }
>+  }
>+}
>+
>+void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
>+                                       MachineBasicBlock::iterator MI,
>+                                       unsigned DestReg, int FrameIndex,
>+                                       const TargetRegisterClass *RC,
>+                                       const TargetRegisterInfo *TRI) const {
>+  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
>+  SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
>+  DebugLoc DL = MBB.findDebugLoc(MI);
>+  if (RC == &AMDGPU::SReg_32RegClass) {
>+     SIMachineFunctionInfo::SpilledReg Spill =
>+        MFI->SpillTracker.getSpilledReg(FrameIndex);
>+    assert(Spill.VGPR);
>+    if (!Spill.hasLane()) {
>+      MRI.setRegClass(DestReg, MRI.getRegClass(Spill.VGPR));
>+      BuildMI(MBB, MI, DL, get(AMDGPU::COPY), DestReg)
>+              .addReg(Spill.VGPR);
>+    } else {
>+      BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32_e32), DestReg)
>+              .addReg(Spill.VGPR)
>+              .addImm(Spill.Lane + 0x80);
>+    }
>+  } else {
>+    for (unsigned i = 0, e = RC->getSize() / 4; i != e; ++i) {
>+      unsigned Flags = RegState::Define;
>+      if (i == 0) {
>+        Flags |= RegState::Undef;
>+      }
>+      unsigned SubReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
>+      loadRegFromStackSlot(MBB, MI, SubReg, FrameIndex + i,
>+                           &AMDGPU::SReg_32RegClass, TRI);
>+      BuildMI(MBB, MI, DL, get(AMDGPU::COPY))
>+              .addReg(DestReg, Flags, RI.getSubRegFromChannel(i))
>+              .addReg(SubReg);
>+    }
>+  }
>+}
>+
> MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
>                                               bool NewMI) const {
> 
>diff --git a/lib/Target/R600/SIInstrInfo.h b/lib/Target/R600/SIInstrInfo.h
>index 4af6348..618deaf 100644
>--- a/lib/Target/R600/SIInstrInfo.h
>+++ b/lib/Target/R600/SIInstrInfo.h
>@@ -43,6 +43,18 @@ public:
>                            unsigned DestReg, unsigned SrcReg,
>                            bool KillSrc) const;
> 
>+  void storeRegToStackSlot(MachineBasicBlock &MBB,
>+                           MachineBasicBlock::iterator MI,
>+                           unsigned SrcReg, bool isKill, int FrameIndex,
>+                           const TargetRegisterClass *RC,
>+                           const TargetRegisterInfo *TRI) const;
>+
>+  void loadRegFromStackSlot(MachineBasicBlock &MBB,
>+                            MachineBasicBlock::iterator MI,
>+                            unsigned DestReg, int FrameIndex,
>+                            const TargetRegisterClass *RC,
>+                            const TargetRegisterInfo *TRI) const;
>+
>   unsigned commuteOpcode(unsigned Opcode) const;
> 
>   virtual MachineInstr *commuteInstruction(MachineInstr *MI,
>diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp
>index 958763d..4cac988 100644
>--- a/lib/Target/R600/SILowerControlFlow.cpp
>+++ b/lib/Target/R600/SILowerControlFlow.cpp
>@@ -431,6 +431,30 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
> 
>       Next = llvm::next(I);
>       MachineInstr &MI = *I;
>+
>+#if 1
>+      if (MFI->SpillTracker.programSpillsRegisters()) {
>+        // XXX: Register spilling hangs the GPU, so replace the program with a
>+        // dummy shader if we have done any spilling.
>+        if (MI.getOpcode() != AMDGPU::S_ENDPGM) {
>+          MI.eraseFromParent();
>+          continue;
>+        }
>+        DebugLoc DL = MBB.findDebugLoc(I);
>+        BuildMI(MBB, I, DL, TII->get(AMDGPU::EXP))
>+            .addImm(0)
>+            .addImm(0x09) // V_008DFC_SQ_EXP_NULL
>+            .addImm(0)
>+            .addImm(1)
>+            .addImm(1)
>+            .addReg(AMDGPU::VGPR0)
>+            .addReg(AMDGPU::VGPR0)
>+            .addReg(AMDGPU::VGPR0)
>+            .addReg(AMDGPU::VGPR0);
>+        continue;
>+      }
>+#endif
>+
>       switch (MI.getOpcode()) {
>         default: break;
>         case AMDGPU::SI_IF:
>diff --git a/lib/Target/R600/SIMachineFunctionInfo.cpp b/lib/Target/R600/SIMachineFunctionInfo.cpp
>index 071f9fa..525e792 100644
>--- a/lib/Target/R600/SIMachineFunctionInfo.cpp
>+++ b/lib/Target/R600/SIMachineFunctionInfo.cpp
>@@ -10,6 +10,10 @@
> 
> 
> #include "SIMachineFunctionInfo.h"
>+#include "SIRegisterInfo.h"
>+#include "llvm/CodeGen/MachineRegisterInfo.h"
>+
>+#define MAX_LANES 1
> 
> using namespace llvm;
> 
>@@ -19,4 +23,33 @@ void SIMachineFunctionInfo::anchor() {}
> 
> SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
>   : AMDGPUMachineFunction(MF),
>-    PSInputAddr(0) { }
>+    PSInputAddr(0),
>+    SpillTracker() { }
>+
>+static unsigned createLaneVGPR(MachineRegisterInfo &MRI) {
>+  return MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
>+}
>+
>+unsigned SIMachineFunctionInfo::RegSpillTracker::getNextLane(MachineRegisterInfo &MRI) {
>+  if (!LaneVGPR) {
>+    LaneVGPR = createLaneVGPR(MRI);
>+  } else {
>+    CurrentLane++;
>+    if (CurrentLane == MAX_LANES) {
>+      CurrentLane = 0;
>+      LaneVGPR = createLaneVGPR(MRI);
>+    }
>+  }
>+  return CurrentLane;
>+}
>+
>+void SIMachineFunctionInfo::RegSpillTracker::addSpilledReg(unsigned FrameIndex,
>+                                                           unsigned Reg,
>+                                                           int Lane) {
>+  SpilledRegisters[FrameIndex] = SpilledReg(Reg, Lane);
>+}
>+
>+const SIMachineFunctionInfo::SpilledReg&
>+SIMachineFunctionInfo::RegSpillTracker::getSpilledReg(unsigned FrameIndex) {
>+  return SpilledRegisters[FrameIndex];
>+}
>diff --git a/lib/Target/R600/SIMachineFunctionInfo.h b/lib/Target/R600/SIMachineFunctionInfo.h
>index 2f1961c..8dc82a0 100644
>--- a/lib/Target/R600/SIMachineFunctionInfo.h
>+++ b/lib/Target/R600/SIMachineFunctionInfo.h
>@@ -16,16 +16,44 @@
> #define SIMACHINEFUNCTIONINFO_H_
> 
> #include "AMDGPUMachineFunction.h"
>+#include <map>
> 
> namespace llvm {
> 
>+class MachineRegisterInfo;
>+
> /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
> /// tells the hardware which interpolation parameters to load.
> class SIMachineFunctionInfo : public AMDGPUMachineFunction {
>   virtual void anchor();
> public:
>+
>+  struct SpilledReg {
>+    unsigned VGPR;
>+    int Lane;
>+    SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
>+    SpilledReg() : VGPR(0), Lane(-1) { }
>+    bool hasLane() { return Lane != -1;}
>+  };
>+
>+  struct RegSpillTracker {
>+  private:
>+    unsigned CurrentLane;
>+    std::map<unsigned, SpilledReg> SpilledRegisters;
>+  public:
>+    unsigned LaneVGPR;
>+    RegSpillTracker() : CurrentLane(0), SpilledRegisters(), LaneVGPR(0) { }
>+    unsigned getNextLane(MachineRegisterInfo &MRI);
>+    void addSpilledReg(unsigned FrameIndex, unsigned Reg, int Lane = -1);
>+    const SpilledReg& getSpilledReg(unsigned FrameIndex);
>+    bool programSpillsRegisters() { return !SpilledRegisters.empty(); }
>+  };
>+
>+  // SIMachineFunctionInfo definition
>+
>   SIMachineFunctionInfo(const MachineFunction &MF);
>   unsigned PSInputAddr;
>+  struct RegSpillTracker SpillTracker;
> };
> 
> } // End namespace llvm
>diff --git a/lib/Target/R600/SIRegisterInfo.cpp b/lib/Target/R600/SIRegisterInfo.cpp
>index ed0bbaf..41784ed 100644
>--- a/lib/Target/R600/SIRegisterInfo.cpp
>+++ b/lib/Target/R600/SIRegisterInfo.cpp
>@@ -16,6 +16,7 @@
> #include "SIRegisterInfo.h"
> #include "AMDGPUTargetMachine.h"
> #include "SIInstrInfo.h"
>+#include "llvm/CodeGen/MachineRegisterInfo.h"
> 
> using namespace llvm;
> 
>@@ -129,3 +130,22 @@ const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
>     return &AMDGPU::VGPR_32RegClass;
>   }
> }
>+
>+bool SIRegisterInfo::allUsesCanBeCopiedToVGPR(const MachineRegisterInfo &MRI,
>+                                         unsigned Reg) const {
>+  if (MRI.use_empty(Reg)) {
>+    return false;
>+  }
>+  const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(TM.getInstrInfo());
>+  for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg),
>+                                         E = MachineRegisterInfo::use_end();
>+                                         I != E; ++I) {
>+    MachineInstr &MI = *I;
>+    if (!TII->canReadVGPR(MI, I.getOperandNo())) {
>+      MI.dump();
>+      return false;
>+    }
>+  }
>+  return true;
>+}
>+
>diff --git a/lib/Target/R600/SIRegisterInfo.h b/lib/Target/R600/SIRegisterInfo.h
>index 8148f7f..369c7a0 100644
>--- a/lib/Target/R600/SIRegisterInfo.h
>+++ b/lib/Target/R600/SIRegisterInfo.h
>@@ -63,6 +63,7 @@ struct SIRegisterInfo : public AMDGPURegisterInfo {
>   /// be returned.
>   const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
>                                             unsigned SubIdx) const;
>+  bool allUsesCanBeCopiedToVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
> };
> 
> } // End namespace llvm
>-- 
>1.8.1.5
>

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